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mv643xx_eth: check for valid hw address (resubmit)
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
1da177e4 57#include <asm/system.h>
ccffad25 58#include <linux/list.h>
fbd6a754 59
e5371493 60static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 61static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 62
fbd6a754 63
fbd6a754
LB		 64/*
65 * Registers shared between all ports.
66 */
3cb4667c
LB		 67#define PHY_ADDR 0x0000
68#define SMI_REG 0x0004
45c5d3bc
LB		 69#define SMI_BUSY 0x10000000
70#define SMI_READ_VALID 0x08000000
71#define SMI_OPCODE_READ 0x04000000
72#define SMI_OPCODE_WRITE 0x00000000
73#define ERR_INT_CAUSE 0x0080
74#define ERR_INT_SMI_DONE 0x00000010
75#define ERR_INT_MASK 0x0084
3cb4667c
LB		 76#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79#define WINDOW_BAR_ENABLE 0x0290
80#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 81
82/*
37a6084f
LB		 83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 85 */
37a6084f 86#define PORT_CONFIG 0x0000
d9a073ea 87#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 88#define PORT_CONFIG_EXT 0x0004
89#define MAC_ADDR_LOW 0x0014
90#define MAC_ADDR_HIGH 0x0018
91#define SDMA_CONFIG 0x001c
becfad97
LB		 92#define TX_BURST_SIZE_16_64BIT 0x01000000
93#define TX_BURST_SIZE_4_64BIT 0x00800000
94#define BLM_TX_NO_SWAP 0x00000020
95#define BLM_RX_NO_SWAP 0x00000010
96#define RX_BURST_SIZE_16_64BIT 0x00000008
97#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 98#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 99#define SET_MII_SPEED_TO_100 0x01000000
100#define SET_GMII_SPEED_TO_1000 0x00800000
101#define SET_FULL_DUPLEX_MODE 0x00200000
102#define MAX_RX_PACKET_9700BYTE 0x000a0000
103#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104#define DO_NOT_FORCE_LINK_FAIL 0x00000400
105#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108#define FORCE_LINK_PASS 0x00000002
109#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 110#define PORT_STATUS 0x0044
a2a41689 111#define TX_FIFO_EMPTY 0x00000400
ae9ae064 112#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 113#define PORT_SPEED_MASK 0x00000030
114#define PORT_SPEED_1000 0x00000010
115#define PORT_SPEED_100 0x00000020
116#define PORT_SPEED_10 0x00000000
117#define FLOW_CONTROL_ENABLED 0x00000008
118#define FULL_DUPLEX 0x00000004
81600eea 119#define LINK_UP 0x00000002
37a6084f
LB		 120#define TXQ_COMMAND 0x0048
121#define TXQ_FIX_PRIO_CONF 0x004c
122#define TX_BW_RATE 0x0050
123#define TX_BW_MTU 0x0058
124#define TX_BW_BURST 0x005c
125#define INT_CAUSE 0x0060
226bb6b7 126#define INT_TX_END 0x07f80000
e0ca8410 127#define INT_TX_END_0 0x00080000
befefe21 128#define INT_RX 0x000003fc
e0ca8410 129#define INT_RX_0 0x00000004
073a345c 130#define INT_EXT 0x00000002
37a6084f 131#define INT_CAUSE_EXT 0x0064
befefe21
LB		 132#define INT_EXT_LINK_PHY 0x00110000
133#define INT_EXT_TX 0x000000ff
37a6084f
LB		 134#define INT_MASK 0x0068
135#define INT_MASK_EXT 0x006c
136#define TX_FIFO_URGENT_THRESHOLD 0x0074
137#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
138#define TX_BW_RATE_MOVED 0x00e0
139#define TX_BW_MTU_MOVED 0x00e8
140#define TX_BW_BURST_MOVED 0x00ec
141#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
142#define RXQ_COMMAND 0x0280
143#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
144#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
145#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
146#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
147
148/*
149 * Misc per-port registers.
150 */
3cb4667c
LB		 151#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
152#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
153#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
154#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 155
2679a550
LB		 156
157/*
becfad97 158 * SDMA configuration register default value.
2679a550 159 */
fbd6a754
LB		 160#if defined(__BIG_ENDIAN)
161#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 162 (RX_BURST_SIZE_4_64BIT | \
163 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 164#elif defined(__LITTLE_ENDIAN)
165#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 166 (RX_BURST_SIZE_4_64BIT | \
167 BLM_RX_NO_SWAP | \
168 BLM_TX_NO_SWAP | \
169 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 170#else
171#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
172#endif
173
2beff77b
LB		 174
175/*
becfad97 176 * Misc definitions.
2beff77b 177 */
becfad97
LB		 178#define DEFAULT_RX_QUEUE_SIZE 128
179#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 180#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 181
fbd6a754 182
7ca72a3b
LB		 183/*
184 * RX/TX descriptors.
fbd6a754
LB		 185 */
186#if defined(__BIG_ENDIAN)
cc9754b3 187struct rx_desc {
fbd6a754
LB		 188 u16 byte_cnt; /* Descriptor buffer byte count */
189 u16 buf_size; /* Buffer size */
190 u32 cmd_sts; /* Descriptor command status */
191 u32 next_desc_ptr; /* Next descriptor pointer */
192 u32 buf_ptr; /* Descriptor buffer pointer */
193};
194
cc9754b3 195struct tx_desc {
fbd6a754
LB		 196 u16 byte_cnt; /* buffer byte count */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u32 cmd_sts; /* Command/status field */
199 u32 next_desc_ptr; /* Pointer to next descriptor */
200 u32 buf_ptr; /* pointer to buffer for this descriptor*/
201};
202#elif defined(__LITTLE_ENDIAN)
cc9754b3 203struct rx_desc {
fbd6a754
LB		 204 u32 cmd_sts; /* Descriptor command status */
205 u16 buf_size; /* Buffer size */
206 u16 byte_cnt; /* Descriptor buffer byte count */
207 u32 buf_ptr; /* Descriptor buffer pointer */
208 u32 next_desc_ptr; /* Next descriptor pointer */
209};
210
cc9754b3 211struct tx_desc {
fbd6a754
LB		 212 u32 cmd_sts; /* Command/status field */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u16 byte_cnt; /* buffer byte count */
215 u32 buf_ptr; /* pointer to buffer for this descriptor*/
216 u32 next_desc_ptr; /* Pointer to next descriptor */
217};
218#else
219#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
220#endif
221
7ca72a3b 222/* RX & TX descriptor command */
cc9754b3 223#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 224
225/* RX & TX descriptor status */
cc9754b3 226#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 227
228/* RX descriptor status */
cc9754b3
LB		 229#define LAYER_4_CHECKSUM_OK 0x40000000
230#define RX_ENABLE_INTERRUPT 0x20000000
231#define RX_FIRST_DESC 0x08000000
232#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 233#define RX_IP_HDR_OK 0x02000000
234#define RX_PKT_IS_IPV4 0x01000000
235#define RX_PKT_IS_ETHERNETV2 0x00800000
236#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
237#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
238#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 239
240/* TX descriptor command */
cc9754b3
LB		 241#define TX_ENABLE_INTERRUPT 0x00800000
242#define GEN_CRC 0x00400000
243#define TX_FIRST_DESC 0x00200000
244#define TX_LAST_DESC 0x00100000
245#define ZERO_PADDING 0x00080000
246#define GEN_IP_V4_CHECKSUM 0x00040000
247#define GEN_TCP_UDP_CHECKSUM 0x00020000
248#define UDP_FRAME 0x00010000
e32b6617
LB		 249#define MAC_HDR_EXTRA_4_BYTES 0x00008000
250#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 251
cc9754b3 252#define TX_IHL_SHIFT 11
7ca72a3b
LB		 253
254
c9df406f 255/* global *******************************************************************/
e5371493 256struct mv643xx_eth_shared_private {
fc32b0e2
LB		 257 /*
258 * Ethernet controller base address.
259 */
cc9754b3 260 void __iomem *base;
c9df406f 261
fc0eb9f2
LB		 262 /*
263 * Points at the right SMI instance to use.
264 */
265 struct mv643xx_eth_shared_private *smi;
266
fc32b0e2 267 /*
ed94493f 268 * Provides access to local SMI interface.
fc32b0e2 269 */
298cf9be 270 struct mii_bus *smi_bus;
c9df406f 271
45c5d3bc
LB		 272 /*
273 * If we have access to the error interrupt pin (which is
274 * somewhat misnamed as it not only reflects internal errors
275 * but also reflects SMI completion), use that to wait for
276 * SMI access completion instead of polling the SMI busy bit.
277 */
278 int err_interrupt;
279 wait_queue_head_t smi_busy_wait;
280
fc32b0e2
LB		 281 /*
282 * Per-port MBUS window access register value.
283 */
c9df406f
LB		 284 u32 win_protect;
285
fc32b0e2
LB		 286 /*
287 * Hardware-specific parameters.
288 */
c9df406f 289 unsigned int t_clk;
773fc3ee 290 int extended_rx_coal_limit;
457b1d5a 291 int tx_bw_control;
c9df406f
LB		 292};
293
457b1d5a
LB		 294#define TX_BW_CONTROL_ABSENT 0
295#define TX_BW_CONTROL_OLD_LAYOUT 1
296#define TX_BW_CONTROL_NEW_LAYOUT 2
297
e7d2f4db
LB		 298static int mv643xx_eth_open(struct net_device *dev);
299static int mv643xx_eth_stop(struct net_device *dev);
300
c9df406f
LB		 301
302/* per-port *****************************************************************/
e5371493 303struct mib_counters {
fbd6a754
LB		 304 u64 good_octets_received;
305 u32 bad_octets_received;
306 u32 internal_mac_transmit_err;
307 u32 good_frames_received;
308 u32 bad_frames_received;
309 u32 broadcast_frames_received;
310 u32 multicast_frames_received;
311 u32 frames_64_octets;
312 u32 frames_65_to_127_octets;
313 u32 frames_128_to_255_octets;
314 u32 frames_256_to_511_octets;
315 u32 frames_512_to_1023_octets;
316 u32 frames_1024_to_max_octets;
317 u64 good_octets_sent;
318 u32 good_frames_sent;
319 u32 excessive_collision;
320 u32 multicast_frames_sent;
321 u32 broadcast_frames_sent;
322 u32 unrec_mac_control_received;
323 u32 fc_sent;
324 u32 good_fc_received;
325 u32 bad_fc_received;
326 u32 undersize_received;
327 u32 fragments_received;
328 u32 oversize_received;
329 u32 jabber_received;
330 u32 mac_receive_error;
331 u32 bad_crc_event;
332 u32 collision;
333 u32 late_collision;
334};
335
eaf5d590
LB		 336struct lro_counters {
337 u32 lro_aggregated;
338 u32 lro_flushed;
339 u32 lro_no_desc;
340};
341
8a578111 342struct rx_queue {
64da80a2
LB		 343 int index;
344
8a578111
LB		 345 int rx_ring_size;
346
347 int rx_desc_count;
348 int rx_curr_desc;
349 int rx_used_desc;
350
351 struct rx_desc *rx_desc_area;
352 dma_addr_t rx_desc_dma;
353 int rx_desc_area_size;
354 struct sk_buff **rx_skb;
eaf5d590 355
eaf5d590
LB		 356 struct net_lro_mgr lro_mgr;
357 struct net_lro_desc lro_arr[8];
8a578111
LB		 358};
359
13d64285 360struct tx_queue {
3d6b35bc
LB		 361 int index;
362
13d64285 363 int tx_ring_size;
fbd6a754 364
13d64285
LB		 365 int tx_desc_count;
366 int tx_curr_desc;
367 int tx_used_desc;
fbd6a754 368
5daffe94 369 struct tx_desc *tx_desc_area;
fbd6a754
LB		 370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
99ab08e0
LB		 372
373 struct sk_buff_head tx_skb;
8fd89211
LB		 374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
13d64285
LB		 378};
379
380struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
37a6084f 382 void __iomem *base;
fc32b0e2 383 int port_num;
13d64285 384
fc32b0e2 385 struct net_device *dev;
fbd6a754 386
ed94493f 387 struct phy_device *phy;
fbd6a754 388
4ff3495a
LB		 389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
fc32b0e2 391 struct mib_counters mib_counters;
4ff3495a 392
eaf5d590
LB		 393 struct lro_counters lro_counters;
394
fc32b0e2 395 struct work_struct tx_timeout_task;
8a578111 396
1fa38c58 397 struct napi_struct napi;
e0ca8410 398 u32 int_mask;
1319ebad 399 u8 oom;
1fa38c58
LB		 400 u8 work_link;
401 u8 work_tx;
402 u8 work_tx_end;
403 u8 work_rx;
404 u8 work_rx_refill;
1fa38c58 405
2bcb4b0f
LB		 406 int skb_size;
407 struct sk_buff_head rx_recycle;
408
8a578111
LB		 409 /*
410 * RX state.
411 */
e7d2f4db 412 int rx_ring_size;
8a578111
LB		 413 unsigned long rx_desc_sram_addr;
414 int rx_desc_sram_size;
f7981c1c 415 int rxq_count;
2257e05c 416 struct timer_list rx_oom;
64da80a2 417 struct rx_queue rxq[8];
13d64285
LB		 418
419 /*
420 * TX state.
421 */
e7d2f4db 422 int tx_ring_size;
13d64285
LB		 423 unsigned long tx_desc_sram_addr;
424 int tx_desc_sram_size;
f7981c1c 425 int txq_count;
3d6b35bc 426 struct tx_queue txq[8];
fbd6a754 427};
1da177e4 428
fbd6a754 429
c9df406f 430/* port register accessors **************************************************/
e5371493 431static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 432{
cc9754b3 433 return readl(mp->shared->base + offset);
c9df406f 434}
fbd6a754 435
37a6084f
LB		 436static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
437{
438 return readl(mp->base + offset);
439}
440
e5371493 441static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 442{
cc9754b3 443 writel(data, mp->shared->base + offset);
c9df406f 444}
fbd6a754 445
37a6084f
LB		 446static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
447{
448 writel(data, mp->base + offset);
449}
450
fbd6a754 451
c9df406f 452/* rxq/txq helper functions *************************************************/
8a578111 453static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 454{
64da80a2 455 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 456}
fbd6a754 457
13d64285
LB		 458static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
459{
3d6b35bc 460 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 461}
462
8a578111 463static void rxq_enable(struct rx_queue *rxq)
c9df406f 464{
8a578111 465 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 466 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 467}
1da177e4 468
8a578111
LB		 469static void rxq_disable(struct rx_queue *rxq)
470{
471 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 472 u8 mask = 1 << rxq->index;
1da177e4 473
37a6084f
LB		 474 wrlp(mp, RXQ_COMMAND, mask << 8);
475 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 476 udelay(10);
c9df406f
LB		 477}
478
6b368f68
LB		 479static void txq_reset_hw_ptr(struct tx_queue *txq)
480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 482 u32 addr;
483
484 addr = (u32)txq->tx_desc_dma;
485 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 486 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 487}
488
13d64285 489static void txq_enable(struct tx_queue *txq)
1da177e4 490{
13d64285 491 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 492 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 493}
494
13d64285 495static void txq_disable(struct tx_queue *txq)
1da177e4 496{
13d64285 497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 498 u8 mask = 1 << txq->index;
c9df406f 499
37a6084f
LB		 500 wrlp(mp, TXQ_COMMAND, mask << 8);
501 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 502 udelay(10);
503}
504
1fa38c58 505static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 506{
507 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 508 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 509
8fd89211
LB		 510 if (netif_tx_queue_stopped(nq)) {
511 __netif_tx_lock(nq, smp_processor_id());
512 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
513 netif_tx_wake_queue(nq);
514 __netif_tx_unlock(nq);
515 }
1da177e4
LT		 516}
517
c9df406f 518
1fa38c58 519/* rx napi ******************************************************************/
eaf5d590
LB		 520static int
521mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
522 u64 *hdr_flags, void *priv)
523{
524 unsigned long cmd_sts = (unsigned long)priv;
525
526 /*
527 * Make sure that this packet is Ethernet II, is not VLAN
528 * tagged, is IPv4, has a valid IP header, and is TCP.
529 */
530 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
532 RX_PKT_IS_VLAN_TAGGED)) !=
533 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
535 return -1;
536
537 skb_reset_network_header(skb);
538 skb_set_transport_header(skb, ip_hdrlen(skb));
539 *iphdr = ip_hdr(skb);
540 *tcph = tcp_hdr(skb);
541 *hdr_flags = LRO_IPV4 | LRO_TCP;
542
543 return 0;
544}
eaf5d590 545
8a578111 546static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 547{
8a578111
LB		 548 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
549 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 550 int lro_flush_needed;
8a578111 551 int rx;
1da177e4 552
eaf5d590 553 lro_flush_needed = 0;
8a578111 554 rx = 0;
9e1f3772 555 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 556 struct rx_desc *rx_desc;
96587661 557 unsigned int cmd_sts;
fc32b0e2 558 struct sk_buff *skb;
6b8f90c2 559 u16 byte_cnt;
ff561eef 560
8a578111 561 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 562
96587661 563 cmd_sts = rx_desc->cmd_sts;
2257e05c 564 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 565 break;
96587661 566 rmb();
1da177e4 567
8a578111
LB		 568 skb = rxq->rx_skb[rxq->rx_curr_desc];
569 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 570
9da78745
LB		 571 rxq->rx_curr_desc++;
572 if (rxq->rx_curr_desc == rxq->rx_ring_size)
573 rxq->rx_curr_desc = 0;
ff561eef 574
eb0519b5 575 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 576 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 577 rxq->rx_desc_count--;
578 rx++;
b1dd9ca1 579
1fa38c58
LB		 580 mp->work_rx_refill |= 1 << rxq->index;
581
6b8f90c2
LB		 582 byte_cnt = rx_desc->byte_cnt;
583
468d09f8
DF		 584 /*
585 * Update statistics.
fc32b0e2
LB		 586 *
587 * Note that the descriptor byte count includes 2 dummy
588 * bytes automatically inserted by the hardware at the
589 * start of the packet (which we don't count), and a 4
590 * byte CRC at the end of the packet (which we do count).
468d09f8 591 */
1da177e4 592 stats->rx_packets++;
6b8f90c2 593 stats->rx_bytes += byte_cnt - 2;
96587661 594
1da177e4 595 /*
fc32b0e2
LB		 596 * In case we received a packet without first / last bits
597 * on, or the error summary bit is set, the packet needs
598 * to be dropped.
1da177e4 599 */
f61e5547
LB		 600 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
601 != (RX_FIRST_DESC | RX_LAST_DESC))
602 goto err;
603
604 /*
605 * The -4 is for the CRC in the trailer of the
606 * received packet
607 */
608 skb_put(skb, byte_cnt - 2 - 4);
609
610 if (cmd_sts & LAYER_4_CHECKSUM_OK)
611 skb->ip_summed = CHECKSUM_UNNECESSARY;
612 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 613
eaf5d590
LB		 614 if (skb->dev->features & NETIF_F_LRO &&
615 skb->ip_summed == CHECKSUM_UNNECESSARY) {
616 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
617 lro_flush_needed = 1;
618 } else
eaf5d590 619 netif_receive_skb(skb);
f61e5547
LB		 620
621 continue;
622
623err:
624 stats->rx_dropped++;
625
626 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
627 (RX_FIRST_DESC | RX_LAST_DESC)) {
628 if (net_ratelimit())
629 dev_printk(KERN_ERR, &mp->dev->dev,
630 "received packet spanning "
631 "multiple descriptors\n");
1da177e4 632 }
f61e5547
LB		 633
634 if (cmd_sts & ERROR_SUMMARY)
635 stats->rx_errors++;
636
637 dev_kfree_skb(skb);
1da177e4 638 }
fc32b0e2 639
eaf5d590
LB		 640 if (lro_flush_needed)
641 lro_flush_all(&rxq->lro_mgr);
eaf5d590 642
1fa38c58
LB		 643 if (rx < budget)
644 mp->work_rx &= ~(1 << rxq->index);
645
8a578111 646 return rx;
1da177e4
LT		 647}
648
1fa38c58 649static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 650{
1fa38c58 651 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 652 int refilled;
8a578111 653
1fa38c58
LB		 654 refilled = 0;
655 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
656 struct sk_buff *skb;
1fa38c58 657 int rx;
53771522 658 struct rx_desc *rx_desc;
d0412d96 659
2bcb4b0f
LB		 660 skb = __skb_dequeue(&mp->rx_recycle);
661 if (skb == NULL)
7fd96ce4 662 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 663
1fa38c58 664 if (skb == NULL) {
1319ebad 665 mp->oom = 1;
1fa38c58
LB		 666 goto oom;
667 }
d0412d96 668
7fd96ce4
LB		 669 if (SKB_DMA_REALIGN)
670 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 671
1fa38c58
LB		 672 refilled++;
673 rxq->rx_desc_count++;
c9df406f 674
1fa38c58
LB		 675 rx = rxq->rx_used_desc++;
676 if (rxq->rx_used_desc == rxq->rx_ring_size)
677 rxq->rx_used_desc = 0;
2257e05c 678
53771522
LB		 679 rx_desc = rxq->rx_desc_area + rx;
680
eb0519b5
GP		 681 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
682 skb->data, mp->skb_size,
683 DMA_FROM_DEVICE);
53771522 684 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 685 rxq->rx_skb[rx] = skb;
686 wmb();
53771522 687 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 688 wmb();
2257e05c 689
1fa38c58
LB		 690 /*
691 * The hardware automatically prepends 2 bytes of
692 * dummy data to each received packet, so that the
693 * IP header ends up 16-byte aligned.
694 */
695 skb_reserve(skb, 2);
696 }
697
698 if (refilled < budget)
699 mp->work_rx_refill &= ~(1 << rxq->index);
700
701oom:
702 return refilled;
d0412d96
JC		 703}
704
c9df406f
LB		 705
706/* tx ***********************************************************************/
c9df406f 707static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 708{
13d64285 709 int frag;
1da177e4 710
c9df406f 711 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 712 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
713 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 714 return 1;
1da177e4 715 }
13d64285 716
c9df406f
LB		 717 return 0;
718}
7303fde8 719
13d64285 720static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 721{
eb0519b5 722 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 723 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 724 int frag;
1da177e4 725
13d64285
LB		 726 for (frag = 0; frag < nr_frags; frag++) {
727 skb_frag_t *this_frag;
728 int tx_index;
729 struct tx_desc *desc;
730
731 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 732 tx_index = txq->tx_curr_desc++;
733 if (txq->tx_curr_desc == txq->tx_ring_size)
734 txq->tx_curr_desc = 0;
13d64285
LB		 735 desc = &txq->tx_desc_area[tx_index];
736
737 /*
738 * The last fragment will generate an interrupt
739 * which will free the skb on TX completion.
740 */
741 if (frag == nr_frags - 1) {
742 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
743 ZERO_PADDING | TX_LAST_DESC |
744 TX_ENABLE_INTERRUPT;
13d64285
LB		 745 } else {
746 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 747 }
748
c9df406f
LB		 749 desc->l4i_chk = 0;
750 desc->byte_cnt = this_frag->size;
eb0519b5
GP		 751 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
752 this_frag->page,
753 this_frag->page_offset,
754 this_frag->size, DMA_TO_DEVICE);
c9df406f 755 }
1da177e4
LT		 756}
757
c9df406f
LB		 758static inline __be16 sum16_as_be(__sum16 sum)
759{
760 return (__force __be16)sum;
761}
1da177e4 762
4df89bd5 763static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 764{
8fa89bf5 765 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 766 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 767 int tx_index;
cc9754b3 768 struct tx_desc *desc;
c9df406f 769 u32 cmd_sts;
4df89bd5 770 u16 l4i_chk;
c9df406f 771 int length;
1da177e4 772
cc9754b3 773 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 774 l4i_chk = 0;
c9df406f
LB		 775
776 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 777 int tag_bytes;
e32b6617
LB		 778
779 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
780 skb->protocol != htons(ETH_P_8021Q));
c9df406f 781
4df89bd5
LB		 782 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
783 if (unlikely(tag_bytes & ~12)) {
784 if (skb_checksum_help(skb) == 0)
785 goto no_csum;
786 kfree_skb(skb);
787 return 1;
788 }
c9df406f 789
4df89bd5 790 if (tag_bytes & 4)
e32b6617 791 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 792 if (tag_bytes & 8)
e32b6617 793 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 794
795 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
796 GEN_IP_V4_CHECKSUM |
797 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 798
c9df406f
LB		 799 switch (ip_hdr(skb)->protocol) {
800 case IPPROTO_UDP:
cc9754b3 801 cmd_sts |= UDP_FRAME;
4df89bd5 802 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 803 break;
804 case IPPROTO_TCP:
4df89bd5 805 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 806 break;
807 default:
808 BUG();
809 }
810 } else {
4df89bd5 811no_csum:
c9df406f 812 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 813 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 814 }
815
66823b92
LB		 816 tx_index = txq->tx_curr_desc++;
817 if (txq->tx_curr_desc == txq->tx_ring_size)
818 txq->tx_curr_desc = 0;
4df89bd5
LB		 819 desc = &txq->tx_desc_area[tx_index];
820
821 if (nr_frags) {
822 txq_submit_frag_skb(txq, skb);
823 length = skb_headlen(skb);
824 } else {
825 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
826 length = skb->len;
827 }
828
829 desc->l4i_chk = l4i_chk;
830 desc->byte_cnt = length;
eb0519b5
GP		 831 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
832 length, DMA_TO_DEVICE);
4df89bd5 833
99ab08e0
LB		 834 __skb_queue_tail(&txq->tx_skb, skb);
835
c9df406f
LB		 836 /* ensure all other descriptors are written before first cmd_sts */
837 wmb();
838 desc->cmd_sts = cmd_sts;
839
1fa38c58
LB		 840 /* clear TX_END status */
841 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 842
c9df406f
LB		 843 /* ensure all descriptors are written before poking hardware */
844 wmb();
13d64285 845 txq_enable(txq);
c9df406f 846
13d64285 847 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 848
849 return 0;
1da177e4 850}
1da177e4 851
0ccfe64d 852static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 853{
e5371493 854 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 855 int queue;
13d64285 856 struct tx_queue *txq;
e5ef1de1 857 struct netdev_queue *nq;
afdb57a2 858
8fd89211
LB		 859 queue = skb_get_queue_mapping(skb);
860 txq = mp->txq + queue;
861 nq = netdev_get_tx_queue(dev, queue);
862
c9df406f 863 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 864 txq->tx_dropped++;
fc32b0e2
LB		 865 dev_printk(KERN_DEBUG, &dev->dev,
866 "failed to linearize skb with tiny "
867 "unaligned fragment\n");
c9df406f
LB		 868 return NETDEV_TX_BUSY;
869 }
870
17cd0a59 871 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 872 if (net_ratelimit())
873 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 874 kfree_skb(skb);
875 return NETDEV_TX_OK;
c9df406f
LB		 876 }
877
4df89bd5
LB		 878 if (!txq_submit_skb(txq, skb)) {
879 int entries_left;
880
881 txq->tx_bytes += skb->len;
882 txq->tx_packets++;
883 dev->trans_start = jiffies;
c9df406f 884
4df89bd5
LB		 885 entries_left = txq->tx_ring_size - txq->tx_desc_count;
886 if (entries_left < MAX_SKB_FRAGS + 1)
887 netif_tx_stop_queue(nq);
888 }
c9df406f 889
c9df406f 890 return NETDEV_TX_OK;
1da177e4
LT		 891}
892
c9df406f 893
1fa38c58
LB		 894/* tx napi ******************************************************************/
895static void txq_kick(struct tx_queue *txq)
896{
897 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 898 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 899 u32 hw_desc_ptr;
900 u32 expected_ptr;
901
8fd89211 902 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 903
37a6084f 904 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 905 goto out;
906
37a6084f 907 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 908 expected_ptr = (u32)txq->tx_desc_dma +
909 txq->tx_curr_desc * sizeof(struct tx_desc);
910
911 if (hw_desc_ptr != expected_ptr)
912 txq_enable(txq);
913
914out:
8fd89211 915 __netif_tx_unlock(nq);
1fa38c58
LB		 916
917 mp->work_tx_end &= ~(1 << txq->index);
918}
919
920static int txq_reclaim(struct tx_queue *txq, int budget, int force)
921{
922 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 923 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 924 int reclaimed;
925
8fd89211 926 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 927
928 reclaimed = 0;
929 while (reclaimed < budget && txq->tx_desc_count > 0) {
930 int tx_index;
931 struct tx_desc *desc;
932 u32 cmd_sts;
933 struct sk_buff *skb;
1fa38c58
LB		 934
935 tx_index = txq->tx_used_desc;
936 desc = &txq->tx_desc_area[tx_index];
937 cmd_sts = desc->cmd_sts;
938
939 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
940 if (!force)
941 break;
942 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
943 }
944
945 txq->tx_used_desc = tx_index + 1;
946 if (txq->tx_used_desc == txq->tx_ring_size)
947 txq->tx_used_desc = 0;
948
949 reclaimed++;
950 txq->tx_desc_count--;
951
99ab08e0
LB		 952 skb = NULL;
953 if (cmd_sts & TX_LAST_DESC)
954 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 955
956 if (cmd_sts & ERROR_SUMMARY) {
957 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
958 mp->dev->stats.tx_errors++;
959 }
960
a418950c 961 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 962 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 963 desc->byte_cnt, DMA_TO_DEVICE);
964 } else {
eb0519b5 965 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 966 desc->byte_cnt, DMA_TO_DEVICE);
967 }
1fa38c58 968
2bcb4b0f
LB		 969 if (skb != NULL) {
970 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 971 mp->rx_ring_size &&
7fd96ce4 972 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 973 __skb_queue_head(&mp->rx_recycle, skb);
974 else
975 dev_kfree_skb(skb);
976 }
1fa38c58
LB		 977 }
978
8fd89211
LB		 979 __netif_tx_unlock(nq);
980
1fa38c58
LB		 981 if (reclaimed < budget)
982 mp->work_tx &= ~(1 << txq->index);
983
1fa38c58
LB		 984 return reclaimed;
985}
986
987
89df5fdc
LB		 988/* tx rate control **********************************************************/
989/*
990 * Set total maximum TX rate (shared by all TX queues for this port)
991 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
992 */
993static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
994{
995 int token_rate;
996 int mtu;
997 int bucket_size;
998
999 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1000 if (token_rate > 1023)
1001 token_rate = 1023;
1002
1003 mtu = (mp->dev->mtu + 255) >> 8;
1004 if (mtu > 63)
1005 mtu = 63;
1006
1007 bucket_size = (burst + 255) >> 8;
1008 if (bucket_size > 65535)
1009 bucket_size = 65535;
1010
457b1d5a
LB		 1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1013 wrlp(mp, TX_BW_RATE, token_rate);
1014 wrlp(mp, TX_BW_MTU, mtu);
1015 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1016 break;
1017 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1018 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1019 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1020 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1021 break;
1e881592 1022 }
89df5fdc
LB		 1023}
1024
1025static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1026{
1027 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1028 int token_rate;
1029 int bucket_size;
1030
1031 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1032 if (token_rate > 1023)
1033 token_rate = 1023;
1034
1035 bucket_size = (burst + 255) >> 8;
1036 if (bucket_size > 65535)
1037 bucket_size = 65535;
1038
37a6084f
LB		 1039 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1040 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1041}
1042
1043static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1044{
1045 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1046 int off;
1047 u32 val;
1048
1049 /*
1050 * Turn on fixed priority mode.
1051 */
457b1d5a
LB		 1052 off = 0;
1053 switch (mp->shared->tx_bw_control) {
1054 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1055 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1056 break;
1057 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1058 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1059 break;
1060 }
89df5fdc 1061
457b1d5a 1062 if (off) {
37a6084f 1063 val = rdlp(mp, off);
457b1d5a 1064 val |= 1 << txq->index;
37a6084f 1065 wrlp(mp, off, val);
457b1d5a 1066 }
89df5fdc
LB		 1067}
1068
89df5fdc 1069
c9df406f 1070/* mii management interface *************************************************/
45c5d3bc
LB		 1071static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1072{
1073 struct mv643xx_eth_shared_private *msp = dev_id;
1074
1075 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1076 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1077 wake_up(&msp->smi_busy_wait);
1078 return IRQ_HANDLED;
1079 }
1080
1081 return IRQ_NONE;
1082}
c9df406f 1083
45c5d3bc 1084static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1085{
45c5d3bc
LB		 1086 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1087}
1da177e4 1088
45c5d3bc
LB		 1089static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1090{
1091 if (msp->err_interrupt == NO_IRQ) {
1092 int i;
c9df406f 1093
45c5d3bc
LB		 1094 for (i = 0; !smi_is_done(msp); i++) {
1095 if (i == 10)
1096 return -ETIMEDOUT;
1097 msleep(10);
c9df406f 1098 }
45c5d3bc
LB		 1099
1100 return 0;
1101 }
1102
ee04448d
LB		 1103 if (!smi_is_done(msp)) {
1104 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1105 msecs_to_jiffies(100));
1106 if (!smi_is_done(msp))
1107 return -ETIMEDOUT;
1108 }
45c5d3bc
LB		 1109
1110 return 0;
1111}
1112
ed94493f 1113static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1114{
ed94493f 1115 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1116 void __iomem *smi_reg = msp->base + SMI_REG;
1117 int ret;
1118
45c5d3bc 1119 if (smi_wait_ready(msp)) {
10a9948d 1120 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1121 return -ETIMEDOUT;
1da177e4
LT		 1122 }
1123
fc32b0e2 1124 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1125
45c5d3bc 1126 if (smi_wait_ready(msp)) {
10a9948d 1127 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1128 return -ETIMEDOUT;
45c5d3bc
LB		 1129 }
1130
1131 ret = readl(smi_reg);
1132 if (!(ret & SMI_READ_VALID)) {
10a9948d 1133 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1134 return -ENODEV;
c9df406f
LB		 1135 }
1136
ed94493f 1137 return ret & 0xffff;
1da177e4
LT		 1138}
1139
ed94493f 1140static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1141{
ed94493f 1142 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1143 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1144
45c5d3bc 1145 if (smi_wait_ready(msp)) {
10a9948d 1146 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1147 return -ETIMEDOUT;
1da177e4
LT		 1148 }
1149
fc32b0e2 1150 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1151 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1152
ed94493f 1153 if (smi_wait_ready(msp)) {
10a9948d 1154 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1155 return -ETIMEDOUT;
1156 }
45c5d3bc
LB		 1157
1158 return 0;
c9df406f 1159}
1da177e4 1160
c9df406f 1161
8fd89211
LB		 1162/* statistics ***************************************************************/
1163static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1164{
1165 struct mv643xx_eth_private *mp = netdev_priv(dev);
1166 struct net_device_stats *stats = &dev->stats;
1167 unsigned long tx_packets = 0;
1168 unsigned long tx_bytes = 0;
1169 unsigned long tx_dropped = 0;
1170 int i;
1171
1172 for (i = 0; i < mp->txq_count; i++) {
1173 struct tx_queue *txq = mp->txq + i;
1174
1175 tx_packets += txq->tx_packets;
1176 tx_bytes += txq->tx_bytes;
1177 tx_dropped += txq->tx_dropped;
1178 }
1179
1180 stats->tx_packets = tx_packets;
1181 stats->tx_bytes = tx_bytes;
1182 stats->tx_dropped = tx_dropped;
1183
1184 return stats;
1185}
1186
eaf5d590
LB		 1187static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1188{
1189 u32 lro_aggregated = 0;
1190 u32 lro_flushed = 0;
1191 u32 lro_no_desc = 0;
1192 int i;
1193
eaf5d590
LB		 1194 for (i = 0; i < mp->rxq_count; i++) {
1195 struct rx_queue *rxq = mp->rxq + i;
1196
1197 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1198 lro_flushed += rxq->lro_mgr.stats.flushed;
1199 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1200 }
eaf5d590
LB		 1201
1202 mp->lro_counters.lro_aggregated = lro_aggregated;
1203 mp->lro_counters.lro_flushed = lro_flushed;
1204 mp->lro_counters.lro_no_desc = lro_no_desc;
1205}
1206
fc32b0e2 1207static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1208{
fc32b0e2 1209 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1210}
1211
fc32b0e2 1212static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1213{
fc32b0e2
LB		 1214 int i;
1215
1216 for (i = 0; i < 0x80; i += 4)
1217 mib_read(mp, i);
c9df406f 1218}
d0412d96 1219
fc32b0e2 1220static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1221{
e5371493 1222 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1223
57e8f26a 1224 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1225 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1226 p->bad_octets_received += mib_read(mp, 0x08);
1227 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1228 p->good_frames_received += mib_read(mp, 0x10);
1229 p->bad_frames_received += mib_read(mp, 0x14);
1230 p->broadcast_frames_received += mib_read(mp, 0x18);
1231 p->multicast_frames_received += mib_read(mp, 0x1c);
1232 p->frames_64_octets += mib_read(mp, 0x20);
1233 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1234 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1235 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1236 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1237 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1238 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1239 p->good_frames_sent += mib_read(mp, 0x40);
1240 p->excessive_collision += mib_read(mp, 0x44);
1241 p->multicast_frames_sent += mib_read(mp, 0x48);
1242 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1243 p->unrec_mac_control_received += mib_read(mp, 0x50);
1244 p->fc_sent += mib_read(mp, 0x54);
1245 p->good_fc_received += mib_read(mp, 0x58);
1246 p->bad_fc_received += mib_read(mp, 0x5c);
1247 p->undersize_received += mib_read(mp, 0x60);
1248 p->fragments_received += mib_read(mp, 0x64);
1249 p->oversize_received += mib_read(mp, 0x68);
1250 p->jabber_received += mib_read(mp, 0x6c);
1251 p->mac_receive_error += mib_read(mp, 0x70);
1252 p->bad_crc_event += mib_read(mp, 0x74);
1253 p->collision += mib_read(mp, 0x78);
1254 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1255 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1256
1257 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1258}
1259
1260static void mib_counters_timer_wrapper(unsigned long _mp)
1261{
1262 struct mv643xx_eth_private *mp = (void *)_mp;
1263
1264 mib_counters_update(mp);
d0412d96
JC		 1265}
1266
c9df406f 1267
3e508034
LB		 1268/* interrupt coalescing *****************************************************/
1269/*
1270 * Hardware coalescing parameters are set in units of 64 t_clk
1271 * cycles. I.e.:
1272 *
1273 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1274 *
1275 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1276 *
1277 * In the ->set*() methods, we round the computed register value
1278 * to the nearest integer.
1279 */
1280static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1281{
1282 u32 val = rdlp(mp, SDMA_CONFIG);
1283 u64 temp;
1284
1285 if (mp->shared->extended_rx_coal_limit)
1286 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1287 else
1288 temp = (val & 0x003fff00) >> 8;
1289
1290 temp *= 64000000;
1291 do_div(temp, mp->shared->t_clk);
1292
1293 return (unsigned int)temp;
1294}
1295
1296static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1297{
1298 u64 temp;
1299 u32 val;
1300
1301 temp = (u64)usec * mp->shared->t_clk;
1302 temp += 31999999;
1303 do_div(temp, 64000000);
1304
1305 val = rdlp(mp, SDMA_CONFIG);
1306 if (mp->shared->extended_rx_coal_limit) {
1307 if (temp > 0xffff)
1308 temp = 0xffff;
1309 val &= ~0x023fff80;
1310 val |= (temp & 0x8000) << 10;
1311 val |= (temp & 0x7fff) << 7;
1312 } else {
1313 if (temp > 0x3fff)
1314 temp = 0x3fff;
1315 val &= ~0x003fff00;
1316 val |= (temp & 0x3fff) << 8;
1317 }
1318 wrlp(mp, SDMA_CONFIG, val);
1319}
1320
1321static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1322{
1323 u64 temp;
1324
1325 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1326 temp *= 64000000;
1327 do_div(temp, mp->shared->t_clk);
1328
1329 return (unsigned int)temp;
1330}
1331
1332static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1333{
1334 u64 temp;
1335
1336 temp = (u64)usec * mp->shared->t_clk;
1337 temp += 31999999;
1338 do_div(temp, 64000000);
1339
1340 if (temp > 0x3fff)
1341 temp = 0x3fff;
1342
1343 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1344}
1345
1346
c9df406f 1347/* ethtool ******************************************************************/
e5371493 1348struct mv643xx_eth_stats {
c9df406f
LB		 1349 char stat_string[ETH_GSTRING_LEN];
1350 int sizeof_stat;
16820054
LB		 1351 int netdev_off;
1352 int mp_off;
c9df406f
LB		 1353};
1354
16820054
LB		 1355#define SSTAT(m) \
1356 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1357 offsetof(struct net_device, stats.m), -1 }
1358
1359#define MIBSTAT(m) \
1360 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1361 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1362
eaf5d590
LB		 1363#define LROSTAT(m) \
1364 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1365 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1366
16820054
LB		 1367static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1368 SSTAT(rx_packets),
1369 SSTAT(tx_packets),
1370 SSTAT(rx_bytes),
1371 SSTAT(tx_bytes),
1372 SSTAT(rx_errors),
1373 SSTAT(tx_errors),
1374 SSTAT(rx_dropped),
1375 SSTAT(tx_dropped),
1376 MIBSTAT(good_octets_received),
1377 MIBSTAT(bad_octets_received),
1378 MIBSTAT(internal_mac_transmit_err),
1379 MIBSTAT(good_frames_received),
1380 MIBSTAT(bad_frames_received),
1381 MIBSTAT(broadcast_frames_received),
1382 MIBSTAT(multicast_frames_received),
1383 MIBSTAT(frames_64_octets),
1384 MIBSTAT(frames_65_to_127_octets),
1385 MIBSTAT(frames_128_to_255_octets),
1386 MIBSTAT(frames_256_to_511_octets),
1387 MIBSTAT(frames_512_to_1023_octets),
1388 MIBSTAT(frames_1024_to_max_octets),
1389 MIBSTAT(good_octets_sent),
1390 MIBSTAT(good_frames_sent),
1391 MIBSTAT(excessive_collision),
1392 MIBSTAT(multicast_frames_sent),
1393 MIBSTAT(broadcast_frames_sent),
1394 MIBSTAT(unrec_mac_control_received),
1395 MIBSTAT(fc_sent),
1396 MIBSTAT(good_fc_received),
1397 MIBSTAT(bad_fc_received),
1398 MIBSTAT(undersize_received),
1399 MIBSTAT(fragments_received),
1400 MIBSTAT(oversize_received),
1401 MIBSTAT(jabber_received),
1402 MIBSTAT(mac_receive_error),
1403 MIBSTAT(bad_crc_event),
1404 MIBSTAT(collision),
1405 MIBSTAT(late_collision),
eaf5d590
LB		 1406 LROSTAT(lro_aggregated),
1407 LROSTAT(lro_flushed),
1408 LROSTAT(lro_no_desc),
c9df406f
LB		 1409};
1410
10a9948d 1411static int
6bdf576e
LB		 1412mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1413 struct ethtool_cmd *cmd)
d0412d96 1414{
d0412d96
JC		 1415 int err;
1416
ed94493f
LB		 1417 err = phy_read_status(mp->phy);
1418 if (err == 0)
1419 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1420
fc32b0e2
LB		 1421 /*
1422 * The MAC does not support 1000baseT_Half.
1423 */
d0412d96
JC		 1424 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1425 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1426
1427 return err;
1428}
1429
10a9948d 1430static int
6bdf576e 1431mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1432 struct ethtool_cmd *cmd)
bedfe324 1433{
81600eea
LB		 1434 u32 port_status;
1435
37a6084f 1436 port_status = rdlp(mp, PORT_STATUS);
81600eea 1437
bedfe324
LB		 1438 cmd->supported = SUPPORTED_MII;
1439 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1440 switch (port_status & PORT_SPEED_MASK) {
1441 case PORT_SPEED_10:
1442 cmd->speed = SPEED_10;
1443 break;
1444 case PORT_SPEED_100:
1445 cmd->speed = SPEED_100;
1446 break;
1447 case PORT_SPEED_1000:
1448 cmd->speed = SPEED_1000;
1449 break;
1450 default:
1451 cmd->speed = -1;
1452 break;
1453 }
1454 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1455 cmd->port = PORT_MII;
1456 cmd->phy_address = 0;
1457 cmd->transceiver = XCVR_INTERNAL;
1458 cmd->autoneg = AUTONEG_DISABLE;
1459 cmd->maxtxpkt = 1;
1460 cmd->maxrxpkt = 1;
1461
1462 return 0;
1463}
1464
6bdf576e
LB		 1465static int
1466mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1467{
1468 struct mv643xx_eth_private *mp = netdev_priv(dev);
1469
1470 if (mp->phy != NULL)
1471 return mv643xx_eth_get_settings_phy(mp, cmd);
1472 else
1473 return mv643xx_eth_get_settings_phyless(mp, cmd);
1474}
1475
10a9948d
LB		 1476static int
1477mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1478{
e5371493 1479 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1480
6bdf576e
LB		 1481 if (mp->phy == NULL)
1482 return -EINVAL;
1483
fc32b0e2
LB		 1484 /*
1485 * The MAC does not support 1000baseT_Half.
1486 */
1487 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1488
ed94493f 1489 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1490}
1da177e4 1491
fc32b0e2
LB		 1492static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1493 struct ethtool_drvinfo *drvinfo)
c9df406f 1494{
e5371493
LB		 1495 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1496 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1497 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1498 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1499 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1500}
1da177e4 1501
fc32b0e2 1502static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1503{
e5371493 1504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1505
6bdf576e
LB		 1506 if (mp->phy == NULL)
1507 return -EINVAL;
1da177e4 1508
6bdf576e 1509 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1510}
1511
c9df406f
LB		 1512static u32 mv643xx_eth_get_link(struct net_device *dev)
1513{
ed94493f 1514 return !!netif_carrier_ok(dev);
bedfe324
LB		 1515}
1516
3e508034
LB		 1517static int
1518mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1519{
1520 struct mv643xx_eth_private *mp = netdev_priv(dev);
1521
1522 ec->rx_coalesce_usecs = get_rx_coal(mp);
1523 ec->tx_coalesce_usecs = get_tx_coal(mp);
1524
1525 return 0;
1526}
1527
1528static int
1529mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1530{
1531 struct mv643xx_eth_private *mp = netdev_priv(dev);
1532
1533 set_rx_coal(mp, ec->rx_coalesce_usecs);
1534 set_tx_coal(mp, ec->tx_coalesce_usecs);
1535
1536 return 0;
1537}
1538
e7d2f4db
LB		 1539static void
1540mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1541{
1542 struct mv643xx_eth_private *mp = netdev_priv(dev);
1543
1544 er->rx_max_pending = 4096;
1545 er->tx_max_pending = 4096;
1546 er->rx_mini_max_pending = 0;
1547 er->rx_jumbo_max_pending = 0;
1548
1549 er->rx_pending = mp->rx_ring_size;
1550 er->tx_pending = mp->tx_ring_size;
1551 er->rx_mini_pending = 0;
1552 er->rx_jumbo_pending = 0;
1553}
1554
1555static int
1556mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1557{
1558 struct mv643xx_eth_private *mp = netdev_priv(dev);
1559
1560 if (er->rx_mini_pending || er->rx_jumbo_pending)
1561 return -EINVAL;
1562
1563 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1564 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1565
1566 if (netif_running(dev)) {
1567 mv643xx_eth_stop(dev);
1568 if (mv643xx_eth_open(dev)) {
1569 dev_printk(KERN_ERR, &dev->dev,
1570 "fatal error on re-opening device after "
1571 "ring param change\n");
1572 return -ENOMEM;
1573 }
1574 }
1575
1576 return 0;
1577}
1578
d888b373
LB		 1579static u32
1580mv643xx_eth_get_rx_csum(struct net_device *dev)
1581{
1582 struct mv643xx_eth_private *mp = netdev_priv(dev);
1583
1584 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1585}
1586
1587static int
1588mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1589{
1590 struct mv643xx_eth_private *mp = netdev_priv(dev);
1591
1592 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1593
1594 return 0;
1595}
1596
fc32b0e2
LB		 1597static void mv643xx_eth_get_strings(struct net_device *dev,
1598 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1599{
1600 int i;
1da177e4 1601
fc32b0e2
LB		 1602 if (stringset == ETH_SS_STATS) {
1603 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1604 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1605 mv643xx_eth_stats[i].stat_string,
e5371493 1606 ETH_GSTRING_LEN);
c9df406f 1607 }
c9df406f
LB		 1608 }
1609}
1da177e4 1610
fc32b0e2
LB		 1611static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1612 struct ethtool_stats *stats,
1613 uint64_t *data)
c9df406f 1614{
b9873841 1615 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1616 int i;
1da177e4 1617
8fd89211 1618 mv643xx_eth_get_stats(dev);
fc32b0e2 1619 mib_counters_update(mp);
eaf5d590 1620 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1621
16820054
LB		 1622 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1623 const struct mv643xx_eth_stats *stat;
1624 void *p;
1625
1626 stat = mv643xx_eth_stats + i;
1627
1628 if (stat->netdev_off >= 0)
1629 p = ((void *)mp->dev) + stat->netdev_off;
1630 else
1631 p = ((void *)mp) + stat->mp_off;
1632
1633 data[i] = (stat->sizeof_stat == 8) ?
1634 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1635 }
c9df406f 1636}
1da177e4 1637
fc32b0e2 1638static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1639{
fc32b0e2 1640 if (sset == ETH_SS_STATS)
16820054 1641 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1642
1643 return -EOPNOTSUPP;
c9df406f 1644}
1da177e4 1645
e5371493 1646static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1647 .get_settings = mv643xx_eth_get_settings,
1648 .set_settings = mv643xx_eth_set_settings,
1649 .get_drvinfo = mv643xx_eth_get_drvinfo,
1650 .nway_reset = mv643xx_eth_nway_reset,
1651 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1652 .get_coalesce = mv643xx_eth_get_coalesce,
1653 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1654 .get_ringparam = mv643xx_eth_get_ringparam,
1655 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1656 .get_rx_csum = mv643xx_eth_get_rx_csum,
1657 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1658 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1659 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1660 .get_strings = mv643xx_eth_get_strings,
1661 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1662 .get_flags = ethtool_op_get_flags,
1663 .set_flags = ethtool_op_set_flags,
e5371493 1664 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1665};
1da177e4 1666
bea3348e 1667
c9df406f 1668/* address handling *********************************************************/
5daffe94 1669static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1670{
66e63ffb
LB		 1671 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1672 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1673
5daffe94
LB		 1674 addr[0] = (mac_h >> 24) & 0xff;
1675 addr[1] = (mac_h >> 16) & 0xff;
1676 addr[2] = (mac_h >> 8) & 0xff;
1677 addr[3] = mac_h & 0xff;
1678 addr[4] = (mac_l >> 8) & 0xff;
1679 addr[5] = mac_l & 0xff;
c9df406f 1680}
1da177e4 1681
66e63ffb 1682static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1683{
66e63ffb
LB		 1684 wrlp(mp, MAC_ADDR_HIGH,
1685 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1686 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1687}
d0412d96 1688
66e63ffb 1689static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1690{
ccffad25 1691 struct netdev_hw_addr *ha;
66e63ffb 1692 u32 nibbles;
1da177e4 1693
66e63ffb
LB		 1694 if (dev->flags & IFF_PROMISC)
1695 return 0;
1da177e4 1696
66e63ffb 1697 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
31278e71 1698 list_for_each_entry(ha, &dev->uc.list, list) {
ccffad25 1699 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1700 return 0;
ccffad25 1701 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1702 return 0;
ff561eef 1703
ccffad25 1704 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1705 }
1da177e4 1706
66e63ffb 1707 return nibbles;
1da177e4
LT		 1708}
1709
66e63ffb 1710static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1711{
e5371493 1712 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1713 u32 port_config;
1714 u32 nibbles;
1715 int i;
1da177e4 1716
cc9754b3 1717 uc_addr_set(mp, dev->dev_addr);
1da177e4 1718
6877f54e
PS		 1719 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1720
66e63ffb
LB		 1721 nibbles = uc_addr_filter_mask(dev);
1722 if (!nibbles) {
1723 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1724 nibbles = 0xffff;
66e63ffb
LB		 1725 }
1726
1727 for (i = 0; i < 16; i += 4) {
1728 int off = UNICAST_TABLE(mp->port_num) + i;
1729 u32 v;
1730
1731 v = 0;
1732 if (nibbles & 1)
1733 v |= 0x00000001;
1734 if (nibbles & 2)
1735 v |= 0x00000100;
1736 if (nibbles & 4)
1737 v |= 0x00010000;
1738 if (nibbles & 8)
1739 v |= 0x01000000;
1740 nibbles >>= 4;
1741
1742 wrl(mp, off, v);
1743 }
1744
66e63ffb 1745 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1746}
1747
69876569
LB		 1748static int addr_crc(unsigned char *addr)
1749{
1750 int crc = 0;
1751 int i;
1752
1753 for (i = 0; i < 6; i++) {
1754 int j;
1755
1756 crc = (crc ^ addr[i]) << 8;
1757 for (j = 7; j >= 0; j--) {
1758 if (crc & (0x100 << j))
1759 crc ^= 0x107 << j;
1760 }
1761 }
1762
1763 return crc;
1764}
1765
66e63ffb 1766static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1767{
fc32b0e2 1768 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1769 u32 *mc_spec;
1770 u32 *mc_other;
fc32b0e2
LB		 1771 struct dev_addr_list *addr;
1772 int i;
c8aaea25 1773
fc32b0e2 1774 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1775 int port_num;
1776 u32 accept;
c8aaea25 1777
66e63ffb
LB		 1778oom:
1779 port_num = mp->port_num;
1780 accept = 0x01010101;
fc32b0e2
LB		 1781 for (i = 0; i < 0x100; i += 4) {
1782 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1783 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1784 }
1785 return;
1786 }
c8aaea25 1787
82a5bd6a 1788 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1789 if (mc_spec == NULL)
1790 goto oom;
1791 mc_other = mc_spec + (0x100 >> 2);
1792
1793 memset(mc_spec, 0, 0x100);
1794 memset(mc_other, 0, 0x100);
1da177e4 1795
fc32b0e2
LB		 1796 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1797 u8 *a = addr->da_addr;
66e63ffb
LB		 1798 u32 *table;
1799 int entry;
1da177e4 1800
fc32b0e2 1801 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1802 table = mc_spec;
1803 entry = a[5];
fc32b0e2 1804 } else {
66e63ffb
LB		 1805 table = mc_other;
1806 entry = addr_crc(a);
fc32b0e2 1807 }
66e63ffb 1808
2b448334 1809 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1810 }
66e63ffb
LB		 1811
1812 for (i = 0; i < 0x100; i += 4) {
1813 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1814 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1815 }
1816
1817 kfree(mc_spec);
1818}
1819
1820static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1821{
1822 mv643xx_eth_program_unicast_filter(dev);
1823 mv643xx_eth_program_multicast_filter(dev);
1824}
1825
1826static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1827{
1828 struct sockaddr *sa = addr;
1829
a29ec08a
DK		 1830 if (!is_valid_ether_addr(sa->sa_data))
1831 return -EINVAL;
1832
66e63ffb
LB		 1833 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1834
1835 netif_addr_lock_bh(dev);
1836 mv643xx_eth_program_unicast_filter(dev);
1837 netif_addr_unlock_bh(dev);
1838
1839 return 0;
c9df406f 1840}
c8aaea25 1841
c8aaea25 1842
c9df406f 1843/* rx/tx queue initialisation ***********************************************/
64da80a2 1844static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1845{
64da80a2 1846 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1847 struct rx_desc *rx_desc;
1848 int size;
c9df406f
LB		 1849 int i;
1850
64da80a2
LB		 1851 rxq->index = index;
1852
e7d2f4db 1853 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1854
1855 rxq->rx_desc_count = 0;
1856 rxq->rx_curr_desc = 0;
1857 rxq->rx_used_desc = 0;
1858
1859 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1860
f7981c1c 1861 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1862 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1863 mp->rx_desc_sram_size);
1864 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1865 } else {
eb0519b5
GP		 1866 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1867 size, &rxq->rx_desc_dma,
1868 GFP_KERNEL);
f7ea3337
PJ		 1869 }
1870
8a578111
LB		 1871 if (rxq->rx_desc_area == NULL) {
1872 dev_printk(KERN_ERR, &mp->dev->dev,
1873 "can't allocate rx ring (%d bytes)\n", size);
1874 goto out;
1875 }
1876 memset(rxq->rx_desc_area, 0, size);
1da177e4 1877
8a578111
LB		 1878 rxq->rx_desc_area_size = size;
1879 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1880 GFP_KERNEL);
1881 if (rxq->rx_skb == NULL) {
1882 dev_printk(KERN_ERR, &mp->dev->dev,
1883 "can't allocate rx skb ring\n");
1884 goto out_free;
1885 }
1886
1887 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1888 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1889 int nexti;
1890
1891 nexti = i + 1;
1892 if (nexti == rxq->rx_ring_size)
1893 nexti = 0;
1894
8a578111
LB		 1895 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1896 nexti * sizeof(struct rx_desc);
1897 }
1898
eaf5d590
LB		 1899 rxq->lro_mgr.dev = mp->dev;
1900 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1901 rxq->lro_mgr.features = LRO_F_NAPI;
1902 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1903 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1904 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1905 rxq->lro_mgr.max_aggr = 32;
1906 rxq->lro_mgr.frag_align_pad = 0;
1907 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1908 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1909
1910 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1911
8a578111
LB		 1912 return 0;
1913
1914
1915out_free:
f7981c1c 1916 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1917 iounmap(rxq->rx_desc_area);
1918 else
eb0519b5 1919 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1920 rxq->rx_desc_area,
1921 rxq->rx_desc_dma);
1922
1923out:
1924 return -ENOMEM;
c9df406f 1925}
c8aaea25 1926
8a578111 1927static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1928{
8a578111
LB		 1929 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1930 int i;
1931
1932 rxq_disable(rxq);
c8aaea25 1933
8a578111
LB		 1934 for (i = 0; i < rxq->rx_ring_size; i++) {
1935 if (rxq->rx_skb[i]) {
1936 dev_kfree_skb(rxq->rx_skb[i]);
1937 rxq->rx_desc_count--;
1da177e4 1938 }
c8aaea25 1939 }
1da177e4 1940
8a578111
LB		 1941 if (rxq->rx_desc_count) {
1942 dev_printk(KERN_ERR, &mp->dev->dev,
1943 "error freeing rx ring -- %d skbs stuck\n",
1944 rxq->rx_desc_count);
1945 }
1946
f7981c1c 1947 if (rxq->index == 0 &&
64da80a2 1948 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1949 iounmap(rxq->rx_desc_area);
c9df406f 1950 else
eb0519b5 1951 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1952 rxq->rx_desc_area, rxq->rx_desc_dma);
1953
1954 kfree(rxq->rx_skb);
c9df406f 1955}
1da177e4 1956
3d6b35bc 1957static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1958{
3d6b35bc 1959 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1960 struct tx_desc *tx_desc;
1961 int size;
c9df406f 1962 int i;
1da177e4 1963
3d6b35bc
LB		 1964 txq->index = index;
1965
e7d2f4db 1966 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1967
1968 txq->tx_desc_count = 0;
1969 txq->tx_curr_desc = 0;
1970 txq->tx_used_desc = 0;
1971
1972 size = txq->tx_ring_size * sizeof(struct tx_desc);
1973
f7981c1c 1974 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1975 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1976 mp->tx_desc_sram_size);
1977 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1978 } else {
eb0519b5
GP		 1979 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1980 size, &txq->tx_desc_dma,
1981 GFP_KERNEL);
13d64285
LB		 1982 }
1983
1984 if (txq->tx_desc_area == NULL) {
1985 dev_printk(KERN_ERR, &mp->dev->dev,
1986 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1987 return -ENOMEM;
c9df406f 1988 }
13d64285
LB		 1989 memset(txq->tx_desc_area, 0, size);
1990
1991 txq->tx_desc_area_size = size;
13d64285
LB		 1992
1993 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1994 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1995 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1996 int nexti;
1997
1998 nexti = i + 1;
1999 if (nexti == txq->tx_ring_size)
2000 nexti = 0;
6b368f68
LB		 2001
2002 txd->cmd_sts = 0;
2003 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2004 nexti * sizeof(struct tx_desc);
2005 }
2006
99ab08e0 2007 skb_queue_head_init(&txq->tx_skb);
c9df406f 2008
99ab08e0 2009 return 0;
c8aaea25 2010}
1da177e4 2011
13d64285 2012static void txq_deinit(struct tx_queue *txq)
c9df406f 2013{
13d64285 2014 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2015
13d64285 2016 txq_disable(txq);
1fa38c58 2017 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2018
13d64285 2019 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2020
f7981c1c 2021 if (txq->index == 0 &&
3d6b35bc 2022 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2023 iounmap(txq->tx_desc_area);
c9df406f 2024 else
eb0519b5 2025 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2026 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2027}
1da177e4 2028
1da177e4 2029
c9df406f 2030/* netdev ops and related ***************************************************/
1fa38c58
LB		 2031static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2032{
2033 u32 int_cause;
2034 u32 int_cause_ext;
2035
e0ca8410 2036 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2037 if (int_cause == 0)
2038 return 0;
2039
2040 int_cause_ext = 0;
e0ca8410
SB		 2041 if (int_cause & INT_EXT) {
2042 int_cause &= ~INT_EXT;
37a6084f 2043 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2044 }
1fa38c58 2045
1fa38c58 2046 if (int_cause) {
37a6084f 2047 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2048 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2049 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2050 mp->work_rx |= (int_cause & INT_RX) >> 2;
2051 }
2052
2053 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2054 if (int_cause_ext) {
37a6084f 2055 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2056 if (int_cause_ext & INT_EXT_LINK_PHY)
2057 mp->work_link = 1;
2058 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2059 }
2060
2061 return 1;
2062}
2063
2064static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2065{
2066 struct net_device *dev = (struct net_device *)dev_id;
2067 struct mv643xx_eth_private *mp = netdev_priv(dev);
2068
2069 if (unlikely(!mv643xx_eth_collect_events(mp)))
2070 return IRQ_NONE;
2071
37a6084f 2072 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2073 napi_schedule(&mp->napi);
2074
2075 return IRQ_HANDLED;
2076}
2077
2f7eb47a
LB		 2078static void handle_link_event(struct mv643xx_eth_private *mp)
2079{
2080 struct net_device *dev = mp->dev;
2081 u32 port_status;
2082 int speed;
2083 int duplex;
2084 int fc;
2085
37a6084f 2086 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2087 if (!(port_status & LINK_UP)) {
2088 if (netif_carrier_ok(dev)) {
2089 int i;
2090
2091 printk(KERN_INFO "%s: link down\n", dev->name);
2092
2093 netif_carrier_off(dev);
2f7eb47a 2094
f7981c1c 2095 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2096 struct tx_queue *txq = mp->txq + i;
2097
1fa38c58 2098 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2099 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2100 }
2101 }
2102 return;
2103 }
2104
2105 switch (port_status & PORT_SPEED_MASK) {
2106 case PORT_SPEED_10:
2107 speed = 10;
2108 break;
2109 case PORT_SPEED_100:
2110 speed = 100;
2111 break;
2112 case PORT_SPEED_1000:
2113 speed = 1000;
2114 break;
2115 default:
2116 speed = -1;
2117 break;
2118 }
2119 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2120 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2121
2122 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2123 "flow control %sabled\n", dev->name,
2124 speed, duplex ? "full" : "half",
2125 fc ? "en" : "dis");
2126
4fdeca3f 2127 if (!netif_carrier_ok(dev))
2f7eb47a 2128 netif_carrier_on(dev);
2f7eb47a
LB		 2129}
2130
1fa38c58 2131static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2132{
1fa38c58
LB		 2133 struct mv643xx_eth_private *mp;
2134 int work_done;
ce4e2e45 2135
1fa38c58 2136 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2137
1319ebad
LB		 2138 if (unlikely(mp->oom)) {
2139 mp->oom = 0;
2140 del_timer(&mp->rx_oom);
2141 }
1da177e4 2142
1fa38c58
LB		 2143 work_done = 0;
2144 while (work_done < budget) {
2145 u8 queue_mask;
2146 int queue;
2147 int work_tbd;
2148
2149 if (mp->work_link) {
2150 mp->work_link = 0;
2151 handle_link_event(mp);
26ef1f17 2152 work_done++;
1fa38c58
LB		 2153 continue;
2154 }
1da177e4 2155
1319ebad
LB		 2156 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2157 if (likely(!mp->oom))
2158 queue_mask |= mp->work_rx_refill;
2159
1fa38c58
LB		 2160 if (!queue_mask) {
2161 if (mv643xx_eth_collect_events(mp))
2162 continue;
2163 break;
2164 }
1da177e4 2165
1fa38c58
LB		 2166 queue = fls(queue_mask) - 1;
2167 queue_mask = 1 << queue;
2168
2169 work_tbd = budget - work_done;
2170 if (work_tbd > 16)
2171 work_tbd = 16;
2172
2173 if (mp->work_tx_end & queue_mask) {
2174 txq_kick(mp->txq + queue);
2175 } else if (mp->work_tx & queue_mask) {
2176 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2177 txq_maybe_wake(mp->txq + queue);
2178 } else if (mp->work_rx & queue_mask) {
2179 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2180 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2181 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2182 } else {
2183 BUG();
2184 }
84dd619e 2185 }
fc32b0e2 2186
1fa38c58 2187 if (work_done < budget) {
1319ebad 2188 if (mp->oom)
1fa38c58
LB		 2189 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2190 napi_complete(napi);
e0ca8410 2191 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2192 }
3d6b35bc 2193
1fa38c58
LB		 2194 return work_done;
2195}
8fa89bf5 2196
1fa38c58
LB		 2197static inline void oom_timer_wrapper(unsigned long data)
2198{
2199 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2200
1fa38c58 2201 napi_schedule(&mp->napi);
1da177e4
LT		 2202}
2203
e5371493 2204static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2205{
45c5d3bc
LB		 2206 int data;
2207
ed94493f 2208 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2209 if (data < 0)
2210 return;
1da177e4 2211
7f106c1d 2212 data |= BMCR_RESET;
ed94493f 2213 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2214 return;
1da177e4 2215
c9df406f 2216 do {
ed94493f 2217 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2218 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2219}
2220
fc32b0e2 2221static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2222{
d0412d96 2223 u32 pscr;
8a578111 2224 int i;
1da177e4 2225
bedfe324
LB		 2226 /*
2227 * Perform PHY reset, if there is a PHY.
2228 */
ed94493f 2229 if (mp->phy != NULL) {
bedfe324
LB		 2230 struct ethtool_cmd cmd;
2231
2232 mv643xx_eth_get_settings(mp->dev, &cmd);
2233 phy_reset(mp);
2234 mv643xx_eth_set_settings(mp->dev, &cmd);
2235 }
1da177e4 2236
81600eea
LB		 2237 /*
2238 * Configure basic link parameters.
2239 */
37a6084f 2240 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2241
2242 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2243 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2244
2245 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2246 if (mp->phy == NULL)
81600eea 2247 pscr |= FORCE_LINK_PASS;
37a6084f 2248 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2249
13d64285
LB		 2250 /*
2251 * Configure TX path and queues.
2252 */
89df5fdc 2253 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2254 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2255 struct tx_queue *txq = mp->txq + i;
13d64285 2256
6b368f68 2257 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2258 txq_set_rate(txq, 1000000000, 16777216);
2259 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2260 }
2261
d9a073ea
LB		 2262 /*
2263 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2264 * frames to RX queue #0, and include the pseudo-header when
2265 * calculating receive checksums.
d9a073ea 2266 */
37a6084f 2267 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2268
376489a2
LB		 2269 /*
2270 * Treat BPDUs as normal multicasts, and disable partition mode.
2271 */
37a6084f 2272 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2273
5a893922
LB		 2274 /*
2275 * Add configured unicast addresses to address filter table.
2276 */
2277 mv643xx_eth_program_unicast_filter(mp->dev);
2278
8a578111 2279 /*
64da80a2 2280 * Enable the receive queues.
8a578111 2281 */
f7981c1c 2282 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2283 struct rx_queue *rxq = mp->rxq + i;
8a578111 2284 u32 addr;
1da177e4 2285
8a578111
LB		 2286 addr = (u32)rxq->rx_desc_dma;
2287 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2288 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2289
8a578111
LB		 2290 rxq_enable(rxq);
2291 }
1da177e4
LT		 2292}
2293
2bcb4b0f
LB		 2294static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2295{
2296 int skb_size;
2297
2298 /*
2299 * Reserve 2+14 bytes for an ethernet header (the hardware
2300 * automatically prepends 2 bytes of dummy data to each
2301 * received packet), 16 bytes for up to four VLAN tags, and
2302 * 4 bytes for the trailing FCS -- 36 bytes total.
2303 */
2304 skb_size = mp->dev->mtu + 36;
2305
2306 /*
2307 * Make sure that the skb size is a multiple of 8 bytes, as
2308 * the lower three bits of the receive descriptor's buffer
2309 * size field are ignored by the hardware.
2310 */
2311 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2312
2313 /*
2314 * If NET_SKB_PAD is smaller than a cache line,
2315 * netdev_alloc_skb() will cause skb->data to be misaligned
2316 * to a cache line boundary. If this is the case, include
2317 * some extra space to allow re-aligning the data area.
2318 */
2319 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2320}
2321
c9df406f 2322static int mv643xx_eth_open(struct net_device *dev)
16e03018 2323{
e5371493 2324 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2325 int err;
64da80a2 2326 int i;
16e03018 2327
37a6084f
LB		 2328 wrlp(mp, INT_CAUSE, 0);
2329 wrlp(mp, INT_CAUSE_EXT, 0);
2330 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2331
fc32b0e2 2332 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2333 IRQF_SHARED, dev->name, dev);
c9df406f 2334 if (err) {
fc32b0e2 2335 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2336 return -EAGAIN;
16e03018
DF		 2337 }
2338
2bcb4b0f
LB		 2339 mv643xx_eth_recalc_skb_size(mp);
2340
2257e05c
LB		 2341 napi_enable(&mp->napi);
2342
2bcb4b0f
LB		 2343 skb_queue_head_init(&mp->rx_recycle);
2344
e0ca8410
SB		 2345 mp->int_mask = INT_EXT;
2346
f7981c1c 2347 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2348 err = rxq_init(mp, i);
2349 if (err) {
2350 while (--i >= 0)
f7981c1c 2351 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2352 goto out;
2353 }
2354
1fa38c58 2355 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2356 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2357 }
2358
1319ebad 2359 if (mp->oom) {
2257e05c
LB		 2360 mp->rx_oom.expires = jiffies + (HZ / 10);
2361 add_timer(&mp->rx_oom);
64da80a2 2362 }
8a578111 2363
f7981c1c 2364 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2365 err = txq_init(mp, i);
2366 if (err) {
2367 while (--i >= 0)
f7981c1c 2368 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2369 goto out_free;
2370 }
e0ca8410 2371 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2372 }
16e03018 2373
fc32b0e2 2374 port_start(mp);
16e03018 2375
37a6084f 2376 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2377 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2378
c9df406f
LB		 2379 return 0;
2380
13d64285 2381
fc32b0e2 2382out_free:
f7981c1c
LB		 2383 for (i = 0; i < mp->rxq_count; i++)
2384 rxq_deinit(mp->rxq + i);
fc32b0e2 2385out:
c9df406f
LB		 2386 free_irq(dev->irq, dev);
2387
2388 return err;
16e03018
DF		 2389}
2390
e5371493 2391static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2392{
fc32b0e2 2393 unsigned int data;
64da80a2 2394 int i;
1da177e4 2395
f7981c1c
LB		 2396 for (i = 0; i < mp->rxq_count; i++)
2397 rxq_disable(mp->rxq + i);
2398 for (i = 0; i < mp->txq_count; i++)
2399 txq_disable(mp->txq + i);
ae9ae064
LB		 2400
2401 while (1) {
37a6084f 2402 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2403
2404 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2405 break;
13d64285 2406 udelay(10);
ae9ae064 2407 }
1da177e4 2408
c9df406f 2409 /* Reset the Enable bit in the Configuration Register */
37a6084f 2410 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2411 data &= ~(SERIAL_PORT_ENABLE |
2412 DO_NOT_FORCE_LINK_FAIL |
2413 FORCE_LINK_PASS);
37a6084f 2414 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2415}
2416
c9df406f 2417static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2418{
e5371493 2419 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2420 int i;
1da177e4 2421
fe65e704 2422 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2423 wrlp(mp, INT_MASK, 0x00000000);
2424 rdlp(mp, INT_MASK);
1da177e4 2425
c9df406f 2426 napi_disable(&mp->napi);
78fff83b 2427
2257e05c
LB		 2428 del_timer_sync(&mp->rx_oom);
2429
c9df406f 2430 netif_carrier_off(dev);
1da177e4 2431
fc32b0e2
LB		 2432 free_irq(dev->irq, dev);
2433
cc9754b3 2434 port_reset(mp);
8fd89211 2435 mv643xx_eth_get_stats(dev);
fc32b0e2 2436 mib_counters_update(mp);
57e8f26a 2437 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2438
2bcb4b0f
LB		 2439 skb_queue_purge(&mp->rx_recycle);
2440
f7981c1c
LB		 2441 for (i = 0; i < mp->rxq_count; i++)
2442 rxq_deinit(mp->rxq + i);
2443 for (i = 0; i < mp->txq_count; i++)
2444 txq_deinit(mp->txq + i);
1da177e4 2445
c9df406f 2446 return 0;
1da177e4
LT		 2447}
2448
fc32b0e2 2449static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2450{
e5371493 2451 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2452
ed94493f
LB		 2453 if (mp->phy != NULL)
2454 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2455
2456 return -EOPNOTSUPP;
1da177e4
LT		 2457}
2458
c9df406f 2459static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2460{
89df5fdc
LB		 2461 struct mv643xx_eth_private *mp = netdev_priv(dev);
2462
fc32b0e2 2463 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2464 return -EINVAL;
1da177e4 2465
c9df406f 2466 dev->mtu = new_mtu;
2bcb4b0f 2467 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2468 tx_set_rate(mp, 1000000000, 16777216);
2469
c9df406f
LB		 2470 if (!netif_running(dev))
2471 return 0;
1da177e4 2472
c9df406f
LB		 2473 /*
2474 * Stop and then re-open the interface. This will allocate RX
2475 * skbs of the new MTU.
2476 * There is a possible danger that the open will not succeed,
fc32b0e2 2477 * due to memory being full.
c9df406f
LB		 2478 */
2479 mv643xx_eth_stop(dev);
2480 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2481 dev_printk(KERN_ERR, &dev->dev,
2482 "fatal error on re-opening device after "
2483 "MTU change\n");
c9df406f
LB		 2484 }
2485
2486 return 0;
1da177e4
LT		 2487}
2488
fc32b0e2 2489static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2490{
fc32b0e2 2491 struct mv643xx_eth_private *mp;
1da177e4 2492
fc32b0e2
LB		 2493 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2494 if (netif_running(mp->dev)) {
e5ef1de1 2495 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2496 port_reset(mp);
2497 port_start(mp);
e5ef1de1 2498 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2499 }
c9df406f
LB		 2500}
2501
c9df406f 2502static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2503{
e5371493 2504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2505
fc32b0e2 2506 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2507
c9df406f 2508 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2509}
2510
c9df406f 2511#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2512static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2513{
fc32b0e2 2514 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2515
37a6084f
LB		 2516 wrlp(mp, INT_MASK, 0x00000000);
2517 rdlp(mp, INT_MASK);
c9df406f 2518
fc32b0e2 2519 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2520
e0ca8410 2521 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2522}
c9df406f 2523#endif
9f8dd319 2524
9f8dd319 2525
c9df406f 2526/* platform glue ************************************************************/
e5371493
LB		 2527static void
2528mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2529 struct mbus_dram_target_info *dram)
c9df406f 2530{
cc9754b3 2531 void __iomem *base = msp->base;
c9df406f
LB		 2532 u32 win_enable;
2533 u32 win_protect;
2534 int i;
9f8dd319 2535
c9df406f
LB		 2536 for (i = 0; i < 6; i++) {
2537 writel(0, base + WINDOW_BASE(i));
2538 writel(0, base + WINDOW_SIZE(i));
2539 if (i < 4)
2540 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2541 }
2542
c9df406f
LB		 2543 win_enable = 0x3f;
2544 win_protect = 0;
2545
2546 for (i = 0; i < dram->num_cs; i++) {
2547 struct mbus_dram_window *cs = dram->cs + i;
2548
2549 writel((cs->base & 0xffff0000) |
2550 (cs->mbus_attr << 8) |
2551 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2552 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2553
2554 win_enable &= ~(1 << i);
2555 win_protect |= 3 << (2 * i);
2556 }
2557
2558 writel(win_enable, base + WINDOW_BAR_ENABLE);
2559 msp->win_protect = win_protect;
9f8dd319
DF		 2560}
2561
773fc3ee
LB		 2562static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2563{
2564 /*
2565 * Check whether we have a 14-bit coal limit field in bits
2566 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2567 * SDMA config register.
2568 */
37a6084f
LB		 2569 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2570 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2571 msp->extended_rx_coal_limit = 1;
2572 else
2573 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2574
2575 /*
457b1d5a
LB		 2576 * Check whether the MAC supports TX rate control, and if
2577 * yes, whether its associated registers are in the old or
2578 * the new place.
1e881592 2579 */
37a6084f
LB		 2580 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2581 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2582 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2583 } else {
37a6084f
LB		 2584 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2585 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2586 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2587 else
2588 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2589 }
773fc3ee
LB		 2590}
2591
c9df406f 2592static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2593{
10a9948d 2594 static int mv643xx_eth_version_printed;
c9df406f 2595 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2596 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2597 struct resource *res;
2598 int ret;
9f8dd319 2599
e5371493 2600 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2601 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2602 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2603
c9df406f
LB		 2604 ret = -EINVAL;
2605 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2606 if (res == NULL)
2607 goto out;
9f8dd319 2608
c9df406f
LB		 2609 ret = -ENOMEM;
2610 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2611 if (msp == NULL)
2612 goto out;
2613 memset(msp, 0, sizeof(*msp));
2614
cc9754b3
LB		 2615 msp->base = ioremap(res->start, res->end - res->start + 1);
2616 if (msp->base == NULL)
c9df406f
LB		 2617 goto out_free;
2618
ed94493f
LB		 2619 /*
2620 * Set up and register SMI bus.
2621 */
2622 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2623 msp->smi_bus = mdiobus_alloc();
2624 if (msp->smi_bus == NULL)
ed94493f 2625 goto out_unmap;
298cf9be
LB		 2626
2627 msp->smi_bus->priv = msp;
2628 msp->smi_bus->name = "mv643xx_eth smi";
2629 msp->smi_bus->read = smi_bus_read;
2630 msp->smi_bus->write = smi_bus_write,
2631 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2632 msp->smi_bus->parent = &pdev->dev;
2633 msp->smi_bus->phy_mask = 0xffffffff;
2634 if (mdiobus_register(msp->smi_bus) < 0)
2635 goto out_free_mii_bus;
ed94493f
LB		 2636 msp->smi = msp;
2637 } else {
fc0eb9f2 2638 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2639 }
c9df406f 2640
45c5d3bc
LB		 2641 msp->err_interrupt = NO_IRQ;
2642 init_waitqueue_head(&msp->smi_busy_wait);
2643
2644 /*
2645 * Check whether the error interrupt is hooked up.
2646 */
2647 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2648 if (res != NULL) {
2649 int err;
2650
2651 err = request_irq(res->start, mv643xx_eth_err_irq,
2652 IRQF_SHARED, "mv643xx_eth", msp);
2653 if (!err) {
2654 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2655 msp->err_interrupt = res->start;
2656 }
2657 }
2658
c9df406f
LB		 2659 /*
2660 * (Re-)program MBUS remapping windows if we are asked to.
2661 */
2662 if (pd != NULL && pd->dram != NULL)
2663 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2664
fc32b0e2
LB		 2665 /*
2666 * Detect hardware parameters.
2667 */
2668 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2669 infer_hw_params(msp);
fc32b0e2
LB		 2670
2671 platform_set_drvdata(pdev, msp);
2672
c9df406f
LB		 2673 return 0;
2674
298cf9be
LB		 2675out_free_mii_bus:
2676 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2677out_unmap:
2678 iounmap(msp->base);
c9df406f
LB		 2679out_free:
2680 kfree(msp);
2681out:
2682 return ret;
2683}
2684
2685static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2686{
e5371493 2687 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2688 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2689
298cf9be 2690 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2691 mdiobus_unregister(msp->smi_bus);
bcb3336c 2692 mdiobus_free(msp->smi_bus);
298cf9be 2693 }
45c5d3bc
LB		 2694 if (msp->err_interrupt != NO_IRQ)
2695 free_irq(msp->err_interrupt, msp);
cc9754b3 2696 iounmap(msp->base);
c9df406f
LB		 2697 kfree(msp);
2698
2699 return 0;
9f8dd319
DF		 2700}
2701
c9df406f 2702static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2703 .probe = mv643xx_eth_shared_probe,
2704 .remove = mv643xx_eth_shared_remove,
c9df406f 2705 .driver = {
fc32b0e2 2706 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2707 .owner = THIS_MODULE,
2708 },
2709};
2710
e5371493 2711static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2712{
c9df406f 2713 int addr_shift = 5 * mp->port_num;
fc32b0e2 2714 u32 data;
1da177e4 2715
fc32b0e2
LB		 2716 data = rdl(mp, PHY_ADDR);
2717 data &= ~(0x1f << addr_shift);
2718 data |= (phy_addr & 0x1f) << addr_shift;
2719 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2720}
2721
e5371493 2722static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2723{
fc32b0e2
LB		 2724 unsigned int data;
2725
2726 data = rdl(mp, PHY_ADDR);
2727
2728 return (data >> (5 * mp->port_num)) & 0x1f;
2729}
2730
2731static void set_params(struct mv643xx_eth_private *mp,
2732 struct mv643xx_eth_platform_data *pd)
2733{
2734 struct net_device *dev = mp->dev;
2735
2736 if (is_valid_ether_addr(pd->mac_addr))
2737 memcpy(dev->dev_addr, pd->mac_addr, 6);
2738 else
2739 uc_addr_get(mp, dev->dev_addr);
2740
e7d2f4db 2741 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2742 if (pd->rx_queue_size)
e7d2f4db 2743 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2744 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2745 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2746
f7981c1c 2747 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2748
e7d2f4db 2749 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2750 if (pd->tx_queue_size)
e7d2f4db 2751 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2752 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2753 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2754
f7981c1c 2755 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2756}
2757
ed94493f
LB		 2758static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2759 int phy_addr)
1da177e4 2760{
298cf9be 2761 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2762 struct phy_device *phydev;
2763 int start;
2764 int num;
2765 int i;
45c5d3bc 2766
ed94493f
LB		 2767 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2768 start = phy_addr_get(mp) & 0x1f;
2769 num = 32;
2770 } else {
2771 start = phy_addr & 0x1f;
2772 num = 1;
2773 }
45c5d3bc 2774
ed94493f
LB		 2775 phydev = NULL;
2776 for (i = 0; i < num; i++) {
2777 int addr = (start + i) & 0x1f;
fc32b0e2 2778
ed94493f
LB		 2779 if (bus->phy_map[addr] == NULL)
2780 mdiobus_scan(bus, addr);
1da177e4 2781
ed94493f
LB		 2782 if (phydev == NULL) {
2783 phydev = bus->phy_map[addr];
2784 if (phydev != NULL)
2785 phy_addr_set(mp, addr);
2786 }
2787 }
1da177e4 2788
ed94493f 2789 return phydev;
1da177e4
LT		 2790}
2791
ed94493f 2792static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2793{
ed94493f 2794 struct phy_device *phy = mp->phy;
c28a4f89 2795
fc32b0e2
LB		 2796 phy_reset(mp);
2797
db1d7bf7 2798 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2799
2800 if (speed == 0) {
2801 phy->autoneg = AUTONEG_ENABLE;
2802 phy->speed = 0;
2803 phy->duplex = 0;
2804 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2805 } else {
ed94493f
LB		 2806 phy->autoneg = AUTONEG_DISABLE;
2807 phy->advertising = 0;
2808 phy->speed = speed;
2809 phy->duplex = duplex;
c9df406f 2810 }
ed94493f 2811 phy_start_aneg(phy);
c28a4f89
JC		 2812}
2813
81600eea
LB		 2814static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2815{
2816 u32 pscr;
2817
37a6084f 2818 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2819 if (pscr & SERIAL_PORT_ENABLE) {
2820 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2821 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2822 }
2823
2824 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2825 if (mp->phy == NULL) {
81600eea
LB		 2826 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2827 if (speed == SPEED_1000)
2828 pscr |= SET_GMII_SPEED_TO_1000;
2829 else if (speed == SPEED_100)
2830 pscr |= SET_MII_SPEED_TO_100;
2831
2832 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2833
2834 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2835 if (duplex == DUPLEX_FULL)
2836 pscr |= SET_FULL_DUPLEX_MODE;
2837 }
2838
37a6084f 2839 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2840}
2841
ea8a8642
LB		 2842static const struct net_device_ops mv643xx_eth_netdev_ops = {
2843 .ndo_open = mv643xx_eth_open,
2844 .ndo_stop = mv643xx_eth_stop,
2845 .ndo_start_xmit = mv643xx_eth_xmit,
2846 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2847 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2848 .ndo_do_ioctl = mv643xx_eth_ioctl,
2849 .ndo_change_mtu = mv643xx_eth_change_mtu,
2850 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2851 .ndo_get_stats = mv643xx_eth_get_stats,
2852#ifdef CONFIG_NET_POLL_CONTROLLER
2853 .ndo_poll_controller = mv643xx_eth_netpoll,
2854#endif
2855};
2856
c9df406f 2857static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2858{
c9df406f 2859 struct mv643xx_eth_platform_data *pd;
e5371493 2860 struct mv643xx_eth_private *mp;
c9df406f 2861 struct net_device *dev;
c9df406f 2862 struct resource *res;
fc32b0e2 2863 int err;
1da177e4 2864
c9df406f
LB		 2865 pd = pdev->dev.platform_data;
2866 if (pd == NULL) {
fc32b0e2
LB		 2867 dev_printk(KERN_ERR, &pdev->dev,
2868 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2869 return -ENODEV;
2870 }
1da177e4 2871
c9df406f 2872 if (pd->shared == NULL) {
fc32b0e2
LB		 2873 dev_printk(KERN_ERR, &pdev->dev,
2874 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2875 return -ENODEV;
2876 }
8f518703 2877
e5ef1de1 2878 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2879 if (!dev)
2880 return -ENOMEM;
1da177e4 2881
c9df406f 2882 mp = netdev_priv(dev);
fc32b0e2
LB		 2883 platform_set_drvdata(pdev, mp);
2884
2885 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2886 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2887 mp->port_num = pd->port_number;
2888
c9df406f 2889 mp->dev = dev;
78fff83b 2890
fc32b0e2 2891 set_params(mp, pd);
e5ef1de1 2892 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2893
ed94493f
LB		 2894 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2895 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2896
6bdf576e 2897 if (mp->phy != NULL)
ed94493f 2898 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2899
2900 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2901
81600eea 2902 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2903
4ff3495a
LB		 2904
2905 mib_counters_clear(mp);
2906
2907 init_timer(&mp->mib_counters_timer);
2908 mp->mib_counters_timer.data = (unsigned long)mp;
2909 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2910 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2911 add_timer(&mp->mib_counters_timer);
2912
2913 spin_lock_init(&mp->mib_counters_lock);
2914
2915 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2916
2257e05c
LB		 2917 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2918
2919 init_timer(&mp->rx_oom);
2920 mp->rx_oom.data = (unsigned long)mp;
2921 mp->rx_oom.function = oom_timer_wrapper;
2922
fc32b0e2 2923
c9df406f
LB		 2924 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2925 BUG_ON(!res);
2926 dev->irq = res->start;
1da177e4 2927
ea8a8642
LB		 2928 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2929
c9df406f
LB		 2930 dev->watchdog_timeo = 2 * HZ;
2931 dev->base_addr = 0;
1da177e4 2932
c9df406f 2933 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2934 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2935
fc32b0e2 2936 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2937
c9df406f 2938 if (mp->shared->win_protect)
fc32b0e2 2939 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2940
a5fe3616
LB		 2941 netif_carrier_off(dev);
2942
b5e86db4
LB		 2943 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2944
4fb0a54a 2945 set_rx_coal(mp, 250);
a5fe3616
LB		 2946 set_tx_coal(mp, 0);
2947
c9df406f
LB		 2948 err = register_netdev(dev);
2949 if (err)
2950 goto out;
1da177e4 2951
e174961c
JB		 2952 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2953 mp->port_num, dev->dev_addr);
1da177e4 2954
13d64285 2955 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2956 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2957
c9df406f 2958 return 0;
1da177e4 2959
c9df406f
LB		 2960out:
2961 free_netdev(dev);
1da177e4 2962
c9df406f 2963 return err;
1da177e4
LT		 2964}
2965
c9df406f 2966static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2967{
fc32b0e2 2968 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2969
fc32b0e2 2970 unregister_netdev(mp->dev);
ed94493f
LB		 2971 if (mp->phy != NULL)
2972 phy_detach(mp->phy);
c9df406f 2973 flush_scheduled_work();
fc32b0e2 2974 free_netdev(mp->dev);
c9df406f 2975
c9df406f 2976 platform_set_drvdata(pdev, NULL);
fc32b0e2 2977
c9df406f 2978 return 0;
1da177e4
LT		 2979}
2980
c9df406f 2981static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2982{
fc32b0e2 2983 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2984
c9df406f 2985 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2986 wrlp(mp, INT_MASK, 0);
2987 rdlp(mp, INT_MASK);
c9df406f 2988
fc32b0e2
LB		 2989 if (netif_running(mp->dev))
2990 port_reset(mp);
d0412d96
JC		 2991}
2992
c9df406f 2993static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2994 .probe = mv643xx_eth_probe,
2995 .remove = mv643xx_eth_remove,
2996 .shutdown = mv643xx_eth_shutdown,
c9df406f 2997 .driver = {
fc32b0e2 2998 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2999 .owner = THIS_MODULE,
3000 },
3001};
3002
e5371493 3003static int __init mv643xx_eth_init_module(void)
d0412d96 3004{
c9df406f 3005 int rc;
d0412d96 3006
c9df406f
LB		 3007 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3008 if (!rc) {
3009 rc = platform_driver_register(&mv643xx_eth_driver);
3010 if (rc)
3011 platform_driver_unregister(&mv643xx_eth_shared_driver);
3012 }
fc32b0e2 3013
c9df406f 3014 return rc;
d0412d96 3015}
fc32b0e2 3016module_init(mv643xx_eth_init_module);
d0412d96 3017
e5371493 3018static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3019{
c9df406f
LB		 3020 platform_driver_unregister(&mv643xx_eth_driver);
3021 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3022}
e5371493 3023module_exit(mv643xx_eth_cleanup_module);
1da177e4 3024
45675bc6
LB		 3025MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3026 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3027MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3028MODULE_LICENSE("GPL");
c9df406f 3029MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3030MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
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