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mv643xx_eth: fix TX hang erratum workaround
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
45675bc6 58static char mv643xx_eth_driver_version[] = "1.1";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 96#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 97#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 98#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 99#define INT_TX_END_0 0x00080000
226bb6b7 100#define INT_TX_END 0x07f80000
64da80a2 101#define INT_RX 0x0007fbfc
073a345c 102#define INT_EXT 0x00000002
3cb4667c 103#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 104#define INT_EXT_LINK 0x00100000
105#define INT_EXT_PHY 0x00010000
106#define INT_EXT_TX_ERROR_0 0x00000100
107#define INT_EXT_TX_0 0x00000001
3d6b35bc 108#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 109#define INT_MASK(p) (0x0468 + ((p) << 10))
110#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
111#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 112#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
113#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
114#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
115#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 116#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 117#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 118#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
119#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
120#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
121#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 122#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
123#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
124#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
125#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 126
2679a550
LB		 127
128/*
129 * SDMA configuration register.
130 */
fbd6a754 131#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 132#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 133#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 134#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 135
136#if defined(__BIG_ENDIAN)
137#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
138 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 139 TX_BURST_SIZE_4_64BIT
140#elif defined(__LITTLE_ENDIAN)
141#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_4_64BIT | \
143 BLM_RX_NO_SWAP | \
144 BLM_TX_NO_SWAP | \
fbd6a754
LB		 145 TX_BURST_SIZE_4_64BIT
146#else
147#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
148#endif
149
2beff77b
LB		 150
151/*
152 * Port serial control register.
153 */
154#define SET_MII_SPEED_TO_100 (1 << 24)
155#define SET_GMII_SPEED_TO_1000 (1 << 23)
156#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 157#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 158#define MAX_RX_PACKET_9700BYTE (5 << 17)
159#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
cc9754b3
LB		 168#define DEFAULT_RX_QUEUE_SIZE 400
169#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
7ca72a3b 232
cc9754b3 233#define TX_IHL_SHIFT 11
7ca72a3b
LB		 234
235
c9df406f 236/* global *******************************************************************/
e5371493 237struct mv643xx_eth_shared_private {
fc32b0e2
LB		 238 /*
239 * Ethernet controller base address.
240 */
cc9754b3 241 void __iomem *base;
c9df406f 242
fc32b0e2
LB		 243 /*
244 * Protects access to SMI_REG, which is shared between ports.
245 */
c9df406f
LB		 246 spinlock_t phy_lock;
247
fc32b0e2
LB		 248 /*
249 * Per-port MBUS window access register value.
250 */
c9df406f
LB		 251 u32 win_protect;
252
fc32b0e2
LB		 253 /*
254 * Hardware-specific parameters.
255 */
c9df406f 256 unsigned int t_clk;
773fc3ee 257 int extended_rx_coal_limit;
1e881592 258 int tx_bw_control_moved;
c9df406f
LB		 259};
260
261
262/* per-port *****************************************************************/
e5371493 263struct mib_counters {
fbd6a754
LB		 264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
283 u32 fc_sent;
284 u32 good_fc_received;
285 u32 bad_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
289 u32 jabber_received;
290 u32 mac_receive_error;
291 u32 bad_crc_event;
292 u32 collision;
293 u32 late_collision;
294};
295
8a578111 296struct rx_queue {
64da80a2
LB		 297 int index;
298
8a578111
LB		 299 int rx_ring_size;
300
301 int rx_desc_count;
302 int rx_curr_desc;
303 int rx_used_desc;
304
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
309
310 struct timer_list rx_oom;
311};
312
13d64285 313struct tx_queue {
3d6b35bc
LB		 314 int index;
315
13d64285 316 int tx_ring_size;
fbd6a754 317
13d64285
LB		 318 int tx_desc_count;
319 int tx_curr_desc;
320 int tx_used_desc;
fbd6a754 321
5daffe94 322 struct tx_desc *tx_desc_area;
fbd6a754
LB		 323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
13d64285
LB		 326};
327
328struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
fc32b0e2 330 int port_num;
13d64285 331
fc32b0e2 332 struct net_device *dev;
fbd6a754 333
fc32b0e2
LB		 334 struct mv643xx_eth_shared_private *shared_smi;
335 int phy_addr;
fbd6a754 336
fbd6a754 337 spinlock_t lock;
fbd6a754 338
fc32b0e2
LB		 339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
fbd6a754 341 struct mii_if_info mii;
8a578111
LB		 342
343 /*
344 * RX state.
345 */
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
64da80a2
LB		 349 u8 rxq_mask;
350 int rxq_primary;
8a578111 351 struct napi_struct napi;
64da80a2 352 struct rx_queue rxq[8];
13d64285
LB		 353
354 /*
355 * TX state.
356 */
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
3d6b35bc
LB		 360 u8 txq_mask;
361 int txq_primary;
362 struct tx_queue txq[8];
13d64285
LB		 363#ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
365#endif
fbd6a754 366};
1da177e4 367
fbd6a754 368
c9df406f 369/* port register accessors **************************************************/
e5371493 370static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 371{
cc9754b3 372 return readl(mp->shared->base + offset);
c9df406f 373}
fbd6a754 374
e5371493 375static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 376{
cc9754b3 377 writel(data, mp->shared->base + offset);
c9df406f 378}
fbd6a754 379
fbd6a754 380
c9df406f 381/* rxq/txq helper functions *************************************************/
8a578111 382static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 383{
64da80a2 384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 385}
fbd6a754 386
13d64285
LB		 387static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
388{
3d6b35bc 389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 390}
391
8a578111 392static void rxq_enable(struct rx_queue *rxq)
c9df406f 393{
8a578111 394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 396}
1da177e4 397
8a578111
LB		 398static void rxq_disable(struct rx_queue *rxq)
399{
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 401 u8 mask = 1 << rxq->index;
1da177e4 402
8a578111
LB		 403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
405 udelay(10);
c9df406f
LB		 406}
407
13d64285 408static void txq_enable(struct tx_queue *txq)
1da177e4 409{
13d64285 410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 411 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 412}
413
13d64285 414static void txq_disable(struct tx_queue *txq)
1da177e4 415{
13d64285 416 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 417 u8 mask = 1 << txq->index;
c9df406f 418
13d64285
LB		 419 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
420 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
421 udelay(10);
422}
423
424static void __txq_maybe_wake(struct tx_queue *txq)
425{
426 struct mv643xx_eth_private *mp = txq_to_mp(txq);
427
3d6b35bc
LB		 428 /*
429 * netif_{stop,wake}_queue() flow control only applies to
430 * the primary queue.
431 */
432 BUG_ON(txq->index != mp->txq_primary);
433
13d64285
LB		 434 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
435 netif_wake_queue(mp->dev);
1da177e4
LT		 436}
437
c9df406f
LB		 438
439/* rx ***********************************************************************/
13d64285 440static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 441
8a578111 442static void rxq_refill(struct rx_queue *rxq)
1da177e4 443{
8a578111 444 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 445 unsigned long flags;
1da177e4 446
c9df406f 447 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 448
8a578111
LB		 449 while (rxq->rx_desc_count < rxq->rx_ring_size) {
450 int skb_size;
de34f225
LB		 451 struct sk_buff *skb;
452 int unaligned;
453 int rx;
454
8a578111
LB		 455 /*
456 * Reserve 2+14 bytes for an ethernet header (the
457 * hardware automatically prepends 2 bytes of dummy
458 * data to each received packet), 4 bytes for a VLAN
459 * header, and 4 bytes for the trailing FCS -- 24
460 * bytes total.
461 */
462 skb_size = mp->dev->mtu + 24;
463
464 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 465 if (skb == NULL)
1da177e4 466 break;
de34f225 467
908b637f 468 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 469 if (unaligned)
908b637f 470 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 471
8a578111
LB		 472 rxq->rx_desc_count++;
473 rx = rxq->rx_used_desc;
474 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 475
8a578111
LB		 476 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
477 skb_size, DMA_FROM_DEVICE);
478 rxq->rx_desc_area[rx].buf_size = skb_size;
479 rxq->rx_skb[rx] = skb;
de34f225 480 wmb();
8a578111 481 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 482 RX_ENABLE_INTERRUPT;
483 wmb();
484
fc32b0e2
LB		 485 /*
486 * The hardware automatically prepends 2 bytes of
487 * dummy data to each received packet, so that the
488 * IP header ends up 16-byte aligned.
489 */
490 skb_reserve(skb, 2);
1da177e4 491 }
de34f225 492
12e4ab79 493 if (rxq->rx_desc_count != rxq->rx_ring_size) {
8a578111
LB		 494 rxq->rx_oom.expires = jiffies + (HZ / 10);
495 add_timer(&rxq->rx_oom);
1da177e4 496 }
de34f225
LB		 497
498 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 499}
500
8a578111 501static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 502{
8a578111 503 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 504}
505
8a578111 506static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 507{
8a578111
LB		 508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
509 struct net_device_stats *stats = &mp->dev->stats;
510 int rx;
1da177e4 511
8a578111
LB		 512 rx = 0;
513 while (rx < budget) {
fc32b0e2 514 struct rx_desc *rx_desc;
96587661 515 unsigned int cmd_sts;
fc32b0e2 516 struct sk_buff *skb;
96587661 517 unsigned long flags;
d344bff9 518
96587661 519 spin_lock_irqsave(&mp->lock, flags);
ff561eef 520
8a578111 521 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 522
96587661
LB		 523 cmd_sts = rx_desc->cmd_sts;
524 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
525 spin_unlock_irqrestore(&mp->lock, flags);
526 break;
527 }
528 rmb();
1da177e4 529
8a578111
LB		 530 skb = rxq->rx_skb[rxq->rx_curr_desc];
531 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 532
8a578111 533 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 534
96587661 535 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 536
fc32b0e2
LB		 537 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
538 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 539 rxq->rx_desc_count--;
540 rx++;
b1dd9ca1 541
468d09f8
DF		 542 /*
543 * Update statistics.
fc32b0e2
LB		 544 *
545 * Note that the descriptor byte count includes 2 dummy
546 * bytes automatically inserted by the hardware at the
547 * start of the packet (which we don't count), and a 4
548 * byte CRC at the end of the packet (which we do count).
468d09f8 549 */
1da177e4 550 stats->rx_packets++;
fc32b0e2 551 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 552
1da177e4 553 /*
fc32b0e2
LB		 554 * In case we received a packet without first / last bits
555 * on, or the error summary bit is set, the packet needs
556 * to be dropped.
1da177e4 557 */
96587661 558 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 559 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 560 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 561 stats->rx_dropped++;
fc32b0e2 562
96587661 563 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 564 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 565 if (net_ratelimit())
fc32b0e2
LB		 566 dev_printk(KERN_ERR, &mp->dev->dev,
567 "received packet spanning "
568 "multiple descriptors\n");
1da177e4 569 }
fc32b0e2 570
96587661 571 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 572 stats->rx_errors++;
573
574 dev_kfree_skb_irq(skb);
575 } else {
576 /*
577 * The -4 is for the CRC in the trailer of the
578 * received packet
579 */
fc32b0e2 580 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 581
96587661 582 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 583 skb->ip_summed = CHECKSUM_UNNECESSARY;
584 skb->csum = htons(
96587661 585 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 586 }
8a578111 587 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 588#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 589 netif_receive_skb(skb);
590#else
591 netif_rx(skb);
592#endif
593 }
fc32b0e2 594
8a578111 595 mp->dev->last_rx = jiffies;
1da177e4 596 }
fc32b0e2 597
8a578111 598 rxq_refill(rxq);
1da177e4 599
8a578111 600 return rx;
1da177e4
LT		 601}
602
e5371493 603#ifdef MV643XX_ETH_NAPI
e5371493 604static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 605{
8a578111
LB		 606 struct mv643xx_eth_private *mp;
607 int rx;
64da80a2 608 int i;
8a578111
LB		 609
610 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 611
e5371493 612#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 613 if (++mp->tx_clean_threshold > 5) {
c9df406f 614 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 615 for (i = 0; i < 8; i++)
616 if (mp->txq_mask & (1 << i))
617 txq_reclaim(mp->txq + i, 0);
d0412d96 618 }
c9df406f 619#endif
d0412d96 620
64da80a2
LB		 621 rx = 0;
622 for (i = 7; rx < budget && i >= 0; i--)
623 if (mp->rxq_mask & (1 << i))
624 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 625
8a578111
LB		 626 if (rx < budget) {
627 netif_rx_complete(mp->dev, napi);
628 wrl(mp, INT_CAUSE(mp->port_num), 0);
629 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 630 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 631 }
c9df406f 632
8a578111 633 return rx;
d0412d96 634}
c9df406f 635#endif
d0412d96 636
c9df406f
LB		 637
638/* tx ***********************************************************************/
c9df406f 639static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 640{
13d64285 641 int frag;
1da177e4 642
c9df406f 643 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 644 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
645 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 646 return 1;
1da177e4 647 }
13d64285 648
c9df406f
LB		 649 return 0;
650}
7303fde8 651
13d64285 652static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 653{
654 int tx_desc_curr;
d0412d96 655
13d64285 656 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 657
13d64285
LB		 658 tx_desc_curr = txq->tx_curr_desc;
659 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 660
13d64285 661 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 662
c9df406f
LB		 663 return tx_desc_curr;
664}
468d09f8 665
13d64285 666static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 667{
13d64285 668 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 669 int frag;
1da177e4 670
13d64285
LB		 671 for (frag = 0; frag < nr_frags; frag++) {
672 skb_frag_t *this_frag;
673 int tx_index;
674 struct tx_desc *desc;
675
676 this_frag = &skb_shinfo(skb)->frags[frag];
677 tx_index = txq_alloc_desc_index(txq);
678 desc = &txq->tx_desc_area[tx_index];
679
680 /*
681 * The last fragment will generate an interrupt
682 * which will free the skb on TX completion.
683 */
684 if (frag == nr_frags - 1) {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
686 ZERO_PADDING | TX_LAST_DESC |
687 TX_ENABLE_INTERRUPT;
688 txq->tx_skb[tx_index] = skb;
689 } else {
690 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
691 txq->tx_skb[tx_index] = NULL;
692 }
693
c9df406f
LB		 694 desc->l4i_chk = 0;
695 desc->byte_cnt = this_frag->size;
696 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
697 this_frag->page_offset,
698 this_frag->size,
699 DMA_TO_DEVICE);
700 }
1da177e4
LT		 701}
702
c9df406f
LB		 703static inline __be16 sum16_as_be(__sum16 sum)
704{
705 return (__force __be16)sum;
706}
1da177e4 707
13d64285 708static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 709{
8fa89bf5 710 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 711 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 712 int tx_index;
cc9754b3 713 struct tx_desc *desc;
c9df406f
LB		 714 u32 cmd_sts;
715 int length;
1da177e4 716
cc9754b3 717 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 718
13d64285
LB		 719 tx_index = txq_alloc_desc_index(txq);
720 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 721
722 if (nr_frags) {
13d64285 723 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 724
725 length = skb_headlen(skb);
13d64285 726 txq->tx_skb[tx_index] = NULL;
c9df406f 727 } else {
cc9754b3 728 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 729 length = skb->len;
13d64285 730 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 731 }
732
733 desc->byte_cnt = length;
734 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
735
736 if (skb->ip_summed == CHECKSUM_PARTIAL) {
737 BUG_ON(skb->protocol != htons(ETH_P_IP));
738
cc9754b3
LB		 739 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
740 GEN_IP_V4_CHECKSUM |
741 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 742
743 switch (ip_hdr(skb)->protocol) {
744 case IPPROTO_UDP:
cc9754b3 745 cmd_sts |= UDP_FRAME;
c9df406f
LB		 746 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
747 break;
748 case IPPROTO_TCP:
749 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
750 break;
751 default:
752 BUG();
753 }
754 } else {
755 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 756 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 757 desc->l4i_chk = 0;
758 }
759
760 /* ensure all other descriptors are written before first cmd_sts */
761 wmb();
762 desc->cmd_sts = cmd_sts;
763
8fa89bf5
LB		 764 /* clear TX_END interrupt status */
765 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
766 rdl(mp, INT_CAUSE(mp->port_num));
767
c9df406f
LB		 768 /* ensure all descriptors are written before poking hardware */
769 wmb();
13d64285 770 txq_enable(txq);
c9df406f 771
13d64285 772 txq->tx_desc_count += nr_frags + 1;
1da177e4 773}
1da177e4 774
fc32b0e2 775static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 776{
e5371493 777 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 778 struct net_device_stats *stats = &dev->stats;
13d64285 779 struct tx_queue *txq;
c9df406f 780 unsigned long flags;
afdb57a2 781
c9df406f
LB		 782 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
783 stats->tx_dropped++;
fc32b0e2
LB		 784 dev_printk(KERN_DEBUG, &dev->dev,
785 "failed to linearize skb with tiny "
786 "unaligned fragment\n");
c9df406f
LB		 787 return NETDEV_TX_BUSY;
788 }
789
790 spin_lock_irqsave(&mp->lock, flags);
791
3d6b35bc 792 txq = mp->txq + mp->txq_primary;
13d64285
LB		 793
794 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 795 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 796 if (txq->index == mp->txq_primary && net_ratelimit())
797 dev_printk(KERN_ERR, &dev->dev,
798 "primary tx queue full?!\n");
799 kfree_skb(skb);
800 return NETDEV_TX_OK;
c9df406f
LB		 801 }
802
13d64285 803 txq_submit_skb(txq, skb);
c9df406f
LB		 804 stats->tx_bytes += skb->len;
805 stats->tx_packets++;
806 dev->trans_start = jiffies;
807
3d6b35bc
LB		 808 if (txq->index == mp->txq_primary) {
809 int entries_left;
810
811 entries_left = txq->tx_ring_size - txq->tx_desc_count;
812 if (entries_left < MAX_DESCS_PER_SKB)
813 netif_stop_queue(dev);
814 }
c9df406f
LB		 815
816 spin_unlock_irqrestore(&mp->lock, flags);
817
818 return NETDEV_TX_OK;
1da177e4
LT		 819}
820
c9df406f 821
89df5fdc
LB		 822/* tx rate control **********************************************************/
823/*
824 * Set total maximum TX rate (shared by all TX queues for this port)
825 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
826 */
827static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
828{
829 int token_rate;
830 int mtu;
831 int bucket_size;
832
833 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
834 if (token_rate > 1023)
835 token_rate = 1023;
836
837 mtu = (mp->dev->mtu + 255) >> 8;
838 if (mtu > 63)
839 mtu = 63;
840
841 bucket_size = (burst + 255) >> 8;
842 if (bucket_size > 65535)
843 bucket_size = 65535;
844
1e881592
LB		 845 if (mp->shared->tx_bw_control_moved) {
846 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
847 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
848 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
849 } else {
850 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
851 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
852 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
853 }
89df5fdc
LB		 854}
855
856static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
857{
858 struct mv643xx_eth_private *mp = txq_to_mp(txq);
859 int token_rate;
860 int bucket_size;
861
862 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
863 if (token_rate > 1023)
864 token_rate = 1023;
865
866 bucket_size = (burst + 255) >> 8;
867 if (bucket_size > 65535)
868 bucket_size = 65535;
869
3d6b35bc
LB		 870 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
871 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 872 (bucket_size << 10) | token_rate);
873}
874
875static void txq_set_fixed_prio_mode(struct tx_queue *txq)
876{
877 struct mv643xx_eth_private *mp = txq_to_mp(txq);
878 int off;
879 u32 val;
880
881 /*
882 * Turn on fixed priority mode.
883 */
1e881592
LB		 884 if (mp->shared->tx_bw_control_moved)
885 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
886 else
887 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 888
889 val = rdl(mp, off);
3d6b35bc 890 val |= 1 << txq->index;
89df5fdc
LB		 891 wrl(mp, off, val);
892}
893
894static void txq_set_wrr(struct tx_queue *txq, int weight)
895{
896 struct mv643xx_eth_private *mp = txq_to_mp(txq);
897 int off;
898 u32 val;
899
900 /*
901 * Turn off fixed priority mode.
902 */
1e881592
LB		 903 if (mp->shared->tx_bw_control_moved)
904 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
905 else
906 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 907
908 val = rdl(mp, off);
3d6b35bc 909 val &= ~(1 << txq->index);
89df5fdc
LB		 910 wrl(mp, off, val);
911
912 /*
913 * Configure WRR weight for this queue.
914 */
3d6b35bc 915 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 916
917 val = rdl(mp, off);
918 val = (val & ~0xff) | (weight & 0xff);
919 wrl(mp, off, val);
920}
921
922
c9df406f 923/* mii management interface *************************************************/
fc32b0e2
LB		 924#define SMI_BUSY 0x10000000
925#define SMI_READ_VALID 0x08000000
926#define SMI_OPCODE_READ 0x04000000
927#define SMI_OPCODE_WRITE 0x00000000
c9df406f 928
fc32b0e2
LB		 929static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
930 unsigned int reg, unsigned int *value)
1da177e4 931{
cc9754b3 932 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 933 unsigned long flags;
1da177e4
LT		 934 int i;
935
c9df406f
LB		 936 /* the SMI register is a shared resource */
937 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
938
939 /* wait for the SMI register to become available */
cc9754b3 940 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 941 if (i == 1000) {
c9df406f
LB		 942 printk("%s: PHY busy timeout\n", mp->dev->name);
943 goto out;
944 }
e1bea50a 945 udelay(10);
1da177e4
LT		 946 }
947
fc32b0e2 948 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 949
c9df406f 950 /* now wait for the data to be valid */
cc9754b3 951 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 952 if (i == 1000) {
c9df406f
LB		 953 printk("%s: PHY read timeout\n", mp->dev->name);
954 goto out;
955 }
e1bea50a 956 udelay(10);
c9df406f
LB		 957 }
958
959 *value = readl(smi_reg) & 0xffff;
960out:
961 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 962}
963
fc32b0e2
LB		 964static void smi_reg_write(struct mv643xx_eth_private *mp,
965 unsigned int addr,
966 unsigned int reg, unsigned int value)
1da177e4 967{
cc9754b3 968 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 969 unsigned long flags;
1da177e4
LT		 970 int i;
971
c9df406f
LB		 972 /* the SMI register is a shared resource */
973 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
974
975 /* wait for the SMI register to become available */
cc9754b3 976 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 977 if (i == 1000) {
c9df406f
LB		 978 printk("%s: PHY busy timeout\n", mp->dev->name);
979 goto out;
980 }
e1bea50a 981 udelay(10);
1da177e4
LT		 982 }
983
fc32b0e2
LB		 984 writel(SMI_OPCODE_WRITE | (reg << 21) |
985 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 986out:
987 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
988}
1da177e4 989
c9df406f
LB		 990
991/* mib counters *************************************************************/
fc32b0e2 992static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 993{
fc32b0e2 994 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 995}
996
fc32b0e2 997static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 998{
fc32b0e2
LB		 999 int i;
1000
1001 for (i = 0; i < 0x80; i += 4)
1002 mib_read(mp, i);
c9df406f 1003}
d0412d96 1004
fc32b0e2 1005static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1006{
e5371493 1007 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1008
fc32b0e2
LB		 1009 p->good_octets_received += mib_read(mp, 0x00);
1010 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1011 p->bad_octets_received += mib_read(mp, 0x08);
1012 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1013 p->good_frames_received += mib_read(mp, 0x10);
1014 p->bad_frames_received += mib_read(mp, 0x14);
1015 p->broadcast_frames_received += mib_read(mp, 0x18);
1016 p->multicast_frames_received += mib_read(mp, 0x1c);
1017 p->frames_64_octets += mib_read(mp, 0x20);
1018 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1019 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1020 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1021 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1022 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1023 p->good_octets_sent += mib_read(mp, 0x38);
1024 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1025 p->good_frames_sent += mib_read(mp, 0x40);
1026 p->excessive_collision += mib_read(mp, 0x44);
1027 p->multicast_frames_sent += mib_read(mp, 0x48);
1028 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1029 p->unrec_mac_control_received += mib_read(mp, 0x50);
1030 p->fc_sent += mib_read(mp, 0x54);
1031 p->good_fc_received += mib_read(mp, 0x58);
1032 p->bad_fc_received += mib_read(mp, 0x5c);
1033 p->undersize_received += mib_read(mp, 0x60);
1034 p->fragments_received += mib_read(mp, 0x64);
1035 p->oversize_received += mib_read(mp, 0x68);
1036 p->jabber_received += mib_read(mp, 0x6c);
1037 p->mac_receive_error += mib_read(mp, 0x70);
1038 p->bad_crc_event += mib_read(mp, 0x74);
1039 p->collision += mib_read(mp, 0x78);
1040 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1041}
1042
c9df406f
LB		 1043
1044/* ethtool ******************************************************************/
e5371493 1045struct mv643xx_eth_stats {
c9df406f
LB		 1046 char stat_string[ETH_GSTRING_LEN];
1047 int sizeof_stat;
16820054
LB		 1048 int netdev_off;
1049 int mp_off;
c9df406f
LB		 1050};
1051
16820054
LB		 1052#define SSTAT(m) \
1053 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1054 offsetof(struct net_device, stats.m), -1 }
1055
1056#define MIBSTAT(m) \
1057 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1058 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1059
1060static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1061 SSTAT(rx_packets),
1062 SSTAT(tx_packets),
1063 SSTAT(rx_bytes),
1064 SSTAT(tx_bytes),
1065 SSTAT(rx_errors),
1066 SSTAT(tx_errors),
1067 SSTAT(rx_dropped),
1068 SSTAT(tx_dropped),
1069 MIBSTAT(good_octets_received),
1070 MIBSTAT(bad_octets_received),
1071 MIBSTAT(internal_mac_transmit_err),
1072 MIBSTAT(good_frames_received),
1073 MIBSTAT(bad_frames_received),
1074 MIBSTAT(broadcast_frames_received),
1075 MIBSTAT(multicast_frames_received),
1076 MIBSTAT(frames_64_octets),
1077 MIBSTAT(frames_65_to_127_octets),
1078 MIBSTAT(frames_128_to_255_octets),
1079 MIBSTAT(frames_256_to_511_octets),
1080 MIBSTAT(frames_512_to_1023_octets),
1081 MIBSTAT(frames_1024_to_max_octets),
1082 MIBSTAT(good_octets_sent),
1083 MIBSTAT(good_frames_sent),
1084 MIBSTAT(excessive_collision),
1085 MIBSTAT(multicast_frames_sent),
1086 MIBSTAT(broadcast_frames_sent),
1087 MIBSTAT(unrec_mac_control_received),
1088 MIBSTAT(fc_sent),
1089 MIBSTAT(good_fc_received),
1090 MIBSTAT(bad_fc_received),
1091 MIBSTAT(undersize_received),
1092 MIBSTAT(fragments_received),
1093 MIBSTAT(oversize_received),
1094 MIBSTAT(jabber_received),
1095 MIBSTAT(mac_receive_error),
1096 MIBSTAT(bad_crc_event),
1097 MIBSTAT(collision),
1098 MIBSTAT(late_collision),
c9df406f
LB		 1099};
1100
e5371493 1101static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1102{
e5371493 1103 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1104 int err;
1105
1106 spin_lock_irq(&mp->lock);
1107 err = mii_ethtool_gset(&mp->mii, cmd);
1108 spin_unlock_irq(&mp->lock);
1109
fc32b0e2
LB		 1110 /*
1111 * The MAC does not support 1000baseT_Half.
1112 */
d0412d96
JC		 1113 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1114 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1115
1116 return err;
1117}
1118
bedfe324
LB		 1119static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1120{
1121 cmd->supported = SUPPORTED_MII;
1122 cmd->advertising = ADVERTISED_MII;
1123 cmd->speed = SPEED_1000;
1124 cmd->duplex = DUPLEX_FULL;
1125 cmd->port = PORT_MII;
1126 cmd->phy_address = 0;
1127 cmd->transceiver = XCVR_INTERNAL;
1128 cmd->autoneg = AUTONEG_DISABLE;
1129 cmd->maxtxpkt = 1;
1130 cmd->maxrxpkt = 1;
1131
1132 return 0;
1133}
1134
e5371493 1135static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1136{
e5371493 1137 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1138 int err;
1139
fc32b0e2
LB		 1140 /*
1141 * The MAC does not support 1000baseT_Half.
1142 */
1143 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1144
c9df406f
LB		 1145 spin_lock_irq(&mp->lock);
1146 err = mii_ethtool_sset(&mp->mii, cmd);
1147 spin_unlock_irq(&mp->lock);
85cf572c 1148
c9df406f
LB		 1149 return err;
1150}
1da177e4 1151
bedfe324
LB		 1152static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1153{
1154 return -EINVAL;
1155}
1156
fc32b0e2
LB		 1157static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1158 struct ethtool_drvinfo *drvinfo)
c9df406f 1159{
e5371493
LB		 1160 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1161 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1162 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1163 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1164 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1165}
1da177e4 1166
fc32b0e2 1167static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1168{
e5371493 1169 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1170
c9df406f
LB		 1171 return mii_nway_restart(&mp->mii);
1172}
1da177e4 1173
bedfe324
LB		 1174static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1175{
1176 return -EINVAL;
1177}
1178
c9df406f
LB		 1179static u32 mv643xx_eth_get_link(struct net_device *dev)
1180{
e5371493 1181 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1182
c9df406f
LB		 1183 return mii_link_ok(&mp->mii);
1184}
1da177e4 1185
bedfe324
LB		 1186static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1187{
1188 return 1;
1189}
1190
fc32b0e2
LB		 1191static void mv643xx_eth_get_strings(struct net_device *dev,
1192 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1193{
1194 int i;
1da177e4 1195
fc32b0e2
LB		 1196 if (stringset == ETH_SS_STATS) {
1197 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1198 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1199 mv643xx_eth_stats[i].stat_string,
e5371493 1200 ETH_GSTRING_LEN);
c9df406f 1201 }
c9df406f
LB		 1202 }
1203}
1da177e4 1204
fc32b0e2
LB		 1205static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1206 struct ethtool_stats *stats,
1207 uint64_t *data)
c9df406f 1208{
fc32b0e2 1209 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1210 int i;
1da177e4 1211
fc32b0e2 1212 mib_counters_update(mp);
1da177e4 1213
16820054
LB		 1214 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1215 const struct mv643xx_eth_stats *stat;
1216 void *p;
1217
1218 stat = mv643xx_eth_stats + i;
1219
1220 if (stat->netdev_off >= 0)
1221 p = ((void *)mp->dev) + stat->netdev_off;
1222 else
1223 p = ((void *)mp) + stat->mp_off;
1224
1225 data[i] = (stat->sizeof_stat == 8) ?
1226 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1227 }
c9df406f 1228}
1da177e4 1229
fc32b0e2 1230static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1231{
fc32b0e2 1232 if (sset == ETH_SS_STATS)
16820054 1233 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1234
1235 return -EOPNOTSUPP;
c9df406f 1236}
1da177e4 1237
e5371493 1238static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1239 .get_settings = mv643xx_eth_get_settings,
1240 .set_settings = mv643xx_eth_set_settings,
1241 .get_drvinfo = mv643xx_eth_get_drvinfo,
1242 .nway_reset = mv643xx_eth_nway_reset,
1243 .get_link = mv643xx_eth_get_link,
c9df406f 1244 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1245 .get_strings = mv643xx_eth_get_strings,
1246 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1247 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1248};
1da177e4 1249
bedfe324
LB		 1250static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1251 .get_settings = mv643xx_eth_get_settings_phyless,
1252 .set_settings = mv643xx_eth_set_settings_phyless,
1253 .get_drvinfo = mv643xx_eth_get_drvinfo,
1254 .nway_reset = mv643xx_eth_nway_reset_phyless,
1255 .get_link = mv643xx_eth_get_link_phyless,
1256 .set_sg = ethtool_op_set_sg,
1257 .get_strings = mv643xx_eth_get_strings,
1258 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1259 .get_sset_count = mv643xx_eth_get_sset_count,
1260};
1261
bea3348e 1262
c9df406f 1263/* address handling *********************************************************/
5daffe94 1264static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1265{
c9df406f
LB		 1266 unsigned int mac_h;
1267 unsigned int mac_l;
1da177e4 1268
fc32b0e2
LB		 1269 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1270 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1271
5daffe94
LB		 1272 addr[0] = (mac_h >> 24) & 0xff;
1273 addr[1] = (mac_h >> 16) & 0xff;
1274 addr[2] = (mac_h >> 8) & 0xff;
1275 addr[3] = mac_h & 0xff;
1276 addr[4] = (mac_l >> 8) & 0xff;
1277 addr[5] = mac_l & 0xff;
c9df406f 1278}
1da177e4 1279
e5371493 1280static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1281{
fc32b0e2 1282 int i;
1da177e4 1283
fc32b0e2
LB		 1284 for (i = 0; i < 0x100; i += 4) {
1285 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1286 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1287 }
fc32b0e2
LB		 1288
1289 for (i = 0; i < 0x10; i += 4)
1290 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1291}
d0412d96 1292
e5371493 1293static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1294 int table, unsigned char entry)
c9df406f
LB		 1295{
1296 unsigned int table_reg;
ab4384a6 1297
c9df406f 1298 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1299 table_reg = rdl(mp, table + (entry & 0xfc));
1300 table_reg |= 0x01 << (8 * (entry & 3));
1301 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1302}
1303
5daffe94 1304static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1305{
c9df406f
LB		 1306 unsigned int mac_h;
1307 unsigned int mac_l;
1308 int table;
1da177e4 1309
fc32b0e2
LB		 1310 mac_l = (addr[4] << 8) | addr[5];
1311 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1312
fc32b0e2
LB		 1313 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1314 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1315
fc32b0e2 1316 table = UNICAST_TABLE(mp->port_num);
5daffe94 1317 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1318}
1319
fc32b0e2 1320static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1321{
e5371493 1322 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1323
fc32b0e2
LB		 1324 /* +2 is for the offset of the HW addr type */
1325 memcpy(dev->dev_addr, addr + 2, 6);
1326
cc9754b3
LB		 1327 init_mac_tables(mp);
1328 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1329
1330 return 0;
1331}
1332
69876569
LB		 1333static int addr_crc(unsigned char *addr)
1334{
1335 int crc = 0;
1336 int i;
1337
1338 for (i = 0; i < 6; i++) {
1339 int j;
1340
1341 crc = (crc ^ addr[i]) << 8;
1342 for (j = 7; j >= 0; j--) {
1343 if (crc & (0x100 << j))
1344 crc ^= 0x107 << j;
1345 }
1346 }
1347
1348 return crc;
1349}
1350
fc32b0e2 1351static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1352{
fc32b0e2
LB		 1353 struct mv643xx_eth_private *mp = netdev_priv(dev);
1354 u32 port_config;
1355 struct dev_addr_list *addr;
1356 int i;
c8aaea25 1357
fc32b0e2
LB		 1358 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1359 if (dev->flags & IFF_PROMISC)
1360 port_config |= UNICAST_PROMISCUOUS_MODE;
1361 else
1362 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1363 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1364
fc32b0e2
LB		 1365 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1366 int port_num = mp->port_num;
1367 u32 accept = 0x01010101;
c8aaea25 1368
fc32b0e2
LB		 1369 for (i = 0; i < 0x100; i += 4) {
1370 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1371 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1372 }
1373 return;
1374 }
c8aaea25 1375
fc32b0e2
LB		 1376 for (i = 0; i < 0x100; i += 4) {
1377 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1378 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1379 }
1380
fc32b0e2
LB		 1381 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1382 u8 *a = addr->da_addr;
1383 int table;
324ff2c1 1384
fc32b0e2
LB		 1385 if (addr->da_addrlen != 6)
1386 continue;
1da177e4 1387
fc32b0e2
LB		 1388 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1389 table = SPECIAL_MCAST_TABLE(mp->port_num);
1390 set_filter_table_entry(mp, table, a[5]);
1391 } else {
1392 int crc = addr_crc(a);
1da177e4 1393
fc32b0e2
LB		 1394 table = OTHER_MCAST_TABLE(mp->port_num);
1395 set_filter_table_entry(mp, table, crc);
1396 }
1397 }
c9df406f 1398}
c8aaea25 1399
c8aaea25 1400
c9df406f 1401/* rx/tx queue initialisation ***********************************************/
64da80a2 1402static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1403{
64da80a2 1404 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1405 struct rx_desc *rx_desc;
1406 int size;
c9df406f
LB		 1407 int i;
1408
64da80a2
LB		 1409 rxq->index = index;
1410
8a578111
LB		 1411 rxq->rx_ring_size = mp->default_rx_ring_size;
1412
1413 rxq->rx_desc_count = 0;
1414 rxq->rx_curr_desc = 0;
1415 rxq->rx_used_desc = 0;
1416
1417 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1418
64da80a2 1419 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1420 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1421 mp->rx_desc_sram_size);
1422 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1423 } else {
1424 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1425 &rxq->rx_desc_dma,
1426 GFP_KERNEL);
f7ea3337
PJ		 1427 }
1428
8a578111
LB		 1429 if (rxq->rx_desc_area == NULL) {
1430 dev_printk(KERN_ERR, &mp->dev->dev,
1431 "can't allocate rx ring (%d bytes)\n", size);
1432 goto out;
1433 }
1434 memset(rxq->rx_desc_area, 0, size);
1da177e4 1435
8a578111
LB		 1436 rxq->rx_desc_area_size = size;
1437 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1438 GFP_KERNEL);
1439 if (rxq->rx_skb == NULL) {
1440 dev_printk(KERN_ERR, &mp->dev->dev,
1441 "can't allocate rx skb ring\n");
1442 goto out_free;
1443 }
1444
1445 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1446 for (i = 0; i < rxq->rx_ring_size; i++) {
1447 int nexti = (i + 1) % rxq->rx_ring_size;
1448 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1449 nexti * sizeof(struct rx_desc);
1450 }
1451
1452 init_timer(&rxq->rx_oom);
1453 rxq->rx_oom.data = (unsigned long)rxq;
1454 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1455
1456 return 0;
1457
1458
1459out_free:
64da80a2 1460 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1461 iounmap(rxq->rx_desc_area);
1462 else
1463 dma_free_coherent(NULL, size,
1464 rxq->rx_desc_area,
1465 rxq->rx_desc_dma);
1466
1467out:
1468 return -ENOMEM;
c9df406f 1469}
c8aaea25 1470
8a578111 1471static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1472{
8a578111
LB		 1473 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1474 int i;
1475
1476 rxq_disable(rxq);
c8aaea25 1477
8a578111 1478 del_timer_sync(&rxq->rx_oom);
c9df406f 1479
8a578111
LB		 1480 for (i = 0; i < rxq->rx_ring_size; i++) {
1481 if (rxq->rx_skb[i]) {
1482 dev_kfree_skb(rxq->rx_skb[i]);
1483 rxq->rx_desc_count--;
1da177e4 1484 }
c8aaea25 1485 }
1da177e4 1486
8a578111
LB		 1487 if (rxq->rx_desc_count) {
1488 dev_printk(KERN_ERR, &mp->dev->dev,
1489 "error freeing rx ring -- %d skbs stuck\n",
1490 rxq->rx_desc_count);
1491 }
1492
64da80a2
LB		 1493 if (rxq->index == mp->rxq_primary &&
1494 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1495 iounmap(rxq->rx_desc_area);
c9df406f 1496 else
8a578111
LB		 1497 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1498 rxq->rx_desc_area, rxq->rx_desc_dma);
1499
1500 kfree(rxq->rx_skb);
c9df406f 1501}
1da177e4 1502
3d6b35bc 1503static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1504{
3d6b35bc 1505 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1506 struct tx_desc *tx_desc;
1507 int size;
c9df406f 1508 int i;
1da177e4 1509
3d6b35bc
LB		 1510 txq->index = index;
1511
13d64285
LB		 1512 txq->tx_ring_size = mp->default_tx_ring_size;
1513
1514 txq->tx_desc_count = 0;
1515 txq->tx_curr_desc = 0;
1516 txq->tx_used_desc = 0;
1517
1518 size = txq->tx_ring_size * sizeof(struct tx_desc);
1519
3d6b35bc 1520 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1521 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1522 mp->tx_desc_sram_size);
1523 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1524 } else {
1525 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1526 &txq->tx_desc_dma,
1527 GFP_KERNEL);
1528 }
1529
1530 if (txq->tx_desc_area == NULL) {
1531 dev_printk(KERN_ERR, &mp->dev->dev,
1532 "can't allocate tx ring (%d bytes)\n", size);
1533 goto out;
c9df406f 1534 }
13d64285
LB		 1535 memset(txq->tx_desc_area, 0, size);
1536
1537 txq->tx_desc_area_size = size;
1538 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1539 GFP_KERNEL);
1540 if (txq->tx_skb == NULL) {
1541 dev_printk(KERN_ERR, &mp->dev->dev,
1542 "can't allocate tx skb ring\n");
1543 goto out_free;
1544 }
1545
1546 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1547 for (i = 0; i < txq->tx_ring_size; i++) {
1548 int nexti = (i + 1) % txq->tx_ring_size;
1549 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1550 nexti * sizeof(struct tx_desc);
1551 }
1552
1553 return 0;
1554
c9df406f 1555
13d64285 1556out_free:
3d6b35bc 1557 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1558 iounmap(txq->tx_desc_area);
1559 else
1560 dma_free_coherent(NULL, size,
1561 txq->tx_desc_area,
1562 txq->tx_desc_dma);
c9df406f 1563
13d64285
LB		 1564out:
1565 return -ENOMEM;
c8aaea25 1566}
1da177e4 1567
13d64285 1568static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1569{
13d64285 1570 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1571 unsigned long flags;
1da177e4 1572
13d64285
LB		 1573 spin_lock_irqsave(&mp->lock, flags);
1574 while (txq->tx_desc_count > 0) {
1575 int tx_index;
1576 struct tx_desc *desc;
1577 u32 cmd_sts;
1578 struct sk_buff *skb;
1579 dma_addr_t addr;
1580 int count;
4d64e718 1581
13d64285
LB		 1582 tx_index = txq->tx_used_desc;
1583 desc = &txq->tx_desc_area[tx_index];
c9df406f 1584 cmd_sts = desc->cmd_sts;
4d64e718 1585
13d64285
LB		 1586 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1587 break;
1da177e4 1588
13d64285
LB		 1589 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1590 txq->tx_desc_count--;
1da177e4 1591
c9df406f
LB		 1592 addr = desc->buf_ptr;
1593 count = desc->byte_cnt;
13d64285
LB		 1594 skb = txq->tx_skb[tx_index];
1595 txq->tx_skb[tx_index] = NULL;
c8aaea25 1596
cc9754b3 1597 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1598 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1599 mp->dev->stats.tx_errors++;
c9df406f 1600 }
1da177e4 1601
13d64285
LB		 1602 /*
1603 * Drop mp->lock while we free the skb.
1604 */
c9df406f 1605 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1606
cc9754b3 1607 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1608 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1609 else
1610 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1611
c9df406f
LB		 1612 if (skb)
1613 dev_kfree_skb_irq(skb);
63c9e549 1614
13d64285 1615 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1616 }
13d64285 1617 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1618}
1da177e4 1619
13d64285 1620static void txq_deinit(struct tx_queue *txq)
c9df406f 1621{
13d64285 1622 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1623
13d64285
LB		 1624 txq_disable(txq);
1625 txq_reclaim(txq, 1);
1da177e4 1626
13d64285 1627 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1628
3d6b35bc
LB		 1629 if (txq->index == mp->txq_primary &&
1630 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1631 iounmap(txq->tx_desc_area);
c9df406f 1632 else
13d64285
LB		 1633 dma_free_coherent(NULL, txq->tx_desc_area_size,
1634 txq->tx_desc_area, txq->tx_desc_dma);
1635
1636 kfree(txq->tx_skb);
c9df406f 1637}
1da177e4 1638
1da177e4 1639
c9df406f 1640/* netdev ops and related ***************************************************/
fc32b0e2 1641static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1642{
13d64285
LB		 1643 u32 pscr_o;
1644 u32 pscr_n;
1da177e4 1645
13d64285 1646 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1647
c9df406f 1648 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1649 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1650 SET_GMII_SPEED_TO_1000 |
1651 SET_FULL_DUPLEX_MODE |
1652 MAX_RX_PACKET_MASK);
1da177e4 1653
fc32b0e2 1654 if (speed == SPEED_1000) {
13d64285
LB		 1655 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1656 } else {
fc32b0e2 1657 if (speed == SPEED_100)
13d64285
LB		 1658 pscr_n |= SET_MII_SPEED_TO_100;
1659 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1660 }
1da177e4 1661
fc32b0e2 1662 if (duplex == DUPLEX_FULL)
13d64285
LB		 1663 pscr_n |= SET_FULL_DUPLEX_MODE;
1664
1665 if (pscr_n != pscr_o) {
1666 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1667 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1668 else {
3d6b35bc
LB		 1669 int i;
1670
1671 for (i = 0; i < 8; i++)
1672 if (mp->txq_mask & (1 << i))
1673 txq_disable(mp->txq + i);
1674
13d64285
LB		 1675 pscr_o &= ~SERIAL_PORT_ENABLE;
1676 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1677 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1678 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
3d6b35bc
LB		 1679
1680 for (i = 0; i < 8; i++)
1681 if (mp->txq_mask & (1 << i))
1682 txq_enable(mp->txq + i);
c9df406f
LB		 1683 }
1684 }
1685}
84dd619e 1686
fc32b0e2 1687static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1688{
1689 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1690 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1691 u32 int_cause;
1692 u32 int_cause_ext;
ce4e2e45 1693
226bb6b7
LB		 1694 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1695 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1696 if (int_cause == 0)
1697 return IRQ_NONE;
1698
1699 int_cause_ext = 0;
cc9754b3 1700 if (int_cause & INT_EXT) {
13d64285 1701 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1702 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1703 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1704 }
1da177e4 1705
fc32b0e2 1706 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
bedfe324 1707 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
3d6b35bc 1708 int i;
13d64285 1709
bedfe324
LB		 1710 if (mp->phy_addr != -1) {
1711 struct ethtool_cmd cmd;
1712
1713 mii_ethtool_gset(&mp->mii, &cmd);
1714 update_pscr(mp, cmd.speed, cmd.duplex);
1715 }
1716
3d6b35bc
LB		 1717 for (i = 0; i < 8; i++)
1718 if (mp->txq_mask & (1 << i))
1719 txq_enable(mp->txq + i);
1720
c9df406f
LB		 1721 if (!netif_carrier_ok(dev)) {
1722 netif_carrier_on(dev);
3d6b35bc 1723 __txq_maybe_wake(mp->txq + mp->txq_primary);
c9df406f
LB		 1724 }
1725 } else if (netif_carrier_ok(dev)) {
1726 netif_stop_queue(dev);
1727 netif_carrier_off(dev);
1728 }
1729 }
1da177e4 1730
64da80a2
LB		 1731 /*
1732 * RxBuffer or RxError set for any of the 8 queues?
1733 */
e5371493 1734#ifdef MV643XX_ETH_NAPI
cc9754b3 1735 if (int_cause & INT_RX) {
13d64285 1736 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1737 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1738
c9df406f 1739 netif_rx_schedule(dev, &mp->napi);
84dd619e 1740 }
c9df406f 1741#else
64da80a2
LB		 1742 if (int_cause & INT_RX) {
1743 int i;
1744
1745 for (i = 7; i >= 0; i--)
1746 if (mp->rxq_mask & (1 << i))
1747 rxq_process(mp->rxq + i, INT_MAX);
1748 }
c9df406f 1749#endif
fc32b0e2 1750
3d6b35bc
LB		 1751 /*
1752 * TxBuffer or TxError set for any of the 8 queues?
1753 */
13d64285 1754 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1755 int i;
1756
1757 for (i = 0; i < 8; i++)
1758 if (mp->txq_mask & (1 << i))
1759 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1760
1761 /*
1762 * Enough space again in the primary TX queue for a
1763 * full packet?
1764 */
1765 spin_lock(&mp->lock);
1766 __txq_maybe_wake(mp->txq + mp->txq_primary);
1767 spin_unlock(&mp->lock);
226bb6b7 1768 }
3d6b35bc 1769
226bb6b7
LB		 1770 /*
1771 * Any TxEnd interrupts?
1772 */
1773 if (int_cause & INT_TX_END) {
1774 int i;
1775
1776 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1777
1778 spin_lock(&mp->lock);
226bb6b7
LB		 1779 for (i = 0; i < 8; i++) {
1780 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1781 u32 hw_desc_ptr;
1782 u32 expected_ptr;
1783
1784 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1785 continue;
1786
1787 hw_desc_ptr =
1788 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1789 expected_ptr = (u32)txq->tx_desc_dma +
1790 txq->tx_curr_desc * sizeof(struct tx_desc);
1791
1792 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1793 txq_enable(txq);
1794 }
8fa89bf5 1795 spin_unlock(&mp->lock);
13d64285 1796 }
1da177e4 1797
c9df406f 1798 return IRQ_HANDLED;
1da177e4
LT		 1799}
1800
e5371493 1801static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1802{
fc32b0e2 1803 unsigned int data;
1da177e4 1804
fc32b0e2
LB		 1805 smi_reg_read(mp, mp->phy_addr, 0, &data);
1806 data |= 0x8000;
1807 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1808
c9df406f
LB		 1809 do {
1810 udelay(1);
fc32b0e2
LB		 1811 smi_reg_read(mp, mp->phy_addr, 0, &data);
1812 } while (data & 0x8000);
1da177e4
LT		 1813}
1814
fc32b0e2 1815static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1816{
d0412d96 1817 u32 pscr;
8a578111 1818 int i;
1da177e4 1819
8a578111
LB		 1820 /*
1821 * Configure basic link parameters.
1822 */
1823 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1824 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1825 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1826 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1827 DISABLE_AUTO_NEG_SPEED_GMII |
1828 DISABLE_AUTO_NEG_FOR_DUPLEX |
1829 DO_NOT_FORCE_LINK_FAIL |
1830 SERIAL_PORT_CONTROL_RESERVED;
1831 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1832 pscr |= SERIAL_PORT_ENABLE;
1833 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1834
8a578111
LB		 1835 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1836
bedfe324
LB		 1837 /*
1838 * Perform PHY reset, if there is a PHY.
1839 */
1840 if (mp->phy_addr != -1) {
1841 struct ethtool_cmd cmd;
1842
1843 mv643xx_eth_get_settings(mp->dev, &cmd);
1844 phy_reset(mp);
1845 mv643xx_eth_set_settings(mp->dev, &cmd);
1846 }
1da177e4 1847
13d64285
LB		 1848 /*
1849 * Configure TX path and queues.
1850 */
89df5fdc 1851 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1852 for (i = 0; i < 8; i++) {
1853 struct tx_queue *txq = mp->txq + i;
1854 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
13d64285
LB		 1855 u32 addr;
1856
3d6b35bc
LB		 1857 if ((mp->txq_mask & (1 << i)) == 0)
1858 continue;
1859
13d64285
LB		 1860 addr = (u32)txq->tx_desc_dma;
1861 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1862 wrl(mp, off, addr);
89df5fdc
LB		 1863
1864 txq_set_rate(txq, 1000000000, 16777216);
1865 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1866 }
1867
fc32b0e2
LB		 1868 /*
1869 * Add configured unicast address to address filter table.
1870 */
1871 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1872
d9a073ea
LB		 1873 /*
1874 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1875 * frames to RX queue #0.
1876 */
8a578111 1877 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1878
376489a2
LB		 1879 /*
1880 * Treat BPDUs as normal multicasts, and disable partition mode.
1881 */
8a578111 1882 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1883
8a578111 1884 /*
64da80a2 1885 * Enable the receive queues.
8a578111 1886 */
64da80a2
LB		 1887 for (i = 0; i < 8; i++) {
1888 struct rx_queue *rxq = mp->rxq + i;
1889 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1890 u32 addr;
1da177e4 1891
64da80a2
LB		 1892 if ((mp->rxq_mask & (1 << i)) == 0)
1893 continue;
1894
8a578111
LB		 1895 addr = (u32)rxq->rx_desc_dma;
1896 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1897 wrl(mp, off, addr);
1da177e4 1898
8a578111
LB		 1899 rxq_enable(rxq);
1900 }
1da177e4
LT		 1901}
1902
ffd86bbe 1903static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1904{
c9df406f 1905 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1906 u32 val;
1da177e4 1907
773fc3ee
LB		 1908 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1909 if (mp->shared->extended_rx_coal_limit) {
1910 if (coal > 0xffff)
1911 coal = 0xffff;
1912 val &= ~0x023fff80;
1913 val |= (coal & 0x8000) << 10;
1914 val |= (coal & 0x7fff) << 7;
1915 } else {
1916 if (coal > 0x3fff)
1917 coal = 0x3fff;
1918 val &= ~0x003fff00;
1919 val |= (coal & 0x3fff) << 8;
1920 }
1921 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1922}
1923
ffd86bbe 1924static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1925{
c9df406f 1926 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1927
fc32b0e2
LB		 1928 if (coal > 0x3fff)
1929 coal = 0x3fff;
1930 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1931}
1932
c9df406f 1933static int mv643xx_eth_open(struct net_device *dev)
16e03018 1934{
e5371493 1935 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1936 int err;
64da80a2 1937 int i;
16e03018 1938
fc32b0e2
LB		 1939 wrl(mp, INT_CAUSE(mp->port_num), 0);
1940 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1941 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1942
fc32b0e2
LB		 1943 err = request_irq(dev->irq, mv643xx_eth_irq,
1944 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1945 dev->name, dev);
c9df406f 1946 if (err) {
fc32b0e2 1947 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1948 return -EAGAIN;
16e03018
DF		 1949 }
1950
fc32b0e2 1951 init_mac_tables(mp);
16e03018 1952
64da80a2
LB		 1953 for (i = 0; i < 8; i++) {
1954 if ((mp->rxq_mask & (1 << i)) == 0)
1955 continue;
1956
1957 err = rxq_init(mp, i);
1958 if (err) {
1959 while (--i >= 0)
1960 if (mp->rxq_mask & (1 << i))
1961 rxq_deinit(mp->rxq + i);
1962 goto out;
1963 }
1964
1965 rxq_refill(mp->rxq + i);
1966 }
8a578111 1967
3d6b35bc
LB		 1968 for (i = 0; i < 8; i++) {
1969 if ((mp->txq_mask & (1 << i)) == 0)
1970 continue;
1971
1972 err = txq_init(mp, i);
1973 if (err) {
1974 while (--i >= 0)
1975 if (mp->txq_mask & (1 << i))
1976 txq_deinit(mp->txq + i);
1977 goto out_free;
1978 }
1979 }
16e03018 1980
e5371493 1981#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1982 napi_enable(&mp->napi);
1983#endif
16e03018 1984
fc32b0e2 1985 port_start(mp);
16e03018 1986
ffd86bbe
LB		 1987 set_rx_coal(mp, 0);
1988 set_tx_coal(mp, 0);
16e03018 1989
fc32b0e2
LB		 1990 wrl(mp, INT_MASK_EXT(mp->port_num),
1991 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1992
226bb6b7 1993 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 1994
c9df406f
LB		 1995 return 0;
1996
13d64285 1997
fc32b0e2 1998out_free:
64da80a2
LB		 1999 for (i = 0; i < 8; i++)
2000 if (mp->rxq_mask & (1 << i))
2001 rxq_deinit(mp->rxq + i);
fc32b0e2 2002out:
c9df406f
LB		 2003 free_irq(dev->irq, dev);
2004
2005 return err;
16e03018
DF		 2006}
2007
e5371493 2008static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2009{
fc32b0e2 2010 unsigned int data;
64da80a2 2011 int i;
1da177e4 2012
64da80a2
LB		 2013 for (i = 0; i < 8; i++) {
2014 if (mp->rxq_mask & (1 << i))
2015 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 2016 if (mp->txq_mask & (1 << i))
2017 txq_disable(mp->txq + i);
64da80a2 2018 }
13d64285
LB		 2019 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2020 udelay(10);
1da177e4 2021
c9df406f 2022 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2023 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2024 data &= ~(SERIAL_PORT_ENABLE |
2025 DO_NOT_FORCE_LINK_FAIL |
2026 FORCE_LINK_PASS);
2027 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2028}
2029
c9df406f 2030static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2031{
e5371493 2032 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2033 int i;
1da177e4 2034
fc32b0e2
LB		 2035 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2036 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2037
e5371493 2038#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2039 napi_disable(&mp->napi);
2040#endif
2041 netif_carrier_off(dev);
2042 netif_stop_queue(dev);
1da177e4 2043
fc32b0e2
LB		 2044 free_irq(dev->irq, dev);
2045
cc9754b3 2046 port_reset(mp);
fc32b0e2 2047 mib_counters_update(mp);
1da177e4 2048
64da80a2
LB		 2049 for (i = 0; i < 8; i++) {
2050 if (mp->rxq_mask & (1 << i))
2051 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 2052 if (mp->txq_mask & (1 << i))
2053 txq_deinit(mp->txq + i);
64da80a2 2054 }
1da177e4 2055
c9df406f 2056 return 0;
1da177e4
LT		 2057}
2058
fc32b0e2 2059static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2060{
e5371493 2061 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2062
bedfe324
LB		 2063 if (mp->phy_addr != -1)
2064 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2065
2066 return -EOPNOTSUPP;
1da177e4
LT		 2067}
2068
c9df406f 2069static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2070{
89df5fdc
LB		 2071 struct mv643xx_eth_private *mp = netdev_priv(dev);
2072
fc32b0e2 2073 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2074 return -EINVAL;
1da177e4 2075
c9df406f 2076 dev->mtu = new_mtu;
89df5fdc
LB		 2077 tx_set_rate(mp, 1000000000, 16777216);
2078
c9df406f
LB		 2079 if (!netif_running(dev))
2080 return 0;
1da177e4 2081
c9df406f
LB		 2082 /*
2083 * Stop and then re-open the interface. This will allocate RX
2084 * skbs of the new MTU.
2085 * There is a possible danger that the open will not succeed,
fc32b0e2 2086 * due to memory being full.
c9df406f
LB		 2087 */
2088 mv643xx_eth_stop(dev);
2089 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2090 dev_printk(KERN_ERR, &dev->dev,
2091 "fatal error on re-opening device after "
2092 "MTU change\n");
c9df406f
LB		 2093 }
2094
2095 return 0;
1da177e4
LT		 2096}
2097
fc32b0e2 2098static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2099{
fc32b0e2 2100 struct mv643xx_eth_private *mp;
1da177e4 2101
fc32b0e2
LB		 2102 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2103 if (netif_running(mp->dev)) {
2104 netif_stop_queue(mp->dev);
c9df406f 2105
fc32b0e2
LB		 2106 port_reset(mp);
2107 port_start(mp);
c9df406f 2108
3d6b35bc 2109 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2110 }
c9df406f
LB		 2111}
2112
c9df406f 2113static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2114{
e5371493 2115 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2116
fc32b0e2 2117 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2118
c9df406f 2119 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2120}
2121
c9df406f 2122#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2123static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2124{
fc32b0e2 2125 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2126
fc32b0e2
LB		 2127 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2128 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2129
fc32b0e2 2130 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2131
f2ca60f2 2132 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2133}
c9df406f 2134#endif
9f8dd319 2135
fc32b0e2 2136static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2137{
e5371493 2138 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2139 int val;
2140
fc32b0e2
LB		 2141 smi_reg_read(mp, addr, reg, &val);
2142
c9df406f 2143 return val;
9f8dd319
DF		 2144}
2145
fc32b0e2 2146static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2147{
e5371493 2148 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2149 smi_reg_write(mp, addr, reg, val);
c9df406f 2150}
9f8dd319 2151
9f8dd319 2152
c9df406f 2153/* platform glue ************************************************************/
e5371493
LB		 2154static void
2155mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2156 struct mbus_dram_target_info *dram)
c9df406f 2157{
cc9754b3 2158 void __iomem *base = msp->base;
c9df406f
LB		 2159 u32 win_enable;
2160 u32 win_protect;
2161 int i;
9f8dd319 2162
c9df406f
LB		 2163 for (i = 0; i < 6; i++) {
2164 writel(0, base + WINDOW_BASE(i));
2165 writel(0, base + WINDOW_SIZE(i));
2166 if (i < 4)
2167 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2168 }
2169
c9df406f
LB		 2170 win_enable = 0x3f;
2171 win_protect = 0;
2172
2173 for (i = 0; i < dram->num_cs; i++) {
2174 struct mbus_dram_window *cs = dram->cs + i;
2175
2176 writel((cs->base & 0xffff0000) |
2177 (cs->mbus_attr << 8) |
2178 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2179 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2180
2181 win_enable &= ~(1 << i);
2182 win_protect |= 3 << (2 * i);
2183 }
2184
2185 writel(win_enable, base + WINDOW_BAR_ENABLE);
2186 msp->win_protect = win_protect;
9f8dd319
DF		 2187}
2188
773fc3ee
LB		 2189static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2190{
2191 /*
2192 * Check whether we have a 14-bit coal limit field in bits
2193 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2194 * SDMA config register.
2195 */
2196 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2197 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2198 msp->extended_rx_coal_limit = 1;
2199 else
2200 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2201
2202 /*
2203 * Check whether the TX rate control registers are in the
2204 * old or the new place.
2205 */
2206 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2207 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2208 msp->tx_bw_control_moved = 1;
2209 else
2210 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2211}
2212
c9df406f 2213static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2214{
e5371493 2215 static int mv643xx_eth_version_printed = 0;
c9df406f 2216 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2217 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2218 struct resource *res;
2219 int ret;
9f8dd319 2220
e5371493 2221 if (!mv643xx_eth_version_printed++)
c9df406f 2222 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 2223
c9df406f
LB		 2224 ret = -EINVAL;
2225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2226 if (res == NULL)
2227 goto out;
9f8dd319 2228
c9df406f
LB		 2229 ret = -ENOMEM;
2230 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2231 if (msp == NULL)
2232 goto out;
2233 memset(msp, 0, sizeof(*msp));
2234
cc9754b3
LB		 2235 msp->base = ioremap(res->start, res->end - res->start + 1);
2236 if (msp->base == NULL)
c9df406f
LB		 2237 goto out_free;
2238
2239 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2240
2241 /*
2242 * (Re-)program MBUS remapping windows if we are asked to.
2243 */
2244 if (pd != NULL && pd->dram != NULL)
2245 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2246
fc32b0e2
LB		 2247 /*
2248 * Detect hardware parameters.
2249 */
2250 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2251 infer_hw_params(msp);
fc32b0e2
LB		 2252
2253 platform_set_drvdata(pdev, msp);
2254
c9df406f
LB		 2255 return 0;
2256
2257out_free:
2258 kfree(msp);
2259out:
2260 return ret;
2261}
2262
2263static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2264{
e5371493 2265 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2266
cc9754b3 2267 iounmap(msp->base);
c9df406f
LB		 2268 kfree(msp);
2269
2270 return 0;
9f8dd319
DF		 2271}
2272
c9df406f 2273static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2274 .probe = mv643xx_eth_shared_probe,
2275 .remove = mv643xx_eth_shared_remove,
c9df406f 2276 .driver = {
fc32b0e2 2277 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2278 .owner = THIS_MODULE,
2279 },
2280};
2281
e5371493 2282static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2283{
c9df406f 2284 int addr_shift = 5 * mp->port_num;
fc32b0e2 2285 u32 data;
1da177e4 2286
fc32b0e2
LB		 2287 data = rdl(mp, PHY_ADDR);
2288 data &= ~(0x1f << addr_shift);
2289 data |= (phy_addr & 0x1f) << addr_shift;
2290 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2291}
2292
e5371493 2293static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2294{
fc32b0e2
LB		 2295 unsigned int data;
2296
2297 data = rdl(mp, PHY_ADDR);
2298
2299 return (data >> (5 * mp->port_num)) & 0x1f;
2300}
2301
2302static void set_params(struct mv643xx_eth_private *mp,
2303 struct mv643xx_eth_platform_data *pd)
2304{
2305 struct net_device *dev = mp->dev;
2306
2307 if (is_valid_ether_addr(pd->mac_addr))
2308 memcpy(dev->dev_addr, pd->mac_addr, 6);
2309 else
2310 uc_addr_get(mp, dev->dev_addr);
2311
2312 if (pd->phy_addr == -1) {
2313 mp->shared_smi = NULL;
2314 mp->phy_addr = -1;
2315 } else {
2316 mp->shared_smi = mp->shared;
2317 if (pd->shared_smi != NULL)
2318 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2319
2320 if (pd->force_phy_addr || pd->phy_addr) {
2321 mp->phy_addr = pd->phy_addr & 0x3f;
2322 phy_addr_set(mp, mp->phy_addr);
2323 } else {
2324 mp->phy_addr = phy_addr_get(mp);
2325 }
2326 }
1da177e4 2327
fc32b0e2
LB		 2328 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2329 if (pd->rx_queue_size)
2330 mp->default_rx_ring_size = pd->rx_queue_size;
2331 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2332 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2333
64da80a2
LB		 2334 if (pd->rx_queue_mask)
2335 mp->rxq_mask = pd->rx_queue_mask;
2336 else
2337 mp->rxq_mask = 0x01;
2338 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2339
fc32b0e2
LB		 2340 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2341 if (pd->tx_queue_size)
2342 mp->default_tx_ring_size = pd->tx_queue_size;
2343 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2344 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2345
2346 if (pd->tx_queue_mask)
2347 mp->txq_mask = pd->tx_queue_mask;
2348 else
2349 mp->txq_mask = 0x01;
2350 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2351}
2352
e5371493 2353static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2354{
fc32b0e2
LB		 2355 unsigned int data;
2356 unsigned int data2;
2357
2358 smi_reg_read(mp, mp->phy_addr, 0, &data);
2359 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2360
fc32b0e2
LB		 2361 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2362 if (((data ^ data2) & 0x1000) == 0)
2363 return -ENODEV;
1da177e4 2364
fc32b0e2 2365 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2366
c9df406f 2367 return 0;
1da177e4
LT		 2368}
2369
fc32b0e2
LB		 2370static int phy_init(struct mv643xx_eth_private *mp,
2371 struct mv643xx_eth_platform_data *pd)
c28a4f89 2372{
fc32b0e2
LB		 2373 struct ethtool_cmd cmd;
2374 int err;
c28a4f89 2375
fc32b0e2
LB		 2376 err = phy_detect(mp);
2377 if (err) {
2378 dev_printk(KERN_INFO, &mp->dev->dev,
2379 "no PHY detected at addr %d\n", mp->phy_addr);
2380 return err;
2381 }
2382 phy_reset(mp);
2383
2384 mp->mii.phy_id = mp->phy_addr;
2385 mp->mii.phy_id_mask = 0x3f;
2386 mp->mii.reg_num_mask = 0x1f;
2387 mp->mii.dev = mp->dev;
2388 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2389 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2390
fc32b0e2 2391 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2392
fc32b0e2
LB		 2393 memset(&cmd, 0, sizeof(cmd));
2394
2395 cmd.port = PORT_MII;
2396 cmd.transceiver = XCVR_INTERNAL;
2397 cmd.phy_address = mp->phy_addr;
2398 if (pd->speed == 0) {
2399 cmd.autoneg = AUTONEG_ENABLE;
2400 cmd.speed = SPEED_100;
2401 cmd.advertising = ADVERTISED_10baseT_Half |
2402 ADVERTISED_10baseT_Full |
2403 ADVERTISED_100baseT_Half |
2404 ADVERTISED_100baseT_Full;
c9df406f 2405 if (mp->mii.supports_gmii)
fc32b0e2 2406 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2407 } else {
fc32b0e2
LB		 2408 cmd.autoneg = AUTONEG_DISABLE;
2409 cmd.speed = pd->speed;
2410 cmd.duplex = pd->duplex;
c9df406f 2411 }
fc32b0e2
LB		 2412
2413 update_pscr(mp, cmd.speed, cmd.duplex);
2414 mv643xx_eth_set_settings(mp->dev, &cmd);
2415
2416 return 0;
c28a4f89
JC		 2417}
2418
c9df406f 2419static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2420{
c9df406f 2421 struct mv643xx_eth_platform_data *pd;
e5371493 2422 struct mv643xx_eth_private *mp;
c9df406f 2423 struct net_device *dev;
c9df406f 2424 struct resource *res;
c9df406f 2425 DECLARE_MAC_BUF(mac);
fc32b0e2 2426 int err;
1da177e4 2427
c9df406f
LB		 2428 pd = pdev->dev.platform_data;
2429 if (pd == NULL) {
fc32b0e2
LB		 2430 dev_printk(KERN_ERR, &pdev->dev,
2431 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2432 return -ENODEV;
2433 }
1da177e4 2434
c9df406f 2435 if (pd->shared == NULL) {
fc32b0e2
LB		 2436 dev_printk(KERN_ERR, &pdev->dev,
2437 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2438 return -ENODEV;
2439 }
8f518703 2440
e5371493 2441 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2442 if (!dev)
2443 return -ENOMEM;
1da177e4 2444
c9df406f 2445 mp = netdev_priv(dev);
fc32b0e2
LB		 2446 platform_set_drvdata(pdev, mp);
2447
2448 mp->shared = platform_get_drvdata(pd->shared);
2449 mp->port_num = pd->port_number;
2450
c9df406f 2451 mp->dev = dev;
e5371493
LB		 2452#ifdef MV643XX_ETH_NAPI
2453 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2454#endif
1da177e4 2455
fc32b0e2
LB		 2456 set_params(mp, pd);
2457
2458 spin_lock_init(&mp->lock);
2459
2460 mib_counters_clear(mp);
2461 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2462
bedfe324
LB		 2463 if (mp->phy_addr != -1) {
2464 err = phy_init(mp, pd);
2465 if (err)
2466 goto out;
2467
2468 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2469 } else {
2470 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2471 }
fc32b0e2
LB		 2472
2473
c9df406f
LB		 2474 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2475 BUG_ON(!res);
2476 dev->irq = res->start;
1da177e4 2477
fc32b0e2 2478 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2479 dev->open = mv643xx_eth_open;
2480 dev->stop = mv643xx_eth_stop;
c9df406f 2481 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2482 dev->set_mac_address = mv643xx_eth_set_mac_address;
2483 dev->do_ioctl = mv643xx_eth_ioctl;
2484 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2485 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2486#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2487 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2488#endif
c9df406f
LB		 2489 dev->watchdog_timeo = 2 * HZ;
2490 dev->base_addr = 0;
1da177e4 2491
e5371493 2492#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2493 /*
c9df406f
LB		 2494 * Zero copy can only work if we use Discovery II memory. Else, we will
2495 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2496 */
c9df406f 2497 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2498#endif
1da177e4 2499
fc32b0e2 2500 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2501
c9df406f 2502 if (mp->shared->win_protect)
fc32b0e2 2503 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2504
c9df406f
LB		 2505 err = register_netdev(dev);
2506 if (err)
2507 goto out;
1da177e4 2508
fc32b0e2
LB		 2509 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2510 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2511
c9df406f 2512 if (dev->features & NETIF_F_SG)
fc32b0e2 2513 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2514
c9df406f 2515 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2516 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2517
e5371493 2518#ifdef MV643XX_ETH_NAPI
fc32b0e2 2519 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2520#endif
1da177e4 2521
13d64285 2522 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2523 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2524
c9df406f 2525 return 0;
1da177e4 2526
c9df406f
LB		 2527out:
2528 free_netdev(dev);
1da177e4 2529
c9df406f 2530 return err;
1da177e4
LT		 2531}
2532
c9df406f 2533static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2534{
fc32b0e2 2535 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2536
fc32b0e2 2537 unregister_netdev(mp->dev);
c9df406f 2538 flush_scheduled_work();
fc32b0e2 2539 free_netdev(mp->dev);
c9df406f 2540
c9df406f 2541 platform_set_drvdata(pdev, NULL);
fc32b0e2 2542
c9df406f 2543 return 0;
1da177e4
LT		 2544}
2545
c9df406f 2546static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2547{
fc32b0e2 2548 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2549
c9df406f 2550 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2551 wrl(mp, INT_MASK(mp->port_num), 0);
2552 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2553
fc32b0e2
LB		 2554 if (netif_running(mp->dev))
2555 port_reset(mp);
d0412d96
JC		 2556}
2557
c9df406f 2558static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2559 .probe = mv643xx_eth_probe,
2560 .remove = mv643xx_eth_remove,
2561 .shutdown = mv643xx_eth_shutdown,
c9df406f 2562 .driver = {
fc32b0e2 2563 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2564 .owner = THIS_MODULE,
2565 },
2566};
2567
e5371493 2568static int __init mv643xx_eth_init_module(void)
d0412d96 2569{
c9df406f 2570 int rc;
d0412d96 2571
c9df406f
LB		 2572 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2573 if (!rc) {
2574 rc = platform_driver_register(&mv643xx_eth_driver);
2575 if (rc)
2576 platform_driver_unregister(&mv643xx_eth_shared_driver);
2577 }
fc32b0e2 2578
c9df406f 2579 return rc;
d0412d96 2580}
fc32b0e2 2581module_init(mv643xx_eth_init_module);
d0412d96 2582
e5371493 2583static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2584{
c9df406f
LB		 2585 platform_driver_unregister(&mv643xx_eth_driver);
2586 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2587}
e5371493 2588module_exit(mv643xx_eth_cleanup_module);
1da177e4 2589
45675bc6
LB		 2590MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2591 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2592MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2593MODULE_LICENSE("GPL");
c9df406f 2594MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2595MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Clone of davem's net-next-2.6 tree