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net: Fix data corruption when splicing from sockets.
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
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1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
37a6084f
LB		 81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 83 */
37a6084f 84#define PORT_CONFIG 0x0000
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 86#define PORT_CONFIG_EXT 0x0004
87#define MAC_ADDR_LOW 0x0014
88#define MAC_ADDR_HIGH 0x0018
89#define SDMA_CONFIG 0x001c
90#define PORT_SERIAL_CONTROL 0x003c
91#define PORT_STATUS 0x0044
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
81600eea 100#define LINK_UP 0x00000002
37a6084f
LB		 101#define TXQ_COMMAND 0x0048
102#define TXQ_FIX_PRIO_CONF 0x004c
103#define TX_BW_RATE 0x0050
104#define TX_BW_MTU 0x0058
105#define TX_BW_BURST 0x005c
106#define INT_CAUSE 0x0060
226bb6b7 107#define INT_TX_END 0x07f80000
befefe21 108#define INT_RX 0x000003fc
073a345c 109#define INT_EXT 0x00000002
37a6084f 110#define INT_CAUSE_EXT 0x0064
befefe21
LB		 111#define INT_EXT_LINK_PHY 0x00110000
112#define INT_EXT_TX 0x000000ff
37a6084f
LB		 113#define INT_MASK 0x0068
114#define INT_MASK_EXT 0x006c
115#define TX_FIFO_URGENT_THRESHOLD 0x0074
116#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117#define TX_BW_RATE_MOVED 0x00e0
118#define TX_BW_MTU_MOVED 0x00e8
119#define TX_BW_BURST_MOVED 0x00ec
120#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121#define RXQ_COMMAND 0x0280
122#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
126
127/*
128 * Misc per-port registers.
129 */
3cb4667c
LB		 130#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 134
2679a550
LB		 135
136/*
137 * SDMA configuration register.
138 */
cd4ccf76 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 140#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 141#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 143
144#if defined(__BIG_ENDIAN)
145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d
LB		 146 (RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 148#elif defined(__LITTLE_ENDIAN)
149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
10a9948d 150 (RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
10a9948d 153 TX_BURST_SIZE_16_64BIT)
fbd6a754
LB		 154#else
155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156#endif
157
2beff77b
LB		 158
159/*
160 * Port serial control register.
161 */
162#define SET_MII_SPEED_TO_100 (1 << 24)
163#define SET_GMII_SPEED_TO_1000 (1 << 23)
164#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171#define FORCE_LINK_PASS (1 << 1)
172#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 173
2b4a624d
LB		 174#define DEFAULT_RX_QUEUE_SIZE 128
175#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 176
fbd6a754 177
7ca72a3b
LB		 178/*
179 * RX/TX descriptors.
fbd6a754
LB		 180 */
181#if defined(__BIG_ENDIAN)
cc9754b3 182struct rx_desc {
fbd6a754
LB		 183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188};
189
cc9754b3 190struct tx_desc {
fbd6a754
LB		 191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196};
197#elif defined(__LITTLE_ENDIAN)
cc9754b3 198struct rx_desc {
fbd6a754
LB		 199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204};
205
cc9754b3 206struct tx_desc {
fbd6a754
LB		 207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212};
213#else
214#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215#endif
216
7ca72a3b 217/* RX & TX descriptor command */
cc9754b3 218#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 219
220/* RX & TX descriptor status */
cc9754b3 221#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 222
223/* RX descriptor status */
cc9754b3
LB		 224#define LAYER_4_CHECKSUM_OK 0x40000000
225#define RX_ENABLE_INTERRUPT 0x20000000
226#define RX_FIRST_DESC 0x08000000
227#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 228
229/* TX descriptor command */
cc9754b3
LB		 230#define TX_ENABLE_INTERRUPT 0x00800000
231#define GEN_CRC 0x00400000
232#define TX_FIRST_DESC 0x00200000
233#define TX_LAST_DESC 0x00100000
234#define ZERO_PADDING 0x00080000
235#define GEN_IP_V4_CHECKSUM 0x00040000
236#define GEN_TCP_UDP_CHECKSUM 0x00020000
237#define UDP_FRAME 0x00010000
e32b6617
LB		 238#define MAC_HDR_EXTRA_4_BYTES 0x00008000
239#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 240
cc9754b3 241#define TX_IHL_SHIFT 11
7ca72a3b
LB		 242
243
c9df406f 244/* global *******************************************************************/
e5371493 245struct mv643xx_eth_shared_private {
fc32b0e2
LB		 246 /*
247 * Ethernet controller base address.
248 */
cc9754b3 249 void __iomem *base;
c9df406f 250
fc0eb9f2
LB		 251 /*
252 * Points at the right SMI instance to use.
253 */
254 struct mv643xx_eth_shared_private *smi;
255
fc32b0e2 256 /*
ed94493f 257 * Provides access to local SMI interface.
fc32b0e2 258 */
298cf9be 259 struct mii_bus *smi_bus;
c9df406f 260
45c5d3bc
LB		 261 /*
262 * If we have access to the error interrupt pin (which is
263 * somewhat misnamed as it not only reflects internal errors
264 * but also reflects SMI completion), use that to wait for
265 * SMI access completion instead of polling the SMI busy bit.
266 */
267 int err_interrupt;
268 wait_queue_head_t smi_busy_wait;
269
fc32b0e2
LB		 270 /*
271 * Per-port MBUS window access register value.
272 */
c9df406f
LB		 273 u32 win_protect;
274
fc32b0e2
LB		 275 /*
276 * Hardware-specific parameters.
277 */
c9df406f 278 unsigned int t_clk;
773fc3ee 279 int extended_rx_coal_limit;
457b1d5a 280 int tx_bw_control;
c9df406f
LB		 281};
282
457b1d5a
LB		 283#define TX_BW_CONTROL_ABSENT 0
284#define TX_BW_CONTROL_OLD_LAYOUT 1
285#define TX_BW_CONTROL_NEW_LAYOUT 2
286
c9df406f
LB		 287
288/* per-port *****************************************************************/
e5371493 289struct mib_counters {
fbd6a754
LB		 290 u64 good_octets_received;
291 u32 bad_octets_received;
292 u32 internal_mac_transmit_err;
293 u32 good_frames_received;
294 u32 bad_frames_received;
295 u32 broadcast_frames_received;
296 u32 multicast_frames_received;
297 u32 frames_64_octets;
298 u32 frames_65_to_127_octets;
299 u32 frames_128_to_255_octets;
300 u32 frames_256_to_511_octets;
301 u32 frames_512_to_1023_octets;
302 u32 frames_1024_to_max_octets;
303 u64 good_octets_sent;
304 u32 good_frames_sent;
305 u32 excessive_collision;
306 u32 multicast_frames_sent;
307 u32 broadcast_frames_sent;
308 u32 unrec_mac_control_received;
309 u32 fc_sent;
310 u32 good_fc_received;
311 u32 bad_fc_received;
312 u32 undersize_received;
313 u32 fragments_received;
314 u32 oversize_received;
315 u32 jabber_received;
316 u32 mac_receive_error;
317 u32 bad_crc_event;
318 u32 collision;
319 u32 late_collision;
320};
321
8a578111 322struct rx_queue {
64da80a2
LB		 323 int index;
324
8a578111
LB		 325 int rx_ring_size;
326
327 int rx_desc_count;
328 int rx_curr_desc;
329 int rx_used_desc;
330
331 struct rx_desc *rx_desc_area;
332 dma_addr_t rx_desc_dma;
333 int rx_desc_area_size;
334 struct sk_buff **rx_skb;
8a578111
LB		 335};
336
13d64285 337struct tx_queue {
3d6b35bc
LB		 338 int index;
339
13d64285 340 int tx_ring_size;
fbd6a754 341
13d64285
LB		 342 int tx_desc_count;
343 int tx_curr_desc;
344 int tx_used_desc;
fbd6a754 345
5daffe94 346 struct tx_desc *tx_desc_area;
fbd6a754
LB		 347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
99ab08e0
LB		 349
350 struct sk_buff_head tx_skb;
8fd89211
LB		 351
352 unsigned long tx_packets;
353 unsigned long tx_bytes;
354 unsigned long tx_dropped;
13d64285
LB		 355};
356
357struct mv643xx_eth_private {
358 struct mv643xx_eth_shared_private *shared;
37a6084f 359 void __iomem *base;
fc32b0e2 360 int port_num;
13d64285 361
fc32b0e2 362 struct net_device *dev;
fbd6a754 363
ed94493f 364 struct phy_device *phy;
fbd6a754 365
4ff3495a
LB		 366 struct timer_list mib_counters_timer;
367 spinlock_t mib_counters_lock;
fc32b0e2 368 struct mib_counters mib_counters;
4ff3495a 369
fc32b0e2 370 struct work_struct tx_timeout_task;
8a578111 371
1fa38c58
LB		 372 struct napi_struct napi;
373 u8 work_link;
374 u8 work_tx;
375 u8 work_tx_end;
376 u8 work_rx;
377 u8 work_rx_refill;
378 u8 work_rx_oom;
379
2bcb4b0f
LB		 380 int skb_size;
381 struct sk_buff_head rx_recycle;
382
8a578111
LB		 383 /*
384 * RX state.
385 */
386 int default_rx_ring_size;
387 unsigned long rx_desc_sram_addr;
388 int rx_desc_sram_size;
f7981c1c 389 int rxq_count;
2257e05c 390 struct timer_list rx_oom;
64da80a2 391 struct rx_queue rxq[8];
13d64285
LB		 392
393 /*
394 * TX state.
395 */
396 int default_tx_ring_size;
397 unsigned long tx_desc_sram_addr;
398 int tx_desc_sram_size;
f7981c1c 399 int txq_count;
3d6b35bc 400 struct tx_queue txq[8];
fbd6a754 401};
1da177e4 402
fbd6a754 403
c9df406f 404/* port register accessors **************************************************/
e5371493 405static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 406{
cc9754b3 407 return readl(mp->shared->base + offset);
c9df406f 408}
fbd6a754 409
37a6084f
LB		 410static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
411{
412 return readl(mp->base + offset);
413}
414
e5371493 415static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 416{
cc9754b3 417 writel(data, mp->shared->base + offset);
c9df406f 418}
fbd6a754 419
37a6084f
LB		 420static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
421{
422 writel(data, mp->base + offset);
423}
424
fbd6a754 425
c9df406f 426/* rxq/txq helper functions *************************************************/
8a578111 427static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 428{
64da80a2 429 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 430}
fbd6a754 431
13d64285
LB		 432static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
433{
3d6b35bc 434 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 435}
436
8a578111 437static void rxq_enable(struct rx_queue *rxq)
c9df406f 438{
8a578111 439 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 440 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 441}
1da177e4 442
8a578111
LB		 443static void rxq_disable(struct rx_queue *rxq)
444{
445 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 446 u8 mask = 1 << rxq->index;
1da177e4 447
37a6084f
LB		 448 wrlp(mp, RXQ_COMMAND, mask << 8);
449 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 450 udelay(10);
c9df406f
LB		 451}
452
6b368f68
LB		 453static void txq_reset_hw_ptr(struct tx_queue *txq)
454{
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 456 u32 addr;
457
458 addr = (u32)txq->tx_desc_dma;
459 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 460 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 461}
462
13d64285 463static void txq_enable(struct tx_queue *txq)
1da177e4 464{
13d64285 465 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 466 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 467}
468
13d64285 469static void txq_disable(struct tx_queue *txq)
1da177e4 470{
13d64285 471 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 472 u8 mask = 1 << txq->index;
c9df406f 473
37a6084f
LB		 474 wrlp(mp, TXQ_COMMAND, mask << 8);
475 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 476 udelay(10);
477}
478
1fa38c58 479static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 480{
481 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 482 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 483
8fd89211
LB		 484 if (netif_tx_queue_stopped(nq)) {
485 __netif_tx_lock(nq, smp_processor_id());
486 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
487 netif_tx_wake_queue(nq);
488 __netif_tx_unlock(nq);
489 }
1da177e4
LT		 490}
491
c9df406f 492
1fa38c58 493/* rx napi ******************************************************************/
8a578111 494static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 495{
8a578111
LB		 496 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
497 struct net_device_stats *stats = &mp->dev->stats;
498 int rx;
1da177e4 499
8a578111 500 rx = 0;
9e1f3772 501 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 502 struct rx_desc *rx_desc;
96587661 503 unsigned int cmd_sts;
fc32b0e2 504 struct sk_buff *skb;
6b8f90c2 505 u16 byte_cnt;
ff561eef 506
8a578111 507 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 508
96587661 509 cmd_sts = rx_desc->cmd_sts;
2257e05c 510 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 511 break;
96587661 512 rmb();
1da177e4 513
8a578111
LB		 514 skb = rxq->rx_skb[rxq->rx_curr_desc];
515 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 516
9da78745
LB		 517 rxq->rx_curr_desc++;
518 if (rxq->rx_curr_desc == rxq->rx_ring_size)
519 rxq->rx_curr_desc = 0;
ff561eef 520
3a499481 521 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 522 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 523 rxq->rx_desc_count--;
524 rx++;
b1dd9ca1 525
1fa38c58
LB		 526 mp->work_rx_refill |= 1 << rxq->index;
527
6b8f90c2
LB		 528 byte_cnt = rx_desc->byte_cnt;
529
468d09f8
DF		 530 /*
531 * Update statistics.
fc32b0e2
LB		 532 *
533 * Note that the descriptor byte count includes 2 dummy
534 * bytes automatically inserted by the hardware at the
535 * start of the packet (which we don't count), and a 4
536 * byte CRC at the end of the packet (which we do count).
468d09f8 537 */
1da177e4 538 stats->rx_packets++;
6b8f90c2 539 stats->rx_bytes += byte_cnt - 2;
96587661 540
1da177e4 541 /*
fc32b0e2
LB		 542 * In case we received a packet without first / last bits
543 * on, or the error summary bit is set, the packet needs
544 * to be dropped.
1da177e4 545 */
f61e5547
LB		 546 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
547 != (RX_FIRST_DESC | RX_LAST_DESC))
548 goto err;
549
550 /*
551 * The -4 is for the CRC in the trailer of the
552 * received packet
553 */
554 skb_put(skb, byte_cnt - 2 - 4);
555
556 if (cmd_sts & LAYER_4_CHECKSUM_OK)
557 skb->ip_summed = CHECKSUM_UNNECESSARY;
558 skb->protocol = eth_type_trans(skb, mp->dev);
559 netif_receive_skb(skb);
560
561 continue;
562
563err:
564 stats->rx_dropped++;
565
566 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
567 (RX_FIRST_DESC | RX_LAST_DESC)) {
568 if (net_ratelimit())
569 dev_printk(KERN_ERR, &mp->dev->dev,
570 "received packet spanning "
571 "multiple descriptors\n");
1da177e4 572 }
f61e5547
LB		 573
574 if (cmd_sts & ERROR_SUMMARY)
575 stats->rx_errors++;
576
577 dev_kfree_skb(skb);
1da177e4 578 }
fc32b0e2 579
1fa38c58
LB		 580 if (rx < budget)
581 mp->work_rx &= ~(1 << rxq->index);
582
8a578111 583 return rx;
1da177e4
LT		 584}
585
1fa38c58 586static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 587{
1fa38c58 588 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 589 int refilled;
8a578111 590
1fa38c58
LB		 591 refilled = 0;
592 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
593 struct sk_buff *skb;
594 int unaligned;
595 int rx;
53771522 596 struct rx_desc *rx_desc;
d0412d96 597
2bcb4b0f
LB		 598 skb = __skb_dequeue(&mp->rx_recycle);
599 if (skb == NULL)
600 skb = dev_alloc_skb(mp->skb_size +
601 dma_get_cache_alignment() - 1);
602
1fa38c58
LB		 603 if (skb == NULL) {
604 mp->work_rx_oom |= 1 << rxq->index;
605 goto oom;
606 }
d0412d96 607
1fa38c58
LB		 608 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
609 if (unaligned)
610 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 611
1fa38c58
LB		 612 refilled++;
613 rxq->rx_desc_count++;
c9df406f 614
1fa38c58
LB		 615 rx = rxq->rx_used_desc++;
616 if (rxq->rx_used_desc == rxq->rx_ring_size)
617 rxq->rx_used_desc = 0;
2257e05c 618
53771522
LB		 619 rx_desc = rxq->rx_desc_area + rx;
620
621 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
622 mp->skb_size, DMA_FROM_DEVICE);
623 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 624 rxq->rx_skb[rx] = skb;
625 wmb();
53771522 626 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 627 wmb();
2257e05c 628
1fa38c58
LB		 629 /*
630 * The hardware automatically prepends 2 bytes of
631 * dummy data to each received packet, so that the
632 * IP header ends up 16-byte aligned.
633 */
634 skb_reserve(skb, 2);
635 }
636
637 if (refilled < budget)
638 mp->work_rx_refill &= ~(1 << rxq->index);
639
640oom:
641 return refilled;
d0412d96
JC		 642}
643
c9df406f
LB		 644
645/* tx ***********************************************************************/
c9df406f 646static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 647{
13d64285 648 int frag;
1da177e4 649
c9df406f 650 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 651 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
652 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 653 return 1;
1da177e4 654 }
13d64285 655
c9df406f
LB		 656 return 0;
657}
7303fde8 658
13d64285 659static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 660{
13d64285 661 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 662 int frag;
1da177e4 663
13d64285
LB		 664 for (frag = 0; frag < nr_frags; frag++) {
665 skb_frag_t *this_frag;
666 int tx_index;
667 struct tx_desc *desc;
668
669 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 670 tx_index = txq->tx_curr_desc++;
671 if (txq->tx_curr_desc == txq->tx_ring_size)
672 txq->tx_curr_desc = 0;
13d64285
LB		 673 desc = &txq->tx_desc_area[tx_index];
674
675 /*
676 * The last fragment will generate an interrupt
677 * which will free the skb on TX completion.
678 */
679 if (frag == nr_frags - 1) {
680 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
681 ZERO_PADDING | TX_LAST_DESC |
682 TX_ENABLE_INTERRUPT;
13d64285
LB		 683 } else {
684 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 685 }
686
c9df406f
LB		 687 desc->l4i_chk = 0;
688 desc->byte_cnt = this_frag->size;
689 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
690 this_frag->page_offset,
691 this_frag->size,
692 DMA_TO_DEVICE);
693 }
1da177e4
LT		 694}
695
c9df406f
LB		 696static inline __be16 sum16_as_be(__sum16 sum)
697{
698 return (__force __be16)sum;
699}
1da177e4 700
4df89bd5 701static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 702{
8fa89bf5 703 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 704 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 705 int tx_index;
cc9754b3 706 struct tx_desc *desc;
c9df406f 707 u32 cmd_sts;
4df89bd5 708 u16 l4i_chk;
c9df406f 709 int length;
1da177e4 710
cc9754b3 711 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 712 l4i_chk = 0;
c9df406f
LB		 713
714 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 715 int tag_bytes;
e32b6617
LB		 716
717 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
718 skb->protocol != htons(ETH_P_8021Q));
c9df406f 719
4df89bd5
LB		 720 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
721 if (unlikely(tag_bytes & ~12)) {
722 if (skb_checksum_help(skb) == 0)
723 goto no_csum;
724 kfree_skb(skb);
725 return 1;
726 }
c9df406f 727
4df89bd5 728 if (tag_bytes & 4)
e32b6617 729 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 730 if (tag_bytes & 8)
e32b6617 731 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 732
733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 GEN_IP_V4_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 736
c9df406f
LB		 737 switch (ip_hdr(skb)->protocol) {
738 case IPPROTO_UDP:
cc9754b3 739 cmd_sts |= UDP_FRAME;
4df89bd5 740 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 741 break;
742 case IPPROTO_TCP:
4df89bd5 743 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 744 break;
745 default:
746 BUG();
747 }
748 } else {
4df89bd5 749no_csum:
c9df406f 750 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 751 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 752 }
753
66823b92
LB		 754 tx_index = txq->tx_curr_desc++;
755 if (txq->tx_curr_desc == txq->tx_ring_size)
756 txq->tx_curr_desc = 0;
4df89bd5
LB		 757 desc = &txq->tx_desc_area[tx_index];
758
759 if (nr_frags) {
760 txq_submit_frag_skb(txq, skb);
761 length = skb_headlen(skb);
762 } else {
763 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
764 length = skb->len;
765 }
766
767 desc->l4i_chk = l4i_chk;
768 desc->byte_cnt = length;
769 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
770
99ab08e0
LB		 771 __skb_queue_tail(&txq->tx_skb, skb);
772
c9df406f
LB		 773 /* ensure all other descriptors are written before first cmd_sts */
774 wmb();
775 desc->cmd_sts = cmd_sts;
776
1fa38c58
LB		 777 /* clear TX_END status */
778 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 779
c9df406f
LB		 780 /* ensure all descriptors are written before poking hardware */
781 wmb();
13d64285 782 txq_enable(txq);
c9df406f 783
13d64285 784 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 785
786 return 0;
1da177e4 787}
1da177e4 788
fc32b0e2 789static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 790{
e5371493 791 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 792 int queue;
13d64285 793 struct tx_queue *txq;
e5ef1de1 794 struct netdev_queue *nq;
afdb57a2 795
8fd89211
LB		 796 queue = skb_get_queue_mapping(skb);
797 txq = mp->txq + queue;
798 nq = netdev_get_tx_queue(dev, queue);
799
c9df406f 800 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 801 txq->tx_dropped++;
fc32b0e2
LB		 802 dev_printk(KERN_DEBUG, &dev->dev,
803 "failed to linearize skb with tiny "
804 "unaligned fragment\n");
c9df406f
LB		 805 return NETDEV_TX_BUSY;
806 }
807
17cd0a59 808 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 809 if (net_ratelimit())
810 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 811 kfree_skb(skb);
812 return NETDEV_TX_OK;
c9df406f
LB		 813 }
814
4df89bd5
LB		 815 if (!txq_submit_skb(txq, skb)) {
816 int entries_left;
817
818 txq->tx_bytes += skb->len;
819 txq->tx_packets++;
820 dev->trans_start = jiffies;
c9df406f 821
4df89bd5
LB		 822 entries_left = txq->tx_ring_size - txq->tx_desc_count;
823 if (entries_left < MAX_SKB_FRAGS + 1)
824 netif_tx_stop_queue(nq);
825 }
c9df406f 826
c9df406f 827 return NETDEV_TX_OK;
1da177e4
LT		 828}
829
c9df406f 830
1fa38c58
LB		 831/* tx napi ******************************************************************/
832static void txq_kick(struct tx_queue *txq)
833{
834 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 835 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 836 u32 hw_desc_ptr;
837 u32 expected_ptr;
838
8fd89211 839 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 840
37a6084f 841 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 842 goto out;
843
37a6084f 844 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 845 expected_ptr = (u32)txq->tx_desc_dma +
846 txq->tx_curr_desc * sizeof(struct tx_desc);
847
848 if (hw_desc_ptr != expected_ptr)
849 txq_enable(txq);
850
851out:
8fd89211 852 __netif_tx_unlock(nq);
1fa38c58
LB		 853
854 mp->work_tx_end &= ~(1 << txq->index);
855}
856
857static int txq_reclaim(struct tx_queue *txq, int budget, int force)
858{
859 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 860 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 861 int reclaimed;
862
8fd89211 863 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 864
865 reclaimed = 0;
866 while (reclaimed < budget && txq->tx_desc_count > 0) {
867 int tx_index;
868 struct tx_desc *desc;
869 u32 cmd_sts;
870 struct sk_buff *skb;
1fa38c58
LB		 871
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
875
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
877 if (!force)
878 break;
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
880 }
881
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
885
886 reclaimed++;
887 txq->tx_desc_count--;
888
99ab08e0
LB		 889 skb = NULL;
890 if (cmd_sts & TX_LAST_DESC)
891 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 892
893 if (cmd_sts & ERROR_SUMMARY) {
894 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
895 mp->dev->stats.tx_errors++;
896 }
897
a418950c
LB		 898 if (cmd_sts & TX_FIRST_DESC) {
899 dma_unmap_single(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
901 } else {
902 dma_unmap_page(NULL, desc->buf_ptr,
903 desc->byte_cnt, DMA_TO_DEVICE);
904 }
1fa38c58 905
2bcb4b0f
LB		 906 if (skb != NULL) {
907 if (skb_queue_len(&mp->rx_recycle) <
908 mp->default_rx_ring_size &&
11b4aa03
LB		 909 skb_recycle_check(skb, mp->skb_size +
910 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 911 __skb_queue_head(&mp->rx_recycle, skb);
912 else
913 dev_kfree_skb(skb);
914 }
1fa38c58
LB		 915 }
916
8fd89211
LB		 917 __netif_tx_unlock(nq);
918
1fa38c58
LB		 919 if (reclaimed < budget)
920 mp->work_tx &= ~(1 << txq->index);
921
1fa38c58
LB		 922 return reclaimed;
923}
924
925
89df5fdc
LB		 926/* tx rate control **********************************************************/
927/*
928 * Set total maximum TX rate (shared by all TX queues for this port)
929 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
930 */
931static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
932{
933 int token_rate;
934 int mtu;
935 int bucket_size;
936
937 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
938 if (token_rate > 1023)
939 token_rate = 1023;
940
941 mtu = (mp->dev->mtu + 255) >> 8;
942 if (mtu > 63)
943 mtu = 63;
944
945 bucket_size = (burst + 255) >> 8;
946 if (bucket_size > 65535)
947 bucket_size = 65535;
948
457b1d5a
LB		 949 switch (mp->shared->tx_bw_control) {
950 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 951 wrlp(mp, TX_BW_RATE, token_rate);
952 wrlp(mp, TX_BW_MTU, mtu);
953 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 954 break;
955 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 956 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
957 wrlp(mp, TX_BW_MTU_MOVED, mtu);
958 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 959 break;
1e881592 960 }
89df5fdc
LB		 961}
962
963static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
964{
965 struct mv643xx_eth_private *mp = txq_to_mp(txq);
966 int token_rate;
967 int bucket_size;
968
969 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
970 if (token_rate > 1023)
971 token_rate = 1023;
972
973 bucket_size = (burst + 255) >> 8;
974 if (bucket_size > 65535)
975 bucket_size = 65535;
976
37a6084f
LB		 977 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
978 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 979}
980
981static void txq_set_fixed_prio_mode(struct tx_queue *txq)
982{
983 struct mv643xx_eth_private *mp = txq_to_mp(txq);
984 int off;
985 u32 val;
986
987 /*
988 * Turn on fixed priority mode.
989 */
457b1d5a
LB		 990 off = 0;
991 switch (mp->shared->tx_bw_control) {
992 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 993 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 994 break;
995 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 996 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 997 break;
998 }
89df5fdc 999
457b1d5a 1000 if (off) {
37a6084f 1001 val = rdlp(mp, off);
457b1d5a 1002 val |= 1 << txq->index;
37a6084f 1003 wrlp(mp, off, val);
457b1d5a 1004 }
89df5fdc
LB		 1005}
1006
1007static void txq_set_wrr(struct tx_queue *txq, int weight)
1008{
1009 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1010 int off;
1011 u32 val;
1012
1013 /*
1014 * Turn off fixed priority mode.
1015 */
457b1d5a
LB		 1016 off = 0;
1017 switch (mp->shared->tx_bw_control) {
1018 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1019 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1020 break;
1021 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1022 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1023 break;
1024 }
89df5fdc 1025
457b1d5a 1026 if (off) {
37a6084f 1027 val = rdlp(mp, off);
457b1d5a 1028 val &= ~(1 << txq->index);
37a6084f 1029 wrlp(mp, off, val);
89df5fdc 1030
457b1d5a
LB		 1031 /*
1032 * Configure WRR weight for this queue.
1033 */
89df5fdc 1034
37a6084f 1035 val = rdlp(mp, off);
457b1d5a 1036 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1037 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1038 }
89df5fdc
LB		 1039}
1040
1041
c9df406f 1042/* mii management interface *************************************************/
45c5d3bc
LB		 1043static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1044{
1045 struct mv643xx_eth_shared_private *msp = dev_id;
1046
1047 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1048 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1049 wake_up(&msp->smi_busy_wait);
1050 return IRQ_HANDLED;
1051 }
1052
1053 return IRQ_NONE;
1054}
c9df406f 1055
45c5d3bc 1056static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1057{
45c5d3bc
LB		 1058 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1059}
1da177e4 1060
45c5d3bc
LB		 1061static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1062{
1063 if (msp->err_interrupt == NO_IRQ) {
1064 int i;
c9df406f 1065
45c5d3bc
LB		 1066 for (i = 0; !smi_is_done(msp); i++) {
1067 if (i == 10)
1068 return -ETIMEDOUT;
1069 msleep(10);
c9df406f 1070 }
45c5d3bc
LB		 1071
1072 return 0;
1073 }
1074
ee04448d
LB		 1075 if (!smi_is_done(msp)) {
1076 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1077 msecs_to_jiffies(100));
1078 if (!smi_is_done(msp))
1079 return -ETIMEDOUT;
1080 }
45c5d3bc
LB		 1081
1082 return 0;
1083}
1084
ed94493f 1085static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1086{
ed94493f 1087 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1088 void __iomem *smi_reg = msp->base + SMI_REG;
1089 int ret;
1090
45c5d3bc 1091 if (smi_wait_ready(msp)) {
10a9948d 1092 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1093 return -ETIMEDOUT;
1da177e4
LT		 1094 }
1095
fc32b0e2 1096 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1097
45c5d3bc 1098 if (smi_wait_ready(msp)) {
10a9948d 1099 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1100 return -ETIMEDOUT;
45c5d3bc
LB		 1101 }
1102
1103 ret = readl(smi_reg);
1104 if (!(ret & SMI_READ_VALID)) {
10a9948d 1105 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1106 return -ENODEV;
c9df406f
LB		 1107 }
1108
ed94493f 1109 return ret & 0xffff;
1da177e4
LT		 1110}
1111
ed94493f 1112static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1113{
ed94493f 1114 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1115 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1116
45c5d3bc 1117 if (smi_wait_ready(msp)) {
10a9948d 1118 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1119 return -ETIMEDOUT;
1da177e4
LT		 1120 }
1121
fc32b0e2 1122 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1123 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1124
ed94493f 1125 if (smi_wait_ready(msp)) {
10a9948d 1126 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1127 return -ETIMEDOUT;
1128 }
45c5d3bc
LB		 1129
1130 return 0;
c9df406f 1131}
1da177e4 1132
c9df406f 1133
8fd89211
LB		 1134/* statistics ***************************************************************/
1135static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1136{
1137 struct mv643xx_eth_private *mp = netdev_priv(dev);
1138 struct net_device_stats *stats = &dev->stats;
1139 unsigned long tx_packets = 0;
1140 unsigned long tx_bytes = 0;
1141 unsigned long tx_dropped = 0;
1142 int i;
1143
1144 for (i = 0; i < mp->txq_count; i++) {
1145 struct tx_queue *txq = mp->txq + i;
1146
1147 tx_packets += txq->tx_packets;
1148 tx_bytes += txq->tx_bytes;
1149 tx_dropped += txq->tx_dropped;
1150 }
1151
1152 stats->tx_packets = tx_packets;
1153 stats->tx_bytes = tx_bytes;
1154 stats->tx_dropped = tx_dropped;
1155
1156 return stats;
1157}
1158
fc32b0e2 1159static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1160{
fc32b0e2 1161 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1162}
1163
fc32b0e2 1164static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1165{
fc32b0e2
LB		 1166 int i;
1167
1168 for (i = 0; i < 0x80; i += 4)
1169 mib_read(mp, i);
c9df406f 1170}
d0412d96 1171
fc32b0e2 1172static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1173{
e5371493 1174 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1175
4ff3495a 1176 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1177 p->good_octets_received += mib_read(mp, 0x00);
1178 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1179 p->bad_octets_received += mib_read(mp, 0x08);
1180 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1181 p->good_frames_received += mib_read(mp, 0x10);
1182 p->bad_frames_received += mib_read(mp, 0x14);
1183 p->broadcast_frames_received += mib_read(mp, 0x18);
1184 p->multicast_frames_received += mib_read(mp, 0x1c);
1185 p->frames_64_octets += mib_read(mp, 0x20);
1186 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1187 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1188 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1189 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1190 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1191 p->good_octets_sent += mib_read(mp, 0x38);
1192 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1193 p->good_frames_sent += mib_read(mp, 0x40);
1194 p->excessive_collision += mib_read(mp, 0x44);
1195 p->multicast_frames_sent += mib_read(mp, 0x48);
1196 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1197 p->unrec_mac_control_received += mib_read(mp, 0x50);
1198 p->fc_sent += mib_read(mp, 0x54);
1199 p->good_fc_received += mib_read(mp, 0x58);
1200 p->bad_fc_received += mib_read(mp, 0x5c);
1201 p->undersize_received += mib_read(mp, 0x60);
1202 p->fragments_received += mib_read(mp, 0x64);
1203 p->oversize_received += mib_read(mp, 0x68);
1204 p->jabber_received += mib_read(mp, 0x6c);
1205 p->mac_receive_error += mib_read(mp, 0x70);
1206 p->bad_crc_event += mib_read(mp, 0x74);
1207 p->collision += mib_read(mp, 0x78);
1208 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1209 spin_unlock(&mp->mib_counters_lock);
1210
1211 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1212}
1213
1214static void mib_counters_timer_wrapper(unsigned long _mp)
1215{
1216 struct mv643xx_eth_private *mp = (void *)_mp;
1217
1218 mib_counters_update(mp);
d0412d96
JC		 1219}
1220
c9df406f
LB		 1221
1222/* ethtool ******************************************************************/
e5371493 1223struct mv643xx_eth_stats {
c9df406f
LB		 1224 char stat_string[ETH_GSTRING_LEN];
1225 int sizeof_stat;
16820054
LB		 1226 int netdev_off;
1227 int mp_off;
c9df406f
LB		 1228};
1229
16820054
LB		 1230#define SSTAT(m) \
1231 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1232 offsetof(struct net_device, stats.m), -1 }
1233
1234#define MIBSTAT(m) \
1235 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1236 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1237
1238static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1239 SSTAT(rx_packets),
1240 SSTAT(tx_packets),
1241 SSTAT(rx_bytes),
1242 SSTAT(tx_bytes),
1243 SSTAT(rx_errors),
1244 SSTAT(tx_errors),
1245 SSTAT(rx_dropped),
1246 SSTAT(tx_dropped),
1247 MIBSTAT(good_octets_received),
1248 MIBSTAT(bad_octets_received),
1249 MIBSTAT(internal_mac_transmit_err),
1250 MIBSTAT(good_frames_received),
1251 MIBSTAT(bad_frames_received),
1252 MIBSTAT(broadcast_frames_received),
1253 MIBSTAT(multicast_frames_received),
1254 MIBSTAT(frames_64_octets),
1255 MIBSTAT(frames_65_to_127_octets),
1256 MIBSTAT(frames_128_to_255_octets),
1257 MIBSTAT(frames_256_to_511_octets),
1258 MIBSTAT(frames_512_to_1023_octets),
1259 MIBSTAT(frames_1024_to_max_octets),
1260 MIBSTAT(good_octets_sent),
1261 MIBSTAT(good_frames_sent),
1262 MIBSTAT(excessive_collision),
1263 MIBSTAT(multicast_frames_sent),
1264 MIBSTAT(broadcast_frames_sent),
1265 MIBSTAT(unrec_mac_control_received),
1266 MIBSTAT(fc_sent),
1267 MIBSTAT(good_fc_received),
1268 MIBSTAT(bad_fc_received),
1269 MIBSTAT(undersize_received),
1270 MIBSTAT(fragments_received),
1271 MIBSTAT(oversize_received),
1272 MIBSTAT(jabber_received),
1273 MIBSTAT(mac_receive_error),
1274 MIBSTAT(bad_crc_event),
1275 MIBSTAT(collision),
1276 MIBSTAT(late_collision),
c9df406f
LB		 1277};
1278
10a9948d
LB		 1279static int
1280mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1281{
e5371493 1282 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1283 int err;
1284
ed94493f
LB		 1285 err = phy_read_status(mp->phy);
1286 if (err == 0)
1287 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1288
fc32b0e2
LB		 1289 /*
1290 * The MAC does not support 1000baseT_Half.
1291 */
d0412d96
JC		 1292 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1293 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1294
1295 return err;
1296}
1297
10a9948d
LB		 1298static int
1299mv643xx_eth_get_settings_phyless(struct net_device *dev,
1300 struct ethtool_cmd *cmd)
bedfe324 1301{
81600eea
LB		 1302 struct mv643xx_eth_private *mp = netdev_priv(dev);
1303 u32 port_status;
1304
37a6084f 1305 port_status = rdlp(mp, PORT_STATUS);
81600eea 1306
bedfe324
LB		 1307 cmd->supported = SUPPORTED_MII;
1308 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1309 switch (port_status & PORT_SPEED_MASK) {
1310 case PORT_SPEED_10:
1311 cmd->speed = SPEED_10;
1312 break;
1313 case PORT_SPEED_100:
1314 cmd->speed = SPEED_100;
1315 break;
1316 case PORT_SPEED_1000:
1317 cmd->speed = SPEED_1000;
1318 break;
1319 default:
1320 cmd->speed = -1;
1321 break;
1322 }
1323 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1324 cmd->port = PORT_MII;
1325 cmd->phy_address = 0;
1326 cmd->transceiver = XCVR_INTERNAL;
1327 cmd->autoneg = AUTONEG_DISABLE;
1328 cmd->maxtxpkt = 1;
1329 cmd->maxrxpkt = 1;
1330
1331 return 0;
1332}
1333
10a9948d
LB		 1334static int
1335mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1336{
e5371493 1337 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1338
fc32b0e2
LB		 1339 /*
1340 * The MAC does not support 1000baseT_Half.
1341 */
1342 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1343
ed94493f 1344 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1345}
1da177e4 1346
10a9948d
LB		 1347static int
1348mv643xx_eth_set_settings_phyless(struct net_device *dev,
1349 struct ethtool_cmd *cmd)
bedfe324
LB		 1350{
1351 return -EINVAL;
1352}
1353
fc32b0e2
LB		 1354static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1355 struct ethtool_drvinfo *drvinfo)
c9df406f 1356{
e5371493
LB		 1357 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1358 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1359 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1360 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1361 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1362}
1da177e4 1363
fc32b0e2 1364static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1365{
e5371493 1366 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1367
ed94493f 1368 return genphy_restart_aneg(mp->phy);
c9df406f 1369}
1da177e4 1370
bedfe324
LB		 1371static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1372{
1373 return -EINVAL;
1374}
1375
c9df406f
LB		 1376static u32 mv643xx_eth_get_link(struct net_device *dev)
1377{
ed94493f 1378 return !!netif_carrier_ok(dev);
bedfe324
LB		 1379}
1380
fc32b0e2
LB		 1381static void mv643xx_eth_get_strings(struct net_device *dev,
1382 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1383{
1384 int i;
1da177e4 1385
fc32b0e2
LB		 1386 if (stringset == ETH_SS_STATS) {
1387 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1388 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1389 mv643xx_eth_stats[i].stat_string,
e5371493 1390 ETH_GSTRING_LEN);
c9df406f 1391 }
c9df406f
LB		 1392 }
1393}
1da177e4 1394
fc32b0e2
LB		 1395static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1396 struct ethtool_stats *stats,
1397 uint64_t *data)
c9df406f 1398{
b9873841 1399 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1400 int i;
1da177e4 1401
8fd89211 1402 mv643xx_eth_get_stats(dev);
fc32b0e2 1403 mib_counters_update(mp);
1da177e4 1404
16820054
LB		 1405 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1406 const struct mv643xx_eth_stats *stat;
1407 void *p;
1408
1409 stat = mv643xx_eth_stats + i;
1410
1411 if (stat->netdev_off >= 0)
1412 p = ((void *)mp->dev) + stat->netdev_off;
1413 else
1414 p = ((void *)mp) + stat->mp_off;
1415
1416 data[i] = (stat->sizeof_stat == 8) ?
1417 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1418 }
c9df406f 1419}
1da177e4 1420
fc32b0e2 1421static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1422{
fc32b0e2 1423 if (sset == ETH_SS_STATS)
16820054 1424 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1425
1426 return -EOPNOTSUPP;
c9df406f 1427}
1da177e4 1428
e5371493 1429static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1430 .get_settings = mv643xx_eth_get_settings,
1431 .set_settings = mv643xx_eth_set_settings,
1432 .get_drvinfo = mv643xx_eth_get_drvinfo,
1433 .nway_reset = mv643xx_eth_nway_reset,
1434 .get_link = mv643xx_eth_get_link,
c9df406f 1435 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1436 .get_strings = mv643xx_eth_get_strings,
1437 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1438 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1439};
1da177e4 1440
bedfe324
LB		 1441static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1442 .get_settings = mv643xx_eth_get_settings_phyless,
1443 .set_settings = mv643xx_eth_set_settings_phyless,
1444 .get_drvinfo = mv643xx_eth_get_drvinfo,
1445 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1446 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1447 .set_sg = ethtool_op_set_sg,
1448 .get_strings = mv643xx_eth_get_strings,
1449 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1450 .get_sset_count = mv643xx_eth_get_sset_count,
1451};
1452
bea3348e 1453
c9df406f 1454/* address handling *********************************************************/
5daffe94 1455static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1456{
66e63ffb
LB		 1457 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1458 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1459
5daffe94
LB		 1460 addr[0] = (mac_h >> 24) & 0xff;
1461 addr[1] = (mac_h >> 16) & 0xff;
1462 addr[2] = (mac_h >> 8) & 0xff;
1463 addr[3] = mac_h & 0xff;
1464 addr[4] = (mac_l >> 8) & 0xff;
1465 addr[5] = mac_l & 0xff;
c9df406f 1466}
1da177e4 1467
66e63ffb 1468static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1469{
66e63ffb
LB		 1470 wrlp(mp, MAC_ADDR_HIGH,
1471 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1472 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1473}
d0412d96 1474
66e63ffb 1475static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1476{
66e63ffb
LB		 1477 struct dev_addr_list *uc_ptr;
1478 u32 nibbles;
1da177e4 1479
66e63ffb
LB		 1480 if (dev->flags & IFF_PROMISC)
1481 return 0;
1da177e4 1482
66e63ffb
LB		 1483 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1484 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1485 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1486 return 0;
1487 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1488 return 0;
ff561eef 1489
66e63ffb
LB		 1490 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1491 }
1da177e4 1492
66e63ffb 1493 return nibbles;
1da177e4
LT		 1494}
1495
66e63ffb 1496static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1497{
e5371493 1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1499 u32 port_config;
1500 u32 nibbles;
1501 int i;
1da177e4 1502
cc9754b3 1503 uc_addr_set(mp, dev->dev_addr);
1da177e4 1504
66e63ffb
LB		 1505 port_config = rdlp(mp, PORT_CONFIG);
1506 nibbles = uc_addr_filter_mask(dev);
1507 if (!nibbles) {
1508 port_config |= UNICAST_PROMISCUOUS_MODE;
1509 wrlp(mp, PORT_CONFIG, port_config);
1510 return;
1511 }
1512
1513 for (i = 0; i < 16; i += 4) {
1514 int off = UNICAST_TABLE(mp->port_num) + i;
1515 u32 v;
1516
1517 v = 0;
1518 if (nibbles & 1)
1519 v |= 0x00000001;
1520 if (nibbles & 2)
1521 v |= 0x00000100;
1522 if (nibbles & 4)
1523 v |= 0x00010000;
1524 if (nibbles & 8)
1525 v |= 0x01000000;
1526 nibbles >>= 4;
1527
1528 wrl(mp, off, v);
1529 }
1530
1531 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1532 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1533}
1534
69876569
LB		 1535static int addr_crc(unsigned char *addr)
1536{
1537 int crc = 0;
1538 int i;
1539
1540 for (i = 0; i < 6; i++) {
1541 int j;
1542
1543 crc = (crc ^ addr[i]) << 8;
1544 for (j = 7; j >= 0; j--) {
1545 if (crc & (0x100 << j))
1546 crc ^= 0x107 << j;
1547 }
1548 }
1549
1550 return crc;
1551}
1552
66e63ffb 1553static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1554{
fc32b0e2 1555 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1556 u32 *mc_spec;
1557 u32 *mc_other;
fc32b0e2
LB		 1558 struct dev_addr_list *addr;
1559 int i;
c8aaea25 1560
fc32b0e2 1561 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1562 int port_num;
1563 u32 accept;
1564 int i;
c8aaea25 1565
66e63ffb
LB		 1566oom:
1567 port_num = mp->port_num;
1568 accept = 0x01010101;
fc32b0e2
LB		 1569 for (i = 0; i < 0x100; i += 4) {
1570 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1571 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1572 }
1573 return;
1574 }
c8aaea25 1575
66e63ffb
LB		 1576 mc_spec = kmalloc(0x200, GFP_KERNEL);
1577 if (mc_spec == NULL)
1578 goto oom;
1579 mc_other = mc_spec + (0x100 >> 2);
1580
1581 memset(mc_spec, 0, 0x100);
1582 memset(mc_other, 0, 0x100);
1da177e4 1583
fc32b0e2
LB		 1584 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1585 u8 *a = addr->da_addr;
66e63ffb
LB		 1586 u32 *table;
1587 int entry;
1da177e4 1588
fc32b0e2 1589 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1590 table = mc_spec;
1591 entry = a[5];
fc32b0e2 1592 } else {
66e63ffb
LB		 1593 table = mc_other;
1594 entry = addr_crc(a);
fc32b0e2 1595 }
66e63ffb
LB		 1596
1597 table[entry >> 2] |= 1 << (entry & 3);
fc32b0e2 1598 }
66e63ffb
LB		 1599
1600 for (i = 0; i < 0x100; i += 4) {
1601 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1602 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1603 }
1604
1605 kfree(mc_spec);
1606}
1607
1608static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1609{
1610 mv643xx_eth_program_unicast_filter(dev);
1611 mv643xx_eth_program_multicast_filter(dev);
1612}
1613
1614static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1615{
1616 struct sockaddr *sa = addr;
1617
1618 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1619
1620 netif_addr_lock_bh(dev);
1621 mv643xx_eth_program_unicast_filter(dev);
1622 netif_addr_unlock_bh(dev);
1623
1624 return 0;
c9df406f 1625}
c8aaea25 1626
c8aaea25 1627
c9df406f 1628/* rx/tx queue initialisation ***********************************************/
64da80a2 1629static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1630{
64da80a2 1631 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1632 struct rx_desc *rx_desc;
1633 int size;
c9df406f
LB		 1634 int i;
1635
64da80a2
LB		 1636 rxq->index = index;
1637
8a578111
LB		 1638 rxq->rx_ring_size = mp->default_rx_ring_size;
1639
1640 rxq->rx_desc_count = 0;
1641 rxq->rx_curr_desc = 0;
1642 rxq->rx_used_desc = 0;
1643
1644 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1645
f7981c1c 1646 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1647 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1648 mp->rx_desc_sram_size);
1649 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1650 } else {
1651 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1652 &rxq->rx_desc_dma,
1653 GFP_KERNEL);
f7ea3337
PJ		 1654 }
1655
8a578111
LB		 1656 if (rxq->rx_desc_area == NULL) {
1657 dev_printk(KERN_ERR, &mp->dev->dev,
1658 "can't allocate rx ring (%d bytes)\n", size);
1659 goto out;
1660 }
1661 memset(rxq->rx_desc_area, 0, size);
1da177e4 1662
8a578111
LB		 1663 rxq->rx_desc_area_size = size;
1664 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1665 GFP_KERNEL);
1666 if (rxq->rx_skb == NULL) {
1667 dev_printk(KERN_ERR, &mp->dev->dev,
1668 "can't allocate rx skb ring\n");
1669 goto out_free;
1670 }
1671
1672 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1673 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1674 int nexti;
1675
1676 nexti = i + 1;
1677 if (nexti == rxq->rx_ring_size)
1678 nexti = 0;
1679
8a578111
LB		 1680 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1681 nexti * sizeof(struct rx_desc);
1682 }
1683
8a578111
LB		 1684 return 0;
1685
1686
1687out_free:
f7981c1c 1688 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1689 iounmap(rxq->rx_desc_area);
1690 else
1691 dma_free_coherent(NULL, size,
1692 rxq->rx_desc_area,
1693 rxq->rx_desc_dma);
1694
1695out:
1696 return -ENOMEM;
c9df406f 1697}
c8aaea25 1698
8a578111 1699static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1700{
8a578111
LB		 1701 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1702 int i;
1703
1704 rxq_disable(rxq);
c8aaea25 1705
8a578111
LB		 1706 for (i = 0; i < rxq->rx_ring_size; i++) {
1707 if (rxq->rx_skb[i]) {
1708 dev_kfree_skb(rxq->rx_skb[i]);
1709 rxq->rx_desc_count--;
1da177e4 1710 }
c8aaea25 1711 }
1da177e4 1712
8a578111
LB		 1713 if (rxq->rx_desc_count) {
1714 dev_printk(KERN_ERR, &mp->dev->dev,
1715 "error freeing rx ring -- %d skbs stuck\n",
1716 rxq->rx_desc_count);
1717 }
1718
f7981c1c 1719 if (rxq->index == 0 &&
64da80a2 1720 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1721 iounmap(rxq->rx_desc_area);
c9df406f 1722 else
8a578111
LB		 1723 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1724 rxq->rx_desc_area, rxq->rx_desc_dma);
1725
1726 kfree(rxq->rx_skb);
c9df406f 1727}
1da177e4 1728
3d6b35bc 1729static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1730{
3d6b35bc 1731 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1732 struct tx_desc *tx_desc;
1733 int size;
c9df406f 1734 int i;
1da177e4 1735
3d6b35bc
LB		 1736 txq->index = index;
1737
13d64285
LB		 1738 txq->tx_ring_size = mp->default_tx_ring_size;
1739
1740 txq->tx_desc_count = 0;
1741 txq->tx_curr_desc = 0;
1742 txq->tx_used_desc = 0;
1743
1744 size = txq->tx_ring_size * sizeof(struct tx_desc);
1745
f7981c1c 1746 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1747 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1748 mp->tx_desc_sram_size);
1749 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1750 } else {
1751 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1752 &txq->tx_desc_dma,
1753 GFP_KERNEL);
1754 }
1755
1756 if (txq->tx_desc_area == NULL) {
1757 dev_printk(KERN_ERR, &mp->dev->dev,
1758 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1759 return -ENOMEM;
c9df406f 1760 }
13d64285
LB		 1761 memset(txq->tx_desc_area, 0, size);
1762
1763 txq->tx_desc_area_size = size;
13d64285
LB		 1764
1765 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1766 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1767 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1768 int nexti;
1769
1770 nexti = i + 1;
1771 if (nexti == txq->tx_ring_size)
1772 nexti = 0;
6b368f68
LB		 1773
1774 txd->cmd_sts = 0;
1775 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1776 nexti * sizeof(struct tx_desc);
1777 }
1778
99ab08e0 1779 skb_queue_head_init(&txq->tx_skb);
c9df406f 1780
99ab08e0 1781 return 0;
c8aaea25 1782}
1da177e4 1783
13d64285 1784static void txq_deinit(struct tx_queue *txq)
c9df406f 1785{
13d64285 1786 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1787
13d64285 1788 txq_disable(txq);
1fa38c58 1789 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1790
13d64285 1791 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1792
f7981c1c 1793 if (txq->index == 0 &&
3d6b35bc 1794 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1795 iounmap(txq->tx_desc_area);
c9df406f 1796 else
13d64285
LB		 1797 dma_free_coherent(NULL, txq->tx_desc_area_size,
1798 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1799}
1da177e4 1800
1da177e4 1801
c9df406f 1802/* netdev ops and related ***************************************************/
1fa38c58
LB		 1803static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1804{
1805 u32 int_cause;
1806 u32 int_cause_ext;
1807
37a6084f 1808 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 1809 if (int_cause == 0)
1810 return 0;
1811
1812 int_cause_ext = 0;
1813 if (int_cause & INT_EXT)
37a6084f 1814 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 1815
1816 int_cause &= INT_TX_END | INT_RX;
1817 if (int_cause) {
37a6084f 1818 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 1819 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 1820 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 1821 mp->work_rx |= (int_cause & INT_RX) >> 2;
1822 }
1823
1824 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1825 if (int_cause_ext) {
37a6084f 1826 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 1827 if (int_cause_ext & INT_EXT_LINK_PHY)
1828 mp->work_link = 1;
1829 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1830 }
1831
1832 return 1;
1833}
1834
1835static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1836{
1837 struct net_device *dev = (struct net_device *)dev_id;
1838 struct mv643xx_eth_private *mp = netdev_priv(dev);
1839
1840 if (unlikely(!mv643xx_eth_collect_events(mp)))
1841 return IRQ_NONE;
1842
37a6084f 1843 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 1844 napi_schedule(&mp->napi);
1845
1846 return IRQ_HANDLED;
1847}
1848
2f7eb47a
LB		 1849static void handle_link_event(struct mv643xx_eth_private *mp)
1850{
1851 struct net_device *dev = mp->dev;
1852 u32 port_status;
1853 int speed;
1854 int duplex;
1855 int fc;
1856
37a6084f 1857 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 1858 if (!(port_status & LINK_UP)) {
1859 if (netif_carrier_ok(dev)) {
1860 int i;
1861
1862 printk(KERN_INFO "%s: link down\n", dev->name);
1863
1864 netif_carrier_off(dev);
2f7eb47a 1865
f7981c1c 1866 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1867 struct tx_queue *txq = mp->txq + i;
1868
1fa38c58 1869 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1870 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1871 }
1872 }
1873 return;
1874 }
1875
1876 switch (port_status & PORT_SPEED_MASK) {
1877 case PORT_SPEED_10:
1878 speed = 10;
1879 break;
1880 case PORT_SPEED_100:
1881 speed = 100;
1882 break;
1883 case PORT_SPEED_1000:
1884 speed = 1000;
1885 break;
1886 default:
1887 speed = -1;
1888 break;
1889 }
1890 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1891 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1892
1893 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1894 "flow control %sabled\n", dev->name,
1895 speed, duplex ? "full" : "half",
1896 fc ? "en" : "dis");
1897
4fdeca3f 1898 if (!netif_carrier_ok(dev))
2f7eb47a 1899 netif_carrier_on(dev);
2f7eb47a
LB		 1900}
1901
1fa38c58 1902static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1903{
1fa38c58
LB		 1904 struct mv643xx_eth_private *mp;
1905 int work_done;
ce4e2e45 1906
1fa38c58 1907 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1908
1fa38c58
LB		 1909 mp->work_rx_refill |= mp->work_rx_oom;
1910 mp->work_rx_oom = 0;
1da177e4 1911
1fa38c58
LB		 1912 work_done = 0;
1913 while (work_done < budget) {
1914 u8 queue_mask;
1915 int queue;
1916 int work_tbd;
1917
1918 if (mp->work_link) {
1919 mp->work_link = 0;
1920 handle_link_event(mp);
1921 continue;
1922 }
1da177e4 1923
1fa38c58
LB		 1924 queue_mask = mp->work_tx | mp->work_tx_end |
1925 mp->work_rx | mp->work_rx_refill;
1926 if (!queue_mask) {
1927 if (mv643xx_eth_collect_events(mp))
1928 continue;
1929 break;
1930 }
1da177e4 1931
1fa38c58
LB		 1932 queue = fls(queue_mask) - 1;
1933 queue_mask = 1 << queue;
1934
1935 work_tbd = budget - work_done;
1936 if (work_tbd > 16)
1937 work_tbd = 16;
1938
1939 if (mp->work_tx_end & queue_mask) {
1940 txq_kick(mp->txq + queue);
1941 } else if (mp->work_tx & queue_mask) {
1942 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1943 txq_maybe_wake(mp->txq + queue);
1944 } else if (mp->work_rx & queue_mask) {
1945 work_done += rxq_process(mp->rxq + queue, work_tbd);
1946 } else if (mp->work_rx_refill & queue_mask) {
1947 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1948 } else {
1949 BUG();
1950 }
84dd619e 1951 }
fc32b0e2 1952
1fa38c58
LB		 1953 if (work_done < budget) {
1954 if (mp->work_rx_oom)
1955 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1956 napi_complete(napi);
37a6084f 1957 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1958 }
3d6b35bc 1959
1fa38c58
LB		 1960 return work_done;
1961}
8fa89bf5 1962
1fa38c58
LB		 1963static inline void oom_timer_wrapper(unsigned long data)
1964{
1965 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1966
1fa38c58 1967 napi_schedule(&mp->napi);
1da177e4
LT		 1968}
1969
e5371493 1970static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1971{
45c5d3bc
LB		 1972 int data;
1973
ed94493f 1974 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1975 if (data < 0)
1976 return;
1da177e4 1977
7f106c1d 1978 data |= BMCR_RESET;
ed94493f 1979 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1980 return;
1da177e4 1981
c9df406f 1982 do {
ed94493f 1983 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1984 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1985}
1986
fc32b0e2 1987static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1988{
d0412d96 1989 u32 pscr;
8a578111 1990 int i;
1da177e4 1991
bedfe324
LB		 1992 /*
1993 * Perform PHY reset, if there is a PHY.
1994 */
ed94493f 1995 if (mp->phy != NULL) {
bedfe324
LB		 1996 struct ethtool_cmd cmd;
1997
1998 mv643xx_eth_get_settings(mp->dev, &cmd);
1999 phy_reset(mp);
2000 mv643xx_eth_set_settings(mp->dev, &cmd);
2001 }
1da177e4 2002
81600eea
LB		 2003 /*
2004 * Configure basic link parameters.
2005 */
37a6084f 2006 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2007
2008 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2009 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2010
2011 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2012 if (mp->phy == NULL)
81600eea 2013 pscr |= FORCE_LINK_PASS;
37a6084f 2014 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2015
37a6084f 2016 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
81600eea 2017
13d64285
LB		 2018 /*
2019 * Configure TX path and queues.
2020 */
89df5fdc 2021 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2022 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2023 struct tx_queue *txq = mp->txq + i;
13d64285 2024
6b368f68 2025 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2026 txq_set_rate(txq, 1000000000, 16777216);
2027 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2028 }
2029
fc32b0e2
LB		 2030 /*
2031 * Add configured unicast address to address filter table.
2032 */
66e63ffb 2033 mv643xx_eth_program_unicast_filter(mp->dev);
1da177e4 2034
d9a073ea
LB		 2035 /*
2036 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2037 * frames to RX queue #0, and include the pseudo-header when
2038 * calculating receive checksums.
d9a073ea 2039 */
37a6084f 2040 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2041
376489a2
LB		 2042 /*
2043 * Treat BPDUs as normal multicasts, and disable partition mode.
2044 */
37a6084f 2045 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2046
8a578111 2047 /*
64da80a2 2048 * Enable the receive queues.
8a578111 2049 */
f7981c1c 2050 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2051 struct rx_queue *rxq = mp->rxq + i;
8a578111 2052 u32 addr;
1da177e4 2053
8a578111
LB		 2054 addr = (u32)rxq->rx_desc_dma;
2055 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2056 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2057
8a578111
LB		 2058 rxq_enable(rxq);
2059 }
1da177e4
LT		 2060}
2061
ffd86bbe 2062static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2063{
c9df406f 2064 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2065 u32 val;
1da177e4 2066
37a6084f 2067 val = rdlp(mp, SDMA_CONFIG);
773fc3ee
LB		 2068 if (mp->shared->extended_rx_coal_limit) {
2069 if (coal > 0xffff)
2070 coal = 0xffff;
2071 val &= ~0x023fff80;
2072 val |= (coal & 0x8000) << 10;
2073 val |= (coal & 0x7fff) << 7;
2074 } else {
2075 if (coal > 0x3fff)
2076 coal = 0x3fff;
2077 val &= ~0x003fff00;
2078 val |= (coal & 0x3fff) << 8;
2079 }
37a6084f 2080 wrlp(mp, SDMA_CONFIG, val);
1da177e4
LT		 2081}
2082
ffd86bbe 2083static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2084{
c9df406f 2085 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2086
fc32b0e2
LB		 2087 if (coal > 0x3fff)
2088 coal = 0x3fff;
37a6084f 2089 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, (coal & 0x3fff) << 4);
16e03018
DF		 2090}
2091
2bcb4b0f
LB		 2092static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2093{
2094 int skb_size;
2095
2096 /*
2097 * Reserve 2+14 bytes for an ethernet header (the hardware
2098 * automatically prepends 2 bytes of dummy data to each
2099 * received packet), 16 bytes for up to four VLAN tags, and
2100 * 4 bytes for the trailing FCS -- 36 bytes total.
2101 */
2102 skb_size = mp->dev->mtu + 36;
2103
2104 /*
2105 * Make sure that the skb size is a multiple of 8 bytes, as
2106 * the lower three bits of the receive descriptor's buffer
2107 * size field are ignored by the hardware.
2108 */
2109 mp->skb_size = (skb_size + 7) & ~7;
2110}
2111
c9df406f 2112static int mv643xx_eth_open(struct net_device *dev)
16e03018 2113{
e5371493 2114 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2115 int err;
64da80a2 2116 int i;
16e03018 2117
37a6084f
LB		 2118 wrlp(mp, INT_CAUSE, 0);
2119 wrlp(mp, INT_CAUSE_EXT, 0);
2120 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2121
fc32b0e2 2122 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2123 IRQF_SHARED, dev->name, dev);
c9df406f 2124 if (err) {
fc32b0e2 2125 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2126 return -EAGAIN;
16e03018
DF		 2127 }
2128
2bcb4b0f
LB		 2129 mv643xx_eth_recalc_skb_size(mp);
2130
2257e05c
LB		 2131 napi_enable(&mp->napi);
2132
2bcb4b0f
LB		 2133 skb_queue_head_init(&mp->rx_recycle);
2134
f7981c1c 2135 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2136 err = rxq_init(mp, i);
2137 if (err) {
2138 while (--i >= 0)
f7981c1c 2139 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2140 goto out;
2141 }
2142
1fa38c58 2143 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2144 }
2145
1fa38c58 2146 if (mp->work_rx_oom) {
2257e05c
LB		 2147 mp->rx_oom.expires = jiffies + (HZ / 10);
2148 add_timer(&mp->rx_oom);
64da80a2 2149 }
8a578111 2150
f7981c1c 2151 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2152 err = txq_init(mp, i);
2153 if (err) {
2154 while (--i >= 0)
f7981c1c 2155 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2156 goto out_free;
2157 }
2158 }
16e03018 2159
2f7eb47a 2160 netif_carrier_off(dev);
2f7eb47a 2161
fc32b0e2 2162 port_start(mp);
16e03018 2163
ffd86bbe
LB		 2164 set_rx_coal(mp, 0);
2165 set_tx_coal(mp, 0);
16e03018 2166
37a6084f
LB		 2167 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2168 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2169
c9df406f
LB		 2170 return 0;
2171
13d64285 2172
fc32b0e2 2173out_free:
f7981c1c
LB		 2174 for (i = 0; i < mp->rxq_count; i++)
2175 rxq_deinit(mp->rxq + i);
fc32b0e2 2176out:
c9df406f
LB		 2177 free_irq(dev->irq, dev);
2178
2179 return err;
16e03018
DF		 2180}
2181
e5371493 2182static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2183{
fc32b0e2 2184 unsigned int data;
64da80a2 2185 int i;
1da177e4 2186
f7981c1c
LB		 2187 for (i = 0; i < mp->rxq_count; i++)
2188 rxq_disable(mp->rxq + i);
2189 for (i = 0; i < mp->txq_count; i++)
2190 txq_disable(mp->txq + i);
ae9ae064
LB		 2191
2192 while (1) {
37a6084f 2193 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2194
2195 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2196 break;
13d64285 2197 udelay(10);
ae9ae064 2198 }
1da177e4 2199
c9df406f 2200 /* Reset the Enable bit in the Configuration Register */
37a6084f 2201 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2202 data &= ~(SERIAL_PORT_ENABLE |
2203 DO_NOT_FORCE_LINK_FAIL |
2204 FORCE_LINK_PASS);
37a6084f 2205 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2206}
2207
c9df406f 2208static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2209{
e5371493 2210 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2211 int i;
1da177e4 2212
37a6084f
LB		 2213 wrlp(mp, INT_MASK, 0x00000000);
2214 rdlp(mp, INT_MASK);
1da177e4 2215
4ff3495a
LB		 2216 del_timer_sync(&mp->mib_counters_timer);
2217
c9df406f 2218 napi_disable(&mp->napi);
78fff83b 2219
2257e05c
LB		 2220 del_timer_sync(&mp->rx_oom);
2221
c9df406f 2222 netif_carrier_off(dev);
1da177e4 2223
fc32b0e2
LB		 2224 free_irq(dev->irq, dev);
2225
cc9754b3 2226 port_reset(mp);
8fd89211 2227 mv643xx_eth_get_stats(dev);
fc32b0e2 2228 mib_counters_update(mp);
1da177e4 2229
2bcb4b0f
LB		 2230 skb_queue_purge(&mp->rx_recycle);
2231
f7981c1c
LB		 2232 for (i = 0; i < mp->rxq_count; i++)
2233 rxq_deinit(mp->rxq + i);
2234 for (i = 0; i < mp->txq_count; i++)
2235 txq_deinit(mp->txq + i);
1da177e4 2236
c9df406f 2237 return 0;
1da177e4
LT		 2238}
2239
fc32b0e2 2240static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2241{
e5371493 2242 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2243
ed94493f
LB		 2244 if (mp->phy != NULL)
2245 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2246
2247 return -EOPNOTSUPP;
1da177e4
LT		 2248}
2249
c9df406f 2250static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2251{
89df5fdc
LB		 2252 struct mv643xx_eth_private *mp = netdev_priv(dev);
2253
fc32b0e2 2254 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2255 return -EINVAL;
1da177e4 2256
c9df406f 2257 dev->mtu = new_mtu;
2bcb4b0f 2258 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2259 tx_set_rate(mp, 1000000000, 16777216);
2260
c9df406f
LB		 2261 if (!netif_running(dev))
2262 return 0;
1da177e4 2263
c9df406f
LB		 2264 /*
2265 * Stop and then re-open the interface. This will allocate RX
2266 * skbs of the new MTU.
2267 * There is a possible danger that the open will not succeed,
fc32b0e2 2268 * due to memory being full.
c9df406f
LB		 2269 */
2270 mv643xx_eth_stop(dev);
2271 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2272 dev_printk(KERN_ERR, &dev->dev,
2273 "fatal error on re-opening device after "
2274 "MTU change\n");
c9df406f
LB		 2275 }
2276
2277 return 0;
1da177e4
LT		 2278}
2279
fc32b0e2 2280static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2281{
fc32b0e2 2282 struct mv643xx_eth_private *mp;
1da177e4 2283
fc32b0e2
LB		 2284 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2285 if (netif_running(mp->dev)) {
e5ef1de1 2286 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2287 port_reset(mp);
2288 port_start(mp);
e5ef1de1 2289 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2290 }
c9df406f
LB		 2291}
2292
c9df406f 2293static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2294{
e5371493 2295 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2296
fc32b0e2 2297 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2298
c9df406f 2299 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2300}
2301
c9df406f 2302#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2303static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2304{
fc32b0e2 2305 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2306
37a6084f
LB		 2307 wrlp(mp, INT_MASK, 0x00000000);
2308 rdlp(mp, INT_MASK);
c9df406f 2309
fc32b0e2 2310 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2311
37a6084f 2312 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2313}
c9df406f 2314#endif
9f8dd319 2315
9f8dd319 2316
c9df406f 2317/* platform glue ************************************************************/
e5371493
LB		 2318static void
2319mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2320 struct mbus_dram_target_info *dram)
c9df406f 2321{
cc9754b3 2322 void __iomem *base = msp->base;
c9df406f
LB		 2323 u32 win_enable;
2324 u32 win_protect;
2325 int i;
9f8dd319 2326
c9df406f
LB		 2327 for (i = 0; i < 6; i++) {
2328 writel(0, base + WINDOW_BASE(i));
2329 writel(0, base + WINDOW_SIZE(i));
2330 if (i < 4)
2331 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2332 }
2333
c9df406f
LB		 2334 win_enable = 0x3f;
2335 win_protect = 0;
2336
2337 for (i = 0; i < dram->num_cs; i++) {
2338 struct mbus_dram_window *cs = dram->cs + i;
2339
2340 writel((cs->base & 0xffff0000) |
2341 (cs->mbus_attr << 8) |
2342 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2343 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2344
2345 win_enable &= ~(1 << i);
2346 win_protect |= 3 << (2 * i);
2347 }
2348
2349 writel(win_enable, base + WINDOW_BAR_ENABLE);
2350 msp->win_protect = win_protect;
9f8dd319
DF		 2351}
2352
773fc3ee
LB		 2353static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2354{
2355 /*
2356 * Check whether we have a 14-bit coal limit field in bits
2357 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2358 * SDMA config register.
2359 */
37a6084f
LB		 2360 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2361 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2362 msp->extended_rx_coal_limit = 1;
2363 else
2364 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2365
2366 /*
457b1d5a
LB		 2367 * Check whether the MAC supports TX rate control, and if
2368 * yes, whether its associated registers are in the old or
2369 * the new place.
1e881592 2370 */
37a6084f
LB		 2371 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2372 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2373 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2374 } else {
37a6084f
LB		 2375 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2376 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2377 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2378 else
2379 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2380 }
773fc3ee
LB		 2381}
2382
c9df406f 2383static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2384{
10a9948d 2385 static int mv643xx_eth_version_printed;
c9df406f 2386 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2387 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2388 struct resource *res;
2389 int ret;
9f8dd319 2390
e5371493 2391 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2392 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2393 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2394
c9df406f
LB		 2395 ret = -EINVAL;
2396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2397 if (res == NULL)
2398 goto out;
9f8dd319 2399
c9df406f
LB		 2400 ret = -ENOMEM;
2401 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2402 if (msp == NULL)
2403 goto out;
2404 memset(msp, 0, sizeof(*msp));
2405
cc9754b3
LB		 2406 msp->base = ioremap(res->start, res->end - res->start + 1);
2407 if (msp->base == NULL)
c9df406f
LB		 2408 goto out_free;
2409
ed94493f
LB		 2410 /*
2411 * Set up and register SMI bus.
2412 */
2413 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2414 msp->smi_bus = mdiobus_alloc();
2415 if (msp->smi_bus == NULL)
ed94493f 2416 goto out_unmap;
298cf9be
LB		 2417
2418 msp->smi_bus->priv = msp;
2419 msp->smi_bus->name = "mv643xx_eth smi";
2420 msp->smi_bus->read = smi_bus_read;
2421 msp->smi_bus->write = smi_bus_write,
2422 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2423 msp->smi_bus->parent = &pdev->dev;
2424 msp->smi_bus->phy_mask = 0xffffffff;
2425 if (mdiobus_register(msp->smi_bus) < 0)
2426 goto out_free_mii_bus;
ed94493f
LB		 2427 msp->smi = msp;
2428 } else {
fc0eb9f2 2429 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2430 }
c9df406f 2431
45c5d3bc
LB		 2432 msp->err_interrupt = NO_IRQ;
2433 init_waitqueue_head(&msp->smi_busy_wait);
2434
2435 /*
2436 * Check whether the error interrupt is hooked up.
2437 */
2438 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2439 if (res != NULL) {
2440 int err;
2441
2442 err = request_irq(res->start, mv643xx_eth_err_irq,
2443 IRQF_SHARED, "mv643xx_eth", msp);
2444 if (!err) {
2445 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2446 msp->err_interrupt = res->start;
2447 }
2448 }
2449
c9df406f
LB		 2450 /*
2451 * (Re-)program MBUS remapping windows if we are asked to.
2452 */
2453 if (pd != NULL && pd->dram != NULL)
2454 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2455
fc32b0e2
LB		 2456 /*
2457 * Detect hardware parameters.
2458 */
2459 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2460 infer_hw_params(msp);
fc32b0e2
LB		 2461
2462 platform_set_drvdata(pdev, msp);
2463
c9df406f
LB		 2464 return 0;
2465
298cf9be
LB		 2466out_free_mii_bus:
2467 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2468out_unmap:
2469 iounmap(msp->base);
c9df406f
LB		 2470out_free:
2471 kfree(msp);
2472out:
2473 return ret;
2474}
2475
2476static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2477{
e5371493 2478 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2479 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2480
298cf9be 2481 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2482 mdiobus_unregister(msp->smi_bus);
bcb3336c 2483 mdiobus_free(msp->smi_bus);
298cf9be 2484 }
45c5d3bc
LB		 2485 if (msp->err_interrupt != NO_IRQ)
2486 free_irq(msp->err_interrupt, msp);
cc9754b3 2487 iounmap(msp->base);
c9df406f
LB		 2488 kfree(msp);
2489
2490 return 0;
9f8dd319
DF		 2491}
2492
c9df406f 2493static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2494 .probe = mv643xx_eth_shared_probe,
2495 .remove = mv643xx_eth_shared_remove,
c9df406f 2496 .driver = {
fc32b0e2 2497 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2498 .owner = THIS_MODULE,
2499 },
2500};
2501
e5371493 2502static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2503{
c9df406f 2504 int addr_shift = 5 * mp->port_num;
fc32b0e2 2505 u32 data;
1da177e4 2506
fc32b0e2
LB		 2507 data = rdl(mp, PHY_ADDR);
2508 data &= ~(0x1f << addr_shift);
2509 data |= (phy_addr & 0x1f) << addr_shift;
2510 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2511}
2512
e5371493 2513static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2514{
fc32b0e2
LB		 2515 unsigned int data;
2516
2517 data = rdl(mp, PHY_ADDR);
2518
2519 return (data >> (5 * mp->port_num)) & 0x1f;
2520}
2521
2522static void set_params(struct mv643xx_eth_private *mp,
2523 struct mv643xx_eth_platform_data *pd)
2524{
2525 struct net_device *dev = mp->dev;
2526
2527 if (is_valid_ether_addr(pd->mac_addr))
2528 memcpy(dev->dev_addr, pd->mac_addr, 6);
2529 else
2530 uc_addr_get(mp, dev->dev_addr);
2531
fc32b0e2
LB		 2532 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2533 if (pd->rx_queue_size)
2534 mp->default_rx_ring_size = pd->rx_queue_size;
2535 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2536 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2537
f7981c1c 2538 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2539
fc32b0e2
LB		 2540 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2541 if (pd->tx_queue_size)
2542 mp->default_tx_ring_size = pd->tx_queue_size;
2543 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2544 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2545
f7981c1c 2546 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2547}
2548
ed94493f
LB		 2549static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2550 int phy_addr)
1da177e4 2551{
298cf9be 2552 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2553 struct phy_device *phydev;
2554 int start;
2555 int num;
2556 int i;
45c5d3bc 2557
ed94493f
LB		 2558 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2559 start = phy_addr_get(mp) & 0x1f;
2560 num = 32;
2561 } else {
2562 start = phy_addr & 0x1f;
2563 num = 1;
2564 }
45c5d3bc 2565
ed94493f
LB		 2566 phydev = NULL;
2567 for (i = 0; i < num; i++) {
2568 int addr = (start + i) & 0x1f;
fc32b0e2 2569
ed94493f
LB		 2570 if (bus->phy_map[addr] == NULL)
2571 mdiobus_scan(bus, addr);
1da177e4 2572
ed94493f
LB		 2573 if (phydev == NULL) {
2574 phydev = bus->phy_map[addr];
2575 if (phydev != NULL)
2576 phy_addr_set(mp, addr);
2577 }
2578 }
1da177e4 2579
ed94493f 2580 return phydev;
1da177e4
LT		 2581}
2582
ed94493f 2583static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2584{
ed94493f 2585 struct phy_device *phy = mp->phy;
c28a4f89 2586
fc32b0e2
LB		 2587 phy_reset(mp);
2588
ed94493f
LB		 2589 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2590
2591 if (speed == 0) {
2592 phy->autoneg = AUTONEG_ENABLE;
2593 phy->speed = 0;
2594 phy->duplex = 0;
2595 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2596 } else {
ed94493f
LB		 2597 phy->autoneg = AUTONEG_DISABLE;
2598 phy->advertising = 0;
2599 phy->speed = speed;
2600 phy->duplex = duplex;
c9df406f 2601 }
ed94493f 2602 phy_start_aneg(phy);
c28a4f89
JC		 2603}
2604
81600eea
LB		 2605static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2606{
2607 u32 pscr;
2608
37a6084f 2609 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2610 if (pscr & SERIAL_PORT_ENABLE) {
2611 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2612 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2613 }
2614
2615 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2616 if (mp->phy == NULL) {
81600eea
LB		 2617 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2618 if (speed == SPEED_1000)
2619 pscr |= SET_GMII_SPEED_TO_1000;
2620 else if (speed == SPEED_100)
2621 pscr |= SET_MII_SPEED_TO_100;
2622
2623 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2624
2625 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2626 if (duplex == DUPLEX_FULL)
2627 pscr |= SET_FULL_DUPLEX_MODE;
2628 }
2629
37a6084f 2630 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2631}
2632
c9df406f 2633static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2634{
c9df406f 2635 struct mv643xx_eth_platform_data *pd;
e5371493 2636 struct mv643xx_eth_private *mp;
c9df406f 2637 struct net_device *dev;
c9df406f 2638 struct resource *res;
fc32b0e2 2639 int err;
1da177e4 2640
c9df406f
LB		 2641 pd = pdev->dev.platform_data;
2642 if (pd == NULL) {
fc32b0e2
LB		 2643 dev_printk(KERN_ERR, &pdev->dev,
2644 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2645 return -ENODEV;
2646 }
1da177e4 2647
c9df406f 2648 if (pd->shared == NULL) {
fc32b0e2
LB		 2649 dev_printk(KERN_ERR, &pdev->dev,
2650 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2651 return -ENODEV;
2652 }
8f518703 2653
e5ef1de1 2654 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2655 if (!dev)
2656 return -ENOMEM;
1da177e4 2657
c9df406f 2658 mp = netdev_priv(dev);
fc32b0e2
LB		 2659 platform_set_drvdata(pdev, mp);
2660
2661 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2662 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2663 mp->port_num = pd->port_number;
2664
c9df406f 2665 mp->dev = dev;
78fff83b 2666
fc32b0e2 2667 set_params(mp, pd);
e5ef1de1 2668 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2669
ed94493f
LB		 2670 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2671 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2672
ed94493f
LB		 2673 if (mp->phy != NULL) {
2674 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2675 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2676 } else {
2677 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2678 }
ed94493f 2679
81600eea 2680 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2681
4ff3495a
LB		 2682
2683 mib_counters_clear(mp);
2684
2685 init_timer(&mp->mib_counters_timer);
2686 mp->mib_counters_timer.data = (unsigned long)mp;
2687 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2688 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2689 add_timer(&mp->mib_counters_timer);
2690
2691 spin_lock_init(&mp->mib_counters_lock);
2692
2693 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2694
2257e05c
LB		 2695 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2696
2697 init_timer(&mp->rx_oom);
2698 mp->rx_oom.data = (unsigned long)mp;
2699 mp->rx_oom.function = oom_timer_wrapper;
2700
fc32b0e2 2701
c9df406f
LB		 2702 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2703 BUG_ON(!res);
2704 dev->irq = res->start;
1da177e4 2705
8fd89211 2706 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2707 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2708 dev->open = mv643xx_eth_open;
2709 dev->stop = mv643xx_eth_stop;
66e63ffb 2710 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2711 dev->set_mac_address = mv643xx_eth_set_mac_address;
2712 dev->do_ioctl = mv643xx_eth_ioctl;
2713 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2714 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2715#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2716 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2717#endif
c9df406f
LB		 2718 dev->watchdog_timeo = 2 * HZ;
2719 dev->base_addr = 0;
1da177e4 2720
c9df406f 2721 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2722 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2723
fc32b0e2 2724 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2725
c9df406f 2726 if (mp->shared->win_protect)
fc32b0e2 2727 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2728
c9df406f
LB		 2729 err = register_netdev(dev);
2730 if (err)
2731 goto out;
1da177e4 2732
e174961c
JB		 2733 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2734 mp->port_num, dev->dev_addr);
1da177e4 2735
13d64285 2736 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2737 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2738
c9df406f 2739 return 0;
1da177e4 2740
c9df406f
LB		 2741out:
2742 free_netdev(dev);
1da177e4 2743
c9df406f 2744 return err;
1da177e4
LT		 2745}
2746
c9df406f 2747static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2748{
fc32b0e2 2749 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2750
fc32b0e2 2751 unregister_netdev(mp->dev);
ed94493f
LB		 2752 if (mp->phy != NULL)
2753 phy_detach(mp->phy);
c9df406f 2754 flush_scheduled_work();
fc32b0e2 2755 free_netdev(mp->dev);
c9df406f 2756
c9df406f 2757 platform_set_drvdata(pdev, NULL);
fc32b0e2 2758
c9df406f 2759 return 0;
1da177e4
LT		 2760}
2761
c9df406f 2762static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2763{
fc32b0e2 2764 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2765
c9df406f 2766 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2767 wrlp(mp, INT_MASK, 0);
2768 rdlp(mp, INT_MASK);
c9df406f 2769
fc32b0e2
LB		 2770 if (netif_running(mp->dev))
2771 port_reset(mp);
d0412d96
JC		 2772}
2773
c9df406f 2774static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2775 .probe = mv643xx_eth_probe,
2776 .remove = mv643xx_eth_remove,
2777 .shutdown = mv643xx_eth_shutdown,
c9df406f 2778 .driver = {
fc32b0e2 2779 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2780 .owner = THIS_MODULE,
2781 },
2782};
2783
e5371493 2784static int __init mv643xx_eth_init_module(void)
d0412d96 2785{
c9df406f 2786 int rc;
d0412d96 2787
c9df406f
LB		 2788 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2789 if (!rc) {
2790 rc = platform_driver_register(&mv643xx_eth_driver);
2791 if (rc)
2792 platform_driver_unregister(&mv643xx_eth_shared_driver);
2793 }
fc32b0e2 2794
c9df406f 2795 return rc;
d0412d96 2796}
fc32b0e2 2797module_init(mv643xx_eth_init_module);
d0412d96 2798
e5371493 2799static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2800{
c9df406f
LB		 2801 platform_driver_unregister(&mv643xx_eth_driver);
2802 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2803}
e5371493 2804module_exit(mv643xx_eth_cleanup_module);
1da177e4 2805
45675bc6
LB		 2806MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2807 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2808MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2809MODULE_LICENSE("GPL");
c9df406f 2810MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2811MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Clone of davem's net-next-2.6 tree