]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/mv643xx_eth.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mv643xx_eth: fix variable shadowing sparse warning
[net-next-2.6.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
1da177e4 57#include <asm/system.h>
fbd6a754 58
e5371493 59static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 60static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 61
fbd6a754 62
fbd6a754
LB		 63/*
64 * Registers shared between all ports.
65 */
3cb4667c
LB		 66#define PHY_ADDR 0x0000
67#define SMI_REG 0x0004
45c5d3bc
LB		 68#define SMI_BUSY 0x10000000
69#define SMI_READ_VALID 0x08000000
70#define SMI_OPCODE_READ 0x04000000
71#define SMI_OPCODE_WRITE 0x00000000
72#define ERR_INT_CAUSE 0x0080
73#define ERR_INT_SMI_DONE 0x00000010
74#define ERR_INT_MASK 0x0084
3cb4667c
LB		 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
37a6084f
LB		 82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 84 */
37a6084f 85#define PORT_CONFIG 0x0000
d9a073ea 86#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 87#define PORT_CONFIG_EXT 0x0004
88#define MAC_ADDR_LOW 0x0014
89#define MAC_ADDR_HIGH 0x0018
90#define SDMA_CONFIG 0x001c
91#define PORT_SERIAL_CONTROL 0x003c
92#define PORT_STATUS 0x0044
a2a41689 93#define TX_FIFO_EMPTY 0x00000400
ae9ae064 94#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 95#define PORT_SPEED_MASK 0x00000030
96#define PORT_SPEED_1000 0x00000010
97#define PORT_SPEED_100 0x00000020
98#define PORT_SPEED_10 0x00000000
99#define FLOW_CONTROL_ENABLED 0x00000008
100#define FULL_DUPLEX 0x00000004
81600eea 101#define LINK_UP 0x00000002
37a6084f
LB		 102#define TXQ_COMMAND 0x0048
103#define TXQ_FIX_PRIO_CONF 0x004c
104#define TX_BW_RATE 0x0050
105#define TX_BW_MTU 0x0058
106#define TX_BW_BURST 0x005c
107#define INT_CAUSE 0x0060
226bb6b7 108#define INT_TX_END 0x07f80000
befefe21 109#define INT_RX 0x000003fc
073a345c 110#define INT_EXT 0x00000002
37a6084f 111#define INT_CAUSE_EXT 0x0064
befefe21
LB		 112#define INT_EXT_LINK_PHY 0x00110000
113#define INT_EXT_TX 0x000000ff
37a6084f
LB		 114#define INT_MASK 0x0068
115#define INT_MASK_EXT 0x006c
116#define TX_FIFO_URGENT_THRESHOLD 0x0074
117#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
118#define TX_BW_RATE_MOVED 0x00e0
119#define TX_BW_MTU_MOVED 0x00e8
120#define TX_BW_BURST_MOVED 0x00ec
121#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
122#define RXQ_COMMAND 0x0280
123#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
124#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
125#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
126#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
127
128/*
129 * Misc per-port registers.
130 */
3cb4667c
LB		 131#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
132#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
133#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
134#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 135
2679a550
LB		 136
137/*
138 * SDMA configuration register.
139 */
e0c6ef93 140#define RX_BURST_SIZE_4_64BIT (2 << 1)
cd4ccf76 141#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 142#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 143#define BLM_TX_NO_SWAP (1 << 5)
e0c6ef93 144#define TX_BURST_SIZE_4_64BIT (2 << 22)
cd4ccf76 145#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 146
147#if defined(__BIG_ENDIAN)
148#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 149 (RX_BURST_SIZE_4_64BIT | \
150 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 151#elif defined(__LITTLE_ENDIAN)
152#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 153 (RX_BURST_SIZE_4_64BIT | \
154 BLM_RX_NO_SWAP | \
155 BLM_TX_NO_SWAP | \
156 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 157#else
158#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
159#endif
160
2beff77b
LB		 161
162/*
163 * Port serial control register.
164 */
165#define SET_MII_SPEED_TO_100 (1 << 24)
166#define SET_GMII_SPEED_TO_1000 (1 << 23)
167#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 168#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 169#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
170#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
171#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
172#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
173#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
174#define FORCE_LINK_PASS (1 << 1)
175#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 176
2b4a624d
LB		 177#define DEFAULT_RX_QUEUE_SIZE 128
178#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 179
fbd6a754 180
7ca72a3b
LB		 181/*
182 * RX/TX descriptors.
fbd6a754
LB		 183 */
184#if defined(__BIG_ENDIAN)
cc9754b3 185struct rx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191};
192
cc9754b3 193struct tx_desc {
fbd6a754
LB		 194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199};
200#elif defined(__LITTLE_ENDIAN)
cc9754b3 201struct rx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207};
208
cc9754b3 209struct tx_desc {
fbd6a754
LB		 210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215};
216#else
217#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218#endif
219
7ca72a3b 220/* RX & TX descriptor command */
cc9754b3 221#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 222
223/* RX & TX descriptor status */
cc9754b3 224#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 225
226/* RX descriptor status */
cc9754b3
LB		 227#define LAYER_4_CHECKSUM_OK 0x40000000
228#define RX_ENABLE_INTERRUPT 0x20000000
229#define RX_FIRST_DESC 0x08000000
230#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 231#define RX_IP_HDR_OK 0x02000000
232#define RX_PKT_IS_IPV4 0x01000000
233#define RX_PKT_IS_ETHERNETV2 0x00800000
234#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 237
238/* TX descriptor command */
cc9754b3
LB		 239#define TX_ENABLE_INTERRUPT 0x00800000
240#define GEN_CRC 0x00400000
241#define TX_FIRST_DESC 0x00200000
242#define TX_LAST_DESC 0x00100000
243#define ZERO_PADDING 0x00080000
244#define GEN_IP_V4_CHECKSUM 0x00040000
245#define GEN_TCP_UDP_CHECKSUM 0x00020000
246#define UDP_FRAME 0x00010000
e32b6617
LB		 247#define MAC_HDR_EXTRA_4_BYTES 0x00008000
248#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 249
cc9754b3 250#define TX_IHL_SHIFT 11
7ca72a3b
LB		 251
252
c9df406f 253/* global *******************************************************************/
e5371493 254struct mv643xx_eth_shared_private {
fc32b0e2
LB		 255 /*
256 * Ethernet controller base address.
257 */
cc9754b3 258 void __iomem *base;
c9df406f 259
fc0eb9f2
LB		 260 /*
261 * Points at the right SMI instance to use.
262 */
263 struct mv643xx_eth_shared_private *smi;
264
fc32b0e2 265 /*
ed94493f 266 * Provides access to local SMI interface.
fc32b0e2 267 */
298cf9be 268 struct mii_bus *smi_bus;
c9df406f 269
45c5d3bc
LB		 270 /*
271 * If we have access to the error interrupt pin (which is
272 * somewhat misnamed as it not only reflects internal errors
273 * but also reflects SMI completion), use that to wait for
274 * SMI access completion instead of polling the SMI busy bit.
275 */
276 int err_interrupt;
277 wait_queue_head_t smi_busy_wait;
278
fc32b0e2
LB		 279 /*
280 * Per-port MBUS window access register value.
281 */
c9df406f
LB		 282 u32 win_protect;
283
fc32b0e2
LB		 284 /*
285 * Hardware-specific parameters.
286 */
c9df406f 287 unsigned int t_clk;
773fc3ee 288 int extended_rx_coal_limit;
457b1d5a 289 int tx_bw_control;
c9df406f
LB		 290};
291
457b1d5a
LB		 292#define TX_BW_CONTROL_ABSENT 0
293#define TX_BW_CONTROL_OLD_LAYOUT 1
294#define TX_BW_CONTROL_NEW_LAYOUT 2
295
e7d2f4db
LB		 296static int mv643xx_eth_open(struct net_device *dev);
297static int mv643xx_eth_stop(struct net_device *dev);
298
c9df406f
LB		 299
300/* per-port *****************************************************************/
e5371493 301struct mib_counters {
fbd6a754
LB		 302 u64 good_octets_received;
303 u32 bad_octets_received;
304 u32 internal_mac_transmit_err;
305 u32 good_frames_received;
306 u32 bad_frames_received;
307 u32 broadcast_frames_received;
308 u32 multicast_frames_received;
309 u32 frames_64_octets;
310 u32 frames_65_to_127_octets;
311 u32 frames_128_to_255_octets;
312 u32 frames_256_to_511_octets;
313 u32 frames_512_to_1023_octets;
314 u32 frames_1024_to_max_octets;
315 u64 good_octets_sent;
316 u32 good_frames_sent;
317 u32 excessive_collision;
318 u32 multicast_frames_sent;
319 u32 broadcast_frames_sent;
320 u32 unrec_mac_control_received;
321 u32 fc_sent;
322 u32 good_fc_received;
323 u32 bad_fc_received;
324 u32 undersize_received;
325 u32 fragments_received;
326 u32 oversize_received;
327 u32 jabber_received;
328 u32 mac_receive_error;
329 u32 bad_crc_event;
330 u32 collision;
331 u32 late_collision;
332};
333
eaf5d590
LB		 334struct lro_counters {
335 u32 lro_aggregated;
336 u32 lro_flushed;
337 u32 lro_no_desc;
338};
339
8a578111 340struct rx_queue {
64da80a2
LB		 341 int index;
342
8a578111
LB		 343 int rx_ring_size;
344
345 int rx_desc_count;
346 int rx_curr_desc;
347 int rx_used_desc;
348
349 struct rx_desc *rx_desc_area;
350 dma_addr_t rx_desc_dma;
351 int rx_desc_area_size;
352 struct sk_buff **rx_skb;
eaf5d590 353
eaf5d590
LB		 354 struct net_lro_mgr lro_mgr;
355 struct net_lro_desc lro_arr[8];
8a578111
LB		 356};
357
13d64285 358struct tx_queue {
3d6b35bc
LB		 359 int index;
360
13d64285 361 int tx_ring_size;
fbd6a754 362
13d64285
LB		 363 int tx_desc_count;
364 int tx_curr_desc;
365 int tx_used_desc;
fbd6a754 366
5daffe94 367 struct tx_desc *tx_desc_area;
fbd6a754
LB		 368 dma_addr_t tx_desc_dma;
369 int tx_desc_area_size;
99ab08e0
LB		 370
371 struct sk_buff_head tx_skb;
8fd89211
LB		 372
373 unsigned long tx_packets;
374 unsigned long tx_bytes;
375 unsigned long tx_dropped;
13d64285
LB		 376};
377
378struct mv643xx_eth_private {
379 struct mv643xx_eth_shared_private *shared;
37a6084f 380 void __iomem *base;
fc32b0e2 381 int port_num;
13d64285 382
fc32b0e2 383 struct net_device *dev;
fbd6a754 384
ed94493f 385 struct phy_device *phy;
fbd6a754 386
4ff3495a
LB		 387 struct timer_list mib_counters_timer;
388 spinlock_t mib_counters_lock;
fc32b0e2 389 struct mib_counters mib_counters;
4ff3495a 390
eaf5d590
LB		 391 struct lro_counters lro_counters;
392
fc32b0e2 393 struct work_struct tx_timeout_task;
8a578111 394
1fa38c58 395 struct napi_struct napi;
1319ebad 396 u8 oom;
1fa38c58
LB		 397 u8 work_link;
398 u8 work_tx;
399 u8 work_tx_end;
400 u8 work_rx;
401 u8 work_rx_refill;
1fa38c58 402
2bcb4b0f
LB		 403 int skb_size;
404 struct sk_buff_head rx_recycle;
405
8a578111
LB		 406 /*
407 * RX state.
408 */
e7d2f4db 409 int rx_ring_size;
8a578111
LB		 410 unsigned long rx_desc_sram_addr;
411 int rx_desc_sram_size;
f7981c1c 412 int rxq_count;
2257e05c 413 struct timer_list rx_oom;
64da80a2 414 struct rx_queue rxq[8];
13d64285
LB		 415
416 /*
417 * TX state.
418 */
e7d2f4db 419 int tx_ring_size;
13d64285
LB		 420 unsigned long tx_desc_sram_addr;
421 int tx_desc_sram_size;
f7981c1c 422 int txq_count;
3d6b35bc 423 struct tx_queue txq[8];
fbd6a754 424};
1da177e4 425
fbd6a754 426
c9df406f 427/* port register accessors **************************************************/
e5371493 428static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 429{
cc9754b3 430 return readl(mp->shared->base + offset);
c9df406f 431}
fbd6a754 432
37a6084f
LB		 433static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
434{
435 return readl(mp->base + offset);
436}
437
e5371493 438static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 439{
cc9754b3 440 writel(data, mp->shared->base + offset);
c9df406f 441}
fbd6a754 442
37a6084f
LB		 443static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
444{
445 writel(data, mp->base + offset);
446}
447
fbd6a754 448
c9df406f 449/* rxq/txq helper functions *************************************************/
8a578111 450static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 451{
64da80a2 452 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 453}
fbd6a754 454
13d64285
LB		 455static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
456{
3d6b35bc 457 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 458}
459
8a578111 460static void rxq_enable(struct rx_queue *rxq)
c9df406f 461{
8a578111 462 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 463 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 464}
1da177e4 465
8a578111
LB		 466static void rxq_disable(struct rx_queue *rxq)
467{
468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 469 u8 mask = 1 << rxq->index;
1da177e4 470
37a6084f
LB		 471 wrlp(mp, RXQ_COMMAND, mask << 8);
472 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 473 udelay(10);
c9df406f
LB		 474}
475
6b368f68
LB		 476static void txq_reset_hw_ptr(struct tx_queue *txq)
477{
478 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 479 u32 addr;
480
481 addr = (u32)txq->tx_desc_dma;
482 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 483 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 484}
485
13d64285 486static void txq_enable(struct tx_queue *txq)
1da177e4 487{
13d64285 488 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 489 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 490}
491
13d64285 492static void txq_disable(struct tx_queue *txq)
1da177e4 493{
13d64285 494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 495 u8 mask = 1 << txq->index;
c9df406f 496
37a6084f
LB		 497 wrlp(mp, TXQ_COMMAND, mask << 8);
498 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 499 udelay(10);
500}
501
1fa38c58 502static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 503{
504 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 505 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 506
8fd89211
LB		 507 if (netif_tx_queue_stopped(nq)) {
508 __netif_tx_lock(nq, smp_processor_id());
509 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
510 netif_tx_wake_queue(nq);
511 __netif_tx_unlock(nq);
512 }
1da177e4
LT		 513}
514
c9df406f 515
1fa38c58 516/* rx napi ******************************************************************/
eaf5d590
LB		 517static int
518mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
519 u64 *hdr_flags, void *priv)
520{
521 unsigned long cmd_sts = (unsigned long)priv;
522
523 /*
524 * Make sure that this packet is Ethernet II, is not VLAN
525 * tagged, is IPv4, has a valid IP header, and is TCP.
526 */
527 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
528 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
529 RX_PKT_IS_VLAN_TAGGED)) !=
530 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
532 return -1;
533
534 skb_reset_network_header(skb);
535 skb_set_transport_header(skb, ip_hdrlen(skb));
536 *iphdr = ip_hdr(skb);
537 *tcph = tcp_hdr(skb);
538 *hdr_flags = LRO_IPV4 | LRO_TCP;
539
540 return 0;
541}
eaf5d590 542
8a578111 543static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 544{
8a578111
LB		 545 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
546 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 547 int lro_flush_needed;
8a578111 548 int rx;
1da177e4 549
eaf5d590 550 lro_flush_needed = 0;
8a578111 551 rx = 0;
9e1f3772 552 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 553 struct rx_desc *rx_desc;
96587661 554 unsigned int cmd_sts;
fc32b0e2 555 struct sk_buff *skb;
6b8f90c2 556 u16 byte_cnt;
ff561eef 557
8a578111 558 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 559
96587661 560 cmd_sts = rx_desc->cmd_sts;
2257e05c 561 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 562 break;
96587661 563 rmb();
1da177e4 564
8a578111
LB		 565 skb = rxq->rx_skb[rxq->rx_curr_desc];
566 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 567
9da78745
LB		 568 rxq->rx_curr_desc++;
569 if (rxq->rx_curr_desc == rxq->rx_ring_size)
570 rxq->rx_curr_desc = 0;
ff561eef 571
3a499481 572 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 573 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 574 rxq->rx_desc_count--;
575 rx++;
b1dd9ca1 576
1fa38c58
LB		 577 mp->work_rx_refill |= 1 << rxq->index;
578
6b8f90c2
LB		 579 byte_cnt = rx_desc->byte_cnt;
580
468d09f8
DF		 581 /*
582 * Update statistics.
fc32b0e2
LB		 583 *
584 * Note that the descriptor byte count includes 2 dummy
585 * bytes automatically inserted by the hardware at the
586 * start of the packet (which we don't count), and a 4
587 * byte CRC at the end of the packet (which we do count).
468d09f8 588 */
1da177e4 589 stats->rx_packets++;
6b8f90c2 590 stats->rx_bytes += byte_cnt - 2;
96587661 591
1da177e4 592 /*
fc32b0e2
LB		 593 * In case we received a packet without first / last bits
594 * on, or the error summary bit is set, the packet needs
595 * to be dropped.
1da177e4 596 */
f61e5547
LB		 597 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
598 != (RX_FIRST_DESC | RX_LAST_DESC))
599 goto err;
600
601 /*
602 * The -4 is for the CRC in the trailer of the
603 * received packet
604 */
605 skb_put(skb, byte_cnt - 2 - 4);
606
607 if (cmd_sts & LAYER_4_CHECKSUM_OK)
608 skb->ip_summed = CHECKSUM_UNNECESSARY;
609 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 610
eaf5d590
LB		 611 if (skb->dev->features & NETIF_F_LRO &&
612 skb->ip_summed == CHECKSUM_UNNECESSARY) {
613 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
614 lro_flush_needed = 1;
615 } else
eaf5d590 616 netif_receive_skb(skb);
f61e5547
LB		 617
618 continue;
619
620err:
621 stats->rx_dropped++;
622
623 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
624 (RX_FIRST_DESC | RX_LAST_DESC)) {
625 if (net_ratelimit())
626 dev_printk(KERN_ERR, &mp->dev->dev,
627 "received packet spanning "
628 "multiple descriptors\n");
1da177e4 629 }
f61e5547
LB		 630
631 if (cmd_sts & ERROR_SUMMARY)
632 stats->rx_errors++;
633
634 dev_kfree_skb(skb);
1da177e4 635 }
fc32b0e2 636
eaf5d590
LB		 637 if (lro_flush_needed)
638 lro_flush_all(&rxq->lro_mgr);
eaf5d590 639
1fa38c58
LB		 640 if (rx < budget)
641 mp->work_rx &= ~(1 << rxq->index);
642
8a578111 643 return rx;
1da177e4
LT		 644}
645
1fa38c58 646static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 647{
1fa38c58 648 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 649 int refilled;
8a578111 650
1fa38c58
LB		 651 refilled = 0;
652 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
653 struct sk_buff *skb;
654 int unaligned;
655 int rx;
53771522 656 struct rx_desc *rx_desc;
d0412d96 657
2bcb4b0f
LB		 658 skb = __skb_dequeue(&mp->rx_recycle);
659 if (skb == NULL)
660 skb = dev_alloc_skb(mp->skb_size +
661 dma_get_cache_alignment() - 1);
662
1fa38c58 663 if (skb == NULL) {
1319ebad 664 mp->oom = 1;
1fa38c58
LB		 665 goto oom;
666 }
d0412d96 667
1fa38c58
LB		 668 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
669 if (unaligned)
670 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 671
1fa38c58
LB		 672 refilled++;
673 rxq->rx_desc_count++;
c9df406f 674
1fa38c58
LB		 675 rx = rxq->rx_used_desc++;
676 if (rxq->rx_used_desc == rxq->rx_ring_size)
677 rxq->rx_used_desc = 0;
2257e05c 678
53771522
LB		 679 rx_desc = rxq->rx_desc_area + rx;
680
681 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
682 mp->skb_size, DMA_FROM_DEVICE);
683 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 684 rxq->rx_skb[rx] = skb;
685 wmb();
53771522 686 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 687 wmb();
2257e05c 688
1fa38c58
LB		 689 /*
690 * The hardware automatically prepends 2 bytes of
691 * dummy data to each received packet, so that the
692 * IP header ends up 16-byte aligned.
693 */
694 skb_reserve(skb, 2);
695 }
696
697 if (refilled < budget)
698 mp->work_rx_refill &= ~(1 << rxq->index);
699
700oom:
701 return refilled;
d0412d96
JC		 702}
703
c9df406f
LB		 704
705/* tx ***********************************************************************/
c9df406f 706static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 707{
13d64285 708 int frag;
1da177e4 709
c9df406f 710 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 711 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
712 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 713 return 1;
1da177e4 714 }
13d64285 715
c9df406f
LB		 716 return 0;
717}
7303fde8 718
13d64285 719static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 720{
13d64285 721 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 722 int frag;
1da177e4 723
13d64285
LB		 724 for (frag = 0; frag < nr_frags; frag++) {
725 skb_frag_t *this_frag;
726 int tx_index;
727 struct tx_desc *desc;
728
729 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 730 tx_index = txq->tx_curr_desc++;
731 if (txq->tx_curr_desc == txq->tx_ring_size)
732 txq->tx_curr_desc = 0;
13d64285
LB		 733 desc = &txq->tx_desc_area[tx_index];
734
735 /*
736 * The last fragment will generate an interrupt
737 * which will free the skb on TX completion.
738 */
739 if (frag == nr_frags - 1) {
740 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
741 ZERO_PADDING | TX_LAST_DESC |
742 TX_ENABLE_INTERRUPT;
13d64285
LB		 743 } else {
744 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 745 }
746
c9df406f
LB		 747 desc->l4i_chk = 0;
748 desc->byte_cnt = this_frag->size;
749 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
750 this_frag->page_offset,
751 this_frag->size,
752 DMA_TO_DEVICE);
753 }
1da177e4
LT		 754}
755
c9df406f
LB		 756static inline __be16 sum16_as_be(__sum16 sum)
757{
758 return (__force __be16)sum;
759}
1da177e4 760
4df89bd5 761static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 762{
8fa89bf5 763 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 764 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 765 int tx_index;
cc9754b3 766 struct tx_desc *desc;
c9df406f 767 u32 cmd_sts;
4df89bd5 768 u16 l4i_chk;
c9df406f 769 int length;
1da177e4 770
cc9754b3 771 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 772 l4i_chk = 0;
c9df406f
LB		 773
774 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 775 int tag_bytes;
e32b6617
LB		 776
777 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
778 skb->protocol != htons(ETH_P_8021Q));
c9df406f 779
4df89bd5
LB		 780 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
781 if (unlikely(tag_bytes & ~12)) {
782 if (skb_checksum_help(skb) == 0)
783 goto no_csum;
784 kfree_skb(skb);
785 return 1;
786 }
c9df406f 787
4df89bd5 788 if (tag_bytes & 4)
e32b6617 789 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 790 if (tag_bytes & 8)
e32b6617 791 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 792
793 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
794 GEN_IP_V4_CHECKSUM |
795 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 796
c9df406f
LB		 797 switch (ip_hdr(skb)->protocol) {
798 case IPPROTO_UDP:
cc9754b3 799 cmd_sts |= UDP_FRAME;
4df89bd5 800 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 801 break;
802 case IPPROTO_TCP:
4df89bd5 803 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 804 break;
805 default:
806 BUG();
807 }
808 } else {
4df89bd5 809no_csum:
c9df406f 810 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 811 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 812 }
813
66823b92
LB		 814 tx_index = txq->tx_curr_desc++;
815 if (txq->tx_curr_desc == txq->tx_ring_size)
816 txq->tx_curr_desc = 0;
4df89bd5
LB		 817 desc = &txq->tx_desc_area[tx_index];
818
819 if (nr_frags) {
820 txq_submit_frag_skb(txq, skb);
821 length = skb_headlen(skb);
822 } else {
823 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
824 length = skb->len;
825 }
826
827 desc->l4i_chk = l4i_chk;
828 desc->byte_cnt = length;
829 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
830
99ab08e0
LB		 831 __skb_queue_tail(&txq->tx_skb, skb);
832
c9df406f
LB		 833 /* ensure all other descriptors are written before first cmd_sts */
834 wmb();
835 desc->cmd_sts = cmd_sts;
836
1fa38c58
LB		 837 /* clear TX_END status */
838 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 839
c9df406f
LB		 840 /* ensure all descriptors are written before poking hardware */
841 wmb();
13d64285 842 txq_enable(txq);
c9df406f 843
13d64285 844 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 845
846 return 0;
1da177e4 847}
1da177e4 848
fc32b0e2 849static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 850{
e5371493 851 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 852 int queue;
13d64285 853 struct tx_queue *txq;
e5ef1de1 854 struct netdev_queue *nq;
afdb57a2 855
8fd89211
LB		 856 queue = skb_get_queue_mapping(skb);
857 txq = mp->txq + queue;
858 nq = netdev_get_tx_queue(dev, queue);
859
c9df406f 860 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 861 txq->tx_dropped++;
fc32b0e2
LB		 862 dev_printk(KERN_DEBUG, &dev->dev,
863 "failed to linearize skb with tiny "
864 "unaligned fragment\n");
c9df406f
LB		 865 return NETDEV_TX_BUSY;
866 }
867
17cd0a59 868 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 869 if (net_ratelimit())
870 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 871 kfree_skb(skb);
872 return NETDEV_TX_OK;
c9df406f
LB		 873 }
874
4df89bd5
LB		 875 if (!txq_submit_skb(txq, skb)) {
876 int entries_left;
877
878 txq->tx_bytes += skb->len;
879 txq->tx_packets++;
880 dev->trans_start = jiffies;
c9df406f 881
4df89bd5
LB		 882 entries_left = txq->tx_ring_size - txq->tx_desc_count;
883 if (entries_left < MAX_SKB_FRAGS + 1)
884 netif_tx_stop_queue(nq);
885 }
c9df406f 886
c9df406f 887 return NETDEV_TX_OK;
1da177e4
LT		 888}
889
c9df406f 890
1fa38c58
LB		 891/* tx napi ******************************************************************/
892static void txq_kick(struct tx_queue *txq)
893{
894 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 895 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 896 u32 hw_desc_ptr;
897 u32 expected_ptr;
898
8fd89211 899 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 900
37a6084f 901 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 902 goto out;
903
37a6084f 904 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 905 expected_ptr = (u32)txq->tx_desc_dma +
906 txq->tx_curr_desc * sizeof(struct tx_desc);
907
908 if (hw_desc_ptr != expected_ptr)
909 txq_enable(txq);
910
911out:
8fd89211 912 __netif_tx_unlock(nq);
1fa38c58
LB		 913
914 mp->work_tx_end &= ~(1 << txq->index);
915}
916
917static int txq_reclaim(struct tx_queue *txq, int budget, int force)
918{
919 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 920 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 921 int reclaimed;
922
8fd89211 923 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 924
925 reclaimed = 0;
926 while (reclaimed < budget && txq->tx_desc_count > 0) {
927 int tx_index;
928 struct tx_desc *desc;
929 u32 cmd_sts;
930 struct sk_buff *skb;
1fa38c58
LB		 931
932 tx_index = txq->tx_used_desc;
933 desc = &txq->tx_desc_area[tx_index];
934 cmd_sts = desc->cmd_sts;
935
936 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
937 if (!force)
938 break;
939 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
940 }
941
942 txq->tx_used_desc = tx_index + 1;
943 if (txq->tx_used_desc == txq->tx_ring_size)
944 txq->tx_used_desc = 0;
945
946 reclaimed++;
947 txq->tx_desc_count--;
948
99ab08e0
LB		 949 skb = NULL;
950 if (cmd_sts & TX_LAST_DESC)
951 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 952
953 if (cmd_sts & ERROR_SUMMARY) {
954 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
955 mp->dev->stats.tx_errors++;
956 }
957
a418950c
LB		 958 if (cmd_sts & TX_FIRST_DESC) {
959 dma_unmap_single(NULL, desc->buf_ptr,
960 desc->byte_cnt, DMA_TO_DEVICE);
961 } else {
962 dma_unmap_page(NULL, desc->buf_ptr,
963 desc->byte_cnt, DMA_TO_DEVICE);
964 }
1fa38c58 965
2bcb4b0f
LB		 966 if (skb != NULL) {
967 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 968 mp->rx_ring_size &&
11b4aa03
LB		 969 skb_recycle_check(skb, mp->skb_size +
970 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 971 __skb_queue_head(&mp->rx_recycle, skb);
972 else
973 dev_kfree_skb(skb);
974 }
1fa38c58
LB		 975 }
976
8fd89211
LB		 977 __netif_tx_unlock(nq);
978
1fa38c58
LB		 979 if (reclaimed < budget)
980 mp->work_tx &= ~(1 << txq->index);
981
1fa38c58
LB		 982 return reclaimed;
983}
984
985
89df5fdc
LB		 986/* tx rate control **********************************************************/
987/*
988 * Set total maximum TX rate (shared by all TX queues for this port)
989 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
990 */
991static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
992{
993 int token_rate;
994 int mtu;
995 int bucket_size;
996
997 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
998 if (token_rate > 1023)
999 token_rate = 1023;
1000
1001 mtu = (mp->dev->mtu + 255) >> 8;
1002 if (mtu > 63)
1003 mtu = 63;
1004
1005 bucket_size = (burst + 255) >> 8;
1006 if (bucket_size > 65535)
1007 bucket_size = 65535;
1008
457b1d5a
LB		 1009 switch (mp->shared->tx_bw_control) {
1010 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1011 wrlp(mp, TX_BW_RATE, token_rate);
1012 wrlp(mp, TX_BW_MTU, mtu);
1013 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1014 break;
1015 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1016 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1017 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1018 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1019 break;
1e881592 1020 }
89df5fdc
LB		 1021}
1022
1023static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1024{
1025 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1026 int token_rate;
1027 int bucket_size;
1028
1029 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1030 if (token_rate > 1023)
1031 token_rate = 1023;
1032
1033 bucket_size = (burst + 255) >> 8;
1034 if (bucket_size > 65535)
1035 bucket_size = 65535;
1036
37a6084f
LB		 1037 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1038 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1039}
1040
1041static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1042{
1043 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1044 int off;
1045 u32 val;
1046
1047 /*
1048 * Turn on fixed priority mode.
1049 */
457b1d5a
LB		 1050 off = 0;
1051 switch (mp->shared->tx_bw_control) {
1052 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1053 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1054 break;
1055 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1056 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1057 break;
1058 }
89df5fdc 1059
457b1d5a 1060 if (off) {
37a6084f 1061 val = rdlp(mp, off);
457b1d5a 1062 val |= 1 << txq->index;
37a6084f 1063 wrlp(mp, off, val);
457b1d5a 1064 }
89df5fdc
LB		 1065}
1066
1067static void txq_set_wrr(struct tx_queue *txq, int weight)
1068{
1069 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1070 int off;
1071 u32 val;
1072
1073 /*
1074 * Turn off fixed priority mode.
1075 */
457b1d5a
LB		 1076 off = 0;
1077 switch (mp->shared->tx_bw_control) {
1078 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1079 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1080 break;
1081 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1082 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1083 break;
1084 }
89df5fdc 1085
457b1d5a 1086 if (off) {
37a6084f 1087 val = rdlp(mp, off);
457b1d5a 1088 val &= ~(1 << txq->index);
37a6084f 1089 wrlp(mp, off, val);
89df5fdc 1090
457b1d5a
LB		 1091 /*
1092 * Configure WRR weight for this queue.
1093 */
89df5fdc 1094
37a6084f 1095 val = rdlp(mp, off);
457b1d5a 1096 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1097 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1098 }
89df5fdc
LB		 1099}
1100
1101
c9df406f 1102/* mii management interface *************************************************/
45c5d3bc
LB		 1103static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1104{
1105 struct mv643xx_eth_shared_private *msp = dev_id;
1106
1107 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1108 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1109 wake_up(&msp->smi_busy_wait);
1110 return IRQ_HANDLED;
1111 }
1112
1113 return IRQ_NONE;
1114}
c9df406f 1115
45c5d3bc 1116static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1117{
45c5d3bc
LB		 1118 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1119}
1da177e4 1120
45c5d3bc
LB		 1121static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1122{
1123 if (msp->err_interrupt == NO_IRQ) {
1124 int i;
c9df406f 1125
45c5d3bc
LB		 1126 for (i = 0; !smi_is_done(msp); i++) {
1127 if (i == 10)
1128 return -ETIMEDOUT;
1129 msleep(10);
c9df406f 1130 }
45c5d3bc
LB		 1131
1132 return 0;
1133 }
1134
ee04448d
LB		 1135 if (!smi_is_done(msp)) {
1136 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1137 msecs_to_jiffies(100));
1138 if (!smi_is_done(msp))
1139 return -ETIMEDOUT;
1140 }
45c5d3bc
LB		 1141
1142 return 0;
1143}
1144
ed94493f 1145static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1146{
ed94493f 1147 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1148 void __iomem *smi_reg = msp->base + SMI_REG;
1149 int ret;
1150
45c5d3bc 1151 if (smi_wait_ready(msp)) {
10a9948d 1152 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1153 return -ETIMEDOUT;
1da177e4
LT		 1154 }
1155
fc32b0e2 1156 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1157
45c5d3bc 1158 if (smi_wait_ready(msp)) {
10a9948d 1159 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1160 return -ETIMEDOUT;
45c5d3bc
LB		 1161 }
1162
1163 ret = readl(smi_reg);
1164 if (!(ret & SMI_READ_VALID)) {
10a9948d 1165 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1166 return -ENODEV;
c9df406f
LB		 1167 }
1168
ed94493f 1169 return ret & 0xffff;
1da177e4
LT		 1170}
1171
ed94493f 1172static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1173{
ed94493f 1174 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1175 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1176
45c5d3bc 1177 if (smi_wait_ready(msp)) {
10a9948d 1178 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1179 return -ETIMEDOUT;
1da177e4
LT		 1180 }
1181
fc32b0e2 1182 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1183 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1184
ed94493f 1185 if (smi_wait_ready(msp)) {
10a9948d 1186 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1187 return -ETIMEDOUT;
1188 }
45c5d3bc
LB		 1189
1190 return 0;
c9df406f 1191}
1da177e4 1192
c9df406f 1193
8fd89211
LB		 1194/* statistics ***************************************************************/
1195static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1196{
1197 struct mv643xx_eth_private *mp = netdev_priv(dev);
1198 struct net_device_stats *stats = &dev->stats;
1199 unsigned long tx_packets = 0;
1200 unsigned long tx_bytes = 0;
1201 unsigned long tx_dropped = 0;
1202 int i;
1203
1204 for (i = 0; i < mp->txq_count; i++) {
1205 struct tx_queue *txq = mp->txq + i;
1206
1207 tx_packets += txq->tx_packets;
1208 tx_bytes += txq->tx_bytes;
1209 tx_dropped += txq->tx_dropped;
1210 }
1211
1212 stats->tx_packets = tx_packets;
1213 stats->tx_bytes = tx_bytes;
1214 stats->tx_dropped = tx_dropped;
1215
1216 return stats;
1217}
1218
eaf5d590
LB		 1219static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1220{
1221 u32 lro_aggregated = 0;
1222 u32 lro_flushed = 0;
1223 u32 lro_no_desc = 0;
1224 int i;
1225
eaf5d590
LB		 1226 for (i = 0; i < mp->rxq_count; i++) {
1227 struct rx_queue *rxq = mp->rxq + i;
1228
1229 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1230 lro_flushed += rxq->lro_mgr.stats.flushed;
1231 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1232 }
eaf5d590
LB		 1233
1234 mp->lro_counters.lro_aggregated = lro_aggregated;
1235 mp->lro_counters.lro_flushed = lro_flushed;
1236 mp->lro_counters.lro_no_desc = lro_no_desc;
1237}
1238
fc32b0e2 1239static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1240{
fc32b0e2 1241 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1242}
1243
fc32b0e2 1244static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1245{
fc32b0e2
LB		 1246 int i;
1247
1248 for (i = 0; i < 0x80; i += 4)
1249 mib_read(mp, i);
c9df406f 1250}
d0412d96 1251
fc32b0e2 1252static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1253{
e5371493 1254 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1255
57e8f26a 1256 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1257 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1258 p->bad_octets_received += mib_read(mp, 0x08);
1259 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1260 p->good_frames_received += mib_read(mp, 0x10);
1261 p->bad_frames_received += mib_read(mp, 0x14);
1262 p->broadcast_frames_received += mib_read(mp, 0x18);
1263 p->multicast_frames_received += mib_read(mp, 0x1c);
1264 p->frames_64_octets += mib_read(mp, 0x20);
1265 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1266 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1267 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1268 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1269 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1270 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1271 p->good_frames_sent += mib_read(mp, 0x40);
1272 p->excessive_collision += mib_read(mp, 0x44);
1273 p->multicast_frames_sent += mib_read(mp, 0x48);
1274 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1275 p->unrec_mac_control_received += mib_read(mp, 0x50);
1276 p->fc_sent += mib_read(mp, 0x54);
1277 p->good_fc_received += mib_read(mp, 0x58);
1278 p->bad_fc_received += mib_read(mp, 0x5c);
1279 p->undersize_received += mib_read(mp, 0x60);
1280 p->fragments_received += mib_read(mp, 0x64);
1281 p->oversize_received += mib_read(mp, 0x68);
1282 p->jabber_received += mib_read(mp, 0x6c);
1283 p->mac_receive_error += mib_read(mp, 0x70);
1284 p->bad_crc_event += mib_read(mp, 0x74);
1285 p->collision += mib_read(mp, 0x78);
1286 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1287 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1288
1289 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1290}
1291
1292static void mib_counters_timer_wrapper(unsigned long _mp)
1293{
1294 struct mv643xx_eth_private *mp = (void *)_mp;
1295
1296 mib_counters_update(mp);
d0412d96
JC		 1297}
1298
c9df406f 1299
3e508034
LB		 1300/* interrupt coalescing *****************************************************/
1301/*
1302 * Hardware coalescing parameters are set in units of 64 t_clk
1303 * cycles. I.e.:
1304 *
1305 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1306 *
1307 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1308 *
1309 * In the ->set*() methods, we round the computed register value
1310 * to the nearest integer.
1311 */
1312static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1313{
1314 u32 val = rdlp(mp, SDMA_CONFIG);
1315 u64 temp;
1316
1317 if (mp->shared->extended_rx_coal_limit)
1318 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1319 else
1320 temp = (val & 0x003fff00) >> 8;
1321
1322 temp *= 64000000;
1323 do_div(temp, mp->shared->t_clk);
1324
1325 return (unsigned int)temp;
1326}
1327
1328static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1329{
1330 u64 temp;
1331 u32 val;
1332
1333 temp = (u64)usec * mp->shared->t_clk;
1334 temp += 31999999;
1335 do_div(temp, 64000000);
1336
1337 val = rdlp(mp, SDMA_CONFIG);
1338 if (mp->shared->extended_rx_coal_limit) {
1339 if (temp > 0xffff)
1340 temp = 0xffff;
1341 val &= ~0x023fff80;
1342 val |= (temp & 0x8000) << 10;
1343 val |= (temp & 0x7fff) << 7;
1344 } else {
1345 if (temp > 0x3fff)
1346 temp = 0x3fff;
1347 val &= ~0x003fff00;
1348 val |= (temp & 0x3fff) << 8;
1349 }
1350 wrlp(mp, SDMA_CONFIG, val);
1351}
1352
1353static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1354{
1355 u64 temp;
1356
1357 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1358 temp *= 64000000;
1359 do_div(temp, mp->shared->t_clk);
1360
1361 return (unsigned int)temp;
1362}
1363
1364static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1365{
1366 u64 temp;
1367
1368 temp = (u64)usec * mp->shared->t_clk;
1369 temp += 31999999;
1370 do_div(temp, 64000000);
1371
1372 if (temp > 0x3fff)
1373 temp = 0x3fff;
1374
1375 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1376}
1377
1378
c9df406f 1379/* ethtool ******************************************************************/
e5371493 1380struct mv643xx_eth_stats {
c9df406f
LB		 1381 char stat_string[ETH_GSTRING_LEN];
1382 int sizeof_stat;
16820054
LB		 1383 int netdev_off;
1384 int mp_off;
c9df406f
LB		 1385};
1386
16820054
LB		 1387#define SSTAT(m) \
1388 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1389 offsetof(struct net_device, stats.m), -1 }
1390
1391#define MIBSTAT(m) \
1392 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1393 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1394
eaf5d590
LB		 1395#define LROSTAT(m) \
1396 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1397 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1398
16820054
LB		 1399static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1400 SSTAT(rx_packets),
1401 SSTAT(tx_packets),
1402 SSTAT(rx_bytes),
1403 SSTAT(tx_bytes),
1404 SSTAT(rx_errors),
1405 SSTAT(tx_errors),
1406 SSTAT(rx_dropped),
1407 SSTAT(tx_dropped),
1408 MIBSTAT(good_octets_received),
1409 MIBSTAT(bad_octets_received),
1410 MIBSTAT(internal_mac_transmit_err),
1411 MIBSTAT(good_frames_received),
1412 MIBSTAT(bad_frames_received),
1413 MIBSTAT(broadcast_frames_received),
1414 MIBSTAT(multicast_frames_received),
1415 MIBSTAT(frames_64_octets),
1416 MIBSTAT(frames_65_to_127_octets),
1417 MIBSTAT(frames_128_to_255_octets),
1418 MIBSTAT(frames_256_to_511_octets),
1419 MIBSTAT(frames_512_to_1023_octets),
1420 MIBSTAT(frames_1024_to_max_octets),
1421 MIBSTAT(good_octets_sent),
1422 MIBSTAT(good_frames_sent),
1423 MIBSTAT(excessive_collision),
1424 MIBSTAT(multicast_frames_sent),
1425 MIBSTAT(broadcast_frames_sent),
1426 MIBSTAT(unrec_mac_control_received),
1427 MIBSTAT(fc_sent),
1428 MIBSTAT(good_fc_received),
1429 MIBSTAT(bad_fc_received),
1430 MIBSTAT(undersize_received),
1431 MIBSTAT(fragments_received),
1432 MIBSTAT(oversize_received),
1433 MIBSTAT(jabber_received),
1434 MIBSTAT(mac_receive_error),
1435 MIBSTAT(bad_crc_event),
1436 MIBSTAT(collision),
1437 MIBSTAT(late_collision),
eaf5d590
LB		 1438 LROSTAT(lro_aggregated),
1439 LROSTAT(lro_flushed),
1440 LROSTAT(lro_no_desc),
c9df406f
LB		 1441};
1442
10a9948d 1443static int
6bdf576e
LB		 1444mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1445 struct ethtool_cmd *cmd)
d0412d96 1446{
d0412d96
JC		 1447 int err;
1448
ed94493f
LB		 1449 err = phy_read_status(mp->phy);
1450 if (err == 0)
1451 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1452
fc32b0e2
LB		 1453 /*
1454 * The MAC does not support 1000baseT_Half.
1455 */
d0412d96
JC		 1456 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1457 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1458
1459 return err;
1460}
1461
10a9948d 1462static int
6bdf576e 1463mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1464 struct ethtool_cmd *cmd)
bedfe324 1465{
81600eea
LB		 1466 u32 port_status;
1467
37a6084f 1468 port_status = rdlp(mp, PORT_STATUS);
81600eea 1469
bedfe324
LB		 1470 cmd->supported = SUPPORTED_MII;
1471 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1472 switch (port_status & PORT_SPEED_MASK) {
1473 case PORT_SPEED_10:
1474 cmd->speed = SPEED_10;
1475 break;
1476 case PORT_SPEED_100:
1477 cmd->speed = SPEED_100;
1478 break;
1479 case PORT_SPEED_1000:
1480 cmd->speed = SPEED_1000;
1481 break;
1482 default:
1483 cmd->speed = -1;
1484 break;
1485 }
1486 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1487 cmd->port = PORT_MII;
1488 cmd->phy_address = 0;
1489 cmd->transceiver = XCVR_INTERNAL;
1490 cmd->autoneg = AUTONEG_DISABLE;
1491 cmd->maxtxpkt = 1;
1492 cmd->maxrxpkt = 1;
1493
1494 return 0;
1495}
1496
6bdf576e
LB		 1497static int
1498mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1499{
1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
1501
1502 if (mp->phy != NULL)
1503 return mv643xx_eth_get_settings_phy(mp, cmd);
1504 else
1505 return mv643xx_eth_get_settings_phyless(mp, cmd);
1506}
1507
10a9948d
LB		 1508static int
1509mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1510{
e5371493 1511 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1512
6bdf576e
LB		 1513 if (mp->phy == NULL)
1514 return -EINVAL;
1515
fc32b0e2
LB		 1516 /*
1517 * The MAC does not support 1000baseT_Half.
1518 */
1519 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1520
ed94493f 1521 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1522}
1da177e4 1523
fc32b0e2
LB		 1524static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1525 struct ethtool_drvinfo *drvinfo)
c9df406f 1526{
e5371493
LB		 1527 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1528 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1529 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1530 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1531 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1532}
1da177e4 1533
fc32b0e2 1534static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1535{
e5371493 1536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1537
6bdf576e
LB		 1538 if (mp->phy == NULL)
1539 return -EINVAL;
1da177e4 1540
6bdf576e 1541 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1542}
1543
c9df406f
LB		 1544static u32 mv643xx_eth_get_link(struct net_device *dev)
1545{
ed94493f 1546 return !!netif_carrier_ok(dev);
bedfe324
LB		 1547}
1548
3e508034
LB		 1549static int
1550mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1551{
1552 struct mv643xx_eth_private *mp = netdev_priv(dev);
1553
1554 ec->rx_coalesce_usecs = get_rx_coal(mp);
1555 ec->tx_coalesce_usecs = get_tx_coal(mp);
1556
1557 return 0;
1558}
1559
1560static int
1561mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1562{
1563 struct mv643xx_eth_private *mp = netdev_priv(dev);
1564
1565 set_rx_coal(mp, ec->rx_coalesce_usecs);
1566 set_tx_coal(mp, ec->tx_coalesce_usecs);
1567
1568 return 0;
1569}
1570
e7d2f4db
LB		 1571static void
1572mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1573{
1574 struct mv643xx_eth_private *mp = netdev_priv(dev);
1575
1576 er->rx_max_pending = 4096;
1577 er->tx_max_pending = 4096;
1578 er->rx_mini_max_pending = 0;
1579 er->rx_jumbo_max_pending = 0;
1580
1581 er->rx_pending = mp->rx_ring_size;
1582 er->tx_pending = mp->tx_ring_size;
1583 er->rx_mini_pending = 0;
1584 er->rx_jumbo_pending = 0;
1585}
1586
1587static int
1588mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1589{
1590 struct mv643xx_eth_private *mp = netdev_priv(dev);
1591
1592 if (er->rx_mini_pending || er->rx_jumbo_pending)
1593 return -EINVAL;
1594
1595 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1596 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1597
1598 if (netif_running(dev)) {
1599 mv643xx_eth_stop(dev);
1600 if (mv643xx_eth_open(dev)) {
1601 dev_printk(KERN_ERR, &dev->dev,
1602 "fatal error on re-opening device after "
1603 "ring param change\n");
1604 return -ENOMEM;
1605 }
1606 }
1607
1608 return 0;
1609}
1610
d888b373
LB		 1611static u32
1612mv643xx_eth_get_rx_csum(struct net_device *dev)
1613{
1614 struct mv643xx_eth_private *mp = netdev_priv(dev);
1615
1616 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1617}
1618
1619static int
1620mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1621{
1622 struct mv643xx_eth_private *mp = netdev_priv(dev);
1623
1624 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1625
1626 return 0;
1627}
1628
fc32b0e2
LB		 1629static void mv643xx_eth_get_strings(struct net_device *dev,
1630 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1631{
1632 int i;
1da177e4 1633
fc32b0e2
LB		 1634 if (stringset == ETH_SS_STATS) {
1635 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1636 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1637 mv643xx_eth_stats[i].stat_string,
e5371493 1638 ETH_GSTRING_LEN);
c9df406f 1639 }
c9df406f
LB		 1640 }
1641}
1da177e4 1642
fc32b0e2
LB		 1643static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1644 struct ethtool_stats *stats,
1645 uint64_t *data)
c9df406f 1646{
b9873841 1647 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1648 int i;
1da177e4 1649
8fd89211 1650 mv643xx_eth_get_stats(dev);
fc32b0e2 1651 mib_counters_update(mp);
eaf5d590 1652 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1653
16820054
LB		 1654 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1655 const struct mv643xx_eth_stats *stat;
1656 void *p;
1657
1658 stat = mv643xx_eth_stats + i;
1659
1660 if (stat->netdev_off >= 0)
1661 p = ((void *)mp->dev) + stat->netdev_off;
1662 else
1663 p = ((void *)mp) + stat->mp_off;
1664
1665 data[i] = (stat->sizeof_stat == 8) ?
1666 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1667 }
c9df406f 1668}
1da177e4 1669
fc32b0e2 1670static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1671{
fc32b0e2 1672 if (sset == ETH_SS_STATS)
16820054 1673 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1674
1675 return -EOPNOTSUPP;
c9df406f 1676}
1da177e4 1677
e5371493 1678static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1679 .get_settings = mv643xx_eth_get_settings,
1680 .set_settings = mv643xx_eth_set_settings,
1681 .get_drvinfo = mv643xx_eth_get_drvinfo,
1682 .nway_reset = mv643xx_eth_nway_reset,
1683 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1684 .get_coalesce = mv643xx_eth_get_coalesce,
1685 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1686 .get_ringparam = mv643xx_eth_get_ringparam,
1687 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1688 .get_rx_csum = mv643xx_eth_get_rx_csum,
1689 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1690 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1691 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1692 .get_strings = mv643xx_eth_get_strings,
1693 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1694 .get_flags = ethtool_op_get_flags,
1695 .set_flags = ethtool_op_set_flags,
e5371493 1696 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1697};
1da177e4 1698
bea3348e 1699
c9df406f 1700/* address handling *********************************************************/
5daffe94 1701static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1702{
66e63ffb
LB		 1703 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1704 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1705
5daffe94
LB		 1706 addr[0] = (mac_h >> 24) & 0xff;
1707 addr[1] = (mac_h >> 16) & 0xff;
1708 addr[2] = (mac_h >> 8) & 0xff;
1709 addr[3] = mac_h & 0xff;
1710 addr[4] = (mac_l >> 8) & 0xff;
1711 addr[5] = mac_l & 0xff;
c9df406f 1712}
1da177e4 1713
66e63ffb 1714static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1715{
66e63ffb
LB		 1716 wrlp(mp, MAC_ADDR_HIGH,
1717 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1718 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1719}
d0412d96 1720
66e63ffb 1721static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1722{
66e63ffb
LB		 1723 struct dev_addr_list *uc_ptr;
1724 u32 nibbles;
1da177e4 1725
66e63ffb
LB		 1726 if (dev->flags & IFF_PROMISC)
1727 return 0;
1da177e4 1728
66e63ffb
LB		 1729 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1730 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1731 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1732 return 0;
1733 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1734 return 0;
ff561eef 1735
66e63ffb
LB		 1736 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1737 }
1da177e4 1738
66e63ffb 1739 return nibbles;
1da177e4
LT		 1740}
1741
66e63ffb 1742static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1743{
e5371493 1744 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1745 u32 port_config;
1746 u32 nibbles;
1747 int i;
1da177e4 1748
cc9754b3 1749 uc_addr_set(mp, dev->dev_addr);
1da177e4 1750
66e63ffb
LB		 1751 port_config = rdlp(mp, PORT_CONFIG);
1752 nibbles = uc_addr_filter_mask(dev);
1753 if (!nibbles) {
1754 port_config |= UNICAST_PROMISCUOUS_MODE;
1755 wrlp(mp, PORT_CONFIG, port_config);
1756 return;
1757 }
1758
1759 for (i = 0; i < 16; i += 4) {
1760 int off = UNICAST_TABLE(mp->port_num) + i;
1761 u32 v;
1762
1763 v = 0;
1764 if (nibbles & 1)
1765 v |= 0x00000001;
1766 if (nibbles & 2)
1767 v |= 0x00000100;
1768 if (nibbles & 4)
1769 v |= 0x00010000;
1770 if (nibbles & 8)
1771 v |= 0x01000000;
1772 nibbles >>= 4;
1773
1774 wrl(mp, off, v);
1775 }
1776
1777 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1778 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1779}
1780
69876569
LB		 1781static int addr_crc(unsigned char *addr)
1782{
1783 int crc = 0;
1784 int i;
1785
1786 for (i = 0; i < 6; i++) {
1787 int j;
1788
1789 crc = (crc ^ addr[i]) << 8;
1790 for (j = 7; j >= 0; j--) {
1791 if (crc & (0x100 << j))
1792 crc ^= 0x107 << j;
1793 }
1794 }
1795
1796 return crc;
1797}
1798
66e63ffb 1799static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1800{
fc32b0e2 1801 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1802 u32 *mc_spec;
1803 u32 *mc_other;
fc32b0e2
LB		 1804 struct dev_addr_list *addr;
1805 int i;
c8aaea25 1806
fc32b0e2 1807 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1808 int port_num;
1809 u32 accept;
c8aaea25 1810
66e63ffb
LB		 1811oom:
1812 port_num = mp->port_num;
1813 accept = 0x01010101;
fc32b0e2
LB		 1814 for (i = 0; i < 0x100; i += 4) {
1815 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1816 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1817 }
1818 return;
1819 }
c8aaea25 1820
82a5bd6a 1821 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1822 if (mc_spec == NULL)
1823 goto oom;
1824 mc_other = mc_spec + (0x100 >> 2);
1825
1826 memset(mc_spec, 0, 0x100);
1827 memset(mc_other, 0, 0x100);
1da177e4 1828
fc32b0e2
LB		 1829 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1830 u8 *a = addr->da_addr;
66e63ffb
LB		 1831 u32 *table;
1832 int entry;
1da177e4 1833
fc32b0e2 1834 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1835 table = mc_spec;
1836 entry = a[5];
fc32b0e2 1837 } else {
66e63ffb
LB		 1838 table = mc_other;
1839 entry = addr_crc(a);
fc32b0e2 1840 }
66e63ffb 1841
2b448334 1842 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1843 }
66e63ffb
LB		 1844
1845 for (i = 0; i < 0x100; i += 4) {
1846 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1847 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1848 }
1849
1850 kfree(mc_spec);
1851}
1852
1853static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1854{
1855 mv643xx_eth_program_unicast_filter(dev);
1856 mv643xx_eth_program_multicast_filter(dev);
1857}
1858
1859static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1860{
1861 struct sockaddr *sa = addr;
1862
1863 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1864
1865 netif_addr_lock_bh(dev);
1866 mv643xx_eth_program_unicast_filter(dev);
1867 netif_addr_unlock_bh(dev);
1868
1869 return 0;
c9df406f 1870}
c8aaea25 1871
c8aaea25 1872
c9df406f 1873/* rx/tx queue initialisation ***********************************************/
64da80a2 1874static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1875{
64da80a2 1876 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1877 struct rx_desc *rx_desc;
1878 int size;
c9df406f
LB		 1879 int i;
1880
64da80a2
LB		 1881 rxq->index = index;
1882
e7d2f4db 1883 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1884
1885 rxq->rx_desc_count = 0;
1886 rxq->rx_curr_desc = 0;
1887 rxq->rx_used_desc = 0;
1888
1889 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1890
f7981c1c 1891 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1892 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1893 mp->rx_desc_sram_size);
1894 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1895 } else {
1896 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1897 &rxq->rx_desc_dma,
1898 GFP_KERNEL);
f7ea3337
PJ		 1899 }
1900
8a578111
LB		 1901 if (rxq->rx_desc_area == NULL) {
1902 dev_printk(KERN_ERR, &mp->dev->dev,
1903 "can't allocate rx ring (%d bytes)\n", size);
1904 goto out;
1905 }
1906 memset(rxq->rx_desc_area, 0, size);
1da177e4 1907
8a578111
LB		 1908 rxq->rx_desc_area_size = size;
1909 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1910 GFP_KERNEL);
1911 if (rxq->rx_skb == NULL) {
1912 dev_printk(KERN_ERR, &mp->dev->dev,
1913 "can't allocate rx skb ring\n");
1914 goto out_free;
1915 }
1916
1917 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1918 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1919 int nexti;
1920
1921 nexti = i + 1;
1922 if (nexti == rxq->rx_ring_size)
1923 nexti = 0;
1924
8a578111
LB		 1925 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1926 nexti * sizeof(struct rx_desc);
1927 }
1928
eaf5d590
LB		 1929 rxq->lro_mgr.dev = mp->dev;
1930 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1931 rxq->lro_mgr.features = LRO_F_NAPI;
1932 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1933 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1934 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1935 rxq->lro_mgr.max_aggr = 32;
1936 rxq->lro_mgr.frag_align_pad = 0;
1937 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1938 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1939
1940 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1941
8a578111
LB		 1942 return 0;
1943
1944
1945out_free:
f7981c1c 1946 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1947 iounmap(rxq->rx_desc_area);
1948 else
1949 dma_free_coherent(NULL, size,
1950 rxq->rx_desc_area,
1951 rxq->rx_desc_dma);
1952
1953out:
1954 return -ENOMEM;
c9df406f 1955}
c8aaea25 1956
8a578111 1957static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1958{
8a578111
LB		 1959 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1960 int i;
1961
1962 rxq_disable(rxq);
c8aaea25 1963
8a578111
LB		 1964 for (i = 0; i < rxq->rx_ring_size; i++) {
1965 if (rxq->rx_skb[i]) {
1966 dev_kfree_skb(rxq->rx_skb[i]);
1967 rxq->rx_desc_count--;
1da177e4 1968 }
c8aaea25 1969 }
1da177e4 1970
8a578111
LB		 1971 if (rxq->rx_desc_count) {
1972 dev_printk(KERN_ERR, &mp->dev->dev,
1973 "error freeing rx ring -- %d skbs stuck\n",
1974 rxq->rx_desc_count);
1975 }
1976
f7981c1c 1977 if (rxq->index == 0 &&
64da80a2 1978 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1979 iounmap(rxq->rx_desc_area);
c9df406f 1980 else
8a578111
LB		 1981 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1982 rxq->rx_desc_area, rxq->rx_desc_dma);
1983
1984 kfree(rxq->rx_skb);
c9df406f 1985}
1da177e4 1986
3d6b35bc 1987static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1988{
3d6b35bc 1989 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1990 struct tx_desc *tx_desc;
1991 int size;
c9df406f 1992 int i;
1da177e4 1993
3d6b35bc
LB		 1994 txq->index = index;
1995
e7d2f4db 1996 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1997
1998 txq->tx_desc_count = 0;
1999 txq->tx_curr_desc = 0;
2000 txq->tx_used_desc = 0;
2001
2002 size = txq->tx_ring_size * sizeof(struct tx_desc);
2003
f7981c1c 2004 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 2005 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2006 mp->tx_desc_sram_size);
2007 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2008 } else {
2009 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
2010 &txq->tx_desc_dma,
2011 GFP_KERNEL);
2012 }
2013
2014 if (txq->tx_desc_area == NULL) {
2015 dev_printk(KERN_ERR, &mp->dev->dev,
2016 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 2017 return -ENOMEM;
c9df406f 2018 }
13d64285
LB		 2019 memset(txq->tx_desc_area, 0, size);
2020
2021 txq->tx_desc_area_size = size;
13d64285
LB		 2022
2023 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2024 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2025 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2026 int nexti;
2027
2028 nexti = i + 1;
2029 if (nexti == txq->tx_ring_size)
2030 nexti = 0;
6b368f68
LB		 2031
2032 txd->cmd_sts = 0;
2033 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2034 nexti * sizeof(struct tx_desc);
2035 }
2036
99ab08e0 2037 skb_queue_head_init(&txq->tx_skb);
c9df406f 2038
99ab08e0 2039 return 0;
c8aaea25 2040}
1da177e4 2041
13d64285 2042static void txq_deinit(struct tx_queue *txq)
c9df406f 2043{
13d64285 2044 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2045
13d64285 2046 txq_disable(txq);
1fa38c58 2047 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2048
13d64285 2049 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2050
f7981c1c 2051 if (txq->index == 0 &&
3d6b35bc 2052 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2053 iounmap(txq->tx_desc_area);
c9df406f 2054 else
13d64285
LB		 2055 dma_free_coherent(NULL, txq->tx_desc_area_size,
2056 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2057}
1da177e4 2058
1da177e4 2059
c9df406f 2060/* netdev ops and related ***************************************************/
1fa38c58
LB		 2061static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2062{
2063 u32 int_cause;
2064 u32 int_cause_ext;
2065
37a6084f 2066 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1fa38c58
LB		 2067 if (int_cause == 0)
2068 return 0;
2069
2070 int_cause_ext = 0;
2071 if (int_cause & INT_EXT)
37a6084f 2072 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1fa38c58
LB		 2073
2074 int_cause &= INT_TX_END | INT_RX;
2075 if (int_cause) {
37a6084f 2076 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2077 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2078 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2079 mp->work_rx |= (int_cause & INT_RX) >> 2;
2080 }
2081
2082 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2083 if (int_cause_ext) {
37a6084f 2084 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2085 if (int_cause_ext & INT_EXT_LINK_PHY)
2086 mp->work_link = 1;
2087 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2088 }
2089
2090 return 1;
2091}
2092
2093static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2094{
2095 struct net_device *dev = (struct net_device *)dev_id;
2096 struct mv643xx_eth_private *mp = netdev_priv(dev);
2097
2098 if (unlikely(!mv643xx_eth_collect_events(mp)))
2099 return IRQ_NONE;
2100
37a6084f 2101 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2102 napi_schedule(&mp->napi);
2103
2104 return IRQ_HANDLED;
2105}
2106
2f7eb47a
LB		 2107static void handle_link_event(struct mv643xx_eth_private *mp)
2108{
2109 struct net_device *dev = mp->dev;
2110 u32 port_status;
2111 int speed;
2112 int duplex;
2113 int fc;
2114
37a6084f 2115 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2116 if (!(port_status & LINK_UP)) {
2117 if (netif_carrier_ok(dev)) {
2118 int i;
2119
2120 printk(KERN_INFO "%s: link down\n", dev->name);
2121
2122 netif_carrier_off(dev);
2f7eb47a 2123
f7981c1c 2124 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2125 struct tx_queue *txq = mp->txq + i;
2126
1fa38c58 2127 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2128 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2129 }
2130 }
2131 return;
2132 }
2133
2134 switch (port_status & PORT_SPEED_MASK) {
2135 case PORT_SPEED_10:
2136 speed = 10;
2137 break;
2138 case PORT_SPEED_100:
2139 speed = 100;
2140 break;
2141 case PORT_SPEED_1000:
2142 speed = 1000;
2143 break;
2144 default:
2145 speed = -1;
2146 break;
2147 }
2148 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2149 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2150
2151 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2152 "flow control %sabled\n", dev->name,
2153 speed, duplex ? "full" : "half",
2154 fc ? "en" : "dis");
2155
4fdeca3f 2156 if (!netif_carrier_ok(dev))
2f7eb47a 2157 netif_carrier_on(dev);
2f7eb47a
LB		 2158}
2159
1fa38c58 2160static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2161{
1fa38c58
LB		 2162 struct mv643xx_eth_private *mp;
2163 int work_done;
ce4e2e45 2164
1fa38c58 2165 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2166
1319ebad
LB		 2167 if (unlikely(mp->oom)) {
2168 mp->oom = 0;
2169 del_timer(&mp->rx_oom);
2170 }
1da177e4 2171
1fa38c58
LB		 2172 work_done = 0;
2173 while (work_done < budget) {
2174 u8 queue_mask;
2175 int queue;
2176 int work_tbd;
2177
2178 if (mp->work_link) {
2179 mp->work_link = 0;
2180 handle_link_event(mp);
2181 continue;
2182 }
1da177e4 2183
1319ebad
LB		 2184 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2185 if (likely(!mp->oom))
2186 queue_mask |= mp->work_rx_refill;
2187
1fa38c58
LB		 2188 if (!queue_mask) {
2189 if (mv643xx_eth_collect_events(mp))
2190 continue;
2191 break;
2192 }
1da177e4 2193
1fa38c58
LB		 2194 queue = fls(queue_mask) - 1;
2195 queue_mask = 1 << queue;
2196
2197 work_tbd = budget - work_done;
2198 if (work_tbd > 16)
2199 work_tbd = 16;
2200
2201 if (mp->work_tx_end & queue_mask) {
2202 txq_kick(mp->txq + queue);
2203 } else if (mp->work_tx & queue_mask) {
2204 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2205 txq_maybe_wake(mp->txq + queue);
2206 } else if (mp->work_rx & queue_mask) {
2207 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2208 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2209 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2210 } else {
2211 BUG();
2212 }
84dd619e 2213 }
fc32b0e2 2214
1fa38c58 2215 if (work_done < budget) {
1319ebad 2216 if (mp->oom)
1fa38c58
LB		 2217 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2218 napi_complete(napi);
37a6084f 2219 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
226bb6b7 2220 }
3d6b35bc 2221
1fa38c58
LB		 2222 return work_done;
2223}
8fa89bf5 2224
1fa38c58
LB		 2225static inline void oom_timer_wrapper(unsigned long data)
2226{
2227 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2228
1fa38c58 2229 napi_schedule(&mp->napi);
1da177e4
LT		 2230}
2231
e5371493 2232static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2233{
45c5d3bc
LB		 2234 int data;
2235
ed94493f 2236 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2237 if (data < 0)
2238 return;
1da177e4 2239
7f106c1d 2240 data |= BMCR_RESET;
ed94493f 2241 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2242 return;
1da177e4 2243
c9df406f 2244 do {
ed94493f 2245 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2246 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2247}
2248
fc32b0e2 2249static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2250{
d0412d96 2251 u32 pscr;
8a578111 2252 int i;
1da177e4 2253
bedfe324
LB		 2254 /*
2255 * Perform PHY reset, if there is a PHY.
2256 */
ed94493f 2257 if (mp->phy != NULL) {
bedfe324
LB		 2258 struct ethtool_cmd cmd;
2259
2260 mv643xx_eth_get_settings(mp->dev, &cmd);
2261 phy_reset(mp);
2262 mv643xx_eth_set_settings(mp->dev, &cmd);
2263 }
1da177e4 2264
81600eea
LB		 2265 /*
2266 * Configure basic link parameters.
2267 */
37a6084f 2268 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2269
2270 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2271 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2272
2273 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2274 if (mp->phy == NULL)
81600eea 2275 pscr |= FORCE_LINK_PASS;
37a6084f 2276 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2277
13d64285
LB		 2278 /*
2279 * Configure TX path and queues.
2280 */
89df5fdc 2281 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2282 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2283 struct tx_queue *txq = mp->txq + i;
13d64285 2284
6b368f68 2285 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2286 txq_set_rate(txq, 1000000000, 16777216);
2287 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2288 }
2289
d9a073ea
LB		 2290 /*
2291 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2292 * frames to RX queue #0, and include the pseudo-header when
2293 * calculating receive checksums.
d9a073ea 2294 */
37a6084f 2295 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2296
376489a2
LB		 2297 /*
2298 * Treat BPDUs as normal multicasts, and disable partition mode.
2299 */
37a6084f 2300 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2301
5a893922
LB		 2302 /*
2303 * Add configured unicast addresses to address filter table.
2304 */
2305 mv643xx_eth_program_unicast_filter(mp->dev);
2306
8a578111 2307 /*
64da80a2 2308 * Enable the receive queues.
8a578111 2309 */
f7981c1c 2310 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2311 struct rx_queue *rxq = mp->rxq + i;
8a578111 2312 u32 addr;
1da177e4 2313
8a578111
LB		 2314 addr = (u32)rxq->rx_desc_dma;
2315 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2316 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2317
8a578111
LB		 2318 rxq_enable(rxq);
2319 }
1da177e4
LT		 2320}
2321
2bcb4b0f
LB		 2322static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2323{
2324 int skb_size;
2325
2326 /*
2327 * Reserve 2+14 bytes for an ethernet header (the hardware
2328 * automatically prepends 2 bytes of dummy data to each
2329 * received packet), 16 bytes for up to four VLAN tags, and
2330 * 4 bytes for the trailing FCS -- 36 bytes total.
2331 */
2332 skb_size = mp->dev->mtu + 36;
2333
2334 /*
2335 * Make sure that the skb size is a multiple of 8 bytes, as
2336 * the lower three bits of the receive descriptor's buffer
2337 * size field are ignored by the hardware.
2338 */
2339 mp->skb_size = (skb_size + 7) & ~7;
2340}
2341
c9df406f 2342static int mv643xx_eth_open(struct net_device *dev)
16e03018 2343{
e5371493 2344 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2345 int err;
64da80a2 2346 int i;
16e03018 2347
37a6084f
LB		 2348 wrlp(mp, INT_CAUSE, 0);
2349 wrlp(mp, INT_CAUSE_EXT, 0);
2350 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2351
fc32b0e2 2352 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2353 IRQF_SHARED, dev->name, dev);
c9df406f 2354 if (err) {
fc32b0e2 2355 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2356 return -EAGAIN;
16e03018
DF		 2357 }
2358
2bcb4b0f
LB		 2359 mv643xx_eth_recalc_skb_size(mp);
2360
2257e05c
LB		 2361 napi_enable(&mp->napi);
2362
2bcb4b0f
LB		 2363 skb_queue_head_init(&mp->rx_recycle);
2364
f7981c1c 2365 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2366 err = rxq_init(mp, i);
2367 if (err) {
2368 while (--i >= 0)
f7981c1c 2369 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2370 goto out;
2371 }
2372
1fa38c58 2373 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2374 }
2375
1319ebad 2376 if (mp->oom) {
2257e05c
LB		 2377 mp->rx_oom.expires = jiffies + (HZ / 10);
2378 add_timer(&mp->rx_oom);
64da80a2 2379 }
8a578111 2380
f7981c1c 2381 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2382 err = txq_init(mp, i);
2383 if (err) {
2384 while (--i >= 0)
f7981c1c 2385 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2386 goto out_free;
2387 }
2388 }
16e03018 2389
fc32b0e2 2390 port_start(mp);
16e03018 2391
37a6084f
LB		 2392 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2393 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
16e03018 2394
c9df406f
LB		 2395 return 0;
2396
13d64285 2397
fc32b0e2 2398out_free:
f7981c1c
LB		 2399 for (i = 0; i < mp->rxq_count; i++)
2400 rxq_deinit(mp->rxq + i);
fc32b0e2 2401out:
c9df406f
LB		 2402 free_irq(dev->irq, dev);
2403
2404 return err;
16e03018
DF		 2405}
2406
e5371493 2407static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2408{
fc32b0e2 2409 unsigned int data;
64da80a2 2410 int i;
1da177e4 2411
f7981c1c
LB		 2412 for (i = 0; i < mp->rxq_count; i++)
2413 rxq_disable(mp->rxq + i);
2414 for (i = 0; i < mp->txq_count; i++)
2415 txq_disable(mp->txq + i);
ae9ae064
LB		 2416
2417 while (1) {
37a6084f 2418 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2419
2420 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2421 break;
13d64285 2422 udelay(10);
ae9ae064 2423 }
1da177e4 2424
c9df406f 2425 /* Reset the Enable bit in the Configuration Register */
37a6084f 2426 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2427 data &= ~(SERIAL_PORT_ENABLE |
2428 DO_NOT_FORCE_LINK_FAIL |
2429 FORCE_LINK_PASS);
37a6084f 2430 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2431}
2432
c9df406f 2433static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2434{
e5371493 2435 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2436 int i;
1da177e4 2437
fe65e704 2438 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2439 wrlp(mp, INT_MASK, 0x00000000);
2440 rdlp(mp, INT_MASK);
1da177e4 2441
c9df406f 2442 napi_disable(&mp->napi);
78fff83b 2443
2257e05c
LB		 2444 del_timer_sync(&mp->rx_oom);
2445
c9df406f 2446 netif_carrier_off(dev);
1da177e4 2447
fc32b0e2
LB		 2448 free_irq(dev->irq, dev);
2449
cc9754b3 2450 port_reset(mp);
8fd89211 2451 mv643xx_eth_get_stats(dev);
fc32b0e2 2452 mib_counters_update(mp);
57e8f26a 2453 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2454
2bcb4b0f
LB		 2455 skb_queue_purge(&mp->rx_recycle);
2456
f7981c1c
LB		 2457 for (i = 0; i < mp->rxq_count; i++)
2458 rxq_deinit(mp->rxq + i);
2459 for (i = 0; i < mp->txq_count; i++)
2460 txq_deinit(mp->txq + i);
1da177e4 2461
c9df406f 2462 return 0;
1da177e4
LT		 2463}
2464
fc32b0e2 2465static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2466{
e5371493 2467 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2468
ed94493f
LB		 2469 if (mp->phy != NULL)
2470 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2471
2472 return -EOPNOTSUPP;
1da177e4
LT		 2473}
2474
c9df406f 2475static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2476{
89df5fdc
LB		 2477 struct mv643xx_eth_private *mp = netdev_priv(dev);
2478
fc32b0e2 2479 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2480 return -EINVAL;
1da177e4 2481
c9df406f 2482 dev->mtu = new_mtu;
2bcb4b0f 2483 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2484 tx_set_rate(mp, 1000000000, 16777216);
2485
c9df406f
LB		 2486 if (!netif_running(dev))
2487 return 0;
1da177e4 2488
c9df406f
LB		 2489 /*
2490 * Stop and then re-open the interface. This will allocate RX
2491 * skbs of the new MTU.
2492 * There is a possible danger that the open will not succeed,
fc32b0e2 2493 * due to memory being full.
c9df406f
LB		 2494 */
2495 mv643xx_eth_stop(dev);
2496 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2497 dev_printk(KERN_ERR, &dev->dev,
2498 "fatal error on re-opening device after "
2499 "MTU change\n");
c9df406f
LB		 2500 }
2501
2502 return 0;
1da177e4
LT		 2503}
2504
fc32b0e2 2505static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2506{
fc32b0e2 2507 struct mv643xx_eth_private *mp;
1da177e4 2508
fc32b0e2
LB		 2509 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2510 if (netif_running(mp->dev)) {
e5ef1de1 2511 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2512 port_reset(mp);
2513 port_start(mp);
e5ef1de1 2514 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2515 }
c9df406f
LB		 2516}
2517
c9df406f 2518static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2519{
e5371493 2520 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2521
fc32b0e2 2522 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2523
c9df406f 2524 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2525}
2526
c9df406f 2527#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2528static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2529{
fc32b0e2 2530 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2531
37a6084f
LB		 2532 wrlp(mp, INT_MASK, 0x00000000);
2533 rdlp(mp, INT_MASK);
c9df406f 2534
fc32b0e2 2535 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2536
37a6084f 2537 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2538}
c9df406f 2539#endif
9f8dd319 2540
9f8dd319 2541
c9df406f 2542/* platform glue ************************************************************/
e5371493
LB		 2543static void
2544mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2545 struct mbus_dram_target_info *dram)
c9df406f 2546{
cc9754b3 2547 void __iomem *base = msp->base;
c9df406f
LB		 2548 u32 win_enable;
2549 u32 win_protect;
2550 int i;
9f8dd319 2551
c9df406f
LB		 2552 for (i = 0; i < 6; i++) {
2553 writel(0, base + WINDOW_BASE(i));
2554 writel(0, base + WINDOW_SIZE(i));
2555 if (i < 4)
2556 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2557 }
2558
c9df406f
LB		 2559 win_enable = 0x3f;
2560 win_protect = 0;
2561
2562 for (i = 0; i < dram->num_cs; i++) {
2563 struct mbus_dram_window *cs = dram->cs + i;
2564
2565 writel((cs->base & 0xffff0000) |
2566 (cs->mbus_attr << 8) |
2567 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2568 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2569
2570 win_enable &= ~(1 << i);
2571 win_protect |= 3 << (2 * i);
2572 }
2573
2574 writel(win_enable, base + WINDOW_BAR_ENABLE);
2575 msp->win_protect = win_protect;
9f8dd319
DF		 2576}
2577
773fc3ee
LB		 2578static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2579{
2580 /*
2581 * Check whether we have a 14-bit coal limit field in bits
2582 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2583 * SDMA config register.
2584 */
37a6084f
LB		 2585 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2586 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2587 msp->extended_rx_coal_limit = 1;
2588 else
2589 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2590
2591 /*
457b1d5a
LB		 2592 * Check whether the MAC supports TX rate control, and if
2593 * yes, whether its associated registers are in the old or
2594 * the new place.
1e881592 2595 */
37a6084f
LB		 2596 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2597 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2598 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2599 } else {
37a6084f
LB		 2600 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2601 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2602 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2603 else
2604 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2605 }
773fc3ee
LB		 2606}
2607
c9df406f 2608static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2609{
10a9948d 2610 static int mv643xx_eth_version_printed;
c9df406f 2611 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2612 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2613 struct resource *res;
2614 int ret;
9f8dd319 2615
e5371493 2616 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2617 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2618 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2619
c9df406f
LB		 2620 ret = -EINVAL;
2621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2622 if (res == NULL)
2623 goto out;
9f8dd319 2624
c9df406f
LB		 2625 ret = -ENOMEM;
2626 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2627 if (msp == NULL)
2628 goto out;
2629 memset(msp, 0, sizeof(*msp));
2630
cc9754b3
LB		 2631 msp->base = ioremap(res->start, res->end - res->start + 1);
2632 if (msp->base == NULL)
c9df406f
LB		 2633 goto out_free;
2634
ed94493f
LB		 2635 /*
2636 * Set up and register SMI bus.
2637 */
2638 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2639 msp->smi_bus = mdiobus_alloc();
2640 if (msp->smi_bus == NULL)
ed94493f 2641 goto out_unmap;
298cf9be
LB		 2642
2643 msp->smi_bus->priv = msp;
2644 msp->smi_bus->name = "mv643xx_eth smi";
2645 msp->smi_bus->read = smi_bus_read;
2646 msp->smi_bus->write = smi_bus_write,
2647 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2648 msp->smi_bus->parent = &pdev->dev;
2649 msp->smi_bus->phy_mask = 0xffffffff;
2650 if (mdiobus_register(msp->smi_bus) < 0)
2651 goto out_free_mii_bus;
ed94493f
LB		 2652 msp->smi = msp;
2653 } else {
fc0eb9f2 2654 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2655 }
c9df406f 2656
45c5d3bc
LB		 2657 msp->err_interrupt = NO_IRQ;
2658 init_waitqueue_head(&msp->smi_busy_wait);
2659
2660 /*
2661 * Check whether the error interrupt is hooked up.
2662 */
2663 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2664 if (res != NULL) {
2665 int err;
2666
2667 err = request_irq(res->start, mv643xx_eth_err_irq,
2668 IRQF_SHARED, "mv643xx_eth", msp);
2669 if (!err) {
2670 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2671 msp->err_interrupt = res->start;
2672 }
2673 }
2674
c9df406f
LB		 2675 /*
2676 * (Re-)program MBUS remapping windows if we are asked to.
2677 */
2678 if (pd != NULL && pd->dram != NULL)
2679 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2680
fc32b0e2
LB		 2681 /*
2682 * Detect hardware parameters.
2683 */
2684 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2685 infer_hw_params(msp);
fc32b0e2
LB		 2686
2687 platform_set_drvdata(pdev, msp);
2688
c9df406f
LB		 2689 return 0;
2690
298cf9be
LB		 2691out_free_mii_bus:
2692 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2693out_unmap:
2694 iounmap(msp->base);
c9df406f
LB		 2695out_free:
2696 kfree(msp);
2697out:
2698 return ret;
2699}
2700
2701static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2702{
e5371493 2703 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2704 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2705
298cf9be 2706 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2707 mdiobus_unregister(msp->smi_bus);
bcb3336c 2708 mdiobus_free(msp->smi_bus);
298cf9be 2709 }
45c5d3bc
LB		 2710 if (msp->err_interrupt != NO_IRQ)
2711 free_irq(msp->err_interrupt, msp);
cc9754b3 2712 iounmap(msp->base);
c9df406f
LB		 2713 kfree(msp);
2714
2715 return 0;
9f8dd319
DF		 2716}
2717
c9df406f 2718static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2719 .probe = mv643xx_eth_shared_probe,
2720 .remove = mv643xx_eth_shared_remove,
c9df406f 2721 .driver = {
fc32b0e2 2722 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2723 .owner = THIS_MODULE,
2724 },
2725};
2726
e5371493 2727static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2728{
c9df406f 2729 int addr_shift = 5 * mp->port_num;
fc32b0e2 2730 u32 data;
1da177e4 2731
fc32b0e2
LB		 2732 data = rdl(mp, PHY_ADDR);
2733 data &= ~(0x1f << addr_shift);
2734 data |= (phy_addr & 0x1f) << addr_shift;
2735 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2736}
2737
e5371493 2738static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2739{
fc32b0e2
LB		 2740 unsigned int data;
2741
2742 data = rdl(mp, PHY_ADDR);
2743
2744 return (data >> (5 * mp->port_num)) & 0x1f;
2745}
2746
2747static void set_params(struct mv643xx_eth_private *mp,
2748 struct mv643xx_eth_platform_data *pd)
2749{
2750 struct net_device *dev = mp->dev;
2751
2752 if (is_valid_ether_addr(pd->mac_addr))
2753 memcpy(dev->dev_addr, pd->mac_addr, 6);
2754 else
2755 uc_addr_get(mp, dev->dev_addr);
2756
e7d2f4db 2757 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2758 if (pd->rx_queue_size)
e7d2f4db 2759 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2760 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2761 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2762
f7981c1c 2763 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2764
e7d2f4db 2765 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2766 if (pd->tx_queue_size)
e7d2f4db 2767 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2768 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2769 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2770
f7981c1c 2771 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2772}
2773
ed94493f
LB		 2774static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2775 int phy_addr)
1da177e4 2776{
298cf9be 2777 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2778 struct phy_device *phydev;
2779 int start;
2780 int num;
2781 int i;
45c5d3bc 2782
ed94493f
LB		 2783 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2784 start = phy_addr_get(mp) & 0x1f;
2785 num = 32;
2786 } else {
2787 start = phy_addr & 0x1f;
2788 num = 1;
2789 }
45c5d3bc 2790
ed94493f
LB		 2791 phydev = NULL;
2792 for (i = 0; i < num; i++) {
2793 int addr = (start + i) & 0x1f;
fc32b0e2 2794
ed94493f
LB		 2795 if (bus->phy_map[addr] == NULL)
2796 mdiobus_scan(bus, addr);
1da177e4 2797
ed94493f
LB		 2798 if (phydev == NULL) {
2799 phydev = bus->phy_map[addr];
2800 if (phydev != NULL)
2801 phy_addr_set(mp, addr);
2802 }
2803 }
1da177e4 2804
ed94493f 2805 return phydev;
1da177e4
LT		 2806}
2807
ed94493f 2808static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2809{
ed94493f 2810 struct phy_device *phy = mp->phy;
c28a4f89 2811
fc32b0e2
LB		 2812 phy_reset(mp);
2813
db1d7bf7 2814 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2815
2816 if (speed == 0) {
2817 phy->autoneg = AUTONEG_ENABLE;
2818 phy->speed = 0;
2819 phy->duplex = 0;
2820 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2821 } else {
ed94493f
LB		 2822 phy->autoneg = AUTONEG_DISABLE;
2823 phy->advertising = 0;
2824 phy->speed = speed;
2825 phy->duplex = duplex;
c9df406f 2826 }
ed94493f 2827 phy_start_aneg(phy);
c28a4f89
JC		 2828}
2829
81600eea
LB		 2830static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2831{
2832 u32 pscr;
2833
37a6084f 2834 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2835 if (pscr & SERIAL_PORT_ENABLE) {
2836 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2837 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2838 }
2839
2840 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2841 if (mp->phy == NULL) {
81600eea
LB		 2842 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2843 if (speed == SPEED_1000)
2844 pscr |= SET_GMII_SPEED_TO_1000;
2845 else if (speed == SPEED_100)
2846 pscr |= SET_MII_SPEED_TO_100;
2847
2848 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2849
2850 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2851 if (duplex == DUPLEX_FULL)
2852 pscr |= SET_FULL_DUPLEX_MODE;
2853 }
2854
37a6084f 2855 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2856}
2857
ea8a8642
LB		 2858static const struct net_device_ops mv643xx_eth_netdev_ops = {
2859 .ndo_open = mv643xx_eth_open,
2860 .ndo_stop = mv643xx_eth_stop,
2861 .ndo_start_xmit = mv643xx_eth_xmit,
2862 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2863 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2864 .ndo_do_ioctl = mv643xx_eth_ioctl,
2865 .ndo_change_mtu = mv643xx_eth_change_mtu,
2866 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2867 .ndo_get_stats = mv643xx_eth_get_stats,
2868#ifdef CONFIG_NET_POLL_CONTROLLER
2869 .ndo_poll_controller = mv643xx_eth_netpoll,
2870#endif
2871};
2872
c9df406f 2873static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2874{
c9df406f 2875 struct mv643xx_eth_platform_data *pd;
e5371493 2876 struct mv643xx_eth_private *mp;
c9df406f 2877 struct net_device *dev;
c9df406f 2878 struct resource *res;
fc32b0e2 2879 int err;
1da177e4 2880
c9df406f
LB		 2881 pd = pdev->dev.platform_data;
2882 if (pd == NULL) {
fc32b0e2
LB		 2883 dev_printk(KERN_ERR, &pdev->dev,
2884 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2885 return -ENODEV;
2886 }
1da177e4 2887
c9df406f 2888 if (pd->shared == NULL) {
fc32b0e2
LB		 2889 dev_printk(KERN_ERR, &pdev->dev,
2890 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2891 return -ENODEV;
2892 }
8f518703 2893
e5ef1de1 2894 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2895 if (!dev)
2896 return -ENOMEM;
1da177e4 2897
c9df406f 2898 mp = netdev_priv(dev);
fc32b0e2
LB		 2899 platform_set_drvdata(pdev, mp);
2900
2901 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2902 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2903 mp->port_num = pd->port_number;
2904
c9df406f 2905 mp->dev = dev;
78fff83b 2906
fc32b0e2 2907 set_params(mp, pd);
e5ef1de1 2908 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2909
ed94493f
LB		 2910 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2911 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2912
6bdf576e 2913 if (mp->phy != NULL)
ed94493f 2914 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2915
2916 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2917
81600eea 2918 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2919
4ff3495a
LB		 2920
2921 mib_counters_clear(mp);
2922
2923 init_timer(&mp->mib_counters_timer);
2924 mp->mib_counters_timer.data = (unsigned long)mp;
2925 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2926 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2927 add_timer(&mp->mib_counters_timer);
2928
2929 spin_lock_init(&mp->mib_counters_lock);
2930
2931 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2932
2257e05c
LB		 2933 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2934
2935 init_timer(&mp->rx_oom);
2936 mp->rx_oom.data = (unsigned long)mp;
2937 mp->rx_oom.function = oom_timer_wrapper;
2938
fc32b0e2 2939
c9df406f
LB		 2940 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2941 BUG_ON(!res);
2942 dev->irq = res->start;
1da177e4 2943
ea8a8642
LB		 2944 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2945
c9df406f
LB		 2946 dev->watchdog_timeo = 2 * HZ;
2947 dev->base_addr = 0;
1da177e4 2948
c9df406f 2949 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2950 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2951
fc32b0e2 2952 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2953
c9df406f 2954 if (mp->shared->win_protect)
fc32b0e2 2955 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2956
a5fe3616
LB		 2957 netif_carrier_off(dev);
2958
b5e86db4
LB		 2959 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2960
4fb0a54a 2961 set_rx_coal(mp, 250);
a5fe3616
LB		 2962 set_tx_coal(mp, 0);
2963
c9df406f
LB		 2964 err = register_netdev(dev);
2965 if (err)
2966 goto out;
1da177e4 2967
e174961c
JB		 2968 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2969 mp->port_num, dev->dev_addr);
1da177e4 2970
13d64285 2971 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2972 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2973
c9df406f 2974 return 0;
1da177e4 2975
c9df406f
LB		 2976out:
2977 free_netdev(dev);
1da177e4 2978
c9df406f 2979 return err;
1da177e4
LT		 2980}
2981
c9df406f 2982static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2983{
fc32b0e2 2984 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2985
fc32b0e2 2986 unregister_netdev(mp->dev);
ed94493f
LB		 2987 if (mp->phy != NULL)
2988 phy_detach(mp->phy);
c9df406f 2989 flush_scheduled_work();
fc32b0e2 2990 free_netdev(mp->dev);
c9df406f 2991
c9df406f 2992 platform_set_drvdata(pdev, NULL);
fc32b0e2 2993
c9df406f 2994 return 0;
1da177e4
LT		 2995}
2996
c9df406f 2997static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2998{
fc32b0e2 2999 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3000
c9df406f 3001 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3002 wrlp(mp, INT_MASK, 0);
3003 rdlp(mp, INT_MASK);
c9df406f 3004
fc32b0e2
LB		 3005 if (netif_running(mp->dev))
3006 port_reset(mp);
d0412d96
JC		 3007}
3008
c9df406f 3009static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3010 .probe = mv643xx_eth_probe,
3011 .remove = mv643xx_eth_remove,
3012 .shutdown = mv643xx_eth_shutdown,
c9df406f 3013 .driver = {
fc32b0e2 3014 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3015 .owner = THIS_MODULE,
3016 },
3017};
3018
e5371493 3019static int __init mv643xx_eth_init_module(void)
d0412d96 3020{
c9df406f 3021 int rc;
d0412d96 3022
c9df406f
LB		 3023 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3024 if (!rc) {
3025 rc = platform_driver_register(&mv643xx_eth_driver);
3026 if (rc)
3027 platform_driver_unregister(&mv643xx_eth_shared_driver);
3028 }
fc32b0e2 3029
c9df406f 3030 return rc;
d0412d96 3031}
fc32b0e2 3032module_init(mv643xx_eth_init_module);
d0412d96 3033
e5371493 3034static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3035{
c9df406f
LB		 3036 platform_driver_unregister(&mv643xx_eth_driver);
3037 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3038}
e5371493 3039module_exit(mv643xx_eth_cleanup_module);
1da177e4 3040
45675bc6
LB		 3041MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3042 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3043MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3044MODULE_LICENSE("GPL");
c9df406f 3045MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3046MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Clone of davem's net-next-2.6 tree