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[net-next-2.6.git] / drivers / net / mace.c
CommitLineData
1da177e4
LT		 1/*
2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
1da177e4
LT		 8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/netdevice.h>
11#include <linux/etherdevice.h>
12#include <linux/delay.h>
13#include <linux/string.h>
14#include <linux/timer.h>
15#include <linux/init.h>
16#include <linux/crc32.h>
17#include <linux/spinlock.h>
bc63eb9c 18#include <linux/bitrev.h>
1da177e4
LT		 19#include <asm/prom.h>
20#include <asm/dbdma.h>
21#include <asm/io.h>
22#include <asm/pgtable.h>
23#include <asm/macio.h>
24
25#include "mace.h"
26
27static int port_aaui = -1;
28
29#define N_RX_RING 8
30#define N_TX_RING 6
31#define MAX_TX_ACTIVE 1
32#define NCMDS_TX 1 /* dma commands per element in tx ring */
33#define RX_BUFLEN (ETH_FRAME_LEN + 8)
34#define TX_TIMEOUT HZ /* 1 second */
35
36/* Chip rev needs workaround on HW & multicast addr change */
37#define BROKEN_ADDRCHG_REV 0x0941
38
39/* Bits in transmit DMA status */
40#define TX_DMA_ERR 0x80
41
42struct mace_data {
43 volatile struct mace __iomem *mace;
44 volatile struct dbdma_regs __iomem *tx_dma;
45 int tx_dma_intr;
46 volatile struct dbdma_regs __iomem *rx_dma;
47 int rx_dma_intr;
48 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
49 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
50 struct sk_buff *rx_bufs[N_RX_RING];
51 int rx_fill;
52 int rx_empty;
53 struct sk_buff *tx_bufs[N_TX_RING];
54 int tx_fill;
55 int tx_empty;
56 unsigned char maccc;
57 unsigned char tx_fullup;
58 unsigned char tx_active;
59 unsigned char tx_bad_runt;
1da177e4
LT		 60 struct timer_list tx_timeout;
61 int timeout_active;
62 int port_aaui;
63 int chipid;
64 struct macio_dev *mdev;
65 spinlock_t lock;
66};
67
68/*
69 * Number of bytes of private data per MACE: allow enough for
70 * the rx and tx dma commands plus a branch dma command each,
71 * and another 16 bytes to allow us to align the dma command
72 * buffers on a 16 byte boundary.
73 */
74#define PRIV_BYTES (sizeof(struct mace_data) \
75 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
76
1da177e4
LT		 77static int mace_open(struct net_device *dev);
78static int mace_close(struct net_device *dev);
79static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
1da177e4
LT		 80static void mace_set_multicast(struct net_device *dev);
81static void mace_reset(struct net_device *dev);
82static int mace_set_address(struct net_device *dev, void *addr);
7d12e780
DH		 83static irqreturn_t mace_interrupt(int irq, void *dev_id);
84static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
85static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
1da177e4
LT		 86static void mace_set_timeout(struct net_device *dev);
87static void mace_tx_timeout(unsigned long data);
88static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
89static inline void mace_clean_rings(struct mace_data *mp);
90static void __mace_set_address(struct net_device *dev, void *addr);
91
92/*
93 * If we can't get a skbuff when we need it, we use this area for DMA.
94 */
95static unsigned char *dummy_buf;
96
488b4abc
AB		 97static const struct net_device_ops mace_netdev_ops = {
98 .ndo_open = mace_open,
99 .ndo_stop = mace_close,
100 .ndo_start_xmit = mace_xmit_start,
101 .ndo_set_multicast_list = mace_set_multicast,
102 .ndo_set_mac_address = mace_set_address,
103 .ndo_change_mtu = eth_change_mtu,
104 .ndo_validate_addr = eth_validate_addr,
105};
106
5e655772 107static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
1da177e4
LT		 108{
109 struct device_node *mace = macio_get_of_node(mdev);
110 struct net_device *dev;
111 struct mace_data *mp;
1a2509c9 112 const unsigned char *addr;
1da177e4
LT		 113 int j, rev, rc = -EBUSY;
114
115 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
116 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
117 mace->full_name);
118 return -ENODEV;
119 }
120
40cd3a45 121 addr = of_get_property(mace, "mac-address", NULL);
1da177e4 122 if (addr == NULL) {
40cd3a45 123 addr = of_get_property(mace, "local-mac-address", NULL);
1da177e4
LT		 124 if (addr == NULL) {
125 printk(KERN_ERR "Can't get mac-address for MACE %s\n",
126 mace->full_name);
127 return -ENODEV;
128 }
129 }
130
131 /*
132 * lazy allocate the driver-wide dummy buffer. (Note that we
133 * never have more than one MACE in the system anyway)
134 */
135 if (dummy_buf == NULL) {
136 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
137 if (dummy_buf == NULL) {
138 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
139 return -ENOMEM;
140 }
141 }
142
143 if (macio_request_resources(mdev, "mace")) {
144 printk(KERN_ERR "MACE: can't request IO resources !\n");
145 return -EBUSY;
146 }
147
148 dev = alloc_etherdev(PRIV_BYTES);
149 if (!dev) {
150 printk(KERN_ERR "MACE: can't allocate ethernet device !\n");
151 rc = -ENOMEM;
152 goto err_release;
153 }
1da177e4
LT		 154 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
155
454d7c9b 156 mp = netdev_priv(dev);
1da177e4
LT		 157 mp->mdev = mdev;
158 macio_set_drvdata(mdev, dev);
159
160 dev->base_addr = macio_resource_start(mdev, 0);
161 mp->mace = ioremap(dev->base_addr, 0x1000);
162 if (mp->mace == NULL) {
163 printk(KERN_ERR "MACE: can't map IO resources !\n");
164 rc = -ENOMEM;
165 goto err_free;
166 }
167 dev->irq = macio_irq(mdev, 0);
168
169 rev = addr[0] == 0 && addr[1] == 0xA0;
170 for (j = 0; j < 6; ++j) {
bc63eb9c 171 dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
1da177e4
LT		 172 }
173 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
174 in_8(&mp->mace->chipid_lo);
6aa20a22 175
1da177e4 176
454d7c9b 177 mp = netdev_priv(dev);
1da177e4
LT		 178 mp->maccc = ENXMT | ENRCV;
179
180 mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
181 if (mp->tx_dma == NULL) {
182 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
183 rc = -ENOMEM;
184 goto err_unmap_io;
185 }
186 mp->tx_dma_intr = macio_irq(mdev, 1);
187
188 mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
189 if (mp->rx_dma == NULL) {
190 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
191 rc = -ENOMEM;
192 goto err_unmap_tx_dma;
193 }
194 mp->rx_dma_intr = macio_irq(mdev, 2);
195
196 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
197 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
198
1da177e4
LT		 199 memset((char *) mp->tx_cmds, 0,
200 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
201 init_timer(&mp->tx_timeout);
202 spin_lock_init(&mp->lock);
203 mp->timeout_active = 0;
204
205 if (port_aaui >= 0)
206 mp->port_aaui = port_aaui;
207 else {
208 /* Apple Network Server uses the AAUI port */
71a157e8 209 if (of_machine_is_compatible("AAPL,ShinerESB"))
1da177e4
LT		 210 mp->port_aaui = 1;
211 else {
212#ifdef CONFIG_MACE_AAUI_PORT
213 mp->port_aaui = 1;
214#else
215 mp->port_aaui = 0;
6aa20a22 216#endif
1da177e4
LT		 217 }
218 }
219
488b4abc 220 dev->netdev_ops = &mace_netdev_ops;
1da177e4
LT		 221
222 /*
223 * Most of what is below could be moved to mace_open()
224 */
225 mace_reset(dev);
226
227 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
228 if (rc) {
229 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
230 goto err_unmap_rx_dma;
231 }
232 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
233 if (rc) {
0ebfff14 234 printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
1da177e4
LT		 235 goto err_free_irq;
236 }
237 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
238 if (rc) {
0ebfff14 239 printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
1da177e4
LT		 240 goto err_free_tx_irq;
241 }
242
243 rc = register_netdev(dev);
244 if (rc) {
245 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
246 goto err_free_rx_irq;
247 }
248
e174961c
JB		 249 printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n",
250 dev->name, dev->dev_addr,
0795af57 251 mp->chipid >> 8, mp->chipid & 0xff);
1da177e4
LT		 252
253 return 0;
6aa20a22 254
1da177e4
LT		 255 err_free_rx_irq:
256 free_irq(macio_irq(mdev, 2), dev);
257 err_free_tx_irq:
258 free_irq(macio_irq(mdev, 1), dev);
259 err_free_irq:
260 free_irq(macio_irq(mdev, 0), dev);
261 err_unmap_rx_dma:
262 iounmap(mp->rx_dma);
263 err_unmap_tx_dma:
264 iounmap(mp->tx_dma);
265 err_unmap_io:
266 iounmap(mp->mace);
267 err_free:
268 free_netdev(dev);
269 err_release:
270 macio_release_resources(mdev);
271
272 return rc;
273}
274
275static int __devexit mace_remove(struct macio_dev *mdev)
276{
277 struct net_device *dev = macio_get_drvdata(mdev);
278 struct mace_data *mp;
279
280 BUG_ON(dev == NULL);
281
282 macio_set_drvdata(mdev, NULL);
283
454d7c9b 284 mp = netdev_priv(dev);
1da177e4
LT		 285
286 unregister_netdev(dev);
287
288 free_irq(dev->irq, dev);
289 free_irq(mp->tx_dma_intr, dev);
290 free_irq(mp->rx_dma_intr, dev);
291
292 iounmap(mp->rx_dma);
293 iounmap(mp->tx_dma);
294 iounmap(mp->mace);
295
296 free_netdev(dev);
297
298 macio_release_resources(mdev);
299
300 return 0;
301}
302
303static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
304{
305 int i;
306
307 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
308
309 /*
310 * Yes this looks peculiar, but apparently it needs to be this
311 * way on some machines.
312 */
313 for (i = 200; i > 0; --i)
314 if (ld_le32(&dma->control) & RUN)
315 udelay(1);
316}
317
318static void mace_reset(struct net_device *dev)
319{
454d7c9b 320 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 321 volatile struct mace __iomem *mb = mp->mace;
322 int i;
323
324 /* soft-reset the chip */
325 i = 200;
326 while (--i) {
327 out_8(&mb->biucc, SWRST);
328 if (in_8(&mb->biucc) & SWRST) {
329 udelay(10);
330 continue;
331 }
332 break;
333 }
334 if (!i) {
335 printk(KERN_ERR "mace: cannot reset chip!\n");
336 return;
337 }
338
339 out_8(&mb->imr, 0xff); /* disable all intrs for now */
340 i = in_8(&mb->ir);
341 out_8(&mb->maccc, 0); /* turn off tx, rx */
342
343 out_8(&mb->biucc, XMTSP_64);
344 out_8(&mb->utr, RTRD);
345 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
346 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
347 out_8(&mb->rcvfc, 0);
348
349 /* load up the hardware address */
350 __mace_set_address(dev, dev->dev_addr);
351
352 /* clear the multicast filter */
353 if (mp->chipid == BROKEN_ADDRCHG_REV)
354 out_8(&mb->iac, LOGADDR);
355 else {
356 out_8(&mb->iac, ADDRCHG | LOGADDR);
357 while ((in_8(&mb->iac) & ADDRCHG) != 0)
358 ;
359 }
360 for (i = 0; i < 8; ++i)
361 out_8(&mb->ladrf, 0);
362
363 /* done changing address */
364 if (mp->chipid != BROKEN_ADDRCHG_REV)
365 out_8(&mb->iac, 0);
366
367 if (mp->port_aaui)
368 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
369 else
370 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
371}
372
373static void __mace_set_address(struct net_device *dev, void *addr)
374{
454d7c9b 375 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 376 volatile struct mace __iomem *mb = mp->mace;
377 unsigned char *p = addr;
378 int i;
379
380 /* load up the hardware address */
381 if (mp->chipid == BROKEN_ADDRCHG_REV)
382 out_8(&mb->iac, PHYADDR);
383 else {
384 out_8(&mb->iac, ADDRCHG | PHYADDR);
385 while ((in_8(&mb->iac) & ADDRCHG) != 0)
386 ;
387 }
388 for (i = 0; i < 6; ++i)
389 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
390 if (mp->chipid != BROKEN_ADDRCHG_REV)
391 out_8(&mb->iac, 0);
392}
393
394static int mace_set_address(struct net_device *dev, void *addr)
395{
454d7c9b 396 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 397 volatile struct mace __iomem *mb = mp->mace;
398 unsigned long flags;
399
400 spin_lock_irqsave(&mp->lock, flags);
401
402 __mace_set_address(dev, addr);
403
404 /* note: setting ADDRCHG clears ENRCV */
405 out_8(&mb->maccc, mp->maccc);
406
407 spin_unlock_irqrestore(&mp->lock, flags);
408 return 0;
409}
410
411static inline void mace_clean_rings(struct mace_data *mp)
412{
413 int i;
414
415 /* free some skb's */
416 for (i = 0; i < N_RX_RING; ++i) {
79ea13ce 417 if (mp->rx_bufs[i] != NULL) {
1da177e4
LT		 418 dev_kfree_skb(mp->rx_bufs[i]);
419 mp->rx_bufs[i] = NULL;
420 }
421 }
422 for (i = mp->tx_empty; i != mp->tx_fill; ) {
423 dev_kfree_skb(mp->tx_bufs[i]);
424 if (++i >= N_TX_RING)
425 i = 0;
426 }
427}
428
429static int mace_open(struct net_device *dev)
430{
454d7c9b 431 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 432 volatile struct mace __iomem *mb = mp->mace;
433 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
434 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
435 volatile struct dbdma_cmd *cp;
436 int i;
437 struct sk_buff *skb;
438 unsigned char *data;
439
440 /* reset the chip */
441 mace_reset(dev);
442
443 /* initialize list of sk_buffs for receiving and set up recv dma */
444 mace_clean_rings(mp);
445 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
446 cp = mp->rx_cmds;
447 for (i = 0; i < N_RX_RING - 1; ++i) {
448 skb = dev_alloc_skb(RX_BUFLEN + 2);
79ea13ce 449 if (!skb) {
1da177e4
LT		 450 data = dummy_buf;
451 } else {
452 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
453 data = skb->data;
454 }
455 mp->rx_bufs[i] = skb;
456 st_le16(&cp->req_count, RX_BUFLEN);
457 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
458 st_le32(&cp->phy_addr, virt_to_bus(data));
459 cp->xfer_status = 0;
460 ++cp;
461 }
462 mp->rx_bufs[i] = NULL;
463 st_le16(&cp->command, DBDMA_STOP);
464 mp->rx_fill = i;
465 mp->rx_empty = 0;
466
467 /* Put a branch back to the beginning of the receive command list */
468 ++cp;
469 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
470 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
471
472 /* start rx dma */
473 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
474 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
475 out_le32(&rd->control, (RUN << 16) | RUN);
476
477 /* put a branch at the end of the tx command list */
478 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
479 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
480 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
481
482 /* reset tx dma */
483 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
484 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
485 mp->tx_fill = 0;
486 mp->tx_empty = 0;
487 mp->tx_fullup = 0;
488 mp->tx_active = 0;
489 mp->tx_bad_runt = 0;
490
491 /* turn it on! */
492 out_8(&mb->maccc, mp->maccc);
493 /* enable all interrupts except receive interrupts */
494 out_8(&mb->imr, RCVINT);
495
496 return 0;
497}
498
499static int mace_close(struct net_device *dev)
500{
454d7c9b 501 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 502 volatile struct mace __iomem *mb = mp->mace;
503 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
504 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
505
506 /* disable rx and tx */
507 out_8(&mb->maccc, 0);
508 out_8(&mb->imr, 0xff); /* disable all intrs */
509
510 /* disable rx and tx dma */
511 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
512 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
513
514 mace_clean_rings(mp);
515
516 return 0;
517}
518
519static inline void mace_set_timeout(struct net_device *dev)
520{
454d7c9b 521 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 522
523 if (mp->timeout_active)
524 del_timer(&mp->tx_timeout);
525 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
526 mp->tx_timeout.function = mace_tx_timeout;
527 mp->tx_timeout.data = (unsigned long) dev;
528 add_timer(&mp->tx_timeout);
529 mp->timeout_active = 1;
530}
531
532static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
533{
454d7c9b 534 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 535 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
536 volatile struct dbdma_cmd *cp, *np;
537 unsigned long flags;
538 int fill, next, len;
539
540 /* see if there's a free slot in the tx ring */
541 spin_lock_irqsave(&mp->lock, flags);
542 fill = mp->tx_fill;
543 next = fill + 1;
544 if (next >= N_TX_RING)
545 next = 0;
546 if (next == mp->tx_empty) {
547 netif_stop_queue(dev);
548 mp->tx_fullup = 1;
549 spin_unlock_irqrestore(&mp->lock, flags);
5b548140 550 return NETDEV_TX_BUSY; /* can't take it at the moment */
1da177e4
LT		 551 }
552 spin_unlock_irqrestore(&mp->lock, flags);
553
554 /* partially fill in the dma command block */
555 len = skb->len;
556 if (len > ETH_FRAME_LEN) {
557 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
558 len = ETH_FRAME_LEN;
559 }
560 mp->tx_bufs[fill] = skb;
561 cp = mp->tx_cmds + NCMDS_TX * fill;
562 st_le16(&cp->req_count, len);
563 st_le32(&cp->phy_addr, virt_to_bus(skb->data));
564
565 np = mp->tx_cmds + NCMDS_TX * next;
566 out_le16(&np->command, DBDMA_STOP);
567
568 /* poke the tx dma channel */
569 spin_lock_irqsave(&mp->lock, flags);
570 mp->tx_fill = next;
571 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
572 out_le16(&cp->xfer_status, 0);
573 out_le16(&cp->command, OUTPUT_LAST);
574 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
575 ++mp->tx_active;
576 mace_set_timeout(dev);
577 }
578 if (++next >= N_TX_RING)
579 next = 0;
580 if (next == mp->tx_empty)
581 netif_stop_queue(dev);
582 spin_unlock_irqrestore(&mp->lock, flags);
583
6ed10654 584 return NETDEV_TX_OK;
1da177e4
LT		 585}
586
1da177e4
LT		 587static void mace_set_multicast(struct net_device *dev)
588{
454d7c9b 589 struct mace_data *mp = netdev_priv(dev);
1da177e4 590 volatile struct mace __iomem *mb = mp->mace;
f9dcbcc9 591 int i;
1da177e4
LT		 592 u32 crc;
593 unsigned long flags;
594
595 spin_lock_irqsave(&mp->lock, flags);
596 mp->maccc &= ~PROM;
597 if (dev->flags & IFF_PROMISC) {
598 mp->maccc |= PROM;
599 } else {
600 unsigned char multicast_filter[8];
22bedad3 601 struct netdev_hw_addr *ha;
1da177e4
LT		 602
603 if (dev->flags & IFF_ALLMULTI) {
604 for (i = 0; i < 8; i++)
605 multicast_filter[i] = 0xff;
606 } else {
607 for (i = 0; i < 8; i++)
608 multicast_filter[i] = 0;
22bedad3
JP		 609 netdev_for_each_mc_addr(ha, dev) {
610 crc = ether_crc_le(6, ha->addr);
f9dcbcc9
JP		 611 i = crc >> 26; /* bit number in multicast_filter */
612 multicast_filter[i >> 3] |= 1 << (i & 7);
1da177e4
LT		 613 }
614 }
615#if 0
616 printk("Multicast filter :");
617 for (i = 0; i < 8; i++)
618 printk("%02x ", multicast_filter[i]);
619 printk("\n");
620#endif
621
622 if (mp->chipid == BROKEN_ADDRCHG_REV)
623 out_8(&mb->iac, LOGADDR);
624 else {
625 out_8(&mb->iac, ADDRCHG | LOGADDR);
626 while ((in_8(&mb->iac) & ADDRCHG) != 0)
627 ;
628 }
629 for (i = 0; i < 8; ++i)
630 out_8(&mb->ladrf, multicast_filter[i]);
631 if (mp->chipid != BROKEN_ADDRCHG_REV)
632 out_8(&mb->iac, 0);
633 }
634 /* reset maccc */
635 out_8(&mb->maccc, mp->maccc);
636 spin_unlock_irqrestore(&mp->lock, flags);
637}
638
09f75cd7 639static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev)
1da177e4
LT		 640{
641 volatile struct mace __iomem *mb = mp->mace;
642 static int mace_babbles, mace_jabbers;
643
644 if (intr & MPCO)
09f75cd7
JG		 645 dev->stats.rx_missed_errors += 256;
646 dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
1da177e4 647 if (intr & RNTPCO)
09f75cd7
JG		 648 dev->stats.rx_length_errors += 256;
649 dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
1da177e4 650 if (intr & CERR)
09f75cd7 651 ++dev->stats.tx_heartbeat_errors;
1da177e4
LT		 652 if (intr & BABBLE)
653 if (mace_babbles++ < 4)
654 printk(KERN_DEBUG "mace: babbling transmitter\n");
655 if (intr & JABBER)
656 if (mace_jabbers++ < 4)
657 printk(KERN_DEBUG "mace: jabbering transceiver\n");
658}
659
7d12e780 660static irqreturn_t mace_interrupt(int irq, void *dev_id)
1da177e4
LT		 661{
662 struct net_device *dev = (struct net_device *) dev_id;
454d7c9b 663 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 664 volatile struct mace __iomem *mb = mp->mace;
665 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
666 volatile struct dbdma_cmd *cp;
667 int intr, fs, i, stat, x;
668 int xcount, dstat;
669 unsigned long flags;
670 /* static int mace_last_fs, mace_last_xcount; */
671
672 spin_lock_irqsave(&mp->lock, flags);
673 intr = in_8(&mb->ir); /* read interrupt register */
674 in_8(&mb->xmtrc); /* get retries */
09f75cd7 675 mace_handle_misc_intrs(mp, intr, dev);
1da177e4
LT		 676
677 i = mp->tx_empty;
678 while (in_8(&mb->pr) & XMTSV) {
679 del_timer(&mp->tx_timeout);
680 mp->timeout_active = 0;
681 /*
682 * Clear any interrupt indication associated with this status
683 * word. This appears to unlatch any error indication from
684 * the DMA controller.
685 */
686 intr = in_8(&mb->ir);
687 if (intr != 0)
09f75cd7 688 mace_handle_misc_intrs(mp, intr, dev);
1da177e4
LT		 689 if (mp->tx_bad_runt) {
690 fs = in_8(&mb->xmtfs);
691 mp->tx_bad_runt = 0;
692 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
693 continue;
694 }
695 dstat = ld_le32(&td->status);
696 /* stop DMA controller */
697 out_le32(&td->control, RUN << 16);
698 /*
699 * xcount is the number of complete frames which have been
700 * written to the fifo but for which status has not been read.
701 */
702 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
703 if (xcount == 0 || (dstat & DEAD)) {
704 /*
705 * If a packet was aborted before the DMA controller has
706 * finished transferring it, it seems that there are 2 bytes
707 * which are stuck in some buffer somewhere. These will get
708 * transmitted as soon as we read the frame status (which
709 * reenables the transmit data transfer request). Turning
710 * off the DMA controller and/or resetting the MACE doesn't
711 * help. So we disable auto-padding and FCS transmission
712 * so the two bytes will only be a runt packet which should
713 * be ignored by other stations.
714 */
715 out_8(&mb->xmtfc, DXMTFCS);
716 }
717 fs = in_8(&mb->xmtfs);
718 if ((fs & XMTSV) == 0) {
719 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
720 fs, xcount, dstat);
721 mace_reset(dev);
722 /*
723 * XXX mace likes to hang the machine after a xmtfs error.
724 * This is hard to reproduce, reseting *may* help
725 */
726 }
727 cp = mp->tx_cmds + NCMDS_TX * i;
728 stat = ld_le16(&cp->xfer_status);
729 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
730 /*
731 * Check whether there were in fact 2 bytes written to
732 * the transmit FIFO.
733 */
734 udelay(1);
735 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
736 if (x != 0) {
737 /* there were two bytes with an end-of-packet indication */
738 mp->tx_bad_runt = 1;
739 mace_set_timeout(dev);
740 } else {
741 /*
742 * Either there weren't the two bytes buffered up, or they
743 * didn't have an end-of-packet indication.
744 * We flush the transmit FIFO just in case (by setting the
745 * XMTFWU bit with the transmitter disabled).
746 */
747 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
748 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
749 udelay(1);
750 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
751 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
752 }
753 }
754 /* dma should have finished */
755 if (i == mp->tx_fill) {
756 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
757 fs, xcount, dstat);
758 continue;
759 }
760 /* Update stats */
761 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
09f75cd7 762 ++dev->stats.tx_errors;
1da177e4 763 if (fs & LCAR)
09f75cd7 764 ++dev->stats.tx_carrier_errors;
1da177e4 765 if (fs & (UFLO|LCOL|RTRY))
09f75cd7 766 ++dev->stats.tx_aborted_errors;
1da177e4 767 } else {
09f75cd7
JG		 768 dev->stats.tx_bytes += mp->tx_bufs[i]->len;
769 ++dev->stats.tx_packets;
1da177e4
LT		 770 }
771 dev_kfree_skb_irq(mp->tx_bufs[i]);
772 --mp->tx_active;
773 if (++i >= N_TX_RING)
774 i = 0;
775#if 0
776 mace_last_fs = fs;
777 mace_last_xcount = xcount;
778#endif
779 }
780
781 if (i != mp->tx_empty) {
782 mp->tx_fullup = 0;
783 netif_wake_queue(dev);
784 }
785 mp->tx_empty = i;
786 i += mp->tx_active;
787 if (i >= N_TX_RING)
788 i -= N_TX_RING;
789 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
790 do {
791 /* set up the next one */
792 cp = mp->tx_cmds + NCMDS_TX * i;
793 out_le16(&cp->xfer_status, 0);
794 out_le16(&cp->command, OUTPUT_LAST);
795 ++mp->tx_active;
796 if (++i >= N_TX_RING)
797 i = 0;
798 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
799 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
800 mace_set_timeout(dev);
801 }
802 spin_unlock_irqrestore(&mp->lock, flags);
803 return IRQ_HANDLED;
804}
805
806static void mace_tx_timeout(unsigned long data)
807{
808 struct net_device *dev = (struct net_device *) data;
454d7c9b 809 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 810 volatile struct mace __iomem *mb = mp->mace;
811 volatile struct dbdma_regs __iomem *td = mp->tx_dma;
812 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
813 volatile struct dbdma_cmd *cp;
814 unsigned long flags;
815 int i;
816
817 spin_lock_irqsave(&mp->lock, flags);
818 mp->timeout_active = 0;
819 if (mp->tx_active == 0 && !mp->tx_bad_runt)
820 goto out;
821
822 /* update various counters */
09f75cd7 823 mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);
1da177e4
LT		 824
825 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
826
827 /* turn off both tx and rx and reset the chip */
828 out_8(&mb->maccc, 0);
829 printk(KERN_ERR "mace: transmit timeout - resetting\n");
830 dbdma_reset(td);
831 mace_reset(dev);
832
833 /* restart rx dma */
834 cp = bus_to_virt(ld_le32(&rd->cmdptr));
835 dbdma_reset(rd);
836 out_le16(&cp->xfer_status, 0);
837 out_le32(&rd->cmdptr, virt_to_bus(cp));
838 out_le32(&rd->control, (RUN << 16) | RUN);
839
840 /* fix up the transmit side */
841 i = mp->tx_empty;
842 mp->tx_active = 0;
09f75cd7 843 ++dev->stats.tx_errors;
1da177e4
LT		 844 if (mp->tx_bad_runt) {
845 mp->tx_bad_runt = 0;
846 } else if (i != mp->tx_fill) {
847 dev_kfree_skb(mp->tx_bufs[i]);
848 if (++i >= N_TX_RING)
849 i = 0;
850 mp->tx_empty = i;
851 }
852 mp->tx_fullup = 0;
853 netif_wake_queue(dev);
854 if (i != mp->tx_fill) {
855 cp = mp->tx_cmds + NCMDS_TX * i;
856 out_le16(&cp->xfer_status, 0);
857 out_le16(&cp->command, OUTPUT_LAST);
858 out_le32(&td->cmdptr, virt_to_bus(cp));
859 out_le32(&td->control, (RUN << 16) | RUN);
860 ++mp->tx_active;
861 mace_set_timeout(dev);
862 }
863
864 /* turn it back on */
865 out_8(&mb->imr, RCVINT);
866 out_8(&mb->maccc, mp->maccc);
867
868out:
869 spin_unlock_irqrestore(&mp->lock, flags);
870}
871
7d12e780 872static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
1da177e4
LT		 873{
874 return IRQ_HANDLED;
875}
876
7d12e780 877static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
1da177e4
LT		 878{
879 struct net_device *dev = (struct net_device *) dev_id;
454d7c9b 880 struct mace_data *mp = netdev_priv(dev);
1da177e4
LT		 881 volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
882 volatile struct dbdma_cmd *cp, *np;
883 int i, nb, stat, next;
884 struct sk_buff *skb;
885 unsigned frame_status;
886 static int mace_lost_status;
887 unsigned char *data;
888 unsigned long flags;
889
890 spin_lock_irqsave(&mp->lock, flags);
891 for (i = mp->rx_empty; i != mp->rx_fill; ) {
892 cp = mp->rx_cmds + i;
893 stat = ld_le16(&cp->xfer_status);
894 if ((stat & ACTIVE) == 0) {
895 next = i + 1;
896 if (next >= N_RX_RING)
897 next = 0;
898 np = mp->rx_cmds + next;
8e95a202
JP		 899 if (next != mp->rx_fill &&
900 (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
1da177e4
LT		 901 printk(KERN_DEBUG "mace: lost a status word\n");
902 ++mace_lost_status;
903 } else
904 break;
905 }
906 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
907 out_le16(&cp->command, DBDMA_STOP);
908 /* got a packet, have a look at it */
909 skb = mp->rx_bufs[i];
79ea13ce 910 if (!skb) {
09f75cd7 911 ++dev->stats.rx_dropped;
1da177e4
LT		 912 } else if (nb > 8) {
913 data = skb->data;
914 frame_status = (data[nb-3] << 8) + data[nb-4];
915 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
09f75cd7 916 ++dev->stats.rx_errors;
1da177e4 917 if (frame_status & RS_OFLO)
09f75cd7 918 ++dev->stats.rx_over_errors;
1da177e4 919 if (frame_status & RS_FRAMERR)
09f75cd7 920 ++dev->stats.rx_frame_errors;
1da177e4 921 if (frame_status & RS_FCSERR)
09f75cd7 922 ++dev->stats.rx_crc_errors;
1da177e4
LT		 923 } else {
924 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
925 * FCS on frames with 802.3 headers. This means that Ethernet
926 * frames have 8 extra octets at the end, while 802.3 frames
927 * have only 4. We need to correctly account for this. */
928 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
929 nb -= 4;
930 else /* Ethernet header; mace includes FCS */
931 nb -= 8;
932 skb_put(skb, nb);
1da177e4 933 skb->protocol = eth_type_trans(skb, dev);
09f75cd7 934 dev->stats.rx_bytes += skb->len;
1da177e4 935 netif_rx(skb);
1da177e4 936 mp->rx_bufs[i] = NULL;
09f75cd7 937 ++dev->stats.rx_packets;
1da177e4
LT		 938 }
939 } else {
09f75cd7
JG		 940 ++dev->stats.rx_errors;
941 ++dev->stats.rx_length_errors;
1da177e4
LT		 942 }
943
944 /* advance to next */
945 if (++i >= N_RX_RING)
946 i = 0;
947 }
948 mp->rx_empty = i;
949
950 i = mp->rx_fill;
951 for (;;) {
952 next = i + 1;
953 if (next >= N_RX_RING)
954 next = 0;
955 if (next == mp->rx_empty)
956 break;
957 cp = mp->rx_cmds + i;
958 skb = mp->rx_bufs[i];
79ea13ce 959 if (!skb) {
1da177e4 960 skb = dev_alloc_skb(RX_BUFLEN + 2);
79ea13ce 961 if (skb) {
1da177e4
LT		 962 skb_reserve(skb, 2);
963 mp->rx_bufs[i] = skb;
964 }
965 }
966 st_le16(&cp->req_count, RX_BUFLEN);
967 data = skb? skb->data: dummy_buf;
968 st_le32(&cp->phy_addr, virt_to_bus(data));
969 out_le16(&cp->xfer_status, 0);
970 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
971#if 0
972 if ((ld_le32(&rd->status) & ACTIVE) != 0) {
973 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
974 while ((in_le32(&rd->status) & ACTIVE) != 0)
975 ;
976 }
977#endif
978 i = next;
979 }
980 if (i != mp->rx_fill) {
981 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
982 mp->rx_fill = i;
983 }
984 spin_unlock_irqrestore(&mp->lock, flags);
985 return IRQ_HANDLED;
986}
987
6aa20a22 988static struct of_device_id mace_match[] =
1da177e4
LT		 989{
990 {
991 .name = "mace",
1da177e4
LT		 992 },
993 {},
994};
8c9795ba 995MODULE_DEVICE_TABLE (of, mace_match);
1da177e4 996
6aa20a22 997static struct macio_driver mace_driver =
1da177e4
LT		 998{
999 .name = "mace",
1000 .match_table = mace_match,
1001 .probe = mace_probe,
1002 .remove = mace_remove,
1003};
1004
1005
1006static int __init mace_init(void)
1007{
1008 return macio_register_driver(&mace_driver);
1009}
1010
1011static void __exit mace_cleanup(void)
1012{
1013 macio_unregister_driver(&mace_driver);
1014
b4558ea9
JJ		 1015 kfree(dummy_buf);
1016 dummy_buf = NULL;
1da177e4
LT		 1017}
1018
1019MODULE_AUTHOR("Paul Mackerras");
1020MODULE_DESCRIPTION("PowerMac MACE driver.");
8d3b33f6 1021module_param(port_aaui, int, 0);
1da177e4
LT		 1022MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1023MODULE_LICENSE("GPL");
1024
1025module_init(mace_init);
1026module_exit(mace_cleanup);
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