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92744989
GL		 1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
92744989
GL		 23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/init.h>
33#include <linux/mii.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/netdevice.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_mdio.h>
40#include <linux/of_platform.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
44#include <linux/udp.h> /* needed for sizeof(udphdr) */
45#include <linux/phy.h>
46#include <linux/in.h>
47#include <linux/io.h>
48#include <linux/ip.h>
5a0e3ad6 49#include <linux/slab.h>
92744989
GL		 50
51#include "ll_temac.h"
52
53#define TX_BD_NUM 64
54#define RX_BD_NUM 128
55
56/* ---------------------------------------------------------------------
57 * Low level register access functions
58 */
59
60u32 temac_ior(struct temac_local *lp, int offset)
61{
62 return in_be32((u32 *)(lp->regs + offset));
63}
64
65void temac_iow(struct temac_local *lp, int offset, u32 value)
66{
67 out_be32((u32 *) (lp->regs + offset), value);
68}
69
70int temac_indirect_busywait(struct temac_local *lp)
71{
72 long end = jiffies + 2;
73
74 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
75 if (end - jiffies <= 0) {
76 WARN_ON(1);
77 return -ETIMEDOUT;
78 }
79 msleep(1);
80 }
81 return 0;
82}
83
84/**
85 * temac_indirect_in32
86 *
87 * lp->indirect_mutex must be held when calling this function
88 */
89u32 temac_indirect_in32(struct temac_local *lp, int reg)
90{
91 u32 val;
92
93 if (temac_indirect_busywait(lp))
94 return -ETIMEDOUT;
95 temac_iow(lp, XTE_CTL0_OFFSET, reg);
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 val = temac_ior(lp, XTE_LSW0_OFFSET);
99
100 return val;
101}
102
103/**
104 * temac_indirect_out32
105 *
106 * lp->indirect_mutex must be held when calling this function
107 */
108void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
109{
110 if (temac_indirect_busywait(lp))
111 return;
112 temac_iow(lp, XTE_LSW0_OFFSET, value);
113 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
114}
115
e44171f1
JL		 116/**
117 * temac_dma_in32 - Memory mapped DMA read, this function expects a
118 * register input that is based on DCR word addresses which
119 * are then converted to memory mapped byte addresses
120 */
92744989 121static u32 temac_dma_in32(struct temac_local *lp, int reg)
45956914 122{
e44171f1 123 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
45956914
JL		 124}
125
e44171f1
JL		 126/**
127 * temac_dma_out32 - Memory mapped DMA read, this function expects a
128 * register input that is based on DCR word addresses which
129 * are then converted to memory mapped byte addresses
130 */
4d8dc679 131static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
e44171f1
JL		 132{
133 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
134}
135
136/* DMA register access functions can be DCR based or memory mapped.
137 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
138 * memory mapped.
139 */
140#ifdef CONFIG_PPC_DCR
141
142/**
143 * temac_dma_dcr_in32 - DCR based DMA read
144 */
145static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
146{
147 return dcr_read(lp->sdma_dcrs, reg);
148}
149
150/**
151 * temac_dma_dcr_out32 - DCR based DMA write
152 */
153static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
92744989
GL		 154{
155 dcr_write(lp->sdma_dcrs, reg, value);
156}
157
e44171f1
JL		 158/**
159 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
160 * I/O functions
161 */
162static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
163 struct device_node *np)
164{
165 unsigned int dcrs;
166
167 /* setup the dcr address mapping if it's in the device tree */
168
169 dcrs = dcr_resource_start(np, 0);
170 if (dcrs != 0) {
171 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
172 lp->dma_in = temac_dma_dcr_in;
173 lp->dma_out = temac_dma_dcr_out;
174 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
175 return 0;
176 }
177 /* no DCR in the device tree, indicate a failure */
178 return -1;
179}
180
181#else
182
183/*
184 * temac_dcr_setup - This is a stub for when DCR is not supported,
185 * such as with MicroBlaze
186 */
187static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
188 struct device_node *np)
189{
190 return -1;
191}
192
193#endif
194
92744989
GL		 195/**
196 * temac_dma_bd_init - Setup buffer descriptor rings
197 */
198static int temac_dma_bd_init(struct net_device *ndev)
199{
200 struct temac_local *lp = netdev_priv(ndev);
201 struct sk_buff *skb;
202 int i;
203
5d66fe92 204 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
92744989
GL		 205 /* allocate the tx and rx ring buffer descriptors. */
206 /* returns a virtual addres and a physical address. */
207 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
208 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
209 &lp->tx_bd_p, GFP_KERNEL);
210 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
211 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
212 &lp->rx_bd_p, GFP_KERNEL);
213
214 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
215 for (i = 0; i < TX_BD_NUM; i++) {
216 lp->tx_bd_v[i].next = lp->tx_bd_p +
217 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
218 }
219
220 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
221 for (i = 0; i < RX_BD_NUM; i++) {
222 lp->rx_bd_v[i].next = lp->rx_bd_p +
223 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
224
e44171f1
JL		 225 skb = netdev_alloc_skb_ip_align(ndev,
226 XTE_MAX_JUMBO_FRAME_SIZE);
227
92744989
GL		 228 if (skb == 0) {
229 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
230 return -1;
231 }
232 lp->rx_skb[i] = skb;
92744989
GL		 233 /* returns physical address of skb->data */
234 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
235 skb->data,
236 XTE_MAX_JUMBO_FRAME_SIZE,
237 DMA_FROM_DEVICE);
238 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
239 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
240 }
241
e44171f1 242 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
92744989
GL		 243 CHNL_CTRL_IRQ_EN |
244 CHNL_CTRL_IRQ_DLY_EN |
245 CHNL_CTRL_IRQ_COAL_EN);
246 /* 0x10220483 */
247 /* 0x00100483 */
e44171f1 248 lp->dma_out(lp, RX_CHNL_CTRL, 0xff010000 |
92744989
GL		 249 CHNL_CTRL_IRQ_EN |
250 CHNL_CTRL_IRQ_DLY_EN |
251 CHNL_CTRL_IRQ_COAL_EN |
252 CHNL_CTRL_IRQ_IOE);
253 /* 0xff010283 */
254
e44171f1
JL		 255 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
256 lp->dma_out(lp, RX_TAILDESC_PTR,
92744989 257 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
e44171f1 258 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
92744989
GL		 259
260 return 0;
261}
262
263/* ---------------------------------------------------------------------
264 * net_device_ops
265 */
266
267static int temac_set_mac_address(struct net_device *ndev, void *address)
268{
269 struct temac_local *lp = netdev_priv(ndev);
270
271 if (address)
272 memcpy(ndev->dev_addr, address, ETH_ALEN);
273
274 if (!is_valid_ether_addr(ndev->dev_addr))
275 random_ether_addr(ndev->dev_addr);
276
277 /* set up unicast MAC address filter set its mac address */
278 mutex_lock(&lp->indirect_mutex);
279 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
280 (ndev->dev_addr[0]) |
281 (ndev->dev_addr[1] << 8) |
282 (ndev->dev_addr[2] << 16) |
283 (ndev->dev_addr[3] << 24));
284 /* There are reserved bits in EUAW1
285 * so don't affect them Set MAC bits [47:32] in EUAW1 */
286 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
287 (ndev->dev_addr[4] & 0x000000ff) |
288 (ndev->dev_addr[5] << 8));
289 mutex_unlock(&lp->indirect_mutex);
290
291 return 0;
292}
293
8ea7a37c
SM		 294static int netdev_set_mac_address(struct net_device *ndev, void *p)
295{
296 struct sockaddr *addr = p;
297
298 return temac_set_mac_address(ndev, addr->sa_data);
299}
300
92744989
GL		 301static void temac_set_multicast_list(struct net_device *ndev)
302{
303 struct temac_local *lp = netdev_priv(ndev);
304 u32 multi_addr_msw, multi_addr_lsw, val;
305 int i;
306
307 mutex_lock(&lp->indirect_mutex);
8e95a202 308 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
4cd24eaf 309 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
92744989
GL		 310 /*
311 * We must make the kernel realise we had to move
312 * into promisc mode or we start all out war on
313 * the cable. If it was a promisc request the
314 * flag is already set. If not we assert it.
315 */
316 ndev->flags |= IFF_PROMISC;
317 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
318 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
4cd24eaf 319 } else if (!netdev_mc_empty(ndev)) {
22bedad3 320 struct netdev_hw_addr *ha;
92744989 321
f9dcbcc9 322 i = 0;
22bedad3 323 netdev_for_each_mc_addr(ha, ndev) {
92744989
GL		 324 if (i >= MULTICAST_CAM_TABLE_NUM)
325 break;
22bedad3
JP		 326 multi_addr_msw = ((ha->addr[3] << 24) |
327 (ha->addr[2] << 16) |
328 (ha->addr[1] << 8) |
329 (ha->addr[0]));
92744989
GL		 330 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
331 multi_addr_msw);
22bedad3
JP		 332 multi_addr_lsw = ((ha->addr[5] << 8) |
333 (ha->addr[4]) | (i << 16));
92744989
GL		 334 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
335 multi_addr_lsw);
f9dcbcc9 336 i++;
92744989
GL		 337 }
338 } else {
339 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
340 temac_indirect_out32(lp, XTE_AFM_OFFSET,
341 val & ~XTE_AFM_EPPRM_MASK);
342 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
343 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
344 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
345 }
346 mutex_unlock(&lp->indirect_mutex);
347}
348
349struct temac_option {
350 int flg;
351 u32 opt;
352 u32 reg;
353 u32 m_or;
354 u32 m_and;
355} temac_options[] = {
356 /* Turn on jumbo packet support for both Rx and Tx */
357 {
358 .opt = XTE_OPTION_JUMBO,
359 .reg = XTE_TXC_OFFSET,
360 .m_or = XTE_TXC_TXJMBO_MASK,
361 },
362 {
363 .opt = XTE_OPTION_JUMBO,
364 .reg = XTE_RXC1_OFFSET,
365 .m_or =XTE_RXC1_RXJMBO_MASK,
366 },
367 /* Turn on VLAN packet support for both Rx and Tx */
368 {
369 .opt = XTE_OPTION_VLAN,
370 .reg = XTE_TXC_OFFSET,
371 .m_or =XTE_TXC_TXVLAN_MASK,
372 },
373 {
374 .opt = XTE_OPTION_VLAN,
375 .reg = XTE_RXC1_OFFSET,
376 .m_or =XTE_RXC1_RXVLAN_MASK,
377 },
378 /* Turn on FCS stripping on receive packets */
379 {
380 .opt = XTE_OPTION_FCS_STRIP,
381 .reg = XTE_RXC1_OFFSET,
382 .m_or =XTE_RXC1_RXFCS_MASK,
383 },
384 /* Turn on FCS insertion on transmit packets */
385 {
386 .opt = XTE_OPTION_FCS_INSERT,
387 .reg = XTE_TXC_OFFSET,
388 .m_or =XTE_TXC_TXFCS_MASK,
389 },
390 /* Turn on length/type field checking on receive packets */
391 {
392 .opt = XTE_OPTION_LENTYPE_ERR,
393 .reg = XTE_RXC1_OFFSET,
394 .m_or =XTE_RXC1_RXLT_MASK,
395 },
396 /* Turn on flow control */
397 {
398 .opt = XTE_OPTION_FLOW_CONTROL,
399 .reg = XTE_FCC_OFFSET,
400 .m_or =XTE_FCC_RXFLO_MASK,
401 },
402 /* Turn on flow control */
403 {
404 .opt = XTE_OPTION_FLOW_CONTROL,
405 .reg = XTE_FCC_OFFSET,
406 .m_or =XTE_FCC_TXFLO_MASK,
407 },
408 /* Turn on promiscuous frame filtering (all frames are received ) */
409 {
410 .opt = XTE_OPTION_PROMISC,
411 .reg = XTE_AFM_OFFSET,
412 .m_or =XTE_AFM_EPPRM_MASK,
413 },
414 /* Enable transmitter if not already enabled */
415 {
416 .opt = XTE_OPTION_TXEN,
417 .reg = XTE_TXC_OFFSET,
418 .m_or =XTE_TXC_TXEN_MASK,
419 },
420 /* Enable receiver? */
421 {
422 .opt = XTE_OPTION_RXEN,
423 .reg = XTE_RXC1_OFFSET,
424 .m_or =XTE_RXC1_RXEN_MASK,
425 },
426 {}
427};
428
429/**
430 * temac_setoptions
431 */
432static u32 temac_setoptions(struct net_device *ndev, u32 options)
433{
434 struct temac_local *lp = netdev_priv(ndev);
435 struct temac_option *tp = &temac_options[0];
436 int reg;
437
438 mutex_lock(&lp->indirect_mutex);
439 while (tp->opt) {
440 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
441 if (options & tp->opt)
442 reg |= tp->m_or;
443 temac_indirect_out32(lp, tp->reg, reg);
444 tp++;
445 }
446 lp->options |= options;
447 mutex_unlock(&lp->indirect_mutex);
448
449 return (0);
450}
451
452/* Initilize temac */
453static void temac_device_reset(struct net_device *ndev)
454{
455 struct temac_local *lp = netdev_priv(ndev);
456 u32 timeout;
457 u32 val;
458
459 /* Perform a software reset */
460
461 /* 0x300 host enable bit ? */
462 /* reset PHY through control register ?:1 */
463
464 dev_dbg(&ndev->dev, "%s()\n", __func__);
465
466 mutex_lock(&lp->indirect_mutex);
467 /* Reset the receiver and wait for it to finish reset */
468 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
469 timeout = 1000;
470 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
471 udelay(1);
472 if (--timeout == 0) {
473 dev_err(&ndev->dev,
474 "temac_device_reset RX reset timeout!!\n");
475 break;
476 }
477 }
478
479 /* Reset the transmitter and wait for it to finish reset */
480 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
481 timeout = 1000;
482 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
483 udelay(1);
484 if (--timeout == 0) {
485 dev_err(&ndev->dev,
486 "temac_device_reset TX reset timeout!!\n");
487 break;
488 }
489 }
490
491 /* Disable the receiver */
492 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
493 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
494
495 /* Reset Local Link (DMA) */
e44171f1 496 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
92744989 497 timeout = 1000;
e44171f1 498 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
92744989
GL		 499 udelay(1);
500 if (--timeout == 0) {
501 dev_err(&ndev->dev,
502 "temac_device_reset DMA reset timeout!!\n");
503 break;
504 }
505 }
e44171f1 506 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
92744989
GL		 507
508 temac_dma_bd_init(ndev);
509
510 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
511 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
512 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
513 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
514
515 mutex_unlock(&lp->indirect_mutex);
516
517 /* Sync default options with HW
518 * but leave receiver and transmitter disabled. */
519 temac_setoptions(ndev,
520 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
521
522 temac_set_mac_address(ndev, NULL);
523
524 /* Set address filter table */
525 temac_set_multicast_list(ndev);
526 if (temac_setoptions(ndev, lp->options))
527 dev_err(&ndev->dev, "Error setting TEMAC options\n");
528
529 /* Init Driver variable */
1ae5dc34 530 ndev->trans_start = jiffies; /* prevent tx timeout */
92744989
GL		 531}
532
533void temac_adjust_link(struct net_device *ndev)
534{
535 struct temac_local *lp = netdev_priv(ndev);
536 struct phy_device *phy = lp->phy_dev;
537 u32 mii_speed;
538 int link_state;
539
540 /* hash together the state values to decide if something has changed */
541 link_state = phy->speed | (phy->duplex << 1) | phy->link;
542
543 mutex_lock(&lp->indirect_mutex);
544 if (lp->last_link != link_state) {
545 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
546 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
547
548 switch (phy->speed) {
549 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
550 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
551 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
552 }
553
554 /* Write new speed setting out to TEMAC */
555 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
556 lp->last_link = link_state;
557 phy_print_status(phy);
558 }
559 mutex_unlock(&lp->indirect_mutex);
560}
561
562static void temac_start_xmit_done(struct net_device *ndev)
563{
564 struct temac_local *lp = netdev_priv(ndev);
565 struct cdmac_bd *cur_p;
566 unsigned int stat = 0;
567
568 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
569 stat = cur_p->app0;
570
571 while (stat & STS_CTRL_APP0_CMPLT) {
572 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
573 DMA_TO_DEVICE);
574 if (cur_p->app4)
575 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
576 cur_p->app0 = 0;
577
578 ndev->stats.tx_packets++;
579 ndev->stats.tx_bytes += cur_p->len;
580
581 lp->tx_bd_ci++;
582 if (lp->tx_bd_ci >= TX_BD_NUM)
583 lp->tx_bd_ci = 0;
584
585 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
586 stat = cur_p->app0;
587 }
588
589 netif_wake_queue(ndev);
590}
591
592static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
593{
594 struct temac_local *lp = netdev_priv(ndev);
595 struct cdmac_bd *cur_p;
596 dma_addr_t start_p, tail_p;
597 int ii;
598 unsigned long num_frag;
599 skb_frag_t *frag;
600
601 num_frag = skb_shinfo(skb)->nr_frags;
602 frag = &skb_shinfo(skb)->frags[0];
603 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
604 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
605
606 if (cur_p->app0 & STS_CTRL_APP0_CMPLT) {
607 if (!netif_queue_stopped(ndev)) {
608 netif_stop_queue(ndev);
609 return NETDEV_TX_BUSY;
610 }
611 return NETDEV_TX_BUSY;
612 }
613
614 cur_p->app0 = 0;
615 if (skb->ip_summed == CHECKSUM_PARTIAL) {
616 const struct iphdr *ip = ip_hdr(skb);
617 int length = 0, start = 0, insert = 0;
618
619 switch (ip->protocol) {
620 case IPPROTO_TCP:
621 start = sizeof(struct iphdr) + ETH_HLEN;
622 insert = sizeof(struct iphdr) + ETH_HLEN + 16;
623 length = ip->tot_len - sizeof(struct iphdr);
624 break;
625 case IPPROTO_UDP:
626 start = sizeof(struct iphdr) + ETH_HLEN;
627 insert = sizeof(struct iphdr) + ETH_HLEN + 6;
628 length = ip->tot_len - sizeof(struct iphdr);
629 break;
630 default:
631 break;
632 }
633 cur_p->app1 = ((start << 16) | insert);
634 cur_p->app2 = csum_tcpudp_magic(ip->saddr, ip->daddr,
635 length, ip->protocol, 0);
636 skb->data[insert] = 0;
637 skb->data[insert + 1] = 0;
638 }
639 cur_p->app0 |= STS_CTRL_APP0_SOP;
640 cur_p->len = skb_headlen(skb);
641 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
642 DMA_TO_DEVICE);
643 cur_p->app4 = (unsigned long)skb;
644
645 for (ii = 0; ii < num_frag; ii++) {
646 lp->tx_bd_tail++;
647 if (lp->tx_bd_tail >= TX_BD_NUM)
648 lp->tx_bd_tail = 0;
649
650 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
651 cur_p->phys = dma_map_single(ndev->dev.parent,
652 (void *)page_address(frag->page) +
653 frag->page_offset,
654 frag->size, DMA_TO_DEVICE);
655 cur_p->len = frag->size;
656 cur_p->app0 = 0;
657 frag++;
658 }
659 cur_p->app0 |= STS_CTRL_APP0_EOP;
660
661 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
662 lp->tx_bd_tail++;
663 if (lp->tx_bd_tail >= TX_BD_NUM)
664 lp->tx_bd_tail = 0;
665
666 /* Kick off the transfer */
e44171f1 667 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
92744989 668
6ed10654 669 return NETDEV_TX_OK;
92744989
GL		 670}
671
672
673static void ll_temac_recv(struct net_device *ndev)
674{
675 struct temac_local *lp = netdev_priv(ndev);
676 struct sk_buff *skb, *new_skb;
677 unsigned int bdstat;
678 struct cdmac_bd *cur_p;
679 dma_addr_t tail_p;
680 int length;
92744989
GL		 681 unsigned long flags;
682
683 spin_lock_irqsave(&lp->rx_lock, flags);
684
685 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
686 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
687
688 bdstat = cur_p->app0;
689 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
690
691 skb = lp->rx_skb[lp->rx_bd_ci];
c3b7c12c 692 length = cur_p->app4 & 0x3FFF;
92744989 693
33646d7f 694 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
92744989
GL		 695 DMA_FROM_DEVICE);
696
697 skb_put(skb, length);
698 skb->dev = ndev;
699 skb->protocol = eth_type_trans(skb, ndev);
700 skb->ip_summed = CHECKSUM_NONE;
701
702 netif_rx(skb);
703
704 ndev->stats.rx_packets++;
705 ndev->stats.rx_bytes += length;
706
e44171f1
JL		 707 new_skb = netdev_alloc_skb_ip_align(ndev,
708 XTE_MAX_JUMBO_FRAME_SIZE);
709
92744989
GL		 710 if (new_skb == 0) {
711 dev_err(&ndev->dev, "no memory for new sk_buff\n");
712 spin_unlock_irqrestore(&lp->rx_lock, flags);
713 return;
714 }
715
92744989
GL		 716 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
717 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
718 XTE_MAX_JUMBO_FRAME_SIZE,
719 DMA_FROM_DEVICE);
720 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
721 lp->rx_skb[lp->rx_bd_ci] = new_skb;
722
723 lp->rx_bd_ci++;
724 if (lp->rx_bd_ci >= RX_BD_NUM)
725 lp->rx_bd_ci = 0;
726
727 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
728 bdstat = cur_p->app0;
729 }
e44171f1 730 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
92744989
GL		 731
732 spin_unlock_irqrestore(&lp->rx_lock, flags);
733}
734
735static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
736{
737 struct net_device *ndev = _ndev;
738 struct temac_local *lp = netdev_priv(ndev);
739 unsigned int status;
740
e44171f1
JL		 741 status = lp->dma_in(lp, TX_IRQ_REG);
742 lp->dma_out(lp, TX_IRQ_REG, status);
92744989
GL		 743
744 if (status & (IRQ_COAL | IRQ_DLY))
745 temac_start_xmit_done(lp->ndev);
746 if (status & 0x080)
747 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
748
749 return IRQ_HANDLED;
750}
751
752static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
753{
754 struct net_device *ndev = _ndev;
755 struct temac_local *lp = netdev_priv(ndev);
756 unsigned int status;
757
758 /* Read and clear the status registers */
e44171f1
JL		 759 status = lp->dma_in(lp, RX_IRQ_REG);
760 lp->dma_out(lp, RX_IRQ_REG, status);
92744989
GL		 761
762 if (status & (IRQ_COAL | IRQ_DLY))
763 ll_temac_recv(lp->ndev);
764
765 return IRQ_HANDLED;
766}
767
768static int temac_open(struct net_device *ndev)
769{
770 struct temac_local *lp = netdev_priv(ndev);
771 int rc;
772
773 dev_dbg(&ndev->dev, "temac_open()\n");
774
775 if (lp->phy_node) {
776 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
777 temac_adjust_link, 0, 0);
778 if (!lp->phy_dev) {
779 dev_err(lp->dev, "of_phy_connect() failed\n");
780 return -ENODEV;
781 }
782
783 phy_start(lp->phy_dev);
784 }
785
786 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
787 if (rc)
788 goto err_tx_irq;
789 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
790 if (rc)
791 goto err_rx_irq;
792
793 temac_device_reset(ndev);
794 return 0;
795
796 err_rx_irq:
797 free_irq(lp->tx_irq, ndev);
798 err_tx_irq:
799 if (lp->phy_dev)
800 phy_disconnect(lp->phy_dev);
801 lp->phy_dev = NULL;
802 dev_err(lp->dev, "request_irq() failed\n");
803 return rc;
804}
805
806static int temac_stop(struct net_device *ndev)
807{
808 struct temac_local *lp = netdev_priv(ndev);
809
810 dev_dbg(&ndev->dev, "temac_close()\n");
811
812 free_irq(lp->tx_irq, ndev);
813 free_irq(lp->rx_irq, ndev);
814
815 if (lp->phy_dev)
816 phy_disconnect(lp->phy_dev);
817 lp->phy_dev = NULL;
818
819 return 0;
820}
821
822#ifdef CONFIG_NET_POLL_CONTROLLER
823static void
824temac_poll_controller(struct net_device *ndev)
825{
826 struct temac_local *lp = netdev_priv(ndev);
827
828 disable_irq(lp->tx_irq);
829 disable_irq(lp->rx_irq);
830
831 ll_temac_rx_irq(lp->tx_irq, lp);
832 ll_temac_tx_irq(lp->rx_irq, lp);
833
834 enable_irq(lp->tx_irq);
835 enable_irq(lp->rx_irq);
836}
837#endif
838
839static const struct net_device_ops temac_netdev_ops = {
840 .ndo_open = temac_open,
841 .ndo_stop = temac_stop,
842 .ndo_start_xmit = temac_start_xmit,
8ea7a37c 843 .ndo_set_mac_address = netdev_set_mac_address,
92744989
GL		 844 //.ndo_set_multicast_list = temac_set_multicast_list,
845#ifdef CONFIG_NET_POLL_CONTROLLER
846 .ndo_poll_controller = temac_poll_controller,
847#endif
848};
849
850/* ---------------------------------------------------------------------
851 * SYSFS device attributes
852 */
853static ssize_t temac_show_llink_regs(struct device *dev,
854 struct device_attribute *attr, char *buf)
855{
856 struct net_device *ndev = dev_get_drvdata(dev);
857 struct temac_local *lp = netdev_priv(ndev);
858 int i, len = 0;
859
860 for (i = 0; i < 0x11; i++)
e44171f1 861 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
92744989
GL		 862 (i % 8) == 7 ? "\n" : " ");
863 len += sprintf(buf + len, "\n");
864
865 return len;
866}
867
868static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
869
870static struct attribute *temac_device_attrs[] = {
871 &dev_attr_llink_regs.attr,
872 NULL,
873};
874
875static const struct attribute_group temac_attr_group = {
876 .attrs = temac_device_attrs,
877};
878
879static int __init
880temac_of_probe(struct of_device *op, const struct of_device_id *match)
881{
882 struct device_node *np;
883 struct temac_local *lp;
884 struct net_device *ndev;
885 const void *addr;
886 int size, rc = 0;
92744989
GL		 887
888 /* Init network device structure */
889 ndev = alloc_etherdev(sizeof(*lp));
890 if (!ndev) {
891 dev_err(&op->dev, "could not allocate device.\n");
892 return -ENOMEM;
893 }
894 ether_setup(ndev);
895 dev_set_drvdata(&op->dev, ndev);
896 SET_NETDEV_DEV(ndev, &op->dev);
897 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
898 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
899 ndev->netdev_ops = &temac_netdev_ops;
900#if 0
901 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
902 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
903 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
904 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
905 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
906 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
907 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
908 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
909 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
910 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
911 ndev->features |= NETIF_F_LRO; /* large receive offload */
912#endif
913
914 /* setup temac private info structure */
915 lp = netdev_priv(ndev);
916 lp->ndev = ndev;
917 lp->dev = &op->dev;
918 lp->options = XTE_OPTION_DEFAULTS;
919 spin_lock_init(&lp->rx_lock);
920 mutex_init(&lp->indirect_mutex);
921
922 /* map device registers */
923 lp->regs = of_iomap(op->node, 0);
924 if (!lp->regs) {
925 dev_err(&op->dev, "could not map temac regs.\n");
926 goto nodev;
927 }
928
929 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
930 np = of_parse_phandle(op->node, "llink-connected", 0);
931 if (!np) {
932 dev_err(&op->dev, "could not find DMA node\n");
933 goto nodev;
934 }
935
e44171f1
JL		 936 /* Setup the DMA register accesses, could be DCR or memory mapped */
937 if (temac_dcr_setup(lp, op, np)) {
938
939 /* no DCR in the device tree, try non-DCR */
940 lp->sdma_regs = of_iomap(np, 0);
941 if (lp->sdma_regs) {
942 lp->dma_in = temac_dma_in32;
943 lp->dma_out = temac_dma_out32;
944 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
945 } else {
946 dev_err(&op->dev, "unable to map DMA registers\n");
947 goto nodev;
948 }
92744989 949 }
92744989
GL		 950
951 lp->rx_irq = irq_of_parse_and_map(np, 0);
952 lp->tx_irq = irq_of_parse_and_map(np, 1);
953 if (!lp->rx_irq || !lp->tx_irq) {
954 dev_err(&op->dev, "could not determine irqs\n");
955 rc = -ENOMEM;
956 goto nodev;
957 }
958
959 of_node_put(np); /* Finished with the DMA node; drop the reference */
960
961 /* Retrieve the MAC address */
962 addr = of_get_property(op->node, "local-mac-address", &size);
963 if ((!addr) || (size != 6)) {
964 dev_err(&op->dev, "could not find MAC address\n");
965 rc = -ENODEV;
966 goto nodev;
967 }
968 temac_set_mac_address(ndev, (void *)addr);
969
970 rc = temac_mdio_setup(lp, op->node);
971 if (rc)
972 dev_warn(&op->dev, "error registering MDIO bus\n");
973
974 lp->phy_node = of_parse_phandle(op->node, "phy-handle", 0);
975 if (lp->phy_node)
976 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
977
978 /* Add the device attributes */
979 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
980 if (rc) {
981 dev_err(lp->dev, "Error creating sysfs files\n");
982 goto nodev;
983 }
984
985 rc = register_netdev(lp->ndev);
986 if (rc) {
987 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
988 goto err_register_ndev;
989 }
990
991 return 0;
992
993 err_register_ndev:
994 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
995 nodev:
996 free_netdev(ndev);
997 ndev = NULL;
998 return rc;
999}
1000
1001static int __devexit temac_of_remove(struct of_device *op)
1002{
1003 struct net_device *ndev = dev_get_drvdata(&op->dev);
1004 struct temac_local *lp = netdev_priv(ndev);
1005
1006 temac_mdio_teardown(lp);
1007 unregister_netdev(ndev);
1008 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1009 if (lp->phy_node)
1010 of_node_put(lp->phy_node);
1011 lp->phy_node = NULL;
1012 dev_set_drvdata(&op->dev, NULL);
1013 free_netdev(ndev);
1014 return 0;
1015}
1016
1017static struct of_device_id temac_of_match[] __devinitdata = {
1018 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
c3b7c12c
SM		 1019 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1020 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1021 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
92744989
GL		 1022 {},
1023};
1024MODULE_DEVICE_TABLE(of, temac_of_match);
1025
1026static struct of_platform_driver temac_of_driver = {
1027 .match_table = temac_of_match,
1028 .probe = temac_of_probe,
1029 .remove = __devexit_p(temac_of_remove),
1030 .driver = {
1031 .owner = THIS_MODULE,
1032 .name = "xilinx_temac",
1033 },
1034};
1035
1036static int __init temac_init(void)
1037{
1038 return of_register_platform_driver(&temac_of_driver);
1039}
1040module_init(temac_init);
1041
1042static void __exit temac_exit(void)
1043{
1044 of_unregister_platform_driver(&temac_of_driver);
1045}
1046module_exit(temac_exit);
1047
1048MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1049MODULE_AUTHOR("Yoshio Kashiwagi");
1050MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree