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netxen: fix firmware download
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
04193058 50#define DRV_VERSION "2.0.16-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 52static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
e8e26350 56 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 57};
58
59/* ixgbe_pci_tbl - PCI Device ID Table
60 *
61 * Wildcard entries (PCI_ANY_ID) should come last
62 * Last entry must be all 0s
63 *
64 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
65 * Class, Class Mask, private data (not used) }
66 */
67static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 68 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
69 board_82598 },
9a799d71 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 73 board_82598 },
0befdb3e
JB		 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
75 board_82598 },
9a799d71 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 77 board_82598 },
8d792cd9
JB		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
79 board_82598 },
c4900be0
DS		 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
81 board_82598 },
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
83 board_82598 },
b95f5fcb
JB		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
85 board_82598 },
c4900be0
DS		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
87 board_82598 },
2f21bdd3
DS		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
89 board_82598 },
e8e26350
PW		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
91 board_82599 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
93 board_82599 },
9a799d71
AK		 94
95 /* required last entry */
96 {0, }
97};
98MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
99
5dd2d332 100#ifdef CONFIG_IXGBE_DCA
bd0362dd 101static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 102 void *p);
bd0362dd
JC		 103static struct notifier_block dca_notifier = {
104 .notifier_call = ixgbe_notify_dca,
105 .next = NULL,
106 .priority = 0
107};
108#endif
109
9a799d71
AK		 110MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
111MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
112MODULE_LICENSE("GPL");
113MODULE_VERSION(DRV_VERSION);
114
115#define DEFAULT_DEBUG_LEVEL_SHIFT 3
116
5eba3699
AV		 117static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
118{
119 u32 ctrl_ext;
120
121 /* Let firmware take over control of h/w */
122 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
123 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 124 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 125}
126
127static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware know the driver has taken over */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 135}
9a799d71 136
e8e26350
PW		 137/*
138 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
139 * @adapter: pointer to adapter struct
140 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
141 * @queue: queue to map the corresponding interrupt to
142 * @msix_vector: the vector to map to the corresponding queue
143 *
144 */
145static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
146 u8 queue, u8 msix_vector)
9a799d71
AK		 147{
148 u32 ivar, index;
e8e26350
PW		 149 struct ixgbe_hw *hw = &adapter->hw;
150 switch (hw->mac.type) {
151 case ixgbe_mac_82598EB:
152 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
153 if (direction == -1)
154 direction = 0;
155 index = (((direction * 64) + queue) >> 2) & 0x1F;
156 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
157 ivar &= ~(0xFF << (8 * (queue & 0x3)));
158 ivar |= (msix_vector << (8 * (queue & 0x3)));
159 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
160 break;
161 case ixgbe_mac_82599EB:
162 if (direction == -1) {
163 /* other causes */
164 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
165 index = ((queue & 1) * 8);
166 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
167 ivar &= ~(0xFF << index);
168 ivar |= (msix_vector << index);
169 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
170 break;
171 } else {
172 /* tx or rx causes */
173 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
174 index = ((16 * (queue & 1)) + (8 * direction));
175 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
176 ivar &= ~(0xFF << index);
177 ivar |= (msix_vector << index);
178 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
179 break;
180 }
181 default:
182 break;
183 }
9a799d71
AK		 184}
185
186static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 187 struct ixgbe_tx_buffer
188 *tx_buffer_info)
9a799d71 189{
44df32c5 190 tx_buffer_info->dma = 0;
9a799d71 191 if (tx_buffer_info->skb) {
44df32c5
AD		 192 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
193 DMA_TO_DEVICE);
9a799d71
AK		 194 dev_kfree_skb_any(tx_buffer_info->skb);
195 tx_buffer_info->skb = NULL;
196 }
44df32c5 197 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 198 /* tx_buffer_info must be completely set up in the transmit path */
199}
200
201static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 202 struct ixgbe_ring *tx_ring,
203 unsigned int eop)
9a799d71 204{
e01c31a5 205 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 206
9a799d71 207 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 208 * check with the clearing of time_stamp and movement of eop */
9a799d71 209 adapter->detect_tx_hung = false;
44df32c5 210 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 211 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
212 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
213 /* detected Tx unit hang */
e01c31a5
JB		 214 union ixgbe_adv_tx_desc *tx_desc;
215 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 216 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 217 " Tx Queue <%d>\n"
218 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 219 " next_to_use <%x>\n"
220 " next_to_clean <%x>\n"
221 "tx_buffer_info[next_to_clean]\n"
222 " time_stamp <%lx>\n"
e01c31a5
JB		 223 " jiffies <%lx>\n",
224 tx_ring->queue_index,
44df32c5
AD		 225 IXGBE_READ_REG(hw, tx_ring->head),
226 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 227 tx_ring->next_to_use, eop,
228 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 229 return true;
230 }
231
232 return false;
233}
234
b4617240
PW		 235#define IXGBE_MAX_TXD_PWR 14
236#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 237
238/* Tx Descriptors needed, worst case */
239#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
240 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
241#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 242 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 243
e01c31a5
JB		 244static void ixgbe_tx_timeout(struct net_device *netdev);
245
9a799d71
AK		 246/**
247 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
248 * @adapter: board private structure
e01c31a5 249 * @tx_ring: tx ring to clean
9a1a69ad
JB		 250 *
251 * returns true if transmit work is done
9a799d71
AK		 252 **/
253static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 254 struct ixgbe_ring *tx_ring)
9a799d71 255{
e01c31a5 256 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 257 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
258 struct ixgbe_tx_buffer *tx_buffer_info;
259 unsigned int i, eop, count = 0;
e01c31a5 260 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 261
262 i = tx_ring->next_to_clean;
12207e49
PWJ		 263 eop = tx_ring->tx_buffer_info[i].next_to_watch;
264 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
265
266 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 267 (count < tx_ring->work_limit)) {
12207e49
PWJ		 268 bool cleaned = false;
269 for ( ; !cleaned; count++) {
270 struct sk_buff *skb;
9a799d71
AK		 271 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
272 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 273 cleaned = (i == eop);
e01c31a5 274 skb = tx_buffer_info->skb;
9a799d71 275
12207e49 276 if (cleaned && skb) {
e092be60 277 unsigned int segs, bytecount;
e01c31a5
JB		 278
279 /* gso_segs is currently only valid for tcp */
e092be60
AV		 280 segs = skb_shinfo(skb)->gso_segs ?: 1;
281 /* multiply data chunks by size of headers */
282 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 283 skb->len;
284 total_packets += segs;
285 total_bytes += bytecount;
e092be60 286 }
e01c31a5 287
9a799d71 288 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 289 tx_buffer_info);
9a799d71 290
12207e49
PWJ		 291 tx_desc->wb.status = 0;
292
9a799d71
AK		 293 i++;
294 if (i == tx_ring->count)
295 i = 0;
e01c31a5 296 }
12207e49
PWJ		 297
298 eop = tx_ring->tx_buffer_info[i].next_to_watch;
299 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
300 }
301
9a799d71
AK		 302 tx_ring->next_to_clean = i;
303
e092be60 304#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 305 if (unlikely(count && netif_carrier_ok(netdev) &&
306 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 307 /* Make sure that anybody stopping the queue after this
308 * sees the new next_to_clean.
309 */
310 smp_mb();
30eba97a
AV		 311 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
312 !test_bit(__IXGBE_DOWN, &adapter->state)) {
313 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 314 ++adapter->restart_queue;
30eba97a 315 }
e092be60 316 }
9a799d71 317
e01c31a5
JB		 318 if (adapter->detect_tx_hung) {
319 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
320 /* schedule immediate reset if we believe we hung */
321 DPRINTK(PROBE, INFO,
322 "tx hang %d detected, resetting adapter\n",
323 adapter->tx_timeout_count + 1);
324 ixgbe_tx_timeout(adapter->netdev);
325 }
326 }
9a799d71 327
e01c31a5 328 /* re-arm the interrupt */
835462fc
NS		 329 if (count >= tx_ring->work_limit) {
330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
332 tx_ring->v_idx);
333 else if (tx_ring->v_idx & 0xFFFFFFFF)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
335 tx_ring->v_idx);
336 else
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
338 (tx_ring->v_idx >> 32));
339 }
340
9a799d71 341
e01c31a5
JB		 342 tx_ring->total_bytes += total_bytes;
343 tx_ring->total_packets += total_packets;
e01c31a5 344 tx_ring->stats.packets += total_packets;
12207e49 345 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 346 adapter->net_stats.tx_bytes += total_bytes;
347 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 348 return (count < tx_ring->work_limit);
9a799d71
AK		 349}
350
5dd2d332 351#ifdef CONFIG_IXGBE_DCA
bd0362dd 352static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 353 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 354{
355 u32 rxctrl;
356 int cpu = get_cpu();
3a581073 357 int q = rx_ring - adapter->rx_ring;
bd0362dd 358
3a581073 359 if (rx_ring->cpu != cpu) {
bd0362dd 360 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 361 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
362 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
363 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
364 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
366 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
367 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
368 }
bd0362dd
JC		 369 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
370 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 371 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
372 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 373 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 374 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 375 rx_ring->cpu = cpu;
bd0362dd
JC		 376 }
377 put_cpu();
378}
379
380static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 381 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 382{
383 u32 txctrl;
384 int cpu = get_cpu();
3a581073 385 int q = tx_ring - adapter->tx_ring;
bd0362dd 386
3a581073 387 if (tx_ring->cpu != cpu) {
bd0362dd 388 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 389 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
390 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
391 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
392 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
394 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
395 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
396 }
bd0362dd
JC		 397 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
398 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 399 tx_ring->cpu = cpu;
bd0362dd
JC		 400 }
401 put_cpu();
402}
403
404static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
405{
406 int i;
407
408 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
409 return;
410
411 for (i = 0; i < adapter->num_tx_queues; i++) {
412 adapter->tx_ring[i].cpu = -1;
413 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
414 }
415 for (i = 0; i < adapter->num_rx_queues; i++) {
416 adapter->rx_ring[i].cpu = -1;
417 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
418 }
419}
420
421static int __ixgbe_notify_dca(struct device *dev, void *data)
422{
423 struct net_device *netdev = dev_get_drvdata(dev);
424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
425 unsigned long event = *(unsigned long *)data;
426
427 switch (event) {
428 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 429 /* if we're already enabled, don't do it again */
430 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
431 break;
bd0362dd
JC		 432 /* Always use CB2 mode, difference is masked
433 * in the CB driver. */
434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 435 if (dca_add_requester(dev) == 0) {
96b0e0f6 436 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 437 ixgbe_setup_dca(adapter);
438 break;
439 }
440 /* Fall Through since DCA is disabled. */
441 case DCA_PROVIDER_REMOVE:
442 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
443 dca_remove_requester(dev);
444 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
446 }
447 break;
448 }
449
652f093f 450 return 0;
bd0362dd
JC		 451}
452
5dd2d332 453#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 454/**
455 * ixgbe_receive_skb - Send a completed packet up the stack
456 * @adapter: board private structure
457 * @skb: packet to send up
177db6ff
MC		 458 * @status: hardware indication of status of receive
459 * @rx_ring: rx descriptor ring (for a specific queue) to setup
460 * @rx_desc: rx descriptor
9a799d71 461 **/
78b6f4ce 462static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 463 struct sk_buff *skb, u8 status,
177db6ff 464 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 465{
78b6f4ce
HX		 466 struct ixgbe_adapter *adapter = q_vector->adapter;
467 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 468 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
469 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 470
0c8dfc83 471 skb_record_rx_queue(skb, q_vector - &adapter->q_vector[0]);
182ff8df 472 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 473 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 474 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 475 else
78b6f4ce 476 napi_gro_receive(napi, skb);
177db6ff 477 } else {
182ff8df
AD		 478 if (adapter->vlgrp && is_vlan && (tag != 0))
479 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
480 else
481 netif_rx(skb);
9a799d71
AK		 482 }
483}
484
e59bd25d
AV		 485/**
486 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
487 * @adapter: address of board private structure
488 * @status_err: hardware indication of status of receive
489 * @skb: skb currently being received and modified
490 **/
9a799d71 491static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 492 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 493{
494 skb->ip_summed = CHECKSUM_NONE;
495
712744be
JB		 496 /* Rx csum disabled */
497 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 498 return;
e59bd25d
AV		 499
500 /* if IP and error */
501 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
502 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 503 adapter->hw_csum_rx_error++;
504 return;
505 }
e59bd25d
AV		 506
507 if (!(status_err & IXGBE_RXD_STAT_L4CS))
508 return;
509
510 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
511 adapter->hw_csum_rx_error++;
512 return;
513 }
514
9a799d71 515 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 516 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 517 adapter->hw_csum_rx_good++;
518}
519
e8e26350
PW		 520static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
521 struct ixgbe_ring *rx_ring, u32 val)
522{
523 /*
524 * Force memory writes to complete before letting h/w
525 * know there are new descriptors to fetch. (Only
526 * applicable for weak-ordered memory model archs,
527 * such as IA-64).
528 */
529 wmb();
530 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
531}
532
9a799d71
AK		 533/**
534 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
535 * @adapter: address of board private structure
536 **/
537static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 538 struct ixgbe_ring *rx_ring,
539 int cleaned_count)
9a799d71 540{
9a799d71
AK		 541 struct pci_dev *pdev = adapter->pdev;
542 union ixgbe_adv_rx_desc *rx_desc;
3a581073 543 struct ixgbe_rx_buffer *bi;
9a799d71 544 unsigned int i;
e8e26350 545 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 546
547 i = rx_ring->next_to_use;
3a581073 548 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 549
550 while (cleaned_count--) {
551 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
552
762f4c57 553 if (!bi->page_dma &&
3a581073 554 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 555 if (!bi->page) {
762f4c57
JB		 556 bi->page = alloc_page(GFP_ATOMIC);
557 if (!bi->page) {
558 adapter->alloc_rx_page_failed++;
559 goto no_buffers;
560 }
561 bi->page_offset = 0;
562 } else {
563 /* use a half page if we're re-using */
564 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 565 }
762f4c57
JB		 566
567 bi->page_dma = pci_map_page(pdev, bi->page,
568 bi->page_offset,
569 (PAGE_SIZE / 2),
570 PCI_DMA_FROMDEVICE);
9a799d71
AK		 571 }
572
3a581073 573 if (!bi->skb) {
5ecc3614 574 struct sk_buff *skb;
e8e26350 575 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 576
577 if (!skb) {
578 adapter->alloc_rx_buff_failed++;
579 goto no_buffers;
580 }
581
582 /*
583 * Make buffer alignment 2 beyond a 16 byte boundary
584 * this will result in a 16 byte aligned IP header after
585 * the 14 byte MAC header is removed
586 */
587 skb_reserve(skb, NET_IP_ALIGN);
588
3a581073 589 bi->skb = skb;
e8e26350 590 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 591 PCI_DMA_FROMDEVICE);
9a799d71
AK		 592 }
593 /* Refresh the desc even if buffer_addrs didn't change because
594 * each write-back erases this info. */
595 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 596 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
597 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 598 } else {
3a581073 599 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 600 }
601
602 i++;
603 if (i == rx_ring->count)
604 i = 0;
3a581073 605 bi = &rx_ring->rx_buffer_info[i];
9a799d71 606 }
7c6e0a43 607
9a799d71
AK		 608no_buffers:
609 if (rx_ring->next_to_use != i) {
610 rx_ring->next_to_use = i;
611 if (i-- == 0)
612 i = (rx_ring->count - 1);
613
e8e26350 614 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 615 }
616}
617
7c6e0a43
JB		 618static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
619{
620 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
621}
622
623static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
624{
625 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
626}
627
f8212f97
AD		 628static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
629{
630 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
631 IXGBE_RXDADV_RSCCNT_MASK) >>
632 IXGBE_RXDADV_RSCCNT_SHIFT;
633}
634
635/**
636 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
637 * @skb: pointer to the last skb in the rsc queue
638 *
639 * This function changes a queue full of hw rsc buffers into a completed
640 * packet. It uses the ->prev pointers to find the first packet and then
641 * turns it into the frag list owner.
642 **/
643static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
644{
645 unsigned int frag_list_size = 0;
646
647 while (skb->prev) {
648 struct sk_buff *prev = skb->prev;
649 frag_list_size += skb->len;
650 skb->prev = NULL;
651 skb = prev;
652 }
653
654 skb_shinfo(skb)->frag_list = skb->next;
655 skb->next = NULL;
656 skb->len += frag_list_size;
657 skb->data_len += frag_list_size;
658 skb->truesize += frag_list_size;
659 return skb;
660}
661
78b6f4ce 662static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 663 struct ixgbe_ring *rx_ring,
664 int *work_done, int work_to_do)
9a799d71 665{
78b6f4ce 666 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 667 struct pci_dev *pdev = adapter->pdev;
668 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
669 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
670 struct sk_buff *skb;
f8212f97 671 unsigned int i, rsc_count = 0;
7c6e0a43 672 u32 len, staterr;
177db6ff
MC		 673 u16 hdr_info;
674 bool cleaned = false;
9a799d71 675 int cleaned_count = 0;
d2f4fbe2 676 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 677
678 i = rx_ring->next_to_clean;
9a799d71
AK		 679 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
680 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
681 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 682
683 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 684 u32 upper_len = 0;
9a799d71
AK		 685 if (*work_done >= work_to_do)
686 break;
687 (*work_done)++;
688
689 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 690 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
691 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 692 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 693 if (hdr_info & IXGBE_RXDADV_SPH)
694 adapter->rx_hdr_split++;
695 if (len > IXGBE_RX_HDR_SIZE)
696 len = IXGBE_RX_HDR_SIZE;
697 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 698 } else {
9a799d71 699 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 700 }
9a799d71
AK		 701
702 cleaned = true;
703 skb = rx_buffer_info->skb;
704 prefetch(skb->data - NET_IP_ALIGN);
705 rx_buffer_info->skb = NULL;
706
707 if (len && !skb_shinfo(skb)->nr_frags) {
708 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 709 rx_ring->rx_buf_len,
b4617240 710 PCI_DMA_FROMDEVICE);
9a799d71
AK		 711 skb_put(skb, len);
712 }
713
714 if (upper_len) {
715 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 716 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 717 rx_buffer_info->page_dma = 0;
718 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 719 rx_buffer_info->page,
720 rx_buffer_info->page_offset,
721 upper_len);
722
723 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
724 (page_count(rx_buffer_info->page) != 1))
725 rx_buffer_info->page = NULL;
726 else
727 get_page(rx_buffer_info->page);
9a799d71
AK		 728
729 skb->len += upper_len;
730 skb->data_len += upper_len;
731 skb->truesize += upper_len;
732 }
733
734 i++;
735 if (i == rx_ring->count)
736 i = 0;
9a799d71
AK		 737
738 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
739 prefetch(next_rxd);
9a799d71 740 cleaned_count++;
f8212f97
AD		 741
742 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
743 rsc_count = ixgbe_get_rsc_count(rx_desc);
744
745 if (rsc_count) {
746 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
747 IXGBE_RXDADV_NEXTP_SHIFT;
748 next_buffer = &rx_ring->rx_buffer_info[nextp];
749 rx_ring->rsc_count += (rsc_count - 1);
750 } else {
751 next_buffer = &rx_ring->rx_buffer_info[i];
752 }
753
9a799d71 754 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 755 if (skb->prev)
756 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 757 rx_ring->stats.packets++;
758 rx_ring->stats.bytes += skb->len;
759 } else {
f8212f97
AD		 760 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
761 rx_buffer_info->skb = next_buffer->skb;
762 rx_buffer_info->dma = next_buffer->dma;
763 next_buffer->skb = skb;
764 next_buffer->dma = 0;
765 } else {
766 skb->next = next_buffer->skb;
767 skb->next->prev = skb;
768 }
9a799d71
AK		 769 adapter->non_eop_descs++;
770 goto next_desc;
771 }
772
773 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
774 dev_kfree_skb_irq(skb);
775 goto next_desc;
776 }
777
778 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 779
780 /* probably a little skewed due to removing CRC */
781 total_rx_bytes += skb->len;
782 total_rx_packets++;
783
74ce8dd2 784 skb->protocol = eth_type_trans(skb, adapter->netdev);
78b6f4ce 785 ixgbe_receive_skb(q_vector, skb, staterr, rx_desc);
9a799d71
AK		 786
787next_desc:
788 rx_desc->wb.upper.status_error = 0;
789
790 /* return some buffers to hardware, one at a time is too slow */
791 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
792 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
793 cleaned_count = 0;
794 }
795
796 /* use prefetched values */
797 rx_desc = next_rxd;
f8212f97 798 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 799
800 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 801 }
802
9a799d71
AK		 803 rx_ring->next_to_clean = i;
804 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
805
806 if (cleaned_count)
807 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
808
f494e8fa
AV		 809 rx_ring->total_packets += total_rx_packets;
810 rx_ring->total_bytes += total_rx_bytes;
811 adapter->net_stats.rx_bytes += total_rx_bytes;
812 adapter->net_stats.rx_packets += total_rx_packets;
813
9a799d71
AK		 814 return cleaned;
815}
816
021230d4 817static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 818/**
819 * ixgbe_configure_msix - Configure MSI-X hardware
820 * @adapter: board private structure
821 *
822 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
823 * interrupts.
824 **/
825static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
826{
021230d4
AV		 827 struct ixgbe_q_vector *q_vector;
828 int i, j, q_vectors, v_idx, r_idx;
829 u32 mask;
9a799d71 830
021230d4 831 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 832
4df10466
JB		 833 /*
834 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 835 * corresponding register.
836 */
837 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
838 q_vector = &adapter->q_vector[v_idx];
839 /* XXX for_each_bit(...) */
840 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 841 adapter->num_rx_queues);
021230d4
AV		 842
843 for (i = 0; i < q_vector->rxr_count; i++) {
844 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 845 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 846 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 847 adapter->num_rx_queues,
848 r_idx + 1);
021230d4
AV		 849 }
850 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 851 adapter->num_tx_queues);
021230d4
AV		 852
853 for (i = 0; i < q_vector->txr_count; i++) {
854 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 855 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 856 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 857 adapter->num_tx_queues,
858 r_idx + 1);
021230d4
AV		 859 }
860
30efa5a3 861 /* if this is a tx only vector halve the interrupt rate */
021230d4 862 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 863 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 864 else if (q_vector->rxr_count)
30efa5a3
JB		 865 /* rx only */
866 q_vector->eitr = adapter->eitr_param;
021230d4 867
509ee935 868 /*
4df10466 869 * since this is initial set up don't need to call
509ee935
JB		 870 * ixgbe_write_eitr helper
871 */
021230d4 872 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 873 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 874 }
875
e8e26350
PW		 876 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
877 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
878 v_idx);
879 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
880 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
882
41fb9248 883 /* set up to autoclear timer, and the vectors */
021230d4 884 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 885 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 887}
888
f494e8fa
AV		 889enum latency_range {
890 lowest_latency = 0,
891 low_latency = 1,
892 bulk_latency = 2,
893 latency_invalid = 255
894};
895
896/**
897 * ixgbe_update_itr - update the dynamic ITR value based on statistics
898 * @adapter: pointer to adapter
899 * @eitr: eitr setting (ints per sec) to give last timeslice
900 * @itr_setting: current throttle rate in ints/second
901 * @packets: the number of packets during this measurement interval
902 * @bytes: the number of bytes during this measurement interval
903 *
904 * Stores a new ITR value based on packets and byte
905 * counts during the last interrupt. The advantage of per interrupt
906 * computation is faster updates and more accurate ITR for the current
907 * traffic pattern. Constants in this function were computed
908 * based on theoretical maximum wire speed and thresholds were set based
909 * on testing data as well as attempting to minimize response time
910 * while increasing bulk throughput.
911 * this functionality is controlled by the InterruptThrottleRate module
912 * parameter (see ixgbe_param.c)
913 **/
914static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 915 u32 eitr, u8 itr_setting,
916 int packets, int bytes)
f494e8fa
AV		 917{
918 unsigned int retval = itr_setting;
919 u32 timepassed_us;
920 u64 bytes_perint;
921
922 if (packets == 0)
923 goto update_itr_done;
924
925
926 /* simple throttlerate management
927 * 0-20MB/s lowest (100000 ints/s)
928 * 20-100MB/s low (20000 ints/s)
929 * 100-1249MB/s bulk (8000 ints/s)
930 */
931 /* what was last interrupt timeslice? */
932 timepassed_us = 1000000/eitr;
933 bytes_perint = bytes / timepassed_us; /* bytes/usec */
934
935 switch (itr_setting) {
936 case lowest_latency:
937 if (bytes_perint > adapter->eitr_low)
938 retval = low_latency;
939 break;
940 case low_latency:
941 if (bytes_perint > adapter->eitr_high)
942 retval = bulk_latency;
943 else if (bytes_perint <= adapter->eitr_low)
944 retval = lowest_latency;
945 break;
946 case bulk_latency:
947 if (bytes_perint <= adapter->eitr_high)
948 retval = low_latency;
949 break;
950 }
951
952update_itr_done:
953 return retval;
954}
955
509ee935
JB		 956/**
957 * ixgbe_write_eitr - write EITR register in hardware specific way
958 * @adapter: pointer to adapter struct
959 * @v_idx: vector index into q_vector array
960 * @itr_reg: new value to be written in *register* format, not ints/s
961 *
962 * This function is made to be called by ethtool and by the driver
963 * when it needs to update EITR registers at runtime. Hardware
964 * specific quirks/differences are taken care of here.
965 */
966void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
967{
968 struct ixgbe_hw *hw = &adapter->hw;
969 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
970 /* must write high and low 16 bits to reset counter */
971 itr_reg |= (itr_reg << 16);
972 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
973 /*
974 * set the WDIS bit to not clear the timer bits and cause an
975 * immediate assertion of the interrupt
976 */
977 itr_reg |= IXGBE_EITR_CNT_WDIS;
978 }
979 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
980}
981
f494e8fa
AV		 982static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
983{
984 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 985 u32 new_itr;
986 u8 current_itr, ret_itr;
987 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 988 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 989 struct ixgbe_ring *rx_ring, *tx_ring;
990
991 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
992 for (i = 0; i < q_vector->txr_count; i++) {
993 tx_ring = &(adapter->tx_ring[r_idx]);
994 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 995 q_vector->tx_itr,
996 tx_ring->total_packets,
997 tx_ring->total_bytes);
f494e8fa
AV		 998 /* if the result for this queue would decrease interrupt
999 * rate for this vector then use that result */
30efa5a3 1000 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1001 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1002 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1003 r_idx + 1);
f494e8fa
AV		 1004 }
1005
1006 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1007 for (i = 0; i < q_vector->rxr_count; i++) {
1008 rx_ring = &(adapter->rx_ring[r_idx]);
1009 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1010 q_vector->rx_itr,
1011 rx_ring->total_packets,
1012 rx_ring->total_bytes);
f494e8fa
AV		 1013 /* if the result for this queue would decrease interrupt
1014 * rate for this vector then use that result */
30efa5a3 1015 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1016 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1017 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1018 r_idx + 1);
f494e8fa
AV		 1019 }
1020
30efa5a3 1021 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1022
1023 switch (current_itr) {
1024 /* counts and packets in update_itr are dependent on these numbers */
1025 case lowest_latency:
1026 new_itr = 100000;
1027 break;
1028 case low_latency:
1029 new_itr = 20000; /* aka hwitr = ~200 */
1030 break;
1031 case bulk_latency:
1032 default:
1033 new_itr = 8000;
1034 break;
1035 }
1036
1037 if (new_itr != q_vector->eitr) {
1038 u32 itr_reg;
509ee935
JB		 1039
1040 /* save the algorithm value here, not the smoothed one */
1041 q_vector->eitr = new_itr;
f494e8fa
AV		 1042 /* do an exponential smoothing */
1043 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1044 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1045 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1046 }
1047
1048 return;
1049}
1050
0befdb3e
JB		 1051static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1052{
1053 struct ixgbe_hw *hw = &adapter->hw;
1054
1055 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1056 (eicr & IXGBE_EICR_GPI_SDP1)) {
1057 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1058 /* write to clear the interrupt */
1059 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1060 }
1061}
cf8280ee 1062
e8e26350
PW		 1063static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1064{
1065 struct ixgbe_hw *hw = &adapter->hw;
1066
1067 if (eicr & IXGBE_EICR_GPI_SDP1) {
1068 /* Clear the interrupt */
1069 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1070 schedule_work(&adapter->multispeed_fiber_task);
1071 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1072 /* Clear the interrupt */
1073 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1074 schedule_work(&adapter->sfp_config_module_task);
1075 } else {
1076 /* Interrupt isn't for us... */
1077 return;
1078 }
1079}
1080
cf8280ee
JB		 1081static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1082{
1083 struct ixgbe_hw *hw = &adapter->hw;
1084
1085 adapter->lsc_int++;
1086 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1087 adapter->link_check_timeout = jiffies;
1088 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1089 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1090 schedule_work(&adapter->watchdog_task);
1091 }
1092}
1093
9a799d71
AK		 1094static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1095{
1096 struct net_device *netdev = data;
1097 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1098 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1099 u32 eicr;
1100
1101 /*
1102 * Workaround for Silicon errata. Use clear-by-write instead
1103 * of clear-by-read. Reading with EICS will return the
1104 * interrupt causes without clearing, which later be done
1105 * with the write to EICR.
1106 */
1107 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1108 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1109
cf8280ee
JB		 1110 if (eicr & IXGBE_EICR_LSC)
1111 ixgbe_check_lsc(adapter);
d4f80882 1112
e8e26350
PW		 1113 if (hw->mac.type == ixgbe_mac_82598EB)
1114 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1115
e8e26350
PW		 1116 if (hw->mac.type == ixgbe_mac_82599EB)
1117 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1118 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1119 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1120
1121 return IRQ_HANDLED;
1122}
1123
1124static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1125{
021230d4
AV		 1126 struct ixgbe_q_vector *q_vector = data;
1127 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1128 struct ixgbe_ring *tx_ring;
021230d4
AV		 1129 int i, r_idx;
1130
1131 if (!q_vector->txr_count)
1132 return IRQ_HANDLED;
1133
1134 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1135 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1136 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1137#ifdef CONFIG_IXGBE_DCA
bd0362dd 1138 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1139 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1140#endif
3a581073
JB		 1141 tx_ring->total_bytes = 0;
1142 tx_ring->total_packets = 0;
1143 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1144 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1145 r_idx + 1);
021230d4 1146 }
9a799d71 1147
9a799d71
AK		 1148 return IRQ_HANDLED;
1149}
1150
021230d4
AV		 1151/**
1152 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1153 * @irq: unused
1154 * @data: pointer to our q_vector struct for this interrupt vector
1155 **/
9a799d71
AK		 1156static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1157{
021230d4
AV		 1158 struct ixgbe_q_vector *q_vector = data;
1159 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1160 struct ixgbe_ring *rx_ring;
021230d4 1161 int r_idx;
30efa5a3 1162 int i;
021230d4
AV		 1163
1164 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1165 for (i = 0; i < q_vector->rxr_count; i++) {
1166 rx_ring = &(adapter->rx_ring[r_idx]);
1167 rx_ring->total_bytes = 0;
1168 rx_ring->total_packets = 0;
1169 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1170 r_idx + 1);
1171 }
1172
021230d4
AV		 1173 if (!q_vector->rxr_count)
1174 return IRQ_HANDLED;
1175
30efa5a3 1176 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1177 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1178 /* disable interrupts on this vector only */
835462fc
NS		 1179 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1180 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1181 else if (rx_ring->v_idx & 0xFFFFFFFF)
1182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1183 else
1184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1185 (rx_ring->v_idx >> 32));
288379f0 1186 napi_schedule(&q_vector->napi);
021230d4
AV		 1187
1188 return IRQ_HANDLED;
1189}
1190
1191static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1192{
1193 ixgbe_msix_clean_rx(irq, data);
1194 ixgbe_msix_clean_tx(irq, data);
9a799d71 1195
9a799d71
AK		 1196 return IRQ_HANDLED;
1197}
1198
835462fc
NS		 1199static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200 u64 qmask)
1201{
1202 u32 mask;
1203
1204 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207 } else {
1208 mask = (qmask & 0xFFFFFFFF);
1209 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210 mask = (qmask >> 32);
1211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212 }
1213 /* skip the flush */
1214}
1215
021230d4
AV		 1216/**
1217 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1218 * @napi: napi struct with our devices info in it
1219 * @budget: amount of work driver is allowed to do this pass, in packets
1220 *
f0848276
JB		 1221 * This function is optimized for cleaning one queue only on a single
1222 * q_vector!!!
021230d4 1223 **/
9a799d71
AK		 1224static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1225{
021230d4 1226 struct ixgbe_q_vector *q_vector =
b4617240 1227 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1228 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1229 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1230 int work_done = 0;
021230d4 1231 long r_idx;
9a799d71 1232
021230d4 1233 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1234 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1235#ifdef CONFIG_IXGBE_DCA
bd0362dd 1236 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1237 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1238#endif
9a799d71 1239
78b6f4ce 1240 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1241
021230d4
AV		 1242 /* If all Rx work done, exit the polling mode */
1243 if (work_done < budget) {
288379f0 1244 napi_complete(napi);
509ee935 1245 if (adapter->itr_setting & 1)
f494e8fa 1246 ixgbe_set_itr_msix(q_vector);
9a799d71 1247 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1248 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1249 }
1250
1251 return work_done;
1252}
1253
f0848276
JB		 1254/**
1255 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1256 * @napi: napi struct with our devices info in it
1257 * @budget: amount of work driver is allowed to do this pass, in packets
1258 *
1259 * This function will clean more than one rx queue associated with a
1260 * q_vector.
1261 **/
1262static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1263{
1264 struct ixgbe_q_vector *q_vector =
1265 container_of(napi, struct ixgbe_q_vector, napi);
1266 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1267 struct ixgbe_ring *rx_ring = NULL;
1268 int work_done = 0, i;
1269 long r_idx;
835462fc 1270 u64 enable_mask = 0;
f0848276
JB		 1271
1272 /* attempt to distribute budget to each queue fairly, but don't allow
1273 * the budget to go below 1 because we'll exit polling */
1274 budget /= (q_vector->rxr_count ?: 1);
1275 budget = max(budget, 1);
1276 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277 for (i = 0; i < q_vector->rxr_count; i++) {
1278 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1279#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1281 ixgbe_update_rx_dca(adapter, rx_ring);
1282#endif
78b6f4ce 1283 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1284 enable_mask |= rx_ring->v_idx;
1285 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1286 r_idx + 1);
1287 }
1288
1289 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1290 rx_ring = &(adapter->rx_ring[r_idx]);
1291 /* If all Rx work done, exit the polling mode */
7f821875 1292 if (work_done < budget) {
288379f0 1293 napi_complete(napi);
509ee935 1294 if (adapter->itr_setting & 1)
f0848276
JB		 1295 ixgbe_set_itr_msix(q_vector);
1296 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1297 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1298 return 0;
1299 }
1300
1301 return work_done;
1302}
021230d4 1303static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1304 int r_idx)
021230d4
AV		 1305{
1306 a->q_vector[v_idx].adapter = a;
1307 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1308 a->q_vector[v_idx].rxr_count++;
1309 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1310}
1311
1312static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1313 int r_idx)
021230d4
AV		 1314{
1315 a->q_vector[v_idx].adapter = a;
1316 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1317 a->q_vector[v_idx].txr_count++;
1318 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1319}
1320
9a799d71 1321/**
021230d4
AV		 1322 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1323 * @adapter: board private structure to initialize
1324 * @vectors: allotted vector count for descriptor rings
9a799d71 1325 *
021230d4
AV		 1326 * This function maps descriptor rings to the queue-specific vectors
1327 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1328 * one vector per ring/queue, but on a constrained vector budget, we
1329 * group the rings as "efficiently" as possible. You would add new
1330 * mapping configurations in here.
9a799d71 1331 **/
021230d4 1332static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1333 int vectors)
021230d4
AV		 1334{
1335 int v_start = 0;
1336 int rxr_idx = 0, txr_idx = 0;
1337 int rxr_remaining = adapter->num_rx_queues;
1338 int txr_remaining = adapter->num_tx_queues;
1339 int i, j;
1340 int rqpv, tqpv;
1341 int err = 0;
1342
1343 /* No mapping required if MSI-X is disabled. */
1344 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1345 goto out;
9a799d71 1346
021230d4
AV		 1347 /*
1348 * The ideal configuration...
1349 * We have enough vectors to map one per queue.
1350 */
1351 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1352 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1353 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1354
021230d4
AV		 1355 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1356 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1357
9a799d71 1358 goto out;
021230d4 1359 }
9a799d71 1360
021230d4
AV		 1361 /*
1362 * If we don't have enough vectors for a 1-to-1
1363 * mapping, we'll have to group them so there are
1364 * multiple queues per vector.
1365 */
1366 /* Re-adjusting *qpv takes care of the remainder. */
1367 for (i = v_start; i < vectors; i++) {
1368 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1369 for (j = 0; j < rqpv; j++) {
1370 map_vector_to_rxq(adapter, i, rxr_idx);
1371 rxr_idx++;
1372 rxr_remaining--;
1373 }
1374 }
1375 for (i = v_start; i < vectors; i++) {
1376 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1377 for (j = 0; j < tqpv; j++) {
1378 map_vector_to_txq(adapter, i, txr_idx);
1379 txr_idx++;
1380 txr_remaining--;
9a799d71 1381 }
9a799d71
AK		 1382 }
1383
021230d4
AV		 1384out:
1385 return err;
1386}
1387
1388/**
1389 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1390 * @adapter: board private structure
1391 *
1392 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1393 * interrupts from the kernel.
1394 **/
1395static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1396{
1397 struct net_device *netdev = adapter->netdev;
1398 irqreturn_t (*handler)(int, void *);
1399 int i, vector, q_vectors, err;
cb13fc20 1400 int ri=0, ti=0;
021230d4
AV		 1401
1402 /* Decrement for Other and TCP Timer vectors */
1403 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1404
1405 /* Map the Tx/Rx rings to the vectors we were allotted. */
1406 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1407 if (err)
1408 goto out;
1409
1410#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1411 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1412 &ixgbe_msix_clean_many)
021230d4
AV		 1413 for (vector = 0; vector < q_vectors; vector++) {
1414 handler = SET_HANDLER(&adapter->q_vector[vector]);
cb13fc20
RO		 1415
1416 if(handler == &ixgbe_msix_clean_rx) {
1417 sprintf(adapter->name[vector], "%s-%s-%d",
1418 netdev->name, "rx", ri++);
1419 }
1420 else if(handler == &ixgbe_msix_clean_tx) {
1421 sprintf(adapter->name[vector], "%s-%s-%d",
1422 netdev->name, "tx", ti++);
1423 }
1424 else
1425 sprintf(adapter->name[vector], "%s-%s-%d",
1426 netdev->name, "TxRx", vector);
1427
021230d4 1428 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1429 handler, 0, adapter->name[vector],
1430 &(adapter->q_vector[vector]));
9a799d71
AK		 1431 if (err) {
1432 DPRINTK(PROBE, ERR,
b4617240
PW		 1433 "request_irq failed for MSIX interrupt "
1434 "Error: %d\n", err);
021230d4 1435 goto free_queue_irqs;
9a799d71 1436 }
9a799d71
AK		 1437 }
1438
021230d4
AV		 1439 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1440 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1441 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1442 if (err) {
1443 DPRINTK(PROBE, ERR,
1444 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1445 goto free_queue_irqs;
9a799d71
AK		 1446 }
1447
9a799d71
AK		 1448 return 0;
1449
021230d4
AV		 1450free_queue_irqs:
1451 for (i = vector - 1; i >= 0; i--)
1452 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1453 &(adapter->q_vector[i]));
021230d4
AV		 1454 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1455 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1456 kfree(adapter->msix_entries);
1457 adapter->msix_entries = NULL;
021230d4 1458out:
9a799d71
AK		 1459 return err;
1460}
1461
f494e8fa
AV		 1462static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1463{
f494e8fa
AV		 1464 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1465 u8 current_itr;
1466 u32 new_itr = q_vector->eitr;
1467 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1468 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1469
30efa5a3 1470 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1471 q_vector->tx_itr,
1472 tx_ring->total_packets,
1473 tx_ring->total_bytes);
30efa5a3 1474 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1475 q_vector->rx_itr,
1476 rx_ring->total_packets,
1477 rx_ring->total_bytes);
f494e8fa 1478
30efa5a3 1479 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1480
1481 switch (current_itr) {
1482 /* counts and packets in update_itr are dependent on these numbers */
1483 case lowest_latency:
1484 new_itr = 100000;
1485 break;
1486 case low_latency:
1487 new_itr = 20000; /* aka hwitr = ~200 */
1488 break;
1489 case bulk_latency:
1490 new_itr = 8000;
1491 break;
1492 default:
1493 break;
1494 }
1495
1496 if (new_itr != q_vector->eitr) {
1497 u32 itr_reg;
509ee935
JB		 1498
1499 /* save the algorithm value here, not the smoothed one */
1500 q_vector->eitr = new_itr;
f494e8fa
AV		 1501 /* do an exponential smoothing */
1502 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1503 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1504 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1505 }
1506
1507 return;
1508}
1509
79aefa45
AD		 1510/**
1511 * ixgbe_irq_enable - Enable default interrupt generation settings
1512 * @adapter: board private structure
1513 **/
1514static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1515{
1516 u32 mask;
835462fc
NS		 1517
1518 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1519 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1520 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1521 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1522 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1523 mask |= IXGBE_EIMS_GPI_SDP1;
1524 mask |= IXGBE_EIMS_GPI_SDP2;
1525 }
1526
79aefa45 1527 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1528 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1529 IXGBE_WRITE_FLUSH(&adapter->hw);
1530}
021230d4 1531
9a799d71 1532/**
021230d4 1533 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1534 * @irq: interrupt number
1535 * @data: pointer to a network interface device structure
9a799d71
AK		 1536 **/
1537static irqreturn_t ixgbe_intr(int irq, void *data)
1538{
1539 struct net_device *netdev = data;
1540 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1541 struct ixgbe_hw *hw = &adapter->hw;
1542 u32 eicr;
1543
54037505
DS		 1544 /*
1545 * Workaround for silicon errata. Mask the interrupts
1546 * before the read of EICR.
1547 */
1548 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1549
021230d4
AV		 1550 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1551 * therefore no explict interrupt disable is necessary */
1552 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1553 if (!eicr) {
1554 /* shared interrupt alert!
1555 * make sure interrupts are enabled because the read will
1556 * have disabled interrupts due to EIAM */
1557 ixgbe_irq_enable(adapter);
9a799d71 1558 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1559 }
9a799d71 1560
cf8280ee
JB		 1561 if (eicr & IXGBE_EICR_LSC)
1562 ixgbe_check_lsc(adapter);
021230d4 1563
e8e26350
PW		 1564 if (hw->mac.type == ixgbe_mac_82599EB)
1565 ixgbe_check_sfp_event(adapter, eicr);
1566
0befdb3e
JB		 1567 ixgbe_check_fan_failure(adapter, eicr);
1568
288379f0 1569 if (napi_schedule_prep(&adapter->q_vector[0].napi)) {
f494e8fa
AV		 1570 adapter->tx_ring[0].total_packets = 0;
1571 adapter->tx_ring[0].total_bytes = 0;
1572 adapter->rx_ring[0].total_packets = 0;
1573 adapter->rx_ring[0].total_bytes = 0;
021230d4 1574 /* would disable interrupts here but EIAM disabled it */
288379f0 1575 __napi_schedule(&adapter->q_vector[0].napi);
9a799d71
AK		 1576 }
1577
1578 return IRQ_HANDLED;
1579}
1580
021230d4
AV		 1581static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1582{
1583 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1584
1585 for (i = 0; i < q_vectors; i++) {
1586 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1587 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1588 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1589 q_vector->rxr_count = 0;
1590 q_vector->txr_count = 0;
1591 }
1592}
1593
9a799d71
AK		 1594/**
1595 * ixgbe_request_irq - initialize interrupts
1596 * @adapter: board private structure
1597 *
1598 * Attempts to configure interrupts using the best available
1599 * capabilities of the hardware and kernel.
1600 **/
021230d4 1601static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1602{
1603 struct net_device *netdev = adapter->netdev;
021230d4 1604 int err;
9a799d71 1605
021230d4
AV		 1606 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1607 err = ixgbe_request_msix_irqs(adapter);
1608 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1609 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1610 netdev->name, netdev);
021230d4
AV		 1611 } else {
1612 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1613 netdev->name, netdev);
9a799d71
AK		 1614 }
1615
9a799d71
AK		 1616 if (err)
1617 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1618
9a799d71
AK		 1619 return err;
1620}
1621
1622static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1623{
1624 struct net_device *netdev = adapter->netdev;
1625
1626 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1627 int i, q_vectors;
9a799d71 1628
021230d4
AV		 1629 q_vectors = adapter->num_msix_vectors;
1630
1631 i = q_vectors - 1;
9a799d71 1632 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1633
021230d4
AV		 1634 i--;
1635 for (; i >= 0; i--) {
1636 free_irq(adapter->msix_entries[i].vector,
b4617240 1637 &(adapter->q_vector[i]));
021230d4
AV		 1638 }
1639
1640 ixgbe_reset_q_vectors(adapter);
1641 } else {
1642 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1643 }
1644}
1645
22d5a71b
JB		 1646/**
1647 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1648 * @adapter: board private structure
1649 **/
1650static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1651{
835462fc
NS		 1652 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1654 } else {
1655 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1657 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1658 }
1659 IXGBE_WRITE_FLUSH(&adapter->hw);
1660 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1661 int i;
1662 for (i = 0; i < adapter->num_msix_vectors; i++)
1663 synchronize_irq(adapter->msix_entries[i].vector);
1664 } else {
1665 synchronize_irq(adapter->pdev->irq);
1666 }
1667}
1668
9a799d71
AK		 1669/**
1670 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1671 *
1672 **/
1673static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1674{
9a799d71
AK		 1675 struct ixgbe_hw *hw = &adapter->hw;
1676
021230d4 1677 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1678 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1679
e8e26350
PW		 1680 ixgbe_set_ivar(adapter, 0, 0, 0);
1681 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1682
1683 map_vector_to_rxq(adapter, 0, 0);
1684 map_vector_to_txq(adapter, 0, 0);
1685
1686 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1687}
1688
1689/**
3a581073 1690 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1691 * @adapter: board private structure
1692 *
1693 * Configure the Tx unit of the MAC after a reset.
1694 **/
1695static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1696{
12207e49 1697 u64 tdba;
9a799d71 1698 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1699 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1700
1701 /* Setup the HW Tx Head and Tail descriptor pointers */
1702 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1703 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1704 j = ring->reg_idx;
1705 tdba = ring->dma;
1706 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1707 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1708 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1709 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1710 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1711 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1712 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1713 adapter->tx_ring[i].head = IXGBE_TDH(j);
1714 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1715 /* Disable Tx Head Writeback RO bit, since this hoses
1716 * bookkeeping if things aren't delivered in order.
1717 */
e01c31a5 1718 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1719 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1720 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1721 }
e8e26350
PW		 1722 if (hw->mac.type == ixgbe_mac_82599EB) {
1723 /* We enable 8 traffic classes, DCB only */
1724 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1725 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1726 IXGBE_MTQC_8TC_8TQ));
1727 }
9a799d71
AK		 1728}
1729
e8e26350 1730#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1731
1732static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1733{
1734 struct ixgbe_ring *rx_ring;
1735 u32 srrctl;
e8e26350 1736 int queue0 = 0;
3be1adfb
AD		 1737 unsigned long mask;
1738
e8e26350
PW		 1739 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1740 queue0 = index;
cc41ac7c 1741 } else {
3be1adfb
AD		 1742 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1743 queue0 = index & mask;
1744 index = index & mask;
cc41ac7c 1745 }
3be1adfb 1746
cc41ac7c
JB		 1747 rx_ring = &adapter->rx_ring[queue0];
1748
1749 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1750
1751 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1752 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1753
1754 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
32344a39
JB		 1755 u16 bufsz = IXGBE_RXBUFFER_2048;
1756 /* grow the amount we can receive on large page machines */
1757 if (bufsz < (PAGE_SIZE / 2))
1758 bufsz = (PAGE_SIZE / 2);
1759 /* cap the bufsz at our largest descriptor size */
1760 bufsz = min((u16)IXGBE_MAX_RXBUFFER, bufsz);
1761
1762 srrctl |= bufsz >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c
JB		 1763 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1764 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1765 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1766 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1767 } else {
1768 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1769
1770 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1771 srrctl |= IXGBE_RXBUFFER_2048 >>
1772 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1773 else
1774 srrctl |= rx_ring->rx_buf_len >>
1775 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1776 }
e8e26350 1777
cc41ac7c
JB		 1778 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1779}
9a799d71 1780
9a799d71 1781/**
3a581073 1782 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1783 * @adapter: board private structure
1784 *
1785 * Configure the Rx unit of the MAC after a reset.
1786 **/
1787static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1788{
1789 u64 rdba;
1790 struct ixgbe_hw *hw = &adapter->hw;
1791 struct net_device *netdev = adapter->netdev;
1792 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1793 int i, j;
9a799d71 1794 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1795 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1796 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1797 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1798 u32 fctrl, hlreg0;
509ee935 1799 u32 reta = 0, mrqc = 0;
cc41ac7c 1800 u32 rdrxctl;
f8212f97 1801 u32 rscctrl;
7c6e0a43 1802 int rx_buf_len;
9a799d71
AK		 1803
1804 /* Decide whether to use packet split mode or not */
762f4c57 1805 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1806
1807 /* Set the RX buffer length according to the mode */
1808 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1809 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1810 if (hw->mac.type == ixgbe_mac_82599EB) {
1811 /* PSRTYPE must be initialized in 82599 */
1812 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1813 IXGBE_PSRTYPE_UDPHDR |
1814 IXGBE_PSRTYPE_IPV4HDR |
1815 IXGBE_PSRTYPE_IPV6HDR;
1816 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1817 }
9a799d71 1818 } else {
f8212f97
AD		 1819 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1820 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1821 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1822 else
7c6e0a43 1823 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1824 }
1825
1826 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1827 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1828 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1829 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1831
1832 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1833 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1834 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1835 else
1836 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1837 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1838
9a799d71
AK		 1839 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1840 /* disable receives while setting up the descriptors */
1841 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1842 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1843
1844 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1845 * the Base and Length of the Rx Descriptor Ring */
1846 for (i = 0; i < adapter->num_rx_queues; i++) {
1847 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1848 j = adapter->rx_ring[i].reg_idx;
284901a9 1849 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1850 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1851 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1852 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1853 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1854 adapter->rx_ring[i].head = IXGBE_RDH(j);
1855 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1856 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c
JB		 1857
1858 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1859 }
1860
e8e26350
PW		 1861 if (hw->mac.type == ixgbe_mac_82598EB) {
1862 /*
1863 * For VMDq support of different descriptor types or
1864 * buffer sizes through the use of multiple SRRCTL
1865 * registers, RDRXCTL.MVMEN must be set to 1
1866 *
1867 * also, the manual doesn't mention it clearly but DCA hints
1868 * will only use queue 0's tags unless this bit is set. Side
1869 * effects of setting this bit are only that SRRCTL must be
1870 * fully programmed [0..15]
1871 */
2a41ff81
JB		 1872 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1873 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1874 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1875 }
177db6ff 1876
e8e26350
PW		 1877 /* Program MRQC for the distribution of queues */
1878 if (hw->mac.type == ixgbe_mac_82599EB) {
1879 int mask = adapter->flags & (
1880 IXGBE_FLAG_RSS_ENABLED
1881 | IXGBE_FLAG_DCB_ENABLED
1882 );
1883
1884 switch (mask) {
1885 case (IXGBE_FLAG_RSS_ENABLED):
1886 mrqc = IXGBE_MRQC_RSSEN;
1887 break;
1888 case (IXGBE_FLAG_DCB_ENABLED):
1889 mrqc = IXGBE_MRQC_RT8TCEN;
1890 break;
1891 default:
1892 break;
1893 }
1894 }
021230d4 1895 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1896 /* Fill out redirection table */
021230d4
AV		 1897 for (i = 0, j = 0; i < 128; i++, j++) {
1898 if (j == adapter->ring_feature[RING_F_RSS].indices)
1899 j = 0;
1900 /* reta = 4-byte sliding window of
1901 * 0x00..(indices-1)(indices-1)00..etc. */
1902 reta = (reta << 8) | (j * 0x11);
1903 if ((i & 3) == 3)
1904 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1905 }
1906
1907 /* Fill out hash function seeds */
1908 for (i = 0; i < 10; i++)
7c6e0a43 1909 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1910
2a41ff81
JB		 1911 if (hw->mac.type == ixgbe_mac_82598EB)
1912 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1913 /* Perform hash on these packet types */
2a41ff81
JB		 1914 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1915 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1916 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1917 | IXGBE_MRQC_RSS_FIELD_IPV6
1918 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1919 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1920 }
2a41ff81 1921 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1922
021230d4
AV		 1923 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1924
1925 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1926 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1927 /* Disable indicating checksum in descriptor, enables
1928 * RSS hash */
9a799d71 1929 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1930 }
021230d4
AV		 1931 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1932 /* Enable IPv4 payload checksum for UDP fragments
1933 * if PCSD is not set */
1934 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1935 }
1936
1937 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1938
1939 if (hw->mac.type == ixgbe_mac_82599EB) {
1940 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1941 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1942 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1943 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1944 }
f8212f97
AD		 1945
1946 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1947 /* Enable 82599 HW-RSC */
1948 for (i = 0; i < adapter->num_rx_queues; i++) {
1949 j = adapter->rx_ring[i].reg_idx;
1950 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1951 rscctrl |= IXGBE_RSCCTL_RSCEN;
1952 /*
1953 * if packet split is enabled we can only support up
1954 * to max frags + 1 descriptors.
1955 */
1956 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
1957#if (MAX_SKB_FRAGS < 3)
1958 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
1959#elif (MAX_SKB_FRAGS < 7)
1960 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
1961#elif (MAX_SKB_FRAGS < 15)
1962 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
1963#else
1964 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1965#endif
1966 else
1967 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
1968 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
1969 }
1970 /* Disable RSC for ACK packets */
1971 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
1972 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
1973 }
9a799d71
AK		 1974}
1975
068c89b0
DS		 1976static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1977{
1978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1979 struct ixgbe_hw *hw = &adapter->hw;
1980
1981 /* add VID to filter table */
1982 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1983}
1984
1985static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1986{
1987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1988 struct ixgbe_hw *hw = &adapter->hw;
1989
1990 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1991 ixgbe_irq_disable(adapter);
1992
1993 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1994
1995 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1996 ixgbe_irq_enable(adapter);
1997
1998 /* remove VID from filter table */
1999 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2000}
2001
9a799d71 2002static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2003 struct vlan_group *grp)
9a799d71
AK		 2004{
2005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2006 u32 ctrl;
e8e26350 2007 int i, j;
9a799d71 2008
d4f80882
AV		 2009 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2010 ixgbe_irq_disable(adapter);
9a799d71
AK		 2011 adapter->vlgrp = grp;
2012
2f90b865
AD		 2013 /*
2014 * For a DCB driver, always enable VLAN tag stripping so we can
2015 * still receive traffic from a DCB-enabled host even if we're
2016 * not in DCB mode.
2017 */
2018 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2019 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2020 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2021 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2022 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2023 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2024 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2025 /* enable VLAN tag insert/strip */
2026 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2027 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2029 for (i = 0; i < adapter->num_rx_queues; i++) {
2030 j = adapter->rx_ring[i].reg_idx;
2031 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2032 ctrl |= IXGBE_RXDCTL_VME;
2033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2034 }
9a799d71 2035 }
e8e26350 2036 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2037
d4f80882
AV		 2038 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2039 ixgbe_irq_enable(adapter);
9a799d71
AK		 2040}
2041
9a799d71
AK		 2042static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2043{
2044 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2045
2046 if (adapter->vlgrp) {
2047 u16 vid;
2048 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2049 if (!vlan_group_get_device(adapter->vlgrp, vid))
2050 continue;
2051 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2052 }
2053 }
2054}
2055
2c5645cf
CL		 2056static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2057{
2058 struct dev_mc_list *mc_ptr;
2059 u8 *addr = *mc_addr_ptr;
2060 *vmdq = 0;
2061
2062 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2063 if (mc_ptr->next)
2064 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2065 else
2066 *mc_addr_ptr = NULL;
2067
2068 return addr;
2069}
2070
9a799d71 2071/**
2c5645cf 2072 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2073 * @netdev: network interface device structure
2074 *
2c5645cf
CL		 2075 * The set_rx_method entry point is called whenever the unicast/multicast
2076 * address list or the network interface flags are updated. This routine is
2077 * responsible for configuring the hardware for proper unicast, multicast and
2078 * promiscuous mode.
9a799d71 2079 **/
2c5645cf 2080static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2081{
2082 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2083 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2084 u32 fctrl, vlnctrl;
2c5645cf
CL		 2085 u8 *addr_list = NULL;
2086 int addr_count = 0;
9a799d71
AK		 2087
2088 /* Check for Promiscuous and All Multicast modes */
2089
2090 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2091 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2092
2093 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2094 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2095 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2096 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2097 } else {
746b9f02
PM		 2098 if (netdev->flags & IFF_ALLMULTI) {
2099 fctrl |= IXGBE_FCTRL_MPE;
2100 fctrl &= ~IXGBE_FCTRL_UPE;
2101 } else {
2102 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2103 }
3d01625a 2104 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2105 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2106 }
2107
2108 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2109 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2110
2c5645cf
CL		 2111 /* reprogram secondary unicast list */
2112 addr_count = netdev->uc_count;
2113 if (addr_count)
2114 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2115 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2116 ixgbe_addr_list_itr);
9a799d71 2117
2c5645cf
CL		 2118 /* reprogram multicast list */
2119 addr_count = netdev->mc_count;
2120 if (addr_count)
2121 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2122 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2123 ixgbe_addr_list_itr);
9a799d71
AK		 2124}
2125
021230d4
AV		 2126static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2127{
2128 int q_idx;
2129 struct ixgbe_q_vector *q_vector;
2130 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2131
2132 /* legacy and MSI only use one vector */
2133 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2134 q_vectors = 1;
2135
2136 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2137 struct napi_struct *napi;
021230d4
AV		 2138 q_vector = &adapter->q_vector[q_idx];
2139 if (!q_vector->rxr_count)
2140 continue;
f0848276
JB		 2141 napi = &q_vector->napi;
2142 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2143 (q_vector->rxr_count > 1))
2144 napi->poll = &ixgbe_clean_rxonly_many;
2145
2146 napi_enable(napi);
021230d4
AV		 2147 }
2148}
2149
2150static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2151{
2152 int q_idx;
2153 struct ixgbe_q_vector *q_vector;
2154 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2155
2156 /* legacy and MSI only use one vector */
2157 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2158 q_vectors = 1;
2159
2160 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2161 q_vector = &adapter->q_vector[q_idx];
2162 if (!q_vector->rxr_count)
2163 continue;
2164 napi_disable(&q_vector->napi);
2165 }
2166}
2167
7a6b6f51 2168#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2169/*
2170 * ixgbe_configure_dcb - Configure DCB hardware
2171 * @adapter: ixgbe adapter struct
2172 *
2173 * This is called by the driver on open to configure the DCB hardware.
2174 * This is also called by the gennetlink interface when reconfiguring
2175 * the DCB state.
2176 */
2177static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2178{
2179 struct ixgbe_hw *hw = &adapter->hw;
2180 u32 txdctl, vlnctrl;
2181 int i, j;
2182
2183 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2184 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2185 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2186
2187 /* reconfigure the hardware */
2188 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2189
2190 for (i = 0; i < adapter->num_tx_queues; i++) {
2191 j = adapter->tx_ring[i].reg_idx;
2192 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2193 /* PThresh workaround for Tx hang with DFP enabled. */
2194 txdctl |= 32;
2195 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2196 }
2197 /* Enable VLAN tag insert/strip */
2198 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2199 if (hw->mac.type == ixgbe_mac_82598EB) {
2200 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2201 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2202 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2203 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2204 vlnctrl |= IXGBE_VLNCTRL_VFE;
2205 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2206 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2207 for (i = 0; i < adapter->num_rx_queues; i++) {
2208 j = adapter->rx_ring[i].reg_idx;
2209 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2210 vlnctrl |= IXGBE_RXDCTL_VME;
2211 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2212 }
2213 }
2f90b865
AD		 2214 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2215}
2216
2217#endif
9a799d71
AK		 2218static void ixgbe_configure(struct ixgbe_adapter *adapter)
2219{
2220 struct net_device *netdev = adapter->netdev;
2221 int i;
2222
2c5645cf 2223 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2224
2225 ixgbe_restore_vlan(adapter);
7a6b6f51 2226#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2227 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2228 netif_set_gso_max_size(netdev, 32768);
2229 ixgbe_configure_dcb(adapter);
2230 } else {
2231 netif_set_gso_max_size(netdev, 65536);
2232 }
2233#else
2234 netif_set_gso_max_size(netdev, 65536);
2235#endif
9a799d71
AK		 2236
2237 ixgbe_configure_tx(adapter);
2238 ixgbe_configure_rx(adapter);
2239 for (i = 0; i < adapter->num_rx_queues; i++)
2240 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2241 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2242}
2243
e8e26350
PW		 2244static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2245{
2246 switch (hw->phy.type) {
2247 case ixgbe_phy_sfp_avago:
2248 case ixgbe_phy_sfp_ftl:
2249 case ixgbe_phy_sfp_intel:
2250 case ixgbe_phy_sfp_unknown:
2251 case ixgbe_phy_tw_tyco:
2252 case ixgbe_phy_tw_unknown:
2253 return true;
2254 default:
2255 return false;
2256 }
2257}
2258
0ecc061d 2259/**
e8e26350
PW		 2260 * ixgbe_sfp_link_config - set up SFP+ link
2261 * @adapter: pointer to private adapter struct
2262 **/
2263static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2264{
2265 struct ixgbe_hw *hw = &adapter->hw;
2266
2267 if (hw->phy.multispeed_fiber) {
2268 /*
2269 * In multispeed fiber setups, the device may not have
2270 * had a physical connection when the driver loaded.
2271 * If that's the case, the initial link configuration
2272 * couldn't get the MAC into 10G or 1G mode, so we'll
2273 * never have a link status change interrupt fire.
2274 * We need to try and force an autonegotiation
2275 * session, then bring up link.
2276 */
2277 hw->mac.ops.setup_sfp(hw);
2278 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2279 schedule_work(&adapter->multispeed_fiber_task);
2280 } else {
2281 /*
2282 * Direct Attach Cu and non-multispeed fiber modules
2283 * still need to be configured properly prior to
2284 * attempting link.
2285 */
2286 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2287 schedule_work(&adapter->sfp_config_module_task);
2288 }
2289}
2290
2291/**
2292 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2293 * @hw: pointer to private hardware struct
2294 *
2295 * Returns 0 on success, negative on failure
2296 **/
e8e26350 2297static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2298{
2299 u32 autoneg;
2300 bool link_up = false;
2301 u32 ret = IXGBE_ERR_LINK_SETUP;
2302
2303 if (hw->mac.ops.check_link)
2304 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2305
2306 if (ret)
2307 goto link_cfg_out;
2308
2309 if (hw->mac.ops.get_link_capabilities)
2310 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2311 &hw->mac.autoneg);
2312 if (ret)
2313 goto link_cfg_out;
2314
2315 if (hw->mac.ops.setup_link_speed)
2316 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2317link_cfg_out:
2318 return ret;
2319}
2320
e8e26350
PW		 2321#define IXGBE_MAX_RX_DESC_POLL 10
2322static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2323 int rxr)
2324{
2325 int j = adapter->rx_ring[rxr].reg_idx;
2326 int k;
2327
2328 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2329 if (IXGBE_READ_REG(&adapter->hw,
2330 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2331 break;
2332 else
2333 msleep(1);
2334 }
2335 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2336 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2337 "not set within the polling period\n", rxr);
2338 }
2339 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2340 (adapter->rx_ring[rxr].count - 1));
2341}
2342
9a799d71
AK		 2343static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2344{
2345 struct net_device *netdev = adapter->netdev;
9a799d71 2346 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2347 int i, j = 0;
e8e26350 2348 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2349 int err;
9a799d71 2350 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2351 u32 txdctl, rxdctl, mhadd;
e8e26350 2352 u32 dmatxctl;
021230d4 2353 u32 gpie;
9a799d71 2354
5eba3699
AV		 2355 ixgbe_get_hw_control(adapter);
2356
021230d4
AV		 2357 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2358 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2359 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2360 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2361 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2362 } else {
2363 /* MSI only */
021230d4 2364 gpie = 0;
9a799d71 2365 }
021230d4
AV		 2366 /* XXX: to interrupt immediately for EICS writes, enable this */
2367 /* gpie |= IXGBE_GPIE_EIMEN; */
2368 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2369 }
2370
021230d4
AV		 2371 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2372 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2373 * specifically only auto mask tx and rx interrupts */
2374 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2375 }
9a799d71 2376
0befdb3e
JB		 2377 /* Enable fan failure interrupt if media type is copper */
2378 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2379 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2380 gpie |= IXGBE_SDP1_GPIEN;
2381 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2382 }
2383
e8e26350
PW		 2384 if (hw->mac.type == ixgbe_mac_82599EB) {
2385 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2386 gpie |= IXGBE_SDP1_GPIEN;
2387 gpie |= IXGBE_SDP2_GPIEN;
2388 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2389 }
2390
021230d4 2391 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2392 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2393 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2394 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2395
2396 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2397 }
2398
2399 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2400 j = adapter->tx_ring[i].reg_idx;
2401 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2402 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2403 txdctl |= (8 << 16);
e8e26350
PW		 2404 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2405 }
2406
2407 if (hw->mac.type == ixgbe_mac_82599EB) {
2408 /* DMATXCTL.EN must be set after all Tx queue config is done */
2409 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2410 dmatxctl |= IXGBE_DMATXCTL_TE;
2411 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2412 }
2413 for (i = 0; i < adapter->num_tx_queues; i++) {
2414 j = adapter->tx_ring[i].reg_idx;
2415 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2416 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2417 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2418 }
2419
e8e26350 2420 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2421 j = adapter->rx_ring[i].reg_idx;
2422 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2423 /* enable PTHRESH=32 descriptors (half the internal cache)
2424 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2425 * this also removes a pesky rx_no_buffer_count increment */
2426 rxdctl |= 0x0020;
9a799d71 2427 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2428 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2429 if (hw->mac.type == ixgbe_mac_82599EB)
2430 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2431 }
2432 /* enable all receives */
2433 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2434 if (hw->mac.type == ixgbe_mac_82598EB)
2435 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2436 else
2437 rxdctl |= IXGBE_RXCTRL_RXEN;
2438 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2439
2440 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2441 ixgbe_configure_msix(adapter);
2442 else
2443 ixgbe_configure_msi_and_legacy(adapter);
2444
2445 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2446 ixgbe_napi_enable_all(adapter);
2447
2448 /* clear any pending interrupts, may auto mask */
2449 IXGBE_READ_REG(hw, IXGBE_EICR);
2450
9a799d71
AK		 2451 ixgbe_irq_enable(adapter);
2452
e8e26350
PW		 2453 /*
2454 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2455 * arrived before interrupts were enabled. We need to kick off
2456 * the SFP+ module setup first, then try to bring up link.
2457 * If we're not hot-pluggable SFP+, we just need to configure link
2458 * and bring it up.
2459 */
2460 err = hw->phy.ops.identify(hw);
2461 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2462 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2463 ixgbe_down(adapter);
2464 return err;
2465 }
2466
2467 if (ixgbe_is_sfp(hw)) {
2468 ixgbe_sfp_link_config(adapter);
2469 } else {
2470 err = ixgbe_non_sfp_link_config(hw);
2471 if (err)
2472 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2473 }
0ecc061d 2474
1da100bb
PWJ		 2475 /* enable transmits */
2476 netif_tx_start_all_queues(netdev);
2477
9a799d71
AK		 2478 /* bring the link up in the watchdog, this could race with our first
2479 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2480 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2481 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2482 mod_timer(&adapter->watchdog_timer, jiffies);
2483 return 0;
2484}
2485
d4f80882
AV		 2486void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2487{
2488 WARN_ON(in_interrupt());
2489 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2490 msleep(1);
2491 ixgbe_down(adapter);
2492 ixgbe_up(adapter);
2493 clear_bit(__IXGBE_RESETTING, &adapter->state);
2494}
2495
9a799d71
AK		 2496int ixgbe_up(struct ixgbe_adapter *adapter)
2497{
2498 /* hardware has been reset, we need to reload some things */
2499 ixgbe_configure(adapter);
2500
4dd64df8
JB		 2501 ixgbe_napi_add_all(adapter);
2502
9a799d71
AK		 2503 return ixgbe_up_complete(adapter);
2504}
2505
2506void ixgbe_reset(struct ixgbe_adapter *adapter)
2507{
c44ade9e
JB		 2508 struct ixgbe_hw *hw = &adapter->hw;
2509 if (hw->mac.ops.init_hw(hw))
2510 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2511
2512 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2513 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2514
2515}
2516
9a799d71
AK		 2517/**
2518 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2519 * @adapter: board private structure
2520 * @rx_ring: ring to free buffers from
2521 **/
2522static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2523 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2524{
2525 struct pci_dev *pdev = adapter->pdev;
2526 unsigned long size;
2527 unsigned int i;
2528
2529 /* Free all the Rx ring sk_buffs */
2530
2531 for (i = 0; i < rx_ring->count; i++) {
2532 struct ixgbe_rx_buffer *rx_buffer_info;
2533
2534 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2535 if (rx_buffer_info->dma) {
2536 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2537 rx_ring->rx_buf_len,
2538 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2539 rx_buffer_info->dma = 0;
2540 }
2541 if (rx_buffer_info->skb) {
f8212f97 2542 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2543 rx_buffer_info->skb = NULL;
f8212f97
AD		 2544 do {
2545 struct sk_buff *this = skb;
2546 skb = skb->prev;
2547 dev_kfree_skb(this);
2548 } while (skb);
9a799d71
AK		 2549 }
2550 if (!rx_buffer_info->page)
2551 continue;
762f4c57
JB		 2552 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2553 PCI_DMA_FROMDEVICE);
9a799d71 2554 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2555 put_page(rx_buffer_info->page);
2556 rx_buffer_info->page = NULL;
762f4c57 2557 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2558 }
2559
2560 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2561 memset(rx_ring->rx_buffer_info, 0, size);
2562
2563 /* Zero out the descriptor ring */
2564 memset(rx_ring->desc, 0, rx_ring->size);
2565
2566 rx_ring->next_to_clean = 0;
2567 rx_ring->next_to_use = 0;
2568
9891ca7c
JB		 2569 if (rx_ring->head)
2570 writel(0, adapter->hw.hw_addr + rx_ring->head);
2571 if (rx_ring->tail)
2572 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2573}
2574
2575/**
2576 * ixgbe_clean_tx_ring - Free Tx Buffers
2577 * @adapter: board private structure
2578 * @tx_ring: ring to be cleaned
2579 **/
2580static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2581 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2582{
2583 struct ixgbe_tx_buffer *tx_buffer_info;
2584 unsigned long size;
2585 unsigned int i;
2586
2587 /* Free all the Tx ring sk_buffs */
2588
2589 for (i = 0; i < tx_ring->count; i++) {
2590 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2591 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2592 }
2593
2594 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2595 memset(tx_ring->tx_buffer_info, 0, size);
2596
2597 /* Zero out the descriptor ring */
2598 memset(tx_ring->desc, 0, tx_ring->size);
2599
2600 tx_ring->next_to_use = 0;
2601 tx_ring->next_to_clean = 0;
2602
9891ca7c
JB		 2603 if (tx_ring->head)
2604 writel(0, adapter->hw.hw_addr + tx_ring->head);
2605 if (tx_ring->tail)
2606 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2607}
2608
2609/**
021230d4 2610 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2611 * @adapter: board private structure
2612 **/
021230d4 2613static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2614{
2615 int i;
2616
021230d4
AV		 2617 for (i = 0; i < adapter->num_rx_queues; i++)
2618 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2619}
2620
2621/**
021230d4 2622 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2623 * @adapter: board private structure
2624 **/
021230d4 2625static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2626{
2627 int i;
2628
021230d4
AV		 2629 for (i = 0; i < adapter->num_tx_queues; i++)
2630 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2631}
2632
2633void ixgbe_down(struct ixgbe_adapter *adapter)
2634{
2635 struct net_device *netdev = adapter->netdev;
7f821875 2636 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2637 u32 rxctrl;
7f821875
JB		 2638 u32 txdctl;
2639 int i, j;
9a799d71
AK		 2640
2641 /* signal that we are down to the interrupt handler */
2642 set_bit(__IXGBE_DOWN, &adapter->state);
2643
2644 /* disable receives */
7f821875
JB		 2645 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2646 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2647
2648 netif_tx_disable(netdev);
2649
7f821875 2650 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2651 msleep(10);
2652
7f821875
JB		 2653 netif_tx_stop_all_queues(netdev);
2654
9a799d71
AK		 2655 ixgbe_irq_disable(adapter);
2656
021230d4 2657 ixgbe_napi_disable_all(adapter);
7f821875 2658
9a799d71 2659 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2660 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2661
7f821875
JB		 2662 /* disable transmits in the hardware now that interrupts are off */
2663 for (i = 0; i < adapter->num_tx_queues; i++) {
2664 j = adapter->tx_ring[i].reg_idx;
2665 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2666 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2667 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2668 }
88512539
PW		 2669 /* Disable the Tx DMA engine on 82599 */
2670 if (hw->mac.type == ixgbe_mac_82599EB)
2671 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2672 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2673 ~IXGBE_DMATXCTL_TE));
7f821875 2674
9a799d71 2675 netif_carrier_off(netdev);
9a799d71 2676
5dd2d332 2677#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2678 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2679 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2680 dca_remove_requester(&adapter->pdev->dev);
2681 }
2682
2683#endif
6f4a0e45
PL		 2684 if (!pci_channel_offline(adapter->pdev))
2685 ixgbe_reset(adapter);
9a799d71
AK		 2686 ixgbe_clean_all_tx_rings(adapter);
2687 ixgbe_clean_all_rx_rings(adapter);
2688
5dd2d332 2689#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2690 /* since we reset the hardware DCA settings were cleared */
2691 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2692 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2693 /* always use CB2 mode, difference is masked
2694 * in the CB driver */
b4617240 2695 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2696 ixgbe_setup_dca(adapter);
2697 }
2698#endif
9a799d71
AK		 2699}
2700
9a799d71 2701/**
021230d4
AV		 2702 * ixgbe_poll - NAPI Rx polling callback
2703 * @napi: structure for representing this polling device
2704 * @budget: how many packets driver is allowed to clean
2705 *
2706 * This function is used for legacy and MSI, NAPI mode
9a799d71 2707 **/
021230d4 2708static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2709{
9a1a69ad
JB		 2710 struct ixgbe_q_vector *q_vector =
2711 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2712 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2713 int tx_clean_complete, work_done = 0;
9a799d71 2714
5dd2d332 2715#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2716 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2717 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2718 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2719 }
2720#endif
2721
9a1a69ad 2722 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2723 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2724
9a1a69ad 2725 if (!tx_clean_complete)
d2c7ddd6
DM		 2726 work_done = budget;
2727
53e52c72
DM		 2728 /* If budget not fully consumed, exit the polling mode */
2729 if (work_done < budget) {
288379f0 2730 napi_complete(napi);
509ee935 2731 if (adapter->itr_setting & 1)
f494e8fa 2732 ixgbe_set_itr(adapter);
d4f80882 2733 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2734 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2735 }
9a799d71
AK		 2736 return work_done;
2737}
2738
2739/**
2740 * ixgbe_tx_timeout - Respond to a Tx Hang
2741 * @netdev: network interface device structure
2742 **/
2743static void ixgbe_tx_timeout(struct net_device *netdev)
2744{
2745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2746
2747 /* Do the reset outside of interrupt context */
2748 schedule_work(&adapter->reset_task);
2749}
2750
2751static void ixgbe_reset_task(struct work_struct *work)
2752{
2753 struct ixgbe_adapter *adapter;
2754 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2755
2f90b865
AD		 2756 /* If we're already down or resetting, just bail */
2757 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2758 test_bit(__IXGBE_RESETTING, &adapter->state))
2759 return;
2760
9a799d71
AK		 2761 adapter->tx_timeout_count++;
2762
d4f80882 2763 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2764}
2765
bc97114d
PWJ		 2766#ifdef CONFIG_IXGBE_DCB
2767static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2768{
bc97114d 2769 bool ret = false;
b9804972 2770
bc97114d
PWJ		 2771 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2772 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2773 adapter->num_rx_queues =
2774 adapter->ring_feature[RING_F_DCB].indices;
2775 adapter->num_tx_queues =
2776 adapter->ring_feature[RING_F_DCB].indices;
2777 ret = true;
2778 } else {
bc97114d
PWJ		 2779 ret = false;
2780 }
2f90b865 2781
bc97114d
PWJ		 2782 return ret;
2783}
2784#endif
2785
4df10466
JB		 2786/**
2787 * ixgbe_set_rss_queues: Allocate queues for RSS
2788 * @adapter: board private structure to initialize
2789 *
2790 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2791 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2792 *
2793 **/
bc97114d
PWJ		 2794static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2795{
2796 bool ret = false;
2797
2798 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2799 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2800 adapter->num_rx_queues =
2801 adapter->ring_feature[RING_F_RSS].indices;
2802 adapter->num_tx_queues =
2803 adapter->ring_feature[RING_F_RSS].indices;
2804 ret = true;
2805 } else {
bc97114d 2806 ret = false;
b9804972
JB		 2807 }
2808
bc97114d
PWJ		 2809 return ret;
2810}
2811
4df10466
JB		 2812/*
2813 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2814 * @adapter: board private structure to initialize
2815 *
2816 * This is the top level queue allocation routine. The order here is very
2817 * important, starting with the "most" number of features turned on at once,
2818 * and ending with the smallest set of features. This way large combinations
2819 * can be allocated if they're turned on, and smaller combinations are the
2820 * fallthrough conditions.
2821 *
2822 **/
bc97114d
PWJ		 2823static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2824{
bc97114d
PWJ		 2825#ifdef CONFIG_IXGBE_DCB
2826 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2827 goto done;
bc97114d
PWJ		 2828
2829#endif
2830 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2831 goto done;
2832
2833 /* fallback to base case */
2834 adapter->num_rx_queues = 1;
2835 adapter->num_tx_queues = 1;
2836
2837done:
2838 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2839 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2840}
2841
021230d4 2842static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2843 int vectors)
021230d4
AV		 2844{
2845 int err, vector_threshold;
2846
2847 /* We'll want at least 3 (vector_threshold):
2848 * 1) TxQ[0] Cleanup
2849 * 2) RxQ[0] Cleanup
2850 * 3) Other (Link Status Change, etc.)
2851 * 4) TCP Timer (optional)
2852 */
2853 vector_threshold = MIN_MSIX_COUNT;
2854
2855 /* The more we get, the more we will assign to Tx/Rx Cleanup
2856 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2857 * Right now, we simply care about how many we'll get; we'll
2858 * set them up later while requesting irq's.
2859 */
2860 while (vectors >= vector_threshold) {
2861 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2862 vectors);
021230d4
AV		 2863 if (!err) /* Success in acquiring all requested vectors. */
2864 break;
2865 else if (err < 0)
2866 vectors = 0; /* Nasty failure, quit now */
2867 else /* err == number of vectors we should try again with */
2868 vectors = err;
2869 }
2870
2871 if (vectors < vector_threshold) {
2872 /* Can't allocate enough MSI-X interrupts? Oh well.
2873 * This just means we'll go with either a single MSI
2874 * vector or fall back to legacy interrupts.
2875 */
2876 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2877 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2878 kfree(adapter->msix_entries);
2879 adapter->msix_entries = NULL;
2f90b865 2880 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2881 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2882 ixgbe_set_num_queues(adapter);
021230d4
AV		 2883 } else {
2884 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 2885 /*
2886 * Adjust for only the vectors we'll use, which is minimum
2887 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
2888 * vectors we were allocated.
2889 */
2890 adapter->num_msix_vectors = min(vectors,
2891 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 2892 }
2893}
2894
021230d4 2895/**
bc97114d 2896 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 2897 * @adapter: board private structure to initialize
2898 *
bc97114d
PWJ		 2899 * Cache the descriptor ring offsets for RSS to the assigned rings.
2900 *
021230d4 2901 **/
bc97114d 2902static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 2903{
bc97114d
PWJ		 2904 int i;
2905 bool ret = false;
2906
2907 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2908 for (i = 0; i < adapter->num_rx_queues; i++)
2909 adapter->rx_ring[i].reg_idx = i;
2910 for (i = 0; i < adapter->num_tx_queues; i++)
2911 adapter->tx_ring[i].reg_idx = i;
2912 ret = true;
2913 } else {
2914 ret = false;
2915 }
2916
2917 return ret;
2918}
2919
2920#ifdef CONFIG_IXGBE_DCB
2921/**
2922 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
2923 * @adapter: board private structure to initialize
2924 *
2925 * Cache the descriptor ring offsets for DCB to the assigned rings.
2926 *
2927 **/
2928static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
2929{
2930 int i;
2931 bool ret = false;
2932 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2933
2934 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2935 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 2936 /* the number of queues is assumed to be symmetric */
2937 for (i = 0; i < dcb_i; i++) {
2938 adapter->rx_ring[i].reg_idx = i << 3;
2939 adapter->tx_ring[i].reg_idx = i << 2;
2940 }
bc97114d 2941 ret = true;
e8e26350 2942 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 2943 if (dcb_i == 8) {
2944 /*
2945 * Tx TC0 starts at: descriptor queue 0
2946 * Tx TC1 starts at: descriptor queue 32
2947 * Tx TC2 starts at: descriptor queue 64
2948 * Tx TC3 starts at: descriptor queue 80
2949 * Tx TC4 starts at: descriptor queue 96
2950 * Tx TC5 starts at: descriptor queue 104
2951 * Tx TC6 starts at: descriptor queue 112
2952 * Tx TC7 starts at: descriptor queue 120
2953 *
2954 * Rx TC0-TC7 are offset by 16 queues each
2955 */
2956 for (i = 0; i < 3; i++) {
2957 adapter->tx_ring[i].reg_idx = i << 5;
2958 adapter->rx_ring[i].reg_idx = i << 4;
2959 }
2960 for ( ; i < 5; i++) {
2961 adapter->tx_ring[i].reg_idx =
2962 ((i + 2) << 4);
2963 adapter->rx_ring[i].reg_idx = i << 4;
2964 }
2965 for ( ; i < dcb_i; i++) {
2966 adapter->tx_ring[i].reg_idx =
2967 ((i + 8) << 3);
2968 adapter->rx_ring[i].reg_idx = i << 4;
2969 }
2970
2971 ret = true;
2972 } else if (dcb_i == 4) {
2973 /*
2974 * Tx TC0 starts at: descriptor queue 0
2975 * Tx TC1 starts at: descriptor queue 64
2976 * Tx TC2 starts at: descriptor queue 96
2977 * Tx TC3 starts at: descriptor queue 112
2978 *
2979 * Rx TC0-TC3 are offset by 32 queues each
2980 */
2981 adapter->tx_ring[0].reg_idx = 0;
2982 adapter->tx_ring[1].reg_idx = 64;
2983 adapter->tx_ring[2].reg_idx = 96;
2984 adapter->tx_ring[3].reg_idx = 112;
2985 for (i = 0 ; i < dcb_i; i++)
2986 adapter->rx_ring[i].reg_idx = i << 5;
2987
2988 ret = true;
2989 } else {
2990 ret = false;
e8e26350 2991 }
bc97114d
PWJ		 2992 } else {
2993 ret = false;
021230d4 2994 }
bc97114d
PWJ		 2995 } else {
2996 ret = false;
021230d4 2997 }
bc97114d
PWJ		 2998
2999 return ret;
3000}
3001#endif
3002
3003/**
3004 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3005 * @adapter: board private structure to initialize
3006 *
3007 * Once we know the feature-set enabled for the device, we'll cache
3008 * the register offset the descriptor ring is assigned to.
3009 *
3010 * Note, the order the various feature calls is important. It must start with
3011 * the "most" features enabled at the same time, then trickle down to the
3012 * least amount of features turned on at once.
3013 **/
3014static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3015{
3016 /* start with default case */
3017 adapter->rx_ring[0].reg_idx = 0;
3018 adapter->tx_ring[0].reg_idx = 0;
3019
3020#ifdef CONFIG_IXGBE_DCB
3021 if (ixgbe_cache_ring_dcb(adapter))
3022 return;
3023
3024#endif
3025 if (ixgbe_cache_ring_rss(adapter))
3026 return;
021230d4
AV		 3027}
3028
9a799d71
AK		 3029/**
3030 * ixgbe_alloc_queues - Allocate memory for all rings
3031 * @adapter: board private structure to initialize
3032 *
3033 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3034 * number of queues at compile-time. The polling_netdev array is
3035 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3036 **/
2f90b865 3037static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3038{
3039 int i;
3040
3041 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3042 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3043 if (!adapter->tx_ring)
021230d4 3044 goto err_tx_ring_allocation;
9a799d71
AK		 3045
3046 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3047 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3048 if (!adapter->rx_ring)
3049 goto err_rx_ring_allocation;
9a799d71 3050
021230d4 3051 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3052 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3053 adapter->tx_ring[i].queue_index = i;
3054 }
b9804972 3055
9a799d71 3056 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3057 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3058 adapter->rx_ring[i].queue_index = i;
3059 }
3060
3061 ixgbe_cache_ring_register(adapter);
3062
3063 return 0;
3064
3065err_rx_ring_allocation:
3066 kfree(adapter->tx_ring);
3067err_tx_ring_allocation:
3068 return -ENOMEM;
3069}
3070
3071/**
3072 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3073 * @adapter: board private structure to initialize
3074 *
3075 * Attempt to configure the interrupts using the best available
3076 * capabilities of the hardware and the kernel.
3077 **/
feea6a57 3078static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3079{
8be0e467 3080 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3081 int err = 0;
3082 int vector, v_budget;
3083
3084 /*
3085 * It's easy to be greedy for MSI-X vectors, but it really
3086 * doesn't do us much good if we have a lot more vectors
3087 * than CPU's. So let's be conservative and only ask for
3088 * (roughly) twice the number of vectors as there are CPU's.
3089 */
3090 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3091 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3092
3093 /*
3094 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3095 * hw.mac->max_msix_vectors vectors. With features
3096 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3097 * descriptor queues supported by our device. Thus, we cap it off in
3098 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3099 */
8be0e467 3100 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3101
3102 /* A failure in MSI-X entry allocation isn't fatal, but it does
3103 * mean we disable MSI-X capabilities of the adapter. */
3104 adapter->msix_entries = kcalloc(v_budget,
b4617240 3105 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 3106 if (!adapter->msix_entries) {
2f90b865 3107 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 3108 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3109 ixgbe_set_num_queues(adapter);
3110 kfree(adapter->tx_ring);
3111 kfree(adapter->rx_ring);
3112 err = ixgbe_alloc_queues(adapter);
3113 if (err) {
3114 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 3115 "for queues\n");
021230d4
AV		 3116 goto out;
3117 }
3118
3119 goto try_msi;
3120 }
3121
3122 for (vector = 0; vector < v_budget; vector++)
3123 adapter->msix_entries[vector].entry = vector;
3124
3125 ixgbe_acquire_msix_vectors(adapter, v_budget);
3126
3127 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3128 goto out;
3129
3130try_msi:
3131 err = pci_enable_msi(adapter->pdev);
3132 if (!err) {
3133 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3134 } else {
3135 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3136 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3137 /* reset err */
3138 err = 0;
3139 }
3140
3141out:
021230d4
AV		 3142 return err;
3143}
3144
2f90b865 3145void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3146{
3147 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3148 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3149 pci_disable_msix(adapter->pdev);
3150 kfree(adapter->msix_entries);
3151 adapter->msix_entries = NULL;
3152 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3153 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3154 pci_disable_msi(adapter->pdev);
3155 }
3156 return;
3157}
3158
3159/**
3160 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3161 * @adapter: board private structure to initialize
3162 *
3163 * We determine which interrupt scheme to use based on...
3164 * - Kernel support (MSI, MSI-X)
3165 * - which can be user-defined (via MODULE_PARAM)
3166 * - Hardware queue count (num_*_queues)
3167 * - defined by miscellaneous hardware support/features (RSS, etc.)
3168 **/
2f90b865 3169int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3170{
3171 int err;
3172
3173 /* Number of supported queues */
3174 ixgbe_set_num_queues(adapter);
3175
3176 err = ixgbe_alloc_queues(adapter);
3177 if (err) {
3178 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3179 goto err_alloc_queues;
3180 }
3181
3182 err = ixgbe_set_interrupt_capability(adapter);
3183 if (err) {
3184 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3185 goto err_set_interrupt;
9a799d71
AK		 3186 }
3187
021230d4 3188 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3189 "Tx Queue count = %u\n",
3190 (adapter->num_rx_queues > 1) ? "Enabled" :
3191 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3192
3193 set_bit(__IXGBE_DOWN, &adapter->state);
3194
9a799d71 3195 return 0;
021230d4
AV		 3196
3197err_set_interrupt:
3198 kfree(adapter->tx_ring);
3199 kfree(adapter->rx_ring);
3200err_alloc_queues:
3201 return err;
9a799d71
AK		 3202}
3203
c4900be0
DS		 3204/**
3205 * ixgbe_sfp_timer - worker thread to find a missing module
3206 * @data: pointer to our adapter struct
3207 **/
3208static void ixgbe_sfp_timer(unsigned long data)
3209{
3210 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3211
4df10466
JB		 3212 /*
3213 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3214 * delays that sfp+ detection requires
3215 */
3216 schedule_work(&adapter->sfp_task);
3217}
3218
3219/**
3220 * ixgbe_sfp_task - worker thread to find a missing module
3221 * @work: pointer to work_struct containing our data
3222 **/
3223static void ixgbe_sfp_task(struct work_struct *work)
3224{
3225 struct ixgbe_adapter *adapter = container_of(work,
3226 struct ixgbe_adapter,
3227 sfp_task);
3228 struct ixgbe_hw *hw = &adapter->hw;
3229
3230 if ((hw->phy.type == ixgbe_phy_nl) &&
3231 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3232 s32 ret = hw->phy.ops.identify_sfp(hw);
3233 if (ret)
3234 goto reschedule;
3235 ret = hw->phy.ops.reset(hw);
3236 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3237 DPRINTK(PROBE, ERR, "failed to initialize because an "
3238 "unsupported SFP+ module type was detected.\n"
3239 "Reload the driver after installing a "
3240 "supported module.\n");
3241 unregister_netdev(adapter->netdev);
3242 } else {
3243 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3244 hw->phy.sfp_type);
3245 }
3246 /* don't need this routine any more */
3247 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3248 }
3249 return;
3250reschedule:
3251 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3252 mod_timer(&adapter->sfp_timer,
3253 round_jiffies(jiffies + (2 * HZ)));
3254}
3255
9a799d71
AK		 3256/**
3257 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3258 * @adapter: board private structure to initialize
3259 *
3260 * ixgbe_sw_init initializes the Adapter private data structure.
3261 * Fields are initialized based on PCI device information and
3262 * OS network device settings (MTU size).
3263 **/
3264static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3265{
3266 struct ixgbe_hw *hw = &adapter->hw;
3267 struct pci_dev *pdev = adapter->pdev;
021230d4 3268 unsigned int rss;
7a6b6f51 3269#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3270 int j;
3271 struct tc_configuration *tc;
3272#endif
021230d4 3273
c44ade9e
JB		 3274 /* PCI config space info */
3275
3276 hw->vendor_id = pdev->vendor;
3277 hw->device_id = pdev->device;
3278 hw->revision_id = pdev->revision;
3279 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3280 hw->subsystem_device_id = pdev->subsystem_device;
3281
021230d4
AV		 3282 /* Set capability flags */
3283 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3284 adapter->ring_feature[RING_F_RSS].indices = rss;
3285 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3286 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
e8e26350
PW		 3287 if (hw->mac.type == ixgbe_mac_82598EB)
3288 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
f8212f97 3289 else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3290 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3291 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3292 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
3293 }
2f90b865 3294
7a6b6f51 3295#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3296 /* Configure DCB traffic classes */
3297 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3298 tc = &adapter->dcb_cfg.tc_config[j];
3299 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3300 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3301 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3302 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3303 tc->dcb_pfc = pfc_disabled;
3304 }
3305 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3306 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3307 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3308 adapter->dcb_cfg.round_robin_enable = false;
3309 adapter->dcb_set_bitmap = 0x00;
3310 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3311 adapter->ring_feature[RING_F_DCB].indices);
3312
3313#endif
9a799d71
AK		 3314
3315 /* default flow control settings */
cd7664f6 3316 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3317 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
2b9ade93
JB		 3318 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3319 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3320 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3321 hw->fc.send_xon = true;
71fd570b 3322 hw->fc.disable_fc_autoneg = false;
9a799d71 3323
30efa5a3
JB		 3324 /* enable itr by default in dynamic mode */
3325 adapter->itr_setting = 1;
3326 adapter->eitr_param = 20000;
3327
3328 /* set defaults for eitr in MegaBytes */
3329 adapter->eitr_low = 10;
3330 adapter->eitr_high = 20;
3331
3332 /* set default ring sizes */
3333 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3334 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3335
9a799d71 3336 /* initialize eeprom parameters */
c44ade9e 3337 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3338 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3339 return -EIO;
3340 }
3341
021230d4 3342 /* enable rx csum by default */
9a799d71
AK		 3343 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3344
9a799d71
AK		 3345 set_bit(__IXGBE_DOWN, &adapter->state);
3346
3347 return 0;
3348}
3349
3350/**
3351 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3352 * @adapter: board private structure
3a581073 3353 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3354 *
3355 * Return 0 on success, negative on failure
3356 **/
3357int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3358 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3359{
3360 struct pci_dev *pdev = adapter->pdev;
3361 int size;
3362
3a581073
JB		 3363 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3364 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3365 if (!tx_ring->tx_buffer_info)
3366 goto err;
3a581073 3367 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3368
3369 /* round up to nearest 4K */
12207e49 3370 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3371 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3372
3a581073
JB		 3373 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3374 &tx_ring->dma);
e01c31a5
JB		 3375 if (!tx_ring->desc)
3376 goto err;
9a799d71 3377
3a581073
JB		 3378 tx_ring->next_to_use = 0;
3379 tx_ring->next_to_clean = 0;
3380 tx_ring->work_limit = tx_ring->count;
9a799d71 3381 return 0;
e01c31a5
JB		 3382
3383err:
3384 vfree(tx_ring->tx_buffer_info);
3385 tx_ring->tx_buffer_info = NULL;
3386 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3387 "descriptor ring\n");
3388 return -ENOMEM;
9a799d71
AK		 3389}
3390
69888674
AD		 3391/**
3392 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3393 * @adapter: board private structure
3394 *
3395 * If this function returns with an error, then it's possible one or
3396 * more of the rings is populated (while the rest are not). It is the
3397 * callers duty to clean those orphaned rings.
3398 *
3399 * Return 0 on success, negative on failure
3400 **/
3401static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3402{
3403 int i, err = 0;
3404
3405 for (i = 0; i < adapter->num_tx_queues; i++) {
3406 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3407 if (!err)
3408 continue;
3409 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3410 break;
3411 }
3412
3413 return err;
3414}
3415
9a799d71
AK		 3416/**
3417 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3418 * @adapter: board private structure
3a581073 3419 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3420 *
3421 * Returns 0 on success, negative on failure
3422 **/
3423int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3424 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3425{
3426 struct pci_dev *pdev = adapter->pdev;
021230d4 3427 int size;
9a799d71 3428
3a581073
JB		 3429 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3430 rx_ring->rx_buffer_info = vmalloc(size);
3431 if (!rx_ring->rx_buffer_info) {
9a799d71 3432 DPRINTK(PROBE, ERR,
b4617240 3433 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3434 goto alloc_failed;
9a799d71 3435 }
3a581073 3436 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3437
9a799d71 3438 /* Round up to nearest 4K */
3a581073
JB		 3439 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3440 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3441
3a581073 3442 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3443
3a581073 3444 if (!rx_ring->desc) {
9a799d71 3445 DPRINTK(PROBE, ERR,
b4617240 3446 "Memory allocation failed for the rx desc ring\n");
3a581073 3447 vfree(rx_ring->rx_buffer_info);
177db6ff 3448 goto alloc_failed;
9a799d71
AK		 3449 }
3450
3a581073
JB		 3451 rx_ring->next_to_clean = 0;
3452 rx_ring->next_to_use = 0;
9a799d71
AK		 3453
3454 return 0;
177db6ff
MC		 3455
3456alloc_failed:
177db6ff 3457 return -ENOMEM;
9a799d71
AK		 3458}
3459
69888674
AD		 3460/**
3461 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3462 * @adapter: board private structure
3463 *
3464 * If this function returns with an error, then it's possible one or
3465 * more of the rings is populated (while the rest are not). It is the
3466 * callers duty to clean those orphaned rings.
3467 *
3468 * Return 0 on success, negative on failure
3469 **/
3470
3471static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3472{
3473 int i, err = 0;
3474
3475 for (i = 0; i < adapter->num_rx_queues; i++) {
3476 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3477 if (!err)
3478 continue;
3479 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3480 break;
3481 }
3482
3483 return err;
3484}
3485
9a799d71
AK		 3486/**
3487 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3488 * @adapter: board private structure
3489 * @tx_ring: Tx descriptor ring for a specific queue
3490 *
3491 * Free all transmit software resources
3492 **/
c431f97e
JB		 3493void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3494 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3495{
3496 struct pci_dev *pdev = adapter->pdev;
3497
3498 ixgbe_clean_tx_ring(adapter, tx_ring);
3499
3500 vfree(tx_ring->tx_buffer_info);
3501 tx_ring->tx_buffer_info = NULL;
3502
3503 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3504
3505 tx_ring->desc = NULL;
3506}
3507
3508/**
3509 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3510 * @adapter: board private structure
3511 *
3512 * Free all transmit software resources
3513 **/
3514static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3515{
3516 int i;
3517
3518 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3519 if (adapter->tx_ring[i].desc)
3520 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3521}
3522
3523/**
b4617240 3524 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3525 * @adapter: board private structure
3526 * @rx_ring: ring to clean the resources from
3527 *
3528 * Free all receive software resources
3529 **/
c431f97e
JB		 3530void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3531 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3532{
3533 struct pci_dev *pdev = adapter->pdev;
3534
3535 ixgbe_clean_rx_ring(adapter, rx_ring);
3536
3537 vfree(rx_ring->rx_buffer_info);
3538 rx_ring->rx_buffer_info = NULL;
3539
3540 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3541
3542 rx_ring->desc = NULL;
3543}
3544
3545/**
3546 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3547 * @adapter: board private structure
3548 *
3549 * Free all receive software resources
3550 **/
3551static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3552{
3553 int i;
3554
3555 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3556 if (adapter->rx_ring[i].desc)
3557 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3558}
3559
9a799d71
AK		 3560/**
3561 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3562 * @netdev: network interface device structure
3563 * @new_mtu: new value for maximum frame size
3564 *
3565 * Returns 0 on success, negative on failure
3566 **/
3567static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3568{
3569 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3570 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3571
42c783c5
JB		 3572 /* MTU < 68 is an error and causes problems on some kernels */
3573 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3574 return -EINVAL;
3575
021230d4 3576 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3577 netdev->mtu, new_mtu);
021230d4 3578 /* must set new MTU before calling down or up */
9a799d71
AK		 3579 netdev->mtu = new_mtu;
3580
d4f80882
AV		 3581 if (netif_running(netdev))
3582 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3583
3584 return 0;
3585}
3586
3587/**
3588 * ixgbe_open - Called when a network interface is made active
3589 * @netdev: network interface device structure
3590 *
3591 * Returns 0 on success, negative value on failure
3592 *
3593 * The open entry point is called when a network interface is made
3594 * active by the system (IFF_UP). At this point all resources needed
3595 * for transmit and receive operations are allocated, the interrupt
3596 * handler is registered with the OS, the watchdog timer is started,
3597 * and the stack is notified that the interface is ready.
3598 **/
3599static int ixgbe_open(struct net_device *netdev)
3600{
3601 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3602 int err;
4bebfaa5
AK		 3603
3604 /* disallow open during test */
3605 if (test_bit(__IXGBE_TESTING, &adapter->state))
3606 return -EBUSY;
9a799d71 3607
54386467
JB		 3608 netif_carrier_off(netdev);
3609
9a799d71
AK		 3610 /* allocate transmit descriptors */
3611 err = ixgbe_setup_all_tx_resources(adapter);
3612 if (err)
3613 goto err_setup_tx;
3614
9a799d71
AK		 3615 /* allocate receive descriptors */
3616 err = ixgbe_setup_all_rx_resources(adapter);
3617 if (err)
3618 goto err_setup_rx;
3619
3620 ixgbe_configure(adapter);
3621
4dd64df8
JB		 3622 ixgbe_napi_add_all(adapter);
3623
021230d4 3624 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3625 if (err)
3626 goto err_req_irq;
3627
9a799d71
AK		 3628 err = ixgbe_up_complete(adapter);
3629 if (err)
3630 goto err_up;
3631
d55b53ff
JK		 3632 netif_tx_start_all_queues(netdev);
3633
9a799d71
AK		 3634 return 0;
3635
3636err_up:
5eba3699 3637 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3638 ixgbe_free_irq(adapter);
3639err_req_irq:
9a799d71 3640err_setup_rx:
a20a1199 3641 ixgbe_free_all_rx_resources(adapter);
9a799d71 3642err_setup_tx:
a20a1199 3643 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3644 ixgbe_reset(adapter);
3645
3646 return err;
3647}
3648
3649/**
3650 * ixgbe_close - Disables a network interface
3651 * @netdev: network interface device structure
3652 *
3653 * Returns 0, this is not allowed to fail
3654 *
3655 * The close entry point is called when an interface is de-activated
3656 * by the OS. The hardware is still under the drivers control, but
3657 * needs to be disabled. A global MAC reset is issued to stop the
3658 * hardware, and all transmit and receive resources are freed.
3659 **/
3660static int ixgbe_close(struct net_device *netdev)
3661{
3662 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3663
3664 ixgbe_down(adapter);
3665 ixgbe_free_irq(adapter);
3666
3667 ixgbe_free_all_tx_resources(adapter);
3668 ixgbe_free_all_rx_resources(adapter);
3669
5eba3699 3670 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3671
3672 return 0;
3673}
3674
b3c8b4ba
AD		 3675/**
3676 * ixgbe_napi_add_all - prep napi structs for use
3677 * @adapter: private struct
4dd64df8 3678 *
b3c8b4ba
AD		 3679 * helper function to napi_add each possible q_vector->napi
3680 */
2f90b865 3681void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3682{
3683 int q_idx, q_vectors;
7adf1525 3684 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 3685 int (*poll)(struct napi_struct *, int);
3686
7adf1525
PWJ		 3687 /* check if we already have our netdev->napi_list populated */
3688 if (&netdev->napi_list != netdev->napi_list.next)
3689 return;
3690
b3c8b4ba
AD		 3691 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3692 poll = &ixgbe_clean_rxonly;
3693 /* Only enable as many vectors as we have rx queues. */
3694 q_vectors = adapter->num_rx_queues;
3695 } else {
3696 poll = &ixgbe_poll;
3697 /* only one q_vector for legacy modes */
3698 q_vectors = 1;
3699 }
3700
3701 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3702 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3703 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3704 }
3705}
3706
2f90b865 3707void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3708{
3709 int q_idx;
3710 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3711
3712 /* legacy and MSI only use one vector */
3713 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3714 q_vectors = 1;
3715
3716 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3717 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3718 if (!q_vector->rxr_count)
3719 continue;
3720 netif_napi_del(&q_vector->napi);
3721 }
3722}
3723
3724#ifdef CONFIG_PM
3725static int ixgbe_resume(struct pci_dev *pdev)
3726{
3727 struct net_device *netdev = pci_get_drvdata(pdev);
3728 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3729 u32 err;
3730
3731 pci_set_power_state(pdev, PCI_D0);
3732 pci_restore_state(pdev);
3733 err = pci_enable_device(pdev);
3734 if (err) {
69888674 3735 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3736 "suspend\n");
3737 return err;
3738 }
3739 pci_set_master(pdev);
3740
3741 pci_enable_wake(pdev, PCI_D3hot, 0);
3742 pci_enable_wake(pdev, PCI_D3cold, 0);
3743
3744 err = ixgbe_init_interrupt_scheme(adapter);
3745 if (err) {
3746 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3747 "device\n");
3748 return err;
3749 }
3750
b3c8b4ba
AD		 3751 ixgbe_reset(adapter);
3752
3753 if (netif_running(netdev)) {
3754 err = ixgbe_open(adapter->netdev);
3755 if (err)
3756 return err;
3757 }
3758
3759 netif_device_attach(netdev);
3760
3761 return 0;
3762}
b3c8b4ba 3763#endif /* CONFIG_PM */
9d8d05ae
RW		 3764
3765static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3766{
3767 struct net_device *netdev = pci_get_drvdata(pdev);
3768 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3769 struct ixgbe_hw *hw = &adapter->hw;
3770 u32 ctrl, fctrl;
3771 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3772#ifdef CONFIG_PM
3773 int retval = 0;
3774#endif
3775
3776 netif_device_detach(netdev);
3777
3778 if (netif_running(netdev)) {
3779 ixgbe_down(adapter);
3780 ixgbe_free_irq(adapter);
3781 ixgbe_free_all_tx_resources(adapter);
3782 ixgbe_free_all_rx_resources(adapter);
3783 }
3784 ixgbe_reset_interrupt_capability(adapter);
3785 ixgbe_napi_del_all(adapter);
7adf1525 3786 INIT_LIST_HEAD(&netdev->napi_list);
b3c8b4ba
AD		 3787 kfree(adapter->tx_ring);
3788 kfree(adapter->rx_ring);
3789
3790#ifdef CONFIG_PM
3791 retval = pci_save_state(pdev);
3792 if (retval)
3793 return retval;
4df10466 3794
b3c8b4ba 3795#endif
e8e26350
PW		 3796 if (wufc) {
3797 ixgbe_set_rx_mode(netdev);
b3c8b4ba 3798
e8e26350
PW		 3799 /* turn on all-multi mode if wake on multicast is enabled */
3800 if (wufc & IXGBE_WUFC_MC) {
3801 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3802 fctrl |= IXGBE_FCTRL_MPE;
3803 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3804 }
3805
3806 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3807 ctrl |= IXGBE_CTRL_GIO_DIS;
3808 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3809
3810 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
3811 } else {
3812 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
3813 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
3814 }
3815
3816 if (wufc && hw->mac.type == ixgbe_mac_82599EB) {
3817 pci_enable_wake(pdev, PCI_D3hot, 1);
3818 pci_enable_wake(pdev, PCI_D3cold, 1);
3819 } else {
3820 pci_enable_wake(pdev, PCI_D3hot, 0);
3821 pci_enable_wake(pdev, PCI_D3cold, 0);
3822 }
b3c8b4ba 3823
9d8d05ae
RW		 3824 *enable_wake = !!wufc;
3825
b3c8b4ba
AD		 3826 ixgbe_release_hw_control(adapter);
3827
3828 pci_disable_device(pdev);
3829
9d8d05ae
RW		 3830 return 0;
3831}
3832
3833#ifdef CONFIG_PM
3834static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3835{
3836 int retval;
3837 bool wake;
3838
3839 retval = __ixgbe_shutdown(pdev, &wake);
3840 if (retval)
3841 return retval;
3842
3843 if (wake) {
3844 pci_prepare_to_sleep(pdev);
3845 } else {
3846 pci_wake_from_d3(pdev, false);
3847 pci_set_power_state(pdev, PCI_D3hot);
3848 }
b3c8b4ba
AD		 3849
3850 return 0;
3851}
9d8d05ae 3852#endif /* CONFIG_PM */
b3c8b4ba
AD		 3853
3854static void ixgbe_shutdown(struct pci_dev *pdev)
3855{
9d8d05ae
RW		 3856 bool wake;
3857
3858 __ixgbe_shutdown(pdev, &wake);
3859
3860 if (system_state == SYSTEM_POWER_OFF) {
3861 pci_wake_from_d3(pdev, wake);
3862 pci_set_power_state(pdev, PCI_D3hot);
3863 }
b3c8b4ba
AD		 3864}
3865
9a799d71
AK		 3866/**
3867 * ixgbe_update_stats - Update the board statistics counters.
3868 * @adapter: board private structure
3869 **/
3870void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3871{
3872 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3873 u64 total_mpc = 0;
3874 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 3875
d51019a4 3876 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 3877 u64 rsc_count = 0;
d51019a4
PW		 3878 for (i = 0; i < 16; i++)
3879 adapter->hw_rx_no_dma_resources +=
3880 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 3881 for (i = 0; i < adapter->num_rx_queues; i++)
3882 rsc_count += adapter->rx_ring[i].rsc_count;
3883 adapter->rsc_count = rsc_count;
d51019a4
PW		 3884 }
3885
9a799d71 3886 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3887 for (i = 0; i < 8; i++) {
3888 /* for packet buffers not used, the register should read 0 */
3889 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3890 missed_rx += mpc;
3891 adapter->stats.mpc[i] += mpc;
3892 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 3893 if (hw->mac.type == ixgbe_mac_82598EB)
3894 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3895 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3896 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3897 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3898 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 3899 if (hw->mac.type == ixgbe_mac_82599EB) {
3900 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3901 IXGBE_PXONRXCNT(i));
3902 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3903 IXGBE_PXOFFRXCNT(i));
3904 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 3905 } else {
3906 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3907 IXGBE_PXONRXC(i));
3908 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3909 IXGBE_PXOFFRXC(i));
3910 }
2f90b865
AD		 3911 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3912 IXGBE_PXONTXC(i));
2f90b865 3913 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 3914 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3915 }
3916 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3917 /* work around hardware counting issue */
3918 adapter->stats.gprc -= missed_rx;
3919
3920 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 3921 if (hw->mac.type == ixgbe_mac_82599EB) {
3922 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3923 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
3924 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3925 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
3926 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3927 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
3928 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3929 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3930 } else {
3931 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3932 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3933 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3934 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3935 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3936 }
9a799d71
AK		 3937 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3938 adapter->stats.bprc += bprc;
3939 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 3940 if (hw->mac.type == ixgbe_mac_82598EB)
3941 adapter->stats.mprc -= bprc;
9a799d71
AK		 3942 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3943 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3944 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3945 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3946 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3947 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3948 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 3949 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 3950 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3951 adapter->stats.lxontxc += lxon;
3952 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3953 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3954 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3955 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3956 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3957 /*
3958 * 82598 errata - tx of flow control packets is included in tx counters
3959 */
3960 xon_off_tot = lxon + lxoff;
3961 adapter->stats.gptc -= xon_off_tot;
3962 adapter->stats.mptc -= xon_off_tot;
3963 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3964 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3965 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3966 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3967 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3968 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3969 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3970 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3971 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3972 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3973 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3974 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3975 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3976
3977 /* Fill out the OS statistics structure */
9a799d71
AK		 3978 adapter->net_stats.multicast = adapter->stats.mprc;
3979
3980 /* Rx Errors */
3981 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3982 adapter->stats.rlec;
9a799d71
AK		 3983 adapter->net_stats.rx_dropped = 0;
3984 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3985 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3986 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3987}
3988
3989/**
3990 * ixgbe_watchdog - Timer Call-back
3991 * @data: pointer to adapter cast into an unsigned long
3992 **/
3993static void ixgbe_watchdog(unsigned long data)
3994{
3995 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3996 struct ixgbe_hw *hw = &adapter->hw;
3997
3998 /* Do the watchdog outside of interrupt context due to the lovely
3999 * delays that some of the newer hardware requires */
4000 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4001 u64 eics = 0;
4002 int i;
4003
4004 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
4005 eics |= (1 << i);
4006
cf8280ee 4007 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4008 switch (hw->mac.type) {
4009 case ixgbe_mac_82598EB:
4010 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4011 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4012 } else {
4013 /*
4014 * for legacy and MSI interrupts don't set any
4015 * bits that are enabled for EIAM, because this
4016 * operation would set *both* EIMS and EICS for
4017 * any bit in EIAM
4018 */
4019 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4020 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4021 }
4022 break;
4023 case ixgbe_mac_82599EB:
4024 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4025 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4026 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4027 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4028 (u32)(eics >> 32));
4029 } else {
4030 /*
4031 * for legacy and MSI interrupts don't set any
4032 * bits that are enabled for EIAM, because this
4033 * operation would set *both* EIMS and EICS for
4034 * any bit in EIAM
4035 */
4036 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4037 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4038 }
4039 break;
4040 default:
4041 break;
cf8280ee
JB		 4042 }
4043 /* Reset the timer */
4044 mod_timer(&adapter->watchdog_timer,
4045 round_jiffies(jiffies + 2 * HZ));
4046 }
9a799d71 4047
cf8280ee
JB		 4048 schedule_work(&adapter->watchdog_task);
4049}
4050
e8e26350
PW		 4051/**
4052 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4053 * @work: pointer to work_struct containing our data
4054 **/
4055static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4056{
4057 struct ixgbe_adapter *adapter = container_of(work,
4058 struct ixgbe_adapter,
4059 multispeed_fiber_task);
4060 struct ixgbe_hw *hw = &adapter->hw;
4061 u32 autoneg;
4062
4063 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4064 if (hw->mac.ops.get_link_capabilities)
4065 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4066 &hw->mac.autoneg);
4067 if (hw->mac.ops.setup_link_speed)
4068 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4069 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4070 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4071}
4072
4073/**
4074 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4075 * @work: pointer to work_struct containing our data
4076 **/
4077static void ixgbe_sfp_config_module_task(struct work_struct *work)
4078{
4079 struct ixgbe_adapter *adapter = container_of(work,
4080 struct ixgbe_adapter,
4081 sfp_config_module_task);
4082 struct ixgbe_hw *hw = &adapter->hw;
4083 u32 err;
4084
4085 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4086 err = hw->phy.ops.identify_sfp(hw);
4087 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4088 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4089 ixgbe_down(adapter);
4090 return;
4091 }
4092 hw->mac.ops.setup_sfp(hw);
4093
8d1c3c07 4094 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4095 /* This will also work for DA Twinax connections */
4096 schedule_work(&adapter->multispeed_fiber_task);
4097 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4098}
4099
cf8280ee 4100/**
69888674
AD		 4101 * ixgbe_watchdog_task - worker thread to bring link up
4102 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4103 **/
4104static void ixgbe_watchdog_task(struct work_struct *work)
4105{
4106 struct ixgbe_adapter *adapter = container_of(work,
4107 struct ixgbe_adapter,
4108 watchdog_task);
4109 struct net_device *netdev = adapter->netdev;
4110 struct ixgbe_hw *hw = &adapter->hw;
4111 u32 link_speed = adapter->link_speed;
4112 bool link_up = adapter->link_up;
bc59fcda
NS		 4113 int i;
4114 struct ixgbe_ring *tx_ring;
4115 int some_tx_pending = 0;
cf8280ee
JB		 4116
4117 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4118
4119 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4120 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4121 if (link_up ||
4122 time_after(jiffies, (adapter->link_check_timeout +
4123 IXGBE_TRY_LINK_TIMEOUT))) {
4124 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4125 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4126 }
4127 adapter->link_up = link_up;
4128 adapter->link_speed = link_speed;
4129 }
9a799d71
AK		 4130
4131 if (link_up) {
4132 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4133 bool flow_rx, flow_tx;
4134
4135 if (hw->mac.type == ixgbe_mac_82599EB) {
4136 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4137 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4138 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4139 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4140 } else {
4141 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4142 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4143 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4144 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4145 }
4146
a46e534b
JK		 4147 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4148 "Flow Control: %s\n",
4149 netdev->name,
4150 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4151 "10 Gbps" :
4152 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4153 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4154 ((flow_rx && flow_tx) ? "RX/TX" :
4155 (flow_rx ? "RX" :
4156 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4157
4158 netif_carrier_on(netdev);
9a799d71
AK		 4159 } else {
4160 /* Force detection of hung controller */
4161 adapter->detect_tx_hung = true;
4162 }
4163 } else {
cf8280ee
JB		 4164 adapter->link_up = false;
4165 adapter->link_speed = 0;
9a799d71 4166 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4167 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4168 netdev->name);
9a799d71 4169 netif_carrier_off(netdev);
9a799d71
AK		 4170 }
4171 }
4172
bc59fcda
NS		 4173 if (!netif_carrier_ok(netdev)) {
4174 for (i = 0; i < adapter->num_tx_queues; i++) {
4175 tx_ring = &adapter->tx_ring[i];
4176 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4177 some_tx_pending = 1;
4178 break;
4179 }
4180 }
4181
4182 if (some_tx_pending) {
4183 /* We've lost link, so the controller stops DMA,
4184 * but we've got queued Tx work that's never going
4185 * to get done, so reset controller to flush Tx.
4186 * (Do the reset outside of interrupt context).
4187 */
4188 schedule_work(&adapter->reset_task);
4189 }
4190 }
4191
9a799d71 4192 ixgbe_update_stats(adapter);
cf8280ee 4193 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4194}
4195
9a799d71 4196static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4197 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4198 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4199{
4200 struct ixgbe_adv_tx_context_desc *context_desc;
4201 unsigned int i;
4202 int err;
4203 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4204 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4205 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4206
4207 if (skb_is_gso(skb)) {
4208 if (skb_header_cloned(skb)) {
4209 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4210 if (err)
4211 return err;
4212 }
4213 l4len = tcp_hdrlen(skb);
4214 *hdr_len += l4len;
4215
8327d000 4216 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4217 struct iphdr *iph = ip_hdr(skb);
4218 iph->tot_len = 0;
4219 iph->check = 0;
4220 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4221 iph->daddr, 0,
4222 IPPROTO_TCP,
4223 0);
9a799d71
AK		 4224 adapter->hw_tso_ctxt++;
4225 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4226 ipv6_hdr(skb)->payload_len = 0;
4227 tcp_hdr(skb)->check =
4228 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4229 &ipv6_hdr(skb)->daddr,
4230 0, IPPROTO_TCP, 0);
9a799d71
AK		 4231 adapter->hw_tso6_ctxt++;
4232 }
4233
4234 i = tx_ring->next_to_use;
4235
4236 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4237 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4238
4239 /* VLAN MACLEN IPLEN */
4240 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4241 vlan_macip_lens |=
4242 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4243 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4244 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4245 *hdr_len += skb_network_offset(skb);
4246 vlan_macip_lens |=
4247 (skb_transport_header(skb) - skb_network_header(skb));
4248 *hdr_len +=
4249 (skb_transport_header(skb) - skb_network_header(skb));
4250 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4251 context_desc->seqnum_seed = 0;
4252
4253 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4254 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4255 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4256
8327d000 4257 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4258 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4259 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4260 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4261
4262 /* MSS L4LEN IDX */
9f8cdf4f 4263 mss_l4len_idx =
9a799d71
AK		 4264 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4265 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4266 /* use index 1 for TSO */
4267 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4268 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4269
4270 tx_buffer_info->time_stamp = jiffies;
4271 tx_buffer_info->next_to_watch = i;
4272
4273 i++;
4274 if (i == tx_ring->count)
4275 i = 0;
4276 tx_ring->next_to_use = i;
4277
4278 return true;
4279 }
4280 return false;
4281}
4282
4283static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4284 struct ixgbe_ring *tx_ring,
4285 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4286{
4287 struct ixgbe_adv_tx_context_desc *context_desc;
4288 unsigned int i;
4289 struct ixgbe_tx_buffer *tx_buffer_info;
4290 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4291
4292 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4293 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4294 i = tx_ring->next_to_use;
4295 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4296 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4297
4298 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4299 vlan_macip_lens |=
4300 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4301 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4302 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4303 if (skb->ip_summed == CHECKSUM_PARTIAL)
4304 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4305 skb_network_header(skb));
9a799d71
AK		 4306
4307 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4308 context_desc->seqnum_seed = 0;
4309
4310 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4311 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4312
4313 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4314 switch (skb->protocol) {
09640e63 4315 case cpu_to_be16(ETH_P_IP):
9a799d71 4316 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4317 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4318 type_tucmd_mlhl |=
b4617240 4319 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4320 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4321 type_tucmd_mlhl |=
4322 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4323 break;
09640e63 4324 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4325 /* XXX what about other V6 headers?? */
4326 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4327 type_tucmd_mlhl |=
b4617240 4328 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4329 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4330 type_tucmd_mlhl |=
4331 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4332 break;
41825d71
AK		 4333 default:
4334 if (unlikely(net_ratelimit())) {
4335 DPRINTK(PROBE, WARNING,
4336 "partial checksum but proto=%x!\n",
4337 skb->protocol);
4338 }
4339 break;
4340 }
9a799d71
AK		 4341 }
4342
4343 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4344 /* use index zero for tx checksum offload */
9a799d71
AK		 4345 context_desc->mss_l4len_idx = 0;
4346
4347 tx_buffer_info->time_stamp = jiffies;
4348 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4349
9a799d71
AK		 4350 adapter->hw_csum_tx_good++;
4351 i++;
4352 if (i == tx_ring->count)
4353 i = 0;
4354 tx_ring->next_to_use = i;
4355
4356 return true;
4357 }
9f8cdf4f 4358
9a799d71
AK		 4359 return false;
4360}
4361
4362static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 4363 struct ixgbe_ring *tx_ring,
4364 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 4365{
4366 struct ixgbe_tx_buffer *tx_buffer_info;
44df32c5 4367 unsigned int len = skb_headlen(skb);
9a799d71
AK		 4368 unsigned int offset = 0, size, count = 0, i;
4369 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4370 unsigned int f;
44df32c5 4371 dma_addr_t *map;
9a799d71
AK		 4372
4373 i = tx_ring->next_to_use;
4374
44df32c5
AD		 4375 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4376 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4377 return 0;
4378 }
4379
4380 map = skb_shinfo(skb)->dma_maps;
4381
9a799d71
AK		 4382 while (len) {
4383 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4384 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4385
4386 tx_buffer_info->length = size;
44df32c5 4387 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4388 tx_buffer_info->time_stamp = jiffies;
4389 tx_buffer_info->next_to_watch = i;
4390
4391 len -= size;
4392 offset += size;
4393 count++;
44df32c5
AD		 4394
4395 if (len) {
4396 i++;
4397 if (i == tx_ring->count)
4398 i = 0;
4399 }
9a799d71
AK		 4400 }
4401
4402 for (f = 0; f < nr_frags; f++) {
4403 struct skb_frag_struct *frag;
4404
4405 frag = &skb_shinfo(skb)->frags[f];
4406 len = frag->size;
44df32c5 4407 offset = 0;
9a799d71
AK		 4408
4409 while (len) {
44df32c5
AD		 4410 i++;
4411 if (i == tx_ring->count)
4412 i = 0;
4413
9a799d71
AK		 4414 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4415 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4416
4417 tx_buffer_info->length = size;
44df32c5 4418 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4419 tx_buffer_info->time_stamp = jiffies;
4420 tx_buffer_info->next_to_watch = i;
4421
4422 len -= size;
4423 offset += size;
4424 count++;
9a799d71
AK		 4425 }
4426 }
44df32c5 4427
9a799d71
AK		 4428 tx_ring->tx_buffer_info[i].skb = skb;
4429 tx_ring->tx_buffer_info[first].next_to_watch = i;
4430
4431 return count;
4432}
4433
4434static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4435 struct ixgbe_ring *tx_ring,
4436 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4437{
4438 union ixgbe_adv_tx_desc *tx_desc = NULL;
4439 struct ixgbe_tx_buffer *tx_buffer_info;
4440 u32 olinfo_status = 0, cmd_type_len = 0;
4441 unsigned int i;
4442 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4443
4444 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4445
4446 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4447
4448 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4449 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4450
4451 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4452 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4453
4454 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4455 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4456
4eeae6fd
PW		 4457 /* use index 1 context for tso */
4458 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4459 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4460 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4461 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4462
4463 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4464 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4465 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4466
4467 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4468
4469 i = tx_ring->next_to_use;
4470 while (count--) {
4471 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4472 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4473 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4474 tx_desc->read.cmd_type_len =
b4617240 4475 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4476 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4477 i++;
4478 if (i == tx_ring->count)
4479 i = 0;
4480 }
4481
4482 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4483
4484 /*
4485 * Force memory writes to complete before letting h/w
4486 * know there are new descriptors to fetch. (Only
4487 * applicable for weak-ordered memory model archs,
4488 * such as IA-64).
4489 */
4490 wmb();
4491
4492 tx_ring->next_to_use = i;
4493 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4494}
4495
e092be60 4496static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4497 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4498{
4499 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4500
30eba97a 4501 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4502 /* Herbert's original patch had:
4503 * smp_mb__after_netif_stop_queue();
4504 * but since that doesn't exist yet, just open code it. */
4505 smp_mb();
4506
4507 /* We need to check again in a case another CPU has just
4508 * made room available. */
4509 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4510 return -EBUSY;
4511
4512 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4513 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4514 ++adapter->restart_queue;
4515 return 0;
4516}
4517
4518static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4519 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4520{
4521 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4522 return 0;
4523 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4524}
4525
09a3b1f8
SH		 4526static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4527{
4528 struct ixgbe_adapter *adapter = netdev_priv(dev);
4529
4530 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4531 return 0; /* All traffic should default to class 0 */
4532
4533 return skb_tx_hash(dev, skb);
4534}
4535
9a799d71
AK		 4536static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4537{
4538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4539 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4540 unsigned int first;
4541 unsigned int tx_flags = 0;
30eba97a
AV		 4542 u8 hdr_len = 0;
4543 int r_idx = 0, tso;
9a799d71
AK		 4544 int count = 0;
4545 unsigned int f;
9f8cdf4f 4546
95615d90 4547 r_idx = skb->queue_mapping;
30eba97a 4548 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4549
9f8cdf4f
JB		 4550 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4551 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4552 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4553 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4554 tx_flags |= (skb->queue_mapping << 13);
4555 }
4556 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4557 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4558 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4559 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4560 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4561 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4562 }
9f8cdf4f
JB		 4563 /* three things can cause us to need a context descriptor */
4564 if (skb_is_gso(skb) ||
4565 (skb->ip_summed == CHECKSUM_PARTIAL) ||
4566 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 4567 count++;
4568
9f8cdf4f
JB		 4569 count += TXD_USE_COUNT(skb_headlen(skb));
4570 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4571 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4572
e092be60 4573 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4574 adapter->tx_busy++;
9a799d71
AK		 4575 return NETDEV_TX_BUSY;
4576 }
9a799d71 4577
8327d000 4578 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4579 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4580 first = tx_ring->next_to_use;
4581 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4582 if (tso < 0) {
4583 dev_kfree_skb_any(skb);
4584 return NETDEV_TX_OK;
4585 }
4586
4587 if (tso)
4588 tx_flags |= IXGBE_TX_FLAGS_TSO;
4589 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 4590 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 4591 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4592
44df32c5 4593 count = ixgbe_tx_map(adapter, tx_ring, skb, first);
9a799d71 4594
44df32c5
AD		 4595 if (count) {
4596 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4597 hdr_len);
4598 netdev->trans_start = jiffies;
4599 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4600
44df32c5
AD		 4601 } else {
4602 dev_kfree_skb_any(skb);
4603 tx_ring->tx_buffer_info[first].time_stamp = 0;
4604 tx_ring->next_to_use = first;
4605 }
9a799d71
AK		 4606
4607 return NETDEV_TX_OK;
4608}
4609
4610/**
4611 * ixgbe_get_stats - Get System Network Statistics
4612 * @netdev: network interface device structure
4613 *
4614 * Returns the address of the device statistics structure.
4615 * The statistics are actually updated from the timer callback.
4616 **/
4617static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4618{
4619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4620
4621 /* only return the current stats */
4622 return &adapter->net_stats;
4623}
4624
4625/**
4626 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4627 * @netdev: network interface device structure
4628 * @p: pointer to an address structure
4629 *
4630 * Returns 0 on success, negative on failure
4631 **/
4632static int ixgbe_set_mac(struct net_device *netdev, void *p)
4633{
4634 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4635 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4636 struct sockaddr *addr = p;
4637
4638 if (!is_valid_ether_addr(addr->sa_data))
4639 return -EADDRNOTAVAIL;
4640
4641 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4642 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4643
b4617240 4644 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4645
4646 return 0;
4647}
4648
4649#ifdef CONFIG_NET_POLL_CONTROLLER
4650/*
4651 * Polling 'interrupt' - used by things like netconsole to send skbs
4652 * without having to re-enable interrupts. It's not called while
4653 * the interrupt routine is executing.
4654 */
4655static void ixgbe_netpoll(struct net_device *netdev)
4656{
4657 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4658
4659 disable_irq(adapter->pdev->irq);
4660 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
4661 ixgbe_intr(adapter->pdev->irq, netdev);
4662 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
4663 enable_irq(adapter->pdev->irq);
4664}
4665#endif
4666
0edc3527
SH		 4667static const struct net_device_ops ixgbe_netdev_ops = {
4668 .ndo_open = ixgbe_open,
4669 .ndo_stop = ixgbe_close,
00829823 4670 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 4671 .ndo_select_queue = ixgbe_select_queue,
0edc3527 4672 .ndo_get_stats = ixgbe_get_stats,
e90d400c 4673 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 4674 .ndo_set_multicast_list = ixgbe_set_rx_mode,
4675 .ndo_validate_addr = eth_validate_addr,
4676 .ndo_set_mac_address = ixgbe_set_mac,
4677 .ndo_change_mtu = ixgbe_change_mtu,
4678 .ndo_tx_timeout = ixgbe_tx_timeout,
4679 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
4680 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
4681 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
4682#ifdef CONFIG_NET_POLL_CONTROLLER
4683 .ndo_poll_controller = ixgbe_netpoll,
4684#endif
4685};
4686
9a799d71
AK		 4687/**
4688 * ixgbe_probe - Device Initialization Routine
4689 * @pdev: PCI device information struct
4690 * @ent: entry in ixgbe_pci_tbl
4691 *
4692 * Returns 0 on success, negative on failure
4693 *
4694 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
4695 * The OS initialization, configuring of the adapter private structure,
4696 * and a hardware reset occur.
4697 **/
4698static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 4699 const struct pci_device_id *ent)
9a799d71
AK		 4700{
4701 struct net_device *netdev;
4702 struct ixgbe_adapter *adapter = NULL;
4703 struct ixgbe_hw *hw;
4704 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 4705 static int cards_found;
4706 int i, err, pci_using_dac;
e8e26350 4707 u16 pm_value = 0;
c44ade9e 4708 u32 part_num, eec;
9a799d71
AK		 4709
4710 err = pci_enable_device(pdev);
4711 if (err)
4712 return err;
4713
6a35528a
YH		 4714 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
4715 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 4716 pci_using_dac = 1;
4717 } else {
284901a9 4718 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4719 if (err) {
284901a9 4720 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 4721 if (err) {
b4617240
PW		 4722 dev_err(&pdev->dev, "No usable DMA "
4723 "configuration, aborting\n");
9a799d71
AK		 4724 goto err_dma;
4725 }
4726 }
4727 pci_using_dac = 0;
4728 }
4729
4730 err = pci_request_regions(pdev, ixgbe_driver_name);
4731 if (err) {
4732 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
4733 goto err_pci_reg;
4734 }
4735
6fabd715
PWJ		 4736 err = pci_enable_pcie_error_reporting(pdev);
4737 if (err) {
4738 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
4739 "0x%x\n", err);
4740 /* non-fatal, continue */
4741 }
4742
9a799d71 4743 pci_set_master(pdev);
fb3b27bc 4744 pci_save_state(pdev);
9a799d71 4745
30eba97a 4746 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 4747 if (!netdev) {
4748 err = -ENOMEM;
4749 goto err_alloc_etherdev;
4750 }
4751
9a799d71
AK		 4752 SET_NETDEV_DEV(netdev, &pdev->dev);
4753
4754 pci_set_drvdata(pdev, netdev);
4755 adapter = netdev_priv(netdev);
4756
4757 adapter->netdev = netdev;
4758 adapter->pdev = pdev;
4759 hw = &adapter->hw;
4760 hw->back = adapter;
4761 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
4762
05857980
JK		 4763 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
4764 pci_resource_len(pdev, 0));
9a799d71
AK		 4765 if (!hw->hw_addr) {
4766 err = -EIO;
4767 goto err_ioremap;
4768 }
4769
4770 for (i = 1; i <= 5; i++) {
4771 if (pci_resource_len(pdev, i) == 0)
4772 continue;
4773 }
4774
0edc3527 4775 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 4776 ixgbe_set_ethtool_ops(netdev);
9a799d71 4777 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 4778 strcpy(netdev->name, pci_name(pdev));
4779
9a799d71
AK		 4780 adapter->bd_number = cards_found;
4781
9a799d71
AK		 4782 /* Setup hw api */
4783 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 4784 hw->mac.type = ii->mac;
9a799d71 4785
c44ade9e
JB		 4786 /* EEPROM */
4787 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4788 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4789 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4790 if (!(eec & (1 << 8)))
4791 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4792
4793 /* PHY */
4794 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0
DS		 4795 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4796
4797 /* set up this timer and work struct before calling get_invariants
4798 * which might start the timer
4799 */
4800 init_timer(&adapter->sfp_timer);
4801 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4802 adapter->sfp_timer.data = (unsigned long) adapter;
4803
4804 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 4805
e8e26350
PW		 4806 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
4807 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
4808
4809 /* a new SFP+ module arrival, called from GPI SDP2 context */
4810 INIT_WORK(&adapter->sfp_config_module_task,
4811 ixgbe_sfp_config_module_task);
4812
9a799d71 4813 err = ii->get_invariants(hw);
c4900be0
DS		 4814 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4815 /* start a kernel thread to watch for a module to arrive */
4816 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4817 mod_timer(&adapter->sfp_timer,
4818 round_jiffies(jiffies + (2 * HZ)));
4819 err = 0;
4820 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4821 DPRINTK(PROBE, ERR, "failed to load because an "
4822 "unsupported SFP+ module type was detected.\n");
9a799d71 4823 goto err_hw_init;
c4900be0
DS		 4824 } else if (err) {
4825 goto err_hw_init;
4826 }
9a799d71
AK		 4827
4828 /* setup the private structure */
4829 err = ixgbe_sw_init(adapter);
4830 if (err)
4831 goto err_sw_init;
4832
c44ade9e
JB		 4833 /* reset_hw fills in the perm_addr as well */
4834 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 4835 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4836 dev_err(&adapter->pdev->dev, "failed to load because an "
4837 "unsupported SFP+ module type was detected.\n");
4838 goto err_sw_init;
4839 } else if (err) {
c44ade9e
JB		 4840 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4841 goto err_sw_init;
4842 }
4843
9a799d71 4844 netdev->features = NETIF_F_SG |
b4617240
PW		 4845 NETIF_F_IP_CSUM |
4846 NETIF_F_HW_VLAN_TX |
4847 NETIF_F_HW_VLAN_RX |
4848 NETIF_F_HW_VLAN_FILTER;
9a799d71 4849
e9990a9c 4850 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4851 netdev->features |= NETIF_F_TSO;
9a799d71 4852 netdev->features |= NETIF_F_TSO6;
78b6f4ce 4853 netdev->features |= NETIF_F_GRO;
ad31c402 4854
45a5ead0
JB		 4855 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4856 netdev->features |= NETIF_F_SCTP_CSUM;
4857
ad31c402
JK		 4858 netdev->vlan_features |= NETIF_F_TSO;
4859 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4860 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4861 netdev->vlan_features |= NETIF_F_SG;
4862
2f90b865
AD		 4863 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4864 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4865
7a6b6f51 4866#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4867 netdev->dcbnl_ops = &dcbnl_ops;
4868#endif
4869
9a799d71
AK		 4870 if (pci_using_dac)
4871 netdev->features |= NETIF_F_HIGHDMA;
4872
f8212f97
AD		 4873 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
4874 netdev->features |= NETIF_F_LRO;
4875
9a799d71 4876 /* make sure the EEPROM is good */
c44ade9e 4877 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4878 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4879 err = -EIO;
4880 goto err_eeprom;
4881 }
4882
4883 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4884 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4885
c44ade9e
JB		 4886 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4887 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4888 err = -EIO;
4889 goto err_eeprom;
4890 }
4891
4892 init_timer(&adapter->watchdog_timer);
4893 adapter->watchdog_timer.function = &ixgbe_watchdog;
4894 adapter->watchdog_timer.data = (unsigned long)adapter;
4895
4896 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4897 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4898
021230d4
AV		 4899 err = ixgbe_init_interrupt_scheme(adapter);
4900 if (err)
4901 goto err_sw_init;
9a799d71 4902
e8e26350
PW		 4903 switch (pdev->device) {
4904 case IXGBE_DEV_ID_82599_KX4:
4905#define IXGBE_PCIE_PMCSR 0x44
4906 adapter->wol = IXGBE_WUFC_MAG;
4907 pci_read_config_word(pdev, IXGBE_PCIE_PMCSR, &pm_value);
4908 pci_write_config_word(pdev, IXGBE_PCIE_PMCSR,
4909 (pm_value | (1 << 8)));
4910 break;
4911 default:
4912 adapter->wol = 0;
4913 break;
4914 }
4915 device_init_wakeup(&adapter->pdev->dev, true);
4916 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
4917
04f165ef
PW		 4918 /* pick up the PCI bus settings for reporting later */
4919 hw->mac.ops.get_bus_info(hw);
4920
9a799d71 4921 /* print bus type/speed/width info */
7c510e4b 4922 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 4923 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
4924 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
4925 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
4926 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
4927 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 4928 "Unknown"),
7c510e4b 4929 netdev->dev_addr);
c44ade9e 4930 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 4931 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
4932 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
4933 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
4934 (part_num >> 8), (part_num & 0xff));
4935 else
4936 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
4937 hw->mac.type, hw->phy.type,
4938 (part_num >> 8), (part_num & 0xff));
9a799d71 4939
e8e26350 4940 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 4941 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4942 "this card is not sufficient for optimal "
4943 "performance.\n");
0c254d86 4944 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4945 "PCI-Express slot is required.\n");
0c254d86
AK		 4946 }
4947
34b0368c
PWJ		 4948 /* save off EEPROM version number */
4949 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
4950
9a799d71 4951 /* reset the hardware with the new settings */
c44ade9e
JB		 4952 hw->mac.ops.start_hw(hw);
4953
9a799d71
AK		 4954 strcpy(netdev->name, "eth%d");
4955 err = register_netdev(netdev);
4956 if (err)
4957 goto err_register;
4958
54386467
JB		 4959 /* carrier off reporting is important to ethtool even BEFORE open */
4960 netif_carrier_off(netdev);
4961
5dd2d332 4962#ifdef CONFIG_IXGBE_DCA
652f093f 4963 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4964 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4965 /* always use CB2 mode, difference is masked
4966 * in the CB driver */
4967 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4968 ixgbe_setup_dca(adapter);
4969 }
4970#endif
9a799d71
AK		 4971
4972 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4973 cards_found++;
4974 return 0;
4975
4976err_register:
5eba3699 4977 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4978err_hw_init:
4979err_sw_init:
021230d4 4980 ixgbe_reset_interrupt_capability(adapter);
9a799d71 4981err_eeprom:
c4900be0
DS		 4982 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4983 del_timer_sync(&adapter->sfp_timer);
4984 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 4985 cancel_work_sync(&adapter->multispeed_fiber_task);
4986 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 4987 iounmap(hw->hw_addr);
4988err_ioremap:
4989 free_netdev(netdev);
4990err_alloc_etherdev:
4991 pci_release_regions(pdev);
4992err_pci_reg:
4993err_dma:
4994 pci_disable_device(pdev);
4995 return err;
4996}
4997
4998/**
4999 * ixgbe_remove - Device Removal Routine
5000 * @pdev: PCI device information struct
5001 *
5002 * ixgbe_remove is called by the PCI subsystem to alert the driver
5003 * that it should release a PCI device. The could be caused by a
5004 * Hot-Plug event, or because the driver is going to be removed from
5005 * memory.
5006 **/
5007static void __devexit ixgbe_remove(struct pci_dev *pdev)
5008{
5009 struct net_device *netdev = pci_get_drvdata(pdev);
5010 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5011 int err;
9a799d71
AK		 5012
5013 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5014 /* clear the module not found bit to make sure the worker won't
5015 * reschedule
5016 */
5017 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5018 del_timer_sync(&adapter->watchdog_timer);
5019
c4900be0
DS		 5020 del_timer_sync(&adapter->sfp_timer);
5021 cancel_work_sync(&adapter->watchdog_task);
5022 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5023 cancel_work_sync(&adapter->multispeed_fiber_task);
5024 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5025 flush_scheduled_work();
5026
5dd2d332 5027#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5028 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5029 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5030 dca_remove_requester(&pdev->dev);
5031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5032 }
5033
5034#endif
c4900be0
DS		 5035 if (netdev->reg_state == NETREG_REGISTERED)
5036 unregister_netdev(netdev);
9a799d71 5037
021230d4 5038 ixgbe_reset_interrupt_capability(adapter);
5eba3699 5039
021230d4 5040 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5041
5042 iounmap(adapter->hw.hw_addr);
5043 pci_release_regions(pdev);
5044
021230d4
AV		 5045 DPRINTK(PROBE, INFO, "complete\n");
5046 kfree(adapter->tx_ring);
5047 kfree(adapter->rx_ring);
5048
9a799d71
AK		 5049 free_netdev(netdev);
5050
6fabd715
PWJ		 5051 err = pci_disable_pcie_error_reporting(pdev);
5052 if (err)
5053 dev_err(&pdev->dev,
5054 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5055
9a799d71
AK		 5056 pci_disable_device(pdev);
5057}
5058
5059/**
5060 * ixgbe_io_error_detected - called when PCI error is detected
5061 * @pdev: Pointer to PCI device
5062 * @state: The current pci connection state
5063 *
5064 * This function is called after a PCI bus error affecting
5065 * this device has been detected.
5066 */
5067static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5068 pci_channel_state_t state)
9a799d71
AK		 5069{
5070 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5072
5073 netif_device_detach(netdev);
5074
5075 if (netif_running(netdev))
5076 ixgbe_down(adapter);
5077 pci_disable_device(pdev);
5078
b4617240 5079 /* Request a slot reset. */
9a799d71
AK		 5080 return PCI_ERS_RESULT_NEED_RESET;
5081}
5082
5083/**
5084 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5085 * @pdev: Pointer to PCI device
5086 *
5087 * Restart the card from scratch, as if from a cold-boot.
5088 */
5089static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5090{
5091 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5093 pci_ers_result_t result;
5094 int err;
9a799d71
AK		 5095
5096 if (pci_enable_device(pdev)) {
5097 DPRINTK(PROBE, ERR,
b4617240 5098 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5099 result = PCI_ERS_RESULT_DISCONNECT;
5100 } else {
5101 pci_set_master(pdev);
5102 pci_restore_state(pdev);
9a799d71 5103
6fabd715
PWJ		 5104 pci_enable_wake(pdev, PCI_D3hot, 0);
5105 pci_enable_wake(pdev, PCI_D3cold, 0);
9a799d71 5106
6fabd715 5107 ixgbe_reset(adapter);
88512539 5108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5109 result = PCI_ERS_RESULT_RECOVERED;
5110 }
5111
5112 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5113 if (err) {
5114 dev_err(&pdev->dev,
5115 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5116 /* non-fatal, continue */
5117 }
9a799d71 5118
6fabd715 5119 return result;
9a799d71
AK		 5120}
5121
5122/**
5123 * ixgbe_io_resume - called when traffic can start flowing again.
5124 * @pdev: Pointer to PCI device
5125 *
5126 * This callback is called when the error recovery driver tells us that
5127 * its OK to resume normal operation.
5128 */
5129static void ixgbe_io_resume(struct pci_dev *pdev)
5130{
5131 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5133
5134 if (netif_running(netdev)) {
5135 if (ixgbe_up(adapter)) {
5136 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5137 return;
5138 }
5139 }
5140
5141 netif_device_attach(netdev);
9a799d71
AK		 5142}
5143
5144static struct pci_error_handlers ixgbe_err_handler = {
5145 .error_detected = ixgbe_io_error_detected,
5146 .slot_reset = ixgbe_io_slot_reset,
5147 .resume = ixgbe_io_resume,
5148};
5149
5150static struct pci_driver ixgbe_driver = {
5151 .name = ixgbe_driver_name,
5152 .id_table = ixgbe_pci_tbl,
5153 .probe = ixgbe_probe,
5154 .remove = __devexit_p(ixgbe_remove),
5155#ifdef CONFIG_PM
5156 .suspend = ixgbe_suspend,
5157 .resume = ixgbe_resume,
5158#endif
5159 .shutdown = ixgbe_shutdown,
5160 .err_handler = &ixgbe_err_handler
5161};
5162
5163/**
5164 * ixgbe_init_module - Driver Registration Routine
5165 *
5166 * ixgbe_init_module is the first routine called when the driver is
5167 * loaded. All it does is register with the PCI subsystem.
5168 **/
5169static int __init ixgbe_init_module(void)
5170{
5171 int ret;
5172 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5173 ixgbe_driver_string, ixgbe_driver_version);
5174
5175 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5176
5dd2d332 5177#ifdef CONFIG_IXGBE_DCA
bd0362dd 5178 dca_register_notify(&dca_notifier);
bd0362dd 5179#endif
5dd2d332 5180
9a799d71
AK		 5181 ret = pci_register_driver(&ixgbe_driver);
5182 return ret;
5183}
b4617240 5184
9a799d71
AK		 5185module_init(ixgbe_init_module);
5186
5187/**
5188 * ixgbe_exit_module - Driver Exit Cleanup Routine
5189 *
5190 * ixgbe_exit_module is called just before the driver is removed
5191 * from memory.
5192 **/
5193static void __exit ixgbe_exit_module(void)
5194{
5dd2d332 5195#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5196 dca_unregister_notify(&dca_notifier);
5197#endif
9a799d71
AK		 5198 pci_unregister_driver(&ixgbe_driver);
5199}
bd0362dd 5200
5dd2d332 5201#ifdef CONFIG_IXGBE_DCA
bd0362dd 5202static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5203 void *p)
bd0362dd
JC		 5204{
5205 int ret_val;
5206
5207 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5208 __ixgbe_notify_dca);
bd0362dd
JC		 5209
5210 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5211}
b453368d 5212
5dd2d332 5213#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5214#ifdef DEBUG
5215/**
5216 * ixgbe_get_hw_dev_name - return device name string
5217 * used by hardware layer to print debugging information
5218 **/
5219char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5220{
5221 struct ixgbe_adapter *adapter = hw->back;
5222 return adapter->netdev->name;
5223}
bd0362dd 5224
b453368d 5225#endif
9a799d71
AK		 5226module_exit(ixgbe_exit_module);
5227
5228/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree