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drivers/net/ixgbe/ixgbe_main.c: Checkpatch cleanups
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 54
99faf68e 55#define DRV_VERSION "2.0.84-k2"
9c8eb720 56const char ixgbe_driver_version[] = DRV_VERSION;
8c47eaa7 57static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
9a799d71
AK		 58
59static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 60 [board_82598] = &ixgbe_82598_info,
e8e26350 61 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 62};
63
64/* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
a3aa1884 72static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
9a799d71 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 78 board_82598 },
0befdb3e
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
3845bec0
PWJ		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 84 board_82598 },
8d792cd9
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
b95f5fcb
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
2f21bdd3
DS		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
e8e26350
PW		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
1fcf03e6
PWJ		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
74757d49
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
38ad1c8e
DS		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
dbfec662
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
8911184f
PWJ		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
119fc60a
MC		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
312eb931
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
9a799d71
AK		 115
116 /* required last entry */
117 {0, }
118};
119MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
5dd2d332 121#ifdef CONFIG_IXGBE_DCA
bd0362dd 122static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 123 void *p);
bd0362dd
JC		 124static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128};
129#endif
130
1cdd1ec8
GR		 131#ifdef CONFIG_PCI_IOV
132static unsigned int max_vfs;
133module_param(max_vfs, uint, 0);
e8e9f696
JP		 134MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 136#endif /* CONFIG_PCI_IOV */
137
9a799d71
AK		 138MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140MODULE_LICENSE("GPL");
141MODULE_VERSION(DRV_VERSION);
142
143#define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
1cdd1ec8
GR		 145static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146{
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152#ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155#endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
e8e9f696
JP		 172
173 kfree(adapter->vfinfo);
1cdd1ec8
GR		 174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178}
179
dcd79aeb
TI		 180struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183};
184
185static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215};
216
217
218/*
219 * ixgbe_regdump - register printout routine
220 */
221static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222{
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298}
299
300/*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303static void ixgbe_dump(struct ixgbe_adapter *adapter)
304{
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 388 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 469 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515exit:
516 return;
517}
518
5eba3699
AV		 519static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520{
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 527}
528
529static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530{
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 537}
9a799d71 538
e8e26350
PW		 539/*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 548 u8 queue, u8 msix_vector)
9a799d71
AK		 549{
550 u32 ivar, index;
e8e26350
PW		 551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
9a799d71
AK		 586}
587
fe49f04a 588static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 589 u64 qmask)
fe49f04a
AD		 590{
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602}
603
84418e3b 604void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
e8e9f696
JP		 605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
9a799d71 607{
e5a43549
AD		 608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
1b507730 610 dma_unmap_page(&adapter->pdev->dev,
e5a43549
AD		 611 tx_buffer_info->dma,
612 tx_buffer_info->length,
1b507730 613 DMA_TO_DEVICE);
e5a43549 614 else
1b507730 615 dma_unmap_single(&adapter->pdev->dev,
e5a43549
AD		 616 tx_buffer_info->dma,
617 tx_buffer_info->length,
1b507730 618 DMA_TO_DEVICE);
e5a43549
AD		 619 tx_buffer_info->dma = 0;
620 }
9a799d71
AK		 621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
44df32c5 625 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 626 /* tx_buffer_info must be completely set up in the transmit path */
627}
628
26f23d82 629/**
7483d9dd 630 * ixgbe_tx_xon_state - check the tx ring xon state
26f23d82
YZ		 631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
7483d9dd 637 * Returns : true if in xon state (currently not paused)
26f23d82 638 */
7483d9dd 639static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
e8e9f696 640 struct ixgbe_ring *tx_ring)
26f23d82 641{
26f23d82
YZ		 642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644#ifdef CONFIG_IXGBE_DCB
ca739481 645 if (adapter->dcb_cfg.pfc_mode_enable) {
30b76832 646 int tc;
26f23d82
YZ		 647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
6837e895
PW		 650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
26f23d82
YZ		 652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
6837e895
PW		 654 break;
655 case ixgbe_mac_82599EB:
26f23d82
YZ		 656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
6837e895
PW		 674 break;
675 default:
676 tc = 0;
26f23d82
YZ		 677 }
678 txoff <<= tc;
679 }
680#endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682}
683
9a799d71 684static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
e8e9f696
JP		 685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
9a799d71 687{
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
9a799d71 690 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 691 * check with the clearing of time_stamp and movement of eop */
9a799d71 692 adapter->detect_tx_hung = false;
44df32c5 693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71 694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
7483d9dd 695 ixgbe_tx_xon_state(adapter, tx_ring)) {
9a799d71 696 /* detected Tx unit hang */
e01c31a5 697 union ixgbe_adv_tx_desc *tx_desc;
31f05a2d 698 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
396e799c 699 e_err(drv, "Detected Tx Unit Hang\n"
849c4542
ET		 700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 712 return true;
713 }
714
715 return false;
716}
717
b4617240
PW		 718#define IXGBE_MAX_TXD_PWR 14
719#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 720
721/* Tx Descriptors needed, worst case */
722#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 726
e01c31a5
JB		 727static void ixgbe_tx_timeout(struct net_device *netdev);
728
9a799d71
AK		 729/**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 731 * @q_vector: structure containing interrupt and ring information
e01c31a5 732 * @tx_ring: tx ring to clean
9a799d71 733 **/
fe49f04a 734static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 735 struct ixgbe_ring *tx_ring)
9a799d71 736{
fe49f04a 737 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 738 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 743
744 i = tx_ring->next_to_clean;
12207e49 745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 746 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 749 (count < tx_ring->work_limit)) {
12207e49 750 bool cleaned = false;
2d0bb1c1 751 rmb(); /* read buffer_info after eop_desc */
12207e49
PWJ		 752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
31f05a2d 754 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 756 cleaned = (i == eop);
e01c31a5 757 skb = tx_buffer_info->skb;
9a799d71 758
12207e49 759 if (cleaned && skb) {
e092be60 760 unsigned int segs, bytecount;
3d8fd385 761 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 762
763 /* gso_segs is currently only valid for tcp */
e092be60 764 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 765#ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776#endif /* IXGBE_FCOE */
e092be60 777 /* multiply data chunks by size of headers */
3d8fd385 778 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 779 total_packets += segs;
780 total_bytes += bytecount;
e092be60 781 }
e01c31a5 782
9a799d71 783 ixgbe_unmap_and_free_tx_resource(adapter,
e8e9f696 784 tx_buffer_info);
9a799d71 785
12207e49
PWJ		 786 tx_desc->wb.status = 0;
787
9a799d71
AK		 788 i++;
789 if (i == tx_ring->count)
790 i = 0;
e01c31a5 791 }
12207e49
PWJ		 792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 794 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 795 }
796
9a799d71
AK		 797 tx_ring->next_to_clean = i;
798
e092be60 799#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5 800 if (unlikely(count && netif_carrier_ok(netdev) &&
e8e9f696 801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
30eba97a
AV		 806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 809 ++tx_ring->restart_queue;
30eba97a 810 }
e092be60 811 }
9a799d71 812
e01c31a5
JB		 813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
396e799c
ET		 816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
e01c31a5
JB		 818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
9a799d71 821
e01c31a5 822 /* re-arm the interrupt */
fe49f04a
AD		 823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 825
e01c31a5
JB		 826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
e01c31a5 828 tx_ring->stats.packets += total_packets;
12207e49 829 tx_ring->stats.bytes += total_bytes;
9a1a69ad 830 return (count < tx_ring->work_limit);
9a799d71
AK		 831}
832
5dd2d332 833#ifdef CONFIG_IXGBE_DCA
bd0362dd 834static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
e8e9f696 835 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 836{
837 u32 rxctrl;
838 int cpu = get_cpu();
4a0b9ca0 839 int q = rx_ring->reg_idx;
bd0362dd 840
3a581073 841 if (rx_ring->cpu != cpu) {
bd0362dd 842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
e8e26350 850 }
bd0362dd
JC		 851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e9f696 855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 857 rx_ring->cpu = cpu;
bd0362dd
JC		 858 }
859 put_cpu();
860}
861
862static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
e8e9f696 863 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 864{
865 u32 txctrl;
866 int cpu = get_cpu();
4a0b9ca0 867 int q = tx_ring->reg_idx;
ee5f784a 868 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 869
3a581073 870 if (tx_ring->cpu != cpu) {
e8e26350 871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
ee5f784a 872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
ee5f784a
DS		 875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
e8e26350 877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
ee5f784a 878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
e8e26350
PW		 879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
e8e9f696 881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
ee5f784a
DS		 882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
e8e26350 884 }
3a581073 885 tx_ring->cpu = cpu;
bd0362dd
JC		 886 }
887 put_cpu();
888}
889
890static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891{
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
e35ec126
AD		 897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
bd0362dd 900 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
bd0362dd
JC		 903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
bd0362dd
JC		 907 }
908}
909
910static int __ixgbe_notify_dca(struct device *dev, void *data)
911{
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
652f093f 921 if (dca_add_requester(dev) == 0) {
96b0e0f6 922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
652f093f 936 return 0;
bd0362dd
JC		 937}
938
5dd2d332 939#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 940/**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
177db6ff
MC		 944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
9a799d71 947 **/
78b6f4ce 948static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 952{
78b6f4ce
HX		 953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 957
182ff8df 958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 961 else
78b6f4ce 962 napi_gro_receive(napi, skb);
177db6ff 963 } else {
8a62babf 964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
9a799d71
AK		 968 }
969}
970
e59bd25d
AV		 971/**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
9a799d71 977static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
9a799d71 980{
8bae1b2b
DS		 981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
bc8acf2c 983 skb_checksum_none_assert(skb);
9a799d71 984
712744be
JB		 985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 987 return;
e59bd25d
AV		 988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 992 adapter->hw_csum_rx_error++;
993 return;
994 }
e59bd25d
AV		 995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
e59bd25d
AV		 1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
9a799d71 1014 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1016}
1017
e8e26350 1018static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
e8e9f696 1019 struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1020{
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029}
1030
9a799d71
AK		 1031/**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
84418e3b 1035void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
9a799d71 1038{
d716a7d8 1039 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1042 struct ixgbe_rx_buffer *bi;
9a799d71 1043 unsigned int i;
d716a7d8 1044 unsigned int bufsz = rx_ring->rx_buf_len;
9a799d71
AK		 1045
1046 i = rx_ring->next_to_use;
3a581073 1047 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1048
1049 while (cleaned_count--) {
31f05a2d 1050 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1051
762f4c57 1052 if (!bi->page_dma &&
6e455b89 1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 1054 if (!bi->page) {
d716a7d8 1055 bi->page = netdev_alloc_page(netdev);
762f4c57
JB		 1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 1064 }
762f4c57 1065
1b507730 1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
e8e9f696
JP		 1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1b507730 1069 DMA_FROM_DEVICE);
9a799d71
AK		 1070 }
1071
3a581073 1072 if (!bi->skb) {
d716a7d8
AD		 1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
9a799d71
AK		 1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
d716a7d8
AD		 1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
9a799d71 1084
d716a7d8
AD		 1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
e8e9f696 1088 rx_ring->rx_buf_len,
1b507730 1089 DMA_FROM_DEVICE);
9a799d71
AK		 1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
6e455b89 1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1096 } else {
3a581073 1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1098 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1099 }
1100
1101 i++;
1102 if (i == rx_ring->count)
1103 i = 0;
3a581073 1104 bi = &rx_ring->rx_buffer_info[i];
9a799d71 1105 }
7c6e0a43 1106
9a799d71
AK		 1107no_buffers:
1108 if (rx_ring->next_to_use != i) {
1109 rx_ring->next_to_use = i;
1110 if (i-- == 0)
1111 i = (rx_ring->count - 1);
1112
e8e26350 1113 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 1114 }
1115}
1116
7c6e0a43
JB		 1117static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1118{
1119 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1120}
1121
1122static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1123{
1124 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1125}
1126
f8212f97
AD		 1127static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1128{
1129 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
e8e9f696
JP		 1130 IXGBE_RXDADV_RSCCNT_MASK) >>
1131 IXGBE_RXDADV_RSCCNT_SHIFT;
f8212f97
AD		 1132}
1133
1134/**
1135 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1136 * @skb: pointer to the last skb in the rsc queue
94b982b2 1137 * @count: pointer to number of packets coalesced in this context
f8212f97
AD		 1138 *
1139 * This function changes a queue full of hw rsc buffers into a completed
1140 * packet. It uses the ->prev pointers to find the first packet and then
1141 * turns it into the frag list owner.
1142 **/
94b982b2 1143static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
e8e9f696 1144 u64 *count)
f8212f97
AD		 1145{
1146 unsigned int frag_list_size = 0;
1147
1148 while (skb->prev) {
1149 struct sk_buff *prev = skb->prev;
1150 frag_list_size += skb->len;
1151 skb->prev = NULL;
1152 skb = prev;
94b982b2 1153 *count += 1;
f8212f97
AD		 1154 }
1155
1156 skb_shinfo(skb)->frag_list = skb->next;
1157 skb->next = NULL;
1158 skb->len += frag_list_size;
1159 skb->data_len += frag_list_size;
1160 skb->truesize += frag_list_size;
1161 return skb;
1162}
1163
43634e82
MC		 1164struct ixgbe_rsc_cb {
1165 dma_addr_t dma;
e8171aaa 1166 bool delay_unmap;
43634e82
MC		 1167};
1168
1169#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1170
78b6f4ce 1171static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1172 struct ixgbe_ring *rx_ring,
1173 int *work_done, int work_to_do)
9a799d71 1174{
78b6f4ce 1175 struct ixgbe_adapter *adapter = q_vector->adapter;
2d86f139 1176 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 1177 struct pci_dev *pdev = adapter->pdev;
1178 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1179 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1180 struct sk_buff *skb;
f8212f97 1181 unsigned int i, rsc_count = 0;
7c6e0a43 1182 u32 len, staterr;
177db6ff
MC		 1183 u16 hdr_info;
1184 bool cleaned = false;
9a799d71 1185 int cleaned_count = 0;
d2f4fbe2 1186 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 1187#ifdef IXGBE_FCOE
1188 int ddp_bytes = 0;
1189#endif /* IXGBE_FCOE */
9a799d71
AK		 1190
1191 i = rx_ring->next_to_clean;
31f05a2d 1192 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71
AK		 1193 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1194 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1195
1196 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1197 u32 upper_len = 0;
9a799d71
AK		 1198 if (*work_done >= work_to_do)
1199 break;
1200 (*work_done)++;
1201
3c945e5b 1202 rmb(); /* read descriptor and rx_buffer_info after status DD */
6e455b89 1203 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 1204 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1205 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 1206 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71 1207 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
0b746e08
SN		 1208 if ((len > IXGBE_RX_HDR_SIZE) ||
1209 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1210 len = IXGBE_RX_HDR_SIZE;
7c6e0a43 1211 } else {
9a799d71 1212 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 1213 }
9a799d71
AK		 1214
1215 cleaned = true;
1216 skb = rx_buffer_info->skb;
7ca3bc58 1217 prefetch(skb->data);
9a799d71
AK		 1218 rx_buffer_info->skb = NULL;
1219
21fa4e66 1220 if (rx_buffer_info->dma) {
43634e82
MC		 1221 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1222 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
e8171aaa 1223 (!(skb->prev))) {
43634e82
MC		 1224 /*
1225 * When HWRSC is enabled, delay unmapping
1226 * of the first packet. It carries the
1227 * header information, HW may still
1228 * access the header after the writeback.
1229 * Only unmap it when EOP is reached
1230 */
e8171aaa 1231 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1232 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1233 } else {
1b507730 1234 dma_unmap_single(&pdev->dev,
e8e9f696
JP		 1235 rx_buffer_info->dma,
1236 rx_ring->rx_buf_len,
1237 DMA_FROM_DEVICE);
e8171aaa 1238 }
4f57ca6e 1239 rx_buffer_info->dma = 0;
9a799d71
AK		 1240 skb_put(skb, len);
1241 }
1242
1243 if (upper_len) {
1b507730
NN		 1244 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1245 PAGE_SIZE / 2, DMA_FROM_DEVICE);
9a799d71
AK		 1246 rx_buffer_info->page_dma = 0;
1247 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1248 rx_buffer_info->page,
1249 rx_buffer_info->page_offset,
1250 upper_len);
762f4c57
JB		 1251
1252 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1253 (page_count(rx_buffer_info->page) != 1))
1254 rx_buffer_info->page = NULL;
1255 else
1256 get_page(rx_buffer_info->page);
9a799d71
AK		 1257
1258 skb->len += upper_len;
1259 skb->data_len += upper_len;
1260 skb->truesize += upper_len;
1261 }
1262
1263 i++;
1264 if (i == rx_ring->count)
1265 i = 0;
9a799d71 1266
31f05a2d 1267 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1268 prefetch(next_rxd);
9a799d71 1269 cleaned_count++;
f8212f97 1270
0c19d6af 1271 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 1272 rsc_count = ixgbe_get_rsc_count(rx_desc);
1273
1274 if (rsc_count) {
1275 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1276 IXGBE_RXDADV_NEXTP_SHIFT;
1277 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1278 } else {
1279 next_buffer = &rx_ring->rx_buffer_info[i];
1280 }
1281
9a799d71 1282 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97 1283 if (skb->prev)
e8e9f696
JP		 1284 skb = ixgbe_transform_rsc_queue(skb,
1285 &(rx_ring->rsc_count));
94b982b2 1286 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
e8171aaa 1287 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1b507730
NN		 1288 dma_unmap_single(&pdev->dev,
1289 IXGBE_RSC_CB(skb)->dma,
e8e9f696 1290 rx_ring->rx_buf_len,
1b507730 1291 DMA_FROM_DEVICE);
fd3686a8 1292 IXGBE_RSC_CB(skb)->dma = 0;
e8171aaa 1293 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 1294 }
94b982b2 1295 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
e8e9f696
JP		 1296 rx_ring->rsc_count +=
1297 skb_shinfo(skb)->nr_frags;
94b982b2
MC		 1298 else
1299 rx_ring->rsc_count++;
1300 rx_ring->rsc_flush++;
1301 }
9a799d71
AK		 1302 rx_ring->stats.packets++;
1303 rx_ring->stats.bytes += skb->len;
1304 } else {
6e455b89 1305 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 1306 rx_buffer_info->skb = next_buffer->skb;
1307 rx_buffer_info->dma = next_buffer->dma;
1308 next_buffer->skb = skb;
1309 next_buffer->dma = 0;
1310 } else {
1311 skb->next = next_buffer->skb;
1312 skb->next->prev = skb;
1313 }
7ca3bc58 1314 rx_ring->non_eop_descs++;
9a799d71
AK		 1315 goto next_desc;
1316 }
1317
1318 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1319 dev_kfree_skb_irq(skb);
1320 goto next_desc;
1321 }
1322
8bae1b2b 1323 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 1324
1325 /* probably a little skewed due to removing CRC */
1326 total_rx_bytes += skb->len;
1327 total_rx_packets++;
1328
74ce8dd2 1329 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 1330#ifdef IXGBE_FCOE
1331 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1332 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1333 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1334 if (!ddp_bytes)
332d4a7d 1335 goto next_desc;
3d8fd385 1336 }
332d4a7d 1337#endif /* IXGBE_FCOE */
fdaff1ce 1338 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1339
1340next_desc:
1341 rx_desc->wb.upper.status_error = 0;
1342
1343 /* return some buffers to hardware, one at a time is too slow */
1344 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1345 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1346 cleaned_count = 0;
1347 }
1348
1349 /* use prefetched values */
1350 rx_desc = next_rxd;
f8212f97 1351 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 1352
1353 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1354 }
1355
9a799d71
AK		 1356 rx_ring->next_to_clean = i;
1357 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1358
1359 if (cleaned_count)
1360 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1361
3d8fd385
YZ		 1362#ifdef IXGBE_FCOE
1363 /* include DDPed FCoE data */
1364 if (ddp_bytes > 0) {
1365 unsigned int mss;
1366
1367 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1368 sizeof(struct fc_frame_header) -
1369 sizeof(struct fcoe_crc_eof);
1370 if (mss > 512)
1371 mss &= ~511;
1372 total_rx_bytes += ddp_bytes;
1373 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1374 }
1375#endif /* IXGBE_FCOE */
1376
f494e8fa
AV		 1377 rx_ring->total_packets += total_rx_packets;
1378 rx_ring->total_bytes += total_rx_bytes;
2d86f139
AK		 1379 netdev->stats.rx_bytes += total_rx_bytes;
1380 netdev->stats.rx_packets += total_rx_packets;
f494e8fa 1381
9a799d71
AK		 1382 return cleaned;
1383}
1384
021230d4 1385static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1386/**
1387 * ixgbe_configure_msix - Configure MSI-X hardware
1388 * @adapter: board private structure
1389 *
1390 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1391 * interrupts.
1392 **/
1393static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1394{
021230d4
AV		 1395 struct ixgbe_q_vector *q_vector;
1396 int i, j, q_vectors, v_idx, r_idx;
1397 u32 mask;
9a799d71 1398
021230d4 1399 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1400
4df10466
JB		 1401 /*
1402 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1403 * corresponding register.
1404 */
1405 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1406 q_vector = adapter->q_vector[v_idx];
984b3f57 1407 /* XXX for_each_set_bit(...) */
021230d4 1408 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1409 adapter->num_rx_queues);
021230d4
AV		 1410
1411 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1412 j = adapter->rx_ring[r_idx]->reg_idx;
e8e26350 1413 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 1414 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1415 adapter->num_rx_queues,
1416 r_idx + 1);
021230d4
AV		 1417 }
1418 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1419 adapter->num_tx_queues);
021230d4
AV		 1420
1421 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1422 j = adapter->tx_ring[r_idx]->reg_idx;
e8e26350 1423 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 1424 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1425 adapter->num_tx_queues,
1426 r_idx + 1);
021230d4
AV		 1427 }
1428
021230d4 1429 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1430 /* tx only */
1431 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1432 else if (q_vector->rxr_count)
f7554a2b
NS		 1433 /* rx or mixed */
1434 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1435
fe49f04a 1436 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1437 }
1438
e8e26350
PW		 1439 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1440 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1441 v_idx);
e8e26350
PW		 1442 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1443 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 1444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1445
41fb9248 1446 /* set up to autoclear timer, and the vectors */
021230d4 1447 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1448 if (adapter->num_vfs)
1449 mask &= ~(IXGBE_EIMS_OTHER |
1450 IXGBE_EIMS_MAILBOX |
1451 IXGBE_EIMS_LSC);
1452 else
1453 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1454 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1455}
1456
f494e8fa
AV		 1457enum latency_range {
1458 lowest_latency = 0,
1459 low_latency = 1,
1460 bulk_latency = 2,
1461 latency_invalid = 255
1462};
1463
1464/**
1465 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1466 * @adapter: pointer to adapter
1467 * @eitr: eitr setting (ints per sec) to give last timeslice
1468 * @itr_setting: current throttle rate in ints/second
1469 * @packets: the number of packets during this measurement interval
1470 * @bytes: the number of bytes during this measurement interval
1471 *
1472 * Stores a new ITR value based on packets and byte
1473 * counts during the last interrupt. The advantage of per interrupt
1474 * computation is faster updates and more accurate ITR for the current
1475 * traffic pattern. Constants in this function were computed
1476 * based on theoretical maximum wire speed and thresholds were set based
1477 * on testing data as well as attempting to minimize response time
1478 * while increasing bulk throughput.
1479 * this functionality is controlled by the InterruptThrottleRate module
1480 * parameter (see ixgbe_param.c)
1481 **/
1482static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1483 u32 eitr, u8 itr_setting,
1484 int packets, int bytes)
f494e8fa
AV		 1485{
1486 unsigned int retval = itr_setting;
1487 u32 timepassed_us;
1488 u64 bytes_perint;
1489
1490 if (packets == 0)
1491 goto update_itr_done;
1492
1493
1494 /* simple throttlerate management
1495 * 0-20MB/s lowest (100000 ints/s)
1496 * 20-100MB/s low (20000 ints/s)
1497 * 100-1249MB/s bulk (8000 ints/s)
1498 */
1499 /* what was last interrupt timeslice? */
1500 timepassed_us = 1000000/eitr;
1501 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1502
1503 switch (itr_setting) {
1504 case lowest_latency:
1505 if (bytes_perint > adapter->eitr_low)
1506 retval = low_latency;
1507 break;
1508 case low_latency:
1509 if (bytes_perint > adapter->eitr_high)
1510 retval = bulk_latency;
1511 else if (bytes_perint <= adapter->eitr_low)
1512 retval = lowest_latency;
1513 break;
1514 case bulk_latency:
1515 if (bytes_perint <= adapter->eitr_high)
1516 retval = low_latency;
1517 break;
1518 }
1519
1520update_itr_done:
1521 return retval;
1522}
1523
509ee935
JB		 1524/**
1525 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1526 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1527 *
1528 * This function is made to be called by ethtool and by the driver
1529 * when it needs to update EITR registers at runtime. Hardware
1530 * specific quirks/differences are taken care of here.
1531 */
fe49f04a 1532void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1533{
fe49f04a 1534 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1535 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1536 int v_idx = q_vector->v_idx;
1537 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1538
509ee935
JB		 1539 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1540 /* must write high and low 16 bits to reset counter */
1541 itr_reg |= (itr_reg << 16);
1542 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f8d1dcaf
JB		 1543 /*
1544 * 82599 can support a value of zero, so allow it for
1545 * max interrupt rate, but there is an errata where it can
1546 * not be zero with RSC
1547 */
1548 if (itr_reg == 8 &&
1549 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1550 itr_reg = 0;
1551
509ee935
JB		 1552 /*
1553 * set the WDIS bit to not clear the timer bits and cause an
1554 * immediate assertion of the interrupt
1555 */
1556 itr_reg |= IXGBE_EITR_CNT_WDIS;
1557 }
1558 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1559}
1560
f494e8fa
AV		 1561static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1562{
1563 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1564 u32 new_itr;
1565 u8 current_itr, ret_itr;
fe49f04a 1566 int i, r_idx;
f494e8fa
AV		 1567 struct ixgbe_ring *rx_ring, *tx_ring;
1568
1569 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1570 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1571 tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1572 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1573 q_vector->tx_itr,
1574 tx_ring->total_packets,
1575 tx_ring->total_bytes);
f494e8fa
AV		 1576 /* if the result for this queue would decrease interrupt
1577 * rate for this vector then use that result */
30efa5a3 1578 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1579 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1580 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1581 r_idx + 1);
f494e8fa
AV		 1582 }
1583
1584 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1585 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1586 rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1587 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1588 q_vector->rx_itr,
1589 rx_ring->total_packets,
1590 rx_ring->total_bytes);
f494e8fa
AV		 1591 /* if the result for this queue would decrease interrupt
1592 * rate for this vector then use that result */
30efa5a3 1593 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1594 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1595 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1596 r_idx + 1);
f494e8fa
AV		 1597 }
1598
30efa5a3 1599 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1600
1601 switch (current_itr) {
1602 /* counts and packets in update_itr are dependent on these numbers */
1603 case lowest_latency:
1604 new_itr = 100000;
1605 break;
1606 case low_latency:
1607 new_itr = 20000; /* aka hwitr = ~200 */
1608 break;
1609 case bulk_latency:
1610 default:
1611 new_itr = 8000;
1612 break;
1613 }
1614
1615 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1616 /* do an exponential smoothing */
1617 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1618
1619 /* save the algorithm value here, not the smoothed one */
1620 q_vector->eitr = new_itr;
fe49f04a
AD		 1621
1622 ixgbe_write_eitr(q_vector);
f494e8fa 1623 }
f494e8fa
AV		 1624}
1625
119fc60a
MC		 1626/**
1627 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1628 * @work: pointer to work_struct containing our data
1629 **/
1630static void ixgbe_check_overtemp_task(struct work_struct *work)
1631{
1632 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1633 struct ixgbe_adapter,
1634 check_overtemp_task);
119fc60a
MC		 1635 struct ixgbe_hw *hw = &adapter->hw;
1636 u32 eicr = adapter->interrupt_event;
1637
1638 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1639 switch (hw->device_id) {
1640 case IXGBE_DEV_ID_82599_T3_LOM: {
1641 u32 autoneg;
1642 bool link_up = false;
1643
1644 if (hw->mac.ops.check_link)
1645 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1646
1647 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1648 (eicr & IXGBE_EICR_LSC))
1649 /* Check if this is due to overtemp */
1650 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1651 break;
1652 }
1653 return;
1654 default:
1655 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1656 return;
1657 break;
1658 }
396e799c
ET		 1659 e_crit(drv, "Network adapter has been stopped because it has "
1660 "over heated. Restart the computer. If the problem "
849c4542
ET		 1661 "persists, power off the system and replace the "
1662 "adapter\n");
119fc60a
MC		 1663 /* write to clear the interrupt */
1664 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1665 }
1666}
1667
0befdb3e
JB		 1668static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1669{
1670 struct ixgbe_hw *hw = &adapter->hw;
1671
1672 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1673 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1674 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1675 /* write to clear the interrupt */
1676 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1677 }
1678}
cf8280ee 1679
e8e26350
PW		 1680static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1681{
1682 struct ixgbe_hw *hw = &adapter->hw;
1683
1684 if (eicr & IXGBE_EICR_GPI_SDP1) {
1685 /* Clear the interrupt */
1686 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1687 schedule_work(&adapter->multispeed_fiber_task);
1688 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1689 /* Clear the interrupt */
1690 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1691 schedule_work(&adapter->sfp_config_module_task);
1692 } else {
1693 /* Interrupt isn't for us... */
1694 return;
1695 }
1696}
1697
cf8280ee
JB		 1698static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1699{
1700 struct ixgbe_hw *hw = &adapter->hw;
1701
1702 adapter->lsc_int++;
1703 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1704 adapter->link_check_timeout = jiffies;
1705 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1707 IXGBE_WRITE_FLUSH(hw);
cf8280ee
JB		 1708 schedule_work(&adapter->watchdog_task);
1709 }
1710}
1711
9a799d71
AK		 1712static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1713{
1714 struct net_device *netdev = data;
1715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1716 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1717 u32 eicr;
1718
1719 /*
1720 * Workaround for Silicon errata. Use clear-by-write instead
1721 * of clear-by-read. Reading with EICS will return the
1722 * interrupt causes without clearing, which later be done
1723 * with the write to EICR.
1724 */
1725 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1726 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1727
cf8280ee
JB		 1728 if (eicr & IXGBE_EICR_LSC)
1729 ixgbe_check_lsc(adapter);
d4f80882 1730
1cdd1ec8
GR		 1731 if (eicr & IXGBE_EICR_MAILBOX)
1732 ixgbe_msg_task(adapter);
1733
e8e26350
PW		 1734 if (hw->mac.type == ixgbe_mac_82598EB)
1735 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1736
c4cf55e5 1737 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1738 ixgbe_check_sfp_event(adapter, eicr);
119fc60a
MC		 1739 adapter->interrupt_event = eicr;
1740 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1741 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1742 schedule_work(&adapter->check_overtemp_task);
c4cf55e5
PWJ		 1743
1744 /* Handle Flow Director Full threshold interrupt */
1745 if (eicr & IXGBE_EICR_FLOW_DIR) {
1746 int i;
1747 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1748 /* Disable transmits before FDIR Re-initialization */
1749 netif_tx_stop_all_queues(netdev);
1750 for (i = 0; i < adapter->num_tx_queues; i++) {
1751 struct ixgbe_ring *tx_ring =
e8e9f696 1752 adapter->tx_ring[i];
c4cf55e5 1753 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 1754 &tx_ring->reinit_state))
c4cf55e5
PWJ		 1755 schedule_work(&adapter->fdir_reinit_task);
1756 }
1757 }
1758 }
d4f80882
AV		 1759 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1760 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1761
1762 return IRQ_HANDLED;
1763}
1764
fe49f04a
AD		 1765static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1766 u64 qmask)
1767{
1768 u32 mask;
1769
1770 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1771 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1773 } else {
1774 mask = (qmask & 0xFFFFFFFF);
1775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1776 mask = (qmask >> 32);
1777 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1778 }
1779 /* skip the flush */
1780}
1781
1782static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1783 u64 qmask)
fe49f04a
AD		 1784{
1785 u32 mask;
1786
1787 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1788 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1790 } else {
1791 mask = (qmask & 0xFFFFFFFF);
1792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1793 mask = (qmask >> 32);
1794 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1795 }
1796 /* skip the flush */
1797}
1798
9a799d71
AK		 1799static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1800{
021230d4
AV		 1801 struct ixgbe_q_vector *q_vector = data;
1802 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1803 struct ixgbe_ring *tx_ring;
021230d4
AV		 1804 int i, r_idx;
1805
1806 if (!q_vector->txr_count)
1807 return IRQ_HANDLED;
1808
1809 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1810 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1811 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 1812 tx_ring->total_bytes = 0;
1813 tx_ring->total_packets = 0;
021230d4 1814 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1815 r_idx + 1);
021230d4 1816 }
9a799d71 1817
9b471446 1818 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1819 napi_schedule(&q_vector->napi);
1820
9a799d71
AK		 1821 return IRQ_HANDLED;
1822}
1823
021230d4
AV		 1824/**
1825 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1826 * @irq: unused
1827 * @data: pointer to our q_vector struct for this interrupt vector
1828 **/
9a799d71
AK		 1829static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1830{
021230d4
AV		 1831 struct ixgbe_q_vector *q_vector = data;
1832 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1833 struct ixgbe_ring *rx_ring;
021230d4 1834 int r_idx;
30efa5a3 1835 int i;
021230d4
AV		 1836
1837 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3 1838 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1839 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 1840 rx_ring->total_bytes = 0;
1841 rx_ring->total_packets = 0;
1842 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1843 r_idx + 1);
30efa5a3
JB		 1844 }
1845
021230d4
AV		 1846 if (!q_vector->rxr_count)
1847 return IRQ_HANDLED;
1848
021230d4 1849 /* disable interrupts on this vector only */
9b471446 1850 /* EIAM disabled interrupts (on this vector) for us */
288379f0 1851 napi_schedule(&q_vector->napi);
021230d4
AV		 1852
1853 return IRQ_HANDLED;
1854}
1855
1856static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1857{
91281fd3
AD		 1858 struct ixgbe_q_vector *q_vector = data;
1859 struct ixgbe_adapter *adapter = q_vector->adapter;
1860 struct ixgbe_ring *ring;
1861 int r_idx;
1862 int i;
1863
1864 if (!q_vector->txr_count && !q_vector->rxr_count)
1865 return IRQ_HANDLED;
1866
1867 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1868 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1869 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1870 ring->total_bytes = 0;
1871 ring->total_packets = 0;
1872 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1873 r_idx + 1);
91281fd3
AD		 1874 }
1875
1876 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1877 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1878 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 1879 ring->total_bytes = 0;
1880 ring->total_packets = 0;
1881 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1882 r_idx + 1);
91281fd3
AD		 1883 }
1884
9b471446 1885 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1886 napi_schedule(&q_vector->napi);
9a799d71 1887
9a799d71
AK		 1888 return IRQ_HANDLED;
1889}
1890
021230d4
AV		 1891/**
1892 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1893 * @napi: napi struct with our devices info in it
1894 * @budget: amount of work driver is allowed to do this pass, in packets
1895 *
f0848276
JB		 1896 * This function is optimized for cleaning one queue only on a single
1897 * q_vector!!!
021230d4 1898 **/
9a799d71
AK		 1899static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1900{
021230d4 1901 struct ixgbe_q_vector *q_vector =
e8e9f696 1902 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1903 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1904 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1905 int work_done = 0;
021230d4 1906 long r_idx;
9a799d71 1907
021230d4 1908 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1909 rx_ring = adapter->rx_ring[r_idx];
5dd2d332 1910#ifdef CONFIG_IXGBE_DCA
bd0362dd 1911 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1912 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1913#endif
9a799d71 1914
78b6f4ce 1915 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1916
021230d4
AV		 1917 /* If all Rx work done, exit the polling mode */
1918 if (work_done < budget) {
288379f0 1919 napi_complete(napi);
f7554a2b 1920 if (adapter->rx_itr_setting & 1)
f494e8fa 1921 ixgbe_set_itr_msix(q_vector);
9a799d71 1922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1923 ixgbe_irq_enable_queues(adapter,
e8e9f696 1924 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1925 }
1926
1927 return work_done;
1928}
1929
f0848276 1930/**
91281fd3 1931 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1932 * @napi: napi struct with our devices info in it
1933 * @budget: amount of work driver is allowed to do this pass, in packets
1934 *
1935 * This function will clean more than one rx queue associated with a
1936 * q_vector.
1937 **/
91281fd3 1938static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1939{
1940 struct ixgbe_q_vector *q_vector =
e8e9f696 1941 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 1942 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1943 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1944 int work_done = 0, i;
1945 long r_idx;
91281fd3
AD		 1946 bool tx_clean_complete = true;
1947
1948 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 1950 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 1951#ifdef CONFIG_IXGBE_DCA
1952 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1953 ixgbe_update_tx_dca(adapter, ring);
1954#endif
1955 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1956 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1957 r_idx + 1);
91281fd3 1958 }
f0848276
JB		 1959
1960 /* attempt to distribute budget to each queue fairly, but don't allow
1961 * the budget to go below 1 because we'll exit polling */
1962 budget /= (q_vector->rxr_count ?: 1);
1963 budget = max(budget, 1);
1964 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1965 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 1966 ring = adapter->rx_ring[r_idx];
5dd2d332 1967#ifdef CONFIG_IXGBE_DCA
f0848276 1968 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1969 ixgbe_update_rx_dca(adapter, ring);
f0848276 1970#endif
91281fd3 1971 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 1972 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1973 r_idx + 1);
f0848276
JB		 1974 }
1975
1976 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 1977 ring = adapter->rx_ring[r_idx];
f0848276 1978 /* If all Rx work done, exit the polling mode */
7f821875 1979 if (work_done < budget) {
288379f0 1980 napi_complete(napi);
f7554a2b 1981 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1982 ixgbe_set_itr_msix(q_vector);
1983 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 1984 ixgbe_irq_enable_queues(adapter,
e8e9f696 1985 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1986 return 0;
1987 }
1988
1989 return work_done;
1990}
91281fd3
AD		 1991
1992/**
1993 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1994 * @napi: napi struct with our devices info in it
1995 * @budget: amount of work driver is allowed to do this pass, in packets
1996 *
1997 * This function is optimized for cleaning one queue only on a single
1998 * q_vector!!!
1999 **/
2000static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2001{
2002 struct ixgbe_q_vector *q_vector =
e8e9f696 2003 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2004 struct ixgbe_adapter *adapter = q_vector->adapter;
2005 struct ixgbe_ring *tx_ring = NULL;
2006 int work_done = 0;
2007 long r_idx;
2008
2009 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
4a0b9ca0 2010 tx_ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2011#ifdef CONFIG_IXGBE_DCA
2012 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2013 ixgbe_update_tx_dca(adapter, tx_ring);
2014#endif
2015
2016 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2017 work_done = budget;
2018
f7554a2b 2019 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2020 if (work_done < budget) {
2021 napi_complete(napi);
f7554a2b 2022 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2023 ixgbe_set_itr_msix(q_vector);
2024 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2025 ixgbe_irq_enable_queues(adapter,
2026 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2027 }
2028
2029 return work_done;
2030}
2031
021230d4 2032static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2033 int r_idx)
021230d4 2034{
7a921c93
AD		 2035 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2036
2037 set_bit(r_idx, q_vector->rxr_idx);
2038 q_vector->rxr_count++;
021230d4
AV		 2039}
2040
2041static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2042 int t_idx)
021230d4 2043{
7a921c93
AD		 2044 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2045
2046 set_bit(t_idx, q_vector->txr_idx);
2047 q_vector->txr_count++;
021230d4
AV		 2048}
2049
9a799d71 2050/**
021230d4
AV		 2051 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2052 * @adapter: board private structure to initialize
2053 * @vectors: allotted vector count for descriptor rings
9a799d71 2054 *
021230d4
AV		 2055 * This function maps descriptor rings to the queue-specific vectors
2056 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2057 * one vector per ring/queue, but on a constrained vector budget, we
2058 * group the rings as "efficiently" as possible. You would add new
2059 * mapping configurations in here.
9a799d71 2060 **/
021230d4 2061static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
e8e9f696 2062 int vectors)
021230d4
AV		 2063{
2064 int v_start = 0;
2065 int rxr_idx = 0, txr_idx = 0;
2066 int rxr_remaining = adapter->num_rx_queues;
2067 int txr_remaining = adapter->num_tx_queues;
2068 int i, j;
2069 int rqpv, tqpv;
2070 int err = 0;
2071
2072 /* No mapping required if MSI-X is disabled. */
2073 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2074 goto out;
9a799d71 2075
021230d4
AV		 2076 /*
2077 * The ideal configuration...
2078 * We have enough vectors to map one per queue.
2079 */
2080 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2081 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2082 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2083
021230d4
AV		 2084 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2085 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2086
9a799d71 2087 goto out;
021230d4 2088 }
9a799d71 2089
021230d4
AV		 2090 /*
2091 * If we don't have enough vectors for a 1-to-1
2092 * mapping, we'll have to group them so there are
2093 * multiple queues per vector.
2094 */
2095 /* Re-adjusting *qpv takes care of the remainder. */
2096 for (i = v_start; i < vectors; i++) {
2097 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2098 for (j = 0; j < rqpv; j++) {
2099 map_vector_to_rxq(adapter, i, rxr_idx);
2100 rxr_idx++;
2101 rxr_remaining--;
2102 }
2103 }
2104 for (i = v_start; i < vectors; i++) {
2105 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2106 for (j = 0; j < tqpv; j++) {
2107 map_vector_to_txq(adapter, i, txr_idx);
2108 txr_idx++;
2109 txr_remaining--;
9a799d71 2110 }
9a799d71
AK		 2111 }
2112
021230d4
AV		 2113out:
2114 return err;
2115}
2116
2117/**
2118 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2119 * @adapter: board private structure
2120 *
2121 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2122 * interrupts from the kernel.
2123 **/
2124static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2125{
2126 struct net_device *netdev = adapter->netdev;
2127 irqreturn_t (*handler)(int, void *);
2128 int i, vector, q_vectors, err;
e8e9f696 2129 int ri = 0, ti = 0;
021230d4
AV		 2130
2131 /* Decrement for Other and TCP Timer vectors */
2132 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2133
2134 /* Map the Tx/Rx rings to the vectors we were allotted. */
2135 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2136 if (err)
2137 goto out;
2138
2139#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
e8e9f696
JP		 2140 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2141 &ixgbe_msix_clean_many)
021230d4 2142 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 2143 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20 2144
e8e9f696 2145 if (handler == &ixgbe_msix_clean_rx) {
cb13fc20
RO		 2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "rx", ri++);
e8e9f696 2148 } else if (handler == &ixgbe_msix_clean_tx) {
cb13fc20
RO		 2149 sprintf(adapter->name[vector], "%s-%s-%d",
2150 netdev->name, "tx", ti++);
e8e9f696 2151 } else
cb13fc20
RO		 2152 sprintf(adapter->name[vector], "%s-%s-%d",
2153 netdev->name, "TxRx", vector);
2154
021230d4 2155 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696
JP		 2156 handler, 0, adapter->name[vector],
2157 adapter->q_vector[vector]);
9a799d71 2158 if (err) {
396e799c 2159 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2160 "Error: %d\n", err);
021230d4 2161 goto free_queue_irqs;
9a799d71 2162 }
9a799d71
AK		 2163 }
2164
021230d4
AV		 2165 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2166 err = request_irq(adapter->msix_entries[vector].vector,
e8e9f696 2167 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71 2168 if (err) {
396e799c 2169 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2170 goto free_queue_irqs;
9a799d71
AK		 2171 }
2172
9a799d71
AK		 2173 return 0;
2174
021230d4
AV		 2175free_queue_irqs:
2176 for (i = vector - 1; i >= 0; i--)
2177 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2178 adapter->q_vector[i]);
021230d4
AV		 2179 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2180 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2181 kfree(adapter->msix_entries);
2182 adapter->msix_entries = NULL;
021230d4 2183out:
9a799d71
AK		 2184 return err;
2185}
2186
f494e8fa
AV		 2187static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2188{
7a921c93 2189 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 2190 u8 current_itr;
2191 u32 new_itr = q_vector->eitr;
4a0b9ca0
PW		 2192 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2193 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
f494e8fa 2194
30efa5a3 2195 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2196 q_vector->tx_itr,
2197 tx_ring->total_packets,
2198 tx_ring->total_bytes);
30efa5a3 2199 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2200 q_vector->rx_itr,
2201 rx_ring->total_packets,
2202 rx_ring->total_bytes);
f494e8fa 2203
30efa5a3 2204 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2205
2206 switch (current_itr) {
2207 /* counts and packets in update_itr are dependent on these numbers */
2208 case lowest_latency:
2209 new_itr = 100000;
2210 break;
2211 case low_latency:
2212 new_itr = 20000; /* aka hwitr = ~200 */
2213 break;
2214 case bulk_latency:
2215 new_itr = 8000;
2216 break;
2217 default:
2218 break;
2219 }
2220
2221 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 2222 /* do an exponential smoothing */
2223 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 2224
2225 /* save the algorithm value here, not the smoothed one */
2226 q_vector->eitr = new_itr;
fe49f04a
AD		 2227
2228 ixgbe_write_eitr(q_vector);
f494e8fa 2229 }
f494e8fa
AV		 2230}
2231
79aefa45
AD		 2232/**
2233 * ixgbe_irq_enable - Enable default interrupt generation settings
2234 * @adapter: board private structure
2235 **/
2236static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2237{
2238 u32 mask;
835462fc
NS		 2239
2240 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2243 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2244 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 2245 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 2246 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2247 mask |= IXGBE_EIMS_GPI_SDP1;
2248 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2249 if (adapter->num_vfs)
2250 mask |= IXGBE_EIMS_MAILBOX;
e8e26350 2251 }
c4cf55e5
PWJ		 2252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2253 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2254 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2255
79aefa45 2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 2257 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45 2258 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2259
2260 if (adapter->num_vfs > 32) {
2261 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2263 }
79aefa45 2264}
021230d4 2265
9a799d71 2266/**
021230d4 2267 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2268 * @irq: interrupt number
2269 * @data: pointer to a network interface device structure
9a799d71
AK		 2270 **/
2271static irqreturn_t ixgbe_intr(int irq, void *data)
2272{
2273 struct net_device *netdev = data;
2274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2275 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2276 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2277 u32 eicr;
2278
54037505
DS		 2279 /*
2280 * Workaround for silicon errata. Mask the interrupts
2281 * before the read of EICR.
2282 */
2283 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2284
021230d4
AV		 2285 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2286 * therefore no explict interrupt disable is necessary */
2287 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 2288 if (!eicr) {
2289 /* shared interrupt alert!
2290 * make sure interrupts are enabled because the read will
2291 * have disabled interrupts due to EIAM */
2292 ixgbe_irq_enable(adapter);
9a799d71 2293 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2294 }
9a799d71 2295
cf8280ee
JB		 2296 if (eicr & IXGBE_EICR_LSC)
2297 ixgbe_check_lsc(adapter);
021230d4 2298
e8e26350
PW		 2299 if (hw->mac.type == ixgbe_mac_82599EB)
2300 ixgbe_check_sfp_event(adapter, eicr);
2301
0befdb3e 2302 ixgbe_check_fan_failure(adapter, eicr);
119fc60a
MC		 2303 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2304 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2305 schedule_work(&adapter->check_overtemp_task);
0befdb3e 2306
7a921c93 2307 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2308 adapter->tx_ring[0]->total_packets = 0;
2309 adapter->tx_ring[0]->total_bytes = 0;
2310 adapter->rx_ring[0]->total_packets = 0;
2311 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2312 /* would disable interrupts here but EIAM disabled it */
7a921c93 2313 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2314 }
2315
2316 return IRQ_HANDLED;
2317}
2318
021230d4
AV		 2319static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2320{
2321 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2322
2323 for (i = 0; i < q_vectors; i++) {
7a921c93 2324 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2325 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2326 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2327 q_vector->rxr_count = 0;
2328 q_vector->txr_count = 0;
2329 }
2330}
2331
9a799d71
AK		 2332/**
2333 * ixgbe_request_irq - initialize interrupts
2334 * @adapter: board private structure
2335 *
2336 * Attempts to configure interrupts using the best available
2337 * capabilities of the hardware and kernel.
2338 **/
021230d4 2339static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2340{
2341 struct net_device *netdev = adapter->netdev;
021230d4 2342 int err;
9a799d71 2343
021230d4
AV		 2344 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2345 err = ixgbe_request_msix_irqs(adapter);
2346 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2347 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2348 netdev->name, netdev);
021230d4 2349 } else {
a0607fd3 2350 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2351 netdev->name, netdev);
9a799d71
AK		 2352 }
2353
9a799d71 2354 if (err)
396e799c 2355 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2356
9a799d71
AK		 2357 return err;
2358}
2359
2360static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2361{
2362 struct net_device *netdev = adapter->netdev;
2363
2364 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2365 int i, q_vectors;
9a799d71 2366
021230d4
AV		 2367 q_vectors = adapter->num_msix_vectors;
2368
2369 i = q_vectors - 1;
9a799d71 2370 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2371
021230d4
AV		 2372 i--;
2373 for (; i >= 0; i--) {
2374 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2375 adapter->q_vector[i]);
021230d4
AV		 2376 }
2377
2378 ixgbe_reset_q_vectors(adapter);
2379 } else {
2380 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2381 }
2382}
2383
22d5a71b
JB		 2384/**
2385 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2386 * @adapter: board private structure
2387 **/
2388static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2389{
835462fc
NS		 2390 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2392 } else {
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2394 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2396 if (adapter->num_vfs > 32)
2397 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
22d5a71b
JB		 2398 }
2399 IXGBE_WRITE_FLUSH(&adapter->hw);
2400 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2401 int i;
2402 for (i = 0; i < adapter->num_msix_vectors; i++)
2403 synchronize_irq(adapter->msix_entries[i].vector);
2404 } else {
2405 synchronize_irq(adapter->pdev->irq);
2406 }
2407}
2408
9a799d71
AK		 2409/**
2410 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2411 *
2412 **/
2413static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2414{
9a799d71
AK		 2415 struct ixgbe_hw *hw = &adapter->hw;
2416
021230d4 2417 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2418 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2419
e8e26350
PW		 2420 ixgbe_set_ivar(adapter, 0, 0, 0);
2421 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2422
2423 map_vector_to_rxq(adapter, 0, 0);
2424 map_vector_to_txq(adapter, 0, 0);
2425
396e799c 2426 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2427}
2428
43e69bf0
AD		 2429/**
2430 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2431 * @adapter: board private structure
2432 * @ring: structure containing ring specific data
2433 *
2434 * Configure the Tx descriptor ring after a reset.
2435 **/
84418e3b
AD		 2436void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2437 struct ixgbe_ring *ring)
43e69bf0
AD		 2438{
2439 struct ixgbe_hw *hw = &adapter->hw;
2440 u64 tdba = ring->dma;
2f1860b8
AD		 2441 int wait_loop = 10;
2442 u32 txdctl;
43e69bf0
AD		 2443 u16 reg_idx = ring->reg_idx;
2444
2f1860b8
AD		 2445 /* disable queue to avoid issues while updating state */
2446 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2447 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2448 txdctl & ~IXGBE_TXDCTL_ENABLE);
2449 IXGBE_WRITE_FLUSH(hw);
2450
43e69bf0 2451 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2452 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2453 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2454 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2455 ring->count * sizeof(union ixgbe_adv_tx_desc));
2456 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2457 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2458 ring->head = IXGBE_TDH(reg_idx);
2459 ring->tail = IXGBE_TDT(reg_idx);
2460
2f1860b8
AD		 2461 /* configure fetching thresholds */
2462 if (adapter->rx_itr_setting == 0) {
2463 /* cannot set wthresh when itr==0 */
2464 txdctl &= ~0x007F0000;
2465 } else {
2466 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2467 txdctl |= (8 << 16);
2468 }
2469 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2470 /* PThresh workaround for Tx hang with DFP enabled. */
2471 txdctl |= 32;
2472 }
2473
2474 /* reinitialize flowdirector state */
2475 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2476
2477 /* enable queue */
2478 txdctl |= IXGBE_TXDCTL_ENABLE;
2479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2480
2481 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2482 if (hw->mac.type == ixgbe_mac_82598EB &&
2483 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2484 return;
2485
2486 /* poll to verify queue is enabled */
2487 do {
2488 msleep(1);
2489 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2490 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2491 if (!wait_loop)
2492 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2493}
2494
120ff942
AD		 2495static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
2498 u32 rttdcs;
2499 u32 mask;
2500
2501 if (hw->mac.type == ixgbe_mac_82598EB)
2502 return;
2503
2504 /* disable the arbiter while setting MTQC */
2505 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2506 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2507 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2508
2509 /* set transmit pool layout */
2510 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2511 switch (adapter->flags & mask) {
2512
2513 case (IXGBE_FLAG_SRIOV_ENABLED):
2514 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2515 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2516 break;
2517
2518 case (IXGBE_FLAG_DCB_ENABLED):
2519 /* We enable 8 traffic classes, DCB only */
2520 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2521 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2522 break;
2523
2524 default:
2525 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2526 break;
2527 }
2528
2529 /* re-enable the arbiter */
2530 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2531 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2532}
2533
9a799d71 2534/**
3a581073 2535 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2536 * @adapter: board private structure
2537 *
2538 * Configure the Tx unit of the MAC after a reset.
2539 **/
2540static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2541{
2f1860b8
AD		 2542 struct ixgbe_hw *hw = &adapter->hw;
2543 u32 dmatxctl;
43e69bf0 2544 u32 i;
9a799d71 2545
2f1860b8
AD		 2546 ixgbe_setup_mtqc(adapter);
2547
2548 if (hw->mac.type != ixgbe_mac_82598EB) {
2549 /* DMATXCTL.EN must be before Tx queues are enabled */
2550 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2551 dmatxctl |= IXGBE_DMATXCTL_TE;
2552 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2553 }
2554
9a799d71 2555 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2556 for (i = 0; i < adapter->num_tx_queues; i++)
2557 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2558}
2559
e8e26350 2560#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2561
a6616b42 2562static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2563 struct ixgbe_ring *rx_ring)
cc41ac7c 2564{
cc41ac7c 2565 u32 srrctl;
a6616b42 2566 int index;
0cefafad 2567 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 2568
a6616b42
YZ		 2569 index = rx_ring->reg_idx;
2570 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2571 unsigned long mask;
0cefafad 2572 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 2573 index = index & mask;
cc41ac7c 2574 }
cc41ac7c
JB		 2575 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2576
2577 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2578 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2579 if (adapter->num_vfs)
2580 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2581
afafd5b0
AD		 2582 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2583 IXGBE_SRRCTL_BSIZEHDR_MASK;
2584
6e455b89 2585 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 2586#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2587 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2588#else
2589 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2590#endif
cc41ac7c 2591 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2592 } else {
afafd5b0
AD		 2593 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2594 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2595 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2596 }
e8e26350 2597
cc41ac7c
JB		 2598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2599}
9a799d71 2600
05abb126 2601static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2602{
05abb126
AD		 2603 struct ixgbe_hw *hw = &adapter->hw;
2604 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2605 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2606 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2607 u32 mrqc = 0, reta = 0;
2608 u32 rxcsum;
2609 int i, j;
0cefafad
JB		 2610 int mask;
2611
05abb126
AD		 2612 /* Fill out hash function seeds */
2613 for (i = 0; i < 10; i++)
2614 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2615
2616 /* Fill out redirection table */
2617 for (i = 0, j = 0; i < 128; i++, j++) {
2618 if (j == adapter->ring_feature[RING_F_RSS].indices)
2619 j = 0;
2620 /* reta = 4-byte sliding window of
2621 * 0x00..(indices-1)(indices-1)00..etc. */
2622 reta = (reta << 8) | (j * 0x11);
2623 if ((i & 3) == 3)
2624 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2625 }
0cefafad 2626
05abb126
AD		 2627 /* Disable indicating checksum in descriptor, enables RSS hash */
2628 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2629 rxcsum |= IXGBE_RXCSUM_PCSD;
2630 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2631
2632 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2633 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2634 else
2635 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2636#ifdef CONFIG_IXGBE_DCB
05abb126 2637 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2638#endif
05abb126
AD		 2639 | IXGBE_FLAG_SRIOV_ENABLED
2640 );
0cefafad
JB		 2641
2642 switch (mask) {
2643 case (IXGBE_FLAG_RSS_ENABLED):
2644 mrqc = IXGBE_MRQC_RSSEN;
2645 break;
1cdd1ec8
GR		 2646 case (IXGBE_FLAG_SRIOV_ENABLED):
2647 mrqc = IXGBE_MRQC_VMDQEN;
2648 break;
0cefafad
JB		 2649#ifdef CONFIG_IXGBE_DCB
2650 case (IXGBE_FLAG_DCB_ENABLED):
2651 mrqc = IXGBE_MRQC_RT8TCEN;
2652 break;
2653#endif /* CONFIG_IXGBE_DCB */
2654 default:
2655 break;
2656 }
2657
05abb126
AD		 2658 /* Perform hash on these packet types */
2659 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2660 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2661 | IXGBE_MRQC_RSS_FIELD_IPV6
2662 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2663
2664 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2665}
2666
bb5a9ad2
NS		 2667/**
2668 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2669 * @adapter: address of board private structure
2670 * @index: index of ring to set
bb5a9ad2 2671 **/
7367096a
AD		 2672static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2673 struct ixgbe_ring *ring)
bb5a9ad2 2674{
bb5a9ad2 2675 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2676 u32 rscctrl;
edd2ea55 2677 int rx_buf_len;
7367096a
AD		 2678 u16 reg_idx = ring->reg_idx;
2679
2680 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2681 return;
bb5a9ad2 2682
7367096a
AD		 2683 rx_buf_len = ring->rx_buf_len;
2684 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2685 rscctrl |= IXGBE_RSCCTL_RSCEN;
2686 /*
2687 * we must limit the number of descriptors so that the
2688 * total size of max desc * buf_len is not greater
2689 * than 65535
2690 */
7367096a 2691 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
bb5a9ad2
NS		 2692#if (MAX_SKB_FRAGS > 16)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2694#elif (MAX_SKB_FRAGS > 8)
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2696#elif (MAX_SKB_FRAGS > 4)
2697 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2698#else
2699 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2700#endif
2701 } else {
2702 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2703 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2704 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2705 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2706 else
2707 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2708 }
7367096a 2709 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2710}
2711
9e10e045
AD		 2712/**
2713 * ixgbe_set_uta - Set unicast filter table address
2714 * @adapter: board private structure
2715 *
2716 * The unicast table address is a register array of 32-bit registers.
2717 * The table is meant to be used in a way similar to how the MTA is used
2718 * however due to certain limitations in the hardware it is necessary to
2719 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2720 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2721 **/
2722static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2723{
2724 struct ixgbe_hw *hw = &adapter->hw;
2725 int i;
2726
2727 /* The UTA table only exists on 82599 hardware and newer */
2728 if (hw->mac.type < ixgbe_mac_82599EB)
2729 return;
2730
2731 /* we only need to do this if VMDq is enabled */
2732 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2733 return;
2734
2735 for (i = 0; i < 128; i++)
2736 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2737}
2738
2739#define IXGBE_MAX_RX_DESC_POLL 10
2740static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2741 struct ixgbe_ring *ring)
2742{
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 int reg_idx = ring->reg_idx;
2745 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2746 u32 rxdctl;
2747
2748 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2749 if (hw->mac.type == ixgbe_mac_82598EB &&
2750 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2751 return;
2752
2753 do {
2754 msleep(1);
2755 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2756 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2757
2758 if (!wait_loop) {
2759 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2760 "the polling period\n", reg_idx);
2761 }
2762}
2763
84418e3b
AD		 2764void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2765 struct ixgbe_ring *ring)
acd37177
AD		 2766{
2767 struct ixgbe_hw *hw = &adapter->hw;
2768 u64 rdba = ring->dma;
9e10e045 2769 u32 rxdctl;
acd37177
AD		 2770 u16 reg_idx = ring->reg_idx;
2771
9e10e045
AD		 2772 /* disable queue to avoid issues while updating state */
2773 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2775 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2776 IXGBE_WRITE_FLUSH(hw);
2777
acd37177
AD		 2778 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2779 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2780 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2781 ring->count * sizeof(union ixgbe_adv_rx_desc));
2782 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2783 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2784 ring->head = IXGBE_RDH(reg_idx);
2785 ring->tail = IXGBE_RDT(reg_idx);
9e10e045
AD		 2786
2787 ixgbe_configure_srrctl(adapter, ring);
2788 ixgbe_configure_rscctl(adapter, ring);
2789
2790 if (hw->mac.type == ixgbe_mac_82598EB) {
2791 /*
2792 * enable cache line friendly hardware writes:
2793 * PTHRESH=32 descriptors (half the internal cache),
2794 * this also removes ugly rx_no_buffer_count increment
2795 * HTHRESH=4 descriptors (to minimize latency on fetch)
2796 * WTHRESH=8 burst writeback up to two cache lines
2797 */
2798 rxdctl &= ~0x3FFFFF;
2799 rxdctl |= 0x080420;
2800 }
2801
2802 /* enable receive descriptor ring */
2803 rxdctl |= IXGBE_RXDCTL_ENABLE;
2804 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2805
2806 ixgbe_rx_desc_queue_enable(adapter, ring);
2807 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 2808}
2809
48654521
AD		 2810static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2811{
2812 struct ixgbe_hw *hw = &adapter->hw;
2813 int p;
2814
2815 /* PSRTYPE must be initialized in non 82598 adapters */
2816 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2817 IXGBE_PSRTYPE_UDPHDR |
2818 IXGBE_PSRTYPE_IPV4HDR |
48654521 2819 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2820 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2821
2822 if (hw->mac.type == ixgbe_mac_82598EB)
2823 return;
2824
2825 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2826 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2827
2828 for (p = 0; p < adapter->num_rx_pools; p++)
2829 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2830 psrtype);
2831}
2832
f5b4a52e
AD		 2833static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2834{
2835 struct ixgbe_hw *hw = &adapter->hw;
2836 u32 gcr_ext;
2837 u32 vt_reg_bits;
2838 u32 reg_offset, vf_shift;
2839 u32 vmdctl;
2840
2841 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2842 return;
2843
2844 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2845 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2846 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2847 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2848
2849 vf_shift = adapter->num_vfs % 32;
2850 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2851
2852 /* Enable only the PF's pool for Tx/Rx */
2853 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2854 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2855 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2856 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2857 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2858
2859 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2860 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2861
2862 /*
2863 * Set up VF register offsets for selected VT Mode,
2864 * i.e. 32 or 64 VFs for SR-IOV
2865 */
2866 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2867 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2868 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2869 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2870
2871 /* enable Tx loopback for VF/PF communication */
2872 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2873}
2874
477de6ed 2875static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2876{
9a799d71
AK		 2877 struct ixgbe_hw *hw = &adapter->hw;
2878 struct net_device *netdev = adapter->netdev;
2879 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2880 int rx_buf_len;
477de6ed
AD		 2881 struct ixgbe_ring *rx_ring;
2882 int i;
2883 u32 mhadd, hlreg0;
48654521 2884
9a799d71 2885 /* Decide whether to use packet split mode or not */
1cdd1ec8
GR		 2886 /* Do not use packet split if we're in SR-IOV Mode */
2887 if (!adapter->num_vfs)
2888 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2889
2890 /* Set the RX buffer length according to the mode */
2891 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2892 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2893 } else {
0c19d6af 2894 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2895 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2896 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2897 else
477de6ed 2898 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2899 }
2900
63f39bd1 2901#ifdef IXGBE_FCOE
477de6ed
AD		 2902 /* adjust max frame to be able to do baby jumbo for FCoE */
2903 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2904 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2905 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2906
477de6ed
AD		 2907#endif /* IXGBE_FCOE */
2908 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2909 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2910 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2911 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2912
2913 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2914 }
2915
2916 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2917 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2918 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2919 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2920
0cefafad
JB		 2921 /*
2922 * Setup the HW Rx Head and Tail Descriptor Pointers and
2923 * the Base and Length of the Rx Descriptor Ring
2924 */
9a799d71 2925 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2926 rx_ring = adapter->rx_ring[i];
a6616b42 2927 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2928
6e455b89
YZ		 2929 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2930 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2931 else
2932 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2933
63f39bd1 2934#ifdef IXGBE_FCOE
e8e9f696 2935 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2936 struct ixgbe_ring_feature *f;
2937 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2938 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2939 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2940 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2941 rx_ring->rx_buf_len =
e8e9f696 2942 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2943 }
63f39bd1 2944 }
63f39bd1 2945#endif /* IXGBE_FCOE */
477de6ed
AD		 2946 }
2947
2948}
2949
7367096a
AD		 2950static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2951{
2952 struct ixgbe_hw *hw = &adapter->hw;
2953 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2954
2955 switch (hw->mac.type) {
2956 case ixgbe_mac_82598EB:
2957 /*
2958 * For VMDq support of different descriptor types or
2959 * buffer sizes through the use of multiple SRRCTL
2960 * registers, RDRXCTL.MVMEN must be set to 1
2961 *
2962 * also, the manual doesn't mention it clearly but DCA hints
2963 * will only use queue 0's tags unless this bit is set. Side
2964 * effects of setting this bit are only that SRRCTL must be
2965 * fully programmed [0..15]
2966 */
2967 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2968 break;
2969 case ixgbe_mac_82599EB:
2970 /* Disable RSC for ACK packets */
2971 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2972 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2973 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2974 /* hardware requires some bits to be set by default */
2975 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2976 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2977 break;
2978 default:
2979 /* We should do nothing since we don't know this hardware */
2980 return;
2981 }
2982
2983 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2984}
2985
477de6ed
AD		 2986/**
2987 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2988 * @adapter: board private structure
2989 *
2990 * Configure the Rx unit of the MAC after a reset.
2991 **/
2992static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2993{
2994 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 2995 int i;
2996 u32 rxctrl;
477de6ed
AD		 2997
2998 /* disable receives while setting up the descriptors */
2999 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3000 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3001
3002 ixgbe_setup_psrtype(adapter);
7367096a 3003 ixgbe_setup_rdrxctl(adapter);
477de6ed 3004
9e10e045 3005 /* Program registers for the distribution of queues */
f5b4a52e 3006 ixgbe_setup_mrqc(adapter);
f5b4a52e 3007
9e10e045
AD		 3008 ixgbe_set_uta(adapter);
3009
477de6ed
AD		 3010 /* set_rx_buffer_len must be called before ring initialization */
3011 ixgbe_set_rx_buffer_len(adapter);
3012
3013 /*
3014 * Setup the HW Rx Head and Tail Descriptor Pointers and
3015 * the Base and Length of the Rx Descriptor Ring
3016 */
9e10e045
AD		 3017 for (i = 0; i < adapter->num_rx_queues; i++)
3018 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3019
9e10e045
AD		 3020 /* disable drop enable for 82598 parts */
3021 if (hw->mac.type == ixgbe_mac_82598EB)
3022 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3023
3024 /* enable all receives */
3025 rxctrl |= IXGBE_RXCTRL_RXEN;
3026 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3027}
3028
068c89b0
DS		 3029static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3030{
3031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3032 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3033 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3034
3035 /* add VID to filter table */
1ada1b1b 3036 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
068c89b0
DS		 3037}
3038
3039static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3040{
3041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3043 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3044
3045 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3046 ixgbe_irq_disable(adapter);
3047
3048 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3049
3050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3051 ixgbe_irq_enable(adapter);
3052
3053 /* remove VID from filter table */
1ada1b1b 3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
068c89b0
DS		 3055}
3056
5f6c0181
JB		 3057/**
3058 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3059 * @adapter: driver data
3060 */
3061static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3065 int i, j;
3066
3067 switch (hw->mac.type) {
3068 case ixgbe_mac_82598EB:
38e0bd98
YZ		 3069 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3070#ifdef CONFIG_IXGBE_DCB
3071 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3072 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3073#endif
5f6c0181
JB		 3074 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3075 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3076 break;
3077 case ixgbe_mac_82599EB:
3078 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
3079 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3080 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
38e0bd98
YZ		 3081#ifdef CONFIG_IXGBE_DCB
3082 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
3083 break;
3084#endif
5f6c0181
JB		 3085 for (i = 0; i < adapter->num_rx_queues; i++) {
3086 j = adapter->rx_ring[i]->reg_idx;
3087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3088 vlnctrl &= ~IXGBE_RXDCTL_VME;
3089 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3090 }
3091 break;
3092 default:
3093 break;
3094 }
3095}
3096
3097/**
3098 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3099 * @adapter: driver data
3100 */
3101static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3102{
3103 struct ixgbe_hw *hw = &adapter->hw;
3104 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3105 int i, j;
3106
3107 switch (hw->mac.type) {
3108 case ixgbe_mac_82598EB:
3109 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
3110 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3111 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3112 break;
3113 case ixgbe_mac_82599EB:
3114 vlnctrl |= IXGBE_VLNCTRL_VFE;
3115 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3117 for (i = 0; i < adapter->num_rx_queues; i++) {
3118 j = adapter->rx_ring[i]->reg_idx;
3119 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3120 vlnctrl |= IXGBE_RXDCTL_VME;
3121 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3122 }
3123 break;
3124 default:
3125 break;
3126 }
3127}
3128
9a799d71 3129static void ixgbe_vlan_rx_register(struct net_device *netdev,
e8e9f696 3130 struct vlan_group *grp)
9a799d71
AK		 3131{
3132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 3133
d4f80882
AV		 3134 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3135 ixgbe_irq_disable(adapter);
9a799d71
AK		 3136 adapter->vlgrp = grp;
3137
2f90b865
AD		 3138 /*
3139 * For a DCB driver, always enable VLAN tag stripping so we can
3140 * still receive traffic from a DCB-enabled host even if we're
3141 * not in DCB mode.
3142 */
5f6c0181 3143 ixgbe_vlan_filter_enable(adapter);
dc63d377 3144
e8e26350 3145 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 3146
d4f80882
AV		 3147 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3148 ixgbe_irq_enable(adapter);
9a799d71
AK		 3149}
3150
9a799d71
AK		 3151static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3152{
3153 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3154
3155 if (adapter->vlgrp) {
3156 u16 vid;
3157 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3158 if (!vlan_group_get_device(adapter->vlgrp, vid))
3159 continue;
3160 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3161 }
3162 }
3163}
3164
2850062a
AD		 3165/**
3166 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3167 * @netdev: network interface device structure
3168 *
3169 * Writes unicast address list to the RAR table.
3170 * Returns: -ENOMEM on failure/insufficient address space
3171 * 0 on no addresses written
3172 * X on writing X addresses to the RAR table
3173 **/
3174static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3175{
3176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3177 struct ixgbe_hw *hw = &adapter->hw;
3178 unsigned int vfn = adapter->num_vfs;
3179 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3180 int count = 0;
3181
3182 /* return ENOMEM indicating insufficient memory for addresses */
3183 if (netdev_uc_count(netdev) > rar_entries)
3184 return -ENOMEM;
3185
3186 if (!netdev_uc_empty(netdev) && rar_entries) {
3187 struct netdev_hw_addr *ha;
3188 /* return error if we do not support writing to RAR table */
3189 if (!hw->mac.ops.set_rar)
3190 return -ENOMEM;
3191
3192 netdev_for_each_uc_addr(ha, netdev) {
3193 if (!rar_entries)
3194 break;
3195 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3196 vfn, IXGBE_RAH_AV);
3197 count++;
3198 }
3199 }
3200 /* write the addresses in reverse order to avoid write combining */
3201 for (; rar_entries > 0 ; rar_entries--)
3202 hw->mac.ops.clear_rar(hw, rar_entries);
3203
3204 return count;
3205}
3206
9a799d71 3207/**
2c5645cf 3208 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3209 * @netdev: network interface device structure
3210 *
2c5645cf
CL		 3211 * The set_rx_method entry point is called whenever the unicast/multicast
3212 * address list or the network interface flags are updated. This routine is
3213 * responsible for configuring the hardware for proper unicast, multicast and
3214 * promiscuous mode.
9a799d71 3215 **/
7f870475 3216void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3217{
3218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3220 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3221 int count;
9a799d71
AK		 3222
3223 /* Check for Promiscuous and All Multicast modes */
3224
3225 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3226
f5dc442b
AD		 3227 /* set all bits that we expect to always be set */
3228 fctrl |= IXGBE_FCTRL_BAM;
3229 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3230 fctrl |= IXGBE_FCTRL_PMCF;
3231
2850062a
AD		 3232 /* clear the bits we are changing the status of */
3233 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3234
9a799d71 3235 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3236 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3237 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3238 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3239 /* don't hardware filter vlans in promisc mode */
3240 ixgbe_vlan_filter_disable(adapter);
9a799d71 3241 } else {
746b9f02
PM		 3242 if (netdev->flags & IFF_ALLMULTI) {
3243 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3244 vmolr |= IXGBE_VMOLR_MPE;
3245 } else {
3246 /*
3247 * Write addresses to the MTA, if the attempt fails
3248 * then we should just turn on promiscous mode so
3249 * that we can at least receive multicast traffic
3250 */
3251 hw->mac.ops.update_mc_addr_list(hw, netdev);
3252 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3253 }
5f6c0181 3254 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3255 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3256 /*
3257 * Write addresses to available RAR registers, if there is not
3258 * sufficient space to store all the addresses then enable
3259 * unicast promiscous mode
3260 */
3261 count = ixgbe_write_uc_addr_list(netdev);
3262 if (count < 0) {
3263 fctrl |= IXGBE_FCTRL_UPE;
3264 vmolr |= IXGBE_VMOLR_ROPE;
3265 }
9a799d71
AK		 3266 }
3267
2850062a 3268 if (adapter->num_vfs) {
1cdd1ec8 3269 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3270 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3271 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3272 IXGBE_VMOLR_ROPE);
3273 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3274 }
3275
3276 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
9a799d71
AK		 3277}
3278
021230d4
AV		 3279static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3280{
3281 int q_idx;
3282 struct ixgbe_q_vector *q_vector;
3283 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3284
3285 /* legacy and MSI only use one vector */
3286 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3287 q_vectors = 1;
3288
3289 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3290 struct napi_struct *napi;
7a921c93 3291 q_vector = adapter->q_vector[q_idx];
f0848276 3292 napi = &q_vector->napi;
91281fd3
AD		 3293 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3294 if (!q_vector->rxr_count || !q_vector->txr_count) {
3295 if (q_vector->txr_count == 1)
3296 napi->poll = &ixgbe_clean_txonly;
3297 else if (q_vector->rxr_count == 1)
3298 napi->poll = &ixgbe_clean_rxonly;
3299 }
3300 }
f0848276
JB		 3301
3302 napi_enable(napi);
021230d4
AV		 3303 }
3304}
3305
3306static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3307{
3308 int q_idx;
3309 struct ixgbe_q_vector *q_vector;
3310 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3311
3312 /* legacy and MSI only use one vector */
3313 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3314 q_vectors = 1;
3315
3316 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3317 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3318 napi_disable(&q_vector->napi);
3319 }
3320}
3321
7a6b6f51 3322#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3323/*
3324 * ixgbe_configure_dcb - Configure DCB hardware
3325 * @adapter: ixgbe adapter struct
3326 *
3327 * This is called by the driver on open to configure the DCB hardware.
3328 * This is also called by the gennetlink interface when reconfiguring
3329 * the DCB state.
3330 */
3331static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3332{
3333 struct ixgbe_hw *hw = &adapter->hw;
5f6c0181 3334 u32 txdctl;
2f90b865
AD		 3335 int i, j;
3336
67ebd791
AD		 3337 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3338 if (hw->mac.type == ixgbe_mac_82598EB)
3339 netif_set_gso_max_size(adapter->netdev, 65536);
3340 return;
3341 }
3342
3343 if (hw->mac.type == ixgbe_mac_82598EB)
3344 netif_set_gso_max_size(adapter->netdev, 32768);
3345
2f90b865
AD		 3346 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3347 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3348 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3349
3350 /* reconfigure the hardware */
3351 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3352
3353 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3354 j = adapter->tx_ring[i]->reg_idx;
2f90b865
AD		 3355 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3356 /* PThresh workaround for Tx hang with DFP enabled. */
3357 txdctl |= 32;
3358 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3359 }
3360 /* Enable VLAN tag insert/strip */
5f6c0181
JB		 3361 ixgbe_vlan_filter_enable(adapter);
3362
2f90b865
AD		 3363 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3364}
3365
3366#endif
9a799d71
AK		 3367static void ixgbe_configure(struct ixgbe_adapter *adapter)
3368{
3369 struct net_device *netdev = adapter->netdev;
c4cf55e5 3370 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3371 int i;
3372
2c5645cf 3373 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 3374
3375 ixgbe_restore_vlan(adapter);
7a6b6f51 3376#ifdef CONFIG_IXGBE_DCB
67ebd791 3377 ixgbe_configure_dcb(adapter);
2f90b865 3378#endif
9a799d71 3379
eacd73f7
YZ		 3380#ifdef IXGBE_FCOE
3381 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3382 ixgbe_configure_fcoe(adapter);
3383
3384#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3385 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3386 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3387 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3388 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3389 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3390 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3391 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3392 }
933d41f1 3393 ixgbe_configure_virtualization(adapter);
c4cf55e5 3394
9a799d71
AK		 3395 ixgbe_configure_tx(adapter);
3396 ixgbe_configure_rx(adapter);
9a799d71
AK		 3397}
3398
e8e26350
PW		 3399static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3400{
3401 switch (hw->phy.type) {
3402 case ixgbe_phy_sfp_avago:
3403 case ixgbe_phy_sfp_ftl:
3404 case ixgbe_phy_sfp_intel:
3405 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3406 case ixgbe_phy_sfp_passive_tyco:
3407 case ixgbe_phy_sfp_passive_unknown:
3408 case ixgbe_phy_sfp_active_unknown:
3409 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3410 return true;
3411 default:
3412 return false;
3413 }
3414}
3415
0ecc061d 3416/**
e8e26350
PW		 3417 * ixgbe_sfp_link_config - set up SFP+ link
3418 * @adapter: pointer to private adapter struct
3419 **/
3420static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3421{
3422 struct ixgbe_hw *hw = &adapter->hw;
3423
3424 if (hw->phy.multispeed_fiber) {
3425 /*
3426 * In multispeed fiber setups, the device may not have
3427 * had a physical connection when the driver loaded.
3428 * If that's the case, the initial link configuration
3429 * couldn't get the MAC into 10G or 1G mode, so we'll
3430 * never have a link status change interrupt fire.
3431 * We need to try and force an autonegotiation
3432 * session, then bring up link.
3433 */
3434 hw->mac.ops.setup_sfp(hw);
3435 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3436 schedule_work(&adapter->multispeed_fiber_task);
3437 } else {
3438 /*
3439 * Direct Attach Cu and non-multispeed fiber modules
3440 * still need to be configured properly prior to
3441 * attempting link.
3442 */
3443 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3444 schedule_work(&adapter->sfp_config_module_task);
3445 }
3446}
3447
3448/**
3449 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3450 * @hw: pointer to private hardware struct
3451 *
3452 * Returns 0 on success, negative on failure
3453 **/
e8e26350 3454static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3455{
3456 u32 autoneg;
8620a103 3457 bool negotiation, link_up = false;
0ecc061d
PWJ		 3458 u32 ret = IXGBE_ERR_LINK_SETUP;
3459
3460 if (hw->mac.ops.check_link)
3461 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3462
3463 if (ret)
3464 goto link_cfg_out;
3465
3466 if (hw->mac.ops.get_link_capabilities)
e8e9f696
JP		 3467 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3468 &negotiation);
0ecc061d
PWJ		 3469 if (ret)
3470 goto link_cfg_out;
3471
8620a103
MC		 3472 if (hw->mac.ops.setup_link)
3473 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3474link_cfg_out:
3475 return ret;
3476}
3477
a34bcfff 3478static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3479{
9a799d71 3480 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3481 u32 gpie = 0;
9a799d71 3482
9b471446 3483 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3484 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3485 IXGBE_GPIE_OCD;
3486 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3487 /*
3488 * use EIAM to auto-mask when MSI-X interrupt is asserted
3489 * this saves a register write for every interrupt
3490 */
3491 switch (hw->mac.type) {
3492 case ixgbe_mac_82598EB:
3493 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3494 break;
3495 default:
3496 case ixgbe_mac_82599EB:
3497 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3498 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3499 break;
3500 }
3501 } else {
021230d4
AV		 3502 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3503 * specifically only auto mask tx and rx interrupts */
3504 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3505 }
9a799d71 3506
a34bcfff
AD		 3507 /* XXX: to interrupt immediately for EICS writes, enable this */
3508 /* gpie |= IXGBE_GPIE_EIMEN; */
3509
3510 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3511 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3512 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3513 }
3514
a34bcfff
AD		 3515 /* Enable fan failure interrupt */
3516 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3517 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3518
a34bcfff 3519 if (hw->mac.type == ixgbe_mac_82599EB)
e8e26350
PW		 3520 gpie |= IXGBE_SDP1_GPIEN;
3521 gpie |= IXGBE_SDP2_GPIEN;
a34bcfff
AD		 3522
3523 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3524}
3525
3526static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3527{
3528 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3529 int err;
a34bcfff
AD		 3530 u32 ctrl_ext;
3531
3532 ixgbe_get_hw_control(adapter);
3533 ixgbe_setup_gpie(adapter);
e8e26350 3534
9a799d71
AK		 3535 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3536 ixgbe_configure_msix(adapter);
3537 else
3538 ixgbe_configure_msi_and_legacy(adapter);
3539
61fac744
PW		 3540 /* enable the optics */
3541 if (hw->phy.multispeed_fiber)
3542 hw->mac.ops.enable_tx_laser(hw);
3543
9a799d71 3544 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3545 ixgbe_napi_enable_all(adapter);
3546
3547 /* clear any pending interrupts, may auto mask */
3548 IXGBE_READ_REG(hw, IXGBE_EICR);
9a799d71
AK		 3549 ixgbe_irq_enable(adapter);
3550
bf069c97
DS		 3551 /*
3552 * If this adapter has a fan, check to see if we had a failure
3553 * before we enabled the interrupt.
3554 */
3555 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3556 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3557 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3558 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3559 }
3560
e8e26350
PW		 3561 /*
3562 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 3563 * arrived before interrupts were enabled but after probe. Such
3564 * devices wouldn't have their type identified yet. We need to
3565 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 3566 * If we're not hot-pluggable SFP+, we just need to configure link
3567 * and bring it up.
3568 */
19343de2
DS		 3569 if (hw->phy.type == ixgbe_phy_unknown) {
3570 err = hw->phy.ops.identify(hw);
3571 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 3572 /*
3573 * Take the device down and schedule the sfp tasklet
3574 * which will unregister_netdev and log it.
3575 */
19343de2 3576 ixgbe_down(adapter);
5da43c1a 3577 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 3578 return err;
3579 }
e8e26350
PW		 3580 }
3581
3582 if (ixgbe_is_sfp(hw)) {
3583 ixgbe_sfp_link_config(adapter);
3584 } else {
3585 err = ixgbe_non_sfp_link_config(hw);
3586 if (err)
396e799c 3587 e_err(probe, "link_config FAILED %d\n", err);
e8e26350 3588 }
0ecc061d 3589
1da100bb 3590 /* enable transmits */
477de6ed 3591 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3592
9a799d71
AK		 3593 /* bring the link up in the watchdog, this could race with our first
3594 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3595 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3596 adapter->link_check_timeout = jiffies;
9a799d71 3597 mod_timer(&adapter->watchdog_timer, jiffies);
c9205697
GR		 3598
3599 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3600 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3601 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3602 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3603
9a799d71
AK		 3604 return 0;
3605}
3606
d4f80882
AV		 3607void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3608{
3609 WARN_ON(in_interrupt());
3610 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3611 msleep(1);
3612 ixgbe_down(adapter);
5809a1ae
GR		 3613 /*
3614 * If SR-IOV enabled then wait a bit before bringing the adapter
3615 * back up to give the VFs time to respond to the reset. The
3616 * two second wait is based upon the watchdog timer cycle in
3617 * the VF driver.
3618 */
3619 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3620 msleep(2000);
d4f80882
AV		 3621 ixgbe_up(adapter);
3622 clear_bit(__IXGBE_RESETTING, &adapter->state);
3623}
3624
9a799d71
AK		 3625int ixgbe_up(struct ixgbe_adapter *adapter)
3626{
3627 /* hardware has been reset, we need to reload some things */
3628 ixgbe_configure(adapter);
3629
3630 return ixgbe_up_complete(adapter);
3631}
3632
3633void ixgbe_reset(struct ixgbe_adapter *adapter)
3634{
c44ade9e 3635 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3636 int err;
3637
3638 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3639 switch (err) {
3640 case 0:
3641 case IXGBE_ERR_SFP_NOT_PRESENT:
3642 break;
3643 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3644 e_dev_err("master disable timed out\n");
da4dd0f7 3645 break;
794caeb2
PWJ		 3646 case IXGBE_ERR_EEPROM_VERSION:
3647 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3648 e_dev_warn("This device is a pre-production adapter/LOM. "
3649 "Please be aware there may be issuesassociated with "
3650 "your hardware. If you are experiencing problems "
3651 "please contact your Intel or hardware "
3652 "representative who provided you with this "
3653 "hardware.\n");
794caeb2 3654 break;
da4dd0f7 3655 default:
849c4542 3656 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3657 }
9a799d71
AK		 3658
3659 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3660 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3661 IXGBE_RAH_AV);
9a799d71
AK		 3662}
3663
9a799d71
AK		 3664/**
3665 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3666 * @adapter: board private structure
3667 * @rx_ring: ring to free buffers from
3668 **/
3669static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3670 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3671{
3672 struct pci_dev *pdev = adapter->pdev;
3673 unsigned long size;
3674 unsigned int i;
3675
84418e3b
AD		 3676 /* ring already cleared, nothing to do */
3677 if (!rx_ring->rx_buffer_info)
3678 return;
9a799d71 3679
84418e3b 3680 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3681 for (i = 0; i < rx_ring->count; i++) {
3682 struct ixgbe_rx_buffer *rx_buffer_info;
3683
3684 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3685 if (rx_buffer_info->dma) {
1b507730 3686 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
e8e9f696 3687 rx_ring->rx_buf_len,
1b507730 3688 DMA_FROM_DEVICE);
9a799d71
AK		 3689 rx_buffer_info->dma = 0;
3690 }
3691 if (rx_buffer_info->skb) {
f8212f97 3692 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3693 rx_buffer_info->skb = NULL;
f8212f97
AD		 3694 do {
3695 struct sk_buff *this = skb;
e8171aaa 3696 if (IXGBE_RSC_CB(this)->delay_unmap) {
1b507730
NN		 3697 dma_unmap_single(&pdev->dev,
3698 IXGBE_RSC_CB(this)->dma,
e8e9f696 3699 rx_ring->rx_buf_len,
1b507730 3700 DMA_FROM_DEVICE);
fd3686a8 3701 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3702 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3703 }
f8212f97
AD		 3704 skb = skb->prev;
3705 dev_kfree_skb(this);
3706 } while (skb);
9a799d71
AK		 3707 }
3708 if (!rx_buffer_info->page)
3709 continue;
4f57ca6e 3710 if (rx_buffer_info->page_dma) {
1b507730
NN		 3711 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3712 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3713 rx_buffer_info->page_dma = 0;
3714 }
9a799d71
AK		 3715 put_page(rx_buffer_info->page);
3716 rx_buffer_info->page = NULL;
762f4c57 3717 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3718 }
3719
3720 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3721 memset(rx_ring->rx_buffer_info, 0, size);
3722
3723 /* Zero out the descriptor ring */
3724 memset(rx_ring->desc, 0, rx_ring->size);
3725
3726 rx_ring->next_to_clean = 0;
3727 rx_ring->next_to_use = 0;
3728
9891ca7c
JB		 3729 if (rx_ring->head)
3730 writel(0, adapter->hw.hw_addr + rx_ring->head);
3731 if (rx_ring->tail)
3732 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 3733}
3734
3735/**
3736 * ixgbe_clean_tx_ring - Free Tx Buffers
3737 * @adapter: board private structure
3738 * @tx_ring: ring to be cleaned
3739 **/
3740static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
e8e9f696 3741 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3742{
3743 struct ixgbe_tx_buffer *tx_buffer_info;
3744 unsigned long size;
3745 unsigned int i;
3746
84418e3b
AD		 3747 /* ring already cleared, nothing to do */
3748 if (!tx_ring->tx_buffer_info)
3749 return;
9a799d71 3750
84418e3b 3751 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3752 for (i = 0; i < tx_ring->count; i++) {
3753 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3754 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3755 }
3756
3757 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3758 memset(tx_ring->tx_buffer_info, 0, size);
3759
3760 /* Zero out the descriptor ring */
3761 memset(tx_ring->desc, 0, tx_ring->size);
3762
3763 tx_ring->next_to_use = 0;
3764 tx_ring->next_to_clean = 0;
3765
9891ca7c
JB		 3766 if (tx_ring->head)
3767 writel(0, adapter->hw.hw_addr + tx_ring->head);
3768 if (tx_ring->tail)
3769 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 3770}
3771
3772/**
021230d4 3773 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3774 * @adapter: board private structure
3775 **/
021230d4 3776static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3777{
3778 int i;
3779
021230d4 3780 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 3781 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
9a799d71
AK		 3782}
3783
3784/**
021230d4 3785 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3786 * @adapter: board private structure
3787 **/
021230d4 3788static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3789{
3790 int i;
3791
021230d4 3792 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3793 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3794}
3795
3796void ixgbe_down(struct ixgbe_adapter *adapter)
3797{
3798 struct net_device *netdev = adapter->netdev;
7f821875 3799 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3800 u32 rxctrl;
7f821875
JB		 3801 u32 txdctl;
3802 int i, j;
9a799d71
AK		 3803
3804 /* signal that we are down to the interrupt handler */
3805 set_bit(__IXGBE_DOWN, &adapter->state);
3806
767081ad
GR		 3807 /* disable receive for all VFs and wait one second */
3808 if (adapter->num_vfs) {
767081ad
GR		 3809 /* ping all the active vfs to let them know we are going down */
3810 ixgbe_ping_all_vfs(adapter);
581d1aa7 3811
767081ad
GR		 3812 /* Disable all VFTE/VFRE TX/RX */
3813 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 3814
3815 /* Mark all the VFs as inactive */
3816 for (i = 0 ; i < adapter->num_vfs; i++)
3817 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 3818 }
3819
9a799d71 3820 /* disable receives */
7f821875
JB		 3821 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3822 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3823
7f821875 3824 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 3825 msleep(10);
3826
7f821875
JB		 3827 netif_tx_stop_all_queues(netdev);
3828
0a1f87cb
DS		 3829 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3830 del_timer_sync(&adapter->sfp_timer);
9a799d71 3831 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 3832 cancel_work_sync(&adapter->watchdog_task);
9a799d71 3833
c0dfb90e
JF		 3834 netif_carrier_off(netdev);
3835 netif_tx_disable(netdev);
3836
3837 ixgbe_irq_disable(adapter);
3838
3839 ixgbe_napi_disable_all(adapter);
3840
c4cf55e5
PWJ		 3841 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3842 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3843 cancel_work_sync(&adapter->fdir_reinit_task);
3844
119fc60a
MC		 3845 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3846 cancel_work_sync(&adapter->check_overtemp_task);
3847
7f821875
JB		 3848 /* disable transmits in the hardware now that interrupts are off */
3849 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 3850 j = adapter->tx_ring[i]->reg_idx;
7f821875
JB		 3851 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3852 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
e8e9f696 3853 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 3854 }
88512539
PW		 3855 /* Disable the Tx DMA engine on 82599 */
3856 if (hw->mac.type == ixgbe_mac_82599EB)
3857 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3858 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3859 ~IXGBE_DMATXCTL_TE));
7f821875 3860
9f756f01
JF		 3861 /* power down the optics */
3862 if (hw->phy.multispeed_fiber)
3863 hw->mac.ops.disable_tx_laser(hw);
3864
9a713e7c
PW		 3865 /* clear n-tuple filters that are cached */
3866 ethtool_ntuple_flush(netdev);
3867
6f4a0e45
PL		 3868 if (!pci_channel_offline(adapter->pdev))
3869 ixgbe_reset(adapter);
9a799d71
AK		 3870 ixgbe_clean_all_tx_rings(adapter);
3871 ixgbe_clean_all_rx_rings(adapter);
3872
5dd2d332 3873#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3874 /* since we reset the hardware DCA settings were cleared */
e35ec126 3875 ixgbe_setup_dca(adapter);
96b0e0f6 3876#endif
9a799d71
AK		 3877}
3878
9a799d71 3879/**
021230d4
AV		 3880 * ixgbe_poll - NAPI Rx polling callback
3881 * @napi: structure for representing this polling device
3882 * @budget: how many packets driver is allowed to clean
3883 *
3884 * This function is used for legacy and MSI, NAPI mode
9a799d71 3885 **/
021230d4 3886static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3887{
9a1a69ad 3888 struct ixgbe_q_vector *q_vector =
e8e9f696 3889 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3890 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3891 int tx_clean_complete, work_done = 0;
9a799d71 3892
5dd2d332 3893#ifdef CONFIG_IXGBE_DCA
bd0362dd 3894 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4a0b9ca0
PW		 3895 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3896 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
bd0362dd
JC		 3897 }
3898#endif
3899
4a0b9ca0
PW		 3900 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3901 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 3902
9a1a69ad 3903 if (!tx_clean_complete)
d2c7ddd6
DM		 3904 work_done = budget;
3905
53e52c72
DM		 3906 /* If budget not fully consumed, exit the polling mode */
3907 if (work_done < budget) {
288379f0 3908 napi_complete(napi);
f7554a2b 3909 if (adapter->rx_itr_setting & 1)
f494e8fa 3910 ixgbe_set_itr(adapter);
d4f80882 3911 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3912 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3913 }
9a799d71
AK		 3914 return work_done;
3915}
3916
3917/**
3918 * ixgbe_tx_timeout - Respond to a Tx Hang
3919 * @netdev: network interface device structure
3920 **/
3921static void ixgbe_tx_timeout(struct net_device *netdev)
3922{
3923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3924
3925 /* Do the reset outside of interrupt context */
3926 schedule_work(&adapter->reset_task);
3927}
3928
3929static void ixgbe_reset_task(struct work_struct *work)
3930{
3931 struct ixgbe_adapter *adapter;
3932 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3933
2f90b865
AD		 3934 /* If we're already down or resetting, just bail */
3935 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3936 test_bit(__IXGBE_RESETTING, &adapter->state))
3937 return;
3938
9a799d71
AK		 3939 adapter->tx_timeout_count++;
3940
dcd79aeb
TI		 3941 ixgbe_dump(adapter);
3942 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 3943 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3944}
3945
bc97114d
PWJ		 3946#ifdef CONFIG_IXGBE_DCB
3947static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3948{
bc97114d 3949 bool ret = false;
0cefafad 3950 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3951
0cefafad
JB		 3952 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3953 return ret;
3954
3955 f->mask = 0x7 << 3;
3956 adapter->num_rx_queues = f->indices;
3957 adapter->num_tx_queues = f->indices;
3958 ret = true;
2f90b865 3959
bc97114d
PWJ		 3960 return ret;
3961}
3962#endif
3963
4df10466
JB		 3964/**
3965 * ixgbe_set_rss_queues: Allocate queues for RSS
3966 * @adapter: board private structure to initialize
3967 *
3968 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3969 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3970 *
3971 **/
bc97114d
PWJ		 3972static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3973{
3974 bool ret = false;
0cefafad 3975 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3976
3977 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3978 f->mask = 0xF;
3979 adapter->num_rx_queues = f->indices;
3980 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3981 ret = true;
3982 } else {
bc97114d 3983 ret = false;
b9804972
JB		 3984 }
3985
bc97114d
PWJ		 3986 return ret;
3987}
3988
c4cf55e5
PWJ		 3989/**
3990 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3991 * @adapter: board private structure to initialize
3992 *
3993 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3994 * to the original CPU that initiated the Tx session. This runs in addition
3995 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3996 * Rx load across CPUs using RSS.
3997 *
3998 **/
e8e9f696 3999static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4000{
4001 bool ret = false;
4002 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4003
4004 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4005 f_fdir->mask = 0;
4006
4007 /* Flow Director must have RSS enabled */
4008 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4009 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4010 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4011 adapter->num_tx_queues = f_fdir->indices;
4012 adapter->num_rx_queues = f_fdir->indices;
4013 ret = true;
4014 } else {
4015 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4016 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4017 }
4018 return ret;
4019}
4020
0331a832
YZ		 4021#ifdef IXGBE_FCOE
4022/**
4023 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4024 * @adapter: board private structure to initialize
4025 *
4026 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4027 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4028 * rx queues out of the max number of rx queues, instead, it is used as the
4029 * index of the first rx queue used by FCoE.
4030 *
4031 **/
4032static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4033{
4034 bool ret = false;
4035 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4036
4037 f->indices = min((int)num_online_cpus(), f->indices);
4038 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 4039 adapter->num_rx_queues = 1;
4040 adapter->num_tx_queues = 1;
0331a832
YZ		 4041#ifdef CONFIG_IXGBE_DCB
4042 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
396e799c 4043 e_info(probe, "FCoE enabled with DCB\n");
0331a832
YZ		 4044 ixgbe_set_dcb_queues(adapter);
4045 }
4046#endif
4047 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4048 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4049 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4050 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4051 ixgbe_set_fdir_queues(adapter);
4052 else
4053 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4054 }
4055 /* adding FCoE rx rings to the end */
4056 f->mask = adapter->num_rx_queues;
4057 adapter->num_rx_queues += f->indices;
8de8b2e6 4058 adapter->num_tx_queues += f->indices;
0331a832
YZ		 4059
4060 ret = true;
4061 }
4062
4063 return ret;
4064}
4065
4066#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4067/**
4068 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4069 * @adapter: board private structure to initialize
4070 *
4071 * IOV doesn't actually use anything, so just NAK the
4072 * request for now and let the other queue routines
4073 * figure out what to do.
4074 */
4075static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4076{
4077 return false;
4078}
4079
4df10466
JB		 4080/*
4081 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4082 * @adapter: board private structure to initialize
4083 *
4084 * This is the top level queue allocation routine. The order here is very
4085 * important, starting with the "most" number of features turned on at once,
4086 * and ending with the smallest set of features. This way large combinations
4087 * can be allocated if they're turned on, and smaller combinations are the
4088 * fallthrough conditions.
4089 *
4090 **/
bc97114d
PWJ		 4091static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4092{
1cdd1ec8
GR		 4093 /* Start with base case */
4094 adapter->num_rx_queues = 1;
4095 adapter->num_tx_queues = 1;
4096 adapter->num_rx_pools = adapter->num_rx_queues;
4097 adapter->num_rx_queues_per_pool = 1;
4098
4099 if (ixgbe_set_sriov_queues(adapter))
4100 return;
4101
0331a832
YZ		 4102#ifdef IXGBE_FCOE
4103 if (ixgbe_set_fcoe_queues(adapter))
4104 goto done;
4105
4106#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4107#ifdef CONFIG_IXGBE_DCB
4108 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4109 goto done;
bc97114d
PWJ		 4110
4111#endif
c4cf55e5
PWJ		 4112 if (ixgbe_set_fdir_queues(adapter))
4113 goto done;
4114
bc97114d 4115 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4116 goto done;
4117
4118 /* fallback to base case */
4119 adapter->num_rx_queues = 1;
4120 adapter->num_tx_queues = 1;
4121
4122done:
4123 /* Notify the stack of the (possibly) reduced Tx Queue count. */
f0796d5c 4124 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
b9804972
JB		 4125}
4126
021230d4 4127static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4128 int vectors)
021230d4
AV		 4129{
4130 int err, vector_threshold;
4131
4132 /* We'll want at least 3 (vector_threshold):
4133 * 1) TxQ[0] Cleanup
4134 * 2) RxQ[0] Cleanup
4135 * 3) Other (Link Status Change, etc.)
4136 * 4) TCP Timer (optional)
4137 */
4138 vector_threshold = MIN_MSIX_COUNT;
4139
4140 /* The more we get, the more we will assign to Tx/Rx Cleanup
4141 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4142 * Right now, we simply care about how many we'll get; we'll
4143 * set them up later while requesting irq's.
4144 */
4145 while (vectors >= vector_threshold) {
4146 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4147 vectors);
021230d4
AV		 4148 if (!err) /* Success in acquiring all requested vectors. */
4149 break;
4150 else if (err < 0)
4151 vectors = 0; /* Nasty failure, quit now */
4152 else /* err == number of vectors we should try again with */
4153 vectors = err;
4154 }
4155
4156 if (vectors < vector_threshold) {
4157 /* Can't allocate enough MSI-X interrupts? Oh well.
4158 * This just means we'll go with either a single MSI
4159 * vector or fall back to legacy interrupts.
4160 */
849c4542
ET		 4161 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4162 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4163 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4164 kfree(adapter->msix_entries);
4165 adapter->msix_entries = NULL;
021230d4
AV		 4166 } else {
4167 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4168 /*
4169 * Adjust for only the vectors we'll use, which is minimum
4170 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4171 * vectors we were allocated.
4172 */
4173 adapter->num_msix_vectors = min(vectors,
e8e9f696 4174 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4175 }
4176}
4177
021230d4 4178/**
bc97114d 4179 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4180 * @adapter: board private structure to initialize
4181 *
bc97114d
PWJ		 4182 * Cache the descriptor ring offsets for RSS to the assigned rings.
4183 *
021230d4 4184 **/
bc97114d 4185static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4186{
bc97114d
PWJ		 4187 int i;
4188 bool ret = false;
4189
4190 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4191 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4192 adapter->rx_ring[i]->reg_idx = i;
bc97114d 4193 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4194 adapter->tx_ring[i]->reg_idx = i;
bc97114d
PWJ		 4195 ret = true;
4196 } else {
4197 ret = false;
4198 }
4199
4200 return ret;
4201}
4202
4203#ifdef CONFIG_IXGBE_DCB
4204/**
4205 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4206 * @adapter: board private structure to initialize
4207 *
4208 * Cache the descriptor ring offsets for DCB to the assigned rings.
4209 *
4210 **/
4211static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4212{
4213 int i;
4214 bool ret = false;
4215 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4216
4217 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4218 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 4219 /* the number of queues is assumed to be symmetric */
4220 for (i = 0; i < dcb_i; i++) {
4a0b9ca0
PW		 4221 adapter->rx_ring[i]->reg_idx = i << 3;
4222 adapter->tx_ring[i]->reg_idx = i << 2;
2f90b865 4223 }
bc97114d 4224 ret = true;
e8e26350 4225 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 4226 if (dcb_i == 8) {
4227 /*
4228 * Tx TC0 starts at: descriptor queue 0
4229 * Tx TC1 starts at: descriptor queue 32
4230 * Tx TC2 starts at: descriptor queue 64
4231 * Tx TC3 starts at: descriptor queue 80
4232 * Tx TC4 starts at: descriptor queue 96
4233 * Tx TC5 starts at: descriptor queue 104
4234 * Tx TC6 starts at: descriptor queue 112
4235 * Tx TC7 starts at: descriptor queue 120
4236 *
4237 * Rx TC0-TC7 are offset by 16 queues each
4238 */
4239 for (i = 0; i < 3; i++) {
4a0b9ca0
PW		 4240 adapter->tx_ring[i]->reg_idx = i << 5;
4241 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4242 }
4243 for ( ; i < 5; i++) {
4a0b9ca0 4244 adapter->tx_ring[i]->reg_idx =
e8e9f696 4245 ((i + 2) << 4);
4a0b9ca0 4246 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4247 }
4248 for ( ; i < dcb_i; i++) {
4a0b9ca0 4249 adapter->tx_ring[i]->reg_idx =
e8e9f696 4250 ((i + 8) << 3);
4a0b9ca0 4251 adapter->rx_ring[i]->reg_idx = i << 4;
f92ef202
PW		 4252 }
4253
4254 ret = true;
4255 } else if (dcb_i == 4) {
4256 /*
4257 * Tx TC0 starts at: descriptor queue 0
4258 * Tx TC1 starts at: descriptor queue 64
4259 * Tx TC2 starts at: descriptor queue 96
4260 * Tx TC3 starts at: descriptor queue 112
4261 *
4262 * Rx TC0-TC3 are offset by 32 queues each
4263 */
4a0b9ca0
PW		 4264 adapter->tx_ring[0]->reg_idx = 0;
4265 adapter->tx_ring[1]->reg_idx = 64;
4266 adapter->tx_ring[2]->reg_idx = 96;
4267 adapter->tx_ring[3]->reg_idx = 112;
f92ef202 4268 for (i = 0 ; i < dcb_i; i++)
4a0b9ca0 4269 adapter->rx_ring[i]->reg_idx = i << 5;
f92ef202
PW		 4270
4271 ret = true;
4272 } else {
4273 ret = false;
e8e26350 4274 }
bc97114d
PWJ		 4275 } else {
4276 ret = false;
021230d4 4277 }
bc97114d
PWJ		 4278 } else {
4279 ret = false;
021230d4 4280 }
bc97114d
PWJ		 4281
4282 return ret;
4283}
4284#endif
4285
c4cf55e5
PWJ		 4286/**
4287 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4288 * @adapter: board private structure to initialize
4289 *
4290 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4291 *
4292 **/
e8e9f696 4293static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4294{
4295 int i;
4296 bool ret = false;
4297
4298 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4299 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4300 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4301 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4302 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4303 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4304 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4305 ret = true;
4306 }
4307
4308 return ret;
4309}
4310
0331a832
YZ		 4311#ifdef IXGBE_FCOE
4312/**
4313 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4314 * @adapter: board private structure to initialize
4315 *
4316 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4317 *
4318 */
4319static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4320{
8de8b2e6 4321 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 4322 bool ret = false;
4323 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4324
4325 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4326#ifdef CONFIG_IXGBE_DCB
4327 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 4328 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4329
0331a832 4330 ixgbe_cache_ring_dcb(adapter);
8de8b2e6 4331 /* find out queues in TC for FCoE */
4a0b9ca0
PW		 4332 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4333 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
8de8b2e6
YZ		 4334 /*
4335 * In 82599, the number of Tx queues for each traffic
4336 * class for both 8-TC and 4-TC modes are:
4337 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4338 * 8 TCs: 32 32 16 16 8 8 8 8
4339 * 4 TCs: 64 64 32 32
4340 * We have max 8 queues for FCoE, where 8 the is
4341 * FCoE redirection table size. If TC for FCoE is
4342 * less than or equal to TC3, we have enough queues
4343 * to add max of 8 queues for FCoE, so we start FCoE
4344 * tx descriptor from the next one, i.e., reg_idx + 1.
4345 * If TC for FCoE is above TC3, implying 8 TC mode,
4346 * and we need 8 for FCoE, we have to take all queues
4347 * in that traffic class for FCoE.
4348 */
4349 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4350 fcoe_tx_i--;
0331a832
YZ		 4351 }
4352#endif /* CONFIG_IXGBE_DCB */
4353 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 4354 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4355 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4356 ixgbe_cache_ring_fdir(adapter);
4357 else
4358 ixgbe_cache_ring_rss(adapter);
4359
8de8b2e6
YZ		 4360 fcoe_rx_i = f->mask;
4361 fcoe_tx_i = f->mask;
4362 }
4363 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4a0b9ca0
PW		 4364 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4365 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
0331a832 4366 }
0331a832
YZ		 4367 ret = true;
4368 }
4369 return ret;
4370}
4371
4372#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4373/**
4374 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4375 * @adapter: board private structure to initialize
4376 *
4377 * SR-IOV doesn't use any descriptor rings but changes the default if
4378 * no other mapping is used.
4379 *
4380 */
4381static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4382{
4a0b9ca0
PW		 4383 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4384 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4385 if (adapter->num_vfs)
4386 return true;
4387 else
4388 return false;
4389}
4390
bc97114d
PWJ		 4391/**
4392 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4393 * @adapter: board private structure to initialize
4394 *
4395 * Once we know the feature-set enabled for the device, we'll cache
4396 * the register offset the descriptor ring is assigned to.
4397 *
4398 * Note, the order the various feature calls is important. It must start with
4399 * the "most" features enabled at the same time, then trickle down to the
4400 * least amount of features turned on at once.
4401 **/
4402static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4403{
4404 /* start with default case */
4a0b9ca0
PW		 4405 adapter->rx_ring[0]->reg_idx = 0;
4406 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4407
1cdd1ec8
GR		 4408 if (ixgbe_cache_ring_sriov(adapter))
4409 return;
4410
0331a832
YZ		 4411#ifdef IXGBE_FCOE
4412 if (ixgbe_cache_ring_fcoe(adapter))
4413 return;
4414
4415#endif /* IXGBE_FCOE */
bc97114d
PWJ		 4416#ifdef CONFIG_IXGBE_DCB
4417 if (ixgbe_cache_ring_dcb(adapter))
4418 return;
4419
4420#endif
c4cf55e5
PWJ		 4421 if (ixgbe_cache_ring_fdir(adapter))
4422 return;
4423
bc97114d
PWJ		 4424 if (ixgbe_cache_ring_rss(adapter))
4425 return;
021230d4
AV		 4426}
4427
9a799d71
AK		 4428/**
4429 * ixgbe_alloc_queues - Allocate memory for all rings
4430 * @adapter: board private structure to initialize
4431 *
4432 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4433 * number of queues at compile-time. The polling_netdev array is
4434 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4435 **/
2f90b865 4436static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 4437{
4438 int i;
4a0b9ca0 4439 int orig_node = adapter->node;
9a799d71 4440
021230d4 4441 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 4442 struct ixgbe_ring *ring = adapter->tx_ring[i];
4443 if (orig_node == -1) {
4444 int cur_node = next_online_node(adapter->node);
4445 if (cur_node == MAX_NUMNODES)
4446 cur_node = first_online_node;
4447 adapter->node = cur_node;
4448 }
4449 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4450 adapter->node);
4a0b9ca0
PW		 4451 if (!ring)
4452 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4453 if (!ring)
4454 goto err_tx_ring_allocation;
4455 ring->count = adapter->tx_ring_count;
4456 ring->queue_index = i;
4457 ring->numa_node = adapter->node;
4458
4459 adapter->tx_ring[i] = ring;
021230d4 4460 }
b9804972 4461
4a0b9ca0
PW		 4462 /* Restore the adapter's original node */
4463 adapter->node = orig_node;
4464
9a799d71 4465 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 4466 struct ixgbe_ring *ring = adapter->rx_ring[i];
4467 if (orig_node == -1) {
4468 int cur_node = next_online_node(adapter->node);
4469 if (cur_node == MAX_NUMNODES)
4470 cur_node = first_online_node;
4471 adapter->node = cur_node;
4472 }
4473 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
e8e9f696 4474 adapter->node);
4a0b9ca0
PW		 4475 if (!ring)
4476 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4477 if (!ring)
4478 goto err_rx_ring_allocation;
4479 ring->count = adapter->rx_ring_count;
4480 ring->queue_index = i;
4481 ring->numa_node = adapter->node;
4482
4483 adapter->rx_ring[i] = ring;
021230d4
AV		 4484 }
4485
4a0b9ca0
PW		 4486 /* Restore the adapter's original node */
4487 adapter->node = orig_node;
4488
021230d4
AV		 4489 ixgbe_cache_ring_register(adapter);
4490
4491 return 0;
4492
4493err_rx_ring_allocation:
4a0b9ca0
PW		 4494 for (i = 0; i < adapter->num_tx_queues; i++)
4495 kfree(adapter->tx_ring[i]);
021230d4
AV		 4496err_tx_ring_allocation:
4497 return -ENOMEM;
4498}
4499
4500/**
4501 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4502 * @adapter: board private structure to initialize
4503 *
4504 * Attempt to configure the interrupts using the best available
4505 * capabilities of the hardware and the kernel.
4506 **/
feea6a57 4507static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4508{
8be0e467 4509 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4510 int err = 0;
4511 int vector, v_budget;
4512
4513 /*
4514 * It's easy to be greedy for MSI-X vectors, but it really
4515 * doesn't do us much good if we have a lot more vectors
4516 * than CPU's. So let's be conservative and only ask for
342bde1b 4517 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4518 */
4519 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4520 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4521
4522 /*
4523 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4524 * hw.mac->max_msix_vectors vectors. With features
4525 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4526 * descriptor queues supported by our device. Thus, we cap it off in
4527 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4528 */
8be0e467 4529 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4530
4531 /* A failure in MSI-X entry allocation isn't fatal, but it does
4532 * mean we disable MSI-X capabilities of the adapter. */
4533 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4534 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4535 if (adapter->msix_entries) {
4536 for (vector = 0; vector < v_budget; vector++)
4537 adapter->msix_entries[vector].entry = vector;
021230d4 4538
7a921c93 4539 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4540
7a921c93
AD		 4541 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4542 goto out;
4543 }
26d27844 4544
7a921c93
AD		 4545 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4546 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 4547 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4548 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4549 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4550 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4551 ixgbe_disable_sriov(adapter);
4552
7a921c93 4553 ixgbe_set_num_queues(adapter);
021230d4 4554
021230d4
AV		 4555 err = pci_enable_msi(adapter->pdev);
4556 if (!err) {
4557 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4558 } else {
849c4542
ET		 4559 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4560 "Unable to allocate MSI interrupt, "
4561 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4562 /* reset err */
4563 err = 0;
4564 }
4565
4566out:
021230d4
AV		 4567 return err;
4568}
4569
7a921c93
AD		 4570/**
4571 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4572 * @adapter: board private structure to initialize
4573 *
4574 * We allocate one q_vector per queue interrupt. If allocation fails we
4575 * return -ENOMEM.
4576 **/
4577static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4578{
4579 int q_idx, num_q_vectors;
4580 struct ixgbe_q_vector *q_vector;
4581 int napi_vectors;
4582 int (*poll)(struct napi_struct *, int);
4583
4584 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4585 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4586 napi_vectors = adapter->num_rx_queues;
91281fd3 4587 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4588 } else {
4589 num_q_vectors = 1;
4590 napi_vectors = 1;
4591 poll = &ixgbe_poll;
4592 }
4593
4594 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4595 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4596 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4597 if (!q_vector)
4598 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4599 GFP_KERNEL);
7a921c93
AD		 4600 if (!q_vector)
4601 goto err_out;
4602 q_vector->adapter = adapter;
f7554a2b
NS		 4603 if (q_vector->txr_count && !q_vector->rxr_count)
4604 q_vector->eitr = adapter->tx_eitr_param;
4605 else
4606 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4607 q_vector->v_idx = q_idx;
91281fd3 4608 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4609 adapter->q_vector[q_idx] = q_vector;
4610 }
4611
4612 return 0;
4613
4614err_out:
4615 while (q_idx) {
4616 q_idx--;
4617 q_vector = adapter->q_vector[q_idx];
4618 netif_napi_del(&q_vector->napi);
4619 kfree(q_vector);
4620 adapter->q_vector[q_idx] = NULL;
4621 }
4622 return -ENOMEM;
4623}
4624
4625/**
4626 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4627 * @adapter: board private structure to initialize
4628 *
4629 * This function frees the memory allocated to the q_vectors. In addition if
4630 * NAPI is enabled it will delete any references to the NAPI struct prior
4631 * to freeing the q_vector.
4632 **/
4633static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4634{
4635 int q_idx, num_q_vectors;
7a921c93 4636
91281fd3 4637 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4638 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4639 else
7a921c93 4640 num_q_vectors = 1;
7a921c93
AD		 4641
4642 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4643 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4644 adapter->q_vector[q_idx] = NULL;
91281fd3 4645 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4646 kfree(q_vector);
4647 }
4648}
4649
7b25cdba 4650static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4651{
4652 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4653 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4654 pci_disable_msix(adapter->pdev);
4655 kfree(adapter->msix_entries);
4656 adapter->msix_entries = NULL;
4657 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4658 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4659 pci_disable_msi(adapter->pdev);
4660 }
021230d4
AV		 4661}
4662
4663/**
4664 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4665 * @adapter: board private structure to initialize
4666 *
4667 * We determine which interrupt scheme to use based on...
4668 * - Kernel support (MSI, MSI-X)
4669 * - which can be user-defined (via MODULE_PARAM)
4670 * - Hardware queue count (num_*_queues)
4671 * - defined by miscellaneous hardware support/features (RSS, etc.)
4672 **/
2f90b865 4673int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4674{
4675 int err;
4676
4677 /* Number of supported queues */
4678 ixgbe_set_num_queues(adapter);
4679
021230d4
AV		 4680 err = ixgbe_set_interrupt_capability(adapter);
4681 if (err) {
849c4542 4682 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4683 goto err_set_interrupt;
9a799d71
AK		 4684 }
4685
7a921c93
AD		 4686 err = ixgbe_alloc_q_vectors(adapter);
4687 if (err) {
849c4542 4688 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4689 goto err_alloc_q_vectors;
4690 }
4691
4692 err = ixgbe_alloc_queues(adapter);
4693 if (err) {
849c4542 4694 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4695 goto err_alloc_queues;
4696 }
4697
849c4542 4698 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4699 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4700 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4701
4702 set_bit(__IXGBE_DOWN, &adapter->state);
4703
9a799d71 4704 return 0;
021230d4 4705
7a921c93
AD		 4706err_alloc_queues:
4707 ixgbe_free_q_vectors(adapter);
4708err_alloc_q_vectors:
4709 ixgbe_reset_interrupt_capability(adapter);
021230d4 4710err_set_interrupt:
7a921c93
AD		 4711 return err;
4712}
4713
4714/**
4715 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4716 * @adapter: board private structure to clear interrupt scheme on
4717 *
4718 * We go through and clear interrupt specific resources and reset the structure
4719 * to pre-load conditions
4720 **/
4721void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4722{
4a0b9ca0
PW		 4723 int i;
4724
4725 for (i = 0; i < adapter->num_tx_queues; i++) {
4726 kfree(adapter->tx_ring[i]);
4727 adapter->tx_ring[i] = NULL;
4728 }
4729 for (i = 0; i < adapter->num_rx_queues; i++) {
4730 kfree(adapter->rx_ring[i]);
4731 adapter->rx_ring[i] = NULL;
4732 }
7a921c93
AD		 4733
4734 ixgbe_free_q_vectors(adapter);
4735 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4736}
4737
c4900be0
DS		 4738/**
4739 * ixgbe_sfp_timer - worker thread to find a missing module
4740 * @data: pointer to our adapter struct
4741 **/
4742static void ixgbe_sfp_timer(unsigned long data)
4743{
4744 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4745
4df10466
JB		 4746 /*
4747 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 4748 * delays that sfp+ detection requires
4749 */
4750 schedule_work(&adapter->sfp_task);
4751}
4752
4753/**
4754 * ixgbe_sfp_task - worker thread to find a missing module
4755 * @work: pointer to work_struct containing our data
4756 **/
4757static void ixgbe_sfp_task(struct work_struct *work)
4758{
4759 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 4760 struct ixgbe_adapter,
4761 sfp_task);
c4900be0
DS		 4762 struct ixgbe_hw *hw = &adapter->hw;
4763
4764 if ((hw->phy.type == ixgbe_phy_nl) &&
4765 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4766 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4767 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 4768 goto reschedule;
4769 ret = hw->phy.ops.reset(hw);
4770 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 4771 e_dev_err("failed to initialize because an unsupported "
4772 "SFP+ module type was detected.\n");
4773 e_dev_err("Reload the driver after installing a "
4774 "supported module.\n");
c4900be0
DS		 4775 unregister_netdev(adapter->netdev);
4776 } else {
396e799c 4777 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
c4900be0
DS		 4778 }
4779 /* don't need this routine any more */
4780 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4781 }
4782 return;
4783reschedule:
4784 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4785 mod_timer(&adapter->sfp_timer,
e8e9f696 4786 round_jiffies(jiffies + (2 * HZ)));
c4900be0
DS		 4787}
4788
9a799d71
AK		 4789/**
4790 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4791 * @adapter: board private structure to initialize
4792 *
4793 * ixgbe_sw_init initializes the Adapter private data structure.
4794 * Fields are initialized based on PCI device information and
4795 * OS network device settings (MTU size).
4796 **/
4797static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4798{
4799 struct ixgbe_hw *hw = &adapter->hw;
4800 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4801 struct net_device *dev = adapter->netdev;
021230d4 4802 unsigned int rss;
7a6b6f51 4803#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4804 int j;
4805 struct tc_configuration *tc;
4806#endif
021230d4 4807
c44ade9e
JB		 4808 /* PCI config space info */
4809
4810 hw->vendor_id = pdev->vendor;
4811 hw->device_id = pdev->device;
4812 hw->revision_id = pdev->revision;
4813 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4814 hw->subsystem_device_id = pdev->subsystem_device;
4815
021230d4
AV		 4816 /* Set capability flags */
4817 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4818 adapter->ring_feature[RING_F_RSS].indices = rss;
4819 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 4820 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 4821 if (hw->mac.type == ixgbe_mac_82598EB) {
4822 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4823 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4824 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 4825 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 4826 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4827 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4828 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4829 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4830 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
9a713e7c
PW		 4831 if (dev->features & NETIF_F_NTUPLE) {
4832 /* Flow Director perfect filter enabled */
4833 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4834 adapter->atr_sample_rate = 0;
4835 spin_lock_init(&adapter->fdir_perfect_lock);
4836 } else {
4837 /* Flow Director hash filters enabled */
4838 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4839 adapter->atr_sample_rate = 20;
4840 }
c4cf55e5 4841 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4842 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 4843 adapter->fdir_pballoc = 0;
eacd73f7 4844#ifdef IXGBE_FCOE
0d551589
YZ		 4845 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4846 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4847 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4848#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 4849 /* Default traffic class to use for FCoE */
4850 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 4851 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4852#endif
eacd73f7 4853#endif /* IXGBE_FCOE */
f8212f97 4854 }
2f90b865 4855
7a6b6f51 4856#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4857 /* Configure DCB traffic classes */
4858 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4859 tc = &adapter->dcb_cfg.tc_config[j];
4860 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4861 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4862 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4863 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4864 tc->dcb_pfc = pfc_disabled;
4865 }
4866 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4867 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4868 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 4869 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 4870 adapter->dcb_cfg.round_robin_enable = false;
4871 adapter->dcb_set_bitmap = 0x00;
4872 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e8e9f696 4873 adapter->ring_feature[RING_F_DCB].indices);
2f90b865
AD		 4874
4875#endif
9a799d71
AK		 4876
4877 /* default flow control settings */
cd7664f6 4878 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4879 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4880#ifdef CONFIG_DCB
4881 adapter->last_lfc_mode = hw->fc.current_mode;
4882#endif
2b9ade93
JB		 4883 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4884 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4885 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4886 hw->fc.send_xon = true;
71fd570b 4887 hw->fc.disable_fc_autoneg = false;
9a799d71 4888
30efa5a3 4889 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4890 adapter->rx_itr_setting = 1;
4891 adapter->rx_eitr_param = 20000;
4892 adapter->tx_itr_setting = 1;
4893 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4894
4895 /* set defaults for eitr in MegaBytes */
4896 adapter->eitr_low = 10;
4897 adapter->eitr_high = 20;
4898
4899 /* set default ring sizes */
4900 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4901 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4902
9a799d71 4903 /* initialize eeprom parameters */
c44ade9e 4904 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4905 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4906 return -EIO;
4907 }
4908
021230d4 4909 /* enable rx csum by default */
9a799d71
AK		 4910 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4911
1a6c14a2
JB		 4912 /* get assigned NUMA node */
4913 adapter->node = dev_to_node(&pdev->dev);
4914
9a799d71
AK		 4915 set_bit(__IXGBE_DOWN, &adapter->state);
4916
4917 return 0;
4918}
4919
4920/**
4921 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4922 * @adapter: board private structure
3a581073 4923 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4924 *
4925 * Return 0 on success, negative on failure
4926 **/
4927int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4928 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4929{
4930 struct pci_dev *pdev = adapter->pdev;
4931 int size;
4932
3a581073 4933 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4a0b9ca0 4934 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
1a6c14a2
JB		 4935 if (!tx_ring->tx_buffer_info)
4936 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 4937 if (!tx_ring->tx_buffer_info)
4938 goto err;
3a581073 4939 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 4940
4941 /* round up to nearest 4K */
12207e49 4942 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4943 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4944
1b507730
NN		 4945 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4946 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4947 if (!tx_ring->desc)
4948 goto err;
9a799d71 4949
3a581073
JB		 4950 tx_ring->next_to_use = 0;
4951 tx_ring->next_to_clean = 0;
4952 tx_ring->work_limit = tx_ring->count;
9a799d71 4953 return 0;
e01c31a5
JB		 4954
4955err:
4956 vfree(tx_ring->tx_buffer_info);
4957 tx_ring->tx_buffer_info = NULL;
396e799c 4958 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4959 return -ENOMEM;
9a799d71
AK		 4960}
4961
69888674
AD		 4962/**
4963 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4964 * @adapter: board private structure
4965 *
4966 * If this function returns with an error, then it's possible one or
4967 * more of the rings is populated (while the rest are not). It is the
4968 * callers duty to clean those orphaned rings.
4969 *
4970 * Return 0 on success, negative on failure
4971 **/
4972static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4973{
4974 int i, err = 0;
4975
4976 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 4977 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
69888674
AD		 4978 if (!err)
4979 continue;
396e799c 4980 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4981 break;
4982 }
4983
4984 return err;
4985}
4986
9a799d71
AK		 4987/**
4988 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4989 * @adapter: board private structure
3a581073 4990 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4991 *
4992 * Returns 0 on success, negative on failure
4993 **/
4994int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 4995 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4996{
4997 struct pci_dev *pdev = adapter->pdev;
021230d4 4998 int size;
9a799d71 4999
3a581073 5000 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1a6c14a2
JB		 5001 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5002 if (!rx_ring->rx_buffer_info)
5003 rx_ring->rx_buffer_info = vmalloc(size);
3a581073 5004 if (!rx_ring->rx_buffer_info) {
396e799c
ET		 5005 e_err(probe, "vmalloc allocation failed for the Rx "
5006 "descriptor ring\n");
177db6ff 5007 goto alloc_failed;
9a799d71 5008 }
3a581073 5009 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 5010
9a799d71 5011 /* Round up to nearest 4K */
3a581073
JB		 5012 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5013 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5014
1b507730
NN		 5015 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5016 &rx_ring->dma, GFP_KERNEL);
9a799d71 5017
3a581073 5018 if (!rx_ring->desc) {
396e799c
ET		 5019 e_err(probe, "Memory allocation failed for the Rx "
5020 "descriptor ring\n");
3a581073 5021 vfree(rx_ring->rx_buffer_info);
177db6ff 5022 goto alloc_failed;
9a799d71
AK		 5023 }
5024
3a581073
JB		 5025 rx_ring->next_to_clean = 0;
5026 rx_ring->next_to_use = 0;
9a799d71
AK		 5027
5028 return 0;
177db6ff
MC		 5029
5030alloc_failed:
177db6ff 5031 return -ENOMEM;
9a799d71
AK		 5032}
5033
69888674
AD		 5034/**
5035 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5036 * @adapter: board private structure
5037 *
5038 * If this function returns with an error, then it's possible one or
5039 * more of the rings is populated (while the rest are not). It is the
5040 * callers duty to clean those orphaned rings.
5041 *
5042 * Return 0 on success, negative on failure
5043 **/
5044
5045static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5046{
5047 int i, err = 0;
5048
5049 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 5050 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
69888674
AD		 5051 if (!err)
5052 continue;
396e799c 5053 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5054 break;
5055 }
5056
5057 return err;
5058}
5059
9a799d71
AK		 5060/**
5061 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5062 * @adapter: board private structure
5063 * @tx_ring: Tx descriptor ring for a specific queue
5064 *
5065 * Free all transmit software resources
5066 **/
c431f97e 5067void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5068 struct ixgbe_ring *tx_ring)
9a799d71
AK		 5069{
5070 struct pci_dev *pdev = adapter->pdev;
5071
5072 ixgbe_clean_tx_ring(adapter, tx_ring);
5073
5074 vfree(tx_ring->tx_buffer_info);
5075 tx_ring->tx_buffer_info = NULL;
5076
1b507730
NN		 5077 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5078 tx_ring->dma);
9a799d71
AK		 5079
5080 tx_ring->desc = NULL;
5081}
5082
5083/**
5084 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5085 * @adapter: board private structure
5086 *
5087 * Free all transmit software resources
5088 **/
5089static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5090{
5091 int i;
5092
5093 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0
PW		 5094 if (adapter->tx_ring[i]->desc)
5095 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
9a799d71
AK		 5096}
5097
5098/**
b4617240 5099 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5100 * @adapter: board private structure
5101 * @rx_ring: ring to clean the resources from
5102 *
5103 * Free all receive software resources
5104 **/
c431f97e 5105void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
e8e9f696 5106 struct ixgbe_ring *rx_ring)
9a799d71
AK		 5107{
5108 struct pci_dev *pdev = adapter->pdev;
5109
5110 ixgbe_clean_rx_ring(adapter, rx_ring);
5111
5112 vfree(rx_ring->rx_buffer_info);
5113 rx_ring->rx_buffer_info = NULL;
5114
1b507730
NN		 5115 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5116 rx_ring->dma);
9a799d71
AK		 5117
5118 rx_ring->desc = NULL;
5119}
5120
5121/**
5122 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5123 * @adapter: board private structure
5124 *
5125 * Free all receive software resources
5126 **/
5127static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5128{
5129 int i;
5130
5131 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0
PW		 5132 if (adapter->rx_ring[i]->desc)
5133 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
9a799d71
AK		 5134}
5135
9a799d71
AK		 5136/**
5137 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5138 * @netdev: network interface device structure
5139 * @new_mtu: new value for maximum frame size
5140 *
5141 * Returns 0 on success, negative on failure
5142 **/
5143static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5144{
5145 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5146 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5147
42c783c5
JB		 5148 /* MTU < 68 is an error and causes problems on some kernels */
5149 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 5150 return -EINVAL;
5151
396e799c 5152 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5153 /* must set new MTU before calling down or up */
9a799d71
AK		 5154 netdev->mtu = new_mtu;
5155
d4f80882
AV		 5156 if (netif_running(netdev))
5157 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5158
5159 return 0;
5160}
5161
5162/**
5163 * ixgbe_open - Called when a network interface is made active
5164 * @netdev: network interface device structure
5165 *
5166 * Returns 0 on success, negative value on failure
5167 *
5168 * The open entry point is called when a network interface is made
5169 * active by the system (IFF_UP). At this point all resources needed
5170 * for transmit and receive operations are allocated, the interrupt
5171 * handler is registered with the OS, the watchdog timer is started,
5172 * and the stack is notified that the interface is ready.
5173 **/
5174static int ixgbe_open(struct net_device *netdev)
5175{
5176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5177 int err;
4bebfaa5
AK		 5178
5179 /* disallow open during test */
5180 if (test_bit(__IXGBE_TESTING, &adapter->state))
5181 return -EBUSY;
9a799d71 5182
54386467
JB		 5183 netif_carrier_off(netdev);
5184
9a799d71
AK		 5185 /* allocate transmit descriptors */
5186 err = ixgbe_setup_all_tx_resources(adapter);
5187 if (err)
5188 goto err_setup_tx;
5189
9a799d71
AK		 5190 /* allocate receive descriptors */
5191 err = ixgbe_setup_all_rx_resources(adapter);
5192 if (err)
5193 goto err_setup_rx;
5194
5195 ixgbe_configure(adapter);
5196
021230d4 5197 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5198 if (err)
5199 goto err_req_irq;
5200
9a799d71
AK		 5201 err = ixgbe_up_complete(adapter);
5202 if (err)
5203 goto err_up;
5204
d55b53ff
JK		 5205 netif_tx_start_all_queues(netdev);
5206
9a799d71
AK		 5207 return 0;
5208
5209err_up:
5eba3699 5210 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5211 ixgbe_free_irq(adapter);
5212err_req_irq:
9a799d71 5213err_setup_rx:
a20a1199 5214 ixgbe_free_all_rx_resources(adapter);
9a799d71 5215err_setup_tx:
a20a1199 5216 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5217 ixgbe_reset(adapter);
5218
5219 return err;
5220}
5221
5222/**
5223 * ixgbe_close - Disables a network interface
5224 * @netdev: network interface device structure
5225 *
5226 * Returns 0, this is not allowed to fail
5227 *
5228 * The close entry point is called when an interface is de-activated
5229 * by the OS. The hardware is still under the drivers control, but
5230 * needs to be disabled. A global MAC reset is issued to stop the
5231 * hardware, and all transmit and receive resources are freed.
5232 **/
5233static int ixgbe_close(struct net_device *netdev)
5234{
5235 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5236
5237 ixgbe_down(adapter);
5238 ixgbe_free_irq(adapter);
5239
5240 ixgbe_free_all_tx_resources(adapter);
5241 ixgbe_free_all_rx_resources(adapter);
5242
5eba3699 5243 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5244
5245 return 0;
5246}
5247
b3c8b4ba
AD		 5248#ifdef CONFIG_PM
5249static int ixgbe_resume(struct pci_dev *pdev)
5250{
5251 struct net_device *netdev = pci_get_drvdata(pdev);
5252 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5253 u32 err;
5254
5255 pci_set_power_state(pdev, PCI_D0);
5256 pci_restore_state(pdev);
656ab817
DS		 5257 /*
5258 * pci_restore_state clears dev->state_saved so call
5259 * pci_save_state to restore it.
5260 */
5261 pci_save_state(pdev);
9ce77666 5262
5263 err = pci_enable_device_mem(pdev);
b3c8b4ba 5264 if (err) {
849c4542 5265 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5266 return err;
5267 }
5268 pci_set_master(pdev);
5269
dd4d8ca6 5270 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5271
5272 err = ixgbe_init_interrupt_scheme(adapter);
5273 if (err) {
849c4542 5274 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5275 return err;
5276 }
5277
b3c8b4ba
AD		 5278 ixgbe_reset(adapter);
5279
495dce12
WJP		 5280 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5281
b3c8b4ba
AD		 5282 if (netif_running(netdev)) {
5283 err = ixgbe_open(adapter->netdev);
5284 if (err)
5285 return err;
5286 }
5287
5288 netif_device_attach(netdev);
5289
5290 return 0;
5291}
b3c8b4ba 5292#endif /* CONFIG_PM */
9d8d05ae
RW		 5293
5294static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 5295{
5296 struct net_device *netdev = pci_get_drvdata(pdev);
5297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 5298 struct ixgbe_hw *hw = &adapter->hw;
5299 u32 ctrl, fctrl;
5300 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5301#ifdef CONFIG_PM
5302 int retval = 0;
5303#endif
5304
5305 netif_device_detach(netdev);
5306
5307 if (netif_running(netdev)) {
5308 ixgbe_down(adapter);
5309 ixgbe_free_irq(adapter);
5310 ixgbe_free_all_tx_resources(adapter);
5311 ixgbe_free_all_rx_resources(adapter);
5312 }
b3c8b4ba
AD		 5313
5314#ifdef CONFIG_PM
5315 retval = pci_save_state(pdev);
5316 if (retval)
5317 return retval;
4df10466 5318
b3c8b4ba 5319#endif
e8e26350
PW		 5320 if (wufc) {
5321 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5322
e8e26350
PW		 5323 /* turn on all-multi mode if wake on multicast is enabled */
5324 if (wufc & IXGBE_WUFC_MC) {
5325 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5326 fctrl |= IXGBE_FCTRL_MPE;
5327 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5328 }
5329
5330 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5331 ctrl |= IXGBE_CTRL_GIO_DIS;
5332 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5333
5334 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5335 } else {
5336 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5337 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5338 }
5339
dd4d8ca6
DS		 5340 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5341 pci_wake_from_d3(pdev, true);
5342 else
5343 pci_wake_from_d3(pdev, false);
b3c8b4ba 5344
9d8d05ae
RW		 5345 *enable_wake = !!wufc;
5346
fa378134
AG		 5347 ixgbe_clear_interrupt_scheme(adapter);
5348
b3c8b4ba
AD		 5349 ixgbe_release_hw_control(adapter);
5350
5351 pci_disable_device(pdev);
5352
9d8d05ae
RW		 5353 return 0;
5354}
5355
5356#ifdef CONFIG_PM
5357static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5358{
5359 int retval;
5360 bool wake;
5361
5362 retval = __ixgbe_shutdown(pdev, &wake);
5363 if (retval)
5364 return retval;
5365
5366 if (wake) {
5367 pci_prepare_to_sleep(pdev);
5368 } else {
5369 pci_wake_from_d3(pdev, false);
5370 pci_set_power_state(pdev, PCI_D3hot);
5371 }
b3c8b4ba
AD		 5372
5373 return 0;
5374}
9d8d05ae 5375#endif /* CONFIG_PM */
b3c8b4ba
AD		 5376
5377static void ixgbe_shutdown(struct pci_dev *pdev)
5378{
9d8d05ae
RW		 5379 bool wake;
5380
5381 __ixgbe_shutdown(pdev, &wake);
5382
5383 if (system_state == SYSTEM_POWER_OFF) {
5384 pci_wake_from_d3(pdev, wake);
5385 pci_set_power_state(pdev, PCI_D3hot);
5386 }
b3c8b4ba
AD		 5387}
5388
9a799d71
AK		 5389/**
5390 * ixgbe_update_stats - Update the board statistics counters.
5391 * @adapter: board private structure
5392 **/
5393void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5394{
2d86f139 5395 struct net_device *netdev = adapter->netdev;
9a799d71 5396 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 5397 u64 total_mpc = 0;
5398 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
eb985f09 5399 u64 non_eop_descs = 0, restart_queue = 0;
9a799d71 5400
d08935c2
DS		 5401 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5402 test_bit(__IXGBE_RESETTING, &adapter->state))
5403 return;
5404
94b982b2 5405 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5406 u64 rsc_count = 0;
94b982b2 5407 u64 rsc_flush = 0;
d51019a4
PW		 5408 for (i = 0; i < 16; i++)
5409 adapter->hw_rx_no_dma_resources +=
e8e9f696 5410 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5411 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 5412 rsc_count += adapter->rx_ring[i]->rsc_count;
5413 rsc_flush += adapter->rx_ring[i]->rsc_flush;
94b982b2
MC		 5414 }
5415 adapter->rsc_total_count = rsc_count;
5416 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5417 }
5418
7ca3bc58
JB		 5419 /* gather some stats to the adapter struct that are per queue */
5420 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5421 restart_queue += adapter->tx_ring[i]->restart_queue;
eb985f09 5422 adapter->restart_queue = restart_queue;
7ca3bc58
JB		 5423
5424 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5425 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
eb985f09 5426 adapter->non_eop_descs = non_eop_descs;
7ca3bc58 5427
9a799d71 5428 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5429 for (i = 0; i < 8; i++) {
5430 /* for packet buffers not used, the register should read 0 */
5431 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5432 missed_rx += mpc;
5433 adapter->stats.mpc[i] += mpc;
5434 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 5435 if (hw->mac.type == ixgbe_mac_82598EB)
5436 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 5437 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5438 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5439 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5440 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 5441 if (hw->mac.type == ixgbe_mac_82599EB) {
5442 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5443 IXGBE_PXONRXCNT(i));
e8e26350 5444 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5445 IXGBE_PXOFFRXCNT(i));
e8e26350 5446 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 5447 } else {
5448 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5449 IXGBE_PXONRXC(i));
e8e26350 5450 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5451 IXGBE_PXOFFRXC(i));
e8e26350 5452 }
2f90b865 5453 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5454 IXGBE_PXONTXC(i));
2f90b865 5455 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e9f696 5456 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 5457 }
5458 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5459 /* work around hardware counting issue */
5460 adapter->stats.gprc -= missed_rx;
5461
5462 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 5463 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 5464 u64 tmp;
e8e26350 5465 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
e8e9f696
JP		 5466 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5467 /* 4 high bits of GORC */
aad71918 5468 adapter->stats.gorc += (tmp << 32);
e8e26350 5469 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
e8e9f696
JP		 5470 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5471 /* 4 high bits of GOTC */
aad71918 5472 adapter->stats.gotc += (tmp << 32);
e8e26350 5473 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
e8e9f696 5474 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
e8e26350
PW		 5475 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5476 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 5477 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5478 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 5479#ifdef IXGBE_FCOE
5480 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5481 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5482 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5483 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5484 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5485 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5486#endif /* IXGBE_FCOE */
e8e26350
PW		 5487 } else {
5488 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5489 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5490 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5491 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5492 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5493 }
9a799d71
AK		 5494 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5495 adapter->stats.bprc += bprc;
5496 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 5497 if (hw->mac.type == ixgbe_mac_82598EB)
5498 adapter->stats.mprc -= bprc;
9a799d71
AK		 5499 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5500 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5501 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5502 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5503 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5504 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5505 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 5506 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 5507 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5508 adapter->stats.lxontxc += lxon;
5509 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5510 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 5511 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5512 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 5513 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5514 /*
5515 * 82598 errata - tx of flow control packets is included in tx counters
5516 */
5517 xon_off_tot = lxon + lxoff;
5518 adapter->stats.gptc -= xon_off_tot;
5519 adapter->stats.mptc -= xon_off_tot;
5520 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 5521 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5522 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5523 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 5524 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5525 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 5526 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 5527 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5528 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5529 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5530 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5531 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 5532 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5533
5534 /* Fill out the OS statistics structure */
2d86f139 5535 netdev->stats.multicast = adapter->stats.mprc;
9a799d71
AK		 5536
5537 /* Rx Errors */
2d86f139 5538 netdev->stats.rx_errors = adapter->stats.crcerrs +
e8e9f696 5539 adapter->stats.rlec;
2d86f139
AK		 5540 netdev->stats.rx_dropped = 0;
5541 netdev->stats.rx_length_errors = adapter->stats.rlec;
5542 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5543 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5544}
5545
5546/**
5547 * ixgbe_watchdog - Timer Call-back
5548 * @data: pointer to adapter cast into an unsigned long
5549 **/
5550static void ixgbe_watchdog(unsigned long data)
5551{
5552 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 5553 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5554 u64 eics = 0;
5555 int i;
cf8280ee 5556
fe49f04a
AD		 5557 /*
5558 * Do the watchdog outside of interrupt context due to the lovely
5559 * delays that some of the newer hardware requires
5560 */
22d5a71b 5561
fe49f04a
AD		 5562 if (test_bit(__IXGBE_DOWN, &adapter->state))
5563 goto watchdog_short_circuit;
22d5a71b 5564
fe49f04a
AD		 5565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5566 /*
5567 * for legacy and MSI interrupts don't set any bits
5568 * that are enabled for EIAM, because this operation
5569 * would set *both* EIMS and EICS for any bit in EIAM
5570 */
5571 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5572 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5573 goto watchdog_reschedule;
5574 }
5575
5576 /* get one bit for every active tx/rx interrupt vector */
5577 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5578 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5579 if (qv->rxr_count || qv->txr_count)
5580 eics |= ((u64)1 << i);
cf8280ee 5581 }
9a799d71 5582
fe49f04a
AD		 5583 /* Cause software interrupt to ensure rx rings are cleaned */
5584 ixgbe_irq_rearm_queues(adapter, eics);
5585
5586watchdog_reschedule:
5587 /* Reset the timer */
5588 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5589
5590watchdog_short_circuit:
cf8280ee
JB		 5591 schedule_work(&adapter->watchdog_task);
5592}
5593
e8e26350
PW		 5594/**
5595 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5596 * @work: pointer to work_struct containing our data
5597 **/
5598static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5599{
5600 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5601 struct ixgbe_adapter,
5602 multispeed_fiber_task);
e8e26350
PW		 5603 struct ixgbe_hw *hw = &adapter->hw;
5604 u32 autoneg;
8620a103 5605 bool negotiation;
e8e26350
PW		 5606
5607 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 5608 autoneg = hw->phy.autoneg_advertised;
5609 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103 5610 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
1097cd17 5611 hw->mac.autotry_restart = false;
8620a103
MC		 5612 if (hw->mac.ops.setup_link)
5613 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 5614 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5615 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5616}
5617
5618/**
5619 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5620 * @work: pointer to work_struct containing our data
5621 **/
5622static void ixgbe_sfp_config_module_task(struct work_struct *work)
5623{
5624 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5625 struct ixgbe_adapter,
5626 sfp_config_module_task);
e8e26350
PW		 5627 struct ixgbe_hw *hw = &adapter->hw;
5628 u32 err;
5629
5630 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 5631
5632 /* Time for electrical oscillations to settle down */
5633 msleep(100);
e8e26350 5634 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 5635
e8e26350 5636 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 5637 e_dev_err("failed to initialize because an unsupported SFP+ "
5638 "module type was detected.\n");
5639 e_dev_err("Reload the driver after installing a supported "
5640 "module.\n");
63d6e1d8 5641 unregister_netdev(adapter->netdev);
e8e26350
PW		 5642 return;
5643 }
5644 hw->mac.ops.setup_sfp(hw);
5645
8d1c3c07 5646 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 5647 /* This will also work for DA Twinax connections */
5648 schedule_work(&adapter->multispeed_fiber_task);
5649 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5650}
5651
c4cf55e5
PWJ		 5652/**
5653 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5654 * @work: pointer to work_struct containing our data
5655 **/
5656static void ixgbe_fdir_reinit_task(struct work_struct *work)
5657{
5658 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5659 struct ixgbe_adapter,
5660 fdir_reinit_task);
c4cf55e5
PWJ		 5661 struct ixgbe_hw *hw = &adapter->hw;
5662 int i;
5663
5664 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5665 for (i = 0; i < adapter->num_tx_queues; i++)
5666 set_bit(__IXGBE_FDIR_INIT_DONE,
e8e9f696 5667 &(adapter->tx_ring[i]->reinit_state));
c4cf55e5 5668 } else {
396e799c 5669 e_err(probe, "failed to finish FDIR re-initialization, "
849c4542 5670 "ignored adding FDIR ATR filters\n");
c4cf55e5
PWJ		 5671 }
5672 /* Done FDIR Re-initialization, enable transmits */
5673 netif_tx_start_all_queues(adapter->netdev);
5674}
5675
10eec955
JF		 5676static DEFINE_MUTEX(ixgbe_watchdog_lock);
5677
cf8280ee 5678/**
69888674
AD		 5679 * ixgbe_watchdog_task - worker thread to bring link up
5680 * @work: pointer to work_struct containing our data
cf8280ee
JB		 5681 **/
5682static void ixgbe_watchdog_task(struct work_struct *work)
5683{
5684 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 5685 struct ixgbe_adapter,
5686 watchdog_task);
cf8280ee
JB		 5687 struct net_device *netdev = adapter->netdev;
5688 struct ixgbe_hw *hw = &adapter->hw;
10eec955
JF		 5689 u32 link_speed;
5690 bool link_up;
bc59fcda
NS		 5691 int i;
5692 struct ixgbe_ring *tx_ring;
5693 int some_tx_pending = 0;
cf8280ee 5694
10eec955
JF		 5695 mutex_lock(&ixgbe_watchdog_lock);
5696
5697 link_up = adapter->link_up;
5698 link_speed = adapter->link_speed;
cf8280ee
JB		 5699
5700 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5701 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 5702 if (link_up) {
5703#ifdef CONFIG_DCB
5704 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5705 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 5706 hw->mac.ops.fc_enable(hw, i);
264857b8 5707 } else {
620fa036 5708 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5709 }
5710#else
620fa036 5711 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 5712#endif
5713 }
5714
cf8280ee
JB		 5715 if (link_up ||
5716 time_after(jiffies, (adapter->link_check_timeout +
e8e9f696 5717 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 5718 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 5719 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 5720 }
5721 adapter->link_up = link_up;
5722 adapter->link_speed = link_speed;
5723 }
9a799d71
AK		 5724
5725 if (link_up) {
5726 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 5727 bool flow_rx, flow_tx;
5728
5729 if (hw->mac.type == ixgbe_mac_82599EB) {
5730 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5731 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 5732 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5733 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 5734 } else {
5735 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5736 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 5737 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5738 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 5739 }
5740
396e799c 5741 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
a46e534b 5742 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
849c4542
ET		 5743 "10 Gbps" :
5744 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5745 "1 Gbps" : "unknown speed")),
e8e26350 5746 ((flow_rx && flow_tx) ? "RX/TX" :
849c4542
ET		 5747 (flow_rx ? "RX" :
5748 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 5749
5750 netif_carrier_on(netdev);
9a799d71
AK		 5751 } else {
5752 /* Force detection of hung controller */
5753 adapter->detect_tx_hung = true;
5754 }
5755 } else {
cf8280ee
JB		 5756 adapter->link_up = false;
5757 adapter->link_speed = 0;
9a799d71 5758 if (netif_carrier_ok(netdev)) {
396e799c 5759 e_info(drv, "NIC Link is Down\n");
9a799d71 5760 netif_carrier_off(netdev);
9a799d71
AK		 5761 }
5762 }
5763
bc59fcda
NS		 5764 if (!netif_carrier_ok(netdev)) {
5765 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0 5766 tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5767 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5768 some_tx_pending = 1;
5769 break;
5770 }
5771 }
5772
5773 if (some_tx_pending) {
5774 /* We've lost link, so the controller stops DMA,
5775 * but we've got queued Tx work that's never going
5776 * to get done, so reset controller to flush Tx.
5777 * (Do the reset outside of interrupt context).
5778 */
5779 schedule_work(&adapter->reset_task);
5780 }
5781 }
5782
9a799d71 5783 ixgbe_update_stats(adapter);
10eec955 5784 mutex_unlock(&ixgbe_watchdog_lock);
9a799d71
AK		 5785}
5786
9a799d71 5787static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5788 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5789 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 5790{
5791 struct ixgbe_adv_tx_context_desc *context_desc;
5792 unsigned int i;
5793 int err;
5794 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 5795 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5796 u32 mss_l4len_idx, l4len;
9a799d71
AK		 5797
5798 if (skb_is_gso(skb)) {
5799 if (skb_header_cloned(skb)) {
5800 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5801 if (err)
5802 return err;
5803 }
5804 l4len = tcp_hdrlen(skb);
5805 *hdr_len += l4len;
5806
8327d000 5807 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 5808 struct iphdr *iph = ip_hdr(skb);
5809 iph->tot_len = 0;
5810 iph->check = 0;
5811 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 5812 iph->daddr, 0,
5813 IPPROTO_TCP,
5814 0);
8e1e8a47 5815 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 5816 ipv6_hdr(skb)->payload_len = 0;
5817 tcp_hdr(skb)->check =
5818 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 5819 &ipv6_hdr(skb)->daddr,
5820 0, IPPROTO_TCP, 0);
9a799d71
AK		 5821 }
5822
5823 i = tx_ring->next_to_use;
5824
5825 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5826 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5827
5828 /* VLAN MACLEN IPLEN */
5829 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5830 vlan_macip_lens |=
5831 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5832 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 5833 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5834 *hdr_len += skb_network_offset(skb);
5835 vlan_macip_lens |=
5836 (skb_transport_header(skb) - skb_network_header(skb));
5837 *hdr_len +=
5838 (skb_transport_header(skb) - skb_network_header(skb));
5839 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5840 context_desc->seqnum_seed = 0;
5841
5842 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 5843 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 5844 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 5845
8327d000 5846 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 5847 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5848 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5849 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5850
5851 /* MSS L4LEN IDX */
9f8cdf4f 5852 mss_l4len_idx =
9a799d71
AK		 5853 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5854 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 5855 /* use index 1 for TSO */
5856 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5857 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5858
5859 tx_buffer_info->time_stamp = jiffies;
5860 tx_buffer_info->next_to_watch = i;
5861
5862 i++;
5863 if (i == tx_ring->count)
5864 i = 0;
5865 tx_ring->next_to_use = i;
5866
5867 return true;
5868 }
5869 return false;
5870}
5871
5872static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5873 struct ixgbe_ring *tx_ring,
5874 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 5875{
5876 struct ixgbe_adv_tx_context_desc *context_desc;
5877 unsigned int i;
5878 struct ixgbe_tx_buffer *tx_buffer_info;
5879 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5880
5881 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5882 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5883 i = tx_ring->next_to_use;
5884 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 5885 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 5886
5887 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5888 vlan_macip_lens |=
5889 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5890 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 5891 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 5892 if (skb->ip_summed == CHECKSUM_PARTIAL)
5893 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 5894 skb_network_header(skb));
9a799d71
AK		 5895
5896 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5897 context_desc->seqnum_seed = 0;
5898
5899 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 5900 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 5901
5902 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ca553980
GS		 5903 __be16 protocol;
5904
5905 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5906 const struct vlan_ethhdr *vhdr =
5907 (const struct vlan_ethhdr *)skb->data;
5908
5909 protocol = vhdr->h_vlan_encapsulated_proto;
5910 } else {
5911 protocol = skb->protocol;
5912 }
5913
5914 switch (protocol) {
09640e63 5915 case cpu_to_be16(ETH_P_IP):
9a799d71 5916 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 5917 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5918 type_tucmd_mlhl |=
e8e9f696 5919 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5920 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5921 type_tucmd_mlhl |=
e8e9f696 5922 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5923 break;
09640e63 5924 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 5925 /* XXX what about other V6 headers?? */
5926 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5927 type_tucmd_mlhl |=
e8e9f696 5928 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 5929 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5930 type_tucmd_mlhl |=
e8e9f696 5931 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 5932 break;
41825d71
AK		 5933 default:
5934 if (unlikely(net_ratelimit())) {
396e799c
ET		 5935 e_warn(probe, "partial checksum "
5936 "but proto=%x!\n",
5937 skb->protocol);
41825d71
AK		 5938 }
5939 break;
5940 }
9a799d71
AK		 5941 }
5942
5943 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 5944 /* use index zero for tx checksum offload */
9a799d71
AK		 5945 context_desc->mss_l4len_idx = 0;
5946
5947 tx_buffer_info->time_stamp = jiffies;
5948 tx_buffer_info->next_to_watch = i;
9f8cdf4f 5949
9a799d71
AK		 5950 i++;
5951 if (i == tx_ring->count)
5952 i = 0;
5953 tx_ring->next_to_use = i;
5954
5955 return true;
5956 }
9f8cdf4f 5957
9a799d71
AK		 5958 return false;
5959}
5960
5961static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 5962 struct ixgbe_ring *tx_ring,
5963 struct sk_buff *skb, u32 tx_flags,
5964 unsigned int first)
9a799d71 5965{
e5a43549 5966 struct pci_dev *pdev = adapter->pdev;
9a799d71 5967 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 5968 unsigned int len;
5969 unsigned int total = skb->len;
9a799d71
AK		 5970 unsigned int offset = 0, size, count = 0, i;
5971 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5972 unsigned int f;
9a799d71
AK		 5973
5974 i = tx_ring->next_to_use;
5975
eacd73f7
YZ		 5976 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5977 /* excluding fcoe_crc_eof for FCoE */
5978 total -= sizeof(struct fcoe_crc_eof);
5979
5980 len = min(skb_headlen(skb), total);
9a799d71
AK		 5981 while (len) {
5982 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5983 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5984
5985 tx_buffer_info->length = size;
e5a43549 5986 tx_buffer_info->mapped_as_page = false;
1b507730 5987 tx_buffer_info->dma = dma_map_single(&pdev->dev,
e5a43549 5988 skb->data + offset,
1b507730
NN		 5989 size, DMA_TO_DEVICE);
5990 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 5991 goto dma_error;
9a799d71
AK		 5992 tx_buffer_info->time_stamp = jiffies;
5993 tx_buffer_info->next_to_watch = i;
5994
5995 len -= size;
eacd73f7 5996 total -= size;
9a799d71
AK		 5997 offset += size;
5998 count++;
44df32c5
AD		 5999
6000 if (len) {
6001 i++;
6002 if (i == tx_ring->count)
6003 i = 0;
6004 }
9a799d71
AK		 6005 }
6006
6007 for (f = 0; f < nr_frags; f++) {
6008 struct skb_frag_struct *frag;
6009
6010 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6011 len = min((unsigned int)frag->size, total);
e5a43549 6012 offset = frag->page_offset;
9a799d71
AK		 6013
6014 while (len) {
44df32c5
AD		 6015 i++;
6016 if (i == tx_ring->count)
6017 i = 0;
6018
9a799d71
AK		 6019 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6020 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6021
6022 tx_buffer_info->length = size;
1b507730 6023 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
e5a43549
AD		 6024 frag->page,
6025 offset, size,
1b507730 6026 DMA_TO_DEVICE);
e5a43549 6027 tx_buffer_info->mapped_as_page = true;
1b507730 6028 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
e5a43549 6029 goto dma_error;
9a799d71
AK		 6030 tx_buffer_info->time_stamp = jiffies;
6031 tx_buffer_info->next_to_watch = i;
6032
6033 len -= size;
eacd73f7 6034 total -= size;
9a799d71
AK		 6035 offset += size;
6036 count++;
9a799d71 6037 }
eacd73f7
YZ		 6038 if (total == 0)
6039 break;
9a799d71 6040 }
44df32c5 6041
9a799d71
AK		 6042 tx_ring->tx_buffer_info[i].skb = skb;
6043 tx_ring->tx_buffer_info[first].next_to_watch = i;
6044
e5a43549
AD		 6045 return count;
6046
6047dma_error:
849c4542 6048 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6049
6050 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6051 tx_buffer_info->dma = 0;
6052 tx_buffer_info->time_stamp = 0;
6053 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6054 if (count)
6055 count--;
e5a43549
AD		 6056
6057 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6058 while (count--) {
e8e9f696 6059 if (i == 0)
e5a43549 6060 i += tx_ring->count;
c1fa347f 6061 i--;
e5a43549
AD		 6062 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6063 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6064 }
6065
e44d38e1 6066 return 0;
9a799d71
AK		 6067}
6068
6069static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6070 struct ixgbe_ring *tx_ring,
6071 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6072{
6073 union ixgbe_adv_tx_desc *tx_desc = NULL;
6074 struct ixgbe_tx_buffer *tx_buffer_info;
6075 u32 olinfo_status = 0, cmd_type_len = 0;
6076 unsigned int i;
6077 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6078
6079 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6080
6081 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6082
6083 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6084 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6085
6086 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6087 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6088
6089 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6090 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6091
4eeae6fd
PW		 6092 /* use index 1 context for tso */
6093 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6094 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6095 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6096 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6097
6098 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6099 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6100 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6101
eacd73f7
YZ		 6102 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6103 olinfo_status |= IXGBE_ADVTXD_CC;
6104 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6105 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6106 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6107 }
6108
9a799d71
AK		 6109 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6110
6111 i = tx_ring->next_to_use;
6112 while (count--) {
6113 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6114 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6115 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6116 tx_desc->read.cmd_type_len =
e8e9f696 6117 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6118 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6119 i++;
6120 if (i == tx_ring->count)
6121 i = 0;
6122 }
6123
6124 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6125
6126 /*
6127 * Force memory writes to complete before letting h/w
6128 * know there are new descriptors to fetch. (Only
6129 * applicable for weak-ordered memory model archs,
6130 * such as IA-64).
6131 */
6132 wmb();
6133
6134 tx_ring->next_to_use = i;
6135 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6136}
6137
c4cf55e5 6138static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
e8e9f696 6139 int queue, u32 tx_flags)
c4cf55e5 6140{
c4cf55e5
PWJ		 6141 struct ixgbe_atr_input atr_input;
6142 struct tcphdr *th;
c4cf55e5
PWJ		 6143 struct iphdr *iph = ip_hdr(skb);
6144 struct ethhdr *eth = (struct ethhdr *)skb->data;
6145 u16 vlan_id, src_port, dst_port, flex_bytes;
6146 u32 src_ipv4_addr, dst_ipv4_addr;
6147 u8 l4type = 0;
6148
d3ead241
GG		 6149 /* Right now, we support IPv4 only */
6150 if (skb->protocol != htons(ETH_P_IP))
6151 return;
c4cf55e5
PWJ		 6152 /* check if we're UDP or TCP */
6153 if (iph->protocol == IPPROTO_TCP) {
6154 th = tcp_hdr(skb);
6155 src_port = th->source;
6156 dst_port = th->dest;
6157 l4type |= IXGBE_ATR_L4TYPE_TCP;
6158 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 6159 } else {
6160 /* Unsupported L4 header, just bail here */
6161 return;
6162 }
6163
6164 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6165
6166 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
e8e9f696 6167 IXGBE_TX_FLAGS_VLAN_SHIFT;
c4cf55e5
PWJ		 6168 src_ipv4_addr = iph->saddr;
6169 dst_ipv4_addr = iph->daddr;
6170 flex_bytes = eth->h_proto;
6171
6172 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6173 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6174 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6175 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6176 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6177 /* src and dst are inverted, think how the receiver sees them */
6178 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6179 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6180
6181 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6182 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6183}
6184
e092be60 6185static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6186 struct ixgbe_ring *tx_ring, int size)
e092be60 6187{
30eba97a 6188 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 6189 /* Herbert's original patch had:
6190 * smp_mb__after_netif_stop_queue();
6191 * but since that doesn't exist yet, just open code it. */
6192 smp_mb();
6193
6194 /* We need to check again in a case another CPU has just
6195 * made room available. */
6196 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6197 return -EBUSY;
6198
6199 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 6200 netif_start_subqueue(netdev, tx_ring->queue_index);
7ca3bc58 6201 ++tx_ring->restart_queue;
e092be60
AV		 6202 return 0;
6203}
6204
6205static int ixgbe_maybe_stop_tx(struct net_device *netdev,
e8e9f696 6206 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6207{
6208 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6209 return 0;
6210 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6211}
6212
09a3b1f8
SH		 6213static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6214{
6215 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6216 int txq = smp_processor_id();
09a3b1f8 6217
56075a98
JF		 6218#ifdef IXGBE_FCOE
6219 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6220 (skb->protocol == htons(ETH_P_FIP))) {
6221 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6222 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6223 txq += adapter->ring_feature[RING_F_FCOE].mask;
6224 return txq;
4bc091d8 6225#ifdef CONFIG_IXGBE_DCB
56075a98
JF		 6226 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6227 txq = adapter->fcoe.up;
6228 return txq;
4bc091d8 6229#endif
56075a98
JF		 6230 }
6231 }
6232#endif
6233
fdd3d631
KK		 6234 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6235 while (unlikely(txq >= dev->real_num_tx_queues))
6236 txq -= dev->real_num_tx_queues;
5f715823 6237 return txq;
fdd3d631 6238 }
c4cf55e5 6239
2ea186ae
JF		 6240 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6241 if (skb->priority == TC_PRIO_CONTROL)
6242 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6243 else
6244 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6245 >> 13;
6246 return txq;
6247 }
09a3b1f8
SH		 6248
6249 return skb_tx_hash(dev, skb);
6250}
6251
84418e3b
AD		 6252netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6253 struct ixgbe_adapter *adapter,
6254 struct ixgbe_ring *tx_ring)
9a799d71 6255{
60d51134 6256 struct netdev_queue *txq;
9a799d71
AK		 6257 unsigned int first;
6258 unsigned int tx_flags = 0;
30eba97a 6259 u8 hdr_len = 0;
5f715823 6260 int tso;
9a799d71
AK		 6261 int count = 0;
6262 unsigned int f;
9f8cdf4f 6263
9f8cdf4f
JB		 6264 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6265 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6266 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6267 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5f715823 6268 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
2f90b865
AD		 6269 }
6270 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6271 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6272 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6273 skb->priority != TC_PRIO_CONTROL) {
2ea186ae
JF		 6274 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6275 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6276 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6277 }
eacd73f7 6278
09ad1cc0 6279#ifdef IXGBE_FCOE
56075a98
JF		 6280 /* for FCoE with DCB, we force the priority to what
6281 * was specified by the switch */
6282 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6283 (skb->protocol == htons(ETH_P_FCOE) ||
6284 skb->protocol == htons(ETH_P_FIP))) {
4bc091d8
JF		 6285#ifdef CONFIG_IXGBE_DCB
6286 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6287 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6288 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6289 tx_flags |= ((adapter->fcoe.up << 13)
6290 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6291 }
6292#endif
ca77cd59
RL		 6293 /* flag for FCoE offloads */
6294 if (skb->protocol == htons(ETH_P_FCOE))
6295 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0 6296 }
ca77cd59
RL		 6297#endif
6298
eacd73f7 6299 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6300 if (skb_is_gso(skb) ||
6301 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6302 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6303 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6304 count++;
6305
9f8cdf4f
JB		 6306 count += TXD_USE_COUNT(skb_headlen(skb));
6307 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6308 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6309
e092be60 6310 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 6311 adapter->tx_busy++;
9a799d71
AK		 6312 return NETDEV_TX_BUSY;
6313 }
9a799d71 6314
9a799d71 6315 first = tx_ring->next_to_use;
eacd73f7
YZ		 6316 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6317#ifdef IXGBE_FCOE
6318 /* setup tx offload for FCoE */
6319 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6320 if (tso < 0) {
6321 dev_kfree_skb_any(skb);
6322 return NETDEV_TX_OK;
6323 }
6324 if (tso)
6325 tx_flags |= IXGBE_TX_FLAGS_FSO;
6326#endif /* IXGBE_FCOE */
6327 } else {
6328 if (skb->protocol == htons(ETH_P_IP))
6329 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6330 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6331 if (tso < 0) {
6332 dev_kfree_skb_any(skb);
6333 return NETDEV_TX_OK;
6334 }
9a799d71 6335
eacd73f7
YZ		 6336 if (tso)
6337 tx_flags |= IXGBE_TX_FLAGS_TSO;
6338 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6339 (skb->ip_summed == CHECKSUM_PARTIAL))
6340 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6341 }
9a799d71 6342
eacd73f7 6343 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 6344 if (count) {
c4cf55e5
PWJ		 6345 /* add the ATR filter if ATR is on */
6346 if (tx_ring->atr_sample_rate) {
6347 ++tx_ring->atr_count;
6348 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
e8e9f696
JP		 6349 test_bit(__IXGBE_FDIR_INIT_DONE,
6350 &tx_ring->reinit_state)) {
c4cf55e5 6351 ixgbe_atr(adapter, skb, tx_ring->queue_index,
e8e9f696 6352 tx_flags);
c4cf55e5
PWJ		 6353 tx_ring->atr_count = 0;
6354 }
6355 }
60d51134
ED		 6356 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6357 txq->tx_bytes += skb->len;
6358 txq->tx_packets++;
44df32c5 6359 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
e8e9f696 6360 hdr_len);
44df32c5 6361 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 6362
44df32c5
AD		 6363 } else {
6364 dev_kfree_skb_any(skb);
6365 tx_ring->tx_buffer_info[first].time_stamp = 0;
6366 tx_ring->next_to_use = first;
6367 }
9a799d71
AK		 6368
6369 return NETDEV_TX_OK;
6370}
6371
84418e3b
AD		 6372static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6373{
6374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6375 struct ixgbe_ring *tx_ring;
6376
6377 tx_ring = adapter->tx_ring[skb->queue_mapping];
6378 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6379}
6380
9a799d71
AK		 6381/**
6382 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6383 * @netdev: network interface device structure
6384 * @p: pointer to an address structure
6385 *
6386 * Returns 0 on success, negative on failure
6387 **/
6388static int ixgbe_set_mac(struct net_device *netdev, void *p)
6389{
6390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6391 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6392 struct sockaddr *addr = p;
6393
6394 if (!is_valid_ether_addr(addr->sa_data))
6395 return -EADDRNOTAVAIL;
6396
6397 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6398 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6399
1cdd1ec8
GR		 6400 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6401 IXGBE_RAH_AV);
9a799d71
AK		 6402
6403 return 0;
6404}
6405
6b73e10d
BH		 6406static int
6407ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6408{
6409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6410 struct ixgbe_hw *hw = &adapter->hw;
6411 u16 value;
6412 int rc;
6413
6414 if (prtad != hw->phy.mdio.prtad)
6415 return -EINVAL;
6416 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6417 if (!rc)
6418 rc = value;
6419 return rc;
6420}
6421
6422static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6423 u16 addr, u16 value)
6424{
6425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426 struct ixgbe_hw *hw = &adapter->hw;
6427
6428 if (prtad != hw->phy.mdio.prtad)
6429 return -EINVAL;
6430 return hw->phy.ops.write_reg(hw, addr, devad, value);
6431}
6432
6433static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6434{
6435 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6436
6437 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6438}
6439
0365e6e4
PW		 6440/**
6441 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6442 * netdev->dev_addrs
0365e6e4
PW		 6443 * @netdev: network interface device structure
6444 *
6445 * Returns non-zero on failure
6446 **/
6447static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6448{
6449 int err = 0;
6450 struct ixgbe_adapter *adapter = netdev_priv(dev);
6451 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6452
6453 if (is_valid_ether_addr(mac->san_addr)) {
6454 rtnl_lock();
6455 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6456 rtnl_unlock();
6457 }
6458 return err;
6459}
6460
6461/**
6462 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6463 * netdev->dev_addrs
0365e6e4
PW		 6464 * @netdev: network interface device structure
6465 *
6466 * Returns non-zero on failure
6467 **/
6468static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6469{
6470 int err = 0;
6471 struct ixgbe_adapter *adapter = netdev_priv(dev);
6472 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6473
6474 if (is_valid_ether_addr(mac->san_addr)) {
6475 rtnl_lock();
6476 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6477 rtnl_unlock();
6478 }
6479 return err;
6480}
6481
9a799d71
AK		 6482#ifdef CONFIG_NET_POLL_CONTROLLER
6483/*
6484 * Polling 'interrupt' - used by things like netconsole to send skbs
6485 * without having to re-enable interrupts. It's not called while
6486 * the interrupt routine is executing.
6487 */
6488static void ixgbe_netpoll(struct net_device *netdev)
6489{
6490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6491 int i;
9a799d71 6492
1a647bd2
AD		 6493 /* if interface is down do nothing */
6494 if (test_bit(__IXGBE_DOWN, &adapter->state))
6495 return;
6496
9a799d71 6497 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6498 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6499 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6500 for (i = 0; i < num_q_vectors; i++) {
6501 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6502 ixgbe_msix_clean_many(0, q_vector);
6503 }
6504 } else {
6505 ixgbe_intr(adapter->pdev->irq, netdev);
6506 }
9a799d71 6507 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6508}
6509#endif
6510
0edc3527 6511static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6512 .ndo_open = ixgbe_open,
0edc3527 6513 .ndo_stop = ixgbe_close,
00829823 6514 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6515 .ndo_select_queue = ixgbe_select_queue,
e90d400c 6516 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6517 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6518 .ndo_validate_addr = eth_validate_addr,
6519 .ndo_set_mac_address = ixgbe_set_mac,
6520 .ndo_change_mtu = ixgbe_change_mtu,
6521 .ndo_tx_timeout = ixgbe_tx_timeout,
6522 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6523 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6524 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6525 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6526 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6527 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6528 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6529 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
0edc3527
SH		 6530#ifdef CONFIG_NET_POLL_CONTROLLER
6531 .ndo_poll_controller = ixgbe_netpoll,
6532#endif
332d4a7d
YZ		 6533#ifdef IXGBE_FCOE
6534 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6535 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6536 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6537 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6538 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 6539#endif /* IXGBE_FCOE */
0edc3527
SH		 6540};
6541
1cdd1ec8
GR		 6542static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6543 const struct ixgbe_info *ii)
6544{
6545#ifdef CONFIG_PCI_IOV
6546 struct ixgbe_hw *hw = &adapter->hw;
6547 int err;
6548
6549 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6550 return;
6551
6552 /* The 82599 supports up to 64 VFs per physical function
6553 * but this implementation limits allocation to 63 so that
6554 * basic networking resources are still available to the
6555 * physical function
6556 */
6557 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6558 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6559 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6560 if (err) {
396e799c 6561 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 6562 goto err_novfs;
6563 }
6564 /* If call to enable VFs succeeded then allocate memory
6565 * for per VF control structures.
6566 */
6567 adapter->vfinfo =
6568 kcalloc(adapter->num_vfs,
6569 sizeof(struct vf_data_storage), GFP_KERNEL);
6570 if (adapter->vfinfo) {
6571 /* Now that we're sure SR-IOV is enabled
6572 * and memory allocated set up the mailbox parameters
6573 */
6574 ixgbe_init_mbx_params_pf(hw);
6575 memcpy(&hw->mbx.ops, ii->mbx_ops,
6576 sizeof(hw->mbx.ops));
6577
6578 /* Disable RSC when in SR-IOV mode */
6579 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6580 IXGBE_FLAG2_RSC_ENABLED);
6581 return;
6582 }
6583
6584 /* Oh oh */
396e799c
ET		 6585 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6586 "SRIOV disabled\n");
1cdd1ec8
GR		 6587 pci_disable_sriov(adapter->pdev);
6588
6589err_novfs:
6590 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6591 adapter->num_vfs = 0;
6592#endif /* CONFIG_PCI_IOV */
6593}
6594
9a799d71
AK		 6595/**
6596 * ixgbe_probe - Device Initialization Routine
6597 * @pdev: PCI device information struct
6598 * @ent: entry in ixgbe_pci_tbl
6599 *
6600 * Returns 0 on success, negative on failure
6601 *
6602 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6603 * The OS initialization, configuring of the adapter private structure,
6604 * and a hardware reset occur.
6605 **/
6606static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6607 const struct pci_device_id *ent)
9a799d71
AK		 6608{
6609 struct net_device *netdev;
6610 struct ixgbe_adapter *adapter = NULL;
6611 struct ixgbe_hw *hw;
6612 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6613 static int cards_found;
6614 int i, err, pci_using_dac;
c85a2618 6615 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6616#ifdef IXGBE_FCOE
6617 u16 device_caps;
6618#endif
c44ade9e 6619 u32 part_num, eec;
9a799d71 6620
bded64a7
AG		 6621 /* Catch broken hardware that put the wrong VF device ID in
6622 * the PCIe SR-IOV capability.
6623 */
6624 if (pdev->is_virtfn) {
6625 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6626 pci_name(pdev), pdev->vendor, pdev->device);
6627 return -EINVAL;
6628 }
6629
9ce77666 6630 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6631 if (err)
6632 return err;
6633
1b507730
NN		 6634 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6635 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6636 pci_using_dac = 1;
6637 } else {
1b507730 6638 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 6639 if (err) {
1b507730
NN		 6640 err = dma_set_coherent_mask(&pdev->dev,
6641 DMA_BIT_MASK(32));
9a799d71 6642 if (err) {
b8bc0421
DC		 6643 dev_err(&pdev->dev,
6644 "No usable DMA configuration, aborting\n");
9a799d71
AK		 6645 goto err_dma;
6646 }
6647 }
6648 pci_using_dac = 0;
6649 }
6650
9ce77666 6651 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 6652 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 6653 if (err) {
b8bc0421
DC		 6654 dev_err(&pdev->dev,
6655 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 6656 goto err_pci_reg;
6657 }
6658
19d5afd4 6659 pci_enable_pcie_error_reporting(pdev);
6fabd715 6660
9a799d71 6661 pci_set_master(pdev);
fb3b27bc 6662 pci_save_state(pdev);
9a799d71 6663
c85a2618
JF		 6664 if (ii->mac == ixgbe_mac_82598EB)
6665 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6666 else
6667 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6668
6669 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6670#ifdef IXGBE_FCOE
6671 indices += min_t(unsigned int, num_possible_cpus(),
6672 IXGBE_MAX_FCOE_INDICES);
6673#endif
c85a2618 6674 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 6675 if (!netdev) {
6676 err = -ENOMEM;
6677 goto err_alloc_etherdev;
6678 }
6679
9a799d71
AK		 6680 SET_NETDEV_DEV(netdev, &pdev->dev);
6681
6682 pci_set_drvdata(pdev, netdev);
6683 adapter = netdev_priv(netdev);
6684
6685 adapter->netdev = netdev;
6686 adapter->pdev = pdev;
6687 hw = &adapter->hw;
6688 hw->back = adapter;
6689 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6690
05857980 6691 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 6692 pci_resource_len(pdev, 0));
9a799d71
AK		 6693 if (!hw->hw_addr) {
6694 err = -EIO;
6695 goto err_ioremap;
6696 }
6697
6698 for (i = 1; i <= 5; i++) {
6699 if (pci_resource_len(pdev, i) == 0)
6700 continue;
6701 }
6702
0edc3527 6703 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 6704 ixgbe_set_ethtool_ops(netdev);
9a799d71 6705 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 6706 strcpy(netdev->name, pci_name(pdev));
6707
9a799d71
AK		 6708 adapter->bd_number = cards_found;
6709
9a799d71
AK		 6710 /* Setup hw api */
6711 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 6712 hw->mac.type = ii->mac;
9a799d71 6713
c44ade9e
JB		 6714 /* EEPROM */
6715 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6716 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6717 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6718 if (!(eec & (1 << 8)))
6719 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6720
6721 /* PHY */
6722 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 6723 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 6724 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6725 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6726 hw->phy.mdio.mmds = 0;
6727 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6728 hw->phy.mdio.dev = netdev;
6729 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6730 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 6731
6732 /* set up this timer and work struct before calling get_invariants
6733 * which might start the timer
6734 */
6735 init_timer(&adapter->sfp_timer);
c061b18d 6736 adapter->sfp_timer.function = ixgbe_sfp_timer;
c4900be0
DS		 6737 adapter->sfp_timer.data = (unsigned long) adapter;
6738
6739 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 6740
e8e26350
PW		 6741 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6742 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6743
6744 /* a new SFP+ module arrival, called from GPI SDP2 context */
6745 INIT_WORK(&adapter->sfp_config_module_task,
e8e9f696 6746 ixgbe_sfp_config_module_task);
e8e26350 6747
8ca783ab 6748 ii->get_invariants(hw);
9a799d71
AK		 6749
6750 /* setup the private structure */
6751 err = ixgbe_sw_init(adapter);
6752 if (err)
6753 goto err_sw_init;
6754
e86bff0e
DS		 6755 /* Make it possible the adapter to be woken up via WOL */
6756 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6758
bf069c97
DS		 6759 /*
6760 * If there is a fan on this device and it has failed log the
6761 * failure.
6762 */
6763 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6764 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6765 if (esdp & IXGBE_ESDP_SDP1)
396e799c 6766 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 6767 }
6768
c44ade9e 6769 /* reset_hw fills in the perm_addr as well */
119fc60a 6770 hw->phy.reset_if_overtemp = true;
c44ade9e 6771 err = hw->mac.ops.reset_hw(hw);
119fc60a 6772 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 6773 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6774 hw->mac.type == ixgbe_mac_82598EB) {
6775 /*
6776 * Start a kernel thread to watch for a module to arrive.
6777 * Only do this for 82598, since 82599 will generate
6778 * interrupts on module arrival.
6779 */
6780 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6781 mod_timer(&adapter->sfp_timer,
6782 round_jiffies(jiffies + (2 * HZ)));
6783 err = 0;
6784 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
849c4542
ET		 6785 e_dev_err("failed to initialize because an unsupported SFP+ "
6786 "module type was detected.\n");
6787 e_dev_err("Reload the driver after installing a supported "
6788 "module.\n");
04f165ef
PW		 6789 goto err_sw_init;
6790 } else if (err) {
849c4542 6791 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 6792 goto err_sw_init;
6793 }
6794
1cdd1ec8
GR		 6795 ixgbe_probe_vf(adapter, ii);
6796
396e799c 6797 netdev->features = NETIF_F_SG |
e8e9f696
JP		 6798 NETIF_F_IP_CSUM |
6799 NETIF_F_HW_VLAN_TX |
6800 NETIF_F_HW_VLAN_RX |
6801 NETIF_F_HW_VLAN_FILTER;
9a799d71 6802
e9990a9c 6803 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 6804 netdev->features |= NETIF_F_TSO;
9a799d71 6805 netdev->features |= NETIF_F_TSO6;
78b6f4ce 6806 netdev->features |= NETIF_F_GRO;
ad31c402 6807
45a5ead0
JB		 6808 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6809 netdev->features |= NETIF_F_SCTP_CSUM;
6810
ad31c402
JK		 6811 netdev->vlan_features |= NETIF_F_TSO;
6812 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 6813 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 6814 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 6815 netdev->vlan_features |= NETIF_F_SG;
6816
1cdd1ec8
GR		 6817 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6818 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6819 IXGBE_FLAG_DCB_ENABLED);
2f90b865
AD		 6820 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6821 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6822
7a6b6f51 6823#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 6824 netdev->dcbnl_ops = &dcbnl_ops;
6825#endif
6826
eacd73f7 6827#ifdef IXGBE_FCOE
0d551589 6828 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 6829 if (hw->mac.ops.get_device_caps) {
6830 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 6831 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6832 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 6833 }
6834 }
5e09d7f6
YZ		 6835 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6836 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6837 netdev->vlan_features |= NETIF_F_FSO;
6838 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6839 }
eacd73f7 6840#endif /* IXGBE_FCOE */
9a799d71
AK		 6841 if (pci_using_dac)
6842 netdev->features |= NETIF_F_HIGHDMA;
6843
0c19d6af 6844 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 6845 netdev->features |= NETIF_F_LRO;
6846
9a799d71 6847 /* make sure the EEPROM is good */
c44ade9e 6848 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 6849 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 6850 err = -EIO;
6851 goto err_eeprom;
6852 }
6853
6854 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6855 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6856
c44ade9e 6857 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 6858 e_dev_err("invalid MAC address\n");
9a799d71
AK		 6859 err = -EIO;
6860 goto err_eeprom;
6861 }
6862
61fac744
PW		 6863 /* power down the optics */
6864 if (hw->phy.multispeed_fiber)
6865 hw->mac.ops.disable_tx_laser(hw);
6866
9a799d71 6867 init_timer(&adapter->watchdog_timer);
c061b18d 6868 adapter->watchdog_timer.function = ixgbe_watchdog;
9a799d71
AK		 6869 adapter->watchdog_timer.data = (unsigned long)adapter;
6870
6871 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 6872 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 6873
021230d4
AV		 6874 err = ixgbe_init_interrupt_scheme(adapter);
6875 if (err)
6876 goto err_sw_init;
9a799d71 6877
e8e26350
PW		 6878 switch (pdev->device) {
6879 case IXGBE_DEV_ID_82599_KX4:
495dce12 6880 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 6881 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 6882 break;
6883 default:
6884 adapter->wol = 0;
6885 break;
6886 }
e8e26350
PW		 6887 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6888
04f165ef
PW		 6889 /* pick up the PCI bus settings for reporting later */
6890 hw->mac.ops.get_bus_info(hw);
6891
9a799d71 6892 /* print bus type/speed/width info */
849c4542 6893 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8e9f696
JP		 6894 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6895 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6896 "Unknown"),
6897 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6898 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6899 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6900 "Unknown"),
6901 netdev->dev_addr);
c44ade9e 6902 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350 6903 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
849c4542
ET		 6904 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6905 "PBA No: %06x-%03x\n",
6906 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6907 (part_num >> 8), (part_num & 0xff));
e8e26350 6908 else
849c4542
ET		 6909 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6910 hw->mac.type, hw->phy.type,
6911 (part_num >> 8), (part_num & 0xff));
9a799d71 6912
e8e26350 6913 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 6914 e_dev_warn("PCI-Express bandwidth available for this card is "
6915 "not sufficient for optimal performance.\n");
6916 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6917 "is required.\n");
0c254d86
AK		 6918 }
6919
34b0368c
PWJ		 6920 /* save off EEPROM version number */
6921 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6922
9a799d71 6923 /* reset the hardware with the new settings */
794caeb2 6924 err = hw->mac.ops.start_hw(hw);
c44ade9e 6925
794caeb2
PWJ		 6926 if (err == IXGBE_ERR_EEPROM_VERSION) {
6927 /* We are running on a pre-production device, log a warning */
849c4542
ET		 6928 e_dev_warn("This device is a pre-production adapter/LOM. "
6929 "Please be aware there may be issues associated "
6930 "with your hardware. If you are experiencing "
6931 "problems please contact your Intel or hardware "
6932 "representative who provided you with this "
6933 "hardware.\n");
794caeb2 6934 }
9a799d71
AK		 6935 strcpy(netdev->name, "eth%d");
6936 err = register_netdev(netdev);
6937 if (err)
6938 goto err_register;
6939
54386467
JB		 6940 /* carrier off reporting is important to ethtool even BEFORE open */
6941 netif_carrier_off(netdev);
6942
c4cf55e5
PWJ		 6943 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6944 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6945 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6946
119fc60a 6947 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 6948 INIT_WORK(&adapter->check_overtemp_task,
6949 ixgbe_check_overtemp_task);
5dd2d332 6950#ifdef CONFIG_IXGBE_DCA
652f093f 6951 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 6952 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 6953 ixgbe_setup_dca(adapter);
6954 }
6955#endif
1cdd1ec8 6956 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 6957 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 6958 for (i = 0; i < adapter->num_vfs; i++)
6959 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6960 }
6961
0365e6e4
PW		 6962 /* add san mac addr to netdev */
6963 ixgbe_add_sanmac_netdev(netdev);
9a799d71 6964
849c4542 6965 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 6966 cards_found++;
6967 return 0;
6968
6969err_register:
5eba3699 6970 ixgbe_release_hw_control(adapter);
7a921c93 6971 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 6972err_sw_init:
6973err_eeprom:
1cdd1ec8
GR		 6974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6975 ixgbe_disable_sriov(adapter);
c4900be0
DS		 6976 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6977 del_timer_sync(&adapter->sfp_timer);
6978 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 6979 cancel_work_sync(&adapter->multispeed_fiber_task);
6980 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 6981 iounmap(hw->hw_addr);
6982err_ioremap:
6983 free_netdev(netdev);
6984err_alloc_etherdev:
e8e9f696
JP		 6985 pci_release_selected_regions(pdev,
6986 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 6987err_pci_reg:
6988err_dma:
6989 pci_disable_device(pdev);
6990 return err;
6991}
6992
6993/**
6994 * ixgbe_remove - Device Removal Routine
6995 * @pdev: PCI device information struct
6996 *
6997 * ixgbe_remove is called by the PCI subsystem to alert the driver
6998 * that it should release a PCI device. The could be caused by a
6999 * Hot-Plug event, or because the driver is going to be removed from
7000 * memory.
7001 **/
7002static void __devexit ixgbe_remove(struct pci_dev *pdev)
7003{
7004 struct net_device *netdev = pci_get_drvdata(pdev);
7005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7006
7007 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 7008 /* clear the module not found bit to make sure the worker won't
7009 * reschedule
7010 */
7011 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 7012 del_timer_sync(&adapter->watchdog_timer);
7013
c4900be0
DS		 7014 del_timer_sync(&adapter->sfp_timer);
7015 cancel_work_sync(&adapter->watchdog_task);
7016 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 7017 cancel_work_sync(&adapter->multispeed_fiber_task);
7018 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 7019 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7020 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7021 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 7022 flush_scheduled_work();
7023
5dd2d332 7024#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7025 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7026 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7027 dca_remove_requester(&pdev->dev);
7028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7029 }
7030
7031#endif
332d4a7d
YZ		 7032#ifdef IXGBE_FCOE
7033 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7034 ixgbe_cleanup_fcoe(adapter);
7035
7036#endif /* IXGBE_FCOE */
0365e6e4
PW		 7037
7038 /* remove the added san mac */
7039 ixgbe_del_sanmac_netdev(netdev);
7040
c4900be0
DS		 7041 if (netdev->reg_state == NETREG_REGISTERED)
7042 unregister_netdev(netdev);
9a799d71 7043
1cdd1ec8
GR		 7044 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7045 ixgbe_disable_sriov(adapter);
7046
7a921c93 7047 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7048
021230d4 7049 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7050
7051 iounmap(adapter->hw.hw_addr);
9ce77666 7052 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7053 IORESOURCE_MEM));
9a799d71 7054
849c4542 7055 e_dev_info("complete\n");
021230d4 7056
9a799d71
AK		 7057 free_netdev(netdev);
7058
19d5afd4 7059 pci_disable_pcie_error_reporting(pdev);
6fabd715 7060
9a799d71
AK		 7061 pci_disable_device(pdev);
7062}
7063
7064/**
7065 * ixgbe_io_error_detected - called when PCI error is detected
7066 * @pdev: Pointer to PCI device
7067 * @state: The current pci connection state
7068 *
7069 * This function is called after a PCI bus error affecting
7070 * this device has been detected.
7071 */
7072static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7073 pci_channel_state_t state)
9a799d71
AK		 7074{
7075 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7077
7078 netif_device_detach(netdev);
7079
3044b8d1
BL		 7080 if (state == pci_channel_io_perm_failure)
7081 return PCI_ERS_RESULT_DISCONNECT;
7082
9a799d71
AK		 7083 if (netif_running(netdev))
7084 ixgbe_down(adapter);
7085 pci_disable_device(pdev);
7086
b4617240 7087 /* Request a slot reset. */
9a799d71
AK		 7088 return PCI_ERS_RESULT_NEED_RESET;
7089}
7090
7091/**
7092 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7093 * @pdev: Pointer to PCI device
7094 *
7095 * Restart the card from scratch, as if from a cold-boot.
7096 */
7097static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7098{
7099 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7100 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 7101 pci_ers_result_t result;
7102 int err;
9a799d71 7103
9ce77666 7104 if (pci_enable_device_mem(pdev)) {
396e799c 7105 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7106 result = PCI_ERS_RESULT_DISCONNECT;
7107 } else {
7108 pci_set_master(pdev);
7109 pci_restore_state(pdev);
c0e1f68b 7110 pci_save_state(pdev);
9a799d71 7111
dd4d8ca6 7112 pci_wake_from_d3(pdev, false);
9a799d71 7113
6fabd715 7114 ixgbe_reset(adapter);
88512539 7115 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7116 result = PCI_ERS_RESULT_RECOVERED;
7117 }
7118
7119 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7120 if (err) {
849c4542
ET		 7121 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7122 "failed 0x%0x\n", err);
6fabd715
PWJ		 7123 /* non-fatal, continue */
7124 }
9a799d71 7125
6fabd715 7126 return result;
9a799d71
AK		 7127}
7128
7129/**
7130 * ixgbe_io_resume - called when traffic can start flowing again.
7131 * @pdev: Pointer to PCI device
7132 *
7133 * This callback is called when the error recovery driver tells us that
7134 * its OK to resume normal operation.
7135 */
7136static void ixgbe_io_resume(struct pci_dev *pdev)
7137{
7138 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 7139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 7140
7141 if (netif_running(netdev)) {
7142 if (ixgbe_up(adapter)) {
396e799c 7143 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7144 return;
7145 }
7146 }
7147
7148 netif_device_attach(netdev);
9a799d71
AK		 7149}
7150
7151static struct pci_error_handlers ixgbe_err_handler = {
7152 .error_detected = ixgbe_io_error_detected,
7153 .slot_reset = ixgbe_io_slot_reset,
7154 .resume = ixgbe_io_resume,
7155};
7156
7157static struct pci_driver ixgbe_driver = {
7158 .name = ixgbe_driver_name,
7159 .id_table = ixgbe_pci_tbl,
7160 .probe = ixgbe_probe,
7161 .remove = __devexit_p(ixgbe_remove),
7162#ifdef CONFIG_PM
7163 .suspend = ixgbe_suspend,
7164 .resume = ixgbe_resume,
7165#endif
7166 .shutdown = ixgbe_shutdown,
7167 .err_handler = &ixgbe_err_handler
7168};
7169
7170/**
7171 * ixgbe_init_module - Driver Registration Routine
7172 *
7173 * ixgbe_init_module is the first routine called when the driver is
7174 * loaded. All it does is register with the PCI subsystem.
7175 **/
7176static int __init ixgbe_init_module(void)
7177{
7178 int ret;
849c4542
ET		 7179 pr_info("%s - version %s\n", ixgbe_driver_string,
7180 ixgbe_driver_version);
7181 pr_info("%s\n", ixgbe_copyright);
9a799d71 7182
5dd2d332 7183#ifdef CONFIG_IXGBE_DCA
bd0362dd 7184 dca_register_notify(&dca_notifier);
bd0362dd 7185#endif
5dd2d332 7186
9a799d71
AK		 7187 ret = pci_register_driver(&ixgbe_driver);
7188 return ret;
7189}
b4617240 7190
9a799d71
AK		 7191module_init(ixgbe_init_module);
7192
7193/**
7194 * ixgbe_exit_module - Driver Exit Cleanup Routine
7195 *
7196 * ixgbe_exit_module is called just before the driver is removed
7197 * from memory.
7198 **/
7199static void __exit ixgbe_exit_module(void)
7200{
5dd2d332 7201#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7202 dca_unregister_notify(&dca_notifier);
7203#endif
9a799d71
AK		 7204 pci_unregister_driver(&ixgbe_driver);
7205}
bd0362dd 7206
5dd2d332 7207#ifdef CONFIG_IXGBE_DCA
bd0362dd 7208static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7209 void *p)
bd0362dd
JC		 7210{
7211 int ret_val;
7212
7213 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7214 __ixgbe_notify_dca);
bd0362dd
JC		 7215
7216 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7217}
b453368d 7218
5dd2d332 7219#endif /* CONFIG_IXGBE_DCA */
849c4542 7220
b453368d 7221/**
849c4542 7222 * ixgbe_get_hw_dev return device
b453368d
AD		 7223 * used by hardware layer to print debugging information
7224 **/
849c4542 7225struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
b453368d
AD		 7226{
7227 struct ixgbe_adapter *adapter = hw->back;
849c4542 7228 return adapter->netdev;
b453368d 7229}
bd0362dd 7230
9a799d71
AK		 7231module_exit(ixgbe_exit_module);
7232
7233/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree