]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/ixgbe/ixgbe_main.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Change Direct Attach Twinax cable detection for SFP+ NICs
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
eacd73f7 42#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
9c8eb720 48static const char ixgbe_driver_string[] =
b4617240 49 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 50
ba98898e 51#define DRV_VERSION "2.0.24-k2"
9c8eb720 52const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 53static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 56 [board_82598] = &ixgbe_82598_info,
e8e26350 57 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 58};
59
60/* ixgbe_pci_tbl - PCI Device ID Table
61 *
62 * Wildcard entries (PCI_ANY_ID) should come last
63 * Last entry must be all 0s
64 *
65 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
66 * Class, Class Mask, private data (not used) }
67 */
68static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
70 board_82598 },
9a799d71 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 74 board_82598 },
0befdb3e
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
76 board_82598 },
9a799d71 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 78 board_82598 },
8d792cd9
JB		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
80 board_82598 },
c4900be0
DS		 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
84 board_82598 },
b95f5fcb
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
86 board_82598 },
c4900be0
DS		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
88 board_82598 },
2f21bdd3
DS		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
90 board_82598 },
e8e26350
PW		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
92 board_82599 },
1fcf03e6
PWJ		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
94 board_82599 },
e8e26350
PW		 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
96 board_82599 },
9a799d71
AK		 97
98 /* required last entry */
99 {0, }
100};
101MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
102
5dd2d332 103#ifdef CONFIG_IXGBE_DCA
bd0362dd 104static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 105 void *p);
bd0362dd
JC		 106static struct notifier_block dca_notifier = {
107 .notifier_call = ixgbe_notify_dca,
108 .next = NULL,
109 .priority = 0
110};
111#endif
112
9a799d71
AK		 113MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
114MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
115MODULE_LICENSE("GPL");
116MODULE_VERSION(DRV_VERSION);
117
118#define DEFAULT_DEBUG_LEVEL_SHIFT 3
119
5eba3699
AV		 120static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
121{
122 u32 ctrl_ext;
123
124 /* Let firmware take over control of h/w */
125 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
126 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 127 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 128}
129
130static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
131{
132 u32 ctrl_ext;
133
134 /* Let firmware know the driver has taken over */
135 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
136 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 137 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 138}
9a799d71 139
e8e26350
PW		 140/*
141 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
142 * @adapter: pointer to adapter struct
143 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
144 * @queue: queue to map the corresponding interrupt to
145 * @msix_vector: the vector to map to the corresponding queue
146 *
147 */
148static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
149 u8 queue, u8 msix_vector)
9a799d71
AK		 150{
151 u32 ivar, index;
e8e26350
PW		 152 struct ixgbe_hw *hw = &adapter->hw;
153 switch (hw->mac.type) {
154 case ixgbe_mac_82598EB:
155 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
156 if (direction == -1)
157 direction = 0;
158 index = (((direction * 64) + queue) >> 2) & 0x1F;
159 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
160 ivar &= ~(0xFF << (8 * (queue & 0x3)));
161 ivar |= (msix_vector << (8 * (queue & 0x3)));
162 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
163 break;
164 case ixgbe_mac_82599EB:
165 if (direction == -1) {
166 /* other causes */
167 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
168 index = ((queue & 1) * 8);
169 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
170 ivar &= ~(0xFF << index);
171 ivar |= (msix_vector << index);
172 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
173 break;
174 } else {
175 /* tx or rx causes */
176 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
177 index = ((16 * (queue & 1)) + (8 * direction));
178 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
179 ivar &= ~(0xFF << index);
180 ivar |= (msix_vector << index);
181 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
182 break;
183 }
184 default:
185 break;
186 }
9a799d71
AK		 187}
188
189static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 190 struct ixgbe_tx_buffer
191 *tx_buffer_info)
9a799d71 192{
44df32c5 193 tx_buffer_info->dma = 0;
9a799d71 194 if (tx_buffer_info->skb) {
44df32c5
AD		 195 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
196 DMA_TO_DEVICE);
9a799d71
AK		 197 dev_kfree_skb_any(tx_buffer_info->skb);
198 tx_buffer_info->skb = NULL;
199 }
44df32c5 200 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 201 /* tx_buffer_info must be completely set up in the transmit path */
202}
203
204static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 205 struct ixgbe_ring *tx_ring,
206 unsigned int eop)
9a799d71 207{
e01c31a5 208 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 209
9a799d71 210 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 211 * check with the clearing of time_stamp and movement of eop */
9a799d71 212 adapter->detect_tx_hung = false;
44df32c5 213 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 214 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
215 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
216 /* detected Tx unit hang */
e01c31a5
JB		 217 union ixgbe_adv_tx_desc *tx_desc;
218 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 219 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 220 " Tx Queue <%d>\n"
221 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 222 " next_to_use <%x>\n"
223 " next_to_clean <%x>\n"
224 "tx_buffer_info[next_to_clean]\n"
225 " time_stamp <%lx>\n"
e01c31a5
JB		 226 " jiffies <%lx>\n",
227 tx_ring->queue_index,
44df32c5
AD		 228 IXGBE_READ_REG(hw, tx_ring->head),
229 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 230 tx_ring->next_to_use, eop,
231 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 232 return true;
233 }
234
235 return false;
236}
237
b4617240
PW		 238#define IXGBE_MAX_TXD_PWR 14
239#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 240
241/* Tx Descriptors needed, worst case */
242#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
243 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
244#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 245 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 246
e01c31a5
JB		 247static void ixgbe_tx_timeout(struct net_device *netdev);
248
9a799d71
AK		 249/**
250 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
251 * @adapter: board private structure
e01c31a5 252 * @tx_ring: tx ring to clean
9a1a69ad
JB		 253 *
254 * returns true if transmit work is done
9a799d71
AK		 255 **/
256static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 257 struct ixgbe_ring *tx_ring)
9a799d71 258{
e01c31a5 259 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 260 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
261 struct ixgbe_tx_buffer *tx_buffer_info;
262 unsigned int i, eop, count = 0;
e01c31a5 263 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 264
265 i = tx_ring->next_to_clean;
12207e49
PWJ		 266 eop = tx_ring->tx_buffer_info[i].next_to_watch;
267 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
268
269 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 270 (count < tx_ring->work_limit)) {
12207e49
PWJ		 271 bool cleaned = false;
272 for ( ; !cleaned; count++) {
273 struct sk_buff *skb;
9a799d71
AK		 274 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
275 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 276 cleaned = (i == eop);
e01c31a5 277 skb = tx_buffer_info->skb;
9a799d71 278
12207e49 279 if (cleaned && skb) {
e092be60 280 unsigned int segs, bytecount;
e01c31a5
JB		 281
282 /* gso_segs is currently only valid for tcp */
e092be60
AV		 283 segs = skb_shinfo(skb)->gso_segs ?: 1;
284 /* multiply data chunks by size of headers */
285 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 286 skb->len;
287 total_packets += segs;
288 total_bytes += bytecount;
e092be60 289 }
e01c31a5 290
9a799d71 291 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 292 tx_buffer_info);
9a799d71 293
12207e49
PWJ		 294 tx_desc->wb.status = 0;
295
9a799d71
AK		 296 i++;
297 if (i == tx_ring->count)
298 i = 0;
e01c31a5 299 }
12207e49
PWJ		 300
301 eop = tx_ring->tx_buffer_info[i].next_to_watch;
302 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
303 }
304
9a799d71
AK		 305 tx_ring->next_to_clean = i;
306
e092be60 307#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 308 if (unlikely(count && netif_carrier_ok(netdev) &&
309 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 310 /* Make sure that anybody stopping the queue after this
311 * sees the new next_to_clean.
312 */
313 smp_mb();
30eba97a
AV		 314 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
315 !test_bit(__IXGBE_DOWN, &adapter->state)) {
316 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 317 ++adapter->restart_queue;
30eba97a 318 }
e092be60 319 }
9a799d71 320
e01c31a5
JB		 321 if (adapter->detect_tx_hung) {
322 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
323 /* schedule immediate reset if we believe we hung */
324 DPRINTK(PROBE, INFO,
325 "tx hang %d detected, resetting adapter\n",
326 adapter->tx_timeout_count + 1);
327 ixgbe_tx_timeout(adapter->netdev);
328 }
329 }
9a799d71 330
e01c31a5 331 /* re-arm the interrupt */
835462fc
NS		 332 if (count >= tx_ring->work_limit) {
333 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
335 tx_ring->v_idx);
336 else if (tx_ring->v_idx & 0xFFFFFFFF)
337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0),
338 tx_ring->v_idx);
339 else
340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1),
341 (tx_ring->v_idx >> 32));
342 }
343
9a799d71 344
e01c31a5
JB		 345 tx_ring->total_bytes += total_bytes;
346 tx_ring->total_packets += total_packets;
e01c31a5 347 tx_ring->stats.packets += total_packets;
12207e49 348 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 349 adapter->net_stats.tx_bytes += total_bytes;
350 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 351 return (count < tx_ring->work_limit);
9a799d71
AK		 352}
353
5dd2d332 354#ifdef CONFIG_IXGBE_DCA
bd0362dd 355static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 356 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 357{
358 u32 rxctrl;
359 int cpu = get_cpu();
3a581073 360 int q = rx_ring - adapter->rx_ring;
bd0362dd 361
3a581073 362 if (rx_ring->cpu != cpu) {
bd0362dd 363 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 364 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
365 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
366 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
367 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
368 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
369 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
370 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
371 }
bd0362dd
JC		 372 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
373 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 374 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
375 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 376 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 377 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 378 rx_ring->cpu = cpu;
bd0362dd
JC		 379 }
380 put_cpu();
381}
382
383static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 384 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 385{
386 u32 txctrl;
387 int cpu = get_cpu();
3a581073 388 int q = tx_ring - adapter->tx_ring;
bd0362dd 389
3a581073 390 if (tx_ring->cpu != cpu) {
bd0362dd 391 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 392 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
393 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
394 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
395 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
396 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
397 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
398 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
399 }
bd0362dd
JC		 400 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 402 tx_ring->cpu = cpu;
bd0362dd
JC		 403 }
404 put_cpu();
405}
406
407static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
408{
409 int i;
410
411 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
412 return;
413
414 for (i = 0; i < adapter->num_tx_queues; i++) {
415 adapter->tx_ring[i].cpu = -1;
416 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
417 }
418 for (i = 0; i < adapter->num_rx_queues; i++) {
419 adapter->rx_ring[i].cpu = -1;
420 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
421 }
422}
423
424static int __ixgbe_notify_dca(struct device *dev, void *data)
425{
426 struct net_device *netdev = dev_get_drvdata(dev);
427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
428 unsigned long event = *(unsigned long *)data;
429
430 switch (event) {
431 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 432 /* if we're already enabled, don't do it again */
433 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
434 break;
bd0362dd
JC		 435 /* Always use CB2 mode, difference is masked
436 * in the CB driver. */
437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 438 if (dca_add_requester(dev) == 0) {
96b0e0f6 439 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 440 ixgbe_setup_dca(adapter);
441 break;
442 }
443 /* Fall Through since DCA is disabled. */
444 case DCA_PROVIDER_REMOVE:
445 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
446 dca_remove_requester(dev);
447 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
449 }
450 break;
451 }
452
652f093f 453 return 0;
bd0362dd
JC		 454}
455
5dd2d332 456#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 457/**
458 * ixgbe_receive_skb - Send a completed packet up the stack
459 * @adapter: board private structure
460 * @skb: packet to send up
177db6ff
MC		 461 * @status: hardware indication of status of receive
462 * @rx_ring: rx descriptor ring (for a specific queue) to setup
463 * @rx_desc: rx descriptor
9a799d71 464 **/
78b6f4ce 465static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 466 struct sk_buff *skb, u8 status,
fdaff1ce 467 struct ixgbe_ring *ring,
177db6ff 468 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 469{
78b6f4ce
HX		 470 struct ixgbe_adapter *adapter = q_vector->adapter;
471 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 472 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
473 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 474
fdaff1ce 475 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 476 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 477 if (adapter->vlgrp && is_vlan && (tag != 0))
78b6f4ce 478 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 479 else
78b6f4ce 480 napi_gro_receive(napi, skb);
177db6ff 481 } else {
182ff8df
AD		 482 if (adapter->vlgrp && is_vlan && (tag != 0))
483 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
484 else
485 netif_rx(skb);
9a799d71
AK		 486 }
487}
488
e59bd25d
AV		 489/**
490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
491 * @adapter: address of board private structure
492 * @status_err: hardware indication of status of receive
493 * @skb: skb currently being received and modified
494 **/
9a799d71 495static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 496 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 497{
498 skb->ip_summed = CHECKSUM_NONE;
499
712744be
JB		 500 /* Rx csum disabled */
501 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 502 return;
e59bd25d
AV		 503
504 /* if IP and error */
505 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
506 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 507 adapter->hw_csum_rx_error++;
508 return;
509 }
e59bd25d
AV		 510
511 if (!(status_err & IXGBE_RXD_STAT_L4CS))
512 return;
513
514 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
515 adapter->hw_csum_rx_error++;
516 return;
517 }
518
9a799d71 519 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 520 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 521 adapter->hw_csum_rx_good++;
522}
523
e8e26350
PW		 524static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
525 struct ixgbe_ring *rx_ring, u32 val)
526{
527 /*
528 * Force memory writes to complete before letting h/w
529 * know there are new descriptors to fetch. (Only
530 * applicable for weak-ordered memory model archs,
531 * such as IA-64).
532 */
533 wmb();
534 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
535}
536
9a799d71
AK		 537/**
538 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
539 * @adapter: address of board private structure
540 **/
541static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 542 struct ixgbe_ring *rx_ring,
543 int cleaned_count)
9a799d71 544{
9a799d71
AK		 545 struct pci_dev *pdev = adapter->pdev;
546 union ixgbe_adv_rx_desc *rx_desc;
3a581073 547 struct ixgbe_rx_buffer *bi;
9a799d71 548 unsigned int i;
e8e26350 549 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 550
551 i = rx_ring->next_to_use;
3a581073 552 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 553
554 while (cleaned_count--) {
555 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
556
762f4c57 557 if (!bi->page_dma &&
3a581073 558 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 559 if (!bi->page) {
762f4c57
JB		 560 bi->page = alloc_page(GFP_ATOMIC);
561 if (!bi->page) {
562 adapter->alloc_rx_page_failed++;
563 goto no_buffers;
564 }
565 bi->page_offset = 0;
566 } else {
567 /* use a half page if we're re-using */
568 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 569 }
762f4c57
JB		 570
571 bi->page_dma = pci_map_page(pdev, bi->page,
572 bi->page_offset,
573 (PAGE_SIZE / 2),
574 PCI_DMA_FROMDEVICE);
9a799d71
AK		 575 }
576
3a581073 577 if (!bi->skb) {
5ecc3614 578 struct sk_buff *skb;
e8e26350 579 skb = netdev_alloc_skb(adapter->netdev, bufsz);
9a799d71
AK		 580
581 if (!skb) {
582 adapter->alloc_rx_buff_failed++;
583 goto no_buffers;
584 }
585
586 /*
587 * Make buffer alignment 2 beyond a 16 byte boundary
588 * this will result in a 16 byte aligned IP header after
589 * the 14 byte MAC header is removed
590 */
591 skb_reserve(skb, NET_IP_ALIGN);
592
3a581073 593 bi->skb = skb;
e8e26350 594 bi->dma = pci_map_single(pdev, skb->data, bufsz,
3a581073 595 PCI_DMA_FROMDEVICE);
9a799d71
AK		 596 }
597 /* Refresh the desc even if buffer_addrs didn't change because
598 * each write-back erases this info. */
599 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 600 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
601 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 602 } else {
3a581073 603 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 604 }
605
606 i++;
607 if (i == rx_ring->count)
608 i = 0;
3a581073 609 bi = &rx_ring->rx_buffer_info[i];
9a799d71 610 }
7c6e0a43 611
9a799d71
AK		 612no_buffers:
613 if (rx_ring->next_to_use != i) {
614 rx_ring->next_to_use = i;
615 if (i-- == 0)
616 i = (rx_ring->count - 1);
617
e8e26350 618 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 619 }
620}
621
7c6e0a43
JB		 622static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
623{
624 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
625}
626
627static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
628{
629 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
630}
631
f8212f97
AD		 632static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
633{
634 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
635 IXGBE_RXDADV_RSCCNT_MASK) >>
636 IXGBE_RXDADV_RSCCNT_SHIFT;
637}
638
639/**
640 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
641 * @skb: pointer to the last skb in the rsc queue
642 *
643 * This function changes a queue full of hw rsc buffers into a completed
644 * packet. It uses the ->prev pointers to find the first packet and then
645 * turns it into the frag list owner.
646 **/
647static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
648{
649 unsigned int frag_list_size = 0;
650
651 while (skb->prev) {
652 struct sk_buff *prev = skb->prev;
653 frag_list_size += skb->len;
654 skb->prev = NULL;
655 skb = prev;
656 }
657
658 skb_shinfo(skb)->frag_list = skb->next;
659 skb->next = NULL;
660 skb->len += frag_list_size;
661 skb->data_len += frag_list_size;
662 skb->truesize += frag_list_size;
663 return skb;
664}
665
78b6f4ce 666static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 667 struct ixgbe_ring *rx_ring,
668 int *work_done, int work_to_do)
9a799d71 669{
78b6f4ce 670 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 671 struct pci_dev *pdev = adapter->pdev;
672 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
673 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
674 struct sk_buff *skb;
f8212f97 675 unsigned int i, rsc_count = 0;
7c6e0a43 676 u32 len, staterr;
177db6ff
MC		 677 u16 hdr_info;
678 bool cleaned = false;
9a799d71 679 int cleaned_count = 0;
d2f4fbe2 680 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 681
682 i = rx_ring->next_to_clean;
9a799d71
AK		 683 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
684 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
685 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 686
687 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 688 u32 upper_len = 0;
9a799d71
AK		 689 if (*work_done >= work_to_do)
690 break;
691 (*work_done)++;
692
693 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 694 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
695 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 696 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 697 if (hdr_info & IXGBE_RXDADV_SPH)
698 adapter->rx_hdr_split++;
699 if (len > IXGBE_RX_HDR_SIZE)
700 len = IXGBE_RX_HDR_SIZE;
701 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 702 } else {
9a799d71 703 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 704 }
9a799d71
AK		 705
706 cleaned = true;
707 skb = rx_buffer_info->skb;
708 prefetch(skb->data - NET_IP_ALIGN);
709 rx_buffer_info->skb = NULL;
710
711 if (len && !skb_shinfo(skb)->nr_frags) {
712 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 713 rx_ring->rx_buf_len,
b4617240 714 PCI_DMA_FROMDEVICE);
9a799d71
AK		 715 skb_put(skb, len);
716 }
717
718 if (upper_len) {
719 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 720 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 721 rx_buffer_info->page_dma = 0;
722 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 723 rx_buffer_info->page,
724 rx_buffer_info->page_offset,
725 upper_len);
726
727 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
728 (page_count(rx_buffer_info->page) != 1))
729 rx_buffer_info->page = NULL;
730 else
731 get_page(rx_buffer_info->page);
9a799d71
AK		 732
733 skb->len += upper_len;
734 skb->data_len += upper_len;
735 skb->truesize += upper_len;
736 }
737
738 i++;
739 if (i == rx_ring->count)
740 i = 0;
9a799d71
AK		 741
742 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
743 prefetch(next_rxd);
9a799d71 744 cleaned_count++;
f8212f97
AD		 745
746 if (adapter->flags & IXGBE_FLAG_RSC_CAPABLE)
747 rsc_count = ixgbe_get_rsc_count(rx_desc);
748
749 if (rsc_count) {
750 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
751 IXGBE_RXDADV_NEXTP_SHIFT;
752 next_buffer = &rx_ring->rx_buffer_info[nextp];
753 rx_ring->rsc_count += (rsc_count - 1);
754 } else {
755 next_buffer = &rx_ring->rx_buffer_info[i];
756 }
757
9a799d71 758 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 759 if (skb->prev)
760 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 761 rx_ring->stats.packets++;
762 rx_ring->stats.bytes += skb->len;
763 } else {
f8212f97
AD		 764 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
765 rx_buffer_info->skb = next_buffer->skb;
766 rx_buffer_info->dma = next_buffer->dma;
767 next_buffer->skb = skb;
768 next_buffer->dma = 0;
769 } else {
770 skb->next = next_buffer->skb;
771 skb->next->prev = skb;
772 }
9a799d71
AK		 773 adapter->non_eop_descs++;
774 goto next_desc;
775 }
776
777 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
778 dev_kfree_skb_irq(skb);
779 goto next_desc;
780 }
781
782 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 783
784 /* probably a little skewed due to removing CRC */
785 total_rx_bytes += skb->len;
786 total_rx_packets++;
787
74ce8dd2 788 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 789#ifdef IXGBE_FCOE
790 /* if ddp, not passing to ULD unless for FCP_RSP or error */
791 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
792 if (!ixgbe_fcoe_ddp(adapter, rx_desc, skb))
793 goto next_desc;
794#endif /* IXGBE_FCOE */
fdaff1ce 795 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 796
797next_desc:
798 rx_desc->wb.upper.status_error = 0;
799
800 /* return some buffers to hardware, one at a time is too slow */
801 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
802 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
803 cleaned_count = 0;
804 }
805
806 /* use prefetched values */
807 rx_desc = next_rxd;
f8212f97 808 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 809
810 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 811 }
812
9a799d71
AK		 813 rx_ring->next_to_clean = i;
814 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
815
816 if (cleaned_count)
817 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
818
f494e8fa
AV		 819 rx_ring->total_packets += total_rx_packets;
820 rx_ring->total_bytes += total_rx_bytes;
821 adapter->net_stats.rx_bytes += total_rx_bytes;
822 adapter->net_stats.rx_packets += total_rx_packets;
823
9a799d71
AK		 824 return cleaned;
825}
826
021230d4 827static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 828/**
829 * ixgbe_configure_msix - Configure MSI-X hardware
830 * @adapter: board private structure
831 *
832 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
833 * interrupts.
834 **/
835static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
836{
021230d4
AV		 837 struct ixgbe_q_vector *q_vector;
838 int i, j, q_vectors, v_idx, r_idx;
839 u32 mask;
9a799d71 840
021230d4 841 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 842
4df10466
JB		 843 /*
844 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 845 * corresponding register.
846 */
847 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 848 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 849 /* XXX for_each_bit(...) */
850 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 851 adapter->num_rx_queues);
021230d4
AV		 852
853 for (i = 0; i < q_vector->rxr_count; i++) {
854 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 855 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 856 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 857 adapter->num_rx_queues,
858 r_idx + 1);
021230d4
AV		 859 }
860 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 861 adapter->num_tx_queues);
021230d4
AV		 862
863 for (i = 0; i < q_vector->txr_count; i++) {
864 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 865 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 866 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 867 adapter->num_tx_queues,
868 r_idx + 1);
021230d4
AV		 869 }
870
30efa5a3 871 /* if this is a tx only vector halve the interrupt rate */
021230d4 872 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 873 q_vector->eitr = (adapter->eitr_param >> 1);
509ee935 874 else if (q_vector->rxr_count)
30efa5a3
JB		 875 /* rx only */
876 q_vector->eitr = adapter->eitr_param;
021230d4 877
509ee935 878 /*
4df10466 879 * since this is initial set up don't need to call
509ee935
JB		 880 * ixgbe_write_eitr helper
881 */
021230d4 882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 883 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 884 }
885
e8e26350
PW		 886 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
887 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
888 v_idx);
889 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
890 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 891 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
892
41fb9248 893 /* set up to autoclear timer, and the vectors */
021230d4 894 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 895 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 896 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 897}
898
f494e8fa
AV		 899enum latency_range {
900 lowest_latency = 0,
901 low_latency = 1,
902 bulk_latency = 2,
903 latency_invalid = 255
904};
905
906/**
907 * ixgbe_update_itr - update the dynamic ITR value based on statistics
908 * @adapter: pointer to adapter
909 * @eitr: eitr setting (ints per sec) to give last timeslice
910 * @itr_setting: current throttle rate in ints/second
911 * @packets: the number of packets during this measurement interval
912 * @bytes: the number of bytes during this measurement interval
913 *
914 * Stores a new ITR value based on packets and byte
915 * counts during the last interrupt. The advantage of per interrupt
916 * computation is faster updates and more accurate ITR for the current
917 * traffic pattern. Constants in this function were computed
918 * based on theoretical maximum wire speed and thresholds were set based
919 * on testing data as well as attempting to minimize response time
920 * while increasing bulk throughput.
921 * this functionality is controlled by the InterruptThrottleRate module
922 * parameter (see ixgbe_param.c)
923 **/
924static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 925 u32 eitr, u8 itr_setting,
926 int packets, int bytes)
f494e8fa
AV		 927{
928 unsigned int retval = itr_setting;
929 u32 timepassed_us;
930 u64 bytes_perint;
931
932 if (packets == 0)
933 goto update_itr_done;
934
935
936 /* simple throttlerate management
937 * 0-20MB/s lowest (100000 ints/s)
938 * 20-100MB/s low (20000 ints/s)
939 * 100-1249MB/s bulk (8000 ints/s)
940 */
941 /* what was last interrupt timeslice? */
942 timepassed_us = 1000000/eitr;
943 bytes_perint = bytes / timepassed_us; /* bytes/usec */
944
945 switch (itr_setting) {
946 case lowest_latency:
947 if (bytes_perint > adapter->eitr_low)
948 retval = low_latency;
949 break;
950 case low_latency:
951 if (bytes_perint > adapter->eitr_high)
952 retval = bulk_latency;
953 else if (bytes_perint <= adapter->eitr_low)
954 retval = lowest_latency;
955 break;
956 case bulk_latency:
957 if (bytes_perint <= adapter->eitr_high)
958 retval = low_latency;
959 break;
960 }
961
962update_itr_done:
963 return retval;
964}
965
509ee935
JB		 966/**
967 * ixgbe_write_eitr - write EITR register in hardware specific way
968 * @adapter: pointer to adapter struct
969 * @v_idx: vector index into q_vector array
970 * @itr_reg: new value to be written in *register* format, not ints/s
971 *
972 * This function is made to be called by ethtool and by the driver
973 * when it needs to update EITR registers at runtime. Hardware
974 * specific quirks/differences are taken care of here.
975 */
976void ixgbe_write_eitr(struct ixgbe_adapter *adapter, int v_idx, u32 itr_reg)
977{
978 struct ixgbe_hw *hw = &adapter->hw;
979 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
980 /* must write high and low 16 bits to reset counter */
981 itr_reg |= (itr_reg << 16);
982 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
983 /*
984 * set the WDIS bit to not clear the timer bits and cause an
985 * immediate assertion of the interrupt
986 */
987 itr_reg |= IXGBE_EITR_CNT_WDIS;
988 }
989 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
990}
991
f494e8fa
AV		 992static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
993{
994 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 995 u32 new_itr;
996 u8 current_itr, ret_itr;
7a921c93 997 int i, r_idx, v_idx = q_vector->v_idx;
f494e8fa
AV		 998 struct ixgbe_ring *rx_ring, *tx_ring;
999
1000 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1001 for (i = 0; i < q_vector->txr_count; i++) {
1002 tx_ring = &(adapter->tx_ring[r_idx]);
1003 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1004 q_vector->tx_itr,
1005 tx_ring->total_packets,
1006 tx_ring->total_bytes);
f494e8fa
AV		 1007 /* if the result for this queue would decrease interrupt
1008 * rate for this vector then use that result */
30efa5a3 1009 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1010 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1011 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1012 r_idx + 1);
f494e8fa
AV		 1013 }
1014
1015 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1016 for (i = 0; i < q_vector->rxr_count; i++) {
1017 rx_ring = &(adapter->rx_ring[r_idx]);
1018 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1019 q_vector->rx_itr,
1020 rx_ring->total_packets,
1021 rx_ring->total_bytes);
f494e8fa
AV		 1022 /* if the result for this queue would decrease interrupt
1023 * rate for this vector then use that result */
30efa5a3 1024 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1025 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1026 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1027 r_idx + 1);
f494e8fa
AV		 1028 }
1029
30efa5a3 1030 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1031
1032 switch (current_itr) {
1033 /* counts and packets in update_itr are dependent on these numbers */
1034 case lowest_latency:
1035 new_itr = 100000;
1036 break;
1037 case low_latency:
1038 new_itr = 20000; /* aka hwitr = ~200 */
1039 break;
1040 case bulk_latency:
1041 default:
1042 new_itr = 8000;
1043 break;
1044 }
1045
1046 if (new_itr != q_vector->eitr) {
1047 u32 itr_reg;
509ee935
JB		 1048
1049 /* save the algorithm value here, not the smoothed one */
1050 q_vector->eitr = new_itr;
f494e8fa
AV		 1051 /* do an exponential smoothing */
1052 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1053 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1054 ixgbe_write_eitr(adapter, v_idx, itr_reg);
f494e8fa
AV		 1055 }
1056
1057 return;
1058}
1059
0befdb3e
JB		 1060static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1061{
1062 struct ixgbe_hw *hw = &adapter->hw;
1063
1064 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1065 (eicr & IXGBE_EICR_GPI_SDP1)) {
1066 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1067 /* write to clear the interrupt */
1068 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1069 }
1070}
cf8280ee 1071
e8e26350
PW		 1072static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1073{
1074 struct ixgbe_hw *hw = &adapter->hw;
1075
1076 if (eicr & IXGBE_EICR_GPI_SDP1) {
1077 /* Clear the interrupt */
1078 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1079 schedule_work(&adapter->multispeed_fiber_task);
1080 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1081 /* Clear the interrupt */
1082 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1083 schedule_work(&adapter->sfp_config_module_task);
1084 } else {
1085 /* Interrupt isn't for us... */
1086 return;
1087 }
1088}
1089
cf8280ee
JB		 1090static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1091{
1092 struct ixgbe_hw *hw = &adapter->hw;
1093
1094 adapter->lsc_int++;
1095 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1096 adapter->link_check_timeout = jiffies;
1097 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1098 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1099 schedule_work(&adapter->watchdog_task);
1100 }
1101}
1102
9a799d71
AK		 1103static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1104{
1105 struct net_device *netdev = data;
1106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1107 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1108 u32 eicr;
1109
1110 /*
1111 * Workaround for Silicon errata. Use clear-by-write instead
1112 * of clear-by-read. Reading with EICS will return the
1113 * interrupt causes without clearing, which later be done
1114 * with the write to EICR.
1115 */
1116 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1117 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1118
cf8280ee
JB		 1119 if (eicr & IXGBE_EICR_LSC)
1120 ixgbe_check_lsc(adapter);
d4f80882 1121
e8e26350
PW		 1122 if (hw->mac.type == ixgbe_mac_82598EB)
1123 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1124
e8e26350
PW		 1125 if (hw->mac.type == ixgbe_mac_82599EB)
1126 ixgbe_check_sfp_event(adapter, eicr);
d4f80882
AV		 1127 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1129
1130 return IRQ_HANDLED;
1131}
1132
1133static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1134{
021230d4
AV		 1135 struct ixgbe_q_vector *q_vector = data;
1136 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1137 struct ixgbe_ring *tx_ring;
021230d4
AV		 1138 int i, r_idx;
1139
1140 if (!q_vector->txr_count)
1141 return IRQ_HANDLED;
1142
1143 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1144 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1145 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 1146#ifdef CONFIG_IXGBE_DCA
bd0362dd 1147 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1148 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 1149#endif
3a581073
JB		 1150 tx_ring->total_bytes = 0;
1151 tx_ring->total_packets = 0;
1152 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 1153 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1154 r_idx + 1);
021230d4 1155 }
9a799d71 1156
9a799d71
AK		 1157 return IRQ_HANDLED;
1158}
1159
021230d4
AV		 1160/**
1161 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1162 * @irq: unused
1163 * @data: pointer to our q_vector struct for this interrupt vector
1164 **/
9a799d71
AK		 1165static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1166{
021230d4
AV		 1167 struct ixgbe_q_vector *q_vector = data;
1168 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1169 struct ixgbe_ring *rx_ring;
021230d4 1170 int r_idx;
30efa5a3 1171 int i;
021230d4
AV		 1172
1173 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1174 for (i = 0; i < q_vector->rxr_count; i++) {
1175 rx_ring = &(adapter->rx_ring[r_idx]);
1176 rx_ring->total_bytes = 0;
1177 rx_ring->total_packets = 0;
1178 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1179 r_idx + 1);
1180 }
1181
021230d4
AV		 1182 if (!q_vector->rxr_count)
1183 return IRQ_HANDLED;
1184
30efa5a3 1185 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1186 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1187 /* disable interrupts on this vector only */
835462fc
NS		 1188 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1189 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
1190 else if (rx_ring->v_idx & 0xFFFFFFFF)
1191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), rx_ring->v_idx);
1192 else
1193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1),
1194 (rx_ring->v_idx >> 32));
288379f0 1195 napi_schedule(&q_vector->napi);
021230d4
AV		 1196
1197 return IRQ_HANDLED;
1198}
1199
1200static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1201{
1202 ixgbe_msix_clean_rx(irq, data);
1203 ixgbe_msix_clean_tx(irq, data);
9a799d71 1204
9a799d71
AK		 1205 return IRQ_HANDLED;
1206}
1207
835462fc
NS		 1208static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1209 u64 qmask)
1210{
1211 u32 mask;
1212
1213 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1214 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1216 } else {
1217 mask = (qmask & 0xFFFFFFFF);
1218 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1219 mask = (qmask >> 32);
1220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1221 }
1222 /* skip the flush */
1223}
1224
021230d4
AV		 1225/**
1226 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1227 * @napi: napi struct with our devices info in it
1228 * @budget: amount of work driver is allowed to do this pass, in packets
1229 *
f0848276
JB		 1230 * This function is optimized for cleaning one queue only on a single
1231 * q_vector!!!
021230d4 1232 **/
9a799d71
AK		 1233static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1234{
021230d4 1235 struct ixgbe_q_vector *q_vector =
b4617240 1236 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1237 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1238 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1239 int work_done = 0;
021230d4 1240 long r_idx;
9a799d71 1241
021230d4 1242 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1243 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1244#ifdef CONFIG_IXGBE_DCA
bd0362dd 1245 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1246 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1247#endif
9a799d71 1248
78b6f4ce 1249 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1250
021230d4
AV		 1251 /* If all Rx work done, exit the polling mode */
1252 if (work_done < budget) {
288379f0 1253 napi_complete(napi);
509ee935 1254 if (adapter->itr_setting & 1)
f494e8fa 1255 ixgbe_set_itr_msix(q_vector);
9a799d71 1256 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1257 ixgbe_irq_enable_queues(adapter, rx_ring->v_idx);
9a799d71
AK		 1258 }
1259
1260 return work_done;
1261}
1262
f0848276
JB		 1263/**
1264 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1265 * @napi: napi struct with our devices info in it
1266 * @budget: amount of work driver is allowed to do this pass, in packets
1267 *
1268 * This function will clean more than one rx queue associated with a
1269 * q_vector.
1270 **/
1271static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1272{
1273 struct ixgbe_q_vector *q_vector =
1274 container_of(napi, struct ixgbe_q_vector, napi);
1275 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1276 struct ixgbe_ring *rx_ring = NULL;
1277 int work_done = 0, i;
1278 long r_idx;
835462fc 1279 u64 enable_mask = 0;
f0848276
JB		 1280
1281 /* attempt to distribute budget to each queue fairly, but don't allow
1282 * the budget to go below 1 because we'll exit polling */
1283 budget /= (q_vector->rxr_count ?: 1);
1284 budget = max(budget, 1);
1285 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1286 for (i = 0; i < q_vector->rxr_count; i++) {
1287 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1288#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1289 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1290 ixgbe_update_rx_dca(adapter, rx_ring);
1291#endif
78b6f4ce 1292 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
f0848276
JB		 1293 enable_mask |= rx_ring->v_idx;
1294 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1295 r_idx + 1);
1296 }
1297
1298 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1299 rx_ring = &(adapter->rx_ring[r_idx]);
1300 /* If all Rx work done, exit the polling mode */
7f821875 1301 if (work_done < budget) {
288379f0 1302 napi_complete(napi);
509ee935 1303 if (adapter->itr_setting & 1)
f0848276
JB		 1304 ixgbe_set_itr_msix(q_vector);
1305 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 1306 ixgbe_irq_enable_queues(adapter, enable_mask);
f0848276
JB		 1307 return 0;
1308 }
1309
1310 return work_done;
1311}
021230d4 1312static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1313 int r_idx)
021230d4 1314{
7a921c93
AD		 1315 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1316
1317 set_bit(r_idx, q_vector->rxr_idx);
1318 q_vector->rxr_count++;
c9c7d2e5 1319 a->rx_ring[r_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1320}
1321
1322static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1323 int t_idx)
021230d4 1324{
7a921c93
AD		 1325 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1326
1327 set_bit(t_idx, q_vector->txr_idx);
1328 q_vector->txr_count++;
c9c7d2e5 1329 a->tx_ring[t_idx].v_idx = (u64)1 << v_idx;
021230d4
AV		 1330}
1331
9a799d71 1332/**
021230d4
AV		 1333 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1334 * @adapter: board private structure to initialize
1335 * @vectors: allotted vector count for descriptor rings
9a799d71 1336 *
021230d4
AV		 1337 * This function maps descriptor rings to the queue-specific vectors
1338 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1339 * one vector per ring/queue, but on a constrained vector budget, we
1340 * group the rings as "efficiently" as possible. You would add new
1341 * mapping configurations in here.
9a799d71 1342 **/
021230d4 1343static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1344 int vectors)
021230d4
AV		 1345{
1346 int v_start = 0;
1347 int rxr_idx = 0, txr_idx = 0;
1348 int rxr_remaining = adapter->num_rx_queues;
1349 int txr_remaining = adapter->num_tx_queues;
1350 int i, j;
1351 int rqpv, tqpv;
1352 int err = 0;
1353
1354 /* No mapping required if MSI-X is disabled. */
1355 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1356 goto out;
9a799d71 1357
021230d4
AV		 1358 /*
1359 * The ideal configuration...
1360 * We have enough vectors to map one per queue.
1361 */
1362 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1363 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1364 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1365
021230d4
AV		 1366 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1367 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1368
9a799d71 1369 goto out;
021230d4 1370 }
9a799d71 1371
021230d4
AV		 1372 /*
1373 * If we don't have enough vectors for a 1-to-1
1374 * mapping, we'll have to group them so there are
1375 * multiple queues per vector.
1376 */
1377 /* Re-adjusting *qpv takes care of the remainder. */
1378 for (i = v_start; i < vectors; i++) {
1379 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1380 for (j = 0; j < rqpv; j++) {
1381 map_vector_to_rxq(adapter, i, rxr_idx);
1382 rxr_idx++;
1383 rxr_remaining--;
1384 }
1385 }
1386 for (i = v_start; i < vectors; i++) {
1387 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1388 for (j = 0; j < tqpv; j++) {
1389 map_vector_to_txq(adapter, i, txr_idx);
1390 txr_idx++;
1391 txr_remaining--;
9a799d71 1392 }
9a799d71
AK		 1393 }
1394
021230d4
AV		 1395out:
1396 return err;
1397}
1398
1399/**
1400 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1401 * @adapter: board private structure
1402 *
1403 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1404 * interrupts from the kernel.
1405 **/
1406static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1407{
1408 struct net_device *netdev = adapter->netdev;
1409 irqreturn_t (*handler)(int, void *);
1410 int i, vector, q_vectors, err;
cb13fc20 1411 int ri=0, ti=0;
021230d4
AV		 1412
1413 /* Decrement for Other and TCP Timer vectors */
1414 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1415
1416 /* Map the Tx/Rx rings to the vectors we were allotted. */
1417 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1418 if (err)
1419 goto out;
1420
1421#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1422 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1423 &ixgbe_msix_clean_many)
021230d4 1424 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1425 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1426
1427 if(handler == &ixgbe_msix_clean_rx) {
1428 sprintf(adapter->name[vector], "%s-%s-%d",
1429 netdev->name, "rx", ri++);
1430 }
1431 else if(handler == &ixgbe_msix_clean_tx) {
1432 sprintf(adapter->name[vector], "%s-%s-%d",
1433 netdev->name, "tx", ti++);
1434 }
1435 else
1436 sprintf(adapter->name[vector], "%s-%s-%d",
1437 netdev->name, "TxRx", vector);
1438
021230d4 1439 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1440 handler, 0, adapter->name[vector],
7a921c93 1441 adapter->q_vector[vector]);
9a799d71
AK		 1442 if (err) {
1443 DPRINTK(PROBE, ERR,
b4617240
PW		 1444 "request_irq failed for MSIX interrupt "
1445 "Error: %d\n", err);
021230d4 1446 goto free_queue_irqs;
9a799d71 1447 }
9a799d71
AK		 1448 }
1449
021230d4
AV		 1450 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1451 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1452 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1453 if (err) {
1454 DPRINTK(PROBE, ERR,
1455 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1456 goto free_queue_irqs;
9a799d71
AK		 1457 }
1458
9a799d71
AK		 1459 return 0;
1460
021230d4
AV		 1461free_queue_irqs:
1462 for (i = vector - 1; i >= 0; i--)
1463 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1464 adapter->q_vector[i]);
021230d4
AV		 1465 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1466 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1467 kfree(adapter->msix_entries);
1468 adapter->msix_entries = NULL;
021230d4 1469out:
9a799d71
AK		 1470 return err;
1471}
1472
f494e8fa
AV		 1473static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1474{
7a921c93 1475 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1476 u8 current_itr;
1477 u32 new_itr = q_vector->eitr;
1478 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1479 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1480
30efa5a3 1481 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1482 q_vector->tx_itr,
1483 tx_ring->total_packets,
1484 tx_ring->total_bytes);
30efa5a3 1485 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1486 q_vector->rx_itr,
1487 rx_ring->total_packets,
1488 rx_ring->total_bytes);
f494e8fa 1489
30efa5a3 1490 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1491
1492 switch (current_itr) {
1493 /* counts and packets in update_itr are dependent on these numbers */
1494 case lowest_latency:
1495 new_itr = 100000;
1496 break;
1497 case low_latency:
1498 new_itr = 20000; /* aka hwitr = ~200 */
1499 break;
1500 case bulk_latency:
1501 new_itr = 8000;
1502 break;
1503 default:
1504 break;
1505 }
1506
1507 if (new_itr != q_vector->eitr) {
1508 u32 itr_reg;
509ee935
JB		 1509
1510 /* save the algorithm value here, not the smoothed one */
1511 q_vector->eitr = new_itr;
f494e8fa
AV		 1512 /* do an exponential smoothing */
1513 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
f494e8fa 1514 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
509ee935 1515 ixgbe_write_eitr(adapter, 0, itr_reg);
f494e8fa
AV		 1516 }
1517
1518 return;
1519}
1520
79aefa45
AD		 1521/**
1522 * ixgbe_irq_enable - Enable default interrupt generation settings
1523 * @adapter: board private structure
1524 **/
1525static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1526{
1527 u32 mask;
835462fc
NS		 1528
1529 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1530 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1531 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1532 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1533 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1534 mask |= IXGBE_EIMS_GPI_SDP1;
1535 mask |= IXGBE_EIMS_GPI_SDP2;
1536 }
1537
79aefa45 1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1539 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1540 IXGBE_WRITE_FLUSH(&adapter->hw);
1541}
021230d4 1542
9a799d71 1543/**
021230d4 1544 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1545 * @irq: interrupt number
1546 * @data: pointer to a network interface device structure
9a799d71
AK		 1547 **/
1548static irqreturn_t ixgbe_intr(int irq, void *data)
1549{
1550 struct net_device *netdev = data;
1551 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1552 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1553 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1554 u32 eicr;
1555
54037505
DS		 1556 /*
1557 * Workaround for silicon errata. Mask the interrupts
1558 * before the read of EICR.
1559 */
1560 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1561
021230d4
AV		 1562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1563 * therefore no explict interrupt disable is necessary */
1564 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1565 if (!eicr) {
1566 /* shared interrupt alert!
1567 * make sure interrupts are enabled because the read will
1568 * have disabled interrupts due to EIAM */
1569 ixgbe_irq_enable(adapter);
9a799d71 1570 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1571 }
9a799d71 1572
cf8280ee
JB		 1573 if (eicr & IXGBE_EICR_LSC)
1574 ixgbe_check_lsc(adapter);
021230d4 1575
e8e26350
PW		 1576 if (hw->mac.type == ixgbe_mac_82599EB)
1577 ixgbe_check_sfp_event(adapter, eicr);
1578
0befdb3e
JB		 1579 ixgbe_check_fan_failure(adapter, eicr);
1580
7a921c93 1581 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1582 adapter->tx_ring[0].total_packets = 0;
1583 adapter->tx_ring[0].total_bytes = 0;
1584 adapter->rx_ring[0].total_packets = 0;
1585 adapter->rx_ring[0].total_bytes = 0;
021230d4 1586 /* would disable interrupts here but EIAM disabled it */
7a921c93 1587 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1588 }
1589
1590 return IRQ_HANDLED;
1591}
1592
021230d4
AV		 1593static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1594{
1595 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1596
1597 for (i = 0; i < q_vectors; i++) {
7a921c93 1598 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1599 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1600 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1601 q_vector->rxr_count = 0;
1602 q_vector->txr_count = 0;
1603 }
1604}
1605
9a799d71
AK		 1606/**
1607 * ixgbe_request_irq - initialize interrupts
1608 * @adapter: board private structure
1609 *
1610 * Attempts to configure interrupts using the best available
1611 * capabilities of the hardware and kernel.
1612 **/
021230d4 1613static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1614{
1615 struct net_device *netdev = adapter->netdev;
021230d4 1616 int err;
9a799d71 1617
021230d4
AV		 1618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1619 err = ixgbe_request_msix_irqs(adapter);
1620 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1621 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1622 netdev->name, netdev);
021230d4
AV		 1623 } else {
1624 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1625 netdev->name, netdev);
9a799d71
AK		 1626 }
1627
9a799d71
AK		 1628 if (err)
1629 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1630
9a799d71
AK		 1631 return err;
1632}
1633
1634static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1635{
1636 struct net_device *netdev = adapter->netdev;
1637
1638 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1639 int i, q_vectors;
9a799d71 1640
021230d4
AV		 1641 q_vectors = adapter->num_msix_vectors;
1642
1643 i = q_vectors - 1;
9a799d71 1644 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1645
021230d4
AV		 1646 i--;
1647 for (; i >= 0; i--) {
1648 free_irq(adapter->msix_entries[i].vector,
7a921c93 1649 adapter->q_vector[i]);
021230d4
AV		 1650 }
1651
1652 ixgbe_reset_q_vectors(adapter);
1653 } else {
1654 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1655 }
1656}
1657
22d5a71b
JB		 1658/**
1659 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1660 * @adapter: board private structure
1661 **/
1662static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1663{
835462fc
NS		 1664 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1666 } else {
1667 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1669 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1670 }
1671 IXGBE_WRITE_FLUSH(&adapter->hw);
1672 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1673 int i;
1674 for (i = 0; i < adapter->num_msix_vectors; i++)
1675 synchronize_irq(adapter->msix_entries[i].vector);
1676 } else {
1677 synchronize_irq(adapter->pdev->irq);
1678 }
1679}
1680
9a799d71
AK		 1681/**
1682 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1683 *
1684 **/
1685static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1686{
9a799d71
AK		 1687 struct ixgbe_hw *hw = &adapter->hw;
1688
021230d4 1689 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1690 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71 1691
e8e26350
PW		 1692 ixgbe_set_ivar(adapter, 0, 0, 0);
1693 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1694
1695 map_vector_to_rxq(adapter, 0, 0);
1696 map_vector_to_txq(adapter, 0, 0);
1697
1698 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1699}
1700
1701/**
3a581073 1702 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1703 * @adapter: board private structure
1704 *
1705 * Configure the Tx unit of the MAC after a reset.
1706 **/
1707static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1708{
12207e49 1709 u64 tdba;
9a799d71 1710 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1711 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1712
1713 /* Setup the HW Tx Head and Tail descriptor pointers */
1714 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1715 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1716 j = ring->reg_idx;
1717 tdba = ring->dma;
1718 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1719 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1720 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1721 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1722 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1723 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1724 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1725 adapter->tx_ring[i].head = IXGBE_TDH(j);
1726 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1727 /* Disable Tx Head Writeback RO bit, since this hoses
1728 * bookkeeping if things aren't delivered in order.
1729 */
e01c31a5 1730 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1731 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1732 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1733 }
e8e26350
PW		 1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 /* We enable 8 traffic classes, DCB only */
1736 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1737 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1738 IXGBE_MTQC_8TC_8TQ));
1739 }
9a799d71
AK		 1740}
1741
e8e26350 1742#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c
JB		 1743
1744static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1745{
1746 struct ixgbe_ring *rx_ring;
1747 u32 srrctl;
e8e26350 1748 int queue0 = 0;
3be1adfb
AD		 1749 unsigned long mask;
1750
e8e26350 1751 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
163de42e
AD		 1752 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1753 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
1754 if (dcb_i == 8)
1755 queue0 = index >> 4;
1756 else if (dcb_i == 4)
1757 queue0 = index >> 5;
1758 else
1759 dev_err(&adapter->pdev->dev, "Invalid DCB "
1760 "configuration\n");
0331a832
YZ		 1761#ifdef IXGBE_FCOE
1762 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1763 struct ixgbe_ring_feature *f;
1764
1765 rx_ring = &adapter->rx_ring[queue0];
1766 f = &adapter->ring_feature[RING_F_FCOE];
1767 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1768 queue0 = f->mask + index -
1769 rx_ring->reg_idx - 1;
1770 }
1771#endif /* IXGBE_FCOE */
163de42e
AD		 1772 } else {
1773 queue0 = index;
1774 }
cc41ac7c 1775 } else {
3be1adfb
AD		 1776 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1777 queue0 = index & mask;
1778 index = index & mask;
cc41ac7c 1779 }
3be1adfb 1780
cc41ac7c
JB		 1781 rx_ring = &adapter->rx_ring[queue0];
1782
1783 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1784
1785 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1786 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1787
afafd5b0
AD		 1788 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1789 IXGBE_SRRCTL_BSIZEHDR_MASK;
1790
cc41ac7c 1791 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
afafd5b0
AD		 1792#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1793 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1794#else
1795 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1796#endif
cc41ac7c 1797 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1798 } else {
afafd5b0
AD		 1799 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1800 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1801 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1802 }
e8e26350 1803
cc41ac7c
JB		 1804 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1805}
9a799d71 1806
9a799d71 1807/**
3a581073 1808 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1809 * @adapter: board private structure
1810 *
1811 * Configure the Rx unit of the MAC after a reset.
1812 **/
1813static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1814{
1815 u64 rdba;
1816 struct ixgbe_hw *hw = &adapter->hw;
1817 struct net_device *netdev = adapter->netdev;
1818 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1819 int i, j;
9a799d71 1820 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1821 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1822 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1823 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1824 u32 fctrl, hlreg0;
509ee935 1825 u32 reta = 0, mrqc = 0;
cc41ac7c 1826 u32 rdrxctl;
f8212f97 1827 u32 rscctrl;
7c6e0a43 1828 int rx_buf_len;
9a799d71
AK		 1829
1830 /* Decide whether to use packet split mode or not */
762f4c57 1831 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 1832
eacd73f7
YZ		 1833#ifdef IXGBE_FCOE
1834 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1835 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
1836#endif /* IXGBE_FCOE */
1837
9a799d71
AK		 1838 /* Set the RX buffer length according to the mode */
1839 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1840 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 1841 if (hw->mac.type == ixgbe_mac_82599EB) {
1842 /* PSRTYPE must be initialized in 82599 */
1843 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
1844 IXGBE_PSRTYPE_UDPHDR |
1845 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 1846 IXGBE_PSRTYPE_IPV6HDR |
1847 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 1848 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
1849 }
9a799d71 1850 } else {
f8212f97
AD		 1851 if (!(adapter->flags & IXGBE_FLAG_RSC_ENABLED) &&
1852 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 1853 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1854 else
7c6e0a43 1855 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1856 }
1857
1858 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1859 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1860 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 1861 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 1862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1863
1864 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1865 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1866 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1867 else
1868 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1
YZ		 1869#ifdef IXGBE_FCOE
1870 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
1871 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1872#endif
9a799d71
AK		 1873 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1874
9a799d71
AK		 1875 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1876 /* disable receives while setting up the descriptors */
1877 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1878 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1879
1880 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1881 * the Base and Length of the Rx Descriptor Ring */
1882 for (i = 0; i < adapter->num_rx_queues; i++) {
1883 rdba = adapter->rx_ring[i].dma;
7c6e0a43 1884 j = adapter->rx_ring[i].reg_idx;
284901a9 1885 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 1886 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1887 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1888 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1889 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1890 adapter->rx_ring[i].head = IXGBE_RDH(j);
1891 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1892 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
cc41ac7c 1893
63f39bd1
YZ		 1894#ifdef IXGBE_FCOE
1895 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1896 struct ixgbe_ring_feature *f;
1897 f = &adapter->ring_feature[RING_F_FCOE];
1898 if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
1899 (i >= f->mask) && (i < f->mask + f->indices))
1900 adapter->rx_ring[i].rx_buf_len =
1901 IXGBE_FCOE_JUMBO_FRAME_SIZE;
1902 }
1903
1904#endif /* IXGBE_FCOE */
cc41ac7c 1905 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1906 }
1907
e8e26350
PW		 1908 if (hw->mac.type == ixgbe_mac_82598EB) {
1909 /*
1910 * For VMDq support of different descriptor types or
1911 * buffer sizes through the use of multiple SRRCTL
1912 * registers, RDRXCTL.MVMEN must be set to 1
1913 *
1914 * also, the manual doesn't mention it clearly but DCA hints
1915 * will only use queue 0's tags unless this bit is set. Side
1916 * effects of setting this bit are only that SRRCTL must be
1917 * fully programmed [0..15]
1918 */
2a41ff81
JB		 1919 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1920 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1921 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 1922 }
177db6ff 1923
e8e26350
PW		 1924 /* Program MRQC for the distribution of queues */
1925 if (hw->mac.type == ixgbe_mac_82599EB) {
1926 int mask = adapter->flags & (
1927 IXGBE_FLAG_RSS_ENABLED
1928 | IXGBE_FLAG_DCB_ENABLED
1929 );
1930
1931 switch (mask) {
1932 case (IXGBE_FLAG_RSS_ENABLED):
1933 mrqc = IXGBE_MRQC_RSSEN;
1934 break;
1935 case (IXGBE_FLAG_DCB_ENABLED):
1936 mrqc = IXGBE_MRQC_RT8TCEN;
1937 break;
1938 default:
1939 break;
1940 }
1941 }
021230d4 1942 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1943 /* Fill out redirection table */
021230d4
AV		 1944 for (i = 0, j = 0; i < 128; i++, j++) {
1945 if (j == adapter->ring_feature[RING_F_RSS].indices)
1946 j = 0;
1947 /* reta = 4-byte sliding window of
1948 * 0x00..(indices-1)(indices-1)00..etc. */
1949 reta = (reta << 8) | (j * 0x11);
1950 if ((i & 3) == 3)
1951 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1952 }
1953
1954 /* Fill out hash function seeds */
1955 for (i = 0; i < 10; i++)
7c6e0a43 1956 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 1957
2a41ff81
JB		 1958 if (hw->mac.type == ixgbe_mac_82598EB)
1959 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 1960 /* Perform hash on these packet types */
2a41ff81
JB		 1961 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
1962 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1963 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1964 | IXGBE_MRQC_RSS_FIELD_IPV6
1965 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1966 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 1967 }
2a41ff81 1968 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 1969
021230d4
AV		 1970 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1971
1972 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1973 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1974 /* Disable indicating checksum in descriptor, enables
1975 * RSS hash */
9a799d71 1976 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1977 }
021230d4
AV		 1978 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1979 /* Enable IPv4 payload checksum for UDP fragments
1980 * if PCSD is not set */
1981 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1982 }
1983
1984 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 1985
1986 if (hw->mac.type == ixgbe_mac_82599EB) {
1987 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1988 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 1989 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 1990 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1991 }
f8212f97
AD		 1992
1993 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED) {
1994 /* Enable 82599 HW-RSC */
1995 for (i = 0; i < adapter->num_rx_queues; i++) {
1996 j = adapter->rx_ring[i].reg_idx;
1997 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
1998 rscctrl |= IXGBE_RSCCTL_RSCEN;
1999 /*
e76678dd
AD		 2000 * we must limit the number of descriptors so that the
2001 * total size of max desc * buf_len is not greater
2002 * than 65535
f8212f97 2003 */
e76678dd
AD		 2004 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2005#if (MAX_SKB_FRAGS > 16)
2006 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2007#elif (MAX_SKB_FRAGS > 8)
f8212f97 2008 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
e76678dd
AD		 2009#elif (MAX_SKB_FRAGS > 4)
2010 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
f8212f97 2011#else
e76678dd 2012 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
f8212f97 2013#endif
e76678dd
AD		 2014 } else {
2015 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2016 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2017 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2018 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2019 else
2020 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2021 }
f8212f97
AD		 2022 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2023 }
2024 /* Disable RSC for ACK packets */
2025 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2026 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2027 }
9a799d71
AK		 2028}
2029
068c89b0
DS		 2030static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2031{
2032 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2033 struct ixgbe_hw *hw = &adapter->hw;
2034
2035 /* add VID to filter table */
2036 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2037}
2038
2039static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2040{
2041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2042 struct ixgbe_hw *hw = &adapter->hw;
2043
2044 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2045 ixgbe_irq_disable(adapter);
2046
2047 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2048
2049 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2050 ixgbe_irq_enable(adapter);
2051
2052 /* remove VID from filter table */
2053 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2054}
2055
9a799d71 2056static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2057 struct vlan_group *grp)
9a799d71
AK		 2058{
2059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2060 u32 ctrl;
e8e26350 2061 int i, j;
9a799d71 2062
d4f80882
AV		 2063 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2064 ixgbe_irq_disable(adapter);
9a799d71
AK		 2065 adapter->vlgrp = grp;
2066
2f90b865
AD		 2067 /*
2068 * For a DCB driver, always enable VLAN tag stripping so we can
2069 * still receive traffic from a DCB-enabled host even if we're
2070 * not in DCB mode.
2071 */
2072 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2073 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2074 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2075 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2076 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2077 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2078 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2079 /* enable VLAN tag insert/strip */
2080 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2081 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2082 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2083 for (i = 0; i < adapter->num_rx_queues; i++) {
2084 j = adapter->rx_ring[i].reg_idx;
2085 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2086 ctrl |= IXGBE_RXDCTL_VME;
2087 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2088 }
9a799d71 2089 }
e8e26350 2090 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2091
d4f80882
AV		 2092 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2093 ixgbe_irq_enable(adapter);
9a799d71
AK		 2094}
2095
9a799d71
AK		 2096static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2097{
2098 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2099
2100 if (adapter->vlgrp) {
2101 u16 vid;
2102 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2103 if (!vlan_group_get_device(adapter->vlgrp, vid))
2104 continue;
2105 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2106 }
2107 }
2108}
2109
2c5645cf
CL		 2110static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2111{
2112 struct dev_mc_list *mc_ptr;
2113 u8 *addr = *mc_addr_ptr;
2114 *vmdq = 0;
2115
2116 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2117 if (mc_ptr->next)
2118 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2119 else
2120 *mc_addr_ptr = NULL;
2121
2122 return addr;
2123}
2124
9a799d71 2125/**
2c5645cf 2126 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2127 * @netdev: network interface device structure
2128 *
2c5645cf
CL		 2129 * The set_rx_method entry point is called whenever the unicast/multicast
2130 * address list or the network interface flags are updated. This routine is
2131 * responsible for configuring the hardware for proper unicast, multicast and
2132 * promiscuous mode.
9a799d71 2133 **/
2c5645cf 2134static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2135{
2136 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2137 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2138 u32 fctrl, vlnctrl;
2c5645cf
CL		 2139 u8 *addr_list = NULL;
2140 int addr_count = 0;
9a799d71
AK		 2141
2142 /* Check for Promiscuous and All Multicast modes */
2143
2144 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2145 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2146
2147 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2148 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2149 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2150 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2151 } else {
746b9f02
PM		 2152 if (netdev->flags & IFF_ALLMULTI) {
2153 fctrl |= IXGBE_FCTRL_MPE;
2154 fctrl &= ~IXGBE_FCTRL_UPE;
2155 } else {
2156 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2157 }
3d01625a 2158 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2159 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2160 }
2161
2162 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2163 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2164
2c5645cf
CL		 2165 /* reprogram secondary unicast list */
2166 addr_count = netdev->uc_count;
2167 if (addr_count)
2168 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 2169 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
2170 ixgbe_addr_list_itr);
9a799d71 2171
2c5645cf
CL		 2172 /* reprogram multicast list */
2173 addr_count = netdev->mc_count;
2174 if (addr_count)
2175 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2176 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2177 ixgbe_addr_list_itr);
9a799d71
AK		 2178}
2179
021230d4
AV		 2180static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2181{
2182 int q_idx;
2183 struct ixgbe_q_vector *q_vector;
2184 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2185
2186 /* legacy and MSI only use one vector */
2187 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2188 q_vectors = 1;
2189
2190 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2191 struct napi_struct *napi;
7a921c93 2192 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2193 if (!q_vector->rxr_count)
2194 continue;
f0848276
JB		 2195 napi = &q_vector->napi;
2196 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
2197 (q_vector->rxr_count > 1))
2198 napi->poll = &ixgbe_clean_rxonly_many;
2199
2200 napi_enable(napi);
021230d4
AV		 2201 }
2202}
2203
2204static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2205{
2206 int q_idx;
2207 struct ixgbe_q_vector *q_vector;
2208 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2209
2210 /* legacy and MSI only use one vector */
2211 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2212 q_vectors = 1;
2213
2214 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2215 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2216 if (!q_vector->rxr_count)
2217 continue;
2218 napi_disable(&q_vector->napi);
2219 }
2220}
2221
7a6b6f51 2222#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2223/*
2224 * ixgbe_configure_dcb - Configure DCB hardware
2225 * @adapter: ixgbe adapter struct
2226 *
2227 * This is called by the driver on open to configure the DCB hardware.
2228 * This is also called by the gennetlink interface when reconfiguring
2229 * the DCB state.
2230 */
2231static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2232{
2233 struct ixgbe_hw *hw = &adapter->hw;
2234 u32 txdctl, vlnctrl;
2235 int i, j;
2236
2237 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2238 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2239 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2240
2241 /* reconfigure the hardware */
2242 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2243
2244 for (i = 0; i < adapter->num_tx_queues; i++) {
2245 j = adapter->tx_ring[i].reg_idx;
2246 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2247 /* PThresh workaround for Tx hang with DFP enabled. */
2248 txdctl |= 32;
2249 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2250 }
2251 /* Enable VLAN tag insert/strip */
2252 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2253 if (hw->mac.type == ixgbe_mac_82598EB) {
2254 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2255 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2256 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2257 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2258 vlnctrl |= IXGBE_VLNCTRL_VFE;
2259 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2260 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2261 for (i = 0; i < adapter->num_rx_queues; i++) {
2262 j = adapter->rx_ring[i].reg_idx;
2263 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2264 vlnctrl |= IXGBE_RXDCTL_VME;
2265 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2266 }
2267 }
2f90b865
AD		 2268 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2269}
2270
2271#endif
9a799d71
AK		 2272static void ixgbe_configure(struct ixgbe_adapter *adapter)
2273{
2274 struct net_device *netdev = adapter->netdev;
2275 int i;
2276
2c5645cf 2277 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2278
2279 ixgbe_restore_vlan(adapter);
7a6b6f51 2280#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2281 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2282 netif_set_gso_max_size(netdev, 32768);
2283 ixgbe_configure_dcb(adapter);
2284 } else {
2285 netif_set_gso_max_size(netdev, 65536);
2286 }
2287#else
2288 netif_set_gso_max_size(netdev, 65536);
2289#endif
9a799d71 2290
eacd73f7
YZ		 2291#ifdef IXGBE_FCOE
2292 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2293 ixgbe_configure_fcoe(adapter);
2294
2295#endif /* IXGBE_FCOE */
9a799d71
AK		 2296 ixgbe_configure_tx(adapter);
2297 ixgbe_configure_rx(adapter);
2298 for (i = 0; i < adapter->num_rx_queues; i++)
2299 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2300 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2301}
2302
e8e26350
PW		 2303static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2304{
2305 switch (hw->phy.type) {
2306 case ixgbe_phy_sfp_avago:
2307 case ixgbe_phy_sfp_ftl:
2308 case ixgbe_phy_sfp_intel:
2309 case ixgbe_phy_sfp_unknown:
2310 case ixgbe_phy_tw_tyco:
2311 case ixgbe_phy_tw_unknown:
2312 return true;
2313 default:
2314 return false;
2315 }
2316}
2317
0ecc061d 2318/**
e8e26350
PW		 2319 * ixgbe_sfp_link_config - set up SFP+ link
2320 * @adapter: pointer to private adapter struct
2321 **/
2322static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2323{
2324 struct ixgbe_hw *hw = &adapter->hw;
2325
2326 if (hw->phy.multispeed_fiber) {
2327 /*
2328 * In multispeed fiber setups, the device may not have
2329 * had a physical connection when the driver loaded.
2330 * If that's the case, the initial link configuration
2331 * couldn't get the MAC into 10G or 1G mode, so we'll
2332 * never have a link status change interrupt fire.
2333 * We need to try and force an autonegotiation
2334 * session, then bring up link.
2335 */
2336 hw->mac.ops.setup_sfp(hw);
2337 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2338 schedule_work(&adapter->multispeed_fiber_task);
2339 } else {
2340 /*
2341 * Direct Attach Cu and non-multispeed fiber modules
2342 * still need to be configured properly prior to
2343 * attempting link.
2344 */
2345 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2346 schedule_work(&adapter->sfp_config_module_task);
2347 }
2348}
2349
2350/**
2351 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2352 * @hw: pointer to private hardware struct
2353 *
2354 * Returns 0 on success, negative on failure
2355 **/
e8e26350 2356static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2357{
2358 u32 autoneg;
2359 bool link_up = false;
2360 u32 ret = IXGBE_ERR_LINK_SETUP;
2361
2362 if (hw->mac.ops.check_link)
2363 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2364
2365 if (ret)
2366 goto link_cfg_out;
2367
2368 if (hw->mac.ops.get_link_capabilities)
2369 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2370 &hw->mac.autoneg);
2371 if (ret)
2372 goto link_cfg_out;
2373
2374 if (hw->mac.ops.setup_link_speed)
2375 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
0ecc061d
PWJ		 2376link_cfg_out:
2377 return ret;
2378}
2379
e8e26350
PW		 2380#define IXGBE_MAX_RX_DESC_POLL 10
2381static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2382 int rxr)
2383{
2384 int j = adapter->rx_ring[rxr].reg_idx;
2385 int k;
2386
2387 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2388 if (IXGBE_READ_REG(&adapter->hw,
2389 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2390 break;
2391 else
2392 msleep(1);
2393 }
2394 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2395 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2396 "not set within the polling period\n", rxr);
2397 }
2398 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2399 (adapter->rx_ring[rxr].count - 1));
2400}
2401
9a799d71
AK		 2402static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2403{
2404 struct net_device *netdev = adapter->netdev;
9a799d71 2405 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2406 int i, j = 0;
e8e26350 2407 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2408 int err;
9a799d71 2409 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2410 u32 txdctl, rxdctl, mhadd;
e8e26350 2411 u32 dmatxctl;
021230d4 2412 u32 gpie;
9a799d71 2413
5eba3699
AV		 2414 ixgbe_get_hw_control(adapter);
2415
021230d4
AV		 2416 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2417 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2418 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2419 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2420 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2421 } else {
2422 /* MSI only */
021230d4 2423 gpie = 0;
9a799d71 2424 }
021230d4
AV		 2425 /* XXX: to interrupt immediately for EICS writes, enable this */
2426 /* gpie |= IXGBE_GPIE_EIMEN; */
2427 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2428 }
2429
021230d4
AV		 2430 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2431 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2432 * specifically only auto mask tx and rx interrupts */
2433 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2434 }
9a799d71 2435
0befdb3e
JB		 2436 /* Enable fan failure interrupt if media type is copper */
2437 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2438 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2439 gpie |= IXGBE_SDP1_GPIEN;
2440 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2441 }
2442
e8e26350
PW		 2443 if (hw->mac.type == ixgbe_mac_82599EB) {
2444 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2445 gpie |= IXGBE_SDP1_GPIEN;
2446 gpie |= IXGBE_SDP2_GPIEN;
2447 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2448 }
2449
63f39bd1
YZ		 2450#ifdef IXGBE_FCOE
2451 /* adjust max frame to be able to do baby jumbo for FCoE */
2452 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2453 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2454 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2455
2456#endif /* IXGBE_FCOE */
021230d4 2457 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2458 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2459 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2460 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2461
2462 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2463 }
2464
2465 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2466 j = adapter->tx_ring[i].reg_idx;
2467 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2468 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2469 txdctl |= (8 << 16);
e8e26350
PW		 2470 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2471 }
2472
2473 if (hw->mac.type == ixgbe_mac_82599EB) {
2474 /* DMATXCTL.EN must be set after all Tx queue config is done */
2475 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2476 dmatxctl |= IXGBE_DMATXCTL_TE;
2477 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2478 }
2479 for (i = 0; i < adapter->num_tx_queues; i++) {
2480 j = adapter->tx_ring[i].reg_idx;
2481 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2482 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2483 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2484 }
2485
e8e26350 2486 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2487 j = adapter->rx_ring[i].reg_idx;
2488 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2489 /* enable PTHRESH=32 descriptors (half the internal cache)
2490 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2491 * this also removes a pesky rx_no_buffer_count increment */
2492 rxdctl |= 0x0020;
9a799d71 2493 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2494 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2495 if (hw->mac.type == ixgbe_mac_82599EB)
2496 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2497 }
2498 /* enable all receives */
2499 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2500 if (hw->mac.type == ixgbe_mac_82598EB)
2501 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2502 else
2503 rxdctl |= IXGBE_RXCTRL_RXEN;
2504 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2505
2506 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2507 ixgbe_configure_msix(adapter);
2508 else
2509 ixgbe_configure_msi_and_legacy(adapter);
2510
2511 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2512 ixgbe_napi_enable_all(adapter);
2513
2514 /* clear any pending interrupts, may auto mask */
2515 IXGBE_READ_REG(hw, IXGBE_EICR);
2516
9a799d71
AK		 2517 ixgbe_irq_enable(adapter);
2518
bf069c97
DS		 2519 /*
2520 * If this adapter has a fan, check to see if we had a failure
2521 * before we enabled the interrupt.
2522 */
2523 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2524 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2525 if (esdp & IXGBE_ESDP_SDP1)
2526 DPRINTK(DRV, CRIT,
2527 "Fan has stopped, replace the adapter\n");
2528 }
2529
e8e26350
PW		 2530 /*
2531 * For hot-pluggable SFP+ devices, a new SFP+ module may have
2532 * arrived before interrupts were enabled. We need to kick off
2533 * the SFP+ module setup first, then try to bring up link.
2534 * If we're not hot-pluggable SFP+, we just need to configure link
2535 * and bring it up.
2536 */
2537 err = hw->phy.ops.identify(hw);
2538 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2539 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
2540 ixgbe_down(adapter);
2541 return err;
2542 }
2543
2544 if (ixgbe_is_sfp(hw)) {
2545 ixgbe_sfp_link_config(adapter);
2546 } else {
2547 err = ixgbe_non_sfp_link_config(hw);
2548 if (err)
2549 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2550 }
0ecc061d 2551
1da100bb
PWJ		 2552 /* enable transmits */
2553 netif_tx_start_all_queues(netdev);
2554
9a799d71
AK		 2555 /* bring the link up in the watchdog, this could race with our first
2556 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2557 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2558 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2559 mod_timer(&adapter->watchdog_timer, jiffies);
2560 return 0;
2561}
2562
d4f80882
AV		 2563void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2564{
2565 WARN_ON(in_interrupt());
2566 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2567 msleep(1);
2568 ixgbe_down(adapter);
2569 ixgbe_up(adapter);
2570 clear_bit(__IXGBE_RESETTING, &adapter->state);
2571}
2572
9a799d71
AK		 2573int ixgbe_up(struct ixgbe_adapter *adapter)
2574{
2575 /* hardware has been reset, we need to reload some things */
2576 ixgbe_configure(adapter);
2577
2578 return ixgbe_up_complete(adapter);
2579}
2580
2581void ixgbe_reset(struct ixgbe_adapter *adapter)
2582{
c44ade9e
JB		 2583 struct ixgbe_hw *hw = &adapter->hw;
2584 if (hw->mac.ops.init_hw(hw))
2585 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2586
2587 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2588 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2589
2590}
2591
9a799d71
AK		 2592/**
2593 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2594 * @adapter: board private structure
2595 * @rx_ring: ring to free buffers from
2596 **/
2597static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2598 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2599{
2600 struct pci_dev *pdev = adapter->pdev;
2601 unsigned long size;
2602 unsigned int i;
2603
2604 /* Free all the Rx ring sk_buffs */
2605
2606 for (i = 0; i < rx_ring->count; i++) {
2607 struct ixgbe_rx_buffer *rx_buffer_info;
2608
2609 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2610 if (rx_buffer_info->dma) {
2611 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2612 rx_ring->rx_buf_len,
2613 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2614 rx_buffer_info->dma = 0;
2615 }
2616 if (rx_buffer_info->skb) {
f8212f97 2617 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2618 rx_buffer_info->skb = NULL;
f8212f97
AD		 2619 do {
2620 struct sk_buff *this = skb;
2621 skb = skb->prev;
2622 dev_kfree_skb(this);
2623 } while (skb);
9a799d71
AK		 2624 }
2625 if (!rx_buffer_info->page)
2626 continue;
762f4c57
JB		 2627 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2628 PCI_DMA_FROMDEVICE);
9a799d71 2629 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2630 put_page(rx_buffer_info->page);
2631 rx_buffer_info->page = NULL;
762f4c57 2632 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2633 }
2634
2635 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2636 memset(rx_ring->rx_buffer_info, 0, size);
2637
2638 /* Zero out the descriptor ring */
2639 memset(rx_ring->desc, 0, rx_ring->size);
2640
2641 rx_ring->next_to_clean = 0;
2642 rx_ring->next_to_use = 0;
2643
9891ca7c
JB		 2644 if (rx_ring->head)
2645 writel(0, adapter->hw.hw_addr + rx_ring->head);
2646 if (rx_ring->tail)
2647 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2648}
2649
2650/**
2651 * ixgbe_clean_tx_ring - Free Tx Buffers
2652 * @adapter: board private structure
2653 * @tx_ring: ring to be cleaned
2654 **/
2655static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2656 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2657{
2658 struct ixgbe_tx_buffer *tx_buffer_info;
2659 unsigned long size;
2660 unsigned int i;
2661
2662 /* Free all the Tx ring sk_buffs */
2663
2664 for (i = 0; i < tx_ring->count; i++) {
2665 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2666 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2667 }
2668
2669 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2670 memset(tx_ring->tx_buffer_info, 0, size);
2671
2672 /* Zero out the descriptor ring */
2673 memset(tx_ring->desc, 0, tx_ring->size);
2674
2675 tx_ring->next_to_use = 0;
2676 tx_ring->next_to_clean = 0;
2677
9891ca7c
JB		 2678 if (tx_ring->head)
2679 writel(0, adapter->hw.hw_addr + tx_ring->head);
2680 if (tx_ring->tail)
2681 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2682}
2683
2684/**
021230d4 2685 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2686 * @adapter: board private structure
2687 **/
021230d4 2688static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2689{
2690 int i;
2691
021230d4
AV		 2692 for (i = 0; i < adapter->num_rx_queues; i++)
2693 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2694}
2695
2696/**
021230d4 2697 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2698 * @adapter: board private structure
2699 **/
021230d4 2700static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2701{
2702 int i;
2703
021230d4
AV		 2704 for (i = 0; i < adapter->num_tx_queues; i++)
2705 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2706}
2707
2708void ixgbe_down(struct ixgbe_adapter *adapter)
2709{
2710 struct net_device *netdev = adapter->netdev;
7f821875 2711 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2712 u32 rxctrl;
7f821875
JB		 2713 u32 txdctl;
2714 int i, j;
9a799d71
AK		 2715
2716 /* signal that we are down to the interrupt handler */
2717 set_bit(__IXGBE_DOWN, &adapter->state);
2718
2719 /* disable receives */
7f821875
JB		 2720 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2721 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2722
2723 netif_tx_disable(netdev);
2724
7f821875 2725 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2726 msleep(10);
2727
7f821875
JB		 2728 netif_tx_stop_all_queues(netdev);
2729
9a799d71
AK		 2730 ixgbe_irq_disable(adapter);
2731
021230d4 2732 ixgbe_napi_disable_all(adapter);
7f821875 2733
9a799d71 2734 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2735 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2736
7f821875
JB		 2737 /* disable transmits in the hardware now that interrupts are off */
2738 for (i = 0; i < adapter->num_tx_queues; i++) {
2739 j = adapter->tx_ring[i].reg_idx;
2740 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2741 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2742 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2743 }
88512539
PW		 2744 /* Disable the Tx DMA engine on 82599 */
2745 if (hw->mac.type == ixgbe_mac_82599EB)
2746 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2747 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2748 ~IXGBE_DMATXCTL_TE));
7f821875 2749
9a799d71 2750 netif_carrier_off(netdev);
9a799d71 2751
5dd2d332 2752#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2753 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2754 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2755 dca_remove_requester(&adapter->pdev->dev);
2756 }
2757
2758#endif
6f4a0e45
PL		 2759 if (!pci_channel_offline(adapter->pdev))
2760 ixgbe_reset(adapter);
9a799d71
AK		 2761 ixgbe_clean_all_tx_rings(adapter);
2762 ixgbe_clean_all_rx_rings(adapter);
2763
5dd2d332 2764#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2765 /* since we reset the hardware DCA settings were cleared */
2766 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2767 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2768 /* always use CB2 mode, difference is masked
2769 * in the CB driver */
b4617240 2770 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2771 ixgbe_setup_dca(adapter);
2772 }
2773#endif
9a799d71
AK		 2774}
2775
9a799d71 2776/**
021230d4
AV		 2777 * ixgbe_poll - NAPI Rx polling callback
2778 * @napi: structure for representing this polling device
2779 * @budget: how many packets driver is allowed to clean
2780 *
2781 * This function is used for legacy and MSI, NAPI mode
9a799d71 2782 **/
021230d4 2783static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2784{
9a1a69ad
JB		 2785 struct ixgbe_q_vector *q_vector =
2786 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2787 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 2788 int tx_clean_complete, work_done = 0;
9a799d71 2789
5dd2d332 2790#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2791 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2792 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2793 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2794 }
2795#endif
2796
9a1a69ad 2797 tx_clean_complete = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
78b6f4ce 2798 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 2799
9a1a69ad 2800 if (!tx_clean_complete)
d2c7ddd6
DM		 2801 work_done = budget;
2802
53e52c72
DM		 2803 /* If budget not fully consumed, exit the polling mode */
2804 if (work_done < budget) {
288379f0 2805 napi_complete(napi);
509ee935 2806 if (adapter->itr_setting & 1)
f494e8fa 2807 ixgbe_set_itr(adapter);
d4f80882 2808 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 2809 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 2810 }
9a799d71
AK		 2811 return work_done;
2812}
2813
2814/**
2815 * ixgbe_tx_timeout - Respond to a Tx Hang
2816 * @netdev: network interface device structure
2817 **/
2818static void ixgbe_tx_timeout(struct net_device *netdev)
2819{
2820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2821
2822 /* Do the reset outside of interrupt context */
2823 schedule_work(&adapter->reset_task);
2824}
2825
2826static void ixgbe_reset_task(struct work_struct *work)
2827{
2828 struct ixgbe_adapter *adapter;
2829 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2830
2f90b865
AD		 2831 /* If we're already down or resetting, just bail */
2832 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2833 test_bit(__IXGBE_RESETTING, &adapter->state))
2834 return;
2835
9a799d71
AK		 2836 adapter->tx_timeout_count++;
2837
d4f80882 2838 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2839}
2840
bc97114d
PWJ		 2841#ifdef CONFIG_IXGBE_DCB
2842static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 2843{
bc97114d 2844 bool ret = false;
b9804972 2845
bc97114d
PWJ		 2846 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2847 adapter->ring_feature[RING_F_DCB].mask = 0x7 << 3;
2848 adapter->num_rx_queues =
2849 adapter->ring_feature[RING_F_DCB].indices;
2850 adapter->num_tx_queues =
2851 adapter->ring_feature[RING_F_DCB].indices;
2852 ret = true;
2853 } else {
bc97114d
PWJ		 2854 ret = false;
2855 }
2f90b865 2856
bc97114d
PWJ		 2857 return ret;
2858}
2859#endif
2860
4df10466
JB		 2861/**
2862 * ixgbe_set_rss_queues: Allocate queues for RSS
2863 * @adapter: board private structure to initialize
2864 *
2865 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
2866 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
2867 *
2868 **/
bc97114d
PWJ		 2869static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
2870{
2871 bool ret = false;
2872
2873 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2874 adapter->ring_feature[RING_F_RSS].mask = 0xF;
2875 adapter->num_rx_queues =
2876 adapter->ring_feature[RING_F_RSS].indices;
2877 adapter->num_tx_queues =
2878 adapter->ring_feature[RING_F_RSS].indices;
2879 ret = true;
2880 } else {
bc97114d 2881 ret = false;
b9804972
JB		 2882 }
2883
bc97114d
PWJ		 2884 return ret;
2885}
2886
0331a832
YZ		 2887#ifdef IXGBE_FCOE
2888/**
2889 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
2890 * @adapter: board private structure to initialize
2891 *
2892 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
2893 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
2894 * rx queues out of the max number of rx queues, instead, it is used as the
2895 * index of the first rx queue used by FCoE.
2896 *
2897 **/
2898static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
2899{
2900 bool ret = false;
2901 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
2902
2903 f->indices = min((int)num_online_cpus(), f->indices);
2904 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2905#ifdef CONFIG_IXGBE_DCB
2906 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2907 DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
2908 ixgbe_set_dcb_queues(adapter);
2909 }
2910#endif
2911 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2912 DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
2913 ixgbe_set_rss_queues(adapter);
2914 }
2915 /* adding FCoE rx rings to the end */
2916 f->mask = adapter->num_rx_queues;
2917 adapter->num_rx_queues += f->indices;
2918 if (adapter->num_tx_queues == 0)
2919 adapter->num_tx_queues = f->indices;
2920
2921 ret = true;
2922 }
2923
2924 return ret;
2925}
2926
2927#endif /* IXGBE_FCOE */
4df10466
JB		 2928/*
2929 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
2930 * @adapter: board private structure to initialize
2931 *
2932 * This is the top level queue allocation routine. The order here is very
2933 * important, starting with the "most" number of features turned on at once,
2934 * and ending with the smallest set of features. This way large combinations
2935 * can be allocated if they're turned on, and smaller combinations are the
2936 * fallthrough conditions.
2937 *
2938 **/
bc97114d
PWJ		 2939static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2940{
0331a832
YZ		 2941#ifdef IXGBE_FCOE
2942 if (ixgbe_set_fcoe_queues(adapter))
2943 goto done;
2944
2945#endif /* IXGBE_FCOE */
bc97114d
PWJ		 2946#ifdef CONFIG_IXGBE_DCB
2947 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 2948 goto done;
bc97114d
PWJ		 2949
2950#endif
2951 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 2952 goto done;
2953
2954 /* fallback to base case */
2955 adapter->num_rx_queues = 1;
2956 adapter->num_tx_queues = 1;
2957
2958done:
2959 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2960 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 2961}
2962
021230d4 2963static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2964 int vectors)
021230d4
AV		 2965{
2966 int err, vector_threshold;
2967
2968 /* We'll want at least 3 (vector_threshold):
2969 * 1) TxQ[0] Cleanup
2970 * 2) RxQ[0] Cleanup
2971 * 3) Other (Link Status Change, etc.)
2972 * 4) TCP Timer (optional)
2973 */
2974 vector_threshold = MIN_MSIX_COUNT;
2975
2976 /* The more we get, the more we will assign to Tx/Rx Cleanup
2977 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2978 * Right now, we simply care about how many we'll get; we'll
2979 * set them up later while requesting irq's.
2980 */
2981 while (vectors >= vector_threshold) {
2982 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2983 vectors);
021230d4
AV		 2984 if (!err) /* Success in acquiring all requested vectors. */
2985 break;
2986 else if (err < 0)
2987 vectors = 0; /* Nasty failure, quit now */
2988 else /* err == number of vectors we should try again with */
2989 vectors = err;
2990 }
2991
2992 if (vectors < vector_threshold) {
2993 /* Can't allocate enough MSI-X interrupts? Oh well.
2994 * This just means we'll go with either a single MSI
2995 * vector or fall back to legacy interrupts.
2996 */
2997 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2998 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2999 kfree(adapter->msix_entries);
3000 adapter->msix_entries = NULL;
021230d4
AV		 3001 } else {
3002 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3003 /*
3004 * Adjust for only the vectors we'll use, which is minimum
3005 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3006 * vectors we were allocated.
3007 */
3008 adapter->num_msix_vectors = min(vectors,
3009 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3010 }
3011}
3012
021230d4 3013/**
bc97114d 3014 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3015 * @adapter: board private structure to initialize
3016 *
bc97114d
PWJ		 3017 * Cache the descriptor ring offsets for RSS to the assigned rings.
3018 *
021230d4 3019 **/
bc97114d 3020static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3021{
bc97114d
PWJ		 3022 int i;
3023 bool ret = false;
3024
3025 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3026 for (i = 0; i < adapter->num_rx_queues; i++)
3027 adapter->rx_ring[i].reg_idx = i;
3028 for (i = 0; i < adapter->num_tx_queues; i++)
3029 adapter->tx_ring[i].reg_idx = i;
3030 ret = true;
3031 } else {
3032 ret = false;
3033 }
3034
3035 return ret;
3036}
3037
3038#ifdef CONFIG_IXGBE_DCB
3039/**
3040 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3041 * @adapter: board private structure to initialize
3042 *
3043 * Cache the descriptor ring offsets for DCB to the assigned rings.
3044 *
3045 **/
3046static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3047{
3048 int i;
3049 bool ret = false;
3050 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3051
3052 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3053 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3054 /* the number of queues is assumed to be symmetric */
3055 for (i = 0; i < dcb_i; i++) {
3056 adapter->rx_ring[i].reg_idx = i << 3;
3057 adapter->tx_ring[i].reg_idx = i << 2;
3058 }
bc97114d 3059 ret = true;
e8e26350 3060 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3061 if (dcb_i == 8) {
3062 /*
3063 * Tx TC0 starts at: descriptor queue 0
3064 * Tx TC1 starts at: descriptor queue 32
3065 * Tx TC2 starts at: descriptor queue 64
3066 * Tx TC3 starts at: descriptor queue 80
3067 * Tx TC4 starts at: descriptor queue 96
3068 * Tx TC5 starts at: descriptor queue 104
3069 * Tx TC6 starts at: descriptor queue 112
3070 * Tx TC7 starts at: descriptor queue 120
3071 *
3072 * Rx TC0-TC7 are offset by 16 queues each
3073 */
3074 for (i = 0; i < 3; i++) {
3075 adapter->tx_ring[i].reg_idx = i << 5;
3076 adapter->rx_ring[i].reg_idx = i << 4;
3077 }
3078 for ( ; i < 5; i++) {
3079 adapter->tx_ring[i].reg_idx =
3080 ((i + 2) << 4);
3081 adapter->rx_ring[i].reg_idx = i << 4;
3082 }
3083 for ( ; i < dcb_i; i++) {
3084 adapter->tx_ring[i].reg_idx =
3085 ((i + 8) << 3);
3086 adapter->rx_ring[i].reg_idx = i << 4;
3087 }
3088
3089 ret = true;
3090 } else if (dcb_i == 4) {
3091 /*
3092 * Tx TC0 starts at: descriptor queue 0
3093 * Tx TC1 starts at: descriptor queue 64
3094 * Tx TC2 starts at: descriptor queue 96
3095 * Tx TC3 starts at: descriptor queue 112
3096 *
3097 * Rx TC0-TC3 are offset by 32 queues each
3098 */
3099 adapter->tx_ring[0].reg_idx = 0;
3100 adapter->tx_ring[1].reg_idx = 64;
3101 adapter->tx_ring[2].reg_idx = 96;
3102 adapter->tx_ring[3].reg_idx = 112;
3103 for (i = 0 ; i < dcb_i; i++)
3104 adapter->rx_ring[i].reg_idx = i << 5;
3105
3106 ret = true;
3107 } else {
3108 ret = false;
e8e26350 3109 }
bc97114d
PWJ		 3110 } else {
3111 ret = false;
021230d4 3112 }
bc97114d
PWJ		 3113 } else {
3114 ret = false;
021230d4 3115 }
bc97114d
PWJ		 3116
3117 return ret;
3118}
3119#endif
3120
0331a832
YZ		 3121#ifdef IXGBE_FCOE
3122/**
3123 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3124 * @adapter: board private structure to initialize
3125 *
3126 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3127 *
3128 */
3129static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3130{
3131 int i, fcoe_i = 0;
3132 bool ret = false;
3133 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3134
3135 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3136#ifdef CONFIG_IXGBE_DCB
3137 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3138 ixgbe_cache_ring_dcb(adapter);
3139 fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3140 }
3141#endif /* CONFIG_IXGBE_DCB */
3142 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3143 ixgbe_cache_ring_rss(adapter);
3144 fcoe_i = f->mask;
3145 }
3146 for (i = 0; i < f->indices; i++, fcoe_i++)
3147 adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3148 ret = true;
3149 }
3150 return ret;
3151}
3152
3153#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3154/**
3155 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3156 * @adapter: board private structure to initialize
3157 *
3158 * Once we know the feature-set enabled for the device, we'll cache
3159 * the register offset the descriptor ring is assigned to.
3160 *
3161 * Note, the order the various feature calls is important. It must start with
3162 * the "most" features enabled at the same time, then trickle down to the
3163 * least amount of features turned on at once.
3164 **/
3165static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3166{
3167 /* start with default case */
3168 adapter->rx_ring[0].reg_idx = 0;
3169 adapter->tx_ring[0].reg_idx = 0;
3170
0331a832
YZ		 3171#ifdef IXGBE_FCOE
3172 if (ixgbe_cache_ring_fcoe(adapter))
3173 return;
3174
3175#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3176#ifdef CONFIG_IXGBE_DCB
3177 if (ixgbe_cache_ring_dcb(adapter))
3178 return;
3179
3180#endif
3181 if (ixgbe_cache_ring_rss(adapter))
3182 return;
021230d4
AV		 3183}
3184
9a799d71
AK		 3185/**
3186 * ixgbe_alloc_queues - Allocate memory for all rings
3187 * @adapter: board private structure to initialize
3188 *
3189 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3190 * number of queues at compile-time. The polling_netdev array is
3191 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3192 **/
2f90b865 3193static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3194{
3195 int i;
3196
3197 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3198 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3199 if (!adapter->tx_ring)
021230d4 3200 goto err_tx_ring_allocation;
9a799d71
AK		 3201
3202 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3203 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3204 if (!adapter->rx_ring)
3205 goto err_rx_ring_allocation;
9a799d71 3206
021230d4 3207 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3208 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3209 adapter->tx_ring[i].queue_index = i;
3210 }
b9804972 3211
9a799d71 3212 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3213 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3214 adapter->rx_ring[i].queue_index = i;
3215 }
3216
3217 ixgbe_cache_ring_register(adapter);
3218
3219 return 0;
3220
3221err_rx_ring_allocation:
3222 kfree(adapter->tx_ring);
3223err_tx_ring_allocation:
3224 return -ENOMEM;
3225}
3226
3227/**
3228 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3229 * @adapter: board private structure to initialize
3230 *
3231 * Attempt to configure the interrupts using the best available
3232 * capabilities of the hardware and the kernel.
3233 **/
feea6a57 3234static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3235{
8be0e467 3236 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3237 int err = 0;
3238 int vector, v_budget;
3239
3240 /*
3241 * It's easy to be greedy for MSI-X vectors, but it really
3242 * doesn't do us much good if we have a lot more vectors
3243 * than CPU's. So let's be conservative and only ask for
3244 * (roughly) twice the number of vectors as there are CPU's.
3245 */
3246 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3247 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3248
3249 /*
3250 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3251 * hw.mac->max_msix_vectors vectors. With features
3252 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3253 * descriptor queues supported by our device. Thus, we cap it off in
3254 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3255 */
8be0e467 3256 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3257
3258 /* A failure in MSI-X entry allocation isn't fatal, but it does
3259 * mean we disable MSI-X capabilities of the adapter. */
3260 adapter->msix_entries = kcalloc(v_budget,
b4617240 3261 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3262 if (adapter->msix_entries) {
3263 for (vector = 0; vector < v_budget; vector++)
3264 adapter->msix_entries[vector].entry = vector;
021230d4 3265
7a921c93 3266 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3267
7a921c93
AD		 3268 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3269 goto out;
3270 }
021230d4 3271
7a921c93
AD		 3272 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3273 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3274 ixgbe_set_num_queues(adapter);
021230d4 3275
021230d4
AV		 3276 err = pci_enable_msi(adapter->pdev);
3277 if (!err) {
3278 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3279 } else {
3280 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3281 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3282 /* reset err */
3283 err = 0;
3284 }
3285
3286out:
021230d4
AV		 3287 return err;
3288}
3289
7a921c93
AD		 3290/**
3291 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3292 * @adapter: board private structure to initialize
3293 *
3294 * We allocate one q_vector per queue interrupt. If allocation fails we
3295 * return -ENOMEM.
3296 **/
3297static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3298{
3299 int q_idx, num_q_vectors;
3300 struct ixgbe_q_vector *q_vector;
3301 int napi_vectors;
3302 int (*poll)(struct napi_struct *, int);
3303
3304 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3305 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3306 napi_vectors = adapter->num_rx_queues;
3307 poll = &ixgbe_clean_rxonly;
3308 } else {
3309 num_q_vectors = 1;
3310 napi_vectors = 1;
3311 poll = &ixgbe_poll;
3312 }
3313
3314 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3315 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3316 if (!q_vector)
3317 goto err_out;
3318 q_vector->adapter = adapter;
3319 q_vector->v_idx = q_idx;
3320 q_vector->eitr = adapter->eitr_param;
3321 if (q_idx < napi_vectors)
3322 netif_napi_add(adapter->netdev, &q_vector->napi,
3323 (*poll), 64);
3324 adapter->q_vector[q_idx] = q_vector;
3325 }
3326
3327 return 0;
3328
3329err_out:
3330 while (q_idx) {
3331 q_idx--;
3332 q_vector = adapter->q_vector[q_idx];
3333 netif_napi_del(&q_vector->napi);
3334 kfree(q_vector);
3335 adapter->q_vector[q_idx] = NULL;
3336 }
3337 return -ENOMEM;
3338}
3339
3340/**
3341 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3342 * @adapter: board private structure to initialize
3343 *
3344 * This function frees the memory allocated to the q_vectors. In addition if
3345 * NAPI is enabled it will delete any references to the NAPI struct prior
3346 * to freeing the q_vector.
3347 **/
3348static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3349{
3350 int q_idx, num_q_vectors;
3351 int napi_vectors;
3352
3353 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3354 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3355 napi_vectors = adapter->num_rx_queues;
3356 } else {
3357 num_q_vectors = 1;
3358 napi_vectors = 1;
3359 }
3360
3361 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3362 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3363
3364 adapter->q_vector[q_idx] = NULL;
3365 if (q_idx < napi_vectors)
3366 netif_napi_del(&q_vector->napi);
3367 kfree(q_vector);
3368 }
3369}
3370
2f90b865 3371void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3372{
3373 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3374 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3375 pci_disable_msix(adapter->pdev);
3376 kfree(adapter->msix_entries);
3377 adapter->msix_entries = NULL;
3378 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3379 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3380 pci_disable_msi(adapter->pdev);
3381 }
3382 return;
3383}
3384
3385/**
3386 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3387 * @adapter: board private structure to initialize
3388 *
3389 * We determine which interrupt scheme to use based on...
3390 * - Kernel support (MSI, MSI-X)
3391 * - which can be user-defined (via MODULE_PARAM)
3392 * - Hardware queue count (num_*_queues)
3393 * - defined by miscellaneous hardware support/features (RSS, etc.)
3394 **/
2f90b865 3395int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3396{
3397 int err;
3398
3399 /* Number of supported queues */
3400 ixgbe_set_num_queues(adapter);
3401
021230d4
AV		 3402 err = ixgbe_set_interrupt_capability(adapter);
3403 if (err) {
3404 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3405 goto err_set_interrupt;
9a799d71
AK		 3406 }
3407
7a921c93
AD		 3408 err = ixgbe_alloc_q_vectors(adapter);
3409 if (err) {
3410 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3411 "vectors\n");
3412 goto err_alloc_q_vectors;
3413 }
3414
3415 err = ixgbe_alloc_queues(adapter);
3416 if (err) {
3417 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3418 goto err_alloc_queues;
3419 }
3420
021230d4 3421 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3422 "Tx Queue count = %u\n",
3423 (adapter->num_rx_queues > 1) ? "Enabled" :
3424 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3425
3426 set_bit(__IXGBE_DOWN, &adapter->state);
3427
9a799d71 3428 return 0;
021230d4 3429
7a921c93
AD		 3430err_alloc_queues:
3431 ixgbe_free_q_vectors(adapter);
3432err_alloc_q_vectors:
3433 ixgbe_reset_interrupt_capability(adapter);
021230d4 3434err_set_interrupt:
7a921c93
AD		 3435 return err;
3436}
3437
3438/**
3439 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3440 * @adapter: board private structure to clear interrupt scheme on
3441 *
3442 * We go through and clear interrupt specific resources and reset the structure
3443 * to pre-load conditions
3444 **/
3445void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3446{
021230d4
AV		 3447 kfree(adapter->tx_ring);
3448 kfree(adapter->rx_ring);
7a921c93
AD		 3449 adapter->tx_ring = NULL;
3450 adapter->rx_ring = NULL;
3451
3452 ixgbe_free_q_vectors(adapter);
3453 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3454}
3455
c4900be0
DS		 3456/**
3457 * ixgbe_sfp_timer - worker thread to find a missing module
3458 * @data: pointer to our adapter struct
3459 **/
3460static void ixgbe_sfp_timer(unsigned long data)
3461{
3462 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3463
4df10466
JB		 3464 /*
3465 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3466 * delays that sfp+ detection requires
3467 */
3468 schedule_work(&adapter->sfp_task);
3469}
3470
3471/**
3472 * ixgbe_sfp_task - worker thread to find a missing module
3473 * @work: pointer to work_struct containing our data
3474 **/
3475static void ixgbe_sfp_task(struct work_struct *work)
3476{
3477 struct ixgbe_adapter *adapter = container_of(work,
3478 struct ixgbe_adapter,
3479 sfp_task);
3480 struct ixgbe_hw *hw = &adapter->hw;
3481
3482 if ((hw->phy.type == ixgbe_phy_nl) &&
3483 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3484 s32 ret = hw->phy.ops.identify_sfp(hw);
3485 if (ret)
3486 goto reschedule;
3487 ret = hw->phy.ops.reset(hw);
3488 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3489 DPRINTK(PROBE, ERR, "failed to initialize because an "
3490 "unsupported SFP+ module type was detected.\n"
3491 "Reload the driver after installing a "
3492 "supported module.\n");
3493 unregister_netdev(adapter->netdev);
3494 } else {
3495 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3496 hw->phy.sfp_type);
3497 }
3498 /* don't need this routine any more */
3499 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3500 }
3501 return;
3502reschedule:
3503 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3504 mod_timer(&adapter->sfp_timer,
3505 round_jiffies(jiffies + (2 * HZ)));
3506}
3507
9a799d71
AK		 3508/**
3509 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3510 * @adapter: board private structure to initialize
3511 *
3512 * ixgbe_sw_init initializes the Adapter private data structure.
3513 * Fields are initialized based on PCI device information and
3514 * OS network device settings (MTU size).
3515 **/
3516static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3517{
3518 struct ixgbe_hw *hw = &adapter->hw;
3519 struct pci_dev *pdev = adapter->pdev;
021230d4 3520 unsigned int rss;
7a6b6f51 3521#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3522 int j;
3523 struct tc_configuration *tc;
3524#endif
021230d4 3525
c44ade9e
JB		 3526 /* PCI config space info */
3527
3528 hw->vendor_id = pdev->vendor;
3529 hw->device_id = pdev->device;
3530 hw->revision_id = pdev->revision;
3531 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3532 hw->subsystem_device_id = pdev->subsystem_device;
3533
021230d4
AV		 3534 /* Set capability flags */
3535 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3536 adapter->ring_feature[RING_F_RSS].indices = rss;
3537 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3538 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3539 if (hw->mac.type == ixgbe_mac_82598EB) {
3540 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3541 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3542 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3543 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3544 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
f8212f97
AD		 3545 adapter->flags |= IXGBE_FLAG_RSC_CAPABLE;
3546 adapter->flags |= IXGBE_FLAG_RSC_ENABLED;
eacd73f7
YZ		 3547#ifdef IXGBE_FCOE
3548 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
0331a832 3549 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
eacd73f7 3550#endif /* IXGBE_FCOE */
f8212f97 3551 }
2f90b865 3552
7a6b6f51 3553#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3554 /* Configure DCB traffic classes */
3555 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3556 tc = &adapter->dcb_cfg.tc_config[j];
3557 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3558 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3559 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3560 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3561 tc->dcb_pfc = pfc_disabled;
3562 }
3563 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3564 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3565 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3566 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3567 adapter->dcb_cfg.round_robin_enable = false;
3568 adapter->dcb_set_bitmap = 0x00;
3569 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3570 adapter->ring_feature[RING_F_DCB].indices);
3571
3572#endif
9a799d71
AK		 3573
3574 /* default flow control settings */
cd7664f6 3575 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3576 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3577#ifdef CONFIG_DCB
3578 adapter->last_lfc_mode = hw->fc.current_mode;
3579#endif
2b9ade93
JB		 3580 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3581 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3582 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3583 hw->fc.send_xon = true;
71fd570b 3584 hw->fc.disable_fc_autoneg = false;
9a799d71 3585
30efa5a3
JB		 3586 /* enable itr by default in dynamic mode */
3587 adapter->itr_setting = 1;
3588 adapter->eitr_param = 20000;
3589
3590 /* set defaults for eitr in MegaBytes */
3591 adapter->eitr_low = 10;
3592 adapter->eitr_high = 20;
3593
3594 /* set default ring sizes */
3595 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3596 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3597
9a799d71 3598 /* initialize eeprom parameters */
c44ade9e 3599 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3600 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3601 return -EIO;
3602 }
3603
021230d4 3604 /* enable rx csum by default */
9a799d71
AK		 3605 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3606
9a799d71
AK		 3607 set_bit(__IXGBE_DOWN, &adapter->state);
3608
3609 return 0;
3610}
3611
3612/**
3613 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3614 * @adapter: board private structure
3a581073 3615 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3616 *
3617 * Return 0 on success, negative on failure
3618 **/
3619int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3620 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3621{
3622 struct pci_dev *pdev = adapter->pdev;
3623 int size;
3624
3a581073
JB		 3625 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3626 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3627 if (!tx_ring->tx_buffer_info)
3628 goto err;
3a581073 3629 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3630
3631 /* round up to nearest 4K */
12207e49 3632 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3633 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3634
3a581073
JB		 3635 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3636 &tx_ring->dma);
e01c31a5
JB		 3637 if (!tx_ring->desc)
3638 goto err;
9a799d71 3639
3a581073
JB		 3640 tx_ring->next_to_use = 0;
3641 tx_ring->next_to_clean = 0;
3642 tx_ring->work_limit = tx_ring->count;
9a799d71 3643 return 0;
e01c31a5
JB		 3644
3645err:
3646 vfree(tx_ring->tx_buffer_info);
3647 tx_ring->tx_buffer_info = NULL;
3648 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3649 "descriptor ring\n");
3650 return -ENOMEM;
9a799d71
AK		 3651}
3652
69888674
AD		 3653/**
3654 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3655 * @adapter: board private structure
3656 *
3657 * If this function returns with an error, then it's possible one or
3658 * more of the rings is populated (while the rest are not). It is the
3659 * callers duty to clean those orphaned rings.
3660 *
3661 * Return 0 on success, negative on failure
3662 **/
3663static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3664{
3665 int i, err = 0;
3666
3667 for (i = 0; i < adapter->num_tx_queues; i++) {
3668 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3669 if (!err)
3670 continue;
3671 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3672 break;
3673 }
3674
3675 return err;
3676}
3677
9a799d71
AK		 3678/**
3679 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3680 * @adapter: board private structure
3a581073 3681 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3682 *
3683 * Returns 0 on success, negative on failure
3684 **/
3685int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 3686 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3687{
3688 struct pci_dev *pdev = adapter->pdev;
021230d4 3689 int size;
9a799d71 3690
3a581073
JB		 3691 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3692 rx_ring->rx_buffer_info = vmalloc(size);
3693 if (!rx_ring->rx_buffer_info) {
9a799d71 3694 DPRINTK(PROBE, ERR,
b4617240 3695 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 3696 goto alloc_failed;
9a799d71 3697 }
3a581073 3698 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 3699
9a799d71 3700 /* Round up to nearest 4K */
3a581073
JB		 3701 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3702 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 3703
3a581073 3704 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 3705
3a581073 3706 if (!rx_ring->desc) {
9a799d71 3707 DPRINTK(PROBE, ERR,
b4617240 3708 "Memory allocation failed for the rx desc ring\n");
3a581073 3709 vfree(rx_ring->rx_buffer_info);
177db6ff 3710 goto alloc_failed;
9a799d71
AK		 3711 }
3712
3a581073
JB		 3713 rx_ring->next_to_clean = 0;
3714 rx_ring->next_to_use = 0;
9a799d71
AK		 3715
3716 return 0;
177db6ff
MC		 3717
3718alloc_failed:
177db6ff 3719 return -ENOMEM;
9a799d71
AK		 3720}
3721
69888674
AD		 3722/**
3723 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3724 * @adapter: board private structure
3725 *
3726 * If this function returns with an error, then it's possible one or
3727 * more of the rings is populated (while the rest are not). It is the
3728 * callers duty to clean those orphaned rings.
3729 *
3730 * Return 0 on success, negative on failure
3731 **/
3732
3733static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3734{
3735 int i, err = 0;
3736
3737 for (i = 0; i < adapter->num_rx_queues; i++) {
3738 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3739 if (!err)
3740 continue;
3741 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3742 break;
3743 }
3744
3745 return err;
3746}
3747
9a799d71
AK		 3748/**
3749 * ixgbe_free_tx_resources - Free Tx Resources per Queue
3750 * @adapter: board private structure
3751 * @tx_ring: Tx descriptor ring for a specific queue
3752 *
3753 * Free all transmit software resources
3754 **/
c431f97e
JB		 3755void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
3756 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3757{
3758 struct pci_dev *pdev = adapter->pdev;
3759
3760 ixgbe_clean_tx_ring(adapter, tx_ring);
3761
3762 vfree(tx_ring->tx_buffer_info);
3763 tx_ring->tx_buffer_info = NULL;
3764
3765 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
3766
3767 tx_ring->desc = NULL;
3768}
3769
3770/**
3771 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
3772 * @adapter: board private structure
3773 *
3774 * Free all transmit software resources
3775 **/
3776static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
3777{
3778 int i;
3779
3780 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 3781 if (adapter->tx_ring[i].desc)
3782 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 3783}
3784
3785/**
b4617240 3786 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 3787 * @adapter: board private structure
3788 * @rx_ring: ring to clean the resources from
3789 *
3790 * Free all receive software resources
3791 **/
c431f97e
JB		 3792void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
3793 struct ixgbe_ring *rx_ring)
9a799d71
AK		 3794{
3795 struct pci_dev *pdev = adapter->pdev;
3796
3797 ixgbe_clean_rx_ring(adapter, rx_ring);
3798
3799 vfree(rx_ring->rx_buffer_info);
3800 rx_ring->rx_buffer_info = NULL;
3801
3802 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
3803
3804 rx_ring->desc = NULL;
3805}
3806
3807/**
3808 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
3809 * @adapter: board private structure
3810 *
3811 * Free all receive software resources
3812 **/
3813static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
3814{
3815 int i;
3816
3817 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 3818 if (adapter->rx_ring[i].desc)
3819 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 3820}
3821
9a799d71
AK		 3822/**
3823 * ixgbe_change_mtu - Change the Maximum Transfer Unit
3824 * @netdev: network interface device structure
3825 * @new_mtu: new value for maximum frame size
3826 *
3827 * Returns 0 on success, negative on failure
3828 **/
3829static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3830{
3831 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3832 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3833
42c783c5
JB		 3834 /* MTU < 68 is an error and causes problems on some kernels */
3835 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3836 return -EINVAL;
3837
021230d4 3838 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3839 netdev->mtu, new_mtu);
021230d4 3840 /* must set new MTU before calling down or up */
9a799d71
AK		 3841 netdev->mtu = new_mtu;
3842
d4f80882
AV		 3843 if (netif_running(netdev))
3844 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3845
3846 return 0;
3847}
3848
3849/**
3850 * ixgbe_open - Called when a network interface is made active
3851 * @netdev: network interface device structure
3852 *
3853 * Returns 0 on success, negative value on failure
3854 *
3855 * The open entry point is called when a network interface is made
3856 * active by the system (IFF_UP). At this point all resources needed
3857 * for transmit and receive operations are allocated, the interrupt
3858 * handler is registered with the OS, the watchdog timer is started,
3859 * and the stack is notified that the interface is ready.
3860 **/
3861static int ixgbe_open(struct net_device *netdev)
3862{
3863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3864 int err;
4bebfaa5
AK		 3865
3866 /* disallow open during test */
3867 if (test_bit(__IXGBE_TESTING, &adapter->state))
3868 return -EBUSY;
9a799d71 3869
54386467
JB		 3870 netif_carrier_off(netdev);
3871
9a799d71
AK		 3872 /* allocate transmit descriptors */
3873 err = ixgbe_setup_all_tx_resources(adapter);
3874 if (err)
3875 goto err_setup_tx;
3876
9a799d71
AK		 3877 /* allocate receive descriptors */
3878 err = ixgbe_setup_all_rx_resources(adapter);
3879 if (err)
3880 goto err_setup_rx;
3881
3882 ixgbe_configure(adapter);
3883
021230d4 3884 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3885 if (err)
3886 goto err_req_irq;
3887
9a799d71
AK		 3888 err = ixgbe_up_complete(adapter);
3889 if (err)
3890 goto err_up;
3891
d55b53ff
JK		 3892 netif_tx_start_all_queues(netdev);
3893
9a799d71
AK		 3894 return 0;
3895
3896err_up:
5eba3699 3897 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3898 ixgbe_free_irq(adapter);
3899err_req_irq:
9a799d71 3900err_setup_rx:
a20a1199 3901 ixgbe_free_all_rx_resources(adapter);
9a799d71 3902err_setup_tx:
a20a1199 3903 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 3904 ixgbe_reset(adapter);
3905
3906 return err;
3907}
3908
3909/**
3910 * ixgbe_close - Disables a network interface
3911 * @netdev: network interface device structure
3912 *
3913 * Returns 0, this is not allowed to fail
3914 *
3915 * The close entry point is called when an interface is de-activated
3916 * by the OS. The hardware is still under the drivers control, but
3917 * needs to be disabled. A global MAC reset is issued to stop the
3918 * hardware, and all transmit and receive resources are freed.
3919 **/
3920static int ixgbe_close(struct net_device *netdev)
3921{
3922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3923
3924 ixgbe_down(adapter);
3925 ixgbe_free_irq(adapter);
3926
3927 ixgbe_free_all_tx_resources(adapter);
3928 ixgbe_free_all_rx_resources(adapter);
3929
5eba3699 3930 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3931
3932 return 0;
3933}
3934
b3c8b4ba
AD		 3935#ifdef CONFIG_PM
3936static int ixgbe_resume(struct pci_dev *pdev)
3937{
3938 struct net_device *netdev = pci_get_drvdata(pdev);
3939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3940 u32 err;
3941
3942 pci_set_power_state(pdev, PCI_D0);
3943 pci_restore_state(pdev);
9ce77666 3944
3945 err = pci_enable_device_mem(pdev);
b3c8b4ba 3946 if (err) {
69888674 3947 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3948 "suspend\n");
3949 return err;
3950 }
3951 pci_set_master(pdev);
3952
dd4d8ca6 3953 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 3954
3955 err = ixgbe_init_interrupt_scheme(adapter);
3956 if (err) {
3957 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3958 "device\n");
3959 return err;
3960 }
3961
b3c8b4ba
AD		 3962 ixgbe_reset(adapter);
3963
495dce12
WJP		 3964 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
3965
b3c8b4ba
AD		 3966 if (netif_running(netdev)) {
3967 err = ixgbe_open(adapter->netdev);
3968 if (err)
3969 return err;
3970 }
3971
3972 netif_device_attach(netdev);
3973
3974 return 0;
3975}
b3c8b4ba 3976#endif /* CONFIG_PM */
9d8d05ae
RW		 3977
3978static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 3979{
3980 struct net_device *netdev = pci_get_drvdata(pdev);
3981 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 3982 struct ixgbe_hw *hw = &adapter->hw;
3983 u32 ctrl, fctrl;
3984 u32 wufc = adapter->wol;
b3c8b4ba
AD		 3985#ifdef CONFIG_PM
3986 int retval = 0;
3987#endif
3988
3989 netif_device_detach(netdev);
3990
3991 if (netif_running(netdev)) {
3992 ixgbe_down(adapter);
3993 ixgbe_free_irq(adapter);
3994 ixgbe_free_all_tx_resources(adapter);
3995 ixgbe_free_all_rx_resources(adapter);
3996 }
7a921c93 3997 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 3998
3999#ifdef CONFIG_PM
4000 retval = pci_save_state(pdev);
4001 if (retval)
4002 return retval;
4df10466 4003
b3c8b4ba 4004#endif
e8e26350
PW		 4005 if (wufc) {
4006 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4007
e8e26350
PW		 4008 /* turn on all-multi mode if wake on multicast is enabled */
4009 if (wufc & IXGBE_WUFC_MC) {
4010 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4011 fctrl |= IXGBE_FCTRL_MPE;
4012 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4013 }
4014
4015 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4016 ctrl |= IXGBE_CTRL_GIO_DIS;
4017 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4018
4019 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4020 } else {
4021 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4022 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4023 }
4024
dd4d8ca6
DS		 4025 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4026 pci_wake_from_d3(pdev, true);
4027 else
4028 pci_wake_from_d3(pdev, false);
b3c8b4ba 4029
9d8d05ae
RW		 4030 *enable_wake = !!wufc;
4031
b3c8b4ba
AD		 4032 ixgbe_release_hw_control(adapter);
4033
4034 pci_disable_device(pdev);
4035
9d8d05ae
RW		 4036 return 0;
4037}
4038
4039#ifdef CONFIG_PM
4040static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4041{
4042 int retval;
4043 bool wake;
4044
4045 retval = __ixgbe_shutdown(pdev, &wake);
4046 if (retval)
4047 return retval;
4048
4049 if (wake) {
4050 pci_prepare_to_sleep(pdev);
4051 } else {
4052 pci_wake_from_d3(pdev, false);
4053 pci_set_power_state(pdev, PCI_D3hot);
4054 }
b3c8b4ba
AD		 4055
4056 return 0;
4057}
9d8d05ae 4058#endif /* CONFIG_PM */
b3c8b4ba
AD		 4059
4060static void ixgbe_shutdown(struct pci_dev *pdev)
4061{
9d8d05ae
RW		 4062 bool wake;
4063
4064 __ixgbe_shutdown(pdev, &wake);
4065
4066 if (system_state == SYSTEM_POWER_OFF) {
4067 pci_wake_from_d3(pdev, wake);
4068 pci_set_power_state(pdev, PCI_D3hot);
4069 }
b3c8b4ba
AD		 4070}
4071
9a799d71
AK		 4072/**
4073 * ixgbe_update_stats - Update the board statistics counters.
4074 * @adapter: board private structure
4075 **/
4076void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4077{
4078 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4079 u64 total_mpc = 0;
4080 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4081
d51019a4 4082 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4083 u64 rsc_count = 0;
d51019a4
PW		 4084 for (i = 0; i < 16; i++)
4085 adapter->hw_rx_no_dma_resources +=
4086 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4087 for (i = 0; i < adapter->num_rx_queues; i++)
4088 rsc_count += adapter->rx_ring[i].rsc_count;
4089 adapter->rsc_count = rsc_count;
d51019a4
PW		 4090 }
4091
9a799d71 4092 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4093 for (i = 0; i < 8; i++) {
4094 /* for packet buffers not used, the register should read 0 */
4095 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4096 missed_rx += mpc;
4097 adapter->stats.mpc[i] += mpc;
4098 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4099 if (hw->mac.type == ixgbe_mac_82598EB)
4100 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4101 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4102 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4103 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4104 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4105 if (hw->mac.type == ixgbe_mac_82599EB) {
4106 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4107 IXGBE_PXONRXCNT(i));
4108 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4109 IXGBE_PXOFFRXCNT(i));
4110 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4111 } else {
4112 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4113 IXGBE_PXONRXC(i));
4114 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4115 IXGBE_PXOFFRXC(i));
4116 }
2f90b865
AD		 4117 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4118 IXGBE_PXONTXC(i));
2f90b865 4119 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4120 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4121 }
4122 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4123 /* work around hardware counting issue */
4124 adapter->stats.gprc -= missed_rx;
4125
4126 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350
PW		 4127 if (hw->mac.type == ixgbe_mac_82599EB) {
4128 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4129 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4130 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4131 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4132 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4133 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4134 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4135 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
6d45522c
YZ		 4136#ifdef IXGBE_FCOE
4137 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4138 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4139 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4140 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4141 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4142 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4143#endif /* IXGBE_FCOE */
e8e26350
PW		 4144 } else {
4145 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4146 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4147 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4148 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4149 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4150 }
9a799d71
AK		 4151 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4152 adapter->stats.bprc += bprc;
4153 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4154 if (hw->mac.type == ixgbe_mac_82598EB)
4155 adapter->stats.mprc -= bprc;
9a799d71
AK		 4156 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4157 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4158 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4159 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4160 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4161 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4162 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4163 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4164 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4165 adapter->stats.lxontxc += lxon;
4166 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4167 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4168 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4169 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4170 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4171 /*
4172 * 82598 errata - tx of flow control packets is included in tx counters
4173 */
4174 xon_off_tot = lxon + lxoff;
4175 adapter->stats.gptc -= xon_off_tot;
4176 adapter->stats.mptc -= xon_off_tot;
4177 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4178 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4179 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4180 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4181 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4182 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4183 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4184 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4185 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4186 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4187 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4188 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4189 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4190
4191 /* Fill out the OS statistics structure */
9a799d71
AK		 4192 adapter->net_stats.multicast = adapter->stats.mprc;
4193
4194 /* Rx Errors */
4195 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4196 adapter->stats.rlec;
9a799d71
AK		 4197 adapter->net_stats.rx_dropped = 0;
4198 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4199 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4200 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4201}
4202
4203/**
4204 * ixgbe_watchdog - Timer Call-back
4205 * @data: pointer to adapter cast into an unsigned long
4206 **/
4207static void ixgbe_watchdog(unsigned long data)
4208{
4209 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 4210 struct ixgbe_hw *hw = &adapter->hw;
4211
4212 /* Do the watchdog outside of interrupt context due to the lovely
4213 * delays that some of the newer hardware requires */
4214 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
22d5a71b
JB		 4215 u64 eics = 0;
4216 int i;
4217
4218 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++)
c9c7d2e5 4219 eics |= ((u64)1 << i);
22d5a71b 4220
cf8280ee 4221 /* Cause software interrupt to ensure rx rings are cleaned */
22d5a71b
JB		 4222 switch (hw->mac.type) {
4223 case ixgbe_mac_82598EB:
4224 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4225 IXGBE_WRITE_REG(hw, IXGBE_EICS, (u32)eics);
4226 } else {
4227 /*
4228 * for legacy and MSI interrupts don't set any
4229 * bits that are enabled for EIAM, because this
4230 * operation would set *both* EIMS and EICS for
4231 * any bit in EIAM
4232 */
4233 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4234 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4235 }
4236 break;
4237 case ixgbe_mac_82599EB:
4238 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
835462fc
NS		 4239 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(0),
4240 (u32)(eics & 0xFFFFFFFF));
22d5a71b 4241 IXGBE_WRITE_REG(hw, IXGBE_EICS_EX(1),
22d5a71b
JB		 4242 (u32)(eics >> 32));
4243 } else {
4244 /*
4245 * for legacy and MSI interrupts don't set any
4246 * bits that are enabled for EIAM, because this
4247 * operation would set *both* EIMS and EICS for
4248 * any bit in EIAM
4249 */
4250 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4251 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4252 }
4253 break;
4254 default:
4255 break;
cf8280ee
JB		 4256 }
4257 /* Reset the timer */
4258 mod_timer(&adapter->watchdog_timer,
4259 round_jiffies(jiffies + 2 * HZ));
4260 }
9a799d71 4261
cf8280ee
JB		 4262 schedule_work(&adapter->watchdog_task);
4263}
4264
e8e26350
PW		 4265/**
4266 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4267 * @work: pointer to work_struct containing our data
4268 **/
4269static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4270{
4271 struct ixgbe_adapter *adapter = container_of(work,
4272 struct ixgbe_adapter,
4273 multispeed_fiber_task);
4274 struct ixgbe_hw *hw = &adapter->hw;
4275 u32 autoneg;
4276
4277 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4278 if (hw->mac.ops.get_link_capabilities)
4279 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4280 &hw->mac.autoneg);
4281 if (hw->mac.ops.setup_link_speed)
4282 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4283 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4284 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4285}
4286
4287/**
4288 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4289 * @work: pointer to work_struct containing our data
4290 **/
4291static void ixgbe_sfp_config_module_task(struct work_struct *work)
4292{
4293 struct ixgbe_adapter *adapter = container_of(work,
4294 struct ixgbe_adapter,
4295 sfp_config_module_task);
4296 struct ixgbe_hw *hw = &adapter->hw;
4297 u32 err;
4298
4299 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4300 err = hw->phy.ops.identify_sfp(hw);
4301 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4302 DPRINTK(PROBE, ERR, "PHY not supported on this NIC %d\n", err);
4303 ixgbe_down(adapter);
4304 return;
4305 }
4306 hw->mac.ops.setup_sfp(hw);
4307
8d1c3c07 4308 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4309 /* This will also work for DA Twinax connections */
4310 schedule_work(&adapter->multispeed_fiber_task);
4311 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4312}
4313
cf8280ee 4314/**
69888674
AD		 4315 * ixgbe_watchdog_task - worker thread to bring link up
4316 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4317 **/
4318static void ixgbe_watchdog_task(struct work_struct *work)
4319{
4320 struct ixgbe_adapter *adapter = container_of(work,
4321 struct ixgbe_adapter,
4322 watchdog_task);
4323 struct net_device *netdev = adapter->netdev;
4324 struct ixgbe_hw *hw = &adapter->hw;
4325 u32 link_speed = adapter->link_speed;
4326 bool link_up = adapter->link_up;
bc59fcda
NS		 4327 int i;
4328 struct ixgbe_ring *tx_ring;
4329 int some_tx_pending = 0;
cf8280ee
JB		 4330
4331 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4332
4333 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4334 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4335 if (link_up) {
4336#ifdef CONFIG_DCB
4337 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4338 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4339 hw->mac.ops.setup_fc(hw, i);
4340 } else {
4341 hw->mac.ops.setup_fc(hw, 0);
4342 }
4343#else
4344 hw->mac.ops.setup_fc(hw, 0);
4345#endif
4346 }
4347
cf8280ee
JB		 4348 if (link_up ||
4349 time_after(jiffies, (adapter->link_check_timeout +
4350 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4351 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4352 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4353 }
4354 adapter->link_up = link_up;
4355 adapter->link_speed = link_speed;
4356 }
9a799d71
AK		 4357
4358 if (link_up) {
4359 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4360 bool flow_rx, flow_tx;
4361
4362 if (hw->mac.type == ixgbe_mac_82599EB) {
4363 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4364 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4365 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4366 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4367 } else {
4368 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4369 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4370 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4371 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4372 }
4373
a46e534b
JK		 4374 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4375 "Flow Control: %s\n",
4376 netdev->name,
4377 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4378 "10 Gbps" :
4379 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4380 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4381 ((flow_rx && flow_tx) ? "RX/TX" :
4382 (flow_rx ? "RX" :
4383 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4384
4385 netif_carrier_on(netdev);
9a799d71
AK		 4386 } else {
4387 /* Force detection of hung controller */
4388 adapter->detect_tx_hung = true;
4389 }
4390 } else {
cf8280ee
JB		 4391 adapter->link_up = false;
4392 adapter->link_speed = 0;
9a799d71 4393 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4394 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4395 netdev->name);
9a799d71 4396 netif_carrier_off(netdev);
9a799d71
AK		 4397 }
4398 }
4399
bc59fcda
NS		 4400 if (!netif_carrier_ok(netdev)) {
4401 for (i = 0; i < adapter->num_tx_queues; i++) {
4402 tx_ring = &adapter->tx_ring[i];
4403 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4404 some_tx_pending = 1;
4405 break;
4406 }
4407 }
4408
4409 if (some_tx_pending) {
4410 /* We've lost link, so the controller stops DMA,
4411 * but we've got queued Tx work that's never going
4412 * to get done, so reset controller to flush Tx.
4413 * (Do the reset outside of interrupt context).
4414 */
4415 schedule_work(&adapter->reset_task);
4416 }
4417 }
4418
9a799d71 4419 ixgbe_update_stats(adapter);
cf8280ee 4420 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4421}
4422
9a799d71 4423static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4424 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4425 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4426{
4427 struct ixgbe_adv_tx_context_desc *context_desc;
4428 unsigned int i;
4429 int err;
4430 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4431 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4432 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4433
4434 if (skb_is_gso(skb)) {
4435 if (skb_header_cloned(skb)) {
4436 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4437 if (err)
4438 return err;
4439 }
4440 l4len = tcp_hdrlen(skb);
4441 *hdr_len += l4len;
4442
8327d000 4443 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4444 struct iphdr *iph = ip_hdr(skb);
4445 iph->tot_len = 0;
4446 iph->check = 0;
4447 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4448 iph->daddr, 0,
4449 IPPROTO_TCP,
4450 0);
9a799d71
AK		 4451 adapter->hw_tso_ctxt++;
4452 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4453 ipv6_hdr(skb)->payload_len = 0;
4454 tcp_hdr(skb)->check =
4455 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4456 &ipv6_hdr(skb)->daddr,
4457 0, IPPROTO_TCP, 0);
9a799d71
AK		 4458 adapter->hw_tso6_ctxt++;
4459 }
4460
4461 i = tx_ring->next_to_use;
4462
4463 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4464 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4465
4466 /* VLAN MACLEN IPLEN */
4467 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4468 vlan_macip_lens |=
4469 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4470 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4471 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4472 *hdr_len += skb_network_offset(skb);
4473 vlan_macip_lens |=
4474 (skb_transport_header(skb) - skb_network_header(skb));
4475 *hdr_len +=
4476 (skb_transport_header(skb) - skb_network_header(skb));
4477 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4478 context_desc->seqnum_seed = 0;
4479
4480 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4481 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4482 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4483
8327d000 4484 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4485 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4486 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4487 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4488
4489 /* MSS L4LEN IDX */
9f8cdf4f 4490 mss_l4len_idx =
9a799d71
AK		 4491 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4492 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4493 /* use index 1 for TSO */
4494 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4495 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4496
4497 tx_buffer_info->time_stamp = jiffies;
4498 tx_buffer_info->next_to_watch = i;
4499
4500 i++;
4501 if (i == tx_ring->count)
4502 i = 0;
4503 tx_ring->next_to_use = i;
4504
4505 return true;
4506 }
4507 return false;
4508}
4509
4510static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4511 struct ixgbe_ring *tx_ring,
4512 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4513{
4514 struct ixgbe_adv_tx_context_desc *context_desc;
4515 unsigned int i;
4516 struct ixgbe_tx_buffer *tx_buffer_info;
4517 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4518
4519 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4520 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4521 i = tx_ring->next_to_use;
4522 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4523 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4524
4525 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4526 vlan_macip_lens |=
4527 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4528 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4529 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4530 if (skb->ip_summed == CHECKSUM_PARTIAL)
4531 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4532 skb_network_header(skb));
9a799d71
AK		 4533
4534 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4535 context_desc->seqnum_seed = 0;
4536
4537 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4538 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4539
4540 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4541 switch (skb->protocol) {
09640e63 4542 case cpu_to_be16(ETH_P_IP):
9a799d71 4543 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4544 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4545 type_tucmd_mlhl |=
b4617240 4546 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4547 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4548 type_tucmd_mlhl |=
4549 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4550 break;
09640e63 4551 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4552 /* XXX what about other V6 headers?? */
4553 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4554 type_tucmd_mlhl |=
b4617240 4555 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4556 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4557 type_tucmd_mlhl |=
4558 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4559 break;
41825d71
AK		 4560 default:
4561 if (unlikely(net_ratelimit())) {
4562 DPRINTK(PROBE, WARNING,
4563 "partial checksum but proto=%x!\n",
4564 skb->protocol);
4565 }
4566 break;
4567 }
9a799d71
AK		 4568 }
4569
4570 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4571 /* use index zero for tx checksum offload */
9a799d71
AK		 4572 context_desc->mss_l4len_idx = 0;
4573
4574 tx_buffer_info->time_stamp = jiffies;
4575 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4576
9a799d71
AK		 4577 adapter->hw_csum_tx_good++;
4578 i++;
4579 if (i == tx_ring->count)
4580 i = 0;
4581 tx_ring->next_to_use = i;
4582
4583 return true;
4584 }
9f8cdf4f 4585
9a799d71
AK		 4586 return false;
4587}
4588
4589static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4590 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4591 struct sk_buff *skb, u32 tx_flags,
4592 unsigned int first)
9a799d71
AK		 4593{
4594 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4595 unsigned int len;
4596 unsigned int total = skb->len;
9a799d71
AK		 4597 unsigned int offset = 0, size, count = 0, i;
4598 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4599 unsigned int f;
44df32c5 4600 dma_addr_t *map;
9a799d71
AK		 4601
4602 i = tx_ring->next_to_use;
4603
44df32c5
AD		 4604 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4605 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4606 return 0;
4607 }
4608
4609 map = skb_shinfo(skb)->dma_maps;
4610
eacd73f7
YZ		 4611 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4612 /* excluding fcoe_crc_eof for FCoE */
4613 total -= sizeof(struct fcoe_crc_eof);
4614
4615 len = min(skb_headlen(skb), total);
9a799d71
AK		 4616 while (len) {
4617 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4618 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4619
4620 tx_buffer_info->length = size;
44df32c5 4621 tx_buffer_info->dma = map[0] + offset;
9a799d71
AK		 4622 tx_buffer_info->time_stamp = jiffies;
4623 tx_buffer_info->next_to_watch = i;
4624
4625 len -= size;
eacd73f7 4626 total -= size;
9a799d71
AK		 4627 offset += size;
4628 count++;
44df32c5
AD		 4629
4630 if (len) {
4631 i++;
4632 if (i == tx_ring->count)
4633 i = 0;
4634 }
9a799d71
AK		 4635 }
4636
4637 for (f = 0; f < nr_frags; f++) {
4638 struct skb_frag_struct *frag;
4639
4640 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4641 len = min((unsigned int)frag->size, total);
44df32c5 4642 offset = 0;
9a799d71
AK		 4643
4644 while (len) {
44df32c5
AD		 4645 i++;
4646 if (i == tx_ring->count)
4647 i = 0;
4648
9a799d71
AK		 4649 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4650 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4651
4652 tx_buffer_info->length = size;
44df32c5 4653 tx_buffer_info->dma = map[f + 1] + offset;
9a799d71
AK		 4654 tx_buffer_info->time_stamp = jiffies;
4655 tx_buffer_info->next_to_watch = i;
4656
4657 len -= size;
eacd73f7 4658 total -= size;
9a799d71
AK		 4659 offset += size;
4660 count++;
9a799d71 4661 }
eacd73f7
YZ		 4662 if (total == 0)
4663 break;
9a799d71 4664 }
44df32c5 4665
9a799d71
AK		 4666 tx_ring->tx_buffer_info[i].skb = skb;
4667 tx_ring->tx_buffer_info[first].next_to_watch = i;
4668
4669 return count;
4670}
4671
4672static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 4673 struct ixgbe_ring *tx_ring,
4674 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 4675{
4676 union ixgbe_adv_tx_desc *tx_desc = NULL;
4677 struct ixgbe_tx_buffer *tx_buffer_info;
4678 u32 olinfo_status = 0, cmd_type_len = 0;
4679 unsigned int i;
4680 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4681
4682 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4683
4684 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4685
4686 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4687 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4688
4689 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4690 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4691
4692 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4693 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4694
4eeae6fd
PW		 4695 /* use index 1 context for tso */
4696 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4697 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4698 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 4699 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 4700
4701 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4702 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 4703 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 4704
eacd73f7
YZ		 4705 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4706 olinfo_status |= IXGBE_ADVTXD_CC;
4707 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4708 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4709 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4710 }
4711
9a799d71
AK		 4712 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4713
4714 i = tx_ring->next_to_use;
4715 while (count--) {
4716 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4717 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4718 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4719 tx_desc->read.cmd_type_len =
b4617240 4720 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 4721 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 4722 i++;
4723 if (i == tx_ring->count)
4724 i = 0;
4725 }
4726
4727 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
4728
4729 /*
4730 * Force memory writes to complete before letting h/w
4731 * know there are new descriptors to fetch. (Only
4732 * applicable for weak-ordered memory model archs,
4733 * such as IA-64).
4734 */
4735 wmb();
4736
4737 tx_ring->next_to_use = i;
4738 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4739}
4740
e092be60 4741static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4742 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4743{
4744 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4745
30eba97a 4746 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4747 /* Herbert's original patch had:
4748 * smp_mb__after_netif_stop_queue();
4749 * but since that doesn't exist yet, just open code it. */
4750 smp_mb();
4751
4752 /* We need to check again in a case another CPU has just
4753 * made room available. */
4754 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
4755 return -EBUSY;
4756
4757 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 4758 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 4759 ++adapter->restart_queue;
4760 return 0;
4761}
4762
4763static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 4764 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 4765{
4766 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
4767 return 0;
4768 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
4769}
4770
09a3b1f8
SH		 4771static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
4772{
4773 struct ixgbe_adapter *adapter = netdev_priv(dev);
4774
4775 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4776 return 0; /* All traffic should default to class 0 */
4777
4778 return skb_tx_hash(dev, skb);
4779}
4780
9a799d71
AK		 4781static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
4782{
4783 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4784 struct ixgbe_ring *tx_ring;
9a799d71
AK		 4785 unsigned int first;
4786 unsigned int tx_flags = 0;
30eba97a
AV		 4787 u8 hdr_len = 0;
4788 int r_idx = 0, tso;
9a799d71
AK		 4789 int count = 0;
4790 unsigned int f;
9f8cdf4f 4791
95615d90 4792 r_idx = skb->queue_mapping;
30eba97a 4793 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 4794
9f8cdf4f
JB		 4795 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
4796 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 4797 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4798 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
4799 tx_flags |= (skb->queue_mapping << 13);
4800 }
4801 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4802 tx_flags |= IXGBE_TX_FLAGS_VLAN;
4803 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4804 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 4805 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
4806 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 4807 }
eacd73f7
YZ		 4808
4809 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4810 (skb->protocol == htons(ETH_P_FCOE)))
4811 tx_flags |= IXGBE_TX_FLAGS_FCOE;
4812
4813 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 4814 if (skb_is_gso(skb) ||
4815 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 4816 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
4817 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 4818 count++;
4819
9f8cdf4f
JB		 4820 count += TXD_USE_COUNT(skb_headlen(skb));
4821 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 4822 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4823
e092be60 4824 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 4825 adapter->tx_busy++;
9a799d71
AK		 4826 return NETDEV_TX_BUSY;
4827 }
9a799d71 4828
9a799d71 4829 first = tx_ring->next_to_use;
eacd73f7
YZ		 4830 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4831#ifdef IXGBE_FCOE
4832 /* setup tx offload for FCoE */
4833 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4834 if (tso < 0) {
4835 dev_kfree_skb_any(skb);
4836 return NETDEV_TX_OK;
4837 }
4838 if (tso)
4839 tx_flags |= IXGBE_TX_FLAGS_FSO;
4840#endif /* IXGBE_FCOE */
4841 } else {
4842 if (skb->protocol == htons(ETH_P_IP))
4843 tx_flags |= IXGBE_TX_FLAGS_IPV4;
4844 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
4845 if (tso < 0) {
4846 dev_kfree_skb_any(skb);
4847 return NETDEV_TX_OK;
4848 }
9a799d71 4849
eacd73f7
YZ		 4850 if (tso)
4851 tx_flags |= IXGBE_TX_FLAGS_TSO;
4852 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
4853 (skb->ip_summed == CHECKSUM_PARTIAL))
4854 tx_flags |= IXGBE_TX_FLAGS_CSUM;
4855 }
9a799d71 4856
eacd73f7 4857 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5
AD		 4858 if (count) {
4859 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
4860 hdr_len);
4861 netdev->trans_start = jiffies;
4862 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 4863
44df32c5
AD		 4864 } else {
4865 dev_kfree_skb_any(skb);
4866 tx_ring->tx_buffer_info[first].time_stamp = 0;
4867 tx_ring->next_to_use = first;
4868 }
9a799d71
AK		 4869
4870 return NETDEV_TX_OK;
4871}
4872
4873/**
4874 * ixgbe_get_stats - Get System Network Statistics
4875 * @netdev: network interface device structure
4876 *
4877 * Returns the address of the device statistics structure.
4878 * The statistics are actually updated from the timer callback.
4879 **/
4880static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
4881{
4882 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4883
4884 /* only return the current stats */
4885 return &adapter->net_stats;
4886}
4887
4888/**
4889 * ixgbe_set_mac - Change the Ethernet Address of the NIC
4890 * @netdev: network interface device structure
4891 * @p: pointer to an address structure
4892 *
4893 * Returns 0 on success, negative on failure
4894 **/
4895static int ixgbe_set_mac(struct net_device *netdev, void *p)
4896{
4897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 4898 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 4899 struct sockaddr *addr = p;
4900
4901 if (!is_valid_ether_addr(addr->sa_data))
4902 return -EADDRNOTAVAIL;
4903
4904 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 4905 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 4906
b4617240 4907 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 4908
4909 return 0;
4910}
4911
6b73e10d
BH		 4912static int
4913ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
4914{
4915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4916 struct ixgbe_hw *hw = &adapter->hw;
4917 u16 value;
4918 int rc;
4919
4920 if (prtad != hw->phy.mdio.prtad)
4921 return -EINVAL;
4922 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
4923 if (!rc)
4924 rc = value;
4925 return rc;
4926}
4927
4928static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
4929 u16 addr, u16 value)
4930{
4931 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4932 struct ixgbe_hw *hw = &adapter->hw;
4933
4934 if (prtad != hw->phy.mdio.prtad)
4935 return -EINVAL;
4936 return hw->phy.ops.write_reg(hw, addr, devad, value);
4937}
4938
4939static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
4940{
4941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4942
4943 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
4944}
4945
0365e6e4
PW		 4946/**
4947 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
4948 * netdev->dev_addr_list
4949 * @netdev: network interface device structure
4950 *
4951 * Returns non-zero on failure
4952 **/
4953static int ixgbe_add_sanmac_netdev(struct net_device *dev)
4954{
4955 int err = 0;
4956 struct ixgbe_adapter *adapter = netdev_priv(dev);
4957 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4958
4959 if (is_valid_ether_addr(mac->san_addr)) {
4960 rtnl_lock();
4961 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4962 rtnl_unlock();
4963 }
4964 return err;
4965}
4966
4967/**
4968 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
4969 * netdev->dev_addr_list
4970 * @netdev: network interface device structure
4971 *
4972 * Returns non-zero on failure
4973 **/
4974static int ixgbe_del_sanmac_netdev(struct net_device *dev)
4975{
4976 int err = 0;
4977 struct ixgbe_adapter *adapter = netdev_priv(dev);
4978 struct ixgbe_mac_info *mac = &adapter->hw.mac;
4979
4980 if (is_valid_ether_addr(mac->san_addr)) {
4981 rtnl_lock();
4982 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
4983 rtnl_unlock();
4984 }
4985 return err;
4986}
4987
9a799d71
AK		 4988#ifdef CONFIG_NET_POLL_CONTROLLER
4989/*
4990 * Polling 'interrupt' - used by things like netconsole to send skbs
4991 * without having to re-enable interrupts. It's not called while
4992 * the interrupt routine is executing.
4993 */
4994static void ixgbe_netpoll(struct net_device *netdev)
4995{
4996 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4997
4998 disable_irq(adapter->pdev->irq);
4999 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5000 ixgbe_intr(adapter->pdev->irq, netdev);
5001 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5002 enable_irq(adapter->pdev->irq);
5003}
5004#endif
5005
0edc3527
SH		 5006static const struct net_device_ops ixgbe_netdev_ops = {
5007 .ndo_open = ixgbe_open,
5008 .ndo_stop = ixgbe_close,
00829823 5009 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5010 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5011 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5012 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5013 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5014 .ndo_validate_addr = eth_validate_addr,
5015 .ndo_set_mac_address = ixgbe_set_mac,
5016 .ndo_change_mtu = ixgbe_change_mtu,
5017 .ndo_tx_timeout = ixgbe_tx_timeout,
5018 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5019 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5020 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5021 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5022#ifdef CONFIG_NET_POLL_CONTROLLER
5023 .ndo_poll_controller = ixgbe_netpoll,
5024#endif
332d4a7d
YZ		 5025#ifdef IXGBE_FCOE
5026 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5027 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5028#endif /* IXGBE_FCOE */
0edc3527
SH		 5029};
5030
9a799d71
AK		 5031/**
5032 * ixgbe_probe - Device Initialization Routine
5033 * @pdev: PCI device information struct
5034 * @ent: entry in ixgbe_pci_tbl
5035 *
5036 * Returns 0 on success, negative on failure
5037 *
5038 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5039 * The OS initialization, configuring of the adapter private structure,
5040 * and a hardware reset occur.
5041 **/
5042static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5043 const struct pci_device_id *ent)
9a799d71
AK		 5044{
5045 struct net_device *netdev;
5046 struct ixgbe_adapter *adapter = NULL;
5047 struct ixgbe_hw *hw;
5048 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5049 static int cards_found;
5050 int i, err, pci_using_dac;
eacd73f7
YZ		 5051#ifdef IXGBE_FCOE
5052 u16 device_caps;
5053#endif
c44ade9e 5054 u32 part_num, eec;
9a799d71 5055
9ce77666 5056 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5057 if (err)
5058 return err;
5059
6a35528a
YH		 5060 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5061 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5062 pci_using_dac = 1;
5063 } else {
284901a9 5064 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5065 if (err) {
284901a9 5066 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5067 if (err) {
b4617240
PW		 5068 dev_err(&pdev->dev, "No usable DMA "
5069 "configuration, aborting\n");
9a799d71
AK		 5070 goto err_dma;
5071 }
5072 }
5073 pci_using_dac = 0;
5074 }
5075
9ce77666 5076 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5077 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5078 if (err) {
9ce77666 5079 dev_err(&pdev->dev,
5080 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5081 goto err_pci_reg;
5082 }
5083
6fabd715
PWJ		 5084 err = pci_enable_pcie_error_reporting(pdev);
5085 if (err) {
5086 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5087 "0x%x\n", err);
5088 /* non-fatal, continue */
5089 }
5090
9a799d71 5091 pci_set_master(pdev);
fb3b27bc 5092 pci_save_state(pdev);
9a799d71 5093
30eba97a 5094 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5095 if (!netdev) {
5096 err = -ENOMEM;
5097 goto err_alloc_etherdev;
5098 }
5099
9a799d71
AK		 5100 SET_NETDEV_DEV(netdev, &pdev->dev);
5101
5102 pci_set_drvdata(pdev, netdev);
5103 adapter = netdev_priv(netdev);
5104
5105 adapter->netdev = netdev;
5106 adapter->pdev = pdev;
5107 hw = &adapter->hw;
5108 hw->back = adapter;
5109 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5110
05857980
JK		 5111 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5112 pci_resource_len(pdev, 0));
9a799d71
AK		 5113 if (!hw->hw_addr) {
5114 err = -EIO;
5115 goto err_ioremap;
5116 }
5117
5118 for (i = 1; i <= 5; i++) {
5119 if (pci_resource_len(pdev, i) == 0)
5120 continue;
5121 }
5122
0edc3527 5123 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5124 ixgbe_set_ethtool_ops(netdev);
9a799d71 5125 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5126 strcpy(netdev->name, pci_name(pdev));
5127
9a799d71
AK		 5128 adapter->bd_number = cards_found;
5129
9a799d71
AK		 5130 /* Setup hw api */
5131 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5132 hw->mac.type = ii->mac;
9a799d71 5133
c44ade9e
JB		 5134 /* EEPROM */
5135 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5136 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5137 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5138 if (!(eec & (1 << 8)))
5139 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5140
5141 /* PHY */
5142 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5143 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5144 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5145 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5146 hw->phy.mdio.mmds = 0;
5147 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5148 hw->phy.mdio.dev = netdev;
5149 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5150 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5151
5152 /* set up this timer and work struct before calling get_invariants
5153 * which might start the timer
5154 */
5155 init_timer(&adapter->sfp_timer);
5156 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5157 adapter->sfp_timer.data = (unsigned long) adapter;
5158
5159 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5160
e8e26350
PW		 5161 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5162 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5163
5164 /* a new SFP+ module arrival, called from GPI SDP2 context */
5165 INIT_WORK(&adapter->sfp_config_module_task,
5166 ixgbe_sfp_config_module_task);
5167
9a799d71 5168 err = ii->get_invariants(hw);
c4900be0
DS		 5169 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5170 /* start a kernel thread to watch for a module to arrive */
5171 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5172 mod_timer(&adapter->sfp_timer,
5173 round_jiffies(jiffies + (2 * HZ)));
5174 err = 0;
5175 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5176 DPRINTK(PROBE, ERR, "failed to load because an "
5177 "unsupported SFP+ module type was detected.\n");
9a799d71 5178 goto err_hw_init;
c4900be0
DS		 5179 } else if (err) {
5180 goto err_hw_init;
5181 }
9a799d71
AK		 5182
5183 /* setup the private structure */
5184 err = ixgbe_sw_init(adapter);
5185 if (err)
5186 goto err_sw_init;
5187
bf069c97
DS		 5188 /*
5189 * If there is a fan on this device and it has failed log the
5190 * failure.
5191 */
5192 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5193 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5194 if (esdp & IXGBE_ESDP_SDP1)
5195 DPRINTK(PROBE, CRIT,
5196 "Fan has stopped, replace the adapter\n");
5197 }
5198
c44ade9e
JB		 5199 /* reset_hw fills in the perm_addr as well */
5200 err = hw->mac.ops.reset_hw(hw);
04f165ef
PW		 5201 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5202 dev_err(&adapter->pdev->dev, "failed to load because an "
5203 "unsupported SFP+ module type was detected.\n");
5204 goto err_sw_init;
5205 } else if (err) {
c44ade9e
JB		 5206 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5207 goto err_sw_init;
5208 }
5209
9a799d71 5210 netdev->features = NETIF_F_SG |
b4617240
PW		 5211 NETIF_F_IP_CSUM |
5212 NETIF_F_HW_VLAN_TX |
5213 NETIF_F_HW_VLAN_RX |
5214 NETIF_F_HW_VLAN_FILTER;
9a799d71 5215
e9990a9c 5216 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5217 netdev->features |= NETIF_F_TSO;
9a799d71 5218 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5219 netdev->features |= NETIF_F_GRO;
ad31c402 5220
45a5ead0
JB		 5221 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5222 netdev->features |= NETIF_F_SCTP_CSUM;
5223
ad31c402
JK		 5224 netdev->vlan_features |= NETIF_F_TSO;
5225 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5226 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 5227 netdev->vlan_features |= NETIF_F_SG;
5228
2f90b865
AD		 5229 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5230 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5231
7a6b6f51 5232#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5233 netdev->dcbnl_ops = &dcbnl_ops;
5234#endif
5235
eacd73f7
YZ		 5236#ifdef IXGBE_FCOE
5237 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5238 if (hw->mac.ops.get_device_caps) {
5239 hw->mac.ops.get_device_caps(hw, &device_caps);
5240 if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5241 netdev->features |= NETIF_F_FCOE_CRC;
5242 netdev->features |= NETIF_F_FSO;
332d4a7d 5243 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
eacd73f7
YZ		 5244 } else {
5245 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5246 }
5247 }
5248 }
5249#endif /* IXGBE_FCOE */
9a799d71
AK		 5250 if (pci_using_dac)
5251 netdev->features |= NETIF_F_HIGHDMA;
5252
f8212f97
AD		 5253 if (adapter->flags & IXGBE_FLAG_RSC_ENABLED)
5254 netdev->features |= NETIF_F_LRO;
5255
9a799d71 5256 /* make sure the EEPROM is good */
c44ade9e 5257 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5258 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5259 err = -EIO;
5260 goto err_eeprom;
5261 }
5262
5263 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5264 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5265
c44ade9e
JB		 5266 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5267 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5268 err = -EIO;
5269 goto err_eeprom;
5270 }
5271
5272 init_timer(&adapter->watchdog_timer);
5273 adapter->watchdog_timer.function = &ixgbe_watchdog;
5274 adapter->watchdog_timer.data = (unsigned long)adapter;
5275
5276 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5277 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5278
021230d4
AV		 5279 err = ixgbe_init_interrupt_scheme(adapter);
5280 if (err)
5281 goto err_sw_init;
9a799d71 5282
e8e26350
PW		 5283 switch (pdev->device) {
5284 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5285 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5286 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 5287 break;
5288 default:
5289 adapter->wol = 0;
5290 break;
5291 }
5292 device_init_wakeup(&adapter->pdev->dev, true);
5293 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5294
04f165ef
PW		 5295 /* pick up the PCI bus settings for reporting later */
5296 hw->mac.ops.get_bus_info(hw);
5297
9a799d71 5298 /* print bus type/speed/width info */
7c510e4b 5299 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5300 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5301 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5302 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5303 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5304 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5305 "Unknown"),
7c510e4b 5306 netdev->dev_addr);
c44ade9e 5307 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5308 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5309 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5310 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5311 (part_num >> 8), (part_num & 0xff));
5312 else
5313 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5314 hw->mac.type, hw->phy.type,
5315 (part_num >> 8), (part_num & 0xff));
9a799d71 5316
e8e26350 5317 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5318 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5319 "this card is not sufficient for optimal "
5320 "performance.\n");
0c254d86 5321 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5322 "PCI-Express slot is required.\n");
0c254d86
AK		 5323 }
5324
34b0368c
PWJ		 5325 /* save off EEPROM version number */
5326 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5327
9a799d71 5328 /* reset the hardware with the new settings */
c44ade9e
JB		 5329 hw->mac.ops.start_hw(hw);
5330
9a799d71
AK		 5331 strcpy(netdev->name, "eth%d");
5332 err = register_netdev(netdev);
5333 if (err)
5334 goto err_register;
5335
54386467
JB		 5336 /* carrier off reporting is important to ethtool even BEFORE open */
5337 netif_carrier_off(netdev);
5338
5dd2d332 5339#ifdef CONFIG_IXGBE_DCA
652f093f 5340 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 5341 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5342 /* always use CB2 mode, difference is masked
5343 * in the CB driver */
5344 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
5345 ixgbe_setup_dca(adapter);
5346 }
5347#endif
0365e6e4
PW		 5348 /* add san mac addr to netdev */
5349 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5350
5351 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5352 cards_found++;
5353 return 0;
5354
5355err_register:
5eba3699 5356 ixgbe_release_hw_control(adapter);
9a799d71 5357err_hw_init:
7a921c93 5358 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5359err_sw_init:
5360err_eeprom:
c4900be0
DS		 5361 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5362 del_timer_sync(&adapter->sfp_timer);
5363 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5364 cancel_work_sync(&adapter->multispeed_fiber_task);
5365 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5366 iounmap(hw->hw_addr);
5367err_ioremap:
5368 free_netdev(netdev);
5369err_alloc_etherdev:
9ce77666 5370 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5371 IORESOURCE_MEM));
9a799d71
AK		 5372err_pci_reg:
5373err_dma:
5374 pci_disable_device(pdev);
5375 return err;
5376}
5377
5378/**
5379 * ixgbe_remove - Device Removal Routine
5380 * @pdev: PCI device information struct
5381 *
5382 * ixgbe_remove is called by the PCI subsystem to alert the driver
5383 * that it should release a PCI device. The could be caused by a
5384 * Hot-Plug event, or because the driver is going to be removed from
5385 * memory.
5386 **/
5387static void __devexit ixgbe_remove(struct pci_dev *pdev)
5388{
5389 struct net_device *netdev = pci_get_drvdata(pdev);
5390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715 5391 int err;
9a799d71
AK		 5392
5393 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5394 /* clear the module not found bit to make sure the worker won't
5395 * reschedule
5396 */
5397 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5398 del_timer_sync(&adapter->watchdog_timer);
5399
c4900be0
DS		 5400 del_timer_sync(&adapter->sfp_timer);
5401 cancel_work_sync(&adapter->watchdog_task);
5402 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5403 cancel_work_sync(&adapter->multispeed_fiber_task);
5404 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5405 flush_scheduled_work();
5406
5dd2d332 5407#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5408 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5409 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5410 dca_remove_requester(&pdev->dev);
5411 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5412 }
5413
5414#endif
332d4a7d
YZ		 5415#ifdef IXGBE_FCOE
5416 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5417 ixgbe_cleanup_fcoe(adapter);
5418
5419#endif /* IXGBE_FCOE */
0365e6e4
PW		 5420
5421 /* remove the added san mac */
5422 ixgbe_del_sanmac_netdev(netdev);
5423
c4900be0
DS		 5424 if (netdev->reg_state == NETREG_REGISTERED)
5425 unregister_netdev(netdev);
9a799d71 5426
7a921c93 5427 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5428
021230d4 5429 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5430
5431 iounmap(adapter->hw.hw_addr);
9ce77666 5432 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5433 IORESOURCE_MEM));
9a799d71 5434
021230d4 5435 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5436
9a799d71
AK		 5437 free_netdev(netdev);
5438
6fabd715
PWJ		 5439 err = pci_disable_pcie_error_reporting(pdev);
5440 if (err)
5441 dev_err(&pdev->dev,
5442 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5443
9a799d71
AK		 5444 pci_disable_device(pdev);
5445}
5446
5447/**
5448 * ixgbe_io_error_detected - called when PCI error is detected
5449 * @pdev: Pointer to PCI device
5450 * @state: The current pci connection state
5451 *
5452 * This function is called after a PCI bus error affecting
5453 * this device has been detected.
5454 */
5455static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5456 pci_channel_state_t state)
9a799d71
AK		 5457{
5458 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5460
5461 netif_device_detach(netdev);
5462
3044b8d1
BL		 5463 if (state == pci_channel_io_perm_failure)
5464 return PCI_ERS_RESULT_DISCONNECT;
5465
9a799d71
AK		 5466 if (netif_running(netdev))
5467 ixgbe_down(adapter);
5468 pci_disable_device(pdev);
5469
b4617240 5470 /* Request a slot reset. */
9a799d71
AK		 5471 return PCI_ERS_RESULT_NEED_RESET;
5472}
5473
5474/**
5475 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5476 * @pdev: Pointer to PCI device
5477 *
5478 * Restart the card from scratch, as if from a cold-boot.
5479 */
5480static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5481{
5482 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5483 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5484 pci_ers_result_t result;
5485 int err;
9a799d71 5486
9ce77666 5487 if (pci_enable_device_mem(pdev)) {
9a799d71 5488 DPRINTK(PROBE, ERR,
b4617240 5489 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5490 result = PCI_ERS_RESULT_DISCONNECT;
5491 } else {
5492 pci_set_master(pdev);
5493 pci_restore_state(pdev);
9a799d71 5494
dd4d8ca6 5495 pci_wake_from_d3(pdev, false);
9a799d71 5496
6fabd715 5497 ixgbe_reset(adapter);
88512539 5498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5499 result = PCI_ERS_RESULT_RECOVERED;
5500 }
5501
5502 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5503 if (err) {
5504 dev_err(&pdev->dev,
5505 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5506 /* non-fatal, continue */
5507 }
9a799d71 5508
6fabd715 5509 return result;
9a799d71
AK		 5510}
5511
5512/**
5513 * ixgbe_io_resume - called when traffic can start flowing again.
5514 * @pdev: Pointer to PCI device
5515 *
5516 * This callback is called when the error recovery driver tells us that
5517 * its OK to resume normal operation.
5518 */
5519static void ixgbe_io_resume(struct pci_dev *pdev)
5520{
5521 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5522 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5523
5524 if (netif_running(netdev)) {
5525 if (ixgbe_up(adapter)) {
5526 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5527 return;
5528 }
5529 }
5530
5531 netif_device_attach(netdev);
9a799d71
AK		 5532}
5533
5534static struct pci_error_handlers ixgbe_err_handler = {
5535 .error_detected = ixgbe_io_error_detected,
5536 .slot_reset = ixgbe_io_slot_reset,
5537 .resume = ixgbe_io_resume,
5538};
5539
5540static struct pci_driver ixgbe_driver = {
5541 .name = ixgbe_driver_name,
5542 .id_table = ixgbe_pci_tbl,
5543 .probe = ixgbe_probe,
5544 .remove = __devexit_p(ixgbe_remove),
5545#ifdef CONFIG_PM
5546 .suspend = ixgbe_suspend,
5547 .resume = ixgbe_resume,
5548#endif
5549 .shutdown = ixgbe_shutdown,
5550 .err_handler = &ixgbe_err_handler
5551};
5552
5553/**
5554 * ixgbe_init_module - Driver Registration Routine
5555 *
5556 * ixgbe_init_module is the first routine called when the driver is
5557 * loaded. All it does is register with the PCI subsystem.
5558 **/
5559static int __init ixgbe_init_module(void)
5560{
5561 int ret;
5562 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5563 ixgbe_driver_string, ixgbe_driver_version);
5564
5565 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5566
5dd2d332 5567#ifdef CONFIG_IXGBE_DCA
bd0362dd 5568 dca_register_notify(&dca_notifier);
bd0362dd 5569#endif
5dd2d332 5570
9a799d71
AK		 5571 ret = pci_register_driver(&ixgbe_driver);
5572 return ret;
5573}
b4617240 5574
9a799d71
AK		 5575module_init(ixgbe_init_module);
5576
5577/**
5578 * ixgbe_exit_module - Driver Exit Cleanup Routine
5579 *
5580 * ixgbe_exit_module is called just before the driver is removed
5581 * from memory.
5582 **/
5583static void __exit ixgbe_exit_module(void)
5584{
5dd2d332 5585#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5586 dca_unregister_notify(&dca_notifier);
5587#endif
9a799d71
AK		 5588 pci_unregister_driver(&ixgbe_driver);
5589}
bd0362dd 5590
5dd2d332 5591#ifdef CONFIG_IXGBE_DCA
bd0362dd 5592static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 5593 void *p)
bd0362dd
JC		 5594{
5595 int ret_val;
5596
5597 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 5598 __ixgbe_notify_dca);
bd0362dd
JC		 5599
5600 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5601}
b453368d 5602
5dd2d332 5603#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 5604#ifdef DEBUG
5605/**
5606 * ixgbe_get_hw_dev_name - return device name string
5607 * used by hardware layer to print debugging information
5608 **/
5609char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5610{
5611 struct ixgbe_adapter *adapter = hw->back;
5612 return adapter->netdev->name;
5613}
bd0362dd 5614
b453368d 5615#endif
9a799d71
AK		 5616module_exit(ixgbe_exit_module);
5617
5618/* ixgbe_main.c */
Clone of davem's net-next-2.6 tree