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ixgbe: add 1g PHY support for 82599
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
9a799d71
AK		 33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
29c3a050
AK		 44enum {NETDEV_STATS, IXGBE_STATS};
45
9a799d71
AK		 46struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
29c3a050 48 int type;
9a799d71
AK		 49 int sizeof_stat;
50 int stat_offset;
51};
52
29c3a050
AK		 53#define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
57 sizeof(((struct net_device *)0)->m), \
58 offsetof(struct net_device, m)
59
9a799d71 60static struct ixgbe_stats ixgbe_gstrings_stats[] = {
2d86f139
AK		 61 {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)},
aad71918
BG		 65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
2d86f139
AK		 72 {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(stats.multicast)},
9a799d71
AK		 77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
2d86f139
AK		 79 {"collisions", IXGBE_NETDEV_STAT(stats.collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)},
94b982b2
MC		 83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
2d86f139
AK		 87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)},
9a799d71
AK		 93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 105#ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112#endif /* IXGBE_FCOE */
9a799d71
AK		 113};
114
115#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 119#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 120#define IXGBE_PB_STATS_LEN ( \
9d2f4720 121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
9a799d71 131
da4dd0f7
PWJ		 132static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136};
137#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
9a799d71 139static int ixgbe_get_settings(struct net_device *netdev,
b4617240 140 struct ethtool_cmd *ecmd)
9a799d71
AK		 141{
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
9a799d71 146
735441fb
AV		 147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 149 ecmd->transceiver = XCVR_EXTERNAL;
74766013 150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 151 (hw->phy.multispeed_fiber)) {
735441fb 152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 153 SUPPORTED_Autoneg);
735441fb 154
74766013 155 ecmd->advertising = ADVERTISED_Autoneg;
735441fb
AV		 156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
735441fb 169
74766013
MC		 170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
1e336d0f
DS		 179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
46a72b35
MC		 188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
1e336d0f 195 }
735441fb
AV		 196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 199 ADVERTISED_FIBRE);
735441fb 200 ecmd->port = PORT_FIBRE;
c44ade9e 201 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 202 }
9a799d71 203
3b8626ba
PW		 204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
cb836a97
DS		 237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
3b8626ba
PW		 244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
c44ade9e 261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 264 SPEED_10000 : SPEED_1000;
9a799d71
AK		 265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
9a799d71
AK		 271 return 0;
272}
273
274static int ixgbe_set_settings(struct net_device *netdev,
b4617240 275 struct ethtool_cmd *ecmd)
9a799d71
AK		 276{
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 278 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 279 u32 advertised, old;
74766013 280 s32 err = 0;
9a799d71 281
74766013 282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 283 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
74766013 299 return err;
0befdb3e 300 /* this sets the link speed and restarts auto-neg */
74766013 301 hw->mac.autotry_restart = true;
8620a103 302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 303 if (err) {
849c4542 304 e_info("setup link failed with code %d\n", err);
8620a103 305 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 306 }
74766013
MC		 307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
74766013
MC		 311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
9a799d71
AK		 313 }
314
74766013 315 return err;
9a799d71
AK		 316}
317
318static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 319 struct ethtool_pauseparam *pause)
9a799d71
AK		 320{
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
71fd570b
DS		 324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
9a799d71 334
8756924c
PWJ		 335#ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341#endif
0ecc061d 342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 343 pause->rx_pause = 1;
0ecc061d 344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 345 pause->tx_pause = 1;
0ecc061d 346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350}
351
352static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
620fa036 357 struct ixgbe_fc_info fc;
9a799d71 358
264857b8
PWJ		 359#ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365#endif
620fa036
MC		 366
367 fc = hw->fc;
368
71fd570b 369 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 370 fc.disable_fc_autoneg = true;
71fd570b 371 else
620fa036 372 fc.disable_fc_autoneg = false;
71fd570b 373
1c4f0ef8 374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 375 fc.requested_mode = ixgbe_fc_full;
9a799d71 376 else if (pause->rx_pause && !pause->tx_pause)
620fa036 377 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 378 else if (!pause->rx_pause && pause->tx_pause)
620fa036 379 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 380 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 381 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 382 else
383 return -EINVAL;
9a799d71 384
264857b8 385#ifdef CONFIG_DCB
620fa036 386 adapter->last_lfc_mode = fc.requested_mode;
264857b8 387#endif
620fa036
MC		 388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
9a799d71
AK		 397
398 return 0;
399}
400
401static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402{
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
404 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
405}
406
407static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408{
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
d4f80882
AV		 415 if (netif_running(netdev))
416 ixgbe_reinit_locked(adapter);
417 else
9a799d71 418 ixgbe_reset(adapter);
9a799d71
AK		 419
420 return 0;
421}
422
423static u32 ixgbe_get_tx_csum(struct net_device *netdev)
424{
22f32b7a 425 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 426}
427
428static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
429{
45a5ead0
JB		 430 struct ixgbe_adapter *adapter = netdev_priv(netdev);
431
432 if (data) {
22f32b7a 433 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 434 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
435 netdev->features |= NETIF_F_SCTP_CSUM;
436 } else {
3d3d6d3c 437 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 438 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
439 netdev->features &= ~NETIF_F_SCTP_CSUM;
440 }
9a799d71
AK		 441
442 return 0;
443}
444
445static int ixgbe_set_tso(struct net_device *netdev, u32 data)
446{
9a799d71
AK		 447 if (data) {
448 netdev->features |= NETIF_F_TSO;
449 netdev->features |= NETIF_F_TSO6;
450 } else {
451 netdev->features &= ~NETIF_F_TSO;
452 netdev->features &= ~NETIF_F_TSO6;
453 }
454 return 0;
455}
456
457static u32 ixgbe_get_msglevel(struct net_device *netdev)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 return adapter->msg_enable;
461}
462
463static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
464{
465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
466 adapter->msg_enable = data;
467}
468
469static int ixgbe_get_regs_len(struct net_device *netdev)
470{
471#define IXGBE_REGS_LEN 1128
472 return IXGBE_REGS_LEN * sizeof(u32);
473}
474
475#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
476
477static void ixgbe_get_regs(struct net_device *netdev,
b4617240 478 struct ethtool_regs *regs, void *p)
9a799d71
AK		 479{
480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
481 struct ixgbe_hw *hw = &adapter->hw;
482 u32 *regs_buff = p;
483 u8 i;
484
485 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
486
487 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
488
489 /* General Registers */
490 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
491 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
492 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
493 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
494 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
495 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
496 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
497 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
498
499 /* NVM Register */
500 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
501 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
502 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
503 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
504 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
505 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
506 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
507 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
508 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
509 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
510
511 /* Interrupt */
98c00a1c
JB		 512 /* don't read EICR because it can clear interrupt causes, instead
513 * read EICS which is a shadow but doesn't clear EICR */
514 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 515 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
516 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
517 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
518 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
519 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
520 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
521 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
522 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
523 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 524 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 525 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
526
527 /* Flow Control */
528 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
529 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
530 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
531 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
532 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
533 for (i = 0; i < 8; i++)
534 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
535 for (i = 0; i < 8; i++)
536 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
537 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
538 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
539
540 /* Receive DMA */
541 for (i = 0; i < 64; i++)
542 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
543 for (i = 0; i < 64; i++)
544 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
545 for (i = 0; i < 64; i++)
546 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
547 for (i = 0; i < 64; i++)
548 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
549 for (i = 0; i < 64; i++)
550 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
551 for (i = 0; i < 64; i++)
552 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
553 for (i = 0; i < 16; i++)
554 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
555 for (i = 0; i < 16; i++)
556 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
557 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
558 for (i = 0; i < 8; i++)
559 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
560 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
561 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
562
563 /* Receive */
564 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
565 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
566 for (i = 0; i < 16; i++)
567 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
568 for (i = 0; i < 16; i++)
569 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 570 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 571 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
572 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
573 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
574 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
575 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
576 for (i = 0; i < 8; i++)
577 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
578 for (i = 0; i < 8; i++)
579 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
580 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
581
582 /* Transmit */
583 for (i = 0; i < 32; i++)
584 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
585 for (i = 0; i < 32; i++)
586 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
587 for (i = 0; i < 32; i++)
588 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
589 for (i = 0; i < 32; i++)
590 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
593 for (i = 0; i < 32; i++)
594 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
595 for (i = 0; i < 32; i++)
596 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
597 for (i = 0; i < 32; i++)
598 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
599 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
600 for (i = 0; i < 16; i++)
601 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
602 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
603 for (i = 0; i < 8; i++)
604 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
605 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
606
607 /* Wake Up */
608 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
609 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
610 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
611 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
612 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
613 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
614 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
615 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 616 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 617
9a799d71
AK		 618 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
619 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
620 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
621 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
622 for (i = 0; i < 8; i++)
623 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
624 for (i = 0; i < 8; i++)
625 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
626 for (i = 0; i < 8; i++)
627 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
634
635 /* Statistics */
636 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
637 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
638 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
639 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
640 for (i = 0; i < 8; i++)
641 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
642 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
643 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
644 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
645 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
646 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
647 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
648 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
649 for (i = 0; i < 8; i++)
650 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
651 for (i = 0; i < 8; i++)
652 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
653 for (i = 0; i < 8; i++)
654 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
655 for (i = 0; i < 8; i++)
656 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
657 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
658 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
659 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
660 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
661 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
662 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
663 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
664 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
665 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
666 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
667 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
668 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
669 for (i = 0; i < 8; i++)
670 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
671 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
672 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
673 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
674 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
675 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
676 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
677 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
678 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
679 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
680 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
681 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
682 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
683 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
684 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
685 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
686 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
687 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
688 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
689 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
690 for (i = 0; i < 16; i++)
691 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
692 for (i = 0; i < 16; i++)
693 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
694 for (i = 0; i < 16; i++)
695 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
696 for (i = 0; i < 16; i++)
697 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
698
699 /* MAC */
700 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
701 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
702 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
703 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
704 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
705 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
706 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
707 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
708 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
709 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
710 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
711 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
712 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
713 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
714 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
715 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
716 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
717 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
718 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
719 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
720 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
721 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
722 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
723 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
724 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
725 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
726 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
728 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
729 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
730 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
731 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
732 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
733
734 /* Diagnostic */
735 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
736 for (i = 0; i < 8; i++)
98c00a1c 737 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 738 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 739 for (i = 0; i < 4; i++)
740 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 741 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
742 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
743 for (i = 0; i < 8; i++)
98c00a1c 744 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 745 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 746 for (i = 0; i < 4; i++)
747 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 748 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
749 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
750 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
751 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
752 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
753 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
754 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
755 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
756 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
757 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
758 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
759 for (i = 0; i < 8; i++)
98c00a1c 760 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 761 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
762 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
763 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
764 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
765 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
766 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
767 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
768 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
769 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
770}
771
772static int ixgbe_get_eeprom_len(struct net_device *netdev)
773{
774 struct ixgbe_adapter *adapter = netdev_priv(netdev);
775 return adapter->hw.eeprom.word_size * 2;
776}
777
778static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 779 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 780{
781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
782 struct ixgbe_hw *hw = &adapter->hw;
783 u16 *eeprom_buff;
784 int first_word, last_word, eeprom_len;
785 int ret_val = 0;
786 u16 i;
787
788 if (eeprom->len == 0)
789 return -EINVAL;
790
791 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
792
793 first_word = eeprom->offset >> 1;
794 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
795 eeprom_len = last_word - first_word + 1;
796
797 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
798 if (!eeprom_buff)
799 return -ENOMEM;
800
801 for (i = 0; i < eeprom_len; i++) {
c44ade9e 802 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 803 &eeprom_buff[i])))
9a799d71
AK		 804 break;
805 }
806
807 /* Device's eeprom is always little-endian, word addressable */
808 for (i = 0; i < eeprom_len; i++)
809 le16_to_cpus(&eeprom_buff[i]);
810
811 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
812 kfree(eeprom_buff);
813
814 return ret_val;
815}
816
817static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 818 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 819{
820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 821 char firmware_version[32];
9a799d71
AK		 822
823 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
824 strncpy(drvinfo->version, ixgbe_driver_version, 32);
34b0368c
PWJ		 825
826 sprintf(firmware_version, "%d.%d-%d",
827 (adapter->eeprom_version & 0xF000) >> 12,
828 (adapter->eeprom_version & 0x0FF0) >> 4,
829 adapter->eeprom_version & 0x000F);
830
831 strncpy(drvinfo->fw_version, firmware_version, 32);
9a799d71
AK		 832 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
833 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 834 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 835 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
836}
837
838static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 839 struct ethtool_ringparam *ring)
9a799d71
AK		 840{
841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 842 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
843 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 844
845 ring->rx_max_pending = IXGBE_MAX_RXD;
846 ring->tx_max_pending = IXGBE_MAX_TXD;
847 ring->rx_mini_max_pending = 0;
848 ring->rx_jumbo_max_pending = 0;
849 ring->rx_pending = rx_ring->count;
850 ring->tx_pending = tx_ring->count;
851 ring->rx_mini_pending = 0;
852 ring->rx_jumbo_pending = 0;
853}
854
855static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 856 struct ethtool_ringparam *ring)
9a799d71
AK		 857{
858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 859 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 860 int i, err = 0;
c431f97e 861 u32 new_rx_count, new_tx_count;
f9ed8854 862 bool need_update = false;
9a799d71
AK		 863
864 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
865 return -EINVAL;
866
867 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
868 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
869 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
870
871 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
872 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
873 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
874
4a0b9ca0
PW		 875 if ((new_tx_count == adapter->tx_ring[0]->count) &&
876 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 877 /* nothing to do */
878 return 0;
879 }
880
d4f80882
AV		 881 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
882 msleep(1);
883
759884b4
AD		 884 if (!netif_running(adapter->netdev)) {
885 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 886 adapter->tx_ring[i]->count = new_tx_count;
759884b4 887 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 888 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 889 adapter->tx_ring_count = new_tx_count;
890 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 891 goto clear_reset;
759884b4
AD		 892 }
893
4a0b9ca0 894 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 895 if (!temp_tx_ring) {
896 err = -ENOMEM;
4a0b9ca0 897 goto clear_reset;
f9ed8854
MC		 898 }
899
900 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 901 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 902 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
903 sizeof(struct ixgbe_ring));
f9ed8854
MC		 904 temp_tx_ring[i].count = new_tx_count;
905 err = ixgbe_setup_tx_resources(adapter,
906 &temp_tx_ring[i]);
9a799d71 907 if (err) {
c431f97e
JB		 908 while (i) {
909 i--;
b4617240 910 ixgbe_free_tx_resources(adapter,
4a0b9ca0 911 &temp_tx_ring[i]);
c431f97e 912 }
4a0b9ca0 913 goto clear_reset;
9a799d71 914 }
9a799d71 915 }
f9ed8854 916 need_update = true;
9a799d71
AK		 917 }
918
4a0b9ca0
PW		 919 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
920 if (!temp_rx_ring) {
f9ed8854
MC		 921 err = -ENOMEM;
922 goto err_setup;
d3fa4721 923 }
9a799d71 924
f9ed8854 925 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 926 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 927 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
928 sizeof(struct ixgbe_ring));
f9ed8854
MC		 929 temp_rx_ring[i].count = new_rx_count;
930 err = ixgbe_setup_rx_resources(adapter,
931 &temp_rx_ring[i]);
9a799d71 932 if (err) {
c431f97e
JB		 933 while (i) {
934 i--;
b4617240 935 ixgbe_free_rx_resources(adapter,
f9ed8854 936 &temp_rx_ring[i]);
c431f97e 937 }
9a799d71
AK		 938 goto err_setup;
939 }
9a799d71 940 }
f9ed8854
MC		 941 need_update = true;
942 }
943
944 /* if rings need to be updated, here's the place to do it in one shot */
945 if (need_update) {
759884b4 946 ixgbe_down(adapter);
f9ed8854
MC		 947
948 /* tx */
949 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0
PW		 950 for (i = 0; i < adapter->num_tx_queues; i++) {
951 ixgbe_free_tx_resources(adapter,
952 adapter->tx_ring[i]);
953 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
954 sizeof(struct ixgbe_ring));
955 }
f9ed8854
MC		 956 adapter->tx_ring_count = new_tx_count;
957 }
958
959 /* rx */
960 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0
PW		 961 for (i = 0; i < adapter->num_rx_queues; i++) {
962 ixgbe_free_rx_resources(adapter,
963 adapter->rx_ring[i]);
964 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
965 sizeof(struct ixgbe_ring));
966 }
f9ed8854
MC		 967 adapter->rx_ring_count = new_rx_count;
968 }
f9ed8854 969 ixgbe_up(adapter);
759884b4 970 }
4a0b9ca0
PW		 971
972 vfree(temp_rx_ring);
f9ed8854 973err_setup:
4a0b9ca0
PW		 974 vfree(temp_tx_ring);
975clear_reset:
d4f80882 976 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 977 return err;
978}
979
b9f2c044 980static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 981{
b9f2c044 982 switch (sset) {
da4dd0f7
PWJ		 983 case ETH_SS_TEST:
984 return IXGBE_TEST_LEN;
b9f2c044
JG		 985 case ETH_SS_STATS:
986 return IXGBE_STATS_LEN;
9a713e7c
PW		 987 case ETH_SS_NTUPLE_FILTERS:
988 return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
989 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY);
b9f2c044
JG		 990 default:
991 return -EOPNOTSUPP;
992 }
9a799d71
AK		 993}
994
995static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 996 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 997{
998 struct ixgbe_adapter *adapter = netdev_priv(netdev);
999 u64 *queue_stat;
1000 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
1001 int j, k;
1002 int i;
29c3a050 1003 char *p = NULL;
9a799d71
AK		 1004
1005 ixgbe_update_stats(adapter);
60d51134 1006 dev_get_stats(netdev);
9a799d71 1007 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1008 switch (ixgbe_gstrings_stats[i].type) {
1009 case NETDEV_STATS:
1010 p = (char *) netdev +
1011 ixgbe_gstrings_stats[i].stat_offset;
1012 break;
1013 case IXGBE_STATS:
1014 p = (char *) adapter +
1015 ixgbe_gstrings_stats[i].stat_offset;
1016 break;
1017 }
1018
9a799d71 1019 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1020 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1021 }
1022 for (j = 0; j < adapter->num_tx_queues; j++) {
4a0b9ca0 1023 queue_stat = (u64 *)&adapter->tx_ring[j]->stats;
9a799d71
AK		 1024 for (k = 0; k < stat_count; k++)
1025 data[i + k] = queue_stat[k];
1026 i += k;
1027 }
1028 for (j = 0; j < adapter->num_rx_queues; j++) {
4a0b9ca0 1029 queue_stat = (u64 *)&adapter->rx_ring[j]->stats;
9a799d71
AK		 1030 for (k = 0; k < stat_count; k++)
1031 data[i + k] = queue_stat[k];
1032 i += k;
1033 }
2f90b865
AD		 1034 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1035 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1036 data[i++] = adapter->stats.pxontxc[j];
1037 data[i++] = adapter->stats.pxofftxc[j];
1038 }
1039 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1040 data[i++] = adapter->stats.pxonrxc[j];
1041 data[i++] = adapter->stats.pxoffrxc[j];
1042 }
1043 }
9a799d71
AK		 1044}
1045
1046static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1047 u8 *data)
9a799d71
AK		 1048{
1049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1050 char *p = (char *)data;
9a799d71
AK		 1051 int i;
1052
1053 switch (stringset) {
da4dd0f7
PWJ		 1054 case ETH_SS_TEST:
1055 memcpy(data, *ixgbe_gstrings_test,
1056 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1057 break;
9a799d71
AK		 1058 case ETH_SS_STATS:
1059 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1060 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1061 ETH_GSTRING_LEN);
1062 p += ETH_GSTRING_LEN;
1063 }
1064 for (i = 0; i < adapter->num_tx_queues; i++) {
1065 sprintf(p, "tx_queue_%u_packets", i);
1066 p += ETH_GSTRING_LEN;
1067 sprintf(p, "tx_queue_%u_bytes", i);
1068 p += ETH_GSTRING_LEN;
1069 }
1070 for (i = 0; i < adapter->num_rx_queues; i++) {
1071 sprintf(p, "rx_queue_%u_packets", i);
1072 p += ETH_GSTRING_LEN;
1073 sprintf(p, "rx_queue_%u_bytes", i);
1074 p += ETH_GSTRING_LEN;
1075 }
2f90b865
AD		 1076 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1077 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1078 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1079 p += ETH_GSTRING_LEN;
1080 sprintf(p, "tx_pb_%u_pxoff", i);
1081 p += ETH_GSTRING_LEN;
2f90b865
AD		 1082 }
1083 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1084 sprintf(p, "rx_pb_%u_pxon", i);
1085 p += ETH_GSTRING_LEN;
1086 sprintf(p, "rx_pb_%u_pxoff", i);
1087 p += ETH_GSTRING_LEN;
2f90b865
AD		 1088 }
1089 }
b4617240 1090 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1091 break;
1092 }
1093}
1094
da4dd0f7
PWJ		 1095static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1096{
1097 struct ixgbe_hw *hw = &adapter->hw;
1098 bool link_up;
1099 u32 link_speed = 0;
1100 *data = 0;
1101
1102 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1103 if (link_up)
1104 return *data;
1105 else
1106 *data = 1;
1107 return *data;
1108}
1109
1110/* ethtool register test data */
1111struct ixgbe_reg_test {
1112 u16 reg;
1113 u8 array_len;
1114 u8 test_type;
1115 u32 mask;
1116 u32 write;
1117};
1118
1119/* In the hardware, registers are laid out either singly, in arrays
1120 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1121 * most tests take place on arrays or single registers (handled
1122 * as a single-element array) and special-case the tables.
1123 * Table tests are always pattern tests.
1124 *
1125 * We also make provision for some required setup steps by specifying
1126 * registers to be written without any read-back testing.
1127 */
1128
1129#define PATTERN_TEST 1
1130#define SET_READ_TEST 2
1131#define WRITE_NO_TEST 3
1132#define TABLE32_TEST 4
1133#define TABLE64_TEST_LO 5
1134#define TABLE64_TEST_HI 6
1135
1136/* default 82599 register test */
1137static struct ixgbe_reg_test reg_test_82599[] = {
1138 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1139 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1140 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1141 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1142 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1143 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1144 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1145 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1146 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1147 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1148 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1149 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1150 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1151 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1152 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1153 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1154 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1155 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1156 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { 0, 0, 0, 0 }
1158};
1159
1160/* default 82598 register test */
1161static struct ixgbe_reg_test reg_test_82598[] = {
1162 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1163 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1164 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1165 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1166 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1167 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1168 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1169 /* Enable all four RX queues before testing. */
1170 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1171 /* RDH is read-only for 82598, only test RDT. */
1172 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1173 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1174 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1175 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1176 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1177 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1178 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1180 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1181 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1182 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1183 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1184 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1185 { 0, 0, 0, 0 }
1186};
1187
1188#define REG_PATTERN_TEST(R, M, W) \
1189{ \
1190 u32 pat, val, before; \
1191 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1192 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1193 before = readl(adapter->hw.hw_addr + R); \
1194 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1195 val = readl(adapter->hw.hw_addr + R); \
1196 if (val != (_test[pat] & W & M)) { \
849c4542
ET		 1197 e_err("pattern test reg %04X failed: got " \
1198 "0x%08X expected 0x%08X\n", \
1199 R, val, (_test[pat] & W & M)); \
da4dd0f7
PWJ		 1200 *data = R; \
1201 writel(before, adapter->hw.hw_addr + R); \
1202 return 1; \
1203 } \
1204 writel(before, adapter->hw.hw_addr + R); \
1205 } \
1206}
1207
1208#define REG_SET_AND_CHECK(R, M, W) \
1209{ \
1210 u32 val, before; \
1211 before = readl(adapter->hw.hw_addr + R); \
1212 writel((W & M), (adapter->hw.hw_addr + R)); \
1213 val = readl(adapter->hw.hw_addr + R); \
1214 if ((W & M) != (val & M)) { \
849c4542
ET		 1215 e_err("set/check reg %04X test failed: got 0x%08X " \
1216 "expected 0x%08X\n", R, (val & M), (W & M)); \
da4dd0f7
PWJ		 1217 *data = R; \
1218 writel(before, (adapter->hw.hw_addr + R)); \
1219 return 1; \
1220 } \
1221 writel(before, (adapter->hw.hw_addr + R)); \
1222}
1223
1224static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1225{
1226 struct ixgbe_reg_test *test;
1227 u32 value, before, after;
1228 u32 i, toggle;
1229
1230 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1231 toggle = 0x7FFFF30F;
1232 test = reg_test_82599;
1233 } else {
1234 toggle = 0x7FFFF3FF;
1235 test = reg_test_82598;
1236 }
1237
1238 /*
1239 * Because the status register is such a special case,
1240 * we handle it separately from the rest of the register
1241 * tests. Some bits are read-only, some toggle, and some
1242 * are writeable on newer MACs.
1243 */
1244 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1245 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1246 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1247 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1248 if (value != after) {
849c4542
ET		 1249 e_err("failed STATUS register test got: 0x%08X expected: "
1250 "0x%08X\n", after, value);
da4dd0f7
PWJ		 1251 *data = 1;
1252 return 1;
1253 }
1254 /* restore previous status */
1255 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1256
1257 /*
1258 * Perform the remainder of the register test, looping through
1259 * the test table until we either fail or reach the null entry.
1260 */
1261 while (test->reg) {
1262 for (i = 0; i < test->array_len; i++) {
1263 switch (test->test_type) {
1264 case PATTERN_TEST:
1265 REG_PATTERN_TEST(test->reg + (i * 0x40),
1266 test->mask,
1267 test->write);
1268 break;
1269 case SET_READ_TEST:
1270 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1271 test->mask,
1272 test->write);
1273 break;
1274 case WRITE_NO_TEST:
1275 writel(test->write,
1276 (adapter->hw.hw_addr + test->reg)
1277 + (i * 0x40));
1278 break;
1279 case TABLE32_TEST:
1280 REG_PATTERN_TEST(test->reg + (i * 4),
1281 test->mask,
1282 test->write);
1283 break;
1284 case TABLE64_TEST_LO:
1285 REG_PATTERN_TEST(test->reg + (i * 8),
1286 test->mask,
1287 test->write);
1288 break;
1289 case TABLE64_TEST_HI:
1290 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1291 test->mask,
1292 test->write);
1293 break;
1294 }
1295 }
1296 test++;
1297 }
1298
1299 *data = 0;
1300 return 0;
1301}
1302
1303static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1304{
1305 struct ixgbe_hw *hw = &adapter->hw;
1306 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1307 *data = 1;
1308 else
1309 *data = 0;
1310 return *data;
1311}
1312
1313static irqreturn_t ixgbe_test_intr(int irq, void *data)
1314{
1315 struct net_device *netdev = (struct net_device *) data;
1316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1317
1318 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1319
1320 return IRQ_HANDLED;
1321}
1322
1323static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1324{
1325 struct net_device *netdev = adapter->netdev;
1326 u32 mask, i = 0, shared_int = true;
1327 u32 irq = adapter->pdev->irq;
1328
1329 *data = 0;
1330
1331 /* Hook up test interrupt handler just for this test */
1332 if (adapter->msix_entries) {
1333 /* NOTE: we don't test MSI-X interrupts here, yet */
1334 return 0;
1335 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1336 shared_int = false;
a0607fd3 1337 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1338 netdev)) {
1339 *data = 1;
1340 return -1;
1341 }
a0607fd3 1342 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1343 netdev->name, netdev)) {
1344 shared_int = false;
a0607fd3 1345 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1346 netdev->name, netdev)) {
1347 *data = 1;
1348 return -1;
1349 }
849c4542
ET		 1350 e_info("testing %s interrupt\n", shared_int ?
1351 "shared" : "unshared");
da4dd0f7
PWJ		 1352
1353 /* Disable all the interrupts */
1354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1355 msleep(10);
1356
1357 /* Test each interrupt */
1358 for (; i < 10; i++) {
1359 /* Interrupt to test */
1360 mask = 1 << i;
1361
1362 if (!shared_int) {
1363 /*
1364 * Disable the interrupts to be reported in
1365 * the cause register and then force the same
1366 * interrupt and see if one gets posted. If
1367 * an interrupt was posted to the bus, the
1368 * test failed.
1369 */
1370 adapter->test_icr = 0;
1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1372 ~mask & 0x00007FFF);
1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1374 ~mask & 0x00007FFF);
1375 msleep(10);
1376
1377 if (adapter->test_icr & mask) {
1378 *data = 3;
1379 break;
1380 }
1381 }
1382
1383 /*
1384 * Enable the interrupt to be reported in the cause
1385 * register and then force the same interrupt and see
1386 * if one gets posted. If an interrupt was not posted
1387 * to the bus, the test failed.
1388 */
1389 adapter->test_icr = 0;
1390 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1392 msleep(10);
1393
1394 if (!(adapter->test_icr &mask)) {
1395 *data = 4;
1396 break;
1397 }
1398
1399 if (!shared_int) {
1400 /*
1401 * Disable the other interrupts to be reported in
1402 * the cause register and then force the other
1403 * interrupts and see if any get posted. If
1404 * an interrupt was posted to the bus, the
1405 * test failed.
1406 */
1407 adapter->test_icr = 0;
1408 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1409 ~mask & 0x00007FFF);
1410 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1411 ~mask & 0x00007FFF);
1412 msleep(10);
1413
1414 if (adapter->test_icr) {
1415 *data = 5;
1416 break;
1417 }
1418 }
1419 }
1420
1421 /* Disable all the interrupts */
1422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1423 msleep(10);
1424
1425 /* Unhook test interrupt handler */
1426 free_irq(irq, netdev);
1427
1428 return *data;
1429}
1430
1431static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1432{
1433 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1434 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1435 struct ixgbe_hw *hw = &adapter->hw;
1436 struct pci_dev *pdev = adapter->pdev;
1437 u32 reg_ctl;
1438 int i;
1439
1440 /* shut down the DMA engines now so they can be reinitialized later */
1441
1442 /* first Rx */
1443 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1444 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1445 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1446 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1447 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1448 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1449
1450 /* now Tx */
1451 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1452 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1453 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1454 if (hw->mac.type == ixgbe_mac_82599EB) {
1455 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1456 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1457 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1458 }
1459
1460 ixgbe_reset(adapter);
1461
1462 if (tx_ring->desc && tx_ring->tx_buffer_info) {
1463 for (i = 0; i < tx_ring->count; i++) {
1464 struct ixgbe_tx_buffer *buf =
1465 &(tx_ring->tx_buffer_info[i]);
1466 if (buf->dma)
1b507730
NN		 1467 dma_unmap_single(&pdev->dev, buf->dma,
1468 buf->length, DMA_TO_DEVICE);
da4dd0f7
PWJ		 1469 if (buf->skb)
1470 dev_kfree_skb(buf->skb);
1471 }
1472 }
1473
1474 if (rx_ring->desc && rx_ring->rx_buffer_info) {
1475 for (i = 0; i < rx_ring->count; i++) {
1476 struct ixgbe_rx_buffer *buf =
1477 &(rx_ring->rx_buffer_info[i]);
1478 if (buf->dma)
1b507730 1479 dma_unmap_single(&pdev->dev, buf->dma,
da4dd0f7 1480 IXGBE_RXBUFFER_2048,
1b507730 1481 DMA_FROM_DEVICE);
da4dd0f7
PWJ		 1482 if (buf->skb)
1483 dev_kfree_skb(buf->skb);
1484 }
1485 }
1486
1487 if (tx_ring->desc) {
1b507730
NN		 1488 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
1489 tx_ring->dma);
da4dd0f7
PWJ		 1490 tx_ring->desc = NULL;
1491 }
1492 if (rx_ring->desc) {
1b507730
NN		 1493 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
1494 rx_ring->dma);
da4dd0f7
PWJ		 1495 rx_ring->desc = NULL;
1496 }
1497
1498 kfree(tx_ring->tx_buffer_info);
1499 tx_ring->tx_buffer_info = NULL;
1500 kfree(rx_ring->rx_buffer_info);
1501 rx_ring->rx_buffer_info = NULL;
da4dd0f7
PWJ		 1502}
1503
1504static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1505{
1506 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1507 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1508 struct pci_dev *pdev = adapter->pdev;
1509 u32 rctl, reg_data;
1510 int i, ret_val;
1511
1512 /* Setup Tx descriptor ring and Tx buffers */
1513
1514 if (!tx_ring->count)
1515 tx_ring->count = IXGBE_DEFAULT_TXD;
1516
1517 tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1518 sizeof(struct ixgbe_tx_buffer),
1519 GFP_KERNEL);
1520 if (!(tx_ring->tx_buffer_info)) {
1521 ret_val = 1;
1522 goto err_nomem;
1523 }
1524
f4ec443b 1525 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
da4dd0f7 1526 tx_ring->size = ALIGN(tx_ring->size, 4096);
1b507730
NN		 1527 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
1528 &tx_ring->dma, GFP_KERNEL);
1529 if (!(tx_ring->desc)) {
da4dd0f7
PWJ		 1530 ret_val = 2;
1531 goto err_nomem;
1532 }
1533 tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1534
1535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1536 ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1538 ((u64) tx_ring->dma >> 32));
1539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
f4ec443b 1540 tx_ring->count * sizeof(union ixgbe_adv_tx_desc));
da4dd0f7
PWJ		 1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1543
1544 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1545 reg_data |= IXGBE_HLREG0_TXPADEN;
1546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1547
1548 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1549 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1550 reg_data |= IXGBE_DMATXCTL_TE;
1551 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1552 }
1553 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1554 reg_data |= IXGBE_TXDCTL_ENABLE;
1555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1556
1557 for (i = 0; i < tx_ring->count; i++) {
f4ec443b 1558 union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
da4dd0f7
PWJ		 1559 struct sk_buff *skb;
1560 unsigned int size = 1024;
1561
1562 skb = alloc_skb(size, GFP_KERNEL);
1563 if (!skb) {
1564 ret_val = 3;
1565 goto err_nomem;
1566 }
1567 skb_put(skb, size);
1568 tx_ring->tx_buffer_info[i].skb = skb;
1569 tx_ring->tx_buffer_info[i].length = skb->len;
1570 tx_ring->tx_buffer_info[i].dma =
1b507730
NN		 1571 dma_map_single(&pdev->dev, skb->data, skb->len,
1572 DMA_TO_DEVICE);
f4ec443b
PWJ		 1573 desc->read.buffer_addr =
1574 cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1575 desc->read.cmd_type_len = cpu_to_le32(skb->len);
1576 desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1577 IXGBE_TXD_CMD_IFCS |
1578 IXGBE_TXD_CMD_RS);
1579 desc->read.olinfo_status = 0;
1580 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1581 desc->read.olinfo_status |=
1582 (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT);
1583
da4dd0f7
PWJ		 1584 }
1585
1586 /* Setup Rx Descriptor ring and Rx buffers */
1587
1588 if (!rx_ring->count)
1589 rx_ring->count = IXGBE_DEFAULT_RXD;
1590
1591 rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1592 sizeof(struct ixgbe_rx_buffer),
1593 GFP_KERNEL);
1594 if (!(rx_ring->rx_buffer_info)) {
1595 ret_val = 4;
1596 goto err_nomem;
1597 }
1598
f4ec443b 1599 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
da4dd0f7 1600 rx_ring->size = ALIGN(rx_ring->size, 4096);
1b507730
NN		 1601 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
1602 &rx_ring->dma, GFP_KERNEL);
1603 if (!(rx_ring->desc)) {
da4dd0f7
PWJ		 1604 ret_val = 5;
1605 goto err_nomem;
1606 }
1607 rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1608
1609 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1611 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1612 ((u64)rx_ring->dma & 0xFFFFFFFF));
1613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1614 ((u64) rx_ring->dma >> 32));
1615 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1618
1619 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1620 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1621 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1622
1623 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1624 reg_data &= ~IXGBE_HLREG0_LPBK;
1625 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1626
1627 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1628#define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum
1629 Threshold Size mask */
1630 reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1632
1633 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1634#define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */
1635 reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1636 reg_data |= adapter->hw.mac.mc_filter_type;
1637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1638
1639 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1640 reg_data |= IXGBE_RXDCTL_ENABLE;
1641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1642 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4a0b9ca0 1643 int j = adapter->rx_ring[0]->reg_idx;
da4dd0f7
PWJ		 1644 u32 k;
1645 for (k = 0; k < 10; k++) {
1646 if (IXGBE_READ_REG(&adapter->hw,
1647 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1648 break;
1649 else
1650 msleep(1);
1651 }
1652 }
1653
1654 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1655 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1656
1657 for (i = 0; i < rx_ring->count; i++) {
f4ec443b
PWJ		 1658 union ixgbe_adv_rx_desc *rx_desc =
1659 IXGBE_RX_DESC_ADV(*rx_ring, i);
da4dd0f7
PWJ		 1660 struct sk_buff *skb;
1661
1662 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1663 if (!skb) {
1664 ret_val = 6;
1665 goto err_nomem;
1666 }
1667 skb_reserve(skb, NET_IP_ALIGN);
1668 rx_ring->rx_buffer_info[i].skb = skb;
1669 rx_ring->rx_buffer_info[i].dma =
1b507730
NN		 1670 dma_map_single(&pdev->dev, skb->data,
1671 IXGBE_RXBUFFER_2048, DMA_FROM_DEVICE);
f4ec443b 1672 rx_desc->read.pkt_addr =
da4dd0f7
PWJ		 1673 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1674 memset(skb->data, 0x00, skb->len);
1675 }
1676
1677 return 0;
1678
1679err_nomem:
1680 ixgbe_free_desc_rings(adapter);
1681 return ret_val;
1682}
1683
1684static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1685{
1686 struct ixgbe_hw *hw = &adapter->hw;
1687 u32 reg_data;
1688
1689 /* right now we only support MAC loopback in the driver */
1690
1691 /* Setup MAC loopback */
1692 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1693 reg_data |= IXGBE_HLREG0_LPBK;
1694 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1695
1696 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1697 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1698 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1700
1701 /* Disable Atlas Tx lanes; re-enabled in reset path */
1702 if (hw->mac.type == ixgbe_mac_82598EB) {
1703 u8 atlas;
1704
1705 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1706 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1707 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1708
1709 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1710 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1711 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1712
1713 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1714 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1715 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1716
1717 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1718 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1719 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1720 }
1721
1722 return 0;
1723}
1724
1725static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1726{
1727 u32 reg_data;
1728
1729 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1730 reg_data &= ~IXGBE_HLREG0_LPBK;
1731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1732}
1733
1734static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1735 unsigned int frame_size)
1736{
1737 memset(skb->data, 0xFF, frame_size);
1738 frame_size &= ~1;
1739 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1740 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1741 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1742}
1743
1744static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1745 unsigned int frame_size)
1746{
1747 frame_size &= ~1;
1748 if (*(skb->data + 3) == 0xFF) {
1749 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1750 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1751 return 0;
1752 }
1753 }
1754 return 13;
1755}
1756
1757static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1758{
1759 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1760 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1761 struct pci_dev *pdev = adapter->pdev;
1762 int i, j, k, l, lc, good_cnt, ret_val = 0;
1763 unsigned long time;
1764
1765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1766
1767 /*
1768 * Calculate the loop count based on the largest descriptor ring
1769 * The idea is to wrap the largest ring a number of times using 64
1770 * send/receive pairs during each loop
1771 */
1772
1773 if (rx_ring->count <= tx_ring->count)
1774 lc = ((tx_ring->count / 64) * 2) + 1;
1775 else
1776 lc = ((rx_ring->count / 64) * 2) + 1;
1777
1778 k = l = 0;
1779 for (j = 0; j <= lc; j++) {
1780 for (i = 0; i < 64; i++) {
1781 ixgbe_create_lbtest_frame(
1782 tx_ring->tx_buffer_info[k].skb,
1783 1024);
1b507730 1784 dma_sync_single_for_device(&pdev->dev,
da4dd0f7
PWJ		 1785 tx_ring->tx_buffer_info[k].dma,
1786 tx_ring->tx_buffer_info[k].length,
1b507730 1787 DMA_TO_DEVICE);
da4dd0f7
PWJ		 1788 if (unlikely(++k == tx_ring->count))
1789 k = 0;
1790 }
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1792 msleep(200);
1793 /* set the start time for the receive */
1794 time = jiffies;
1795 good_cnt = 0;
1796 do {
1797 /* receive the sent packets */
1b507730 1798 dma_sync_single_for_cpu(&pdev->dev,
da4dd0f7
PWJ		 1799 rx_ring->rx_buffer_info[l].dma,
1800 IXGBE_RXBUFFER_2048,
1b507730 1801 DMA_FROM_DEVICE);
da4dd0f7
PWJ		 1802 ret_val = ixgbe_check_lbtest_frame(
1803 rx_ring->rx_buffer_info[l].skb, 1024);
1804 if (!ret_val)
1805 good_cnt++;
1806 if (++l == rx_ring->count)
1807 l = 0;
1808 /*
1809 * time + 20 msecs (200 msecs on 2.4) is more than
1810 * enough time to complete the receives, if it's
1811 * exceeded, break and error off
1812 */
1813 } while (good_cnt < 64 && jiffies < (time + 20));
1814 if (good_cnt != 64) {
1815 /* ret_val is the same as mis-compare */
1816 ret_val = 13;
1817 break;
1818 }
1819 if (jiffies >= (time + 20)) {
1820 /* Error code for time out error */
1821 ret_val = 14;
1822 break;
1823 }
1824 }
1825
1826 return ret_val;
1827}
1828
1829static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1830{
1831 *data = ixgbe_setup_desc_rings(adapter);
1832 if (*data)
1833 goto out;
1834 *data = ixgbe_setup_loopback_test(adapter);
1835 if (*data)
1836 goto err_loopback;
1837 *data = ixgbe_run_loopback_test(adapter);
1838 ixgbe_loopback_cleanup(adapter);
1839
1840err_loopback:
1841 ixgbe_free_desc_rings(adapter);
1842out:
1843 return *data;
1844}
1845
1846static void ixgbe_diag_test(struct net_device *netdev,
1847 struct ethtool_test *eth_test, u64 *data)
1848{
1849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1850 bool if_running = netif_running(netdev);
1851
1852 set_bit(__IXGBE_TESTING, &adapter->state);
1853 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1854 /* Offline tests */
1855
849c4542 1856 e_info("offline testing starting\n");
da4dd0f7
PWJ		 1857
1858 /* Link test performed before hardware reset so autoneg doesn't
1859 * interfere with test result */
1860 if (ixgbe_link_test(adapter, &data[4]))
1861 eth_test->flags |= ETH_TEST_FL_FAILED;
1862
e7d481a6
GR		 1863 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1864 int i;
1865 for (i = 0; i < adapter->num_vfs; i++) {
1866 if (adapter->vfinfo[i].clear_to_send) {
1867 netdev_warn(netdev, "%s",
1868 "offline diagnostic is not "
1869 "supported when VFs are "
1870 "present\n");
1871 data[0] = 1;
1872 data[1] = 1;
1873 data[2] = 1;
1874 data[3] = 1;
1875 eth_test->flags |= ETH_TEST_FL_FAILED;
1876 clear_bit(__IXGBE_TESTING,
1877 &adapter->state);
1878 goto skip_ol_tests;
1879 }
1880 }
1881 }
1882
da4dd0f7
PWJ		 1883 if (if_running)
1884 /* indicate we're in test mode */
1885 dev_close(netdev);
1886 else
1887 ixgbe_reset(adapter);
1888
849c4542 1889 e_info("register testing starting\n");
da4dd0f7
PWJ		 1890 if (ixgbe_reg_test(adapter, &data[0]))
1891 eth_test->flags |= ETH_TEST_FL_FAILED;
1892
1893 ixgbe_reset(adapter);
849c4542 1894 e_info("eeprom testing starting\n");
da4dd0f7
PWJ		 1895 if (ixgbe_eeprom_test(adapter, &data[1]))
1896 eth_test->flags |= ETH_TEST_FL_FAILED;
1897
1898 ixgbe_reset(adapter);
849c4542 1899 e_info("interrupt testing starting\n");
da4dd0f7
PWJ		 1900 if (ixgbe_intr_test(adapter, &data[2]))
1901 eth_test->flags |= ETH_TEST_FL_FAILED;
1902
bdbec4b8
GR		 1903 /* If SRIOV or VMDq is enabled then skip MAC
1904 * loopback diagnostic. */
1905 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1906 IXGBE_FLAG_VMDQ_ENABLED)) {
849c4542 1907 e_info("Skip MAC loopback diagnostic in VT mode\n");
bdbec4b8
GR		 1908 data[3] = 0;
1909 goto skip_loopback;
1910 }
1911
da4dd0f7 1912 ixgbe_reset(adapter);
849c4542 1913 e_info("loopback testing starting\n");
da4dd0f7
PWJ		 1914 if (ixgbe_loopback_test(adapter, &data[3]))
1915 eth_test->flags |= ETH_TEST_FL_FAILED;
1916
bdbec4b8 1917skip_loopback:
da4dd0f7
PWJ		 1918 ixgbe_reset(adapter);
1919
1920 clear_bit(__IXGBE_TESTING, &adapter->state);
1921 if (if_running)
1922 dev_open(netdev);
1923 } else {
849c4542 1924 e_info("online testing starting\n");
da4dd0f7
PWJ		 1925 /* Online tests */
1926 if (ixgbe_link_test(adapter, &data[4]))
1927 eth_test->flags |= ETH_TEST_FL_FAILED;
1928
1929 /* Online tests aren't run; pass by default */
1930 data[0] = 0;
1931 data[1] = 0;
1932 data[2] = 0;
1933 data[3] = 0;
1934
1935 clear_bit(__IXGBE_TESTING, &adapter->state);
1936 }
e7d481a6 1937skip_ol_tests:
da4dd0f7
PWJ		 1938 msleep_interruptible(4 * 1000);
1939}
9a799d71 1940
d6c519e1
AD		 1941static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1942 struct ethtool_wolinfo *wol)
1943{
1944 struct ixgbe_hw *hw = &adapter->hw;
1945 int retval = 1;
1946
1947 switch(hw->device_id) {
1948 case IXGBE_DEV_ID_82599_KX4:
1949 retval = 0;
1950 break;
1951 default:
1952 wol->supported = 0;
d6c519e1
AD		 1953 }
1954
1955 return retval;
1956}
1957
9a799d71 1958static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1959 struct ethtool_wolinfo *wol)
9a799d71 1960{
e63d9762
PW		 1961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1962
1963 wol->supported = WAKE_UCAST | WAKE_MCAST |
1964 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1965 wol->wolopts = 0;
1966
d6c519e1
AD		 1967 if (ixgbe_wol_exclusion(adapter, wol) ||
1968 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1969 return;
1970
1971 if (adapter->wol & IXGBE_WUFC_EX)
1972 wol->wolopts |= WAKE_UCAST;
1973 if (adapter->wol & IXGBE_WUFC_MC)
1974 wol->wolopts |= WAKE_MCAST;
1975 if (adapter->wol & IXGBE_WUFC_BC)
1976 wol->wolopts |= WAKE_BCAST;
1977 if (adapter->wol & IXGBE_WUFC_MAG)
1978 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1979}
1980
e63d9762
PW		 1981static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1982{
1983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1984
1985 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1986 return -EOPNOTSUPP;
1987
d6c519e1
AD		 1988 if (ixgbe_wol_exclusion(adapter, wol))
1989 return wol->wolopts ? -EOPNOTSUPP : 0;
1990
e63d9762
PW		 1991 adapter->wol = 0;
1992
1993 if (wol->wolopts & WAKE_UCAST)
1994 adapter->wol |= IXGBE_WUFC_EX;
1995 if (wol->wolopts & WAKE_MCAST)
1996 adapter->wol |= IXGBE_WUFC_MC;
1997 if (wol->wolopts & WAKE_BCAST)
1998 adapter->wol |= IXGBE_WUFC_BC;
1999 if (wol->wolopts & WAKE_MAGIC)
2000 adapter->wol |= IXGBE_WUFC_MAG;
2001
2002 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2003
2004 return 0;
2005}
2006
9a799d71
AK		 2007static int ixgbe_nway_reset(struct net_device *netdev)
2008{
2009 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2010
d4f80882
AV		 2011 if (netif_running(netdev))
2012 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2013
2014 return 0;
2015}
2016
2017static int ixgbe_phys_id(struct net_device *netdev, u32 data)
2018{
2019 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 2020 struct ixgbe_hw *hw = &adapter->hw;
2021 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 2022 u32 i;
2023
2024 if (!data || data > 300)
2025 data = 300;
2026
2027 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 2028 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 2029 msleep_interruptible(200);
c44ade9e 2030 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 2031 msleep_interruptible(200);
2032 }
2033
2034 /* Restore LED settings */
2035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
2036
2037 return 0;
2038}
2039
2040static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2041 struct ethtool_coalesce *ec)
9a799d71
AK		 2042{
2043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2044
4a0b9ca0 2045 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 2046
2047 /* only valid if in constant ITR mode */
f7554a2b 2048 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2049 case 0:
2050 /* throttling disabled */
2051 ec->rx_coalesce_usecs = 0;
2052 break;
2053 case 1:
2054 /* dynamic ITR mode */
2055 ec->rx_coalesce_usecs = 1;
2056 break;
2057 default:
2058 /* fixed interrupt rate mode */
f7554a2b 2059 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2060 break;
2061 }
f7554a2b 2062
cfb3f91a
SN		 2063 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2064 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2065 return 0;
2066
f7554a2b
NS		 2067 /* only valid if in constant ITR mode */
2068 switch (adapter->tx_itr_setting) {
2069 case 0:
2070 /* throttling disabled */
2071 ec->tx_coalesce_usecs = 0;
2072 break;
2073 case 1:
2074 /* dynamic ITR mode */
2075 ec->tx_coalesce_usecs = 1;
2076 break;
2077 default:
2078 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2079 break;
2080 }
2081
9a799d71
AK		 2082 return 0;
2083}
2084
2085static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2086 struct ethtool_coalesce *ec)
9a799d71
AK		 2087{
2088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2089 struct ixgbe_q_vector *q_vector;
30efa5a3 2090 int i;
ef021194 2091 bool need_reset = false;
9a799d71 2092
cfb3f91a
SN		 2093 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2094 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2095 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2096 return -EINVAL;
2097
9a799d71 2098 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2099 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2100
2101 if (ec->rx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2102 u32 max_int;
2103 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2104 max_int = IXGBE_MAX_RSC_INT_RATE;
2105 else
2106 max_int = IXGBE_MAX_INT_RATE;
2107
509ee935 2108 /* check the limits */
f8d1dcaf 2109 if ((1000000/ec->rx_coalesce_usecs > max_int) ||
509ee935
JB		 2110 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2111 return -EINVAL;
2112
30efa5a3 2113 /* store the value in ints/second */
f7554a2b 2114 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2115
2116 /* static value of interrupt rate */
f7554a2b 2117 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2118 /* clear the lower bit as its used for dynamic state */
f7554a2b 2119 adapter->rx_itr_setting &= ~1;
30efa5a3
JB		 2120 } else if (ec->rx_coalesce_usecs == 1) {
2121 /* 1 means dynamic mode */
f7554a2b
NS		 2122 adapter->rx_eitr_param = 20000;
2123 adapter->rx_itr_setting = 1;
30efa5a3 2124 } else {
509ee935
JB		 2125 /*
2126 * any other value means disable eitr, which is best
2127 * served by setting the interrupt rate very high
2128 */
f8d1dcaf 2129 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b 2130 adapter->rx_itr_setting = 0;
f8d1dcaf
JB		 2131
2132 /*
2133 * if hardware RSC is enabled, disable it when
2134 * setting low latency mode, to avoid errata, assuming
2135 * that when the user set low latency mode they want
2136 * it at the cost of anything else
2137 */
2138 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2139 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
28c8e479
AG		 2140 if (netdev->features & NETIF_F_LRO) {
2141 netdev->features &= ~NETIF_F_LRO;
6b08f516 2142 e_info("rx-usecs set to 0, disabling RSC\n");
28c8e479 2143 }
ef021194 2144 need_reset = true;
f8d1dcaf 2145 }
f7554a2b
NS		 2146 }
2147
2148 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2149 /*
2150 * don't have to worry about max_int as above because
2151 * tx vectors don't do hardware RSC (an rx function)
2152 */
f7554a2b
NS		 2153 /* check the limits */
2154 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2155 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2156 return -EINVAL;
2157
2158 /* store the value in ints/second */
2159 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2160
2161 /* static value of interrupt rate */
2162 adapter->tx_itr_setting = adapter->tx_eitr_param;
2163
2164 /* clear the lower bit as its used for dynamic state */
2165 adapter->tx_itr_setting &= ~1;
2166 } else if (ec->tx_coalesce_usecs == 1) {
2167 /* 1 means dynamic mode */
2168 adapter->tx_eitr_param = 10000;
2169 adapter->tx_itr_setting = 1;
2170 } else {
2171 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2172 adapter->tx_itr_setting = 0;
30efa5a3 2173 }
9a799d71 2174
237057ad
DS		 2175 /* MSI/MSIx Interrupt Mode */
2176 if (adapter->flags &
2177 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2178 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2179 for (i = 0; i < num_vectors; i++) {
2180 q_vector = adapter->q_vector[i];
2181 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2182 /* tx only */
2183 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2184 else
2185 /* rx only or mixed */
f7554a2b 2186 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2187 ixgbe_write_eitr(q_vector);
2188 }
2189 /* Legacy Interrupt Mode */
2190 } else {
2191 q_vector = adapter->q_vector[0];
f7554a2b 2192 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2193 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2194 }
2195
ef021194
JB		 2196 /*
2197 * do reset here at the end to make sure EITR==0 case is handled
2198 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2199 * also locks in RSC enable/disable which requires reset
2200 */
2201 if (need_reset) {
2202 if (netif_running(netdev))
2203 ixgbe_reinit_locked(adapter);
2204 else
2205 ixgbe_reset(adapter);
2206 }
2207
9a799d71
AK		 2208 return 0;
2209}
2210
f8212f97
AD		 2211static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2212{
2213 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2214 bool need_reset = false;
1437ce39 2215 int rc;
f8212f97 2216
1437ce39
BH		 2217 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE);
2218 if (rc)
2219 return rc;
f8212f97 2220
f8212f97 2221 /* if state changes we need to update adapter->flags and reset */
f8d1dcaf
JB		 2222 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
2223 /*
2224 * cast both to bool and verify if they are set the same
2225 * but only enable RSC if itr is non-zero, as
2226 * itr=0 and RSC are mutually exclusive
2227 */
2228 if (((!!(data & ETH_FLAG_LRO)) !=
2229 (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) &&
2230 adapter->rx_itr_setting) {
2231 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2232 switch (adapter->hw.mac.type) {
2233 case ixgbe_mac_82599EB:
2234 need_reset = true;
2235 break;
2236 default:
2237 break;
2238 }
2239 } else if (!adapter->rx_itr_setting) {
2240 netdev->features &= ~ETH_FLAG_LRO;
28c8e479 2241 if (data & ETH_FLAG_LRO)
6b08f516 2242 e_info("rx-usecs set to 0, "
28c8e479 2243 "LRO/RSC cannot be enabled.\n");
f8d1dcaf 2244 }
9a713e7c
PW		 2245 }
2246
2247 /*
2248 * Check if Flow Director n-tuple support was enabled or disabled. If
2249 * the state changed, we need to reset.
2250 */
2251 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2252 (!(data & ETH_FLAG_NTUPLE))) {
2253 /* turn off Flow Director perfect, set hash and reset */
2254 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2255 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2256 need_reset = true;
2257 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2258 (data & ETH_FLAG_NTUPLE)) {
2259 /* turn off Flow Director hash, enable perfect and reset */
2260 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2261 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2262 need_reset = true;
2263 } else {
2264 /* no state change */
2265 }
2266
2267 if (need_reset) {
f8212f97
AD		 2268 if (netif_running(netdev))
2269 ixgbe_reinit_locked(adapter);
2270 else
2271 ixgbe_reset(adapter);
2272 }
9a713e7c 2273
f8212f97 2274 return 0;
9a713e7c
PW		 2275}
2276
2277static int ixgbe_set_rx_ntuple(struct net_device *dev,
2278 struct ethtool_rx_ntuple *cmd)
2279{
2280 struct ixgbe_adapter *adapter = netdev_priv(dev);
2281 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2282 struct ixgbe_atr_input input_struct;
2283 struct ixgbe_atr_input_masks input_masks;
2284 int target_queue;
2285
2286 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2287 return -EOPNOTSUPP;
2288
2289 /*
2290 * Don't allow programming if the action is a queue greater than
2291 * the number of online Tx queues.
2292 */
2293 if ((fs.action >= adapter->num_tx_queues) ||
2294 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2295 return -EINVAL;
2296
2297 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2298 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2299
2300 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2301 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2302 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2303 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2304 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2305 /* only use the lowest 2 bytes for flex bytes */
2306 input_masks.data_mask = (fs.data_mask & 0xffff);
2307
2308 switch (fs.flow_type) {
2309 case TCP_V4_FLOW:
2310 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2311 break;
2312 case UDP_V4_FLOW:
2313 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2314 break;
2315 case SCTP_V4_FLOW:
2316 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2317 break;
2318 default:
2319 return -1;
2320 }
f8212f97 2321
9a713e7c
PW		 2322 /* Mask bits from the inputs based on user-supplied mask */
2323 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2324 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2325 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2326 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2327 /* 82599 expects these to be byte-swapped for perfect filtering */
2328 ixgbe_atr_set_src_port_82599(&input_struct,
2329 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2330 ixgbe_atr_set_dst_port_82599(&input_struct,
2331 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2332
2333 /* VLAN and Flex bytes are either completely masked or not */
2334 if (!fs.vlan_tag_mask)
2335 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2336
2337 if (!input_masks.data_mask)
2338 /* make sure we only use the first 2 bytes of user data */
2339 ixgbe_atr_set_flex_byte_82599(&input_struct,
2340 (fs.data & 0xffff));
2341
2342 /* determine if we need to drop or route the packet */
2343 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2344 target_queue = MAX_RX_QUEUES - 1;
2345 else
2346 target_queue = fs.action;
2347
2348 spin_lock(&adapter->fdir_perfect_lock);
2349 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2350 &input_masks, 0, target_queue);
2351 spin_unlock(&adapter->fdir_perfect_lock);
2352
2353 return 0;
f8212f97 2354}
9a799d71 2355
b9804972 2356static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2357 .get_settings = ixgbe_get_settings,
2358 .set_settings = ixgbe_set_settings,
2359 .get_drvinfo = ixgbe_get_drvinfo,
2360 .get_regs_len = ixgbe_get_regs_len,
2361 .get_regs = ixgbe_get_regs,
2362 .get_wol = ixgbe_get_wol,
e63d9762 2363 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2364 .nway_reset = ixgbe_nway_reset,
2365 .get_link = ethtool_op_get_link,
2366 .get_eeprom_len = ixgbe_get_eeprom_len,
2367 .get_eeprom = ixgbe_get_eeprom,
2368 .get_ringparam = ixgbe_get_ringparam,
2369 .set_ringparam = ixgbe_set_ringparam,
2370 .get_pauseparam = ixgbe_get_pauseparam,
2371 .set_pauseparam = ixgbe_set_pauseparam,
2372 .get_rx_csum = ixgbe_get_rx_csum,
2373 .set_rx_csum = ixgbe_set_rx_csum,
2374 .get_tx_csum = ixgbe_get_tx_csum,
2375 .set_tx_csum = ixgbe_set_tx_csum,
2376 .get_sg = ethtool_op_get_sg,
2377 .set_sg = ethtool_op_set_sg,
2378 .get_msglevel = ixgbe_get_msglevel,
2379 .set_msglevel = ixgbe_set_msglevel,
2380 .get_tso = ethtool_op_get_tso,
2381 .set_tso = ixgbe_set_tso,
da4dd0f7 2382 .self_test = ixgbe_diag_test,
9a799d71
AK		 2383 .get_strings = ixgbe_get_strings,
2384 .phys_id = ixgbe_phys_id,
b4617240 2385 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2386 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2387 .get_coalesce = ixgbe_get_coalesce,
2388 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2389 .get_flags = ethtool_op_get_flags,
f8212f97 2390 .set_flags = ixgbe_set_flags,
9a713e7c 2391 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2392};
2393
2394void ixgbe_set_ethtool_ops(struct net_device *netdev)
2395{
2396 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2397}
Clone of davem's net-next-2.6 tree