[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_dcb.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2009 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _DCB_CONFIG_H_
#define _DCB_CONFIG_H_

#include "ixgbe_type.h"

/* DCB data structures */

#define IXGBE_MAX_PACKET_BUFFERS 8
#define MAX_USER_PRIORITY        8
#define MAX_TRAFFIC_CLASS        8
#define MAX_BW_GROUP             8
#define BW_PERCENT               100

#define DCB_TX_CONFIG            0
#define DCB_RX_CONFIG            1

/* DCB error Codes */
#define DCB_SUCCESS              0
#define DCB_ERR_CONFIG           -1
#define DCB_ERR_PARAM            -2

/* Transmit and receive Errors */
/* Error in bandwidth group allocation */
#define DCB_ERR_BW_GROUP        -3
/* Error in traffic class bandwidth allocation */
#define DCB_ERR_TC_BW           -4
/* Traffic class has both link strict and group strict enabled */
#define DCB_ERR_LS_GS           -5
/* Link strict traffic class has non zero bandwidth */
#define DCB_ERR_LS_BW_NONZERO   -6
/* Link strict bandwidth group has non zero bandwidth */
#define DCB_ERR_LS_BWG_NONZERO  -7
/*  Traffic class has zero bandwidth */
#define DCB_ERR_TC_BW_ZERO      -8

#define DCB_NOT_IMPLEMENTED      0x7FFFFFFF

struct dcb_pfc_tc_debug {
	u8  tc;
	u8  pause_status;
	u64 pause_quanta;
};

enum strict_prio_type {
	prio_none = 0,
	prio_group,
	prio_link
};

/* Traffic class bandwidth allocation per direction */
struct tc_bw_alloc {
	u8 bwg_id;		  /* Bandwidth Group (BWG) ID */
	u8 bwg_percent;		  /* % of BWG's bandwidth */
	u8 link_percent;	  /* % of link bandwidth */
	u8 up_to_tc_bitmap;	  /* User Priority to Traffic Class mapping */
	u16 data_credits_refill;  /* Credit refill amount in 64B granularity */
	u16 data_credits_max;	  /* Max credits for a configured packet buffer
				   * in 64B granularity.*/
	enum strict_prio_type prio_type; /* Link or Group Strict Priority */
};

enum dcb_pfc_type {
	pfc_disabled = 0,
	pfc_enabled_full,
	pfc_enabled_tx,
	pfc_enabled_rx
};

/* Traffic class configuration */
struct tc_configuration {
	struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
	enum dcb_pfc_type  dcb_pfc; /* Class based flow control setting */

	u16 desc_credits_max; /* For Tx Descriptor arbitration */
	u8 tc; /* Traffic class (TC) */
};

enum dcb_rx_pba_cfg {
	pba_equal,     /* PBA[0-7] each use 64KB FIFO */
	pba_80_48      /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
};

/*
 * This structure contains many values encoded as fixed-point
 * numbers, meaning that some of bits are dedicated to the
 * magnitude and others to the fraction part. In the comments
 * this is shown as f=n, where n is the number of fraction bits.
 * These fraction bits are always the low-order bits. The size
 * of the magnitude is not specified.
 */
struct bcn_config {
	u32 rp_admin_mode[MAX_TRAFFIC_CLASS]; /* BCN enabled, per TC */
	u32 bcna_option[2]; /* BCNA Port + MAC Addr */
	u32 rp_w;        /* Derivative Weight, f=3 */
	u32 rp_gi;       /* Increase Gain, f=12 */
	u32 rp_gd;       /* Decrease Gain, f=12 */
	u32 rp_ru;       /* Rate Unit */
	u32 rp_alpha;    /* Max Decrease Factor, f=12 */
	u32 rp_beta;     /* Max Increase Factor, f=12 */
	u32 rp_ri;       /* Initial Rate */
	u32 rp_td;       /* Drift Interval Timer */
	u32 rp_rd;       /* Drift Increase */
	u32 rp_tmax;     /* Severe Congestion Backoff Timer Range */
	u32 rp_rmin;     /* Severe Congestion Restart Rate */
	u32 rp_wrtt;     /* RTT Moving Average Weight */
};

struct ixgbe_dcb_config {
	struct bcn_config bcn;

	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
	u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */

	bool  round_robin_enable;

	enum dcb_rx_pba_cfg rx_pba_cfg;

	u32  dcb_cfg_version; /* Not used...OS-specific? */
	u32  link_speed; /* For bandwidth allocation validation purpose */
};

/* DCB driver APIs */

/* DCB rule checking function.*/
s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *config);

/* DCB credits calculation */
s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8);

/* DCB PFC functions */
s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, struct ixgbe_dcb_config *g);
s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);

/* DCB traffic class stats */
s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);

/* DCB config arbiters */
s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *,
                                     struct ixgbe_dcb_config *);
s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *,
                                     struct ixgbe_dcb_config *);
s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw *, struct ixgbe_dcb_config *);

/* DCB hw initialization */
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);

/* DCB definitions for credit calculation */
#define MAX_CREDIT_REFILL       511  /* 0x1FF * 64B = 32704B */
#define MINIMUM_CREDIT_REFILL   5    /* 5*64B = 320B */
#define MINIMUM_CREDIT_FOR_JUMBO 145  /* 145= UpperBound((9*1024+54)/64B) for 9KB jumbo frame */
#define DCB_MAX_TSO_SIZE        (32*1024) /* MAX TSO packet size supported in DCB mode */
#define MINIMUM_CREDIT_FOR_TSO  (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
#define MAX_CREDIT              4095 /* Maximum credit supported: 256KB * 1204 / 64B */

#endif /* _DCB_CONFIG_H */
Commit	Line	Data
2f90b865 AD	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
3efac5a0	4	Copyright(c) 1999 - 2009 Intel Corporation.
2f90b865 AD	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#ifndef _DCB_CONFIG_H_
	30	#define _DCB_CONFIG_H_
	31
	32	#include "ixgbe_type.h"
	33
	34	/* DCB data structures */
	35
	36	#define IXGBE_MAX_PACKET_BUFFERS 8
	37	#define MAX_USER_PRIORITY 8
	38	#define MAX_TRAFFIC_CLASS 8
	39	#define MAX_BW_GROUP 8
	40	#define BW_PERCENT 100
	41
	42	#define DCB_TX_CONFIG 0
	43	#define DCB_RX_CONFIG 1
	44
	45	/* DCB error Codes */
	46	#define DCB_SUCCESS 0
	47	#define DCB_ERR_CONFIG -1
	48	#define DCB_ERR_PARAM -2
	49
	50	/* Transmit and receive Errors */
	51	/* Error in bandwidth group allocation */
	52	#define DCB_ERR_BW_GROUP -3
	53	/* Error in traffic class bandwidth allocation */
	54	#define DCB_ERR_TC_BW -4
	55	/* Traffic class has both link strict and group strict enabled */
	56	#define DCB_ERR_LS_GS -5
	57	/* Link strict traffic class has non zero bandwidth */
	58	#define DCB_ERR_LS_BW_NONZERO -6
	59	/* Link strict bandwidth group has non zero bandwidth */
	60	#define DCB_ERR_LS_BWG_NONZERO -7
	61	/* Traffic class has zero bandwidth */
	62	#define DCB_ERR_TC_BW_ZERO -8
	63
	64	#define DCB_NOT_IMPLEMENTED 0x7FFFFFFF
	65
	66	struct dcb_pfc_tc_debug {
	67	u8 tc;
	68	u8 pause_status;
69	u64 pause_quanta;
70	};
71
72	enum strict_prio_type {
73	prio_none = 0,
74	prio_group,
75	prio_link
76	};
77
78	/* Traffic class bandwidth allocation per direction */
79	struct tc_bw_alloc {
80	u8 bwg_id; /* Bandwidth Group (BWG) ID */
81	u8 bwg_percent; /* % of BWG's bandwidth */
82	u8 link_percent; /* % of link bandwidth */
83	u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */
84	u16 data_credits_refill; /* Credit refill amount in 64B granularity */
85	u16 data_credits_max; /* Max credits for a configured packet buffer
86	* in 64B granularity.*/
87	enum strict_prio_type prio_type; /* Link or Group Strict Priority */
88	};
89
90	enum dcb_pfc_type {
91	pfc_disabled = 0,
92	pfc_enabled_full,
93	pfc_enabled_tx,
94	pfc_enabled_rx
95	};
96
97	/* Traffic class configuration */
98	struct tc_configuration {
99	struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
100	enum dcb_pfc_type dcb_pfc; /* Class based flow control setting */
101
102	u16 desc_credits_max; /* For Tx Descriptor arbitration */
103	u8 tc; /* Traffic class (TC) */
104	};
105
106	enum dcb_rx_pba_cfg {
107	pba_equal, /* PBA[0-7] each use 64KB FIFO */
108	pba_80_48 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */
109	};
110
859ee3c4 AD	111	/*
	112	* This structure contains many values encoded as fixed-point
	113	* numbers, meaning that some of bits are dedicated to the
	114	* magnitude and others to the fraction part. In the comments
	115	* this is shown as f=n, where n is the number of fraction bits.
	116	* These fraction bits are always the low-order bits. The size
	117	* of the magnitude is not specified.
	118	*/
	119	struct bcn_config {
	120	u32 rp_admin_mode[MAX_TRAFFIC_CLASS]; /* BCN enabled, per TC */
	121	u32 bcna_option[2]; /* BCNA Port + MAC Addr */
	122	u32 rp_w; /* Derivative Weight, f=3 */
	123	u32 rp_gi; /* Increase Gain, f=12 */
	124	u32 rp_gd; /* Decrease Gain, f=12 */
	125	u32 rp_ru; /* Rate Unit */
	126	u32 rp_alpha; /* Max Decrease Factor, f=12 */
	127	u32 rp_beta; /* Max Increase Factor, f=12 */
	128	u32 rp_ri; /* Initial Rate */
	129	u32 rp_td; /* Drift Interval Timer */
	130	u32 rp_rd; /* Drift Increase */
	131	u32 rp_tmax; /* Severe Congestion Backoff Timer Range */
	132	u32 rp_rmin; /* Severe Congestion Restart Rate */
	133	u32 rp_wrtt; /* RTT Moving Average Weight */
	134	};
	135
2f90b865	136	struct ixgbe_dcb_config {
859ee3c4 AD	137	struct bcn_config bcn;
859ee3c4 AD	138
2f90b865 AD	139	struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
	140	u8 bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
	141
	142	bool round_robin_enable;
	143
	144	enum dcb_rx_pba_cfg rx_pba_cfg;
	145
	146	u32 dcb_cfg_version; /* Not used...OS-specific? */
	147	u32 link_speed; /* For bandwidth allocation validation purpose */
	148	};
	149
	150	/* DCB driver APIs */
	151
	152	/* DCB rule checking function.*/
	153	s32 ixgbe_dcb_check_config(struct ixgbe_dcb_config *config);
	154
	155	/* DCB credits calculation */
	156	s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, u8);
	157
	158	/* DCB PFC functions */
	159	s32 ixgbe_dcb_config_pfc(struct ixgbe_hw , struct ixgbe_dcb_config g);
	160	s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw , struct ixgbe_hw_stats , u8);
	161
	162	/* DCB traffic class stats */
	163	s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);
	164	s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw , struct ixgbe_hw_stats , u8);
	165
	166	/* DCB config arbiters */
	167	s32 ixgbe_dcb_config_tx_desc_arbiter(struct ixgbe_hw *,
	168	struct ixgbe_dcb_config *);
	169	s32 ixgbe_dcb_config_tx_data_arbiter(struct ixgbe_hw *,
	170	struct ixgbe_dcb_config *);
	171	s32 ixgbe_dcb_config_rx_arbiter(struct ixgbe_hw , struct ixgbe_dcb_config );
	172
	173	/* DCB hw initialization */
	174	s32 ixgbe_dcb_hw_config(struct ixgbe_hw , struct ixgbe_dcb_config );
	175
	176	/* DCB definitions for credit calculation */
	177	#define MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */
	178	#define MINIMUM_CREDIT_REFILL 5 /* 564B = 320B /
	179	#define MINIMUM_CREDIT_FOR_JUMBO 145 /* 145= UpperBound((91024+54)/64B) for 9KB jumbo frame /
	180	#define DCB_MAX_TSO_SIZE (321024) / MAX TSO packet size supported in DCB mode */
	181	#define MINIMUM_CREDIT_FOR_TSO (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
	182	#define MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1204 / 64B */
	183
	184	#endif /* _DCB_CONFIG_H */