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[net-next-2.6.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4 1/*********************************************************************
1da177e4
LT		 2 *
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Status: Experimental.
5 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 6 * Created at:
7 * Modified at:
8 * Modified by:
9 *
1da177e4
LT		 10 * Copyright (c) 2002 Daniele Peri
11 * All Rights Reserved.
12 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 13 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 20 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
527b6af4
DT		 26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
1da177e4 30 * the License, or (at your option) any later version.
527b6af4 31 *
1da177e4
LT		 32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
527b6af4
DT		 36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
1da177e4
LT		 51#include <linux/init.h>
52#include <linux/rtnetlink.h>
53#include <linux/serial_reg.h>
54#include <linux/dma-mapping.h>
d94c77b9 55#include <linux/pnp.h>
d052d1be 56#include <linux/platform_device.h>
5a0e3ad6 57#include <linux/gfp.h>
1da177e4
LT		 58
59#include <asm/io.h>
60#include <asm/dma.h>
61#include <asm/byteorder.h>
62
63#include <linux/spinlock.h>
64#include <linux/pm.h>
c1e14a6e
LW		 65#ifdef CONFIG_PCI
66#include <linux/pci.h>
67#endif
1da177e4
LT		 68
69#include <net/irda/wrapper.h>
70#include <net/irda/irda.h>
71#include <net/irda/irda_device.h>
72
73#include "smsc-ircc2.h"
74#include "smsc-sio.h"
75
98b77773
DT		 76
77MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79MODULE_LICENSE("GPL");
80
cbcdd772 81static int smsc_nopnp = 1;
d0d4f69b 82module_param_named(nopnp, smsc_nopnp, bool, 0);
32db9276 83MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
d0d4f69b 84
916f11c7
BH		 85#define DMA_INVAL 255
86static int ircc_dma = DMA_INVAL;
98b77773
DT		 87module_param(ircc_dma, int, 0);
88MODULE_PARM_DESC(ircc_dma, "DMA channel");
89
916f11c7
BH		 90#define IRQ_INVAL 255
91static int ircc_irq = IRQ_INVAL;
98b77773
DT		 92module_param(ircc_irq, int, 0);
93MODULE_PARM_DESC(ircc_irq, "IRQ line");
94
95static int ircc_fir;
96module_param(ircc_fir, int, 0);
97MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
98
99static int ircc_sir;
100module_param(ircc_sir, int, 0);
101MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
102
103static int ircc_cfg;
104module_param(ircc_cfg, int, 0);
105MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
106
107static int ircc_transceiver;
108module_param(ircc_transceiver, int, 0);
109MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
110
1da177e4
LT		 111/* Types */
112
c1e14a6e
LW		 113#ifdef CONFIG_PCI
114struct smsc_ircc_subsystem_configuration {
115 unsigned short vendor; /* PCI vendor ID */
116 unsigned short device; /* PCI vendor ID */
117 unsigned short subvendor; /* PCI subsystem vendor ID */
83cf0a9b 118 unsigned short subdevice; /* PCI subsystem device ID */
c1e14a6e
LW		 119 unsigned short sir_io; /* I/O port for SIR */
120 unsigned short fir_io; /* I/O port for FIR */
121 unsigned char fir_irq; /* FIR IRQ */
122 unsigned char fir_dma; /* FIR DMA */
123 unsigned short cfg_base; /* I/O port for chip configuration */
124 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
125 const char *name; /* name shown as info */
126};
127#endif
128
1da177e4
LT		 129struct smsc_transceiver {
130 char *name;
527b6af4 131 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 132 int (*probe)(int fir_base);
133};
1da177e4
LT		 134
135struct smsc_chip {
136 char *name;
137 #if 0
138 u8 type;
139 #endif
140 u16 flags;
141 u8 devid;
142 u8 rev;
143};
1da177e4
LT		 144
145struct smsc_chip_address {
146 unsigned int cfg_base;
147 unsigned int type;
148};
1da177e4
LT		 149
150/* Private data for each instance */
151struct smsc_ircc_cb {
152 struct net_device *netdev; /* Yes! we are some kind of netdevice */
1da177e4 153 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 154
1da177e4
LT		 155 chipio_t io; /* IrDA controller information */
156 iobuff_t tx_buff; /* Transmit buffer */
157 iobuff_t rx_buff; /* Receive buffer */
158 dma_addr_t tx_buff_dma;
159 dma_addr_t rx_buff_dma;
160
161 struct qos_info qos; /* QoS capabilities for this device */
162
163 spinlock_t lock; /* For serializing operations */
527b6af4 164
1da177e4
LT		 165 __u32 new_speed;
166 __u32 flags; /* Interface flags */
167
168 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
169 int tx_len; /* Number of frames in tx_buff */
170
171 int transceiver;
6bb3b2cd 172 struct platform_device *pldev;
1da177e4
LT		 173};
174
175/* Constants */
176
6bb3b2cd
DT		 177#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
178
1da177e4
LT		 179#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
180#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 181#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 182#define SMSC_IRCC2_C_SIR_STOP 0
183
6bb3b2cd
DT		 184static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
185
1da177e4
LT		 186/* Prototypes */
187
188static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
189static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
190static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
191static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
192static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
193static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 194static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
195static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4 196static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
6518bbb8
SH		 197static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
198 struct net_device *dev);
199static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
200 struct net_device *dev);
80a90589
DT		 201static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 203static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
7d12e780 205static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
1da177e4
LT		 206static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208#if SMSC_IRCC2_C_SIR_STOP
209static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
210#endif
211static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213static int smsc_ircc_net_open(struct net_device *dev);
214static int smsc_ircc_net_close(struct net_device *dev);
215static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216#if SMSC_IRCC2_C_NET_TIMEOUT
217static void smsc_ircc_timeout(struct net_device *dev);
218#endif
1da177e4
LT		 219static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
220static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
221static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
222static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
223
224/* Probing */
225static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 226static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
227static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
228static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 229static int __init smsc_superio_fdc(unsigned short cfg_base);
230static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e
LW		 231#ifdef CONFIG_PCI
232static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
233static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
08d09997
LW		 234static void __init preconfigure_ali_port(struct pci_dev *dev,
235 unsigned short port);
c1e14a6e
LW		 236static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
237static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
238 unsigned short ircc_fir,
239 unsigned short ircc_sir,
240 unsigned char ircc_dma,
241 unsigned char ircc_irq);
242#endif
1da177e4
LT		 243
244/* Transceivers specific functions */
245
246static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
247static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
248static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
249static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
250static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
251static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
252
253/* Power Management */
254
3ae5eaec
RK		 255static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
256static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 257
3ae5eaec 258static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 259 .suspend = smsc_ircc_suspend,
260 .resume = smsc_ircc_resume,
3ae5eaec
RK		 261 .driver = {
262 .name = SMSC_IRCC2_DRIVER_NAME,
263 },
6bb3b2cd 264};
1da177e4
LT		 265
266/* Transceivers for SMSC-ircc */
267
b6158d23 268static struct smsc_transceiver smsc_transceivers[] =
1da177e4 269{
98b77773
DT		 270 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
271 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
272 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
273 { NULL, NULL }
1da177e4 274};
a956f4ca 275#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 276
277/* SMC SuperIO chipsets definitions */
278
279#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
280#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
281#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
282#define SIR 0 /* SuperIO Chip has only slow IRDA */
283#define FIR 4 /* SuperIO Chip has fast IRDA */
284#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
285
b6158d23 286static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 287{
288 /* Base address 0x3f0 or 0x370 */
289 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
290 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
291 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
292 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
294 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
295 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
296 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
297 { NULL }
298};
299
b6158d23 300static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 301{
302 /* Base address 0x3f0 or 0x370 */
303 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
304 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
305 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
306 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
308 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
309 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
310 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
311 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
312 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
313 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
314 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
315 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
316 { NULL }
317};
318
b6158d23 319static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 320{
321 /* Base address 0x2E or 0x4E */
322 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
afdf27c9 323 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
1da177e4
LT		 324 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
325 { NULL }
326};
327
b6158d23 328static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 329{
330 /* Base address 0x2E or 0x4E */
331 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
332 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
333 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
335 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
336 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
337 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
338 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
339 { NULL }
340};
341
342#define SMSCSIO_TYPE_FDC 1
343#define SMSCSIO_TYPE_LPC 2
344#define SMSCSIO_TYPE_FLAT 4
345#define SMSCSIO_TYPE_PAGED 8
346
b6158d23 347static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 348{
98b77773
DT		 349 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0, 0 }
1da177e4
LT		 355};
356
357/* Globals */
358
98b77773
DT		 359static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
360static unsigned short dev_count;
1da177e4
LT		 361
362static inline void register_bank(int iobase, int bank)
363{
98b77773
DT		 364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
365 iobase + IRCC_MASTER);
1da177e4
LT		 366}
367
d94c77b9
DB		 368/* PNP hotplug support */
369static const struct pnp_device_id smsc_ircc_pnp_table[] = {
370 { .id = "SMCf010", .driver_data = 0 },
371 /* and presumably others */
372 { }
373};
374MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
d0d4f69b
BH		 375
376static int pnp_driver_registered;
377
7a1aa309 378#ifdef CONFIG_PNP
d0d4f69b
BH		 379static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
380 const struct pnp_device_id *dev_id)
381{
382 unsigned int firbase, sirbase;
383 u8 dma, irq;
384
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
387 return -EINVAL;
388
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
393
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
395 return -ENODEV;
396
397 return 0;
398}
399
400static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
404};
7a1aa309
IM		 405#else /* CONFIG_PNP */
406static struct pnp_driver smsc_ircc_pnp_driver;
407#endif
1da177e4
LT		 408
409/*******************************************************************************
410 *
411 *
412 * SMSC-ircc stuff
413 *
414 *
415 *******************************************************************************/
416
d0d4f69b
BH		 417static int __init smsc_ircc_legacy_probe(void)
418{
419 int ret = 0;
420
7c31d2f5
BH		 421#ifdef CONFIG_PCI
422 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
423 /* Ignore errors from preconfiguration */
424 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
425 }
426#endif
427
d0d4f69b
BH		 428 if (ircc_fir > 0 && ircc_sir > 0) {
429 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
430 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
431
432 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
433 ret = -ENODEV;
434 } else {
435 ret = -ENODEV;
436
437 /* try user provided configuration register base address */
438 if (ircc_cfg > 0) {
439 IRDA_MESSAGE(" Overriding configuration address "
440 "0x%04x\n", ircc_cfg);
441 if (!smsc_superio_fdc(ircc_cfg))
442 ret = 0;
443 if (!smsc_superio_lpc(ircc_cfg))
444 ret = 0;
445 }
446
447 if (smsc_ircc_look_for_chips() > 0)
448 ret = 0;
449 }
450 return ret;
451}
452
1da177e4
LT		 453/*
454 * Function smsc_ircc_init ()
455 *
456 * Initialize chip. Just try to find out how many chips we are dealing with
457 * and where they are
458 */
459static int __init smsc_ircc_init(void)
460{
6bb3b2cd 461 int ret;
1da177e4 462
a97a6f10 463 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 464
3ae5eaec 465 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 466 if (ret) {
467 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
468 return ret;
469 }
470
98b77773 471 dev_count = 0;
527b6af4 472
d0d4f69b
BH		 473 if (smsc_nopnp || !pnp_platform_devices ||
474 ircc_cfg || ircc_fir || ircc_sir ||
475 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
476 ret = smsc_ircc_legacy_probe();
6bb3b2cd 477 } else {
d0d4f69b
BH		 478 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
479 pnp_driver_registered = 1;
1da177e4 480 }
527b6af4 481
d0d4f69b
BH		 482 if (ret) {
483 if (pnp_driver_registered)
484 pnp_unregister_driver(&smsc_ircc_pnp_driver);
3ae5eaec 485 platform_driver_unregister(&smsc_ircc_driver);
d0d4f69b 486 }
527b6af4 487
1da177e4
LT		 488 return ret;
489}
490
6518bbb8
SH		 491static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
492 struct net_device *dev)
02087be6
SH		 493{
494 struct smsc_ircc_cb *self = netdev_priv(dev);
495
496 if (self->io.speed > 115200)
497 return smsc_ircc_hard_xmit_fir(skb, dev);
498 else
499 return smsc_ircc_hard_xmit_sir(skb, dev);
500}
501
502static const struct net_device_ops smsc_ircc_netdev_ops = {
503 .ndo_open = smsc_ircc_net_open,
504 .ndo_stop = smsc_ircc_net_close,
505 .ndo_do_ioctl = smsc_ircc_net_ioctl,
506 .ndo_start_xmit = smsc_ircc_net_xmit,
507#if SMSC_IRCC2_C_NET_TIMEOUT
508 .ndo_tx_timeout = smsc_ircc_timeout,
509#endif
510};
511
1da177e4
LT		 512/*
513 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
514 *
515 * Try to open driver instance
516 *
517 */
518static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
519{
520 struct smsc_ircc_cb *self;
521 struct net_device *dev;
522 int err;
527b6af4 523
a97a6f10 524 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 525
526 err = smsc_ircc_present(fir_base, sir_base);
98b77773 527 if (err)
1da177e4 528 goto err_out;
527b6af4 529
1da177e4 530 err = -ENOMEM;
a956f4ca 531 if (dev_count >= ARRAY_SIZE(dev_self)) {
a97a6f10 532 IRDA_WARNING("%s(), too many devices!\n", __func__);
1da177e4
LT		 533 goto err_out1;
534 }
535
536 /*
537 * Allocate new instance of the driver
538 */
539 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
540 if (!dev) {
a97a6f10 541 IRDA_WARNING("%s() can't allocate net device\n", __func__);
1da177e4
LT		 542 goto err_out1;
543 }
544
1da177e4 545#if SMSC_IRCC2_C_NET_TIMEOUT
98b77773 546 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4 547#endif
02087be6 548 dev->netdev_ops = &smsc_ircc_netdev_ops;
527b6af4 549
da0841a0 550 self = netdev_priv(dev);
1da177e4
LT		 551 self->netdev = dev;
552
553 /* Make ifconfig display some details */
554 dev->base_addr = self->io.fir_base = fir_base;
555 dev->irq = self->io.irq = irq;
556
557 /* Need to store self somewhere */
6bb3b2cd 558 dev_self[dev_count] = self;
1da177e4
LT		 559 spin_lock_init(&self->lock);
560
527b6af4 561 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 562 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
563
564 self->rx_buff.head =
565 dma_alloc_coherent(NULL, self->rx_buff.truesize,
566 &self->rx_buff_dma, GFP_KERNEL);
567 if (self->rx_buff.head == NULL) {
568 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
569 driver_name);
570 goto err_out2;
571 }
572
573 self->tx_buff.head =
574 dma_alloc_coherent(NULL, self->tx_buff.truesize,
575 &self->tx_buff_dma, GFP_KERNEL);
576 if (self->tx_buff.head == NULL) {
577 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
578 driver_name);
579 goto err_out3;
580 }
581
582 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
583 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
584
585 self->rx_buff.in_frame = FALSE;
586 self->rx_buff.state = OUTSIDE_FRAME;
587 self->tx_buff.data = self->tx_buff.head;
588 self->rx_buff.data = self->rx_buff.head;
527b6af4 589
1da177e4 590 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 591 smsc_ircc_setup_qos(self);
1da177e4 592 smsc_ircc_init_chip(self);
527b6af4 593
98b77773
DT		 594 if (ircc_transceiver > 0 &&
595 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 596 self->transceiver = ircc_transceiver;
597 else
598 smsc_ircc_probe_transceiver(self);
599
600 err = register_netdev(self->netdev);
98b77773 601 if (err) {
1da177e4
LT		 602 IRDA_ERROR("%s, Network device registration failed!\n",
603 driver_name);
604 goto err_out4;
605 }
606
6bb3b2cd
DT		 607 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
608 dev_count, NULL, 0);
609 if (IS_ERR(self->pldev)) {
610 err = PTR_ERR(self->pldev);
611 goto err_out5;
612 }
3ae5eaec 613 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 614
615 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 616 dev_count++;
1da177e4
LT		 617
618 return 0;
98b77773 619
6bb3b2cd
DT		 620 err_out5:
621 unregister_netdev(self->netdev);
622
1da177e4
LT		 623 err_out4:
624 dma_free_coherent(NULL, self->tx_buff.truesize,
625 self->tx_buff.head, self->tx_buff_dma);
626 err_out3:
627 dma_free_coherent(NULL, self->rx_buff.truesize,
628 self->rx_buff.head, self->rx_buff_dma);
629 err_out2:
630 free_netdev(self->netdev);
6bb3b2cd 631 dev_self[dev_count] = NULL;
1da177e4
LT		 632 err_out1:
633 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
634 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
635 err_out:
636 return err;
637}
638
639/*
640 * Function smsc_ircc_present(fir_base, sir_base)
641 *
642 * Check the smsc-ircc chip presence
643 *
644 */
645static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
646{
647 unsigned char low, high, chip, config, dma, irq, version;
648
649 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
650 driver_name)) {
651 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
a97a6f10 652 __func__, fir_base);
1da177e4
LT		 653 goto out1;
654 }
655
656 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
657 driver_name)) {
658 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
a97a6f10 659 __func__, sir_base);
1da177e4
LT		 660 goto out2;
661 }
662
663 register_bank(fir_base, 3);
664
98b77773
DT		 665 high = inb(fir_base + IRCC_ID_HIGH);
666 low = inb(fir_base + IRCC_ID_LOW);
667 chip = inb(fir_base + IRCC_CHIP_ID);
668 version = inb(fir_base + IRCC_VERSION);
669 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 670 dma = config & IRCC_INTERFACE_DMA_MASK;
671 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
672
527b6af4 673 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 674 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
a97a6f10 675 __func__, fir_base);
1da177e4
LT		 676 goto out3;
677 }
678 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
679 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
680 chip & 0x0f, version, fir_base, sir_base, dma, irq);
681
682 return 0;
98b77773 683
1da177e4
LT		 684 out3:
685 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
686 out2:
687 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
688 out1:
689 return -ENODEV;
690}
691
692/*
693 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
694 *
695 * Setup I/O
696 *
697 */
527b6af4
DT		 698static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
699 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 700 u8 dma, u8 irq)
701{
702 unsigned char config, chip_dma, chip_irq;
703
704 register_bank(fir_base, 3);
98b77773
DT		 705 config = inb(fir_base + IRCC_INTERFACE);
706 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
707 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 708
709 self->io.fir_base = fir_base;
710 self->io.sir_base = sir_base;
711 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
712 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
713 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
714 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
715
916f11c7 716 if (irq != IRQ_INVAL) {
1da177e4
LT		 717 if (irq != chip_irq)
718 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
719 driver_name, chip_irq, irq);
720 self->io.irq = irq;
98b77773 721 } else
1da177e4 722 self->io.irq = chip_irq;
527b6af4 723
916f11c7 724 if (dma != DMA_INVAL) {
1da177e4
LT		 725 if (dma != chip_dma)
726 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
727 driver_name, chip_dma, dma);
728 self->io.dma = dma;
98b77773 729 } else
1da177e4
LT		 730 self->io.dma = chip_dma;
731
732}
733
734/*
735 * Function smsc_ircc_setup_qos(self)
736 *
737 * Setup qos
738 *
739 */
740static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
741{
742 /* Initialize QoS for this device */
743 irda_init_max_qos_capabilies(&self->qos);
527b6af4 744
1da177e4
LT		 745 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
746 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
747
748 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
749 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
750 irda_qos_bits_to_value(&self->qos);
751}
752
753/*
754 * Function smsc_ircc_init_chip(self)
755 *
756 * Init chip
757 *
758 */
759static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
760{
e812cb52 761 int iobase = self->io.fir_base;
1da177e4
LT		 762
763 register_bank(iobase, 0);
98b77773
DT		 764 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
765 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 766
767 register_bank(iobase, 1);
e812cb52 768 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 769 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 770
771#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 772 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
773 iobase + IRCC_SCE_CFGB);
527b6af4 774#else
98b77773
DT		 775 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
776 iobase + IRCC_SCE_CFGB);
527b6af4 777#endif
98b77773
DT		 778 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
779 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 780
1da177e4 781 register_bank(iobase, 4);
e812cb52 782 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 783
1da177e4 784 register_bank(iobase, 0);
e812cb52 785 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 786
787 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 788
1da177e4 789 /* Power on device */
98b77773 790 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 791}
792
793/*
794 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
795 *
796 * Process IOCTL commands for this device
797 *
798 */
799static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
800{
801 struct if_irda_req *irq = (struct if_irda_req *) rq;
802 struct smsc_ircc_cb *self;
803 unsigned long flags;
804 int ret = 0;
805
806 IRDA_ASSERT(dev != NULL, return -1;);
807
da0841a0 808 self = netdev_priv(dev);
1da177e4
LT		 809
810 IRDA_ASSERT(self != NULL, return -1;);
811
a97a6f10 812 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
527b6af4 813
1da177e4
LT		 814 switch (cmd) {
815 case SIOCSBANDWIDTH: /* Set bandwidth */
816 if (!capable(CAP_NET_ADMIN))
817 ret = -EPERM;
818 else {
819 /* Make sure we are the only one touching
820 * self->io.speed and the hardware - Jean II */
821 spin_lock_irqsave(&self->lock, flags);
822 smsc_ircc_change_speed(self, irq->ifr_baudrate);
823 spin_unlock_irqrestore(&self->lock, flags);
824 }
825 break;
826 case SIOCSMEDIABUSY: /* Set media busy */
827 if (!capable(CAP_NET_ADMIN)) {
828 ret = -EPERM;
829 break;
830 }
831
832 irda_device_set_media_busy(self->netdev, TRUE);
833 break;
834 case SIOCGRECEIVING: /* Check if we are receiving right now */
835 irq->ifr_receiving = smsc_ircc_is_receiving(self);
836 break;
837 #if 0
838 case SIOCSDTRRTS:
839 if (!capable(CAP_NET_ADMIN)) {
840 ret = -EPERM;
841 break;
842 }
843 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
844 break;
845 #endif
846 default:
847 ret = -EOPNOTSUPP;
848 }
527b6af4 849
1da177e4
LT		 850 return ret;
851}
852
1da177e4
LT		 853#if SMSC_IRCC2_C_NET_TIMEOUT
854/*
855 * Function smsc_ircc_timeout (struct net_device *dev)
856 *
857 * The networking timeout management.
858 *
859 */
860
861static void smsc_ircc_timeout(struct net_device *dev)
862{
da0841a0 863 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 864 unsigned long flags;
865
1da177e4
LT		 866 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
867 dev->name, self->io.speed);
868 spin_lock_irqsave(&self->lock, flags);
869 smsc_ircc_sir_start(self);
870 smsc_ircc_change_speed(self, self->io.speed);
871 dev->trans_start = jiffies;
872 netif_wake_queue(dev);
873 spin_unlock_irqrestore(&self->lock, flags);
874}
875#endif
876
877/*
878 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
879 *
880 * Transmits the current frame until FIFO is full, then
881 * waits until the next transmit interrupt, and continues until the
882 * frame is transmitted.
883 */
6518bbb8
SH		 884static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
885 struct net_device *dev)
1da177e4
LT		 886{
887 struct smsc_ircc_cb *self;
888 unsigned long flags;
1da177e4
LT		 889 s32 speed;
890
a97a6f10 891 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 892
ec634fe3 893 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
527b6af4 894
da0841a0 895 self = netdev_priv(dev);
ec634fe3 896 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 897
1da177e4 898 netif_stop_queue(dev);
527b6af4 899
1da177e4
LT		 900 /* Make sure test of self->io.speed & speed change are atomic */
901 spin_lock_irqsave(&self->lock, flags);
902
903 /* Check if we need to change the speed */
904 speed = irda_get_next_speed(skb);
98b77773 905 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 906 /* Check for empty frame */
907 if (!skb->len) {
908 /*
909 * We send frames one by one in SIR mode (no
910 * pipelining), so at this point, if we were sending
911 * a previous frame, we just received the interrupt
912 * telling us it is finished (UART_IIR_THRI).
913 * Therefore, waiting for the transmitter to really
914 * finish draining the fifo won't take too long.
915 * And the interrupt handler is not expected to run.
916 * - Jean II */
917 smsc_ircc_sir_wait_hw_transmitter_finish(self);
918 smsc_ircc_change_speed(self, speed);
919 spin_unlock_irqrestore(&self->lock, flags);
920 dev_kfree_skb(skb);
ec634fe3 921 return NETDEV_TX_OK;
1da177e4 922 }
98b77773 923 self->new_speed = speed;
1da177e4
LT		 924 }
925
926 /* Init tx buffer */
927 self->tx_buff.data = self->tx_buff.head;
928
929 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 930 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 931 self->tx_buff.truesize);
527b6af4 932
af049081 933 dev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 934
935 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 936 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 937
938 spin_unlock_irqrestore(&self->lock, flags);
939
940 dev_kfree_skb(skb);
527b6af4 941
ec634fe3 942 return NETDEV_TX_OK;
1da177e4
LT		 943}
944
945/*
946 * Function smsc_ircc_set_fir_speed (self, baud)
947 *
948 * Change the speed of the device
949 *
950 */
951static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
952{
953 int fir_base, ir_mode, ctrl, fast;
954
955 IRDA_ASSERT(self != NULL, return;);
956 fir_base = self->io.fir_base;
957
958 self->io.speed = speed;
959
98b77773 960 switch (speed) {
1da177e4 961 default:
527b6af4 962 case 576000:
1da177e4
LT		 963 ir_mode = IRCC_CFGA_IRDA_HDLC;
964 ctrl = IRCC_CRC;
965 fast = 0;
a97a6f10 966 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
1da177e4
LT		 967 break;
968 case 1152000:
969 ir_mode = IRCC_CFGA_IRDA_HDLC;
970 ctrl = IRCC_1152 | IRCC_CRC;
971 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
972 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
a97a6f10 973 __func__);
1da177e4
LT		 974 break;
975 case 4000000:
976 ir_mode = IRCC_CFGA_IRDA_4PPM;
977 ctrl = IRCC_CRC;
978 fast = IRCC_LCR_A_FAST;
979 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
a97a6f10 980 __func__);
1da177e4
LT		 981 break;
982 }
983 #if 0
984 Now in tranceiver!
985 /* This causes an interrupt */
986 register_bank(fir_base, 0);
98b77773 987 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 988 #endif
527b6af4 989
1da177e4 990 register_bank(fir_base, 1);
98b77773 991 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 992
1da177e4 993 register_bank(fir_base, 4);
98b77773 994 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 995}
996
997/*
998 * Function smsc_ircc_fir_start(self)
999 *
1000 * Change the speed of the device
1001 *
1002 */
1003static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1004{
1005 struct net_device *dev;
1006 int fir_base;
1007
a97a6f10 1008 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1009
1010 IRDA_ASSERT(self != NULL, return;);
1011 dev = self->netdev;
1012 IRDA_ASSERT(dev != NULL, return;);
1013
1014 fir_base = self->io.fir_base;
1015
1016 /* Reset everything */
1017
1da177e4 1018 /* Clear FIFO */
98b77773 1019 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 1020
1021 /* Enable interrupt */
98b77773 1022 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 1023
1024 register_bank(fir_base, 1);
1025
527b6af4 1026 /* Select the TX/RX interface */
1da177e4 1027#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 1028 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1029 fir_base + IRCC_SCE_CFGB);
527b6af4 1030#else
98b77773
DT		 1031 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1032 fir_base + IRCC_SCE_CFGB);
527b6af4 1033#endif
98b77773 1034 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 1035
1036 /* Enable SCE interrupts */
98b77773 1037 outb(0, fir_base + IRCC_MASTER);
1da177e4 1038 register_bank(fir_base, 0);
98b77773
DT		 1039 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1040 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 1041}
1042
1043/*
1044 * Function smsc_ircc_fir_stop(self, baud)
1045 *
1046 * Change the speed of the device
1047 *
1048 */
1049static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1050{
1051 int fir_base;
1052
a97a6f10 1053 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1054
1da177e4
LT		 1055 IRDA_ASSERT(self != NULL, return;);
1056
1057 fir_base = self->io.fir_base;
1058 register_bank(fir_base, 0);
98b77773
DT		 1059 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1060 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 1061}
1062
1063
1064/*
1065 * Function smsc_ircc_change_speed(self, baud)
1066 *
1067 * Change the speed of the device
1068 *
1069 * This function *must* be called with spinlock held, because it may
1070 * be called from the irq handler. - Jean II
1071 */
0fa2f491 1072static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1073{
1da177e4 1074 struct net_device *dev;
1da177e4 1075 int last_speed_was_sir;
527b6af4 1076
a97a6f10 1077 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1da177e4
LT		 1078
1079 IRDA_ASSERT(self != NULL, return;);
1080 dev = self->netdev;
1da177e4
LT		 1081
1082 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1083
1084 #if 0
1085 /* Temp Hack */
1086 speed= 1152000;
1087 self->io.speed = speed;
1088 last_speed_was_sir = 0;
527b6af4 1089 smsc_ircc_fir_start(self);
1da177e4 1090 #endif
527b6af4 1091
98b77773 1092 if (self->io.speed == 0)
1da177e4
LT		 1093 smsc_ircc_sir_start(self);
1094
1095 #if 0
98b77773 1096 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1097 #endif
1098
98b77773
DT		 1099 if (self->io.speed != speed)
1100 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1101
1102 self->io.speed = speed;
527b6af4 1103
98b77773
DT		 1104 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1105 if (!last_speed_was_sir) {
1da177e4
LT		 1106 smsc_ircc_fir_stop(self);
1107 smsc_ircc_sir_start(self);
1108 }
527b6af4 1109 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1110 } else {
1111 if (last_speed_was_sir) {
527b6af4 1112 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1113 smsc_ircc_sir_stop(self);
1114 #endif
1115 smsc_ircc_fir_start(self);
1116 }
1117 smsc_ircc_set_fir_speed(self, speed);
1118
1119 #if 0
1120 self->tx_buff.len = 10;
1121 self->tx_buff.data = self->tx_buff.head;
527b6af4 1122
80a90589 1123 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1124 #endif
1125 /* Be ready for incoming frames */
80a90589 1126 smsc_ircc_dma_receive(self);
1da177e4 1127 }
527b6af4 1128
1da177e4
LT		 1129 netif_wake_queue(dev);
1130}
1131
1132/*
1133 * Function smsc_ircc_set_sir_speed (self, speed)
1134 *
1135 * Set speed of IrDA port to specified baudrate
1136 *
1137 */
0e49e645 1138static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1139{
527b6af4 1140 int iobase;
1da177e4
LT		 1141 int fcr; /* FIFO control reg */
1142 int lcr; /* Line control reg */
1143 int divisor;
1144
a97a6f10 1145 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1da177e4
LT		 1146
1147 IRDA_ASSERT(self != NULL, return;);
1148 iobase = self->io.sir_base;
527b6af4 1149
1da177e4
LT		 1150 /* Update accounting for new speed */
1151 self->io.speed = speed;
1152
1153 /* Turn off interrupts */
98b77773 1154 outb(0, iobase + UART_IER);
1da177e4 1155
98b77773 1156 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1157
1da177e4
LT		 1158 fcr = UART_FCR_ENABLE_FIFO;
1159
527b6af4 1160 /*
1da177e4
LT		 1161 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1162 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1163 * about this timeout since it will always be fast enough.
1da177e4 1164 */
98b77773
DT		 1165 fcr |= self->io.speed < 38400 ?
1166 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1167
1da177e4
LT		 1168 /* IrDA ports use 8N1 */
1169 lcr = UART_LCR_WLEN8;
527b6af4 1170
98b77773
DT		 1171 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1172 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1173 outb(divisor >> 8, iobase + UART_DLM);
1174 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1175 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1176
1177 /* Turn on interrups */
98b77773 1178 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4 1179
a97a6f10 1180 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1da177e4
LT		 1181}
1182
1183
1184/*
1185 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1186 *
1187 * Transmit the frame!
1188 *
1189 */
6518bbb8
SH		 1190static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1191 struct net_device *dev)
1da177e4
LT		 1192{
1193 struct smsc_ircc_cb *self;
1194 unsigned long flags;
1195 s32 speed;
1da177e4
LT		 1196 int mtt;
1197
ec634fe3 1198 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
da0841a0 1199 self = netdev_priv(dev);
ec634fe3 1200 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4 1201
1da177e4
LT		 1202 netif_stop_queue(dev);
1203
1204 /* Make sure test of self->io.speed & speed change are atomic */
1205 spin_lock_irqsave(&self->lock, flags);
1206
1207 /* Check if we need to change the speed after this frame */
1208 speed = irda_get_next_speed(skb);
98b77773 1209 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1210 /* Check for empty frame */
1211 if (!skb->len) {
1212 /* Note : you should make sure that speed changes
1213 * are not going to corrupt any outgoing frame.
1214 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1215 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1216 spin_unlock_irqrestore(&self->lock, flags);
1217 dev_kfree_skb(skb);
ec634fe3 1218 return NETDEV_TX_OK;
98b77773
DT		 1219 }
1220
1221 self->new_speed = speed;
1da177e4 1222 }
527b6af4 1223
d626f62b 1224 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1da177e4
LT		 1225
1226 self->tx_buff.len = skb->len;
1227 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1228
1229 mtt = irda_get_mtt(skb);
1da177e4
LT		 1230 if (mtt) {
1231 int bofs;
1232
527b6af4 1233 /*
1da177e4
LT		 1234 * Compute how many BOFs (STA or PA's) we need to waste the
1235 * min turn time given the speed of the link.
1236 */
1237 bofs = mtt * (self->io.speed / 1000) / 8000;
1238 if (bofs > 4095)
1239 bofs = 4095;
1240
80a90589 1241 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1242 } else {
1243 /* Transmit frame */
80a90589 1244 smsc_ircc_dma_xmit(self, 0);
1da177e4 1245 }
98b77773 1246
1da177e4
LT		 1247 spin_unlock_irqrestore(&self->lock, flags);
1248 dev_kfree_skb(skb);
1249
ec634fe3 1250 return NETDEV_TX_OK;
1da177e4
LT		 1251}
1252
1253/*
80a90589 1254 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1255 *
1256 * Transmit data using DMA
1257 *
1258 */
80a90589 1259static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1260{
80a90589 1261 int iobase = self->io.fir_base;
1da177e4
LT		 1262 u8 ctrl;
1263
a97a6f10 1264 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1265#if 1
1266 /* Disable Rx */
1267 register_bank(iobase, 0);
98b77773 1268 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1269#endif
1270 register_bank(iobase, 1);
98b77773
DT		 1271 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1272 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1273
1274 self->io.direction = IO_XMIT;
1275
1276 /* Set BOF additional count for generating the min turn time */
1277 register_bank(iobase, 4);
98b77773
DT		 1278 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1279 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1280 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1281
1282 /* Set max Tx frame size */
98b77773
DT		 1283 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1284 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1285
1286 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1287
1da177e4
LT		 1288 /* Enable burst mode chip Tx DMA */
1289 register_bank(iobase, 1);
98b77773
DT		 1290 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1291 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1292
1293 /* Setup DMA controller (must be done after enabling chip DMA) */
1294 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1295 DMA_TX_MODE);
1296
1297 /* Enable interrupt */
1298
1299 register_bank(iobase, 0);
98b77773
DT		 1300 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1301 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1302
1da177e4 1303 /* Enable transmit */
98b77773 1304 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1305}
1306
1307/*
1308 * Function smsc_ircc_dma_xmit_complete (self)
1309 *
527b6af4 1310 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1311 * by the interrupt handler
1312 *
1313 */
80a90589 1314static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1315{
80a90589
DT		 1316 int iobase = self->io.fir_base;
1317
a97a6f10 1318 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1319#if 0
1320 /* Disable Tx */
1321 register_bank(iobase, 0);
98b77773 1322 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1323#endif
80a90589
DT		 1324 register_bank(iobase, 1);
1325 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1326 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1327
1328 /* Check for underrun! */
1329 register_bank(iobase, 0);
98b77773 1330 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
af049081
SH		 1331 self->netdev->stats.tx_errors++;
1332 self->netdev->stats.tx_fifo_errors++;
1da177e4
LT		 1333
1334 /* Reset error condition */
1335 register_bank(iobase, 0);
98b77773
DT		 1336 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1337 outb(0x00, iobase + IRCC_MASTER);
1da177e4 1338 } else {
af049081
SH		 1339 self->netdev->stats.tx_packets++;
1340 self->netdev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1341 }
1342
1343 /* Check if it's time to change the speed */
1344 if (self->new_speed) {
527b6af4 1345 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1346 self->new_speed = 0;
1347 }
1348
1349 netif_wake_queue(self->netdev);
1350}
1351
1352/*
1353 * Function smsc_ircc_dma_receive(self)
1354 *
1355 * Get ready for receiving a frame. The device will initiate a DMA
1356 * if it starts to receive a frame.
1357 *
1358 */
80a90589 1359static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1360{
80a90589 1361 int iobase = self->io.fir_base;
1da177e4
LT		 1362#if 0
1363 /* Turn off chip DMA */
1364 register_bank(iobase, 1);
98b77773
DT		 1365 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1366 iobase + IRCC_SCE_CFGB);
1da177e4 1367#endif
527b6af4 1368
1da177e4
LT		 1369 /* Disable Tx */
1370 register_bank(iobase, 0);
98b77773 1371 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1372
1373 /* Turn off chip DMA */
1374 register_bank(iobase, 1);
98b77773
DT		 1375 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1376 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1377
1378 self->io.direction = IO_RECV;
1379 self->rx_buff.data = self->rx_buff.head;
1380
1381 /* Set max Rx frame size */
1382 register_bank(iobase, 4);
98b77773
DT		 1383 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1384 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1385
1386 /* Setup DMA controller */
1387 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1388 DMA_RX_MODE);
1389
1390 /* Enable burst mode chip Rx DMA */
1391 register_bank(iobase, 1);
98b77773
DT		 1392 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1393 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1394
1395 /* Enable interrupt */
1396 register_bank(iobase, 0);
98b77773
DT		 1397 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1398 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1399
1400 /* Enable receiver */
1401 register_bank(iobase, 0);
527b6af4 1402 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1403 iobase + IRCC_LCR_B);
527b6af4 1404
1da177e4
LT		 1405 return 0;
1406}
1407
1408/*
80a90589 1409 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1410 *
1411 * Finished with receiving frames
1412 *
1413 */
80a90589 1414static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1415{
1416 struct sk_buff *skb;
1417 int len, msgcnt, lsr;
80a90589 1418 int iobase = self->io.fir_base;
527b6af4 1419
1da177e4 1420 register_bank(iobase, 0);
527b6af4 1421
a97a6f10 1422 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1423#if 0
1424 /* Disable Rx */
1425 register_bank(iobase, 0);
98b77773 1426 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1427#endif
1428 register_bank(iobase, 0);
98b77773
DT		 1429 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1430 lsr= inb(iobase + IRCC_LSR);
1431 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4 1432
a97a6f10 1433 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1434 get_dma_residue(self->io.dma));
1435
1436 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1437
98b77773
DT		 1438 /* Look for errors */
1439 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
af049081 1440 self->netdev->stats.rx_errors++;
98b77773 1441 if (lsr & IRCC_LSR_FRAME_ERROR)
af049081 1442 self->netdev->stats.rx_frame_errors++;
98b77773 1443 if (lsr & IRCC_LSR_CRC_ERROR)
af049081 1444 self->netdev->stats.rx_crc_errors++;
98b77773 1445 if (lsr & IRCC_LSR_SIZE_ERROR)
af049081 1446 self->netdev->stats.rx_length_errors++;
98b77773 1447 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
af049081 1448 self->netdev->stats.rx_length_errors++;
1da177e4
LT		 1449 return;
1450 }
98b77773 1451
1da177e4 1452 /* Remove CRC */
98b77773 1453 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1454
98b77773 1455 if (len < 2 || len > 2050) {
a97a6f10 1456 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1da177e4
LT		 1457 return;
1458 }
a97a6f10 1459 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1da177e4 1460
98b77773
DT		 1461 skb = dev_alloc_skb(len + 1);
1462 if (!skb) {
1da177e4 1463 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
a97a6f10 1464 __func__);
1da177e4 1465 return;
527b6af4 1466 }
1da177e4 1467 /* Make sure IP header gets aligned */
527b6af4 1468 skb_reserve(skb, 1);
1da177e4
LT		 1469
1470 memcpy(skb_put(skb, len), self->rx_buff.data, len);
af049081
SH		 1471 self->netdev->stats.rx_packets++;
1472 self->netdev->stats.rx_bytes += len;
1da177e4
LT		 1473
1474 skb->dev = self->netdev;
459a98ed 1475 skb_reset_mac_header(skb);
1da177e4
LT		 1476 skb->protocol = htons(ETH_P_IRDA);
1477 netif_rx(skb);
1478}
1479
1480/*
1481 * Function smsc_ircc_sir_receive (self)
1482 *
1483 * Receive one frame from the infrared port
1484 *
1485 */
527b6af4 1486static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1487{
1488 int boguscount = 0;
1489 int iobase;
1490
1491 IRDA_ASSERT(self != NULL, return;);
1492
1493 iobase = self->io.sir_base;
1494
527b6af4
DT		 1495 /*
1496 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1497 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1498 */
1499 do {
af049081 1500 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
98b77773 1501 inb(iobase + UART_RX));
1da177e4
LT		 1502
1503 /* Make sure we don't stay here to long */
1504 if (boguscount++ > 32) {
a97a6f10 1505 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1da177e4
LT		 1506 break;
1507 }
98b77773 1508 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1509}
1510
1511
1512/*
1513 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1514 *
1515 * An interrupt from the chip has arrived. Time to do some work
1516 *
1517 */
28fc1f5a 1518static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1da177e4 1519{
28fc1f5a
JG		 1520 struct net_device *dev = dev_id;
1521 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1522 int iobase, iir, lcra, lsr;
1523 irqreturn_t ret = IRQ_NONE;
1524
1da177e4 1525 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1526 spin_lock(&self->lock);
1da177e4
LT		 1527
1528 /* Check if we should use the SIR interrupt handler */
98b77773 1529 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1530 ret = smsc_ircc_interrupt_sir(dev);
1531 goto irq_ret_unlock;
1532 }
1533
1534 iobase = self->io.fir_base;
1535
1536 register_bank(iobase, 0);
98b77773 1537 iir = inb(iobase + IRCC_IIR);
527b6af4 1538 if (iir == 0)
1da177e4
LT		 1539 goto irq_ret_unlock;
1540 ret = IRQ_HANDLED;
1541
1542 /* Disable interrupts */
98b77773
DT		 1543 outb(0, iobase + IRCC_IER);
1544 lcra = inb(iobase + IRCC_LCR_A);
1545 lsr = inb(iobase + IRCC_LSR);
527b6af4 1546
a97a6f10 1547 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1da177e4
LT		 1548
1549 if (iir & IRCC_IIR_EOM) {
1550 if (self->io.direction == IO_RECV)
80a90589 1551 smsc_ircc_dma_receive_complete(self);
1da177e4 1552 else
80a90589 1553 smsc_ircc_dma_xmit_complete(self);
527b6af4 1554
80a90589 1555 smsc_ircc_dma_receive(self);
1da177e4
LT		 1556 }
1557
1558 if (iir & IRCC_IIR_ACTIVE_FRAME) {
a97a6f10 1559 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1da177e4
LT		 1560 }
1561
1562 /* Enable interrupts again */
1563
1564 register_bank(iobase, 0);
98b77773 1565 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1566
1567 irq_ret_unlock:
1568 spin_unlock(&self->lock);
28fc1f5a 1569
1da177e4
LT		 1570 return ret;
1571}
1572
1573/*
7d12e780 1574 * Function irport_interrupt_sir (irq, dev_id)
1da177e4
LT		 1575 *
1576 * Interrupt handler for SIR modes
1577 */
1578static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1579{
da0841a0 1580 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1581 int boguscount = 0;
1582 int iobase;
1583 int iir, lsr;
1584
1585 /* Already locked comming here in smsc_ircc_interrupt() */
1586 /*spin_lock(&self->lock);*/
1587
1588 iobase = self->io.sir_base;
1589
98b77773 1590 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1591 if (iir == 0)
1592 return IRQ_NONE;
1593 while (iir) {
1594 /* Clear interrupt */
98b77773 1595 lsr = inb(iobase + UART_LSR);
1da177e4 1596
527b6af4 1597 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
a97a6f10 1598 __func__, iir, lsr, iobase);
1da177e4
LT		 1599
1600 switch (iir) {
1601 case UART_IIR_RLSI:
a97a6f10 1602 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1da177e4
LT		 1603 break;
1604 case UART_IIR_RDI:
1605 /* Receive interrupt */
1606 smsc_ircc_sir_receive(self);
1607 break;
1608 case UART_IIR_THRI:
1609 if (lsr & UART_LSR_THRE)
1610 /* Transmitter ready for data */
1611 smsc_ircc_sir_write_wakeup(self);
1612 break;
1613 default:
1614 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
a97a6f10 1615 __func__, iir);
1da177e4 1616 break;
527b6af4
DT		 1617 }
1618
1da177e4
LT		 1619 /* Make sure we don't stay here to long */
1620 if (boguscount++ > 100)
1621 break;
1622
527b6af4 1623 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1624 }
1625 /*spin_unlock(&self->lock);*/
1626 return IRQ_HANDLED;
1627}
1628
1629
1630#if 0 /* unused */
1631/*
1632 * Function ircc_is_receiving (self)
1633 *
1634 * Return TRUE is we are currently receiving a frame
1635 *
1636 */
1637static int ircc_is_receiving(struct smsc_ircc_cb *self)
1638{
1639 int status = FALSE;
1640 /* int iobase; */
1641
a97a6f10 1642 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1643
1644 IRDA_ASSERT(self != NULL, return FALSE;);
1645
a97a6f10 1646 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1da177e4
LT		 1647 get_dma_residue(self->io.dma));
1648
1649 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1650
1da177e4
LT		 1651 return status;
1652}
1653#endif /* unused */
1654
e812cb52
DT		 1655static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1656{
1657 int error;
1658
1659 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1660 self->netdev->name, self->netdev);
1661 if (error)
1662 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
a97a6f10 1663 __func__, self->io.irq, error);
e812cb52
DT		 1664
1665 return error;
1666}
1667
1668static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1669{
1670 unsigned long flags;
1671
1672 spin_lock_irqsave(&self->lock, flags);
1673
1674 self->io.speed = 0;
1675 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1676
1677 spin_unlock_irqrestore(&self->lock, flags);
1678}
1679
1680static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1681{
1682 int iobase = self->io.fir_base;
1683 unsigned long flags;
1684
1685 spin_lock_irqsave(&self->lock, flags);
1686
1687 register_bank(iobase, 0);
1688 outb(0, iobase + IRCC_IER);
1689 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1690 outb(0x00, iobase + IRCC_MASTER);
1691
1692 spin_unlock_irqrestore(&self->lock, flags);
1693}
1694
1da177e4
LT		 1695
1696/*
1697 * Function smsc_ircc_net_open (dev)
1698 *
1699 * Start the device
1700 *
1701 */
1702static int smsc_ircc_net_open(struct net_device *dev)
1703{
1704 struct smsc_ircc_cb *self;
1da177e4 1705 char hwname[16];
1da177e4 1706
a97a6f10 1707 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1708
1da177e4 1709 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1710 self = netdev_priv(dev);
1da177e4 1711 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1712
e812cb52 1713 if (self->io.suspended) {
a97a6f10 1714 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
e812cb52
DT		 1715 return -EAGAIN;
1716 }
1717
527b6af4 1718 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1719 (void *) dev)) {
1720 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
a97a6f10 1721 __func__, self->io.irq);
1da177e4
LT		 1722 return -EAGAIN;
1723 }
1724
e812cb52 1725 smsc_ircc_start_interrupts(self);
527b6af4 1726
1da177e4
LT		 1727 /* Give self a hardware name */
1728 /* It would be cool to offer the chip revision here - Jean II */
1729 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1730
527b6af4 1731 /*
1da177e4 1732 * Open new IrLAP layer instance, now that everything should be
527b6af4 1733 * initialized properly
1da177e4
LT		 1734 */
1735 self->irlap = irlap_open(dev, &self->qos, hwname);
1736
1737 /*
1738 * Always allocate the DMA channel after the IRQ,
1739 * and clean up on failure.
1740 */
1741 if (request_dma(self->io.dma, dev->name)) {
1742 smsc_ircc_net_close(dev);
1743
1744 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
a97a6f10 1745 __func__, self->io.dma);
1da177e4
LT		 1746 return -EAGAIN;
1747 }
527b6af4 1748
1da177e4
LT		 1749 netif_start_queue(dev);
1750
1751 return 0;
1752}
1753
1754/*
1755 * Function smsc_ircc_net_close (dev)
1756 *
1757 * Stop the device
1758 *
1759 */
1760static int smsc_ircc_net_close(struct net_device *dev)
1761{
1762 struct smsc_ircc_cb *self;
1da177e4 1763
a97a6f10 1764 IRDA_DEBUG(1, "%s\n", __func__);
527b6af4 1765
1da177e4 1766 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1767 self = netdev_priv(dev);
1da177e4 1768 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1769
1da177e4
LT		 1770 /* Stop device */
1771 netif_stop_queue(dev);
527b6af4 1772
1da177e4
LT		 1773 /* Stop and remove instance of IrLAP */
1774 if (self->irlap)
1775 irlap_close(self->irlap);
1776 self->irlap = NULL;
1777
e812cb52
DT		 1778 smsc_ircc_stop_interrupts(self);
1779
1780 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1781 if (!self->io.suspended)
1782 free_irq(self->io.irq, dev);
1783
1da177e4 1784 disable_dma(self->io.dma);
1da177e4
LT		 1785 free_dma(self->io.dma);
1786
1787 return 0;
1788}
1789
3ae5eaec 1790static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1791{
3ae5eaec 1792 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1793
9480e307 1794 if (!self->io.suspended) {
e812cb52
DT		 1795 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1796
1797 rtnl_lock();
1798 if (netif_running(self->netdev)) {
1799 netif_device_detach(self->netdev);
1800 smsc_ircc_stop_interrupts(self);
1801 free_irq(self->io.irq, self->netdev);
1802 disable_dma(self->io.dma);
1803 }
98b77773 1804 self->io.suspended = 1;
e812cb52 1805 rtnl_unlock();
98b77773 1806 }
6bb3b2cd
DT		 1807
1808 return 0;
1da177e4
LT		 1809}
1810
3ae5eaec 1811static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1812{
3ae5eaec 1813 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1814
9480e307 1815 if (self->io.suspended) {
e812cb52
DT		 1816 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1817
1818 rtnl_lock();
1819 smsc_ircc_init_chip(self);
1820 if (netif_running(self->netdev)) {
1821 if (smsc_ircc_request_irq(self)) {
1822 /*
1823 * Don't fail resume process, just kill this
1824 * network interface
1825 */
1826 unregister_netdevice(self->netdev);
1827 } else {
1828 enable_dma(self->io.dma);
1829 smsc_ircc_start_interrupts(self);
1830 netif_device_attach(self->netdev);
1831 }
1832 }
6bb3b2cd 1833 self->io.suspended = 0;
e812cb52 1834 rtnl_unlock();
6bb3b2cd 1835 }
1da177e4
LT		 1836 return 0;
1837}
1838
1839/*
1840 * Function smsc_ircc_close (self)
1841 *
1842 * Close driver instance
1843 *
1844 */
1845static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1846{
a97a6f10 1847 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 1848
1849 IRDA_ASSERT(self != NULL, return -1;);
1850
6bb3b2cd 1851 platform_device_unregister(self->pldev);
1da177e4
LT		 1852
1853 /* Remove netdevice */
1854 unregister_netdev(self->netdev);
1855
e812cb52 1856 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1857
1858 /* Release the PORTS that this driver is using */
a97a6f10 1859 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1860 self->io.fir_base);
1861
1862 release_region(self->io.fir_base, self->io.fir_ext);
1863
a97a6f10 1864 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1da177e4
LT		 1865 self->io.sir_base);
1866
1867 release_region(self->io.sir_base, self->io.sir_ext);
1868
1869 if (self->tx_buff.head)
1870 dma_free_coherent(NULL, self->tx_buff.truesize,
1871 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1872
1da177e4
LT		 1873 if (self->rx_buff.head)
1874 dma_free_coherent(NULL, self->rx_buff.truesize,
1875 self->rx_buff.head, self->rx_buff_dma);
1876
1877 free_netdev(self->netdev);
1878
1879 return 0;
1880}
1881
1882static void __exit smsc_ircc_cleanup(void)
1883{
1884 int i;
1885
a97a6f10 1886 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 1887
98b77773 1888 for (i = 0; i < 2; i++) {
1da177e4
LT		 1889 if (dev_self[i])
1890 smsc_ircc_close(dev_self[i]);
1891 }
6bb3b2cd 1892
d0d4f69b
BH		 1893 if (pnp_driver_registered)
1894 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1895
3ae5eaec 1896 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1897}
1898
1899/*
1900 * Start SIR operations
1901 *
1902 * This function *must* be called with spinlock held, because it may
1903 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1904 */
0e49e645 1905static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1da177e4
LT		 1906{
1907 struct net_device *dev;
1908 int fir_base, sir_base;
1909
a97a6f10 1910 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4 1911
527b6af4 1912 IRDA_ASSERT(self != NULL, return;);
98b77773 1913 dev = self->netdev;
527b6af4 1914 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1915
1916 fir_base = self->io.fir_base;
1917 sir_base = self->io.sir_base;
1918
1919 /* Reset everything */
98b77773 1920 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1921
1922 #if SMSC_IRCC2_C_SIR_STOP
1923 /*smsc_ircc_sir_stop(self);*/
1924 #endif
1925
1926 register_bank(fir_base, 1);
98b77773 1927 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1928
1929 /* Initialize UART */
98b77773
DT		 1930 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1931 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1932
1da177e4 1933 /* Turn on interrups */
98b77773 1934 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4 1935
a97a6f10 1936 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1da177e4 1937
98b77773 1938 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1939}
1940
1941#if SMSC_IRCC2_C_SIR_STOP
1942void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1943{
1944 int iobase;
1945
a97a6f10 1946 IRDA_DEBUG(3, "%s\n", __func__);
1da177e4
LT		 1947 iobase = self->io.sir_base;
1948
1949 /* Reset UART */
98b77773 1950 outb(0, iobase + UART_MCR);
527b6af4 1951
1da177e4 1952 /* Turn off interrupts */
98b77773 1953 outb(0, iobase + UART_IER);
1da177e4
LT		 1954}
1955#endif
1956
1957/*
1958 * Function smsc_sir_write_wakeup (self)
1959 *
1960 * Called by the SIR interrupt handler when there's room for more data.
1961 * If we have more packets to send, we send them here.
1962 *
1963 */
1964static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1965{
1966 int actual = 0;
1967 int iobase;
1968 int fcr;
1969
1970 IRDA_ASSERT(self != NULL, return;);
1971
a97a6f10 1972 IRDA_DEBUG(4, "%s\n", __func__);
1da177e4
LT		 1973
1974 iobase = self->io.sir_base;
1975
1976 /* Finished with frame? */
1977 if (self->tx_buff.len > 0) {
1978 /* Write data left in transmit buffer */
527b6af4 1979 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1980 self->tx_buff.data, self->tx_buff.len);
1981 self->tx_buff.data += actual;
1982 self->tx_buff.len -= actual;
1983 } else {
527b6af4 1984
1da177e4 1985 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1986
1987 /*
1988 * Now serial buffer is almost free & we can start
1da177e4
LT		 1989 * transmission of another packet. But first we must check
1990 * if we need to change the speed of the hardware
1991 */
1992 if (self->new_speed) {
1993 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
a97a6f10 1994 __func__, self->new_speed);
1da177e4
LT		 1995 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1996 smsc_ircc_change_speed(self, self->new_speed);
1997 self->new_speed = 0;
1998 } else {
1999 /* Tell network layer that we want more frames */
2000 netif_wake_queue(self->netdev);
2001 }
af049081 2002 self->netdev->stats.tx_packets++;
1da177e4 2003
98b77773
DT		 2004 if (self->io.speed <= 115200) {
2005 /*
2006 * Reset Rx FIFO to make sure that all reflected transmit data
2007 * is discarded. This is needed for half duplex operation
2008 */
2009 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2010 fcr |= self->io.speed < 38400 ?
2011 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 2012
98b77773 2013 outb(fcr, iobase + UART_FCR);
1da177e4 2014
98b77773
DT		 2015 /* Turn on receive interrupts */
2016 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 2017 }
2018 }
2019}
2020
2021/*
2022 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2023 *
2024 * Fill Tx FIFO with transmit data
2025 *
2026 */
2027static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2028{
2029 int actual = 0;
527b6af4 2030
1da177e4 2031 /* Tx FIFO should be empty! */
98b77773 2032 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
a97a6f10 2033 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
1da177e4
LT		 2034 return 0;
2035 }
527b6af4 2036
1da177e4 2037 /* Fill FIFO with current frame */
98b77773 2038 while (fifo_size-- > 0 && actual < len) {
1da177e4 2039 /* Transmit next byte */
98b77773 2040 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 2041 actual++;
2042 }
2043 return actual;
2044}
2045
2046/*
2047 * Function smsc_ircc_is_receiving (self)
2048 *
2049 * Returns true is we are currently receiving data
2050 *
2051 */
2052static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2053{
2054 return (self->rx_buff.state != OUTSIDE_FRAME);
2055}
2056
2057
2058/*
2059 * Function smsc_ircc_probe_transceiver(self)
2060 *
2061 * Tries to find the used Transceiver
2062 *
2063 */
2064static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2065{
2066 unsigned int i;
527b6af4 2067
1da177e4 2068 IRDA_ASSERT(self != NULL, return;);
527b6af4 2069
98b77773
DT		 2070 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2071 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2072 IRDA_MESSAGE(" %s transceiver found\n",
2073 smsc_transceivers[i].name);
98b77773 2074 self->transceiver= i + 1;
1da177e4
LT		 2075 return;
2076 }
98b77773 2077
1da177e4
LT		 2078 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2079 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2080
98b77773 2081 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2082}
2083
2084
2085/*
2086 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2087 *
2088 * Set the transceiver according to the speed
2089 *
2090 */
2091static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2092{
2093 unsigned int trx;
527b6af4 2094
1da177e4 2095 trx = self->transceiver;
98b77773
DT		 2096 if (trx > 0)
2097 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2098}
2099
2100/*
2101 * Function smsc_ircc_wait_hw_transmitter_finish ()
2102 *
2103 * Wait for the real end of HW transmission
2104 *
2105 * The UART is a strict FIFO, and we get called only when we have finished
2106 * pushing data to the FIFO, so the maximum amount of time we must wait
2107 * is only for the FIFO to drain out.
2108 *
2109 * We use a simple calibrated loop. We may need to adjust the loop
2110 * delay (udelay) to balance I/O traffic and latency. And we also need to
2111 * adjust the maximum timeout.
2112 * It would probably be better to wait for the proper interrupt,
2113 * but it doesn't seem to be available.
2114 *
2115 * We can't use jiffies or kernel timers because :
2116 * 1) We are called from the interrupt handler, which disable softirqs,
2117 * so jiffies won't be increased
2118 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2119 * want to wait that long to detect stuck hardware.
2120 * Jean II
2121 */
2122
2123static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2124{
98b77773 2125 int iobase = self->io.sir_base;
1da177e4 2126 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2127
1da177e4 2128 /* Calibrated busy loop */
98b77773 2129 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2130 udelay(1);
2131
adbf7f01 2132 if (count < 0)
a97a6f10 2133 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
1da177e4
LT		 2134}
2135
2136
2137/* PROBING
2138 *
d94c77b9
DB		 2139 * REVISIT we can be told about the device by PNP, and should use that info
2140 * instead of probing hardware and creating a platform_device ...
1da177e4
LT		 2141 */
2142
2143static int __init smsc_ircc_look_for_chips(void)
2144{
b6158d23 2145 struct smsc_chip_address *address;
98b77773 2146 char *type;
1da177e4 2147 unsigned int cfg_base, found;
527b6af4 2148
1da177e4
LT		 2149 found = 0;
2150 address = possible_addresses;
527b6af4 2151
98b77773 2152 while (address->cfg_base) {
1da177e4 2153 cfg_base = address->cfg_base;
527b6af4 2154
a97a6f10 2155 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
527b6af4 2156
98b77773 2157 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2158 type = "FDC";
98b77773
DT		 2159 if (address->type & SMSCSIO_TYPE_FLAT)
2160 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2161 found++;
2162
2163 if (address->type & SMSCSIO_TYPE_PAGED)
2164 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2165 found++;
1da177e4 2166 }
98b77773 2167 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2168 type = "LPC";
98b77773
DT		 2169 if (address->type & SMSCSIO_TYPE_FLAT)
2170 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2171 found++;
2172
2173 if (address->type & SMSCSIO_TYPE_PAGED)
2174 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2175 found++;
1da177e4
LT		 2176 }
2177 address++;
2178 }
2179 return found;
527b6af4 2180}
1da177e4
LT		 2181
2182/*
2183 * Function smsc_superio_flat (chip, base, type)
2184 *
2185 * Try to get configuration of a smc SuperIO chip with flat register model
2186 *
2187 */
b6158d23 2188static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2189{
2190 unsigned short firbase, sirbase;
2191 u8 mode, dma, irq;
2192 int ret = -ENODEV;
2193
a97a6f10 2194 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2195
98b77773 2196 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2197 return ret;
2198
2199 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2200 mode = inb(cfgbase + 1);
527b6af4 2201
a97a6f10 2202 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
527b6af4 2203
98b77773 2204 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
a97a6f10 2205 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
1da177e4
LT		 2206
2207 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2208 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2209
527b6af4 2210 /* FIR iobase */
1da177e4 2211 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2212 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2213
2214 /* DMA */
2215 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2216 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2217
1da177e4
LT		 2218 /* IRQ */
2219 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2220 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4 2221
a97a6f10 2222 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
1da177e4 2223
98b77773
DT		 2224 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2225 ret = 0;
527b6af4 2226
1da177e4
LT		 2227 /* Exit configuration */
2228 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2229
2230 return ret;
2231}
2232
2233/*
2234 * Function smsc_superio_paged (chip, base, type)
2235 *
2236 * Try to get configuration of a smc SuperIO chip with paged register model
2237 *
2238 */
b6158d23 2239static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2240{
2241 unsigned short fir_io, sir_io;
2242 int ret = -ENODEV;
527b6af4 2243
a97a6f10 2244 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4 2245
98b77773 2246 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2247 return ret;
527b6af4 2248
1da177e4
LT		 2249 /* Select logical device (UART2) */
2250 outb(0x07, cfg_base);
2251 outb(0x05, cfg_base + 1);
527b6af4 2252
1da177e4
LT		 2253 /* SIR iobase */
2254 outb(0x60, cfg_base);
98b77773 2255 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2256 outb(0x61, cfg_base);
2257 sir_io |= inb(cfg_base + 1);
527b6af4 2258
1da177e4
LT		 2259 /* Read FIR base */
2260 outb(0x62, cfg_base);
2261 fir_io = inb(cfg_base + 1) << 8;
2262 outb(0x63, cfg_base);
2263 fir_io |= inb(cfg_base + 1);
2264 outb(0x2b, cfg_base); /* ??? */
2265
98b77773
DT		 2266 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2267 ret = 0;
527b6af4 2268
1da177e4
LT		 2269 /* Exit configuration */
2270 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2271
2272 return ret;
2273}
2274
2275
98b77773 2276static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4 2277{
a97a6f10 2278 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2279
2280 outb(reg, cfg_base);
98b77773 2281 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2282}
2283
b6158d23 2284static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2285{
98b77773 2286 u8 devid, xdevid, rev;
1da177e4 2287
a97a6f10 2288 IRDA_DEBUG(1, "%s\n", __func__);
1da177e4
LT		 2289
2290 /* Leave configuration */
2291
2292 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2293
2294 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2295 return NULL;
2296
2297 outb(reg, cfg_base);
2298
98b77773 2299 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2300
2301 /* Enter configuration */
2302
2303 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2304
2305 #if 0
2306 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2307 return NULL;
2308 #endif
527b6af4 2309
1da177e4
LT		 2310 /* probe device ID */
2311
98b77773 2312 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2313 return NULL;
2314
98b77773 2315 devid = inb(cfg_base + 1);
527b6af4 2316
98b77773 2317 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2318 return NULL;
2319
2320 /* probe revision ID */
2321
98b77773 2322 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2323 return NULL;
2324
98b77773 2325 rev = inb(cfg_base + 1);
1da177e4 2326
98b77773 2327 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2328 return NULL;
2329
98b77773 2330 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2331 return NULL;
2332
2333 /* Check for expected device ID; are there others? */
2334
98b77773 2335 while (chip->devid != devid) {
1da177e4
LT		 2336
2337 chip++;
2338
98b77773 2339 if (chip->name == NULL)
1da177e4
LT		 2340 return NULL;
2341 }
2342
98b77773
DT		 2343 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2344 devid, rev, cfg_base, type, chip->name);
1da177e4 2345
98b77773 2346 if (chip->rev > rev) {
527b6af4 2347 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2348 return NULL;
2349 }
527b6af4 2350
98b77773 2351 if (chip->flags & NoIRDA)
1da177e4
LT		 2352 IRDA_MESSAGE("chipset does not support IRDA\n");
2353
2354 return chip;
2355}
2356
2357static int __init smsc_superio_fdc(unsigned short cfg_base)
2358{
2359 int ret = -1;
2360
2361 if (!request_region(cfg_base, 2, driver_name)) {
2362 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2363 __func__, cfg_base);
1da177e4 2364 } else {
98b77773
DT		 2365 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2366 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2367 ret = 0;
2368
2369 release_region(cfg_base, 2);
2370 }
2371
2372 return ret;
2373}
2374
2375static int __init smsc_superio_lpc(unsigned short cfg_base)
2376{
2377 int ret = -1;
2378
2379 if (!request_region(cfg_base, 2, driver_name)) {
2380 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
a97a6f10 2381 __func__, cfg_base);
1da177e4 2382 } else {
98b77773
DT		 2383 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2384 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2385 ret = 0;
98b77773 2386
1da177e4
LT		 2387 release_region(cfg_base, 2);
2388 }
2389 return ret;
2390}
2391
c1e14a6e
LW		 2392/*
2393 * Look for some specific subsystem setups that need
2394 * pre-configuration not properly done by the BIOS (especially laptops)
2395 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2396 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2397 * for ISA bridges with an LPC (Low Pin Count) controller which
2398 * handles the communication with the SMSC device. After the LPC
2399 * controller is initialized through PCI, the SMSC device is initialized
2400 * through a dedicated port in the ISA port-mapped I/O area, this latter
2401 * area is used to configure the SMSC device with default
2402 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2403 * used different sets of parameters and different control port
2404 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2405 */
2406#ifdef CONFIG_PCI
2407#define PCIID_VENDOR_INTEL 0x8086
2408#define PCIID_VENDOR_ALI 0x10b9
c5d965ca 2409static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
895de090
LWLE		 2410 /*
2411 * Subsystems needing entries:
2412 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2413 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2414 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2415 */
2416 {
2417 /* Guessed entry */
2418 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2419 .device = 0x24cc,
2420 .subvendor = 0x103c,
2421 .subdevice = 0x08bc,
2422 .sir_io = 0x02f8,
2423 .fir_io = 0x0130,
2424 .fir_irq = 0x05,
2425 .fir_dma = 0x03,
2426 .cfg_base = 0x004e,
2427 .preconfigure = preconfigure_through_82801,
2428 .name = "HP nx5000 family",
2429 },
c1e14a6e
LW		 2430 {
2431 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2432 .device = 0x24cc,
2433 .subvendor = 0x103c,
2434 .subdevice = 0x088c,
08d09997
LW		 2435 /* Quite certain these are the same for nc8000 as for nc6000 */
2436 .sir_io = 0x02f8,
c1e14a6e 2437 .fir_io = 0x0130,
08d09997 2438 .fir_irq = 0x05,
c1e14a6e
LW		 2439 .fir_dma = 0x03,
2440 .cfg_base = 0x004e,
2441 .preconfigure = preconfigure_through_82801,
895de090 2442 .name = "HP nc8000 family",
c1e14a6e
LW		 2443 },
2444 {
2445 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2446 .device = 0x24cc,
2447 .subvendor = 0x103c,
2448 .subdevice = 0x0890,
2449 .sir_io = 0x02f8,
2450 .fir_io = 0x0130,
08d09997 2451 .fir_irq = 0x05,
c1e14a6e
LW		 2452 .fir_dma = 0x03,
2453 .cfg_base = 0x004e,
2454 .preconfigure = preconfigure_through_82801,
895de090
LWLE		 2455 .name = "HP nc6000 family",
2456 },
2457 {
2458 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2459 .device = 0x24cc,
2460 .subvendor = 0x0e11,
2461 .subdevice = 0x0860,
2462 /* I assume these are the same for x1000 as for the others */
2463 .sir_io = 0x02e8,
2464 .fir_io = 0x02f8,
2465 .fir_irq = 0x07,
2466 .fir_dma = 0x03,
2467 .cfg_base = 0x002e,
2468 .preconfigure = preconfigure_through_82801,
2469 .name = "Compaq x1000 family",
c1e14a6e
LW		 2470 },
2471 {
08d09997
LW		 2472 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2473 .vendor = PCIID_VENDOR_INTEL,
c1e14a6e
LW		 2474 .device = 0x24c0,
2475 .subvendor = 0x1179,
08d09997 2476 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2477 .sir_io = 0x03f8,
2478 .fir_io = 0x0130,
2479 .fir_irq = 0x07,
2480 .fir_dma = 0x01,
2481 .cfg_base = 0x002e,
2482 .preconfigure = preconfigure_through_82801,
08d09997 2483 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2484 },
2485 {
2486 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2487 .device = 0x248c,
c1e14a6e 2488 .subvendor = 0x1179,
08d09997 2489 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2490 .sir_io = 0x03f8,
2491 .fir_io = 0x0130,
2492 .fir_irq = 0x03,
2493 .fir_dma = 0x03,
2494 .cfg_base = 0x002e,
2495 .preconfigure = preconfigure_through_82801,
08d09997 2496 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2497 },
2498 {
08d09997
LW		 2499 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2500 .vendor = PCIID_VENDOR_INTEL,
2501 .device = 0x24cc,
2502 .subvendor = 0x1179,
2503 .subdevice = 0xffff, /* 0xffff is "any" */
2504 .sir_io = 0x03f8,
2505 .fir_io = 0x0130,
2506 .fir_irq = 0x03,
2507 .fir_dma = 0x03,
2508 .cfg_base = 0x002e,
2509 .preconfigure = preconfigure_through_82801,
2510 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2511 },
2512 {
2513 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2514 .vendor = PCIID_VENDOR_ALI,
c1e14a6e
LW		 2515 .device = 0x1533,
2516 .subvendor = 0x1179,
08d09997 2517 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2518 .sir_io = 0x02e8,
2519 .fir_io = 0x02f8,
2520 .fir_irq = 0x07,
2521 .fir_dma = 0x03,
2522 .cfg_base = 0x002e,
2523 .preconfigure = preconfigure_through_ali,
08d09997 2524 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2525 },
2526 { } // Terminator
2527};
2528
2529
2530/*
08d09997
LW		 2531 * This sets up the basic SMSC parameters
2532 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2533 * through the chip configuration port.
2534 */
08d09997
LW		 2535static int __init preconfigure_smsc_chip(struct
2536 smsc_ircc_subsystem_configuration
2537 *conf)
c1e14a6e
LW		 2538{
2539 unsigned short iobase = conf->cfg_base;
2540 unsigned char tmpbyte;
2541
2542 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2543 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2544 tmpbyte = inb(iobase +1); // Read device ID
08d09997
LW		 2545 IRDA_DEBUG(0,
2546 "Detected Chip id: 0x%02x, setting up registers...\n",
2547 tmpbyte);
c1e14a6e
LW		 2548
2549 /* Disable UART1 and set up SIR I/O port */
2550 outb(0x24, iobase); // select CR24 - UART1 base addr
2551 outb(0x00, iobase + 1); // disable UART1
2552 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2553 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2554 tmpbyte = inb(iobase + 1);
2555 if (tmpbyte != (conf->sir_io >> 2) ) {
2556 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
08d09997 2557 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
c1e14a6e
LW		 2558 return -ENXIO;
2559 }
2560
2561 /* Set up FIR IRQ channel for UART2 */
2562 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2563 tmpbyte = inb(iobase + 1);
2564 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2565 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2566 outb(tmpbyte, iobase + 1);
2567 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2568 if (tmpbyte != conf->fir_irq) {
2569 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2570 return -ENXIO;
2571 }
2572
2573 /* Set up FIR I/O port */
2574 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2575 outb((conf->fir_io >> 3), iobase + 1);
2576 tmpbyte = inb(iobase + 1);
2577 if (tmpbyte != (conf->fir_io >> 3) ) {
2578 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2579 return -ENXIO;
2580 }
2581
2582 /* Set up FIR DMA channel */
2583 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2584 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2585 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2586 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2587 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2588 return -ENXIO;
2589 }
2590
2591 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2592 tmpbyte = inb(iobase + 1);
08d09997
LW		 2593 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2594 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2595 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2596
2597 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2598 tmpbyte = inb(iobase + 1);
2599 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2600
2601 /* This one was not part of tosh1800 */
2602 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2603 tmpbyte = inb(iobase + 1);
2604 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2605
2606 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2607 tmpbyte = inb(iobase + 1);
2608 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2609
2610 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2611 tmpbyte = inb(iobase + 1);
2612 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2613
2614 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2615
2616 return 0;
2617}
2618
08d09997 2619/* 82801CAM generic registers */
c1e14a6e
LW		 2620#define VID 0x00
2621#define DID 0x02
08d09997
LW		 2622#define PIRQ_A_D_ROUT 0x60
2623#define SIRQ_CNTL 0x64
2624#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2625#define PCI_DMA_C 0x90
08d09997 2626/* LPC-specific registers */
c1e14a6e 2627#define COM_DEC 0xe0
08d09997 2628#define GEN1_DEC 0xe4
c1e14a6e
LW		 2629#define LPC_EN 0xe6
2630#define GEN2_DEC 0xec
2631/*
08d09997
LW		 2632 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2633 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2634 * They all work the same way!
c1e14a6e
LW		 2635 */
2636static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2637 struct
2638 smsc_ircc_subsystem_configuration
2639 *conf)
c1e14a6e
LW		 2640{
2641 unsigned short tmpword;
08d09997 2642 unsigned char tmpbyte;
c1e14a6e 2643
08d09997
LW		 2644 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2645 /*
2646 * Select the range for the COMA COM port (SIR)
2647 * Register COM_DEC:
2648 * Bit 7: reserved
2649 * Bit 6-4, COMB decode range
2650 * Bit 3: reserved
2651 * Bit 2-0, COMA decode range
2652 *
2653 * Decode ranges:
2654 * 000 = 0x3f8-0x3ff (COM1)
2655 * 001 = 0x2f8-0x2ff (COM2)
2656 * 010 = 0x220-0x227
2657 * 011 = 0x228-0x22f
2658 * 100 = 0x238-0x23f
2659 * 101 = 0x2e8-0x2ef (COM4)
2660 * 110 = 0x338-0x33f
2661 * 111 = 0x3e8-0x3ef (COM3)
2662 */
2663 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2664 tmpbyte &= 0xf8; /* mask COMA bits */
2665 switch(conf->sir_io) {
2666 case 0x3f8:
2667 tmpbyte |= 0x00;
2668 break;
2669 case 0x2f8:
2670 tmpbyte |= 0x01;
2671 break;
2672 case 0x220:
2673 tmpbyte |= 0x02;
2674 break;
2675 case 0x228:
2676 tmpbyte |= 0x03;
2677 break;
2678 case 0x238:
2679 tmpbyte |= 0x04;
2680 break;
2681 case 0x2e8:
2682 tmpbyte |= 0x05;
2683 break;
2684 case 0x338:
2685 tmpbyte |= 0x06;
2686 break;
2687 case 0x3e8:
2688 tmpbyte |= 0x07;
2689 break;
2690 default:
2691 tmpbyte |= 0x01; /* COM2 default */
2692 }
2693 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2694 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2695
08d09997
LW		 2696 /* Enable Low Pin Count interface */
2697 pci_read_config_word(dev, LPC_EN, &tmpword);
2698 /* These seem to be set up at all times,
2699 * just make sure it is properly set.
2700 */
2701 switch(conf->cfg_base) {
2702 case 0x04e:
2703 tmpword |= 0x2000;
2704 break;
2705 case 0x02e:
2706 tmpword |= 0x1000;
2707 break;
2708 case 0x062:
2709 tmpword |= 0x0800;
2710 break;
2711 case 0x060:
2712 tmpword |= 0x0400;
2713 break;
2714 default:
2715 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2716 conf->cfg_base);
2717 break;
2718 }
2719 tmpword &= 0xfffd; /* disable LPC COMB */
2720 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2721 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2722 pci_write_config_word(dev, LPC_EN, tmpword);
2723
08d09997
LW		 2724 /*
2725 * Configure LPC DMA channel
2726 * PCI_DMA_C bits:
2727 * Bit 15-14: DMA channel 7 select
2728 * Bit 13-12: DMA channel 6 select
2729 * Bit 11-10: DMA channel 5 select
2730 * Bit 9-8: Reserved
2731 * Bit 7-6: DMA channel 3 select
2732 * Bit 5-4: DMA channel 2 select
2733 * Bit 3-2: DMA channel 1 select
2734 * Bit 1-0: DMA channel 0 select
2735 * 00 = Reserved value
2736 * 01 = PC/PCI DMA
2737 * 10 = Reserved value
2738 * 11 = LPC I/F DMA
2739 */
2740 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2741 switch(conf->fir_dma) {
2742 case 0x07:
2743 tmpword |= 0xc000;
2744 break;
2745 case 0x06:
2746 tmpword |= 0x3000;
2747 break;
2748 case 0x05:
2749 tmpword |= 0x0c00;
2750 break;
2751 case 0x03:
2752 tmpword |= 0x00c0;
2753 break;
2754 case 0x02:
2755 tmpword |= 0x0030;
2756 break;
2757 case 0x01:
2758 tmpword |= 0x000c;
2759 break;
2760 case 0x00:
2761 tmpword |= 0x0003;
2762 break;
2763 default:
2764 break; /* do not change settings */
2765 }
2766 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2767 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2768
2769 /*
2770 * GEN2_DEC bits:
2771 * Bit 15-4: Generic I/O range
2772 * Bit 3-1: reserved (read as 0)
2773 * Bit 0: enable GEN2 range on LPC I/F
2774 */
2775 tmpword = conf->fir_io & 0xfff8;
2776 tmpword |= 0x0001;
2777 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2778 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2779
2780 /* Pre-configure chip */
08d09997
LW		 2781 return preconfigure_smsc_chip(conf);
2782}
c1e14a6e 2783
08d09997
LW		 2784/*
2785 * Pre-configure a certain port on the ALi 1533 bridge.
2786 * This is based on reverse-engineering since ALi does not
2787 * provide any data sheet for the 1533 chip.
2788 */
2789static void __init preconfigure_ali_port(struct pci_dev *dev,
2790 unsigned short port)
2791{
2792 unsigned char reg;
2793 /* These bits obviously control the different ports */
2794 unsigned char mask;
2795 unsigned char tmpbyte;
2796
2797 switch(port) {
2798 case 0x0130:
2799 case 0x0178:
2800 reg = 0xb0;
2801 mask = 0x80;
2802 break;
2803 case 0x03f8:
2804 reg = 0xb4;
2805 mask = 0x80;
2806 break;
2807 case 0x02f8:
2808 reg = 0xb4;
2809 mask = 0x30;
2810 break;
2811 case 0x02e8:
2812 reg = 0xb4;
2813 mask = 0x08;
2814 break;
2815 default:
2816 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2817 return;
2818 }
2819
2820 pci_read_config_byte(dev, reg, &tmpbyte);
2821 /* Turn on the right bits */
2822 tmpbyte |= mask;
2823 pci_write_config_byte(dev, reg, tmpbyte);
2824 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2825 return;
c1e14a6e
LW		 2826}
2827
2828static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2829 struct
2830 smsc_ircc_subsystem_configuration
2831 *conf)
c1e14a6e 2832{
08d09997
LW		 2833 /* Configure the two ports on the ALi 1533 */
2834 preconfigure_ali_port(dev, conf->sir_io);
2835 preconfigure_ali_port(dev, conf->fir_io);
2836
2837 /* Pre-configure chip */
2838 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2839}
2840
2841static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2842 unsigned short ircc_fir,
2843 unsigned short ircc_sir,
2844 unsigned char ircc_dma,
2845 unsigned char ircc_irq)
2846{
2847 struct pci_dev *dev = NULL;
2848 unsigned short ss_vendor = 0x0000;
2849 unsigned short ss_device = 0x0000;
2850 int ret = 0;
2851
2852 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2853
2854 while (dev != NULL) {
2855 struct smsc_ircc_subsystem_configuration *conf;
2856
2857 /*
08d09997
LW		 2858 * Cache the subsystem vendor/device:
2859 * some manufacturers fail to set this for all components,
2860 * so we save it in case there is just 0x0000 0x0000 on the
2861 * device we want to check.
c1e14a6e
LW		 2862 */
2863 if (dev->subsystem_vendor != 0x0000U) {
2864 ss_vendor = dev->subsystem_vendor;
2865 ss_device = dev->subsystem_device;
2866 }
2867 conf = subsystem_configurations;
2868 for( ; conf->subvendor; conf++) {
2869 if(conf->vendor == dev->vendor &&
2870 conf->device == dev->device &&
08d09997
LW		 2871 conf->subvendor == ss_vendor &&
2872 /* Sometimes these are cached values */
2873 (conf->subdevice == ss_device ||
2874 conf->subdevice == 0xffff)) {
2875 struct smsc_ircc_subsystem_configuration
2876 tmpconf;
c1e14a6e 2877
08d09997
LW		 2878 memcpy(&tmpconf, conf,
2879 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2880
08d09997
LW		 2881 /*
2882 * Override the default values with anything
2883 * passed in as parameter
2884 */
c1e14a6e
LW		 2885 if (ircc_cfg != 0)
2886 tmpconf.cfg_base = ircc_cfg;
2887 if (ircc_fir != 0)
2888 tmpconf.fir_io = ircc_fir;
2889 if (ircc_sir != 0)
2890 tmpconf.sir_io = ircc_sir;
916f11c7 2891 if (ircc_dma != DMA_INVAL)
c1e14a6e 2892 tmpconf.fir_dma = ircc_dma;
916f11c7 2893 if (ircc_irq != IRQ_INVAL)
c1e14a6e
LW		 2894 tmpconf.fir_irq = ircc_irq;
2895
2896 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2897 if (conf->preconfigure)
2898 ret = conf->preconfigure(dev, &tmpconf);
2899 else
2900 ret = -ENODEV;
2901 }
2902 }
2903 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2904 }
2905
2906 return ret;
2907}
2908#endif // CONFIG_PCI
2909
1da177e4
LT		 2910/************************************************
2911 *
2912 * Transceivers specific functions
2913 *
2914 ************************************************/
2915
2916
2917/*
2918 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2919 *
2920 * Program transceiver through smsc-ircc ATC circuitry
2921 *
2922 */
2923
2924static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2925{
2926 unsigned long jiffies_now, jiffies_timeout;
98b77773 2927 u8 val;
527b6af4 2928
98b77773
DT		 2929 jiffies_now = jiffies;
2930 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2931
1da177e4
LT		 2932 /* ATC */
2933 register_bank(fir_base, 4);
98b77773
DT		 2934 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2935 fir_base + IRCC_ATC);
2936
2937 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2938 !time_after(jiffies, jiffies_timeout))
2939 /* empty */;
2940
2941 if (val)
a97a6f10 2942 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
98b77773 2943 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2944}
2945
2946/*
2947 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2948 *
2949 * Probe transceiver smsc-ircc ATC circuitry
2950 *
2951 */
2952
2953static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2954{
2955 return 0;
2956}
2957
2958/*
2959 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2960 *
527b6af4 2961 * Set transceiver
1da177e4
LT		 2962 *
2963 */
2964
2965static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2966{
98b77773 2967 u8 fast_mode;
527b6af4 2968
98b77773
DT		 2969 switch (speed) {
2970 default:
2971 case 576000 :
527b6af4 2972 fast_mode = 0;
1da177e4 2973 break;
98b77773
DT		 2974 case 1152000 :
2975 case 4000000 :
1da177e4
LT		 2976 fast_mode = IRCC_LCR_A_FAST;
2977 break;
1da177e4
LT		 2978 }
2979 register_bank(fir_base, 0);
98b77773 2980 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2981}
2982
2983/*
2984 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2985 *
527b6af4 2986 * Probe transceiver
1da177e4
LT		 2987 *
2988 */
2989
2990static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2991{
2992 return 0;
2993}
2994
2995/*
2996 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2997 *
527b6af4 2998 * Set transceiver
1da177e4
LT		 2999 *
3000 */
3001
3002static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
3003{
98b77773 3004 u8 fast_mode;
527b6af4 3005
98b77773
DT		 3006 switch (speed) {
3007 default:
3008 case 576000 :
527b6af4 3009 fast_mode = 0;
1da177e4 3010 break;
98b77773
DT		 3011 case 1152000 :
3012 case 4000000 :
1da177e4
LT		 3013 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3014 break;
527b6af4 3015
1da177e4
LT		 3016 }
3017 /* This causes an interrupt */
3018 register_bank(fir_base, 0);
98b77773 3019 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 3020}
3021
3022/*
3023 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3024 *
527b6af4 3025 * Probe transceiver
1da177e4
LT		 3026 *
3027 */
3028
3029static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3030{
3031 return 0;
3032}
3033
3034
3035module_init(smsc_ircc_init);
3036module_exit(smsc_ircc_cleanup);
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