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igb: remove redundant count set and err_hw_init
[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 692 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
fa4dfae0
AD		 891 switch (mac->type) {
892 case e1000_82576:
2d064c06 893 pba = E1000_PBA_64K;
fa4dfae0
AD		 894 break;
895 case e1000_82575:
896 default:
897 pba = E1000_PBA_34K;
898 break;
2d064c06 899 }
9d5c8243 900
2d064c06
AD		 901 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
902 (mac->type < e1000_82576)) {
9d5c8243
AK		 903 /* adjust PBA for jumbo frames */
904 wr32(E1000_PBA, pba);
905
906 /* To maintain wire speed transmits, the Tx FIFO should be
907 * large enough to accommodate two full transmit packets,
908 * rounded up to the next 1KB and expressed in KB. Likewise,
909 * the Rx FIFO should be large enough to accommodate at least
910 * one full receive packet and is similarly rounded up and
911 * expressed in KB. */
912 pba = rd32(E1000_PBA);
913 /* upper 16 bits has Tx packet buffer allocation size in KB */
914 tx_space = pba >> 16;
915 /* lower 16 bits has Rx packet buffer allocation size in KB */
916 pba &= 0xffff;
917 /* the tx fifo also stores 16 bytes of information about the tx
918 * but don't include ethernet FCS because hardware appends it */
919 min_tx_space = (adapter->max_frame_size +
920 sizeof(struct e1000_tx_desc) -
921 ETH_FCS_LEN) * 2;
922 min_tx_space = ALIGN(min_tx_space, 1024);
923 min_tx_space >>= 10;
924 /* software strips receive CRC, so leave room for it */
925 min_rx_space = adapter->max_frame_size;
926 min_rx_space = ALIGN(min_rx_space, 1024);
927 min_rx_space >>= 10;
928
929 /* If current Tx allocation is less than the min Tx FIFO size,
930 * and the min Tx FIFO size is less than the current Rx FIFO
931 * allocation, take space away from current Rx allocation */
932 if (tx_space < min_tx_space &&
933 ((min_tx_space - tx_space) < pba)) {
934 pba = pba - (min_tx_space - tx_space);
935
936 /* if short on rx space, rx wins and must trump tx
937 * adjustment */
938 if (pba < min_rx_space)
939 pba = min_rx_space;
940 }
2d064c06 941 wr32(E1000_PBA, pba);
9d5c8243 942 }
9d5c8243
AK		 943
944 /* flow control settings */
945 /* The high water mark must be low enough to fit one full frame
946 * (or the size used for early receive) above it in the Rx FIFO.
947 * Set it to the lower of:
948 * - 90% of the Rx FIFO size, or
949 * - the full Rx FIFO size minus one full frame */
950 hwm = min(((pba << 10) * 9 / 10),
2d064c06 951 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 952
2d064c06
AD		 953 if (mac->type < e1000_82576) {
954 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
955 fc->low_water = fc->high_water - 8;
956 } else {
957 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
958 fc->low_water = fc->high_water - 16;
959 }
9d5c8243
AK		 960 fc->pause_time = 0xFFFF;
961 fc->send_xon = 1;
962 fc->type = fc->original_type;
963
964 /* Allow time for pending master requests to run */
965 adapter->hw.mac.ops.reset_hw(&adapter->hw);
966 wr32(E1000_WUC, 0);
967
968 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
969 dev_err(&adapter->pdev->dev, "Hardware Error\n");
970
971 igb_update_mng_vlan(adapter);
972
973 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
974 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
975
976 igb_reset_adaptive(&adapter->hw);
f5f4cf08 977 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 978}
979
2e5c6922
SH		 980static const struct net_device_ops igb_netdev_ops = {
981 .ndo_open = igb_open,
982 .ndo_stop = igb_close,
00829823 983 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 984 .ndo_get_stats = igb_get_stats,
985 .ndo_set_multicast_list = igb_set_multi,
986 .ndo_set_mac_address = igb_set_mac,
987 .ndo_change_mtu = igb_change_mtu,
988 .ndo_do_ioctl = igb_ioctl,
989 .ndo_tx_timeout = igb_tx_timeout,
990 .ndo_validate_addr = eth_validate_addr,
991 .ndo_vlan_rx_register = igb_vlan_rx_register,
992 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
993 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
994#ifdef CONFIG_NET_POLL_CONTROLLER
995 .ndo_poll_controller = igb_netpoll,
996#endif
997};
998
9d5c8243
AK		 999/**
1000 * igb_probe - Device Initialization Routine
1001 * @pdev: PCI device information struct
1002 * @ent: entry in igb_pci_tbl
1003 *
1004 * Returns 0 on success, negative on failure
1005 *
1006 * igb_probe initializes an adapter identified by a pci_dev structure.
1007 * The OS initialization, configuring of the adapter private structure,
1008 * and a hardware reset occur.
1009 **/
1010static int __devinit igb_probe(struct pci_dev *pdev,
1011 const struct pci_device_id *ent)
1012{
1013 struct net_device *netdev;
1014 struct igb_adapter *adapter;
1015 struct e1000_hw *hw;
c54106bb 1016 struct pci_dev *us_dev;
9d5c8243
AK		 1017 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1018 unsigned long mmio_start, mmio_len;
450c87c8 1019 int err, pci_using_dac, pos;
c54106bb 1020 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1021 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1022 u32 part_num;
1023
aed5dec3 1024 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1025 if (err)
1026 return err;
1027
1028 pci_using_dac = 0;
1029 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1030 if (!err) {
1031 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1032 if (!err)
1033 pci_using_dac = 1;
1034 } else {
1035 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1036 if (err) {
1037 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1038 if (err) {
1039 dev_err(&pdev->dev, "No usable DMA "
1040 "configuration, aborting\n");
1041 goto err_dma;
1042 }
1043 }
1044 }
1045
c54106bb
AD		 1046 /* 82575 requires that the pci-e link partner disable the L0s state */
1047 switch (pdev->device) {
1048 case E1000_DEV_ID_82575EB_COPPER:
1049 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1050 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1051 us_dev = pdev->bus->self;
1052 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1053 if (pos) {
1054 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055 &state);
1056 state &= ~PCIE_LINK_STATE_L0S;
1057 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1058 state);
ac450208
BH		 1059 dev_info(&pdev->dev,
1060 "Disabling ASPM L0s upstream switch port %s\n",
1061 pci_name(us_dev));
c54106bb
AD		 1062 }
1063 default:
1064 break;
1065 }
1066
aed5dec3
AD		 1067 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1068 IORESOURCE_MEM),
1069 igb_driver_name);
9d5c8243
AK		 1070 if (err)
1071 goto err_pci_reg;
1072
ea943d41
JK		 1073 err = pci_enable_pcie_error_reporting(pdev);
1074 if (err) {
1075 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1076 "0x%x\n", err);
1077 /* non-fatal, continue */
1078 }
40a914fa 1079
9d5c8243 1080 pci_set_master(pdev);
c682fc23 1081 pci_save_state(pdev);
9d5c8243
AK		 1082
1083 err = -ENOMEM;
661086df 1084 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1085 if (!netdev)
1086 goto err_alloc_etherdev;
1087
1088 SET_NETDEV_DEV(netdev, &pdev->dev);
1089
1090 pci_set_drvdata(pdev, netdev);
1091 adapter = netdev_priv(netdev);
1092 adapter->netdev = netdev;
1093 adapter->pdev = pdev;
1094 hw = &adapter->hw;
1095 hw->back = adapter;
1096 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1097
1098 mmio_start = pci_resource_start(pdev, 0);
1099 mmio_len = pci_resource_len(pdev, 0);
1100
1101 err = -EIO;
28b0759c
AD		 1102 hw->hw_addr = ioremap(mmio_start, mmio_len);
1103 if (!hw->hw_addr)
9d5c8243
AK		 1104 goto err_ioremap;
1105
2e5c6922 1106 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1107 igb_set_ethtool_ops(netdev);
9d5c8243 1108 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1109
1110 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1111
1112 netdev->mem_start = mmio_start;
1113 netdev->mem_end = mmio_start + mmio_len;
1114
9d5c8243
AK		 1115 /* PCI config space info */
1116 hw->vendor_id = pdev->vendor;
1117 hw->device_id = pdev->device;
1118 hw->revision_id = pdev->revision;
1119 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1120 hw->subsystem_device_id = pdev->subsystem_device;
1121
1122 /* setup the private structure */
1123 hw->back = adapter;
1124 /* Copy the default MAC, PHY and NVM function pointers */
1125 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1126 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1127 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1128 /* Initialize skew-specific constants */
1129 err = ei->get_invariants(hw);
1130 if (err)
450c87c8 1131 goto err_sw_init;
9d5c8243 1132
450c87c8 1133 /* setup the private structure */
9d5c8243
AK		 1134 err = igb_sw_init(adapter);
1135 if (err)
1136 goto err_sw_init;
1137
1138 igb_get_bus_info_pcie(hw);
1139
7dfc16fa
AD		 1140 /* set flags */
1141 switch (hw->mac.type) {
7dfc16fa 1142 case e1000_82575:
7dfc16fa
AD		 1143 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1144 break;
bbd98fe4 1145 case e1000_82576:
7dfc16fa
AD		 1146 default:
1147 break;
1148 }
1149
9d5c8243
AK		 1150 hw->phy.autoneg_wait_to_complete = false;
1151 hw->mac.adaptive_ifs = true;
1152
1153 /* Copper options */
1154 if (hw->phy.media_type == e1000_media_type_copper) {
1155 hw->phy.mdix = AUTO_ALL_MODES;
1156 hw->phy.disable_polarity_correction = false;
1157 hw->phy.ms_type = e1000_ms_hw_default;
1158 }
1159
1160 if (igb_check_reset_block(hw))
1161 dev_info(&pdev->dev,
1162 "PHY reset is blocked due to SOL/IDER session.\n");
1163
1164 netdev->features = NETIF_F_SG |
7d8eb29e 1165 NETIF_F_IP_CSUM |
9d5c8243
AK		 1166 NETIF_F_HW_VLAN_TX |
1167 NETIF_F_HW_VLAN_RX |
1168 NETIF_F_HW_VLAN_FILTER;
1169
7d8eb29e 1170 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1171 netdev->features |= NETIF_F_TSO;
9d5c8243 1172 netdev->features |= NETIF_F_TSO6;
48f29ffc 1173
d3352520 1174#ifdef CONFIG_IGB_LRO
5c0999b7 1175 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1176#endif
1177
48f29ffc
JK		 1178 netdev->vlan_features |= NETIF_F_TSO;
1179 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1180 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1181 netdev->vlan_features |= NETIF_F_SG;
1182
9d5c8243
AK		 1183 if (pci_using_dac)
1184 netdev->features |= NETIF_F_HIGHDMA;
1185
9d5c8243
AK		 1186 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1187
1188 /* before reading the NVM, reset the controller to put the device in a
1189 * known good starting state */
1190 hw->mac.ops.reset_hw(hw);
1191
1192 /* make sure the NVM is good */
1193 if (igb_validate_nvm_checksum(hw) < 0) {
1194 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1195 err = -EIO;
1196 goto err_eeprom;
1197 }
1198
1199 /* copy the MAC address out of the NVM */
1200 if (hw->mac.ops.read_mac_addr(hw))
1201 dev_err(&pdev->dev, "NVM Read Error\n");
1202
1203 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1204 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1205
1206 if (!is_valid_ether_addr(netdev->perm_addr)) {
1207 dev_err(&pdev->dev, "Invalid MAC Address\n");
1208 err = -EIO;
1209 goto err_eeprom;
1210 }
1211
1212 init_timer(&adapter->watchdog_timer);
1213 adapter->watchdog_timer.function = &igb_watchdog;
1214 adapter->watchdog_timer.data = (unsigned long) adapter;
1215
1216 init_timer(&adapter->phy_info_timer);
1217 adapter->phy_info_timer.function = &igb_update_phy_info;
1218 adapter->phy_info_timer.data = (unsigned long) adapter;
1219
1220 INIT_WORK(&adapter->reset_task, igb_reset_task);
1221 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1222
450c87c8 1223 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1224 adapter->fc_autoneg = true;
1225 hw->mac.autoneg = true;
1226 hw->phy.autoneg_advertised = 0x2f;
1227
1228 hw->fc.original_type = e1000_fc_default;
1229 hw->fc.type = e1000_fc_default;
1230
1231 adapter->itr_setting = 3;
1232 adapter->itr = IGB_START_ITR;
1233
1234 igb_validate_mdi_setting(hw);
1235
1236 adapter->rx_csum = 1;
1237
1238 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1239 * enable the ACPI Magic Packet filter
1240 */
1241
1242 if (hw->bus.func == 0 ||
1243 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1244 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1245
1246 if (eeprom_data & eeprom_apme_mask)
1247 adapter->eeprom_wol |= E1000_WUFC_MAG;
1248
1249 /* now that we have the eeprom settings, apply the special cases where
1250 * the eeprom may be wrong or the board simply won't support wake on
1251 * lan on a particular port */
1252 switch (pdev->device) {
1253 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1254 adapter->eeprom_wol = 0;
1255 break;
1256 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1257 case E1000_DEV_ID_82576_FIBER:
1258 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1259 /* Wake events only supported on port A for dual fiber
1260 * regardless of eeprom setting */
1261 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1262 adapter->eeprom_wol = 0;
1263 break;
1264 }
1265
1266 /* initialize the wol settings based on the eeprom settings */
1267 adapter->wol = adapter->eeprom_wol;
e1b86d84 1268 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1269
1270 /* reset the hardware with the new settings */
1271 igb_reset(adapter);
1272
1273 /* let the f/w know that the h/w is now under the control of the
1274 * driver. */
1275 igb_get_hw_control(adapter);
1276
1277 /* tell the stack to leave us alone until igb_open() is called */
1278 netif_carrier_off(netdev);
fd2ea0a7 1279 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1280
1281 strcpy(netdev->name, "eth%d");
1282 err = register_netdev(netdev);
1283 if (err)
1284 goto err_register;
1285
421e02f0 1286#ifdef CONFIG_IGB_DCA
bbd98fe4 1287 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1288 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1289 dev_info(&pdev->dev, "DCA enabled\n");
1290 /* Always use CB2 mode, difference is masked
1291 * in the CB driver. */
1292 wr32(E1000_DCA_CTRL, 2);
1293 igb_setup_dca(adapter);
1294 }
1295#endif
1296
9d5c8243
AK		 1297 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1298 /* print bus type/speed/width info */
7c510e4b 1299 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1300 netdev->name,
1301 ((hw->bus.speed == e1000_bus_speed_2500)
1302 ? "2.5Gb/s" : "unknown"),
1303 ((hw->bus.width == e1000_bus_width_pcie_x4)
1304 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1305 ? "Width x1" : "unknown"),
7c510e4b 1306 netdev->dev_addr);
9d5c8243
AK		 1307
1308 igb_read_part_num(hw, &part_num);
1309 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1310 (part_num >> 8), (part_num & 0xff));
1311
1312 dev_info(&pdev->dev,
1313 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1314 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1315 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1316 adapter->num_rx_queues, adapter->num_tx_queues);
1317
9d5c8243
AK		 1318 return 0;
1319
1320err_register:
1321 igb_release_hw_control(adapter);
1322err_eeprom:
1323 if (!igb_check_reset_block(hw))
f5f4cf08 1324 igb_reset_phy(hw);
9d5c8243
AK		 1325
1326 if (hw->flash_address)
1327 iounmap(hw->flash_address);
1328
a88f10ec 1329 igb_free_queues(adapter);
9d5c8243 1330err_sw_init:
9d5c8243
AK		 1331 iounmap(hw->hw_addr);
1332err_ioremap:
1333 free_netdev(netdev);
1334err_alloc_etherdev:
aed5dec3
AD		 1335 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1336 IORESOURCE_MEM));
9d5c8243
AK		 1337err_pci_reg:
1338err_dma:
1339 pci_disable_device(pdev);
1340 return err;
1341}
1342
1343/**
1344 * igb_remove - Device Removal Routine
1345 * @pdev: PCI device information struct
1346 *
1347 * igb_remove is called by the PCI subsystem to alert the driver
1348 * that it should release a PCI device. The could be caused by a
1349 * Hot-Plug event, or because the driver is going to be removed from
1350 * memory.
1351 **/
1352static void __devexit igb_remove(struct pci_dev *pdev)
1353{
1354 struct net_device *netdev = pci_get_drvdata(pdev);
1355 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1356 struct e1000_hw *hw = &adapter->hw;
ea943d41 1357 int err;
9d5c8243
AK		 1358
1359 /* flush_scheduled work may reschedule our watchdog task, so
1360 * explicitly disable watchdog tasks from being rescheduled */
1361 set_bit(__IGB_DOWN, &adapter->state);
1362 del_timer_sync(&adapter->watchdog_timer);
1363 del_timer_sync(&adapter->phy_info_timer);
1364
1365 flush_scheduled_work();
1366
421e02f0 1367#ifdef CONFIG_IGB_DCA
7dfc16fa 1368 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1369 dev_info(&pdev->dev, "DCA disabled\n");
1370 dca_remove_requester(&pdev->dev);
7dfc16fa 1371 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1372 wr32(E1000_DCA_CTRL, 1);
1373 }
1374#endif
1375
9d5c8243
AK		 1376 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1377 * would have already happened in close and is redundant. */
1378 igb_release_hw_control(adapter);
1379
1380 unregister_netdev(netdev);
1381
f5f4cf08
AD		 1382 if (!igb_check_reset_block(&adapter->hw))
1383 igb_reset_phy(&adapter->hw);
9d5c8243 1384
9d5c8243
AK		 1385 igb_reset_interrupt_capability(adapter);
1386
a88f10ec 1387 igb_free_queues(adapter);
9d5c8243 1388
28b0759c
AD		 1389 iounmap(hw->hw_addr);
1390 if (hw->flash_address)
1391 iounmap(hw->flash_address);
aed5dec3
AD		 1392 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1393 IORESOURCE_MEM));
9d5c8243
AK		 1394
1395 free_netdev(netdev);
1396
ea943d41
JK		 1397 err = pci_disable_pcie_error_reporting(pdev);
1398 if (err)
1399 dev_err(&pdev->dev,
1400 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1401
9d5c8243
AK		 1402 pci_disable_device(pdev);
1403}
1404
1405/**
1406 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1407 * @adapter: board private structure to initialize
1408 *
1409 * igb_sw_init initializes the Adapter private data structure.
1410 * Fields are initialized based on PCI device information and
1411 * OS network device settings (MTU size).
1412 **/
1413static int __devinit igb_sw_init(struct igb_adapter *adapter)
1414{
1415 struct e1000_hw *hw = &adapter->hw;
1416 struct net_device *netdev = adapter->netdev;
1417 struct pci_dev *pdev = adapter->pdev;
1418
1419 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1420
68fd9910
AD		 1421 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1422 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1423 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1424 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1425 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1426 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1427
661086df
PWJ		 1428 /* This call may decrease the number of queues depending on
1429 * interrupt mode. */
9d5c8243
AK		 1430 igb_set_interrupt_capability(adapter);
1431
1432 if (igb_alloc_queues(adapter)) {
1433 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1434 return -ENOMEM;
1435 }
1436
1437 /* Explicitly disable IRQ since the NIC can be in any state. */
1438 igb_irq_disable(adapter);
1439
1440 set_bit(__IGB_DOWN, &adapter->state);
1441 return 0;
1442}
1443
1444/**
1445 * igb_open - Called when a network interface is made active
1446 * @netdev: network interface device structure
1447 *
1448 * Returns 0 on success, negative value on failure
1449 *
1450 * The open entry point is called when a network interface is made
1451 * active by the system (IFF_UP). At this point all resources needed
1452 * for transmit and receive operations are allocated, the interrupt
1453 * handler is registered with the OS, the watchdog timer is started,
1454 * and the stack is notified that the interface is ready.
1455 **/
1456static int igb_open(struct net_device *netdev)
1457{
1458 struct igb_adapter *adapter = netdev_priv(netdev);
1459 struct e1000_hw *hw = &adapter->hw;
1460 int err;
1461 int i;
1462
1463 /* disallow open during test */
1464 if (test_bit(__IGB_TESTING, &adapter->state))
1465 return -EBUSY;
1466
1467 /* allocate transmit descriptors */
1468 err = igb_setup_all_tx_resources(adapter);
1469 if (err)
1470 goto err_setup_tx;
1471
1472 /* allocate receive descriptors */
1473 err = igb_setup_all_rx_resources(adapter);
1474 if (err)
1475 goto err_setup_rx;
1476
1477 /* e1000_power_up_phy(adapter); */
1478
1479 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1480 if ((adapter->hw.mng_cookie.status &
1481 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1482 igb_update_mng_vlan(adapter);
1483
1484 /* before we allocate an interrupt, we must be ready to handle it.
1485 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1486 * as soon as we call pci_request_irq, so we have to setup our
1487 * clean_rx handler before we do so. */
1488 igb_configure(adapter);
1489
1490 err = igb_request_irq(adapter);
1491 if (err)
1492 goto err_req_irq;
1493
1494 /* From here on the code is the same as igb_up() */
1495 clear_bit(__IGB_DOWN, &adapter->state);
1496
844290e5
PW		 1497 for (i = 0; i < adapter->num_rx_queues; i++)
1498 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1499
1500 /* Clear any pending interrupts. */
1501 rd32(E1000_ICR);
844290e5
PW		 1502
1503 igb_irq_enable(adapter);
1504
d55b53ff
JK		 1505 netif_tx_start_all_queues(netdev);
1506
9d5c8243
AK		 1507 /* Fire a link status change interrupt to start the watchdog. */
1508 wr32(E1000_ICS, E1000_ICS_LSC);
1509
1510 return 0;
1511
1512err_req_irq:
1513 igb_release_hw_control(adapter);
1514 /* e1000_power_down_phy(adapter); */
1515 igb_free_all_rx_resources(adapter);
1516err_setup_rx:
1517 igb_free_all_tx_resources(adapter);
1518err_setup_tx:
1519 igb_reset(adapter);
1520
1521 return err;
1522}
1523
1524/**
1525 * igb_close - Disables a network interface
1526 * @netdev: network interface device structure
1527 *
1528 * Returns 0, this is not allowed to fail
1529 *
1530 * The close entry point is called when an interface is de-activated
1531 * by the OS. The hardware is still under the driver's control, but
1532 * needs to be disabled. A global MAC reset is issued to stop the
1533 * hardware, and all transmit and receive resources are freed.
1534 **/
1535static int igb_close(struct net_device *netdev)
1536{
1537 struct igb_adapter *adapter = netdev_priv(netdev);
1538
1539 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1540 igb_down(adapter);
1541
1542 igb_free_irq(adapter);
1543
1544 igb_free_all_tx_resources(adapter);
1545 igb_free_all_rx_resources(adapter);
1546
1547 /* kill manageability vlan ID if supported, but not if a vlan with
1548 * the same ID is registered on the host OS (let 8021q kill it) */
1549 if ((adapter->hw.mng_cookie.status &
1550 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1551 !(adapter->vlgrp &&
1552 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1553 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1554
1555 return 0;
1556}
1557
1558/**
1559 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1560 * @adapter: board private structure
1561 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1562 *
1563 * Return 0 on success, negative on failure
1564 **/
1565
1566int igb_setup_tx_resources(struct igb_adapter *adapter,
1567 struct igb_ring *tx_ring)
1568{
1569 struct pci_dev *pdev = adapter->pdev;
1570 int size;
1571
1572 size = sizeof(struct igb_buffer) * tx_ring->count;
1573 tx_ring->buffer_info = vmalloc(size);
1574 if (!tx_ring->buffer_info)
1575 goto err;
1576 memset(tx_ring->buffer_info, 0, size);
1577
1578 /* round up to nearest 4K */
0e014cb1 1579 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1580 tx_ring->size = ALIGN(tx_ring->size, 4096);
1581
1582 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1583 &tx_ring->dma);
1584
1585 if (!tx_ring->desc)
1586 goto err;
1587
1588 tx_ring->adapter = adapter;
1589 tx_ring->next_to_use = 0;
1590 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1591 return 0;
1592
1593err:
1594 vfree(tx_ring->buffer_info);
1595 dev_err(&adapter->pdev->dev,
1596 "Unable to allocate memory for the transmit descriptor ring\n");
1597 return -ENOMEM;
1598}
1599
1600/**
1601 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1602 * (Descriptors) for all queues
1603 * @adapter: board private structure
1604 *
1605 * Return 0 on success, negative on failure
1606 **/
1607static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1608{
1609 int i, err = 0;
661086df 1610 int r_idx;
9d5c8243
AK		 1611
1612 for (i = 0; i < adapter->num_tx_queues; i++) {
1613 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1614 if (err) {
1615 dev_err(&adapter->pdev->dev,
1616 "Allocation for Tx Queue %u failed\n", i);
1617 for (i--; i >= 0; i--)
3b644cf6 1618 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1619 break;
1620 }
1621 }
1622
661086df
PWJ		 1623 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1624 r_idx = i % adapter->num_tx_queues;
1625 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1626 }
9d5c8243
AK		 1627 return err;
1628}
1629
1630/**
1631 * igb_configure_tx - Configure transmit Unit after Reset
1632 * @adapter: board private structure
1633 *
1634 * Configure the Tx unit of the MAC after a reset.
1635 **/
1636static void igb_configure_tx(struct igb_adapter *adapter)
1637{
0e014cb1 1638 u64 tdba;
9d5c8243
AK		 1639 struct e1000_hw *hw = &adapter->hw;
1640 u32 tctl;
1641 u32 txdctl, txctrl;
26bc19ec 1642 int i, j;
9d5c8243
AK		 1643
1644 for (i = 0; i < adapter->num_tx_queues; i++) {
1645 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1646 j = ring->reg_idx;
1647 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1648 ring->count * sizeof(struct e1000_tx_desc));
1649 tdba = ring->dma;
26bc19ec 1650 wr32(E1000_TDBAL(j),
9d5c8243 1651 tdba & 0x00000000ffffffffULL);
26bc19ec 1652 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1653
26bc19ec
AD		 1654 ring->head = E1000_TDH(j);
1655 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1656 writel(0, hw->hw_addr + ring->tail);
1657 writel(0, hw->hw_addr + ring->head);
26bc19ec 1658 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1659 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1660 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1661
1662 /* Turn off Relaxed Ordering on head write-backs. The
1663 * writebacks MUST be delivered in order or it will
1664 * completely screw up our bookeeping.
1665 */
26bc19ec 1666 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1667 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1668 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1669 }
1670
1671
1672
1673 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1674
1675 /* Program the Transmit Control Register */
1676
1677 tctl = rd32(E1000_TCTL);
1678 tctl &= ~E1000_TCTL_CT;
1679 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1680 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1681
1682 igb_config_collision_dist(hw);
1683
1684 /* Setup Transmit Descriptor Settings for eop descriptor */
1685 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1686
1687 /* Enable transmits */
1688 tctl |= E1000_TCTL_EN;
1689
1690 wr32(E1000_TCTL, tctl);
1691}
1692
1693/**
1694 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1695 * @adapter: board private structure
1696 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1697 *
1698 * Returns 0 on success, negative on failure
1699 **/
1700
1701int igb_setup_rx_resources(struct igb_adapter *adapter,
1702 struct igb_ring *rx_ring)
1703{
1704 struct pci_dev *pdev = adapter->pdev;
1705 int size, desc_len;
1706
1707 size = sizeof(struct igb_buffer) * rx_ring->count;
1708 rx_ring->buffer_info = vmalloc(size);
1709 if (!rx_ring->buffer_info)
1710 goto err;
1711 memset(rx_ring->buffer_info, 0, size);
1712
1713 desc_len = sizeof(union e1000_adv_rx_desc);
1714
1715 /* Round up to nearest 4K */
1716 rx_ring->size = rx_ring->count * desc_len;
1717 rx_ring->size = ALIGN(rx_ring->size, 4096);
1718
1719 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1720 &rx_ring->dma);
1721
1722 if (!rx_ring->desc)
1723 goto err;
1724
1725 rx_ring->next_to_clean = 0;
1726 rx_ring->next_to_use = 0;
9d5c8243
AK		 1727
1728 rx_ring->adapter = adapter;
9d5c8243
AK		 1729
1730 return 0;
1731
1732err:
1733 vfree(rx_ring->buffer_info);
1734 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1735 "the receive descriptor ring\n");
1736 return -ENOMEM;
1737}
1738
1739/**
1740 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1741 * (Descriptors) for all queues
1742 * @adapter: board private structure
1743 *
1744 * Return 0 on success, negative on failure
1745 **/
1746static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1747{
1748 int i, err = 0;
1749
1750 for (i = 0; i < adapter->num_rx_queues; i++) {
1751 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1752 if (err) {
1753 dev_err(&adapter->pdev->dev,
1754 "Allocation for Rx Queue %u failed\n", i);
1755 for (i--; i >= 0; i--)
3b644cf6 1756 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1757 break;
1758 }
1759 }
1760
1761 return err;
1762}
1763
1764/**
1765 * igb_setup_rctl - configure the receive control registers
1766 * @adapter: Board private structure
1767 **/
1768static void igb_setup_rctl(struct igb_adapter *adapter)
1769{
1770 struct e1000_hw *hw = &adapter->hw;
1771 u32 rctl;
1772 u32 srrctl = 0;
26bc19ec 1773 int i, j;
9d5c8243
AK		 1774
1775 rctl = rd32(E1000_RCTL);
1776
1777 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1778 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1779
69d728ba 1780 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1781 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1782
87cb7e8c
AK		 1783 /*
1784 * enable stripping of CRC. It's unlikely this will break BMC
1785 * redirection as it did with e1000. Newer features require
1786 * that the HW strips the CRC.
9d5c8243 1787 */
87cb7e8c 1788 rctl |= E1000_RCTL_SECRC;
9d5c8243 1789
9b07f3d3 1790 /*
ec54d7d6 1791 * disable store bad packets and clear size bits.
9b07f3d3 1792 */
ec54d7d6 1793 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1794
ec54d7d6 1795 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1796 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1797
1798 /* Setup buffer sizes */
1799 switch (adapter->rx_buffer_len) {
1800 case IGB_RXBUFFER_256:
1801 rctl |= E1000_RCTL_SZ_256;
1802 break;
1803 case IGB_RXBUFFER_512:
1804 rctl |= E1000_RCTL_SZ_512;
1805 break;
1806 default:
1807 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1808 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1809 break;
9d5c8243
AK		 1810 }
1811
1812 /* 82575 and greater support packet-split where the protocol
1813 * header is placed in skb->data and the packet data is
1814 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1815 * In the case of a non-split, skb->data is linearly filled,
1816 * followed by the page buffers. Therefore, skb->data is
1817 * sized to hold the largest protocol header.
1818 */
1819 /* allocations using alloc_page take too long for regular MTU
1820 * so only enable packet split for jumbo frames */
ec54d7d6 1821 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1822 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1823 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1824 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1825 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1826 } else {
1827 adapter->rx_ps_hdr_size = 0;
1828 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1829 }
1830
26bc19ec
AD		 1831 for (i = 0; i < adapter->num_rx_queues; i++) {
1832 j = adapter->rx_ring[i].reg_idx;
1833 wr32(E1000_SRRCTL(j), srrctl);
1834 }
9d5c8243
AK		 1835
1836 wr32(E1000_RCTL, rctl);
1837}
1838
1839/**
1840 * igb_configure_rx - Configure receive Unit after Reset
1841 * @adapter: board private structure
1842 *
1843 * Configure the Rx unit of the MAC after a reset.
1844 **/
1845static void igb_configure_rx(struct igb_adapter *adapter)
1846{
1847 u64 rdba;
1848 struct e1000_hw *hw = &adapter->hw;
1849 u32 rctl, rxcsum;
1850 u32 rxdctl;
26bc19ec 1851 int i, j;
9d5c8243
AK		 1852
1853 /* disable receives while setting up the descriptors */
1854 rctl = rd32(E1000_RCTL);
1855 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1856 wrfl();
1857 mdelay(10);
1858
1859 if (adapter->itr_setting > 3)
6eb5a7f1 1860 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1861
1862 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1863 * the Base and Length of the Rx Descriptor Ring */
1864 for (i = 0; i < adapter->num_rx_queues; i++) {
1865 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1866 j = ring->reg_idx;
9d5c8243 1867 rdba = ring->dma;
26bc19ec 1868 wr32(E1000_RDBAL(j),
9d5c8243 1869 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1870 wr32(E1000_RDBAH(j), rdba >> 32);
1871 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1872 ring->count * sizeof(union e1000_adv_rx_desc));
1873
26bc19ec
AD		 1874 ring->head = E1000_RDH(j);
1875 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1876 writel(0, hw->hw_addr + ring->tail);
1877 writel(0, hw->hw_addr + ring->head);
1878
26bc19ec 1879 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1880 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1881 rxdctl &= 0xFFF00000;
1882 rxdctl |= IGB_RX_PTHRESH;
1883 rxdctl |= IGB_RX_HTHRESH << 8;
1884 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1885 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1886 }
1887
1888 if (adapter->num_rx_queues > 1) {
1889 u32 random[10];
1890 u32 mrqc;
1891 u32 j, shift;
1892 union e1000_reta {
1893 u32 dword;
1894 u8 bytes[4];
1895 } reta;
1896
1897 get_random_bytes(&random[0], 40);
1898
2d064c06
AD		 1899 if (hw->mac.type >= e1000_82576)
1900 shift = 0;
1901 else
1902 shift = 6;
9d5c8243
AK		 1903 for (j = 0; j < (32 * 4); j++) {
1904 reta.bytes[j & 3] =
26bc19ec 1905 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1906 if ((j & 3) == 3)
1907 writel(reta.dword,
1908 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1909 }
1910 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1911
1912 /* Fill out hash function seeds */
1913 for (j = 0; j < 10; j++)
1914 array_wr32(E1000_RSSRK(0), j, random[j]);
1915
1916 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1917 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1918 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1919 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1920 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1921 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1922 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1923 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1924
1925
1926 wr32(E1000_MRQC, mrqc);
1927
1928 /* Multiqueue and raw packet checksumming are mutually
1929 * exclusive. Note that this not the same as TCP/IP
1930 * checksumming, which works fine. */
1931 rxcsum = rd32(E1000_RXCSUM);
1932 rxcsum |= E1000_RXCSUM_PCSD;
1933 wr32(E1000_RXCSUM, rxcsum);
1934 } else {
1935 /* Enable Receive Checksum Offload for TCP and UDP */
1936 rxcsum = rd32(E1000_RXCSUM);
1937 if (adapter->rx_csum) {
1938 rxcsum |= E1000_RXCSUM_TUOFL;
1939
1940 /* Enable IPv4 payload checksum for UDP fragments
1941 * Must be used in conjunction with packet-split. */
1942 if (adapter->rx_ps_hdr_size)
1943 rxcsum |= E1000_RXCSUM_IPPCSE;
1944 } else {
1945 rxcsum &= ~E1000_RXCSUM_TUOFL;
1946 /* don't need to clear IPPCSE as it defaults to 0 */
1947 }
1948 wr32(E1000_RXCSUM, rxcsum);
1949 }
1950
1951 if (adapter->vlgrp)
1952 wr32(E1000_RLPML,
1953 adapter->max_frame_size + VLAN_TAG_SIZE);
1954 else
1955 wr32(E1000_RLPML, adapter->max_frame_size);
1956
1957 /* Enable Receives */
1958 wr32(E1000_RCTL, rctl);
1959}
1960
1961/**
1962 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1963 * @tx_ring: Tx descriptor ring for a specific queue
1964 *
1965 * Free all transmit software resources
1966 **/
68fd9910 1967void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1968{
3b644cf6 1969 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1970
3b644cf6 1971 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1972
1973 vfree(tx_ring->buffer_info);
1974 tx_ring->buffer_info = NULL;
1975
1976 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1977
1978 tx_ring->desc = NULL;
1979}
1980
1981/**
1982 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1983 * @adapter: board private structure
1984 *
1985 * Free all transmit software resources
1986 **/
1987static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1988{
1989 int i;
1990
1991 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1992 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1993}
1994
1995static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1996 struct igb_buffer *buffer_info)
1997{
1998 if (buffer_info->dma) {
1999 pci_unmap_page(adapter->pdev,
2000 buffer_info->dma,
2001 buffer_info->length,
2002 PCI_DMA_TODEVICE);
2003 buffer_info->dma = 0;
2004 }
2005 if (buffer_info->skb) {
2006 dev_kfree_skb_any(buffer_info->skb);
2007 buffer_info->skb = NULL;
2008 }
2009 buffer_info->time_stamp = 0;
2010 /* buffer_info must be completely set up in the transmit path */
2011}
2012
2013/**
2014 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2015 * @tx_ring: ring to be cleaned
2016 **/
3b644cf6 2017static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2018{
3b644cf6 2019 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2020 struct igb_buffer *buffer_info;
2021 unsigned long size;
2022 unsigned int i;
2023
2024 if (!tx_ring->buffer_info)
2025 return;
2026 /* Free all the Tx ring sk_buffs */
2027
2028 for (i = 0; i < tx_ring->count; i++) {
2029 buffer_info = &tx_ring->buffer_info[i];
2030 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2031 }
2032
2033 size = sizeof(struct igb_buffer) * tx_ring->count;
2034 memset(tx_ring->buffer_info, 0, size);
2035
2036 /* Zero out the descriptor ring */
2037
2038 memset(tx_ring->desc, 0, tx_ring->size);
2039
2040 tx_ring->next_to_use = 0;
2041 tx_ring->next_to_clean = 0;
2042
2043 writel(0, adapter->hw.hw_addr + tx_ring->head);
2044 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2045}
2046
2047/**
2048 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2049 * @adapter: board private structure
2050 **/
2051static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2052{
2053 int i;
2054
2055 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2056 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2057}
2058
2059/**
2060 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2061 * @rx_ring: ring to clean the resources from
2062 *
2063 * Free all receive software resources
2064 **/
68fd9910 2065void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2066{
3b644cf6 2067 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2068
3b644cf6 2069 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2070
2071 vfree(rx_ring->buffer_info);
2072 rx_ring->buffer_info = NULL;
2073
2074 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2075
2076 rx_ring->desc = NULL;
2077}
2078
2079/**
2080 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2081 * @adapter: board private structure
2082 *
2083 * Free all receive software resources
2084 **/
2085static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2086{
2087 int i;
2088
2089 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2090 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2091}
2092
2093/**
2094 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2095 * @rx_ring: ring to free buffers from
2096 **/
3b644cf6 2097static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2098{
3b644cf6 2099 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2100 struct igb_buffer *buffer_info;
2101 struct pci_dev *pdev = adapter->pdev;
2102 unsigned long size;
2103 unsigned int i;
2104
2105 if (!rx_ring->buffer_info)
2106 return;
2107 /* Free all the Rx ring sk_buffs */
2108 for (i = 0; i < rx_ring->count; i++) {
2109 buffer_info = &rx_ring->buffer_info[i];
2110 if (buffer_info->dma) {
2111 if (adapter->rx_ps_hdr_size)
2112 pci_unmap_single(pdev, buffer_info->dma,
2113 adapter->rx_ps_hdr_size,
2114 PCI_DMA_FROMDEVICE);
2115 else
2116 pci_unmap_single(pdev, buffer_info->dma,
2117 adapter->rx_buffer_len,
2118 PCI_DMA_FROMDEVICE);
2119 buffer_info->dma = 0;
2120 }
2121
2122 if (buffer_info->skb) {
2123 dev_kfree_skb(buffer_info->skb);
2124 buffer_info->skb = NULL;
2125 }
2126 if (buffer_info->page) {
bf36c1a0
AD		 2127 if (buffer_info->page_dma)
2128 pci_unmap_page(pdev, buffer_info->page_dma,
2129 PAGE_SIZE / 2,
2130 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2131 put_page(buffer_info->page);
2132 buffer_info->page = NULL;
2133 buffer_info->page_dma = 0;
bf36c1a0 2134 buffer_info->page_offset = 0;
9d5c8243
AK		 2135 }
2136 }
2137
9d5c8243
AK		 2138 size = sizeof(struct igb_buffer) * rx_ring->count;
2139 memset(rx_ring->buffer_info, 0, size);
2140
2141 /* Zero out the descriptor ring */
2142 memset(rx_ring->desc, 0, rx_ring->size);
2143
2144 rx_ring->next_to_clean = 0;
2145 rx_ring->next_to_use = 0;
2146
2147 writel(0, adapter->hw.hw_addr + rx_ring->head);
2148 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2149}
2150
2151/**
2152 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2153 * @adapter: board private structure
2154 **/
2155static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2156{
2157 int i;
2158
2159 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2160 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2161}
2162
2163/**
2164 * igb_set_mac - Change the Ethernet Address of the NIC
2165 * @netdev: network interface device structure
2166 * @p: pointer to an address structure
2167 *
2168 * Returns 0 on success, negative on failure
2169 **/
2170static int igb_set_mac(struct net_device *netdev, void *p)
2171{
2172 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2173 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2174 struct sockaddr *addr = p;
2175
2176 if (!is_valid_ether_addr(addr->sa_data))
2177 return -EADDRNOTAVAIL;
2178
2179 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2180 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2181
28b0759c 2182 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243
AK		 2183
2184 return 0;
2185}
2186
2187/**
2188 * igb_set_multi - Multicast and Promiscuous mode set
2189 * @netdev: network interface device structure
2190 *
2191 * The set_multi entry point is called whenever the multicast address
2192 * list or the network interface flags are updated. This routine is
2193 * responsible for configuring the hardware for proper multicast,
2194 * promiscuous mode, and all-multi behavior.
2195 **/
2196static void igb_set_multi(struct net_device *netdev)
2197{
2198 struct igb_adapter *adapter = netdev_priv(netdev);
2199 struct e1000_hw *hw = &adapter->hw;
2200 struct e1000_mac_info *mac = &hw->mac;
2201 struct dev_mc_list *mc_ptr;
2202 u8 *mta_list;
2203 u32 rctl;
2204 int i;
2205
2206 /* Check for Promiscuous and All Multicast modes */
2207
2208 rctl = rd32(E1000_RCTL);
2209
746b9f02 2210 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2211 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2212 rctl &= ~E1000_RCTL_VFE;
2213 } else {
2214 if (netdev->flags & IFF_ALLMULTI) {
2215 rctl |= E1000_RCTL_MPE;
2216 rctl &= ~E1000_RCTL_UPE;
2217 } else
2218 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2219 rctl |= E1000_RCTL_VFE;
746b9f02 2220 }
9d5c8243
AK		 2221 wr32(E1000_RCTL, rctl);
2222
2223 if (!netdev->mc_count) {
2224 /* nothing to program, so clear mc list */
8a900862
AD		 2225 igb_update_mc_addr_list(hw, NULL, 0, 1,
2226 mac->rar_entry_count);
9d5c8243
AK		 2227 return;
2228 }
2229
2230 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2231 if (!mta_list)
2232 return;
2233
2234 /* The shared function expects a packed array of only addresses. */
2235 mc_ptr = netdev->mc_list;
2236
2237 for (i = 0; i < netdev->mc_count; i++) {
2238 if (!mc_ptr)
2239 break;
2240 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2241 mc_ptr = mc_ptr->next;
2242 }
8a900862 2243 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2244 kfree(mta_list);
2245}
2246
2247/* Need to wait a few seconds after link up to get diagnostic information from
2248 * the phy */
2249static void igb_update_phy_info(unsigned long data)
2250{
2251 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2252 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2253}
2254
4d6b725e
AD		 2255/**
2256 * igb_has_link - check shared code for link and determine up/down
2257 * @adapter: pointer to driver private info
2258 **/
2259static bool igb_has_link(struct igb_adapter *adapter)
2260{
2261 struct e1000_hw *hw = &adapter->hw;
2262 bool link_active = false;
2263 s32 ret_val = 0;
2264
2265 /* get_link_status is set on LSC (link status) interrupt or
2266 * rx sequence error interrupt. get_link_status will stay
2267 * false until the e1000_check_for_link establishes link
2268 * for copper adapters ONLY
2269 */
2270 switch (hw->phy.media_type) {
2271 case e1000_media_type_copper:
2272 if (hw->mac.get_link_status) {
2273 ret_val = hw->mac.ops.check_for_link(hw);
2274 link_active = !hw->mac.get_link_status;
2275 } else {
2276 link_active = true;
2277 }
2278 break;
2279 case e1000_media_type_fiber:
2280 ret_val = hw->mac.ops.check_for_link(hw);
2281 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2282 break;
2283 case e1000_media_type_internal_serdes:
2284 ret_val = hw->mac.ops.check_for_link(hw);
2285 link_active = hw->mac.serdes_has_link;
2286 break;
2287 default:
2288 case e1000_media_type_unknown:
2289 break;
2290 }
2291
2292 return link_active;
2293}
2294
9d5c8243
AK		 2295/**
2296 * igb_watchdog - Timer Call-back
2297 * @data: pointer to adapter cast into an unsigned long
2298 **/
2299static void igb_watchdog(unsigned long data)
2300{
2301 struct igb_adapter *adapter = (struct igb_adapter *)data;
2302 /* Do the rest outside of interrupt context */
2303 schedule_work(&adapter->watchdog_task);
2304}
2305
2306static void igb_watchdog_task(struct work_struct *work)
2307{
2308 struct igb_adapter *adapter = container_of(work,
2309 struct igb_adapter, watchdog_task);
2310 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2311 struct net_device *netdev = adapter->netdev;
2312 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2313 u32 link;
7a6ea550 2314 u32 eics = 0;
7a6ea550 2315 int i;
9d5c8243 2316
4d6b725e
AD		 2317 link = igb_has_link(adapter);
2318 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2319 goto link_up;
2320
9d5c8243
AK		 2321 if (link) {
2322 if (!netif_carrier_ok(netdev)) {
2323 u32 ctrl;
2324 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2325 &adapter->link_speed,
2326 &adapter->link_duplex);
2327
2328 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2329 /* Links status message must follow this format */
2330 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2331 "Flow Control: %s\n",
527d47c1 2332 netdev->name,
9d5c8243
AK		 2333 adapter->link_speed,
2334 adapter->link_duplex == FULL_DUPLEX ?
2335 "Full Duplex" : "Half Duplex",
2336 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2337 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2338 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2339 E1000_CTRL_TFCE) ? "TX" : "None")));
2340
2341 /* tweak tx_queue_len according to speed/duplex and
2342 * adjust the timeout factor */
2343 netdev->tx_queue_len = adapter->tx_queue_len;
2344 adapter->tx_timeout_factor = 1;
2345 switch (adapter->link_speed) {
2346 case SPEED_10:
2347 netdev->tx_queue_len = 10;
2348 adapter->tx_timeout_factor = 14;
2349 break;
2350 case SPEED_100:
2351 netdev->tx_queue_len = 100;
2352 /* maybe add some timeout factor ? */
2353 break;
2354 }
2355
2356 netif_carrier_on(netdev);
fd2ea0a7 2357 netif_tx_wake_all_queues(netdev);
9d5c8243 2358
4b1a9877 2359 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2360 if (!test_bit(__IGB_DOWN, &adapter->state))
2361 mod_timer(&adapter->phy_info_timer,
2362 round_jiffies(jiffies + 2 * HZ));
2363 }
2364 } else {
2365 if (netif_carrier_ok(netdev)) {
2366 adapter->link_speed = 0;
2367 adapter->link_duplex = 0;
527d47c1
AD		 2368 /* Links status message must follow this format */
2369 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2370 netdev->name);
9d5c8243 2371 netif_carrier_off(netdev);
fd2ea0a7 2372 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2373
2374 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2375 if (!test_bit(__IGB_DOWN, &adapter->state))
2376 mod_timer(&adapter->phy_info_timer,
2377 round_jiffies(jiffies + 2 * HZ));
2378 }
2379 }
2380
2381link_up:
2382 igb_update_stats(adapter);
2383
4b1a9877 2384 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2385 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2386 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2387 adapter->colc_old = adapter->stats.colc;
2388
2389 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2390 adapter->gorc_old = adapter->stats.gorc;
2391 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2392 adapter->gotc_old = adapter->stats.gotc;
2393
2394 igb_update_adaptive(&adapter->hw);
2395
2396 if (!netif_carrier_ok(netdev)) {
2397 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2398 /* We've lost link, so the controller stops DMA,
2399 * but we've got queued Tx work that's never going
2400 * to get done, so reset controller to flush Tx.
2401 * (Do the reset outside of interrupt context). */
2402 adapter->tx_timeout_count++;
2403 schedule_work(&adapter->reset_task);
2404 }
2405 }
2406
2407 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2408 if (adapter->msix_entries) {
2409 for (i = 0; i < adapter->num_rx_queues; i++)
2410 eics |= adapter->rx_ring[i].eims_value;
2411 wr32(E1000_EICS, eics);
2412 } else {
2413 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2414 }
9d5c8243
AK		 2415
2416 /* Force detection of hung controller every watchdog period */
2417 tx_ring->detect_tx_hung = true;
2418
2419 /* Reset the timer */
2420 if (!test_bit(__IGB_DOWN, &adapter->state))
2421 mod_timer(&adapter->watchdog_timer,
2422 round_jiffies(jiffies + 2 * HZ));
2423}
2424
2425enum latency_range {
2426 lowest_latency = 0,
2427 low_latency = 1,
2428 bulk_latency = 2,
2429 latency_invalid = 255
2430};
2431
2432
6eb5a7f1
AD		 2433/**
2434 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2435 *
2436 * Stores a new ITR value based on strictly on packet size. This
2437 * algorithm is less sophisticated than that used in igb_update_itr,
2438 * due to the difficulty of synchronizing statistics across multiple
2439 * receive rings. The divisors and thresholds used by this fuction
2440 * were determined based on theoretical maximum wire speed and testing
2441 * data, in order to minimize response time while increasing bulk
2442 * throughput.
2443 * This functionality is controlled by the InterruptThrottleRate module
2444 * parameter (see igb_param.c)
2445 * NOTE: This function is called only when operating in a multiqueue
2446 * receive environment.
2447 * @rx_ring: pointer to ring
2448 **/
2449static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2450{
6eb5a7f1
AD		 2451 int new_val = rx_ring->itr_val;
2452 int avg_wire_size = 0;
2453 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2454
6eb5a7f1
AD		 2455 if (!rx_ring->total_packets)
2456 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2457
6eb5a7f1
AD		 2458 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2459 * ints/sec - ITR timer value of 120 ticks.
2460 */
2461 if (adapter->link_speed != SPEED_1000) {
2462 new_val = 120;
2463 goto set_itr_val;
9d5c8243 2464 }
6eb5a7f1 2465 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2466
6eb5a7f1
AD		 2467 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2468 avg_wire_size += 24;
2469
2470 /* Don't starve jumbo frames */
2471 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2472
6eb5a7f1
AD		 2473 /* Give a little boost to mid-size frames */
2474 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2475 new_val = avg_wire_size / 3;
2476 else
2477 new_val = avg_wire_size / 2;
9d5c8243 2478
6eb5a7f1 2479set_itr_val:
9d5c8243
AK		 2480 if (new_val != rx_ring->itr_val) {
2481 rx_ring->itr_val = new_val;
6eb5a7f1 2482 rx_ring->set_itr = 1;
9d5c8243 2483 }
6eb5a7f1
AD		 2484clear_counts:
2485 rx_ring->total_bytes = 0;
2486 rx_ring->total_packets = 0;
9d5c8243
AK		 2487}
2488
2489/**
2490 * igb_update_itr - update the dynamic ITR value based on statistics
2491 * Stores a new ITR value based on packets and byte
2492 * counts during the last interrupt. The advantage of per interrupt
2493 * computation is faster updates and more accurate ITR for the current
2494 * traffic pattern. Constants in this function were computed
2495 * based on theoretical maximum wire speed and thresholds were set based
2496 * on testing data as well as attempting to minimize response time
2497 * while increasing bulk throughput.
2498 * this functionality is controlled by the InterruptThrottleRate module
2499 * parameter (see igb_param.c)
2500 * NOTE: These calculations are only valid when operating in a single-
2501 * queue environment.
2502 * @adapter: pointer to adapter
2503 * @itr_setting: current adapter->itr
2504 * @packets: the number of packets during this measurement interval
2505 * @bytes: the number of bytes during this measurement interval
2506 **/
2507static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2508 int packets, int bytes)
2509{
2510 unsigned int retval = itr_setting;
2511
2512 if (packets == 0)
2513 goto update_itr_done;
2514
2515 switch (itr_setting) {
2516 case lowest_latency:
2517 /* handle TSO and jumbo frames */
2518 if (bytes/packets > 8000)
2519 retval = bulk_latency;
2520 else if ((packets < 5) && (bytes > 512))
2521 retval = low_latency;
2522 break;
2523 case low_latency: /* 50 usec aka 20000 ints/s */
2524 if (bytes > 10000) {
2525 /* this if handles the TSO accounting */
2526 if (bytes/packets > 8000) {
2527 retval = bulk_latency;
2528 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2529 retval = bulk_latency;
2530 } else if ((packets > 35)) {
2531 retval = lowest_latency;
2532 }
2533 } else if (bytes/packets > 2000) {
2534 retval = bulk_latency;
2535 } else if (packets <= 2 && bytes < 512) {
2536 retval = lowest_latency;
2537 }
2538 break;
2539 case bulk_latency: /* 250 usec aka 4000 ints/s */
2540 if (bytes > 25000) {
2541 if (packets > 35)
2542 retval = low_latency;
2543 } else if (bytes < 6000) {
2544 retval = low_latency;
2545 }
2546 break;
2547 }
2548
2549update_itr_done:
2550 return retval;
2551}
2552
6eb5a7f1 2553static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2554{
2555 u16 current_itr;
2556 u32 new_itr = adapter->itr;
2557
2558 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2559 if (adapter->link_speed != SPEED_1000) {
2560 current_itr = 0;
2561 new_itr = 4000;
2562 goto set_itr_now;
2563 }
2564
2565 adapter->rx_itr = igb_update_itr(adapter,
2566 adapter->rx_itr,
2567 adapter->rx_ring->total_packets,
2568 adapter->rx_ring->total_bytes);
9d5c8243 2569
6eb5a7f1 2570 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2571 adapter->tx_itr = igb_update_itr(adapter,
2572 adapter->tx_itr,
2573 adapter->tx_ring->total_packets,
2574 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2575
2576 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2577 } else {
2578 current_itr = adapter->rx_itr;
2579 }
2580
6eb5a7f1
AD		 2581 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2582 if (adapter->itr_setting == 3 &&
2583 current_itr == lowest_latency)
2584 current_itr = low_latency;
2585
9d5c8243
AK		 2586 switch (current_itr) {
2587 /* counts and packets in update_itr are dependent on these numbers */
2588 case lowest_latency:
2589 new_itr = 70000;
2590 break;
2591 case low_latency:
2592 new_itr = 20000; /* aka hwitr = ~200 */
2593 break;
2594 case bulk_latency:
2595 new_itr = 4000;
2596 break;
2597 default:
2598 break;
2599 }
2600
2601set_itr_now:
6eb5a7f1
AD		 2602 adapter->rx_ring->total_bytes = 0;
2603 adapter->rx_ring->total_packets = 0;
2604 if (adapter->rx_ring->buddy) {
2605 adapter->rx_ring->buddy->total_bytes = 0;
2606 adapter->rx_ring->buddy->total_packets = 0;
2607 }
2608
9d5c8243
AK		 2609 if (new_itr != adapter->itr) {
2610 /* this attempts to bias the interrupt rate towards Bulk
2611 * by adding intermediate steps when interrupt rate is
2612 * increasing */
2613 new_itr = new_itr > adapter->itr ?
2614 min(adapter->itr + (new_itr >> 2), new_itr) :
2615 new_itr;
2616 /* Don't write the value here; it resets the adapter's
2617 * internal timer, and causes us to delay far longer than
2618 * we should between interrupts. Instead, we write the ITR
2619 * value at the beginning of the next interrupt so the timing
2620 * ends up being correct.
2621 */
2622 adapter->itr = new_itr;
6eb5a7f1
AD		 2623 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2624 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2625 }
2626
2627 return;
2628}
2629
2630
2631#define IGB_TX_FLAGS_CSUM 0x00000001
2632#define IGB_TX_FLAGS_VLAN 0x00000002
2633#define IGB_TX_FLAGS_TSO 0x00000004
2634#define IGB_TX_FLAGS_IPV4 0x00000008
2635#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2636#define IGB_TX_FLAGS_VLAN_SHIFT 16
2637
2638static inline int igb_tso_adv(struct igb_adapter *adapter,
2639 struct igb_ring *tx_ring,
2640 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2641{
2642 struct e1000_adv_tx_context_desc *context_desc;
2643 unsigned int i;
2644 int err;
2645 struct igb_buffer *buffer_info;
2646 u32 info = 0, tu_cmd = 0;
2647 u32 mss_l4len_idx, l4len;
2648 *hdr_len = 0;
2649
2650 if (skb_header_cloned(skb)) {
2651 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2652 if (err)
2653 return err;
2654 }
2655
2656 l4len = tcp_hdrlen(skb);
2657 *hdr_len += l4len;
2658
2659 if (skb->protocol == htons(ETH_P_IP)) {
2660 struct iphdr *iph = ip_hdr(skb);
2661 iph->tot_len = 0;
2662 iph->check = 0;
2663 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2664 iph->daddr, 0,
2665 IPPROTO_TCP,
2666 0);
2667 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2668 ipv6_hdr(skb)->payload_len = 0;
2669 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2670 &ipv6_hdr(skb)->daddr,
2671 0, IPPROTO_TCP, 0);
2672 }
2673
2674 i = tx_ring->next_to_use;
2675
2676 buffer_info = &tx_ring->buffer_info[i];
2677 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2678 /* VLAN MACLEN IPLEN */
2679 if (tx_flags & IGB_TX_FLAGS_VLAN)
2680 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2681 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2682 *hdr_len += skb_network_offset(skb);
2683 info |= skb_network_header_len(skb);
2684 *hdr_len += skb_network_header_len(skb);
2685 context_desc->vlan_macip_lens = cpu_to_le32(info);
2686
2687 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2688 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2689
2690 if (skb->protocol == htons(ETH_P_IP))
2691 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2692 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2693
2694 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2695
2696 /* MSS L4LEN IDX */
2697 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2698 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2699
7dfc16fa
AD		 2700 /* Context index must be unique per ring. */
2701 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2702 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2703
2704 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2705 context_desc->seqnum_seed = 0;
2706
2707 buffer_info->time_stamp = jiffies;
0e014cb1 2708 buffer_info->next_to_watch = i;
9d5c8243
AK		 2709 buffer_info->dma = 0;
2710 i++;
2711 if (i == tx_ring->count)
2712 i = 0;
2713
2714 tx_ring->next_to_use = i;
2715
2716 return true;
2717}
2718
2719static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2720 struct igb_ring *tx_ring,
2721 struct sk_buff *skb, u32 tx_flags)
2722{
2723 struct e1000_adv_tx_context_desc *context_desc;
2724 unsigned int i;
2725 struct igb_buffer *buffer_info;
2726 u32 info = 0, tu_cmd = 0;
2727
2728 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2729 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2730 i = tx_ring->next_to_use;
2731 buffer_info = &tx_ring->buffer_info[i];
2732 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2733
2734 if (tx_flags & IGB_TX_FLAGS_VLAN)
2735 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2736 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2737 if (skb->ip_summed == CHECKSUM_PARTIAL)
2738 info |= skb_network_header_len(skb);
2739
2740 context_desc->vlan_macip_lens = cpu_to_le32(info);
2741
2742 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2743
2744 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2745 switch (skb->protocol) {
09640e63 2746 case cpu_to_be16(ETH_P_IP):
9d5c8243 2747 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2748 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2749 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2750 break;
09640e63 2751 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2752 /* XXX what about other V6 headers?? */
2753 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2754 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2755 break;
2756 default:
2757 if (unlikely(net_ratelimit()))
2758 dev_warn(&adapter->pdev->dev,
2759 "partial checksum but proto=%x!\n",
2760 skb->protocol);
2761 break;
2762 }
9d5c8243
AK		 2763 }
2764
2765 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2766 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2767 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2768 context_desc->mss_l4len_idx =
2769 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2770
2771 buffer_info->time_stamp = jiffies;
0e014cb1 2772 buffer_info->next_to_watch = i;
9d5c8243
AK		 2773 buffer_info->dma = 0;
2774
2775 i++;
2776 if (i == tx_ring->count)
2777 i = 0;
2778 tx_ring->next_to_use = i;
2779
2780 return true;
2781 }
2782
2783
2784 return false;
2785}
2786
2787#define IGB_MAX_TXD_PWR 16
2788#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2789
2790static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2791 struct igb_ring *tx_ring, struct sk_buff *skb,
2792 unsigned int first)
9d5c8243
AK		 2793{
2794 struct igb_buffer *buffer_info;
2795 unsigned int len = skb_headlen(skb);
2796 unsigned int count = 0, i;
2797 unsigned int f;
2798
2799 i = tx_ring->next_to_use;
2800
2801 buffer_info = &tx_ring->buffer_info[i];
2802 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2803 buffer_info->length = len;
2804 /* set time_stamp *before* dma to help avoid a possible race */
2805 buffer_info->time_stamp = jiffies;
0e014cb1 2806 buffer_info->next_to_watch = i;
9d5c8243
AK		 2807 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2808 PCI_DMA_TODEVICE);
2809 count++;
2810 i++;
2811 if (i == tx_ring->count)
2812 i = 0;
2813
2814 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2815 struct skb_frag_struct *frag;
2816
2817 frag = &skb_shinfo(skb)->frags[f];
2818 len = frag->size;
2819
2820 buffer_info = &tx_ring->buffer_info[i];
2821 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2822 buffer_info->length = len;
2823 buffer_info->time_stamp = jiffies;
0e014cb1 2824 buffer_info->next_to_watch = i;
9d5c8243
AK		 2825 buffer_info->dma = pci_map_page(adapter->pdev,
2826 frag->page,
2827 frag->page_offset,
2828 len,
2829 PCI_DMA_TODEVICE);
2830
2831 count++;
2832 i++;
2833 if (i == tx_ring->count)
2834 i = 0;
2835 }
2836
0e014cb1 2837 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2838 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2839 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2840
2841 return count;
2842}
2843
2844static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2845 struct igb_ring *tx_ring,
2846 int tx_flags, int count, u32 paylen,
2847 u8 hdr_len)
2848{
2849 union e1000_adv_tx_desc *tx_desc = NULL;
2850 struct igb_buffer *buffer_info;
2851 u32 olinfo_status = 0, cmd_type_len;
2852 unsigned int i;
2853
2854 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2855 E1000_ADVTXD_DCMD_DEXT);
2856
2857 if (tx_flags & IGB_TX_FLAGS_VLAN)
2858 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2859
2860 if (tx_flags & IGB_TX_FLAGS_TSO) {
2861 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2862
2863 /* insert tcp checksum */
2864 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2865
2866 /* insert ip checksum */
2867 if (tx_flags & IGB_TX_FLAGS_IPV4)
2868 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2869
2870 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2871 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2872 }
2873
7dfc16fa
AD		 2874 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2875 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2876 IGB_TX_FLAGS_VLAN)))
661086df 2877 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2878
2879 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2880
2881 i = tx_ring->next_to_use;
2882 while (count--) {
2883 buffer_info = &tx_ring->buffer_info[i];
2884 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2885 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2886 tx_desc->read.cmd_type_len =
2887 cpu_to_le32(cmd_type_len | buffer_info->length);
2888 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2889 i++;
2890 if (i == tx_ring->count)
2891 i = 0;
2892 }
2893
2894 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2895 /* Force memory writes to complete before letting h/w
2896 * know there are new descriptors to fetch. (Only
2897 * applicable for weak-ordered memory model archs,
2898 * such as IA-64). */
2899 wmb();
2900
2901 tx_ring->next_to_use = i;
2902 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2903 /* we need this if more than one processor can write to our tail
2904 * at a time, it syncronizes IO on IA64/Altix systems */
2905 mmiowb();
2906}
2907
2908static int __igb_maybe_stop_tx(struct net_device *netdev,
2909 struct igb_ring *tx_ring, int size)
2910{
2911 struct igb_adapter *adapter = netdev_priv(netdev);
2912
661086df 2913 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2914
9d5c8243
AK		 2915 /* Herbert's original patch had:
2916 * smp_mb__after_netif_stop_queue();
2917 * but since that doesn't exist yet, just open code it. */
2918 smp_mb();
2919
2920 /* We need to check again in a case another CPU has just
2921 * made room available. */
2922 if (IGB_DESC_UNUSED(tx_ring) < size)
2923 return -EBUSY;
2924
2925 /* A reprieve! */
661086df 2926 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2927 ++adapter->restart_queue;
2928 return 0;
2929}
2930
2931static int igb_maybe_stop_tx(struct net_device *netdev,
2932 struct igb_ring *tx_ring, int size)
2933{
2934 if (IGB_DESC_UNUSED(tx_ring) >= size)
2935 return 0;
2936 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2937}
2938
2939#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2940
2941static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2942 struct net_device *netdev,
2943 struct igb_ring *tx_ring)
2944{
2945 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2946 unsigned int first;
9d5c8243
AK		 2947 unsigned int tx_flags = 0;
2948 unsigned int len;
9d5c8243
AK		 2949 u8 hdr_len = 0;
2950 int tso = 0;
2951
2952 len = skb_headlen(skb);
2953
2954 if (test_bit(__IGB_DOWN, &adapter->state)) {
2955 dev_kfree_skb_any(skb);
2956 return NETDEV_TX_OK;
2957 }
2958
2959 if (skb->len <= 0) {
2960 dev_kfree_skb_any(skb);
2961 return NETDEV_TX_OK;
2962 }
2963
9d5c8243
AK		 2964 /* need: 1 descriptor per page,
2965 * + 2 desc gap to keep tail from touching head,
2966 * + 1 desc for skb->data,
2967 * + 1 desc for context descriptor,
2968 * otherwise try next time */
2969 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2970 /* this is a hard error */
9d5c8243
AK		 2971 return NETDEV_TX_BUSY;
2972 }
6eb5a7f1 2973 skb_orphan(skb);
9d5c8243
AK		 2974
2975 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2976 tx_flags |= IGB_TX_FLAGS_VLAN;
2977 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2978 }
2979
661086df
PWJ		 2980 if (skb->protocol == htons(ETH_P_IP))
2981 tx_flags |= IGB_TX_FLAGS_IPV4;
2982
0e014cb1
AD		 2983 first = tx_ring->next_to_use;
2984
9d5c8243
AK		 2985 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2986 &hdr_len) : 0;
2987
2988 if (tso < 0) {
2989 dev_kfree_skb_any(skb);
9d5c8243
AK		 2990 return NETDEV_TX_OK;
2991 }
2992
2993 if (tso)
2994 tx_flags |= IGB_TX_FLAGS_TSO;
2995 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2996 if (skb->ip_summed == CHECKSUM_PARTIAL)
2997 tx_flags |= IGB_TX_FLAGS_CSUM;
2998
9d5c8243 2999 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3000 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3001 skb->len, hdr_len);
3002
3003 netdev->trans_start = jiffies;
3004
3005 /* Make sure there is space in the ring for the next send. */
3006 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3007
9d5c8243
AK		 3008 return NETDEV_TX_OK;
3009}
3010
3011static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3012{
3013 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3014 struct igb_ring *tx_ring;
3015
661086df
PWJ		 3016 int r_idx = 0;
3017 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3018 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3019
3020 /* This goes back to the question of how to logically map a tx queue
3021 * to a flow. Right now, performance is impacted slightly negatively
3022 * if using multiple tx queues. If the stack breaks away from a
3023 * single qdisc implementation, we can look at this again. */
3024 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3025}
3026
3027/**
3028 * igb_tx_timeout - Respond to a Tx Hang
3029 * @netdev: network interface device structure
3030 **/
3031static void igb_tx_timeout(struct net_device *netdev)
3032{
3033 struct igb_adapter *adapter = netdev_priv(netdev);
3034 struct e1000_hw *hw = &adapter->hw;
3035
3036 /* Do the reset outside of interrupt context */
3037 adapter->tx_timeout_count++;
3038 schedule_work(&adapter->reset_task);
3039 wr32(E1000_EICS, adapter->eims_enable_mask &
3040 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3041}
3042
3043static void igb_reset_task(struct work_struct *work)
3044{
3045 struct igb_adapter *adapter;
3046 adapter = container_of(work, struct igb_adapter, reset_task);
3047
3048 igb_reinit_locked(adapter);
3049}
3050
3051/**
3052 * igb_get_stats - Get System Network Statistics
3053 * @netdev: network interface device structure
3054 *
3055 * Returns the address of the device statistics structure.
3056 * The statistics are actually updated from the timer callback.
3057 **/
3058static struct net_device_stats *
3059igb_get_stats(struct net_device *netdev)
3060{
3061 struct igb_adapter *adapter = netdev_priv(netdev);
3062
3063 /* only return the current stats */
3064 return &adapter->net_stats;
3065}
3066
3067/**
3068 * igb_change_mtu - Change the Maximum Transfer Unit
3069 * @netdev: network interface device structure
3070 * @new_mtu: new value for maximum frame size
3071 *
3072 * Returns 0 on success, negative on failure
3073 **/
3074static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3075{
3076 struct igb_adapter *adapter = netdev_priv(netdev);
3077 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3078
3079 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3080 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3081 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3082 return -EINVAL;
3083 }
3084
3085#define MAX_STD_JUMBO_FRAME_SIZE 9234
3086 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3087 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3088 return -EINVAL;
3089 }
3090
3091 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3092 msleep(1);
3093 /* igb_down has a dependency on max_frame_size */
3094 adapter->max_frame_size = max_frame;
3095 if (netif_running(netdev))
3096 igb_down(adapter);
3097
3098 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3099 * means we reserve 2 more, this pushes us to allocate from the next
3100 * larger slab size.
3101 * i.e. RXBUFFER_2048 --> size-4096 slab
3102 */
3103
3104 if (max_frame <= IGB_RXBUFFER_256)
3105 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3106 else if (max_frame <= IGB_RXBUFFER_512)
3107 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3108 else if (max_frame <= IGB_RXBUFFER_1024)
3109 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3110 else if (max_frame <= IGB_RXBUFFER_2048)
3111 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3112 else
bf36c1a0
AD		 3113#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3114 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3115#else
3116 adapter->rx_buffer_len = PAGE_SIZE / 2;
3117#endif
9d5c8243
AK		 3118 /* adjust allocation if LPE protects us, and we aren't using SBP */
3119 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3120 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3121 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3122
3123 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3124 netdev->mtu, new_mtu);
3125 netdev->mtu = new_mtu;
3126
3127 if (netif_running(netdev))
3128 igb_up(adapter);
3129 else
3130 igb_reset(adapter);
3131
3132 clear_bit(__IGB_RESETTING, &adapter->state);
3133
3134 return 0;
3135}
3136
3137/**
3138 * igb_update_stats - Update the board statistics counters
3139 * @adapter: board private structure
3140 **/
3141
3142void igb_update_stats(struct igb_adapter *adapter)
3143{
3144 struct e1000_hw *hw = &adapter->hw;
3145 struct pci_dev *pdev = adapter->pdev;
3146 u16 phy_tmp;
3147
3148#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3149
3150 /*
3151 * Prevent stats update while adapter is being reset, or if the pci
3152 * connection is down.
3153 */
3154 if (adapter->link_speed == 0)
3155 return;
3156 if (pci_channel_offline(pdev))
3157 return;
3158
3159 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3160 adapter->stats.gprc += rd32(E1000_GPRC);
3161 adapter->stats.gorc += rd32(E1000_GORCL);
3162 rd32(E1000_GORCH); /* clear GORCL */
3163 adapter->stats.bprc += rd32(E1000_BPRC);
3164 adapter->stats.mprc += rd32(E1000_MPRC);
3165 adapter->stats.roc += rd32(E1000_ROC);
3166
3167 adapter->stats.prc64 += rd32(E1000_PRC64);
3168 adapter->stats.prc127 += rd32(E1000_PRC127);
3169 adapter->stats.prc255 += rd32(E1000_PRC255);
3170 adapter->stats.prc511 += rd32(E1000_PRC511);
3171 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3172 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3173 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3174 adapter->stats.sec += rd32(E1000_SEC);
3175
3176 adapter->stats.mpc += rd32(E1000_MPC);
3177 adapter->stats.scc += rd32(E1000_SCC);
3178 adapter->stats.ecol += rd32(E1000_ECOL);
3179 adapter->stats.mcc += rd32(E1000_MCC);
3180 adapter->stats.latecol += rd32(E1000_LATECOL);
3181 adapter->stats.dc += rd32(E1000_DC);
3182 adapter->stats.rlec += rd32(E1000_RLEC);
3183 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3184 adapter->stats.xontxc += rd32(E1000_XONTXC);
3185 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3186 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3187 adapter->stats.fcruc += rd32(E1000_FCRUC);
3188 adapter->stats.gptc += rd32(E1000_GPTC);
3189 adapter->stats.gotc += rd32(E1000_GOTCL);
3190 rd32(E1000_GOTCH); /* clear GOTCL */
3191 adapter->stats.rnbc += rd32(E1000_RNBC);
3192 adapter->stats.ruc += rd32(E1000_RUC);
3193 adapter->stats.rfc += rd32(E1000_RFC);
3194 adapter->stats.rjc += rd32(E1000_RJC);
3195 adapter->stats.tor += rd32(E1000_TORH);
3196 adapter->stats.tot += rd32(E1000_TOTH);
3197 adapter->stats.tpr += rd32(E1000_TPR);
3198
3199 adapter->stats.ptc64 += rd32(E1000_PTC64);
3200 adapter->stats.ptc127 += rd32(E1000_PTC127);
3201 adapter->stats.ptc255 += rd32(E1000_PTC255);
3202 adapter->stats.ptc511 += rd32(E1000_PTC511);
3203 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3204 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3205
3206 adapter->stats.mptc += rd32(E1000_MPTC);
3207 adapter->stats.bptc += rd32(E1000_BPTC);
3208
3209 /* used for adaptive IFS */
3210
3211 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3212 adapter->stats.tpt += hw->mac.tx_packet_delta;
3213 hw->mac.collision_delta = rd32(E1000_COLC);
3214 adapter->stats.colc += hw->mac.collision_delta;
3215
3216 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3217 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3218 adapter->stats.tncrs += rd32(E1000_TNCRS);
3219 adapter->stats.tsctc += rd32(E1000_TSCTC);
3220 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3221
3222 adapter->stats.iac += rd32(E1000_IAC);
3223 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3224 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3225 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3226 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3227 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3228 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3229 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3230 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3231
3232 /* Fill out the OS statistics structure */
3233 adapter->net_stats.multicast = adapter->stats.mprc;
3234 adapter->net_stats.collisions = adapter->stats.colc;
3235
3236 /* Rx Errors */
3237
3238 /* RLEC on some newer hardware can be incorrect so build
3239 * our own version based on RUC and ROC */
3240 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3241 adapter->stats.crcerrs + adapter->stats.algnerrc +
3242 adapter->stats.ruc + adapter->stats.roc +
3243 adapter->stats.cexterr;
3244 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3245 adapter->stats.roc;
3246 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3247 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3248 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3249
3250 /* Tx Errors */
3251 adapter->net_stats.tx_errors = adapter->stats.ecol +
3252 adapter->stats.latecol;
3253 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3254 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3255 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3256
3257 /* Tx Dropped needs to be maintained elsewhere */
3258
3259 /* Phy Stats */
3260 if (hw->phy.media_type == e1000_media_type_copper) {
3261 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3262 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3263 &phy_tmp))) {
3264 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3265 adapter->phy_stats.idle_errors += phy_tmp;
3266 }
3267 }
3268
3269 /* Management Stats */
3270 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3271 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3272 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3273}
3274
3275
3276static irqreturn_t igb_msix_other(int irq, void *data)
3277{
3278 struct net_device *netdev = data;
3279 struct igb_adapter *adapter = netdev_priv(netdev);
3280 struct e1000_hw *hw = &adapter->hw;
844290e5 3281 u32 icr = rd32(E1000_ICR);
9d5c8243 3282
844290e5 3283 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3284
3285 if(icr & E1000_ICR_DOUTSYNC) {
3286 /* HW is reporting DMA is out of sync */
3287 adapter->stats.doosync++;
3288 }
844290e5
PW		 3289 if (!(icr & E1000_ICR_LSC))
3290 goto no_link_interrupt;
3291 hw->mac.get_link_status = 1;
3292 /* guard against interrupt when we're going down */
3293 if (!test_bit(__IGB_DOWN, &adapter->state))
3294 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3295
9d5c8243 3296no_link_interrupt:
dda0e083 3297 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3298 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3299
3300 return IRQ_HANDLED;
3301}
3302
3303static irqreturn_t igb_msix_tx(int irq, void *data)
3304{
3305 struct igb_ring *tx_ring = data;
3306 struct igb_adapter *adapter = tx_ring->adapter;
3307 struct e1000_hw *hw = &adapter->hw;
3308
421e02f0 3309#ifdef CONFIG_IGB_DCA
7dfc16fa 3310 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3311 igb_update_tx_dca(tx_ring);
3312#endif
9d5c8243
AK		 3313 tx_ring->total_bytes = 0;
3314 tx_ring->total_packets = 0;
661086df
PWJ		 3315
3316 /* auto mask will automatically reenable the interrupt when we write
3317 * EICS */
3b644cf6 3318 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3319 /* Ring was not completely cleaned, so fire another interrupt */
3320 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3321 else
9d5c8243 3322 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3323
9d5c8243
AK		 3324 return IRQ_HANDLED;
3325}
3326
6eb5a7f1
AD		 3327static void igb_write_itr(struct igb_ring *ring)
3328{
3329 struct e1000_hw *hw = &ring->adapter->hw;
3330 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3331 switch (hw->mac.type) {
3332 case e1000_82576:
3333 wr32(ring->itr_register,
3334 ring->itr_val |
3335 0x80000000);
3336 break;
3337 default:
3338 wr32(ring->itr_register,
3339 ring->itr_val |
3340 (ring->itr_val << 16));
3341 break;
3342 }
3343 ring->set_itr = 0;
3344 }
3345}
3346
9d5c8243
AK		 3347static irqreturn_t igb_msix_rx(int irq, void *data)
3348{
3349 struct igb_ring *rx_ring = data;
9d5c8243 3350
844290e5
PW		 3351 /* Write the ITR value calculated at the end of the
3352 * previous interrupt.
3353 */
9d5c8243 3354
6eb5a7f1 3355 igb_write_itr(rx_ring);
9d5c8243 3356
288379f0
BH		 3357 if (napi_schedule_prep(&rx_ring->napi))
3358 __napi_schedule(&rx_ring->napi);
844290e5 3359
421e02f0 3360#ifdef CONFIG_IGB_DCA
8d253320 3361 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3362 igb_update_rx_dca(rx_ring);
3363#endif
3364 return IRQ_HANDLED;
3365}
3366
421e02f0 3367#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3368static void igb_update_rx_dca(struct igb_ring *rx_ring)
3369{
3370 u32 dca_rxctrl;
3371 struct igb_adapter *adapter = rx_ring->adapter;
3372 struct e1000_hw *hw = &adapter->hw;
3373 int cpu = get_cpu();
26bc19ec 3374 int q = rx_ring->reg_idx;
fe4506b6
JC		 3375
3376 if (rx_ring->cpu != cpu) {
3377 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3378 if (hw->mac.type == e1000_82576) {
3379 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3380 dca_rxctrl |= dca_get_tag(cpu) <<
3381 E1000_DCA_RXCTRL_CPUID_SHIFT;
3382 } else {
3383 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3384 dca_rxctrl |= dca_get_tag(cpu);
3385 }
fe4506b6
JC		 3386 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3387 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3388 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3389 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3390 rx_ring->cpu = cpu;
3391 }
3392 put_cpu();
3393}
3394
3395static void igb_update_tx_dca(struct igb_ring *tx_ring)
3396{
3397 u32 dca_txctrl;
3398 struct igb_adapter *adapter = tx_ring->adapter;
3399 struct e1000_hw *hw = &adapter->hw;
3400 int cpu = get_cpu();
26bc19ec 3401 int q = tx_ring->reg_idx;
fe4506b6
JC		 3402
3403 if (tx_ring->cpu != cpu) {
3404 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3405 if (hw->mac.type == e1000_82576) {
3406 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3407 dca_txctrl |= dca_get_tag(cpu) <<
3408 E1000_DCA_TXCTRL_CPUID_SHIFT;
3409 } else {
3410 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3411 dca_txctrl |= dca_get_tag(cpu);
3412 }
fe4506b6
JC		 3413 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3414 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3415 tx_ring->cpu = cpu;
3416 }
3417 put_cpu();
3418}
3419
3420static void igb_setup_dca(struct igb_adapter *adapter)
3421{
3422 int i;
3423
7dfc16fa 3424 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3425 return;
3426
3427 for (i = 0; i < adapter->num_tx_queues; i++) {
3428 adapter->tx_ring[i].cpu = -1;
3429 igb_update_tx_dca(&adapter->tx_ring[i]);
3430 }
3431 for (i = 0; i < adapter->num_rx_queues; i++) {
3432 adapter->rx_ring[i].cpu = -1;
3433 igb_update_rx_dca(&adapter->rx_ring[i]);
3434 }
3435}
3436
3437static int __igb_notify_dca(struct device *dev, void *data)
3438{
3439 struct net_device *netdev = dev_get_drvdata(dev);
3440 struct igb_adapter *adapter = netdev_priv(netdev);
3441 struct e1000_hw *hw = &adapter->hw;
3442 unsigned long event = *(unsigned long *)data;
3443
3444 switch (event) {
3445 case DCA_PROVIDER_ADD:
3446 /* if already enabled, don't do it again */
7dfc16fa 3447 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3448 break;
fe4506b6
JC		 3449 /* Always use CB2 mode, difference is masked
3450 * in the CB driver. */
3451 wr32(E1000_DCA_CTRL, 2);
3452 if (dca_add_requester(dev) == 0) {
bbd98fe4 3453 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3454 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3455 igb_setup_dca(adapter);
3456 break;
3457 }
3458 /* Fall Through since DCA is disabled. */
3459 case DCA_PROVIDER_REMOVE:
7dfc16fa 3460 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3461 /* without this a class_device is left
3462 * hanging around in the sysfs model */
3463 dca_remove_requester(dev);
3464 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3465 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3466 wr32(E1000_DCA_CTRL, 1);
3467 }
3468 break;
3469 }
bbd98fe4 3470
fe4506b6 3471 return 0;
9d5c8243
AK		 3472}
3473
fe4506b6
JC		 3474static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3475 void *p)
3476{
3477 int ret_val;
3478
3479 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3480 __igb_notify_dca);
3481
3482 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3483}
421e02f0 3484#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3485
3486/**
3487 * igb_intr_msi - Interrupt Handler
3488 * @irq: interrupt number
3489 * @data: pointer to a network interface device structure
3490 **/
3491static irqreturn_t igb_intr_msi(int irq, void *data)
3492{
3493 struct net_device *netdev = data;
3494 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3495 struct e1000_hw *hw = &adapter->hw;
3496 /* read ICR disables interrupts using IAM */
3497 u32 icr = rd32(E1000_ICR);
3498
6eb5a7f1 3499 igb_write_itr(adapter->rx_ring);
9d5c8243 3500
dda0e083
AD		 3501 if(icr & E1000_ICR_DOUTSYNC) {
3502 /* HW is reporting DMA is out of sync */
3503 adapter->stats.doosync++;
3504 }
3505
9d5c8243
AK		 3506 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3507 hw->mac.get_link_status = 1;
3508 if (!test_bit(__IGB_DOWN, &adapter->state))
3509 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3510 }
3511
288379f0 3512 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3513
3514 return IRQ_HANDLED;
3515}
3516
3517/**
4a3c6433 3518 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 3519 * @irq: interrupt number
3520 * @data: pointer to a network interface device structure
3521 **/
3522static irqreturn_t igb_intr(int irq, void *data)
3523{
3524 struct net_device *netdev = data;
3525 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3526 struct e1000_hw *hw = &adapter->hw;
3527 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3528 * need for the IMC write */
3529 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 3530 if (!icr)
3531 return IRQ_NONE; /* Not our interrupt */
3532
6eb5a7f1 3533 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3534
3535 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3536 * not set, then the adapter didn't send an interrupt */
3537 if (!(icr & E1000_ICR_INT_ASSERTED))
3538 return IRQ_NONE;
3539
dda0e083
AD		 3540 if(icr & E1000_ICR_DOUTSYNC) {
3541 /* HW is reporting DMA is out of sync */
3542 adapter->stats.doosync++;
3543 }
3544
9d5c8243
AK		 3545 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3546 hw->mac.get_link_status = 1;
3547 /* guard against interrupt when we're going down */
3548 if (!test_bit(__IGB_DOWN, &adapter->state))
3549 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3550 }
3551
288379f0 3552 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3553
3554 return IRQ_HANDLED;
3555}
3556
3557/**
661086df
PWJ		 3558 * igb_poll - NAPI Rx polling callback
3559 * @napi: napi polling structure
3560 * @budget: count of how many packets we should handle
9d5c8243 3561 **/
661086df 3562static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3563{
661086df
PWJ		 3564 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3565 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3566 struct net_device *netdev = adapter->netdev;
661086df 3567 int tx_clean_complete, work_done = 0;
9d5c8243 3568
661086df 3569 /* this poll routine only supports one tx and one rx queue */
421e02f0 3570#ifdef CONFIG_IGB_DCA
7dfc16fa 3571 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3572 igb_update_tx_dca(&adapter->tx_ring[0]);
3573#endif
661086df 3574 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3575
421e02f0 3576#ifdef CONFIG_IGB_DCA
7dfc16fa 3577 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3578 igb_update_rx_dca(&adapter->rx_ring[0]);
3579#endif
661086df 3580 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3581
3582 /* If no Tx and not enough Rx work done, exit the polling mode */
3583 if ((tx_clean_complete && (work_done < budget)) ||
3584 !netif_running(netdev)) {
9d5c8243 3585 if (adapter->itr_setting & 3)
6eb5a7f1 3586 igb_set_itr(adapter);
288379f0 3587 napi_complete(napi);
9d5c8243
AK		 3588 if (!test_bit(__IGB_DOWN, &adapter->state))
3589 igb_irq_enable(adapter);
3590 return 0;
3591 }
3592
3593 return 1;
3594}
3595
3596static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3597{
3598 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3599 struct igb_adapter *adapter = rx_ring->adapter;
3600 struct e1000_hw *hw = &adapter->hw;
3601 struct net_device *netdev = adapter->netdev;
3602 int work_done = 0;
3603
421e02f0 3604#ifdef CONFIG_IGB_DCA
7dfc16fa 3605 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3606 igb_update_rx_dca(rx_ring);
3607#endif
3b644cf6 3608 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3609
3610
3611 /* If not enough Rx work done, exit the polling mode */
3612 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3613 napi_complete(napi);
9d5c8243 3614
6eb5a7f1
AD		 3615 if (adapter->itr_setting & 3) {
3616 if (adapter->num_rx_queues == 1)
3617 igb_set_itr(adapter);
3618 else
3619 igb_update_ring_itr(rx_ring);
9d5c8243 3620 }
844290e5
PW		 3621
3622 if (!test_bit(__IGB_DOWN, &adapter->state))
3623 wr32(E1000_EIMS, rx_ring->eims_value);
3624
9d5c8243
AK		 3625 return 0;
3626 }
3627
3628 return 1;
3629}
6d8126f9 3630
9d5c8243
AK		 3631/**
3632 * igb_clean_tx_irq - Reclaim resources after transmit completes
3633 * @adapter: board private structure
3634 * returns true if ring is completely cleaned
3635 **/
3b644cf6 3636static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3637{
3b644cf6 3638 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3639 struct net_device *netdev = adapter->netdev;
0e014cb1 3640 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3641 struct igb_buffer *buffer_info;
3642 struct sk_buff *skb;
0e014cb1 3643 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3644 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3645 unsigned int i, eop, count = 0;
3646 bool cleaned = false;
9d5c8243 3647
9d5c8243 3648 i = tx_ring->next_to_clean;
0e014cb1
AD		 3649 eop = tx_ring->buffer_info[i].next_to_watch;
3650 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3651
3652 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3653 (count < tx_ring->count)) {
3654 for (cleaned = false; !cleaned; count++) {
3655 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3656 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3657 cleaned = (i == eop);
9d5c8243
AK		 3658 skb = buffer_info->skb;
3659
3660 if (skb) {
3661 unsigned int segs, bytecount;
3662 /* gso_segs is currently only valid for tcp */
3663 segs = skb_shinfo(skb)->gso_segs ?: 1;
3664 /* multiply data chunks by size of headers */
3665 bytecount = ((segs - 1) * skb_headlen(skb)) +
3666 skb->len;
3667 total_packets += segs;
3668 total_bytes += bytecount;
3669 }
3670
3671 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3672 tx_desc->wb.status = 0;
9d5c8243
AK		 3673
3674 i++;
3675 if (i == tx_ring->count)
3676 i = 0;
9d5c8243 3677 }
0e014cb1
AD		 3678
3679 eop = tx_ring->buffer_info[i].next_to_watch;
3680 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3681 }
3682
9d5c8243
AK		 3683 tx_ring->next_to_clean = i;
3684
fc7d345d 3685 if (unlikely(count &&
9d5c8243
AK		 3686 netif_carrier_ok(netdev) &&
3687 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3688 /* Make sure that anybody stopping the queue after this
3689 * sees the new next_to_clean.
3690 */
3691 smp_mb();
661086df
PWJ		 3692 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3693 !(test_bit(__IGB_DOWN, &adapter->state))) {
3694 netif_wake_subqueue(netdev, tx_ring->queue_index);
3695 ++adapter->restart_queue;
3696 }
9d5c8243
AK		 3697 }
3698
3699 if (tx_ring->detect_tx_hung) {
3700 /* Detect a transmit hang in hardware, this serializes the
3701 * check with the clearing of time_stamp and movement of i */
3702 tx_ring->detect_tx_hung = false;
3703 if (tx_ring->buffer_info[i].time_stamp &&
3704 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3705 (adapter->tx_timeout_factor * HZ))
3706 && !(rd32(E1000_STATUS) &
3707 E1000_STATUS_TXOFF)) {
3708
9d5c8243
AK		 3709 /* detected Tx unit hang */
3710 dev_err(&adapter->pdev->dev,
3711 "Detected Tx Unit Hang\n"
2d064c06 3712 " Tx Queue <%d>\n"
9d5c8243
AK		 3713 " TDH <%x>\n"
3714 " TDT <%x>\n"
3715 " next_to_use <%x>\n"
3716 " next_to_clean <%x>\n"
9d5c8243
AK		 3717 "buffer_info[next_to_clean]\n"
3718 " time_stamp <%lx>\n"
0e014cb1 3719 " next_to_watch <%x>\n"
9d5c8243
AK		 3720 " jiffies <%lx>\n"
3721 " desc.status <%x>\n",
2d064c06 3722 tx_ring->queue_index,
9d5c8243
AK		 3723 readl(adapter->hw.hw_addr + tx_ring->head),
3724 readl(adapter->hw.hw_addr + tx_ring->tail),
3725 tx_ring->next_to_use,
3726 tx_ring->next_to_clean,
9d5c8243 3727 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3728 eop,
9d5c8243 3729 jiffies,
0e014cb1 3730 eop_desc->wb.status);
661086df 3731 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3732 }
3733 }
3734 tx_ring->total_bytes += total_bytes;
3735 tx_ring->total_packets += total_packets;
e21ed353
AD		 3736 tx_ring->tx_stats.bytes += total_bytes;
3737 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3738 adapter->net_stats.tx_bytes += total_bytes;
3739 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3740 return (count < tx_ring->count);
9d5c8243
AK		 3741}
3742
9d5c8243
AK		 3743/**
3744 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3745 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3746 * @status: descriptor status field as written by hardware
3747 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3748 * @skb: pointer to sk_buff to be indicated to stack
3749 **/
d3352520
AD		 3750static void igb_receive_skb(struct igb_ring *ring, u8 status,
3751 union e1000_adv_rx_desc * rx_desc,
3752 struct sk_buff *skb)
3753{
3754 struct igb_adapter * adapter = ring->adapter;
3755 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3756
0c8dfc83 3757 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3758 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3759 if (vlan_extracted)
5c0999b7
HX		 3760 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3761 le16_to_cpu(rx_desc->wb.upper.vlan),
3762 skb);
d3352520 3763 else
5c0999b7 3764 napi_gro_receive(&ring->napi, skb);
d3352520 3765 } else {
d3352520
AD		 3766 if (vlan_extracted)
3767 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3768 le16_to_cpu(rx_desc->wb.upper.vlan));
3769 else
d3352520 3770 netif_receive_skb(skb);
d3352520 3771 }
9d5c8243
AK		 3772}
3773
3774
3775static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3776 u32 status_err, struct sk_buff *skb)
3777{
3778 skb->ip_summed = CHECKSUM_NONE;
3779
3780 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3781 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3782 return;
3783 /* TCP/UDP checksum error bit is set */
3784 if (status_err &
3785 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3786 /* let the stack verify checksum errors */
3787 adapter->hw_csum_err++;
3788 return;
3789 }
3790 /* It must be a TCP or UDP packet with a valid checksum */
3791 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3792 skb->ip_summed = CHECKSUM_UNNECESSARY;
3793
3794 adapter->hw_csum_good++;
3795}
3796
3b644cf6
MW		 3797static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3798 int *work_done, int budget)
9d5c8243 3799{
3b644cf6 3800 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3801 struct net_device *netdev = adapter->netdev;
3802 struct pci_dev *pdev = adapter->pdev;
3803 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3804 struct igb_buffer *buffer_info , *next_buffer;
3805 struct sk_buff *skb;
bf36c1a0 3806 unsigned int i;
9d5c8243
AK		 3807 u32 length, hlen, staterr;
3808 bool cleaned = false;
3809 int cleaned_count = 0;
3810 unsigned int total_bytes = 0, total_packets = 0;
3811
3812 i = rx_ring->next_to_clean;
69d3ca53 3813 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3814 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3815 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3816
3817 while (staterr & E1000_RXD_STAT_DD) {
3818 if (*work_done >= budget)
3819 break;
3820 (*work_done)++;
9d5c8243 3821
69d3ca53
AD		 3822 skb = buffer_info->skb;
3823 prefetch(skb->data - NET_IP_ALIGN);
3824 buffer_info->skb = NULL;
3825
3826 i++;
3827 if (i == rx_ring->count)
3828 i = 0;
3829 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3830 prefetch(next_rxd);
3831 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3832
3833 length = le16_to_cpu(rx_desc->wb.upper.length);
3834 cleaned = true;
3835 cleaned_count++;
3836
bf36c1a0
AD		 3837 if (!adapter->rx_ps_hdr_size) {
3838 pci_unmap_single(pdev, buffer_info->dma,
3839 adapter->rx_buffer_len +
3840 NET_IP_ALIGN,
3841 PCI_DMA_FROMDEVICE);
3842 skb_put(skb, length);
3843 goto send_up;
9d5c8243
AK		 3844 }
3845
69d3ca53
AD		 3846 /* HW will not DMA in data larger than the given buffer, even
3847 * if it parses the (NFS, of course) header to be larger. In
3848 * that case, it fills the header buffer and spills the rest
3849 * into the page.
3850 */
3851 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3852 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3853 if (hlen > adapter->rx_ps_hdr_size)
3854 hlen = adapter->rx_ps_hdr_size;
3855
bf36c1a0
AD		 3856 if (!skb_shinfo(skb)->nr_frags) {
3857 pci_unmap_single(pdev, buffer_info->dma,
3858 adapter->rx_ps_hdr_size +
3859 NET_IP_ALIGN,
3860 PCI_DMA_FROMDEVICE);
3861 skb_put(skb, hlen);
3862 }
3863
3864 if (length) {
9d5c8243 3865 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3866 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3867 buffer_info->page_dma = 0;
bf36c1a0
AD		 3868
3869 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3870 buffer_info->page,
3871 buffer_info->page_offset,
3872 length);
3873
3874 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3875 (page_count(buffer_info->page) != 1))
3876 buffer_info->page = NULL;
3877 else
3878 get_page(buffer_info->page);
9d5c8243
AK		 3879
3880 skb->len += length;
3881 skb->data_len += length;
9d5c8243 3882
bf36c1a0 3883 skb->truesize += length;
9d5c8243 3884 }
9d5c8243 3885
bf36c1a0 3886 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3887 buffer_info->skb = next_buffer->skb;
3888 buffer_info->dma = next_buffer->dma;
3889 next_buffer->skb = skb;
3890 next_buffer->dma = 0;
bf36c1a0
AD		 3891 goto next_desc;
3892 }
69d3ca53 3893send_up:
9d5c8243
AK		 3894 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3895 dev_kfree_skb_irq(skb);
3896 goto next_desc;
3897 }
9d5c8243
AK		 3898
3899 total_bytes += skb->len;
3900 total_packets++;
3901
3902 igb_rx_checksum_adv(adapter, staterr, skb);
3903
3904 skb->protocol = eth_type_trans(skb, netdev);
3905
d3352520 3906 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3907
9d5c8243
AK		 3908next_desc:
3909 rx_desc->wb.upper.status_error = 0;
3910
3911 /* return some buffers to hardware, one at a time is too slow */
3912 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3913 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3914 cleaned_count = 0;
3915 }
3916
3917 /* use prefetched values */
3918 rx_desc = next_rxd;
3919 buffer_info = next_buffer;
9d5c8243
AK		 3920 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3921 }
bf36c1a0 3922
9d5c8243
AK		 3923 rx_ring->next_to_clean = i;
3924 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3925
3926 if (cleaned_count)
3b644cf6 3927 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3928
3929 rx_ring->total_packets += total_packets;
3930 rx_ring->total_bytes += total_bytes;
3931 rx_ring->rx_stats.packets += total_packets;
3932 rx_ring->rx_stats.bytes += total_bytes;
3933 adapter->net_stats.rx_bytes += total_bytes;
3934 adapter->net_stats.rx_packets += total_packets;
3935 return cleaned;
3936}
3937
3938
3939/**
3940 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3941 * @adapter: address of board private structure
3942 **/
3b644cf6 3943static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3944 int cleaned_count)
3945{
3b644cf6 3946 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3947 struct net_device *netdev = adapter->netdev;
3948 struct pci_dev *pdev = adapter->pdev;
3949 union e1000_adv_rx_desc *rx_desc;
3950 struct igb_buffer *buffer_info;
3951 struct sk_buff *skb;
3952 unsigned int i;
db761762 3953 int bufsz;
9d5c8243
AK		 3954
3955 i = rx_ring->next_to_use;
3956 buffer_info = &rx_ring->buffer_info[i];
3957
db761762
AD		 3958 if (adapter->rx_ps_hdr_size)
3959 bufsz = adapter->rx_ps_hdr_size;
3960 else
3961 bufsz = adapter->rx_buffer_len;
3962 bufsz += NET_IP_ALIGN;
3963
9d5c8243
AK		 3964 while (cleaned_count--) {
3965 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3966
bf36c1a0 3967 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3968 if (!buffer_info->page) {
bf36c1a0
AD		 3969 buffer_info->page = alloc_page(GFP_ATOMIC);
3970 if (!buffer_info->page) {
3971 adapter->alloc_rx_buff_failed++;
3972 goto no_buffers;
3973 }
3974 buffer_info->page_offset = 0;
3975 } else {
3976 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3977 }
3978 buffer_info->page_dma =
db761762 3979 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3980 buffer_info->page_offset,
3981 PAGE_SIZE / 2,
9d5c8243
AK		 3982 PCI_DMA_FROMDEVICE);
3983 }
3984
3985 if (!buffer_info->skb) {
9d5c8243 3986 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3987 if (!skb) {
3988 adapter->alloc_rx_buff_failed++;
3989 goto no_buffers;
3990 }
3991
3992 /* Make buffer alignment 2 beyond a 16 byte boundary
3993 * this will result in a 16 byte aligned IP header after
3994 * the 14 byte MAC header is removed
3995 */
3996 skb_reserve(skb, NET_IP_ALIGN);
3997
3998 buffer_info->skb = skb;
3999 buffer_info->dma = pci_map_single(pdev, skb->data,
4000 bufsz,
4001 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4002 }
4003 /* Refresh the desc even if buffer_addrs didn't change because
4004 * each write-back erases this info. */
4005 if (adapter->rx_ps_hdr_size) {
4006 rx_desc->read.pkt_addr =
4007 cpu_to_le64(buffer_info->page_dma);
4008 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4009 } else {
4010 rx_desc->read.pkt_addr =
4011 cpu_to_le64(buffer_info->dma);
4012 rx_desc->read.hdr_addr = 0;
4013 }
4014
4015 i++;
4016 if (i == rx_ring->count)
4017 i = 0;
4018 buffer_info = &rx_ring->buffer_info[i];
4019 }
4020
4021no_buffers:
4022 if (rx_ring->next_to_use != i) {
4023 rx_ring->next_to_use = i;
4024 if (i == 0)
4025 i = (rx_ring->count - 1);
4026 else
4027 i--;
4028
4029 /* Force memory writes to complete before letting h/w
4030 * know there are new descriptors to fetch. (Only
4031 * applicable for weak-ordered memory model archs,
4032 * such as IA-64). */
4033 wmb();
4034 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4035 }
4036}
4037
4038/**
4039 * igb_mii_ioctl -
4040 * @netdev:
4041 * @ifreq:
4042 * @cmd:
4043 **/
4044static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4045{
4046 struct igb_adapter *adapter = netdev_priv(netdev);
4047 struct mii_ioctl_data *data = if_mii(ifr);
4048
4049 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4050 return -EOPNOTSUPP;
4051
4052 switch (cmd) {
4053 case SIOCGMIIPHY:
4054 data->phy_id = adapter->hw.phy.addr;
4055 break;
4056 case SIOCGMIIREG:
4057 if (!capable(CAP_NET_ADMIN))
4058 return -EPERM;
f5f4cf08
AD		 4059 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4060 &data->val_out))
9d5c8243
AK		 4061 return -EIO;
4062 break;
4063 case SIOCSMIIREG:
4064 default:
4065 return -EOPNOTSUPP;
4066 }
4067 return 0;
4068}
4069
4070/**
4071 * igb_ioctl -
4072 * @netdev:
4073 * @ifreq:
4074 * @cmd:
4075 **/
4076static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4077{
4078 switch (cmd) {
4079 case SIOCGMIIPHY:
4080 case SIOCGMIIREG:
4081 case SIOCSMIIREG:
4082 return igb_mii_ioctl(netdev, ifr, cmd);
4083 default:
4084 return -EOPNOTSUPP;
4085 }
4086}
4087
4088static void igb_vlan_rx_register(struct net_device *netdev,
4089 struct vlan_group *grp)
4090{
4091 struct igb_adapter *adapter = netdev_priv(netdev);
4092 struct e1000_hw *hw = &adapter->hw;
4093 u32 ctrl, rctl;
4094
4095 igb_irq_disable(adapter);
4096 adapter->vlgrp = grp;
4097
4098 if (grp) {
4099 /* enable VLAN tag insert/strip */
4100 ctrl = rd32(E1000_CTRL);
4101 ctrl |= E1000_CTRL_VME;
4102 wr32(E1000_CTRL, ctrl);
4103
4104 /* enable VLAN receive filtering */
4105 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4106 rctl &= ~E1000_RCTL_CFIEN;
4107 wr32(E1000_RCTL, rctl);
4108 igb_update_mng_vlan(adapter);
4109 wr32(E1000_RLPML,
4110 adapter->max_frame_size + VLAN_TAG_SIZE);
4111 } else {
4112 /* disable VLAN tag insert/strip */
4113 ctrl = rd32(E1000_CTRL);
4114 ctrl &= ~E1000_CTRL_VME;
4115 wr32(E1000_CTRL, ctrl);
4116
9d5c8243
AK		 4117 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4118 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4119 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4120 }
4121 wr32(E1000_RLPML,
4122 adapter->max_frame_size);
4123 }
4124
4125 if (!test_bit(__IGB_DOWN, &adapter->state))
4126 igb_irq_enable(adapter);
4127}
4128
4129static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4130{
4131 struct igb_adapter *adapter = netdev_priv(netdev);
4132 struct e1000_hw *hw = &adapter->hw;
4133 u32 vfta, index;
4134
28b0759c 4135 if ((hw->mng_cookie.status &
9d5c8243
AK		 4136 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4137 (vid == adapter->mng_vlan_id))
4138 return;
4139 /* add VID to filter table */
4140 index = (vid >> 5) & 0x7F;
4141 vfta = array_rd32(E1000_VFTA, index);
4142 vfta |= (1 << (vid & 0x1F));
4143 igb_write_vfta(&adapter->hw, index, vfta);
4144}
4145
4146static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4147{
4148 struct igb_adapter *adapter = netdev_priv(netdev);
4149 struct e1000_hw *hw = &adapter->hw;
4150 u32 vfta, index;
4151
4152 igb_irq_disable(adapter);
4153 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4154
4155 if (!test_bit(__IGB_DOWN, &adapter->state))
4156 igb_irq_enable(adapter);
4157
4158 if ((adapter->hw.mng_cookie.status &
4159 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4160 (vid == adapter->mng_vlan_id)) {
4161 /* release control to f/w */
4162 igb_release_hw_control(adapter);
4163 return;
4164 }
4165
4166 /* remove VID from filter table */
4167 index = (vid >> 5) & 0x7F;
4168 vfta = array_rd32(E1000_VFTA, index);
4169 vfta &= ~(1 << (vid & 0x1F));
4170 igb_write_vfta(&adapter->hw, index, vfta);
4171}
4172
4173static void igb_restore_vlan(struct igb_adapter *adapter)
4174{
4175 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4176
4177 if (adapter->vlgrp) {
4178 u16 vid;
4179 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4180 if (!vlan_group_get_device(adapter->vlgrp, vid))
4181 continue;
4182 igb_vlan_rx_add_vid(adapter->netdev, vid);
4183 }
4184 }
4185}
4186
4187int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4188{
4189 struct e1000_mac_info *mac = &adapter->hw.mac;
4190
4191 mac->autoneg = 0;
4192
4193 /* Fiber NICs only allow 1000 gbps Full duplex */
4194 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4195 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4196 dev_err(&adapter->pdev->dev,
4197 "Unsupported Speed/Duplex configuration\n");
4198 return -EINVAL;
4199 }
4200
4201 switch (spddplx) {
4202 case SPEED_10 + DUPLEX_HALF:
4203 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4204 break;
4205 case SPEED_10 + DUPLEX_FULL:
4206 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4207 break;
4208 case SPEED_100 + DUPLEX_HALF:
4209 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4210 break;
4211 case SPEED_100 + DUPLEX_FULL:
4212 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4213 break;
4214 case SPEED_1000 + DUPLEX_FULL:
4215 mac->autoneg = 1;
4216 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4217 break;
4218 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4219 default:
4220 dev_err(&adapter->pdev->dev,
4221 "Unsupported Speed/Duplex configuration\n");
4222 return -EINVAL;
4223 }
4224 return 0;
4225}
4226
4227
4228static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4229{
4230 struct net_device *netdev = pci_get_drvdata(pdev);
4231 struct igb_adapter *adapter = netdev_priv(netdev);
4232 struct e1000_hw *hw = &adapter->hw;
2d064c06 4233 u32 ctrl, rctl, status;
9d5c8243
AK		 4234 u32 wufc = adapter->wol;
4235#ifdef CONFIG_PM
4236 int retval = 0;
4237#endif
4238
4239 netif_device_detach(netdev);
4240
a88f10ec
AD		 4241 if (netif_running(netdev))
4242 igb_close(netdev);
4243
4244 igb_reset_interrupt_capability(adapter);
4245
4246 igb_free_queues(adapter);
9d5c8243
AK		 4247
4248#ifdef CONFIG_PM
4249 retval = pci_save_state(pdev);
4250 if (retval)
4251 return retval;
4252#endif
4253
4254 status = rd32(E1000_STATUS);
4255 if (status & E1000_STATUS_LU)
4256 wufc &= ~E1000_WUFC_LNKC;
4257
4258 if (wufc) {
4259 igb_setup_rctl(adapter);
4260 igb_set_multi(netdev);
4261
4262 /* turn on all-multi mode if wake on multicast is enabled */
4263 if (wufc & E1000_WUFC_MC) {
4264 rctl = rd32(E1000_RCTL);
4265 rctl |= E1000_RCTL_MPE;
4266 wr32(E1000_RCTL, rctl);
4267 }
4268
4269 ctrl = rd32(E1000_CTRL);
4270 /* advertise wake from D3Cold */
4271 #define E1000_CTRL_ADVD3WUC 0x00100000
4272 /* phy power management enable */
4273 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4274 ctrl |= E1000_CTRL_ADVD3WUC;
4275 wr32(E1000_CTRL, ctrl);
4276
9d5c8243
AK		 4277 /* Allow time for pending master requests to run */
4278 igb_disable_pcie_master(&adapter->hw);
4279
4280 wr32(E1000_WUC, E1000_WUC_PME_EN);
4281 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4282 } else {
4283 wr32(E1000_WUC, 0);
4284 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4285 }
4286
2d064c06
AD		 4287 /* make sure adapter isn't asleep if manageability/wol is enabled */
4288 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4289 pci_enable_wake(pdev, PCI_D3hot, 1);
4290 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4291 } else {
4292 igb_shutdown_fiber_serdes_link_82575(hw);
4293 pci_enable_wake(pdev, PCI_D3hot, 0);
4294 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4295 }
4296
4297 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4298 * would have already happened in close and is redundant. */
4299 igb_release_hw_control(adapter);
4300
4301 pci_disable_device(pdev);
4302
4303 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4304
4305 return 0;
4306}
4307
4308#ifdef CONFIG_PM
4309static int igb_resume(struct pci_dev *pdev)
4310{
4311 struct net_device *netdev = pci_get_drvdata(pdev);
4312 struct igb_adapter *adapter = netdev_priv(netdev);
4313 struct e1000_hw *hw = &adapter->hw;
4314 u32 err;
4315
4316 pci_set_power_state(pdev, PCI_D0);
4317 pci_restore_state(pdev);
42bfd33a 4318
aed5dec3 4319 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4320 if (err) {
4321 dev_err(&pdev->dev,
4322 "igb: Cannot enable PCI device from suspend\n");
4323 return err;
4324 }
4325 pci_set_master(pdev);
4326
4327 pci_enable_wake(pdev, PCI_D3hot, 0);
4328 pci_enable_wake(pdev, PCI_D3cold, 0);
4329
a88f10ec
AD		 4330 igb_set_interrupt_capability(adapter);
4331
4332 if (igb_alloc_queues(adapter)) {
4333 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4334 return -ENOMEM;
9d5c8243
AK		 4335 }
4336
4337 /* e1000_power_up_phy(adapter); */
4338
4339 igb_reset(adapter);
a8564f03
AD		 4340
4341 /* let the f/w know that the h/w is now under the control of the
4342 * driver. */
4343 igb_get_hw_control(adapter);
4344
9d5c8243
AK		 4345 wr32(E1000_WUS, ~0);
4346
a88f10ec
AD		 4347 if (netif_running(netdev)) {
4348 err = igb_open(netdev);
4349 if (err)
4350 return err;
4351 }
9d5c8243
AK		 4352
4353 netif_device_attach(netdev);
4354
9d5c8243
AK		 4355 return 0;
4356}
4357#endif
4358
4359static void igb_shutdown(struct pci_dev *pdev)
4360{
4361 igb_suspend(pdev, PMSG_SUSPEND);
4362}
4363
4364#ifdef CONFIG_NET_POLL_CONTROLLER
4365/*
4366 * Polling 'interrupt' - used by things like netconsole to send skbs
4367 * without having to re-enable interrupts. It's not called while
4368 * the interrupt routine is executing.
4369 */
4370static void igb_netpoll(struct net_device *netdev)
4371{
4372 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4373 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4374 int i;
9d5c8243 4375
eebbbdba
AD		 4376 if (!adapter->msix_entries) {
4377 igb_irq_disable(adapter);
4378 napi_schedule(&adapter->rx_ring[0].napi);
4379 return;
4380 }
9d5c8243 4381
eebbbdba
AD		 4382 for (i = 0; i < adapter->num_tx_queues; i++) {
4383 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4384 wr32(E1000_EIMC, tx_ring->eims_value);
4385 igb_clean_tx_irq(tx_ring);
4386 wr32(E1000_EIMS, tx_ring->eims_value);
4387 }
9d5c8243 4388
eebbbdba
AD		 4389 for (i = 0; i < adapter->num_rx_queues; i++) {
4390 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4391 wr32(E1000_EIMC, rx_ring->eims_value);
4392 napi_schedule(&rx_ring->napi);
4393 }
9d5c8243
AK		 4394}
4395#endif /* CONFIG_NET_POLL_CONTROLLER */
4396
4397/**
4398 * igb_io_error_detected - called when PCI error is detected
4399 * @pdev: Pointer to PCI device
4400 * @state: The current pci connection state
4401 *
4402 * This function is called after a PCI bus error affecting
4403 * this device has been detected.
4404 */
4405static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4406 pci_channel_state_t state)
4407{
4408 struct net_device *netdev = pci_get_drvdata(pdev);
4409 struct igb_adapter *adapter = netdev_priv(netdev);
4410
4411 netif_device_detach(netdev);
4412
4413 if (netif_running(netdev))
4414 igb_down(adapter);
4415 pci_disable_device(pdev);
4416
4417 /* Request a slot slot reset. */
4418 return PCI_ERS_RESULT_NEED_RESET;
4419}
4420
4421/**
4422 * igb_io_slot_reset - called after the pci bus has been reset.
4423 * @pdev: Pointer to PCI device
4424 *
4425 * Restart the card from scratch, as if from a cold-boot. Implementation
4426 * resembles the first-half of the igb_resume routine.
4427 */
4428static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4429{
4430 struct net_device *netdev = pci_get_drvdata(pdev);
4431 struct igb_adapter *adapter = netdev_priv(netdev);
4432 struct e1000_hw *hw = &adapter->hw;
40a914fa 4433 pci_ers_result_t result;
42bfd33a 4434 int err;
9d5c8243 4435
aed5dec3 4436 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4437 dev_err(&pdev->dev,
4438 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4439 result = PCI_ERS_RESULT_DISCONNECT;
4440 } else {
4441 pci_set_master(pdev);
4442 pci_restore_state(pdev);
9d5c8243 4443
40a914fa
AD		 4444 pci_enable_wake(pdev, PCI_D3hot, 0);
4445 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4446
40a914fa
AD		 4447 igb_reset(adapter);
4448 wr32(E1000_WUS, ~0);
4449 result = PCI_ERS_RESULT_RECOVERED;
4450 }
9d5c8243 4451
ea943d41
JK		 4452 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4453 if (err) {
4454 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4455 "failed 0x%0x\n", err);
4456 /* non-fatal, continue */
4457 }
40a914fa
AD		 4458
4459 return result;
9d5c8243
AK		 4460}
4461
4462/**
4463 * igb_io_resume - called when traffic can start flowing again.
4464 * @pdev: Pointer to PCI device
4465 *
4466 * This callback is called when the error recovery driver tells us that
4467 * its OK to resume normal operation. Implementation resembles the
4468 * second-half of the igb_resume routine.
4469 */
4470static void igb_io_resume(struct pci_dev *pdev)
4471{
4472 struct net_device *netdev = pci_get_drvdata(pdev);
4473 struct igb_adapter *adapter = netdev_priv(netdev);
4474
9d5c8243
AK		 4475 if (netif_running(netdev)) {
4476 if (igb_up(adapter)) {
4477 dev_err(&pdev->dev, "igb_up failed after reset\n");
4478 return;
4479 }
4480 }
4481
4482 netif_device_attach(netdev);
4483
4484 /* let the f/w know that the h/w is now under the control of the
4485 * driver. */
4486 igb_get_hw_control(adapter);
9d5c8243
AK		 4487}
4488
4489/* igb_main.c */
Clone of davem's net-next-2.6 tree