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[net-next-2.6.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
9d5c8243 206 ret = pci_register_driver(&igb_driver);
421e02f0 207#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 208 dca_register_notify(&dca_notifier);
209#endif
9d5c8243
AK		 210 return ret;
211}
212
213module_init(igb_init_module);
214
215/**
216 * igb_exit_module - Driver Exit Cleanup Routine
217 *
218 * igb_exit_module is called just before the driver is removed
219 * from memory.
220 **/
221static void __exit igb_exit_module(void)
222{
421e02f0 223#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 224 dca_unregister_notify(&dca_notifier);
225#endif
9d5c8243
AK		 226 pci_unregister_driver(&igb_driver);
227}
228
229module_exit(igb_exit_module);
230
26bc19ec
AD		 231#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
232/**
233 * igb_cache_ring_register - Descriptor ring to register mapping
234 * @adapter: board private structure to initialize
235 *
236 * Once we know the feature-set enabled for the device, we'll cache
237 * the register offset the descriptor ring is assigned to.
238 **/
239static void igb_cache_ring_register(struct igb_adapter *adapter)
240{
241 int i;
242
243 switch (adapter->hw.mac.type) {
244 case e1000_82576:
245 /* The queues are allocated for virtualization such that VF 0
246 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
247 * In order to avoid collision we start at the first free queue
248 * and continue consuming queues in the same sequence
249 */
250 for (i = 0; i < adapter->num_rx_queues; i++)
251 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
252 for (i = 0; i < adapter->num_tx_queues; i++)
253 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
254 break;
255 case e1000_82575:
256 default:
257 for (i = 0; i < adapter->num_rx_queues; i++)
258 adapter->rx_ring[i].reg_idx = i;
259 for (i = 0; i < adapter->num_tx_queues; i++)
260 adapter->tx_ring[i].reg_idx = i;
261 break;
262 }
263}
264
9d5c8243
AK		 265/**
266 * igb_alloc_queues - Allocate memory for all rings
267 * @adapter: board private structure to initialize
268 *
269 * We allocate one ring per queue at run-time since we don't know the
270 * number of queues at compile-time.
271 **/
272static int igb_alloc_queues(struct igb_adapter *adapter)
273{
274 int i;
275
276 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
277 sizeof(struct igb_ring), GFP_KERNEL);
278 if (!adapter->tx_ring)
279 return -ENOMEM;
280
281 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
282 sizeof(struct igb_ring), GFP_KERNEL);
283 if (!adapter->rx_ring) {
284 kfree(adapter->tx_ring);
285 return -ENOMEM;
286 }
287
6eb5a7f1
AD		 288 adapter->rx_ring->buddy = adapter->tx_ring;
289
661086df
PWJ		 290 for (i = 0; i < adapter->num_tx_queues; i++) {
291 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 292 ring->count = adapter->tx_ring_count;
661086df
PWJ		 293 ring->adapter = adapter;
294 ring->queue_index = i;
295 }
9d5c8243
AK		 296 for (i = 0; i < adapter->num_rx_queues; i++) {
297 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 298 ring->count = adapter->rx_ring_count;
9d5c8243 299 ring->adapter = adapter;
844290e5 300 ring->queue_index = i;
9d5c8243
AK		 301 ring->itr_register = E1000_ITR;
302
844290e5 303 /* set a default napi handler for each rx_ring */
661086df 304 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 305 }
26bc19ec
AD		 306
307 igb_cache_ring_register(adapter);
9d5c8243
AK		 308 return 0;
309}
310
a88f10ec
AD		 311static void igb_free_queues(struct igb_adapter *adapter)
312{
313 int i;
314
315 for (i = 0; i < adapter->num_rx_queues; i++)
316 netif_napi_del(&adapter->rx_ring[i].napi);
317
318 kfree(adapter->tx_ring);
319 kfree(adapter->rx_ring);
320}
321
9d5c8243
AK		 322#define IGB_N0_QUEUE -1
323static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
324 int tx_queue, int msix_vector)
325{
326 u32 msixbm = 0;
327 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 328 u32 ivar, index;
329
330 switch (hw->mac.type) {
331 case e1000_82575:
9d5c8243
AK		 332 /* The 82575 assigns vectors using a bitmask, which matches the
333 bitmask for the EICR/EIMS/EIMC registers. To assign one
334 or more queues to a vector, we write the appropriate bits
335 into the MSIXBM register for that vector. */
336 if (rx_queue > IGB_N0_QUEUE) {
337 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
338 adapter->rx_ring[rx_queue].eims_value = msixbm;
339 }
340 if (tx_queue > IGB_N0_QUEUE) {
341 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
342 adapter->tx_ring[tx_queue].eims_value =
343 E1000_EICR_TX_QUEUE0 << tx_queue;
344 }
345 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 346 break;
347 case e1000_82576:
26bc19ec 348 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 349 Each queue has a single entry in the table to which we write
350 a vector number along with a "valid" bit. Sadly, the layout
351 of the table is somewhat counterintuitive. */
352 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 353 index = (rx_queue >> 1);
2d064c06 354 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 355 if (rx_queue & 0x1) {
2d064c06
AD		 356 /* vector goes into third byte of register */
357 ivar = ivar & 0xFF00FFFF;
358 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 359 } else {
360 /* vector goes into low byte of register */
361 ivar = ivar & 0xFFFFFF00;
362 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 363 }
364 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
365 array_wr32(E1000_IVAR0, index, ivar);
366 }
367 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 368 index = (tx_queue >> 1);
2d064c06 369 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 370 if (tx_queue & 0x1) {
2d064c06
AD		 371 /* vector goes into high byte of register */
372 ivar = ivar & 0x00FFFFFF;
373 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 374 } else {
375 /* vector goes into second byte of register */
376 ivar = ivar & 0xFFFF00FF;
377 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 378 }
379 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
380 array_wr32(E1000_IVAR0, index, ivar);
381 }
382 break;
383 default:
384 BUG();
385 break;
386 }
9d5c8243
AK		 387}
388
389/**
390 * igb_configure_msix - Configure MSI-X hardware
391 *
392 * igb_configure_msix sets up the hardware to properly
393 * generate MSI-X interrupts.
394 **/
395static void igb_configure_msix(struct igb_adapter *adapter)
396{
397 u32 tmp;
398 int i, vector = 0;
399 struct e1000_hw *hw = &adapter->hw;
400
401 adapter->eims_enable_mask = 0;
2d064c06
AD		 402 if (hw->mac.type == e1000_82576)
403 /* Turn on MSI-X capability first, or our settings
404 * won't stick. And it will take days to debug. */
405 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
406 E1000_GPIE_PBA | E1000_GPIE_EIAME |
407 E1000_GPIE_NSICR);
9d5c8243
AK		 408
409 for (i = 0; i < adapter->num_tx_queues; i++) {
410 struct igb_ring *tx_ring = &adapter->tx_ring[i];
411 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
412 adapter->eims_enable_mask |= tx_ring->eims_value;
413 if (tx_ring->itr_val)
6eb5a7f1 414 writel(tx_ring->itr_val,
9d5c8243
AK		 415 hw->hw_addr + tx_ring->itr_register);
416 else
417 writel(1, hw->hw_addr + tx_ring->itr_register);
418 }
419
420 for (i = 0; i < adapter->num_rx_queues; i++) {
421 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 422 rx_ring->buddy = NULL;
9d5c8243
AK		 423 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
424 adapter->eims_enable_mask |= rx_ring->eims_value;
425 if (rx_ring->itr_val)
6eb5a7f1 426 writel(rx_ring->itr_val,
9d5c8243
AK		 427 hw->hw_addr + rx_ring->itr_register);
428 else
429 writel(1, hw->hw_addr + rx_ring->itr_register);
430 }
431
432
433 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 434 switch (hw->mac.type) {
435 case e1000_82575:
9d5c8243
AK		 436 array_wr32(E1000_MSIXBM(0), vector++,
437 E1000_EIMS_OTHER);
438
9d5c8243
AK		 439 tmp = rd32(E1000_CTRL_EXT);
440 /* enable MSI-X PBA support*/
441 tmp |= E1000_CTRL_EXT_PBA_CLR;
442
443 /* Auto-Mask interrupts upon ICR read. */
444 tmp |= E1000_CTRL_EXT_EIAME;
445 tmp |= E1000_CTRL_EXT_IRCA;
446
447 wr32(E1000_CTRL_EXT, tmp);
448 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 449 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 450
2d064c06
AD		 451 break;
452
453 case e1000_82576:
454 tmp = (vector++ | E1000_IVAR_VALID) << 8;
455 wr32(E1000_IVAR_MISC, tmp);
456
457 adapter->eims_enable_mask = (1 << (vector)) - 1;
458 adapter->eims_other = 1 << (vector - 1);
459 break;
460 default:
461 /* do nothing, since nothing else supports MSI-X */
462 break;
463 } /* switch (hw->mac.type) */
9d5c8243
AK		 464 wrfl();
465}
466
467/**
468 * igb_request_msix - Initialize MSI-X interrupts
469 *
470 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
471 * kernel.
472 **/
473static int igb_request_msix(struct igb_adapter *adapter)
474{
475 struct net_device *netdev = adapter->netdev;
476 int i, err = 0, vector = 0;
477
478 vector = 0;
479
480 for (i = 0; i < adapter->num_tx_queues; i++) {
481 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 482 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 483 err = request_irq(adapter->msix_entries[vector].vector,
484 &igb_msix_tx, 0, ring->name,
485 &(adapter->tx_ring[i]));
486 if (err)
487 goto out;
488 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 489 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 490 vector++;
491 }
492 for (i = 0; i < adapter->num_rx_queues; i++) {
493 struct igb_ring *ring = &(adapter->rx_ring[i]);
494 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 495 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 496 else
497 memcpy(ring->name, netdev->name, IFNAMSIZ);
498 err = request_irq(adapter->msix_entries[vector].vector,
499 &igb_msix_rx, 0, ring->name,
500 &(adapter->rx_ring[i]));
501 if (err)
502 goto out;
503 ring->itr_register = E1000_EITR(0) + (vector << 2);
504 ring->itr_val = adapter->itr;
844290e5
PW		 505 /* overwrite the poll routine for MSIX, we've already done
506 * netif_napi_add */
507 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 508 vector++;
509 }
510
511 err = request_irq(adapter->msix_entries[vector].vector,
512 &igb_msix_other, 0, netdev->name, netdev);
513 if (err)
514 goto out;
515
9d5c8243
AK		 516 igb_configure_msix(adapter);
517 return 0;
518out:
519 return err;
520}
521
522static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
523{
524 if (adapter->msix_entries) {
525 pci_disable_msix(adapter->pdev);
526 kfree(adapter->msix_entries);
527 adapter->msix_entries = NULL;
7dfc16fa 528 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 529 pci_disable_msi(adapter->pdev);
530 return;
531}
532
533
534/**
535 * igb_set_interrupt_capability - set MSI or MSI-X if supported
536 *
537 * Attempt to configure interrupts using the best available
538 * capabilities of the hardware and kernel.
539 **/
540static void igb_set_interrupt_capability(struct igb_adapter *adapter)
541{
542 int err;
543 int numvecs, i;
544
545 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
546 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
547 GFP_KERNEL);
548 if (!adapter->msix_entries)
549 goto msi_only;
550
551 for (i = 0; i < numvecs; i++)
552 adapter->msix_entries[i].entry = i;
553
554 err = pci_enable_msix(adapter->pdev,
555 adapter->msix_entries,
556 numvecs);
557 if (err == 0)
34a20e89 558 goto out;
9d5c8243
AK		 559
560 igb_reset_interrupt_capability(adapter);
561
562 /* If we can't do MSI-X, try MSI */
563msi_only:
564 adapter->num_rx_queues = 1;
661086df 565 adapter->num_tx_queues = 1;
9d5c8243 566 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 567 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 568out:
661086df 569 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 570 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 571 return;
572}
573
574/**
575 * igb_request_irq - initialize interrupts
576 *
577 * Attempts to configure interrupts using the best available
578 * capabilities of the hardware and kernel.
579 **/
580static int igb_request_irq(struct igb_adapter *adapter)
581{
582 struct net_device *netdev = adapter->netdev;
583 struct e1000_hw *hw = &adapter->hw;
584 int err = 0;
585
586 if (adapter->msix_entries) {
587 err = igb_request_msix(adapter);
844290e5 588 if (!err)
9d5c8243 589 goto request_done;
9d5c8243
AK		 590 /* fall back to MSI */
591 igb_reset_interrupt_capability(adapter);
592 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 593 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 594 igb_free_all_tx_resources(adapter);
595 igb_free_all_rx_resources(adapter);
596 adapter->num_rx_queues = 1;
597 igb_alloc_queues(adapter);
844290e5 598 } else {
2d064c06
AD		 599 switch (hw->mac.type) {
600 case e1000_82575:
601 wr32(E1000_MSIXBM(0),
602 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
603 break;
604 case e1000_82576:
605 wr32(E1000_IVAR0, E1000_IVAR_VALID);
606 break;
607 default:
608 break;
609 }
9d5c8243 610 }
844290e5 611
7dfc16fa 612 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 613 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
614 netdev->name, netdev);
615 if (!err)
616 goto request_done;
617 /* fall back to legacy interrupts */
618 igb_reset_interrupt_capability(adapter);
7dfc16fa 619 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 620 }
621
622 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
623 netdev->name, netdev);
624
6cb5e577 625 if (err)
9d5c8243
AK		 626 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
627 err);
9d5c8243
AK		 628
629request_done:
630 return err;
631}
632
633static void igb_free_irq(struct igb_adapter *adapter)
634{
635 struct net_device *netdev = adapter->netdev;
636
637 if (adapter->msix_entries) {
638 int vector = 0, i;
639
640 for (i = 0; i < adapter->num_tx_queues; i++)
641 free_irq(adapter->msix_entries[vector++].vector,
642 &(adapter->tx_ring[i]));
643 for (i = 0; i < adapter->num_rx_queues; i++)
644 free_irq(adapter->msix_entries[vector++].vector,
645 &(adapter->rx_ring[i]));
646
647 free_irq(adapter->msix_entries[vector++].vector, netdev);
648 return;
649 }
650
651 free_irq(adapter->pdev->irq, netdev);
652}
653
654/**
655 * igb_irq_disable - Mask off interrupt generation on the NIC
656 * @adapter: board private structure
657 **/
658static void igb_irq_disable(struct igb_adapter *adapter)
659{
660 struct e1000_hw *hw = &adapter->hw;
661
662 if (adapter->msix_entries) {
844290e5 663 wr32(E1000_EIAM, 0);
9d5c8243
AK		 664 wr32(E1000_EIMC, ~0);
665 wr32(E1000_EIAC, 0);
666 }
844290e5
PW		 667
668 wr32(E1000_IAM, 0);
9d5c8243
AK		 669 wr32(E1000_IMC, ~0);
670 wrfl();
671 synchronize_irq(adapter->pdev->irq);
672}
673
674/**
675 * igb_irq_enable - Enable default interrupt generation settings
676 * @adapter: board private structure
677 **/
678static void igb_irq_enable(struct igb_adapter *adapter)
679{
680 struct e1000_hw *hw = &adapter->hw;
681
682 if (adapter->msix_entries) {
844290e5
PW		 683 wr32(E1000_EIAC, adapter->eims_enable_mask);
684 wr32(E1000_EIAM, adapter->eims_enable_mask);
685 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 686 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 687 } else {
688 wr32(E1000_IMS, IMS_ENABLE_MASK);
689 wr32(E1000_IAM, IMS_ENABLE_MASK);
690 }
9d5c8243
AK		 691}
692
693static void igb_update_mng_vlan(struct igb_adapter *adapter)
694{
695 struct net_device *netdev = adapter->netdev;
696 u16 vid = adapter->hw.mng_cookie.vlan_id;
697 u16 old_vid = adapter->mng_vlan_id;
698 if (adapter->vlgrp) {
699 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
700 if (adapter->hw.mng_cookie.status &
701 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
702 igb_vlan_rx_add_vid(netdev, vid);
703 adapter->mng_vlan_id = vid;
704 } else
705 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
706
707 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
708 (vid != old_vid) &&
709 !vlan_group_get_device(adapter->vlgrp, old_vid))
710 igb_vlan_rx_kill_vid(netdev, old_vid);
711 } else
712 adapter->mng_vlan_id = vid;
713 }
714}
715
716/**
717 * igb_release_hw_control - release control of the h/w to f/w
718 * @adapter: address of board private structure
719 *
720 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
721 * For ASF and Pass Through versions of f/w this means that the
722 * driver is no longer loaded.
723 *
724 **/
725static void igb_release_hw_control(struct igb_adapter *adapter)
726{
727 struct e1000_hw *hw = &adapter->hw;
728 u32 ctrl_ext;
729
730 /* Let firmware take over control of h/w */
731 ctrl_ext = rd32(E1000_CTRL_EXT);
732 wr32(E1000_CTRL_EXT,
733 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
734}
735
736
737/**
738 * igb_get_hw_control - get control of the h/w from f/w
739 * @adapter: address of board private structure
740 *
741 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
742 * For ASF and Pass Through versions of f/w this means that
743 * the driver is loaded.
744 *
745 **/
746static void igb_get_hw_control(struct igb_adapter *adapter)
747{
748 struct e1000_hw *hw = &adapter->hw;
749 u32 ctrl_ext;
750
751 /* Let firmware know the driver has taken over */
752 ctrl_ext = rd32(E1000_CTRL_EXT);
753 wr32(E1000_CTRL_EXT,
754 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
755}
756
9d5c8243
AK		 757/**
758 * igb_configure - configure the hardware for RX and TX
759 * @adapter: private board structure
760 **/
761static void igb_configure(struct igb_adapter *adapter)
762{
763 struct net_device *netdev = adapter->netdev;
764 int i;
765
766 igb_get_hw_control(adapter);
767 igb_set_multi(netdev);
768
769 igb_restore_vlan(adapter);
9d5c8243
AK		 770
771 igb_configure_tx(adapter);
772 igb_setup_rctl(adapter);
773 igb_configure_rx(adapter);
662d7205
AD		 774
775 igb_rx_fifo_flush_82575(&adapter->hw);
776
9d5c8243
AK		 777 /* call IGB_DESC_UNUSED which always leaves
778 * at least 1 descriptor unused to make sure
779 * next_to_use != next_to_clean */
780 for (i = 0; i < adapter->num_rx_queues; i++) {
781 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 782 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 783 }
784
785
786 adapter->tx_queue_len = netdev->tx_queue_len;
787}
788
789
790/**
791 * igb_up - Open the interface and prepare it to handle traffic
792 * @adapter: board private structure
793 **/
794
795int igb_up(struct igb_adapter *adapter)
796{
797 struct e1000_hw *hw = &adapter->hw;
798 int i;
799
800 /* hardware has been reset, we need to reload some things */
801 igb_configure(adapter);
802
803 clear_bit(__IGB_DOWN, &adapter->state);
804
844290e5
PW		 805 for (i = 0; i < adapter->num_rx_queues; i++)
806 napi_enable(&adapter->rx_ring[i].napi);
807 if (adapter->msix_entries)
9d5c8243 808 igb_configure_msix(adapter);
9d5c8243
AK		 809
810 /* Clear any pending interrupts. */
811 rd32(E1000_ICR);
812 igb_irq_enable(adapter);
813
814 /* Fire a link change interrupt to start the watchdog. */
815 wr32(E1000_ICS, E1000_ICS_LSC);
816 return 0;
817}
818
819void igb_down(struct igb_adapter *adapter)
820{
821 struct e1000_hw *hw = &adapter->hw;
822 struct net_device *netdev = adapter->netdev;
823 u32 tctl, rctl;
824 int i;
825
826 /* signal that we're down so the interrupt handler does not
827 * reschedule our watchdog timer */
828 set_bit(__IGB_DOWN, &adapter->state);
829
830 /* disable receives in the hardware */
831 rctl = rd32(E1000_RCTL);
832 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
833 /* flush and sleep below */
834
fd2ea0a7 835 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 836
837 /* disable transmits in the hardware */
838 tctl = rd32(E1000_TCTL);
839 tctl &= ~E1000_TCTL_EN;
840 wr32(E1000_TCTL, tctl);
841 /* flush both disables and wait for them to finish */
842 wrfl();
843 msleep(10);
844
844290e5
PW		 845 for (i = 0; i < adapter->num_rx_queues; i++)
846 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 847
9d5c8243
AK		 848 igb_irq_disable(adapter);
849
850 del_timer_sync(&adapter->watchdog_timer);
851 del_timer_sync(&adapter->phy_info_timer);
852
853 netdev->tx_queue_len = adapter->tx_queue_len;
854 netif_carrier_off(netdev);
855 adapter->link_speed = 0;
856 adapter->link_duplex = 0;
857
3023682e
JK		 858 if (!pci_channel_offline(adapter->pdev))
859 igb_reset(adapter);
9d5c8243
AK		 860 igb_clean_all_tx_rings(adapter);
861 igb_clean_all_rx_rings(adapter);
862}
863
864void igb_reinit_locked(struct igb_adapter *adapter)
865{
866 WARN_ON(in_interrupt());
867 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
868 msleep(1);
869 igb_down(adapter);
870 igb_up(adapter);
871 clear_bit(__IGB_RESETTING, &adapter->state);
872}
873
874void igb_reset(struct igb_adapter *adapter)
875{
876 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 877 struct e1000_mac_info *mac = &hw->mac;
878 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 879 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
880 u16 hwm;
881
882 /* Repartition Pba for greater than 9k mtu
883 * To take effect CTRL.RST is required.
884 */
2d064c06 885 if (mac->type != e1000_82576) {
9d5c8243 886 pba = E1000_PBA_34K;
2d064c06
AD		 887 }
888 else {
889 pba = E1000_PBA_64K;
890 }
9d5c8243 891
2d064c06
AD		 892 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
893 (mac->type < e1000_82576)) {
9d5c8243
AK		 894 /* adjust PBA for jumbo frames */
895 wr32(E1000_PBA, pba);
896
897 /* To maintain wire speed transmits, the Tx FIFO should be
898 * large enough to accommodate two full transmit packets,
899 * rounded up to the next 1KB and expressed in KB. Likewise,
900 * the Rx FIFO should be large enough to accommodate at least
901 * one full receive packet and is similarly rounded up and
902 * expressed in KB. */
903 pba = rd32(E1000_PBA);
904 /* upper 16 bits has Tx packet buffer allocation size in KB */
905 tx_space = pba >> 16;
906 /* lower 16 bits has Rx packet buffer allocation size in KB */
907 pba &= 0xffff;
908 /* the tx fifo also stores 16 bytes of information about the tx
909 * but don't include ethernet FCS because hardware appends it */
910 min_tx_space = (adapter->max_frame_size +
911 sizeof(struct e1000_tx_desc) -
912 ETH_FCS_LEN) * 2;
913 min_tx_space = ALIGN(min_tx_space, 1024);
914 min_tx_space >>= 10;
915 /* software strips receive CRC, so leave room for it */
916 min_rx_space = adapter->max_frame_size;
917 min_rx_space = ALIGN(min_rx_space, 1024);
918 min_rx_space >>= 10;
919
920 /* If current Tx allocation is less than the min Tx FIFO size,
921 * and the min Tx FIFO size is less than the current Rx FIFO
922 * allocation, take space away from current Rx allocation */
923 if (tx_space < min_tx_space &&
924 ((min_tx_space - tx_space) < pba)) {
925 pba = pba - (min_tx_space - tx_space);
926
927 /* if short on rx space, rx wins and must trump tx
928 * adjustment */
929 if (pba < min_rx_space)
930 pba = min_rx_space;
931 }
2d064c06 932 wr32(E1000_PBA, pba);
9d5c8243 933 }
9d5c8243
AK		 934
935 /* flow control settings */
936 /* The high water mark must be low enough to fit one full frame
937 * (or the size used for early receive) above it in the Rx FIFO.
938 * Set it to the lower of:
939 * - 90% of the Rx FIFO size, or
940 * - the full Rx FIFO size minus one full frame */
941 hwm = min(((pba << 10) * 9 / 10),
2d064c06 942 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 943
2d064c06
AD		 944 if (mac->type < e1000_82576) {
945 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
946 fc->low_water = fc->high_water - 8;
947 } else {
948 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
949 fc->low_water = fc->high_water - 16;
950 }
9d5c8243
AK		 951 fc->pause_time = 0xFFFF;
952 fc->send_xon = 1;
953 fc->type = fc->original_type;
954
955 /* Allow time for pending master requests to run */
956 adapter->hw.mac.ops.reset_hw(&adapter->hw);
957 wr32(E1000_WUC, 0);
958
959 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
960 dev_err(&adapter->pdev->dev, "Hardware Error\n");
961
962 igb_update_mng_vlan(adapter);
963
964 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
965 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
966
967 igb_reset_adaptive(&adapter->hw);
f5f4cf08 968 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 969}
970
42bfd33a
TI		 971/**
972 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
973 * @pdev: PCI device information struct
974 *
975 * Returns true if an adapter needs ioport resources
976 **/
977static int igb_is_need_ioport(struct pci_dev *pdev)
978{
979 switch (pdev->device) {
980 /* Currently there are no adapters that need ioport resources */
981 default:
982 return false;
983 }
984}
985
2e5c6922
SH		 986static const struct net_device_ops igb_netdev_ops = {
987 .ndo_open = igb_open,
988 .ndo_stop = igb_close,
00829823 989 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 990 .ndo_get_stats = igb_get_stats,
991 .ndo_set_multicast_list = igb_set_multi,
992 .ndo_set_mac_address = igb_set_mac,
993 .ndo_change_mtu = igb_change_mtu,
994 .ndo_do_ioctl = igb_ioctl,
995 .ndo_tx_timeout = igb_tx_timeout,
996 .ndo_validate_addr = eth_validate_addr,
997 .ndo_vlan_rx_register = igb_vlan_rx_register,
998 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
999 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1000#ifdef CONFIG_NET_POLL_CONTROLLER
1001 .ndo_poll_controller = igb_netpoll,
1002#endif
1003};
1004
9d5c8243
AK		 1005/**
1006 * igb_probe - Device Initialization Routine
1007 * @pdev: PCI device information struct
1008 * @ent: entry in igb_pci_tbl
1009 *
1010 * Returns 0 on success, negative on failure
1011 *
1012 * igb_probe initializes an adapter identified by a pci_dev structure.
1013 * The OS initialization, configuring of the adapter private structure,
1014 * and a hardware reset occur.
1015 **/
1016static int __devinit igb_probe(struct pci_dev *pdev,
1017 const struct pci_device_id *ent)
1018{
1019 struct net_device *netdev;
1020 struct igb_adapter *adapter;
1021 struct e1000_hw *hw;
c54106bb 1022 struct pci_dev *us_dev;
9d5c8243
AK		 1023 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1024 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1025 int i, err, pci_using_dac, pos;
1026 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1027 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1028 u32 part_num;
42bfd33a 1029 int bars, need_ioport;
9d5c8243 1030
42bfd33a
TI		 1031 /* do not allocate ioport bars when not needed */
1032 need_ioport = igb_is_need_ioport(pdev);
1033 if (need_ioport) {
1034 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1035 err = pci_enable_device(pdev);
1036 } else {
1037 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1038 err = pci_enable_device_mem(pdev);
1039 }
9d5c8243
AK		 1040 if (err)
1041 return err;
1042
1043 pci_using_dac = 0;
1044 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1045 if (!err) {
1046 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1047 if (!err)
1048 pci_using_dac = 1;
1049 } else {
1050 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1051 if (err) {
1052 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1053 if (err) {
1054 dev_err(&pdev->dev, "No usable DMA "
1055 "configuration, aborting\n");
1056 goto err_dma;
1057 }
1058 }
1059 }
1060
c54106bb
AD		 1061 /* 82575 requires that the pci-e link partner disable the L0s state */
1062 switch (pdev->device) {
1063 case E1000_DEV_ID_82575EB_COPPER:
1064 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1065 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1066 us_dev = pdev->bus->self;
1067 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1068 if (pos) {
1069 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1070 &state);
1071 state &= ~PCIE_LINK_STATE_L0S;
1072 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1073 state);
ac450208
BH		 1074 dev_info(&pdev->dev,
1075 "Disabling ASPM L0s upstream switch port %s\n",
1076 pci_name(us_dev));
c54106bb
AD		 1077 }
1078 default:
1079 break;
1080 }
1081
42bfd33a 1082 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1083 if (err)
1084 goto err_pci_reg;
1085
ea943d41
JK		 1086 err = pci_enable_pcie_error_reporting(pdev);
1087 if (err) {
1088 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1089 "0x%x\n", err);
1090 /* non-fatal, continue */
1091 }
40a914fa 1092
9d5c8243 1093 pci_set_master(pdev);
c682fc23 1094 pci_save_state(pdev);
9d5c8243
AK		 1095
1096 err = -ENOMEM;
661086df 1097 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1098 if (!netdev)
1099 goto err_alloc_etherdev;
1100
1101 SET_NETDEV_DEV(netdev, &pdev->dev);
1102
1103 pci_set_drvdata(pdev, netdev);
1104 adapter = netdev_priv(netdev);
1105 adapter->netdev = netdev;
1106 adapter->pdev = pdev;
1107 hw = &adapter->hw;
1108 hw->back = adapter;
1109 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1110 adapter->bars = bars;
1111 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1112
1113 mmio_start = pci_resource_start(pdev, 0);
1114 mmio_len = pci_resource_len(pdev, 0);
1115
1116 err = -EIO;
1117 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1118 if (!adapter->hw.hw_addr)
1119 goto err_ioremap;
1120
2e5c6922 1121 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1122 igb_set_ethtool_ops(netdev);
9d5c8243 1123 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1124
1125 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1126
1127 netdev->mem_start = mmio_start;
1128 netdev->mem_end = mmio_start + mmio_len;
1129
9d5c8243
AK		 1130 /* PCI config space info */
1131 hw->vendor_id = pdev->vendor;
1132 hw->device_id = pdev->device;
1133 hw->revision_id = pdev->revision;
1134 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1135 hw->subsystem_device_id = pdev->subsystem_device;
1136
1137 /* setup the private structure */
1138 hw->back = adapter;
1139 /* Copy the default MAC, PHY and NVM function pointers */
1140 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1141 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1142 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1143 /* Initialize skew-specific constants */
1144 err = ei->get_invariants(hw);
1145 if (err)
1146 goto err_hw_init;
1147
1148 err = igb_sw_init(adapter);
1149 if (err)
1150 goto err_sw_init;
1151
1152 igb_get_bus_info_pcie(hw);
1153
7dfc16fa
AD		 1154 /* set flags */
1155 switch (hw->mac.type) {
1156 case e1000_82576:
1157 case e1000_82575:
1158 adapter->flags |= IGB_FLAG_HAS_DCA;
1159 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1160 break;
1161 default:
1162 break;
1163 }
1164
9d5c8243
AK		 1165 hw->phy.autoneg_wait_to_complete = false;
1166 hw->mac.adaptive_ifs = true;
1167
1168 /* Copper options */
1169 if (hw->phy.media_type == e1000_media_type_copper) {
1170 hw->phy.mdix = AUTO_ALL_MODES;
1171 hw->phy.disable_polarity_correction = false;
1172 hw->phy.ms_type = e1000_ms_hw_default;
1173 }
1174
1175 if (igb_check_reset_block(hw))
1176 dev_info(&pdev->dev,
1177 "PHY reset is blocked due to SOL/IDER session.\n");
1178
1179 netdev->features = NETIF_F_SG |
1180 NETIF_F_HW_CSUM |
1181 NETIF_F_HW_VLAN_TX |
1182 NETIF_F_HW_VLAN_RX |
1183 NETIF_F_HW_VLAN_FILTER;
1184
1185 netdev->features |= NETIF_F_TSO;
9d5c8243 1186 netdev->features |= NETIF_F_TSO6;
48f29ffc 1187
d3352520 1188#ifdef CONFIG_IGB_LRO
5c0999b7 1189 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1190#endif
1191
48f29ffc
JK		 1192 netdev->vlan_features |= NETIF_F_TSO;
1193 netdev->vlan_features |= NETIF_F_TSO6;
1194 netdev->vlan_features |= NETIF_F_HW_CSUM;
1195 netdev->vlan_features |= NETIF_F_SG;
1196
9d5c8243
AK		 1197 if (pci_using_dac)
1198 netdev->features |= NETIF_F_HIGHDMA;
1199
9d5c8243
AK		 1200 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1201
1202 /* before reading the NVM, reset the controller to put the device in a
1203 * known good starting state */
1204 hw->mac.ops.reset_hw(hw);
1205
1206 /* make sure the NVM is good */
1207 if (igb_validate_nvm_checksum(hw) < 0) {
1208 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1209 err = -EIO;
1210 goto err_eeprom;
1211 }
1212
1213 /* copy the MAC address out of the NVM */
1214 if (hw->mac.ops.read_mac_addr(hw))
1215 dev_err(&pdev->dev, "NVM Read Error\n");
1216
1217 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1218 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1219
1220 if (!is_valid_ether_addr(netdev->perm_addr)) {
1221 dev_err(&pdev->dev, "Invalid MAC Address\n");
1222 err = -EIO;
1223 goto err_eeprom;
1224 }
1225
1226 init_timer(&adapter->watchdog_timer);
1227 adapter->watchdog_timer.function = &igb_watchdog;
1228 adapter->watchdog_timer.data = (unsigned long) adapter;
1229
1230 init_timer(&adapter->phy_info_timer);
1231 adapter->phy_info_timer.function = &igb_update_phy_info;
1232 adapter->phy_info_timer.data = (unsigned long) adapter;
1233
1234 INIT_WORK(&adapter->reset_task, igb_reset_task);
1235 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1236
1237 /* Initialize link & ring properties that are user-changeable */
1238 adapter->tx_ring->count = 256;
1239 for (i = 0; i < adapter->num_tx_queues; i++)
1240 adapter->tx_ring[i].count = adapter->tx_ring->count;
1241 adapter->rx_ring->count = 256;
1242 for (i = 0; i < adapter->num_rx_queues; i++)
1243 adapter->rx_ring[i].count = adapter->rx_ring->count;
1244
1245 adapter->fc_autoneg = true;
1246 hw->mac.autoneg = true;
1247 hw->phy.autoneg_advertised = 0x2f;
1248
1249 hw->fc.original_type = e1000_fc_default;
1250 hw->fc.type = e1000_fc_default;
1251
1252 adapter->itr_setting = 3;
1253 adapter->itr = IGB_START_ITR;
1254
1255 igb_validate_mdi_setting(hw);
1256
1257 adapter->rx_csum = 1;
1258
1259 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1260 * enable the ACPI Magic Packet filter
1261 */
1262
1263 if (hw->bus.func == 0 ||
1264 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1265 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1266 &eeprom_data);
1267
1268 if (eeprom_data & eeprom_apme_mask)
1269 adapter->eeprom_wol |= E1000_WUFC_MAG;
1270
1271 /* now that we have the eeprom settings, apply the special cases where
1272 * the eeprom may be wrong or the board simply won't support wake on
1273 * lan on a particular port */
1274 switch (pdev->device) {
1275 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1276 adapter->eeprom_wol = 0;
1277 break;
1278 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1279 case E1000_DEV_ID_82576_FIBER:
1280 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1281 /* Wake events only supported on port A for dual fiber
1282 * regardless of eeprom setting */
1283 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1284 adapter->eeprom_wol = 0;
1285 break;
1286 }
1287
1288 /* initialize the wol settings based on the eeprom settings */
1289 adapter->wol = adapter->eeprom_wol;
e1b86d84 1290 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1291
1292 /* reset the hardware with the new settings */
1293 igb_reset(adapter);
1294
1295 /* let the f/w know that the h/w is now under the control of the
1296 * driver. */
1297 igb_get_hw_control(adapter);
1298
1299 /* tell the stack to leave us alone until igb_open() is called */
1300 netif_carrier_off(netdev);
fd2ea0a7 1301 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1302
1303 strcpy(netdev->name, "eth%d");
1304 err = register_netdev(netdev);
1305 if (err)
1306 goto err_register;
1307
421e02f0 1308#ifdef CONFIG_IGB_DCA
7dfc16fa
AD		 1309 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1310 (dca_add_requester(&pdev->dev) == 0)) {
1311 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1312 dev_info(&pdev->dev, "DCA enabled\n");
1313 /* Always use CB2 mode, difference is masked
1314 * in the CB driver. */
1315 wr32(E1000_DCA_CTRL, 2);
1316 igb_setup_dca(adapter);
1317 }
1318#endif
1319
9d5c8243
AK		 1320 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1321 /* print bus type/speed/width info */
7c510e4b 1322 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1323 netdev->name,
1324 ((hw->bus.speed == e1000_bus_speed_2500)
1325 ? "2.5Gb/s" : "unknown"),
1326 ((hw->bus.width == e1000_bus_width_pcie_x4)
1327 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1328 ? "Width x1" : "unknown"),
7c510e4b 1329 netdev->dev_addr);
9d5c8243
AK		 1330
1331 igb_read_part_num(hw, &part_num);
1332 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1333 (part_num >> 8), (part_num & 0xff));
1334
1335 dev_info(&pdev->dev,
1336 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1337 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1338 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1339 adapter->num_rx_queues, adapter->num_tx_queues);
1340
9d5c8243
AK		 1341 return 0;
1342
1343err_register:
1344 igb_release_hw_control(adapter);
1345err_eeprom:
1346 if (!igb_check_reset_block(hw))
f5f4cf08 1347 igb_reset_phy(hw);
9d5c8243
AK		 1348
1349 if (hw->flash_address)
1350 iounmap(hw->flash_address);
1351
1352 igb_remove_device(hw);
a88f10ec 1353 igb_free_queues(adapter);
9d5c8243
AK		 1354err_sw_init:
1355err_hw_init:
1356 iounmap(hw->hw_addr);
1357err_ioremap:
1358 free_netdev(netdev);
1359err_alloc_etherdev:
42bfd33a 1360 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1361err_pci_reg:
1362err_dma:
1363 pci_disable_device(pdev);
1364 return err;
1365}
1366
1367/**
1368 * igb_remove - Device Removal Routine
1369 * @pdev: PCI device information struct
1370 *
1371 * igb_remove is called by the PCI subsystem to alert the driver
1372 * that it should release a PCI device. The could be caused by a
1373 * Hot-Plug event, or because the driver is going to be removed from
1374 * memory.
1375 **/
1376static void __devexit igb_remove(struct pci_dev *pdev)
1377{
1378 struct net_device *netdev = pci_get_drvdata(pdev);
1379 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1380#ifdef CONFIG_IGB_DCA
fe4506b6 1381 struct e1000_hw *hw = &adapter->hw;
9280fa52 1382#endif
ea943d41 1383 int err;
9d5c8243
AK		 1384
1385 /* flush_scheduled work may reschedule our watchdog task, so
1386 * explicitly disable watchdog tasks from being rescheduled */
1387 set_bit(__IGB_DOWN, &adapter->state);
1388 del_timer_sync(&adapter->watchdog_timer);
1389 del_timer_sync(&adapter->phy_info_timer);
1390
1391 flush_scheduled_work();
1392
421e02f0 1393#ifdef CONFIG_IGB_DCA
7dfc16fa 1394 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1395 dev_info(&pdev->dev, "DCA disabled\n");
1396 dca_remove_requester(&pdev->dev);
7dfc16fa 1397 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1398 wr32(E1000_DCA_CTRL, 1);
1399 }
1400#endif
1401
9d5c8243
AK		 1402 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1403 * would have already happened in close and is redundant. */
1404 igb_release_hw_control(adapter);
1405
1406 unregister_netdev(netdev);
1407
f5f4cf08
AD		 1408 if (!igb_check_reset_block(&adapter->hw))
1409 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1410
1411 igb_remove_device(&adapter->hw);
1412 igb_reset_interrupt_capability(adapter);
1413
a88f10ec 1414 igb_free_queues(adapter);
9d5c8243
AK		 1415
1416 iounmap(adapter->hw.hw_addr);
1417 if (adapter->hw.flash_address)
1418 iounmap(adapter->hw.flash_address);
42bfd33a 1419 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1420
1421 free_netdev(netdev);
1422
ea943d41
JK		 1423 err = pci_disable_pcie_error_reporting(pdev);
1424 if (err)
1425 dev_err(&pdev->dev,
1426 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1427
9d5c8243
AK		 1428 pci_disable_device(pdev);
1429}
1430
1431/**
1432 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1433 * @adapter: board private structure to initialize
1434 *
1435 * igb_sw_init initializes the Adapter private data structure.
1436 * Fields are initialized based on PCI device information and
1437 * OS network device settings (MTU size).
1438 **/
1439static int __devinit igb_sw_init(struct igb_adapter *adapter)
1440{
1441 struct e1000_hw *hw = &adapter->hw;
1442 struct net_device *netdev = adapter->netdev;
1443 struct pci_dev *pdev = adapter->pdev;
1444
1445 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1446
68fd9910
AD		 1447 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1448 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1449 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1450 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1451 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1452 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1453
1454 /* Number of supported queues. */
1455 /* Having more queues than CPUs doesn't make sense. */
e42e4ba0
LT		 1456 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
1457 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1458
661086df
PWJ		 1459 /* This call may decrease the number of queues depending on
1460 * interrupt mode. */
9d5c8243
AK		 1461 igb_set_interrupt_capability(adapter);
1462
1463 if (igb_alloc_queues(adapter)) {
1464 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1465 return -ENOMEM;
1466 }
1467
1468 /* Explicitly disable IRQ since the NIC can be in any state. */
1469 igb_irq_disable(adapter);
1470
1471 set_bit(__IGB_DOWN, &adapter->state);
1472 return 0;
1473}
1474
1475/**
1476 * igb_open - Called when a network interface is made active
1477 * @netdev: network interface device structure
1478 *
1479 * Returns 0 on success, negative value on failure
1480 *
1481 * The open entry point is called when a network interface is made
1482 * active by the system (IFF_UP). At this point all resources needed
1483 * for transmit and receive operations are allocated, the interrupt
1484 * handler is registered with the OS, the watchdog timer is started,
1485 * and the stack is notified that the interface is ready.
1486 **/
1487static int igb_open(struct net_device *netdev)
1488{
1489 struct igb_adapter *adapter = netdev_priv(netdev);
1490 struct e1000_hw *hw = &adapter->hw;
1491 int err;
1492 int i;
1493
1494 /* disallow open during test */
1495 if (test_bit(__IGB_TESTING, &adapter->state))
1496 return -EBUSY;
1497
1498 /* allocate transmit descriptors */
1499 err = igb_setup_all_tx_resources(adapter);
1500 if (err)
1501 goto err_setup_tx;
1502
1503 /* allocate receive descriptors */
1504 err = igb_setup_all_rx_resources(adapter);
1505 if (err)
1506 goto err_setup_rx;
1507
1508 /* e1000_power_up_phy(adapter); */
1509
1510 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1511 if ((adapter->hw.mng_cookie.status &
1512 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1513 igb_update_mng_vlan(adapter);
1514
1515 /* before we allocate an interrupt, we must be ready to handle it.
1516 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1517 * as soon as we call pci_request_irq, so we have to setup our
1518 * clean_rx handler before we do so. */
1519 igb_configure(adapter);
1520
1521 err = igb_request_irq(adapter);
1522 if (err)
1523 goto err_req_irq;
1524
1525 /* From here on the code is the same as igb_up() */
1526 clear_bit(__IGB_DOWN, &adapter->state);
1527
844290e5
PW		 1528 for (i = 0; i < adapter->num_rx_queues; i++)
1529 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1530
1531 /* Clear any pending interrupts. */
1532 rd32(E1000_ICR);
844290e5
PW		 1533
1534 igb_irq_enable(adapter);
1535
d55b53ff
JK		 1536 netif_tx_start_all_queues(netdev);
1537
9d5c8243
AK		 1538 /* Fire a link status change interrupt to start the watchdog. */
1539 wr32(E1000_ICS, E1000_ICS_LSC);
1540
1541 return 0;
1542
1543err_req_irq:
1544 igb_release_hw_control(adapter);
1545 /* e1000_power_down_phy(adapter); */
1546 igb_free_all_rx_resources(adapter);
1547err_setup_rx:
1548 igb_free_all_tx_resources(adapter);
1549err_setup_tx:
1550 igb_reset(adapter);
1551
1552 return err;
1553}
1554
1555/**
1556 * igb_close - Disables a network interface
1557 * @netdev: network interface device structure
1558 *
1559 * Returns 0, this is not allowed to fail
1560 *
1561 * The close entry point is called when an interface is de-activated
1562 * by the OS. The hardware is still under the driver's control, but
1563 * needs to be disabled. A global MAC reset is issued to stop the
1564 * hardware, and all transmit and receive resources are freed.
1565 **/
1566static int igb_close(struct net_device *netdev)
1567{
1568 struct igb_adapter *adapter = netdev_priv(netdev);
1569
1570 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1571 igb_down(adapter);
1572
1573 igb_free_irq(adapter);
1574
1575 igb_free_all_tx_resources(adapter);
1576 igb_free_all_rx_resources(adapter);
1577
1578 /* kill manageability vlan ID if supported, but not if a vlan with
1579 * the same ID is registered on the host OS (let 8021q kill it) */
1580 if ((adapter->hw.mng_cookie.status &
1581 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1582 !(adapter->vlgrp &&
1583 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1584 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1585
1586 return 0;
1587}
1588
1589/**
1590 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1591 * @adapter: board private structure
1592 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1593 *
1594 * Return 0 on success, negative on failure
1595 **/
1596
1597int igb_setup_tx_resources(struct igb_adapter *adapter,
1598 struct igb_ring *tx_ring)
1599{
1600 struct pci_dev *pdev = adapter->pdev;
1601 int size;
1602
1603 size = sizeof(struct igb_buffer) * tx_ring->count;
1604 tx_ring->buffer_info = vmalloc(size);
1605 if (!tx_ring->buffer_info)
1606 goto err;
1607 memset(tx_ring->buffer_info, 0, size);
1608
1609 /* round up to nearest 4K */
0e014cb1 1610 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1611 tx_ring->size = ALIGN(tx_ring->size, 4096);
1612
1613 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1614 &tx_ring->dma);
1615
1616 if (!tx_ring->desc)
1617 goto err;
1618
1619 tx_ring->adapter = adapter;
1620 tx_ring->next_to_use = 0;
1621 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1622 return 0;
1623
1624err:
1625 vfree(tx_ring->buffer_info);
1626 dev_err(&adapter->pdev->dev,
1627 "Unable to allocate memory for the transmit descriptor ring\n");
1628 return -ENOMEM;
1629}
1630
1631/**
1632 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1633 * (Descriptors) for all queues
1634 * @adapter: board private structure
1635 *
1636 * Return 0 on success, negative on failure
1637 **/
1638static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1639{
1640 int i, err = 0;
661086df 1641 int r_idx;
9d5c8243
AK		 1642
1643 for (i = 0; i < adapter->num_tx_queues; i++) {
1644 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1645 if (err) {
1646 dev_err(&adapter->pdev->dev,
1647 "Allocation for Tx Queue %u failed\n", i);
1648 for (i--; i >= 0; i--)
3b644cf6 1649 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1650 break;
1651 }
1652 }
1653
661086df
PWJ		 1654 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1655 r_idx = i % adapter->num_tx_queues;
1656 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1657 }
9d5c8243
AK		 1658 return err;
1659}
1660
1661/**
1662 * igb_configure_tx - Configure transmit Unit after Reset
1663 * @adapter: board private structure
1664 *
1665 * Configure the Tx unit of the MAC after a reset.
1666 **/
1667static void igb_configure_tx(struct igb_adapter *adapter)
1668{
0e014cb1 1669 u64 tdba;
9d5c8243
AK		 1670 struct e1000_hw *hw = &adapter->hw;
1671 u32 tctl;
1672 u32 txdctl, txctrl;
26bc19ec 1673 int i, j;
9d5c8243
AK		 1674
1675 for (i = 0; i < adapter->num_tx_queues; i++) {
1676 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1677 j = ring->reg_idx;
1678 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1679 ring->count * sizeof(struct e1000_tx_desc));
1680 tdba = ring->dma;
26bc19ec 1681 wr32(E1000_TDBAL(j),
9d5c8243 1682 tdba & 0x00000000ffffffffULL);
26bc19ec 1683 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1684
26bc19ec
AD		 1685 ring->head = E1000_TDH(j);
1686 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1687 writel(0, hw->hw_addr + ring->tail);
1688 writel(0, hw->hw_addr + ring->head);
26bc19ec 1689 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1690 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1691 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1692
1693 /* Turn off Relaxed Ordering on head write-backs. The
1694 * writebacks MUST be delivered in order or it will
1695 * completely screw up our bookeeping.
1696 */
26bc19ec 1697 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1698 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1699 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1700 }
1701
1702
1703
1704 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1705
1706 /* Program the Transmit Control Register */
1707
1708 tctl = rd32(E1000_TCTL);
1709 tctl &= ~E1000_TCTL_CT;
1710 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1711 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1712
1713 igb_config_collision_dist(hw);
1714
1715 /* Setup Transmit Descriptor Settings for eop descriptor */
1716 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1717
1718 /* Enable transmits */
1719 tctl |= E1000_TCTL_EN;
1720
1721 wr32(E1000_TCTL, tctl);
1722}
1723
1724/**
1725 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1726 * @adapter: board private structure
1727 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1728 *
1729 * Returns 0 on success, negative on failure
1730 **/
1731
1732int igb_setup_rx_resources(struct igb_adapter *adapter,
1733 struct igb_ring *rx_ring)
1734{
1735 struct pci_dev *pdev = adapter->pdev;
1736 int size, desc_len;
1737
1738 size = sizeof(struct igb_buffer) * rx_ring->count;
1739 rx_ring->buffer_info = vmalloc(size);
1740 if (!rx_ring->buffer_info)
1741 goto err;
1742 memset(rx_ring->buffer_info, 0, size);
1743
1744 desc_len = sizeof(union e1000_adv_rx_desc);
1745
1746 /* Round up to nearest 4K */
1747 rx_ring->size = rx_ring->count * desc_len;
1748 rx_ring->size = ALIGN(rx_ring->size, 4096);
1749
1750 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1751 &rx_ring->dma);
1752
1753 if (!rx_ring->desc)
1754 goto err;
1755
1756 rx_ring->next_to_clean = 0;
1757 rx_ring->next_to_use = 0;
9d5c8243
AK		 1758
1759 rx_ring->adapter = adapter;
9d5c8243
AK		 1760
1761 return 0;
1762
1763err:
1764 vfree(rx_ring->buffer_info);
1765 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1766 "the receive descriptor ring\n");
1767 return -ENOMEM;
1768}
1769
1770/**
1771 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1772 * (Descriptors) for all queues
1773 * @adapter: board private structure
1774 *
1775 * Return 0 on success, negative on failure
1776 **/
1777static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1778{
1779 int i, err = 0;
1780
1781 for (i = 0; i < adapter->num_rx_queues; i++) {
1782 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1783 if (err) {
1784 dev_err(&adapter->pdev->dev,
1785 "Allocation for Rx Queue %u failed\n", i);
1786 for (i--; i >= 0; i--)
3b644cf6 1787 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1788 break;
1789 }
1790 }
1791
1792 return err;
1793}
1794
1795/**
1796 * igb_setup_rctl - configure the receive control registers
1797 * @adapter: Board private structure
1798 **/
1799static void igb_setup_rctl(struct igb_adapter *adapter)
1800{
1801 struct e1000_hw *hw = &adapter->hw;
1802 u32 rctl;
1803 u32 srrctl = 0;
26bc19ec 1804 int i, j;
9d5c8243
AK		 1805
1806 rctl = rd32(E1000_RCTL);
1807
1808 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1809 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1810
69d728ba 1811 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1812 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1813
87cb7e8c
AK		 1814 /*
1815 * enable stripping of CRC. It's unlikely this will break BMC
1816 * redirection as it did with e1000. Newer features require
1817 * that the HW strips the CRC.
9d5c8243 1818 */
87cb7e8c 1819 rctl |= E1000_RCTL_SECRC;
9d5c8243 1820
9b07f3d3
AD		 1821 /*
1822 * disable store bad packets, long packet enable, and clear size bits.
1823 */
1824 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_LPE | E1000_RCTL_SZ_256);
9d5c8243 1825
b4557be2 1826 if (adapter->netdev->mtu > ETH_DATA_LEN)
9b07f3d3 1827 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1828
1829 /* Setup buffer sizes */
1830 switch (adapter->rx_buffer_len) {
1831 case IGB_RXBUFFER_256:
1832 rctl |= E1000_RCTL_SZ_256;
1833 break;
1834 case IGB_RXBUFFER_512:
1835 rctl |= E1000_RCTL_SZ_512;
1836 break;
1837 default:
1838 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1839 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1840 break;
9d5c8243
AK		 1841 }
1842
1843 /* 82575 and greater support packet-split where the protocol
1844 * header is placed in skb->data and the packet data is
1845 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1846 * In the case of a non-split, skb->data is linearly filled,
1847 * followed by the page buffers. Therefore, skb->data is
1848 * sized to hold the largest protocol header.
1849 */
1850 /* allocations using alloc_page take too long for regular MTU
1851 * so only enable packet split for jumbo frames */
1852 if (rctl & E1000_RCTL_LPE) {
1853 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1854 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1855 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1856 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1857 } else {
1858 adapter->rx_ps_hdr_size = 0;
1859 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1860 }
1861
26bc19ec
AD		 1862 for (i = 0; i < adapter->num_rx_queues; i++) {
1863 j = adapter->rx_ring[i].reg_idx;
1864 wr32(E1000_SRRCTL(j), srrctl);
1865 }
9d5c8243
AK		 1866
1867 wr32(E1000_RCTL, rctl);
1868}
1869
1870/**
1871 * igb_configure_rx - Configure receive Unit after Reset
1872 * @adapter: board private structure
1873 *
1874 * Configure the Rx unit of the MAC after a reset.
1875 **/
1876static void igb_configure_rx(struct igb_adapter *adapter)
1877{
1878 u64 rdba;
1879 struct e1000_hw *hw = &adapter->hw;
1880 u32 rctl, rxcsum;
1881 u32 rxdctl;
26bc19ec 1882 int i, j;
9d5c8243
AK		 1883
1884 /* disable receives while setting up the descriptors */
1885 rctl = rd32(E1000_RCTL);
1886 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1887 wrfl();
1888 mdelay(10);
1889
1890 if (adapter->itr_setting > 3)
6eb5a7f1 1891 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1892
1893 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1894 * the Base and Length of the Rx Descriptor Ring */
1895 for (i = 0; i < adapter->num_rx_queues; i++) {
1896 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1897 j = ring->reg_idx;
9d5c8243 1898 rdba = ring->dma;
26bc19ec 1899 wr32(E1000_RDBAL(j),
9d5c8243 1900 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1901 wr32(E1000_RDBAH(j), rdba >> 32);
1902 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1903 ring->count * sizeof(union e1000_adv_rx_desc));
1904
26bc19ec
AD		 1905 ring->head = E1000_RDH(j);
1906 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1907 writel(0, hw->hw_addr + ring->tail);
1908 writel(0, hw->hw_addr + ring->head);
1909
26bc19ec 1910 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1911 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1912 rxdctl &= 0xFFF00000;
1913 rxdctl |= IGB_RX_PTHRESH;
1914 rxdctl |= IGB_RX_HTHRESH << 8;
1915 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1916 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1917 }
1918
1919 if (adapter->num_rx_queues > 1) {
1920 u32 random[10];
1921 u32 mrqc;
1922 u32 j, shift;
1923 union e1000_reta {
1924 u32 dword;
1925 u8 bytes[4];
1926 } reta;
1927
1928 get_random_bytes(&random[0], 40);
1929
2d064c06
AD		 1930 if (hw->mac.type >= e1000_82576)
1931 shift = 0;
1932 else
1933 shift = 6;
9d5c8243
AK		 1934 for (j = 0; j < (32 * 4); j++) {
1935 reta.bytes[j & 3] =
26bc19ec 1936 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1937 if ((j & 3) == 3)
1938 writel(reta.dword,
1939 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1940 }
1941 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1942
1943 /* Fill out hash function seeds */
1944 for (j = 0; j < 10; j++)
1945 array_wr32(E1000_RSSRK(0), j, random[j]);
1946
1947 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1948 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1949 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1950 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1951 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1952 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1953 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1954 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1955
1956
1957 wr32(E1000_MRQC, mrqc);
1958
1959 /* Multiqueue and raw packet checksumming are mutually
1960 * exclusive. Note that this not the same as TCP/IP
1961 * checksumming, which works fine. */
1962 rxcsum = rd32(E1000_RXCSUM);
1963 rxcsum |= E1000_RXCSUM_PCSD;
1964 wr32(E1000_RXCSUM, rxcsum);
1965 } else {
1966 /* Enable Receive Checksum Offload for TCP and UDP */
1967 rxcsum = rd32(E1000_RXCSUM);
1968 if (adapter->rx_csum) {
1969 rxcsum |= E1000_RXCSUM_TUOFL;
1970
1971 /* Enable IPv4 payload checksum for UDP fragments
1972 * Must be used in conjunction with packet-split. */
1973 if (adapter->rx_ps_hdr_size)
1974 rxcsum |= E1000_RXCSUM_IPPCSE;
1975 } else {
1976 rxcsum &= ~E1000_RXCSUM_TUOFL;
1977 /* don't need to clear IPPCSE as it defaults to 0 */
1978 }
1979 wr32(E1000_RXCSUM, rxcsum);
1980 }
1981
1982 if (adapter->vlgrp)
1983 wr32(E1000_RLPML,
1984 adapter->max_frame_size + VLAN_TAG_SIZE);
1985 else
1986 wr32(E1000_RLPML, adapter->max_frame_size);
1987
1988 /* Enable Receives */
1989 wr32(E1000_RCTL, rctl);
1990}
1991
1992/**
1993 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1994 * @tx_ring: Tx descriptor ring for a specific queue
1995 *
1996 * Free all transmit software resources
1997 **/
68fd9910 1998void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1999{
3b644cf6 2000 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2001
3b644cf6 2002 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2003
2004 vfree(tx_ring->buffer_info);
2005 tx_ring->buffer_info = NULL;
2006
2007 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2008
2009 tx_ring->desc = NULL;
2010}
2011
2012/**
2013 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2014 * @adapter: board private structure
2015 *
2016 * Free all transmit software resources
2017 **/
2018static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2019{
2020 int i;
2021
2022 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2023 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2024}
2025
2026static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2027 struct igb_buffer *buffer_info)
2028{
2029 if (buffer_info->dma) {
2030 pci_unmap_page(adapter->pdev,
2031 buffer_info->dma,
2032 buffer_info->length,
2033 PCI_DMA_TODEVICE);
2034 buffer_info->dma = 0;
2035 }
2036 if (buffer_info->skb) {
2037 dev_kfree_skb_any(buffer_info->skb);
2038 buffer_info->skb = NULL;
2039 }
2040 buffer_info->time_stamp = 0;
2041 /* buffer_info must be completely set up in the transmit path */
2042}
2043
2044/**
2045 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2046 * @tx_ring: ring to be cleaned
2047 **/
3b644cf6 2048static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2049{
3b644cf6 2050 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2051 struct igb_buffer *buffer_info;
2052 unsigned long size;
2053 unsigned int i;
2054
2055 if (!tx_ring->buffer_info)
2056 return;
2057 /* Free all the Tx ring sk_buffs */
2058
2059 for (i = 0; i < tx_ring->count; i++) {
2060 buffer_info = &tx_ring->buffer_info[i];
2061 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2062 }
2063
2064 size = sizeof(struct igb_buffer) * tx_ring->count;
2065 memset(tx_ring->buffer_info, 0, size);
2066
2067 /* Zero out the descriptor ring */
2068
2069 memset(tx_ring->desc, 0, tx_ring->size);
2070
2071 tx_ring->next_to_use = 0;
2072 tx_ring->next_to_clean = 0;
2073
2074 writel(0, adapter->hw.hw_addr + tx_ring->head);
2075 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2076}
2077
2078/**
2079 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2080 * @adapter: board private structure
2081 **/
2082static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2083{
2084 int i;
2085
2086 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2087 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2088}
2089
2090/**
2091 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2092 * @rx_ring: ring to clean the resources from
2093 *
2094 * Free all receive software resources
2095 **/
68fd9910 2096void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2097{
3b644cf6 2098 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2099
3b644cf6 2100 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2101
2102 vfree(rx_ring->buffer_info);
2103 rx_ring->buffer_info = NULL;
2104
2105 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2106
2107 rx_ring->desc = NULL;
2108}
2109
2110/**
2111 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2112 * @adapter: board private structure
2113 *
2114 * Free all receive software resources
2115 **/
2116static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2117{
2118 int i;
2119
2120 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2121 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2122}
2123
2124/**
2125 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2126 * @rx_ring: ring to free buffers from
2127 **/
3b644cf6 2128static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2129{
3b644cf6 2130 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2131 struct igb_buffer *buffer_info;
2132 struct pci_dev *pdev = adapter->pdev;
2133 unsigned long size;
2134 unsigned int i;
2135
2136 if (!rx_ring->buffer_info)
2137 return;
2138 /* Free all the Rx ring sk_buffs */
2139 for (i = 0; i < rx_ring->count; i++) {
2140 buffer_info = &rx_ring->buffer_info[i];
2141 if (buffer_info->dma) {
2142 if (adapter->rx_ps_hdr_size)
2143 pci_unmap_single(pdev, buffer_info->dma,
2144 adapter->rx_ps_hdr_size,
2145 PCI_DMA_FROMDEVICE);
2146 else
2147 pci_unmap_single(pdev, buffer_info->dma,
2148 adapter->rx_buffer_len,
2149 PCI_DMA_FROMDEVICE);
2150 buffer_info->dma = 0;
2151 }
2152
2153 if (buffer_info->skb) {
2154 dev_kfree_skb(buffer_info->skb);
2155 buffer_info->skb = NULL;
2156 }
2157 if (buffer_info->page) {
bf36c1a0
AD		 2158 if (buffer_info->page_dma)
2159 pci_unmap_page(pdev, buffer_info->page_dma,
2160 PAGE_SIZE / 2,
2161 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2162 put_page(buffer_info->page);
2163 buffer_info->page = NULL;
2164 buffer_info->page_dma = 0;
bf36c1a0 2165 buffer_info->page_offset = 0;
9d5c8243
AK		 2166 }
2167 }
2168
9d5c8243
AK		 2169 size = sizeof(struct igb_buffer) * rx_ring->count;
2170 memset(rx_ring->buffer_info, 0, size);
2171
2172 /* Zero out the descriptor ring */
2173 memset(rx_ring->desc, 0, rx_ring->size);
2174
2175 rx_ring->next_to_clean = 0;
2176 rx_ring->next_to_use = 0;
2177
2178 writel(0, adapter->hw.hw_addr + rx_ring->head);
2179 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2180}
2181
2182/**
2183 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2184 * @adapter: board private structure
2185 **/
2186static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2187{
2188 int i;
2189
2190 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2191 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2192}
2193
2194/**
2195 * igb_set_mac - Change the Ethernet Address of the NIC
2196 * @netdev: network interface device structure
2197 * @p: pointer to an address structure
2198 *
2199 * Returns 0 on success, negative on failure
2200 **/
2201static int igb_set_mac(struct net_device *netdev, void *p)
2202{
2203 struct igb_adapter *adapter = netdev_priv(netdev);
2204 struct sockaddr *addr = p;
2205
2206 if (!is_valid_ether_addr(addr->sa_data))
2207 return -EADDRNOTAVAIL;
2208
2209 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2210 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2211
2212 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2213
2214 return 0;
2215}
2216
2217/**
2218 * igb_set_multi - Multicast and Promiscuous mode set
2219 * @netdev: network interface device structure
2220 *
2221 * The set_multi entry point is called whenever the multicast address
2222 * list or the network interface flags are updated. This routine is
2223 * responsible for configuring the hardware for proper multicast,
2224 * promiscuous mode, and all-multi behavior.
2225 **/
2226static void igb_set_multi(struct net_device *netdev)
2227{
2228 struct igb_adapter *adapter = netdev_priv(netdev);
2229 struct e1000_hw *hw = &adapter->hw;
2230 struct e1000_mac_info *mac = &hw->mac;
2231 struct dev_mc_list *mc_ptr;
2232 u8 *mta_list;
2233 u32 rctl;
2234 int i;
2235
2236 /* Check for Promiscuous and All Multicast modes */
2237
2238 rctl = rd32(E1000_RCTL);
2239
746b9f02 2240 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2241 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2242 rctl &= ~E1000_RCTL_VFE;
2243 } else {
2244 if (netdev->flags & IFF_ALLMULTI) {
2245 rctl |= E1000_RCTL_MPE;
2246 rctl &= ~E1000_RCTL_UPE;
2247 } else
2248 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2249 rctl |= E1000_RCTL_VFE;
746b9f02 2250 }
9d5c8243
AK		 2251 wr32(E1000_RCTL, rctl);
2252
2253 if (!netdev->mc_count) {
2254 /* nothing to program, so clear mc list */
2d064c06 2255 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2256 mac->rar_entry_count);
2257 return;
2258 }
2259
2260 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2261 if (!mta_list)
2262 return;
2263
2264 /* The shared function expects a packed array of only addresses. */
2265 mc_ptr = netdev->mc_list;
2266
2267 for (i = 0; i < netdev->mc_count; i++) {
2268 if (!mc_ptr)
2269 break;
2270 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2271 mc_ptr = mc_ptr->next;
2272 }
2d064c06
AD		 2273 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2274 mac->rar_entry_count);
9d5c8243
AK		 2275 kfree(mta_list);
2276}
2277
2278/* Need to wait a few seconds after link up to get diagnostic information from
2279 * the phy */
2280static void igb_update_phy_info(unsigned long data)
2281{
2282 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2283 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2284}
2285
2286/**
2287 * igb_watchdog - Timer Call-back
2288 * @data: pointer to adapter cast into an unsigned long
2289 **/
2290static void igb_watchdog(unsigned long data)
2291{
2292 struct igb_adapter *adapter = (struct igb_adapter *)data;
2293 /* Do the rest outside of interrupt context */
2294 schedule_work(&adapter->watchdog_task);
2295}
2296
2297static void igb_watchdog_task(struct work_struct *work)
2298{
2299 struct igb_adapter *adapter = container_of(work,
2300 struct igb_adapter, watchdog_task);
2301 struct e1000_hw *hw = &adapter->hw;
2302
2303 struct net_device *netdev = adapter->netdev;
2304 struct igb_ring *tx_ring = adapter->tx_ring;
2305 struct e1000_mac_info *mac = &adapter->hw.mac;
2306 u32 link;
7a6ea550 2307 u32 eics = 0;
9d5c8243 2308 s32 ret_val;
7a6ea550 2309 int i;
9d5c8243
AK		 2310
2311 if ((netif_carrier_ok(netdev)) &&
2312 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2313 goto link_up;
2314
2315 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2316 if ((ret_val == E1000_ERR_PHY) &&
2317 (hw->phy.type == e1000_phy_igp_3) &&
2318 (rd32(E1000_CTRL) &
2319 E1000_PHY_CTRL_GBE_DISABLE))
2320 dev_info(&adapter->pdev->dev,
2321 "Gigabit has been disabled, downgrading speed\n");
2322
2323 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2324 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2325 link = mac->serdes_has_link;
2326 else
2327 link = rd32(E1000_STATUS) &
2328 E1000_STATUS_LU;
2329
2330 if (link) {
2331 if (!netif_carrier_ok(netdev)) {
2332 u32 ctrl;
2333 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2334 &adapter->link_speed,
2335 &adapter->link_duplex);
2336
2337 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2338 /* Links status message must follow this format */
2339 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2340 "Flow Control: %s\n",
527d47c1 2341 netdev->name,
9d5c8243
AK		 2342 adapter->link_speed,
2343 adapter->link_duplex == FULL_DUPLEX ?
2344 "Full Duplex" : "Half Duplex",
2345 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2346 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2347 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2348 E1000_CTRL_TFCE) ? "TX" : "None")));
2349
2350 /* tweak tx_queue_len according to speed/duplex and
2351 * adjust the timeout factor */
2352 netdev->tx_queue_len = adapter->tx_queue_len;
2353 adapter->tx_timeout_factor = 1;
2354 switch (adapter->link_speed) {
2355 case SPEED_10:
2356 netdev->tx_queue_len = 10;
2357 adapter->tx_timeout_factor = 14;
2358 break;
2359 case SPEED_100:
2360 netdev->tx_queue_len = 100;
2361 /* maybe add some timeout factor ? */
2362 break;
2363 }
2364
2365 netif_carrier_on(netdev);
fd2ea0a7 2366 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2367
2368 if (!test_bit(__IGB_DOWN, &adapter->state))
2369 mod_timer(&adapter->phy_info_timer,
2370 round_jiffies(jiffies + 2 * HZ));
2371 }
2372 } else {
2373 if (netif_carrier_ok(netdev)) {
2374 adapter->link_speed = 0;
2375 adapter->link_duplex = 0;
527d47c1
AD		 2376 /* Links status message must follow this format */
2377 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2378 netdev->name);
9d5c8243 2379 netif_carrier_off(netdev);
fd2ea0a7 2380 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2381 if (!test_bit(__IGB_DOWN, &adapter->state))
2382 mod_timer(&adapter->phy_info_timer,
2383 round_jiffies(jiffies + 2 * HZ));
2384 }
2385 }
2386
2387link_up:
2388 igb_update_stats(adapter);
2389
2390 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2391 adapter->tpt_old = adapter->stats.tpt;
2392 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2393 adapter->colc_old = adapter->stats.colc;
2394
2395 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2396 adapter->gorc_old = adapter->stats.gorc;
2397 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2398 adapter->gotc_old = adapter->stats.gotc;
2399
2400 igb_update_adaptive(&adapter->hw);
2401
2402 if (!netif_carrier_ok(netdev)) {
2403 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2404 /* We've lost link, so the controller stops DMA,
2405 * but we've got queued Tx work that's never going
2406 * to get done, so reset controller to flush Tx.
2407 * (Do the reset outside of interrupt context). */
2408 adapter->tx_timeout_count++;
2409 schedule_work(&adapter->reset_task);
2410 }
2411 }
2412
2413 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2414 if (adapter->msix_entries) {
2415 for (i = 0; i < adapter->num_rx_queues; i++)
2416 eics |= adapter->rx_ring[i].eims_value;
2417 wr32(E1000_EICS, eics);
2418 } else {
2419 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2420 }
9d5c8243
AK		 2421
2422 /* Force detection of hung controller every watchdog period */
2423 tx_ring->detect_tx_hung = true;
2424
2425 /* Reset the timer */
2426 if (!test_bit(__IGB_DOWN, &adapter->state))
2427 mod_timer(&adapter->watchdog_timer,
2428 round_jiffies(jiffies + 2 * HZ));
2429}
2430
2431enum latency_range {
2432 lowest_latency = 0,
2433 low_latency = 1,
2434 bulk_latency = 2,
2435 latency_invalid = 255
2436};
2437
2438
6eb5a7f1
AD		 2439/**
2440 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2441 *
2442 * Stores a new ITR value based on strictly on packet size. This
2443 * algorithm is less sophisticated than that used in igb_update_itr,
2444 * due to the difficulty of synchronizing statistics across multiple
2445 * receive rings. The divisors and thresholds used by this fuction
2446 * were determined based on theoretical maximum wire speed and testing
2447 * data, in order to minimize response time while increasing bulk
2448 * throughput.
2449 * This functionality is controlled by the InterruptThrottleRate module
2450 * parameter (see igb_param.c)
2451 * NOTE: This function is called only when operating in a multiqueue
2452 * receive environment.
2453 * @rx_ring: pointer to ring
2454 **/
2455static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2456{
6eb5a7f1
AD		 2457 int new_val = rx_ring->itr_val;
2458 int avg_wire_size = 0;
2459 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2460
6eb5a7f1
AD		 2461 if (!rx_ring->total_packets)
2462 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2463
6eb5a7f1
AD		 2464 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2465 * ints/sec - ITR timer value of 120 ticks.
2466 */
2467 if (adapter->link_speed != SPEED_1000) {
2468 new_val = 120;
2469 goto set_itr_val;
9d5c8243 2470 }
6eb5a7f1 2471 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2472
6eb5a7f1
AD		 2473 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2474 avg_wire_size += 24;
2475
2476 /* Don't starve jumbo frames */
2477 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2478
6eb5a7f1
AD		 2479 /* Give a little boost to mid-size frames */
2480 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2481 new_val = avg_wire_size / 3;
2482 else
2483 new_val = avg_wire_size / 2;
9d5c8243 2484
6eb5a7f1 2485set_itr_val:
9d5c8243
AK		 2486 if (new_val != rx_ring->itr_val) {
2487 rx_ring->itr_val = new_val;
6eb5a7f1 2488 rx_ring->set_itr = 1;
9d5c8243 2489 }
6eb5a7f1
AD		 2490clear_counts:
2491 rx_ring->total_bytes = 0;
2492 rx_ring->total_packets = 0;
9d5c8243
AK		 2493}
2494
2495/**
2496 * igb_update_itr - update the dynamic ITR value based on statistics
2497 * Stores a new ITR value based on packets and byte
2498 * counts during the last interrupt. The advantage of per interrupt
2499 * computation is faster updates and more accurate ITR for the current
2500 * traffic pattern. Constants in this function were computed
2501 * based on theoretical maximum wire speed and thresholds were set based
2502 * on testing data as well as attempting to minimize response time
2503 * while increasing bulk throughput.
2504 * this functionality is controlled by the InterruptThrottleRate module
2505 * parameter (see igb_param.c)
2506 * NOTE: These calculations are only valid when operating in a single-
2507 * queue environment.
2508 * @adapter: pointer to adapter
2509 * @itr_setting: current adapter->itr
2510 * @packets: the number of packets during this measurement interval
2511 * @bytes: the number of bytes during this measurement interval
2512 **/
2513static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2514 int packets, int bytes)
2515{
2516 unsigned int retval = itr_setting;
2517
2518 if (packets == 0)
2519 goto update_itr_done;
2520
2521 switch (itr_setting) {
2522 case lowest_latency:
2523 /* handle TSO and jumbo frames */
2524 if (bytes/packets > 8000)
2525 retval = bulk_latency;
2526 else if ((packets < 5) && (bytes > 512))
2527 retval = low_latency;
2528 break;
2529 case low_latency: /* 50 usec aka 20000 ints/s */
2530 if (bytes > 10000) {
2531 /* this if handles the TSO accounting */
2532 if (bytes/packets > 8000) {
2533 retval = bulk_latency;
2534 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2535 retval = bulk_latency;
2536 } else if ((packets > 35)) {
2537 retval = lowest_latency;
2538 }
2539 } else if (bytes/packets > 2000) {
2540 retval = bulk_latency;
2541 } else if (packets <= 2 && bytes < 512) {
2542 retval = lowest_latency;
2543 }
2544 break;
2545 case bulk_latency: /* 250 usec aka 4000 ints/s */
2546 if (bytes > 25000) {
2547 if (packets > 35)
2548 retval = low_latency;
2549 } else if (bytes < 6000) {
2550 retval = low_latency;
2551 }
2552 break;
2553 }
2554
2555update_itr_done:
2556 return retval;
2557}
2558
6eb5a7f1 2559static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2560{
2561 u16 current_itr;
2562 u32 new_itr = adapter->itr;
2563
2564 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2565 if (adapter->link_speed != SPEED_1000) {
2566 current_itr = 0;
2567 new_itr = 4000;
2568 goto set_itr_now;
2569 }
2570
2571 adapter->rx_itr = igb_update_itr(adapter,
2572 adapter->rx_itr,
2573 adapter->rx_ring->total_packets,
2574 adapter->rx_ring->total_bytes);
9d5c8243 2575
6eb5a7f1 2576 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2577 adapter->tx_itr = igb_update_itr(adapter,
2578 adapter->tx_itr,
2579 adapter->tx_ring->total_packets,
2580 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2581
2582 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2583 } else {
2584 current_itr = adapter->rx_itr;
2585 }
2586
6eb5a7f1
AD		 2587 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2588 if (adapter->itr_setting == 3 &&
2589 current_itr == lowest_latency)
2590 current_itr = low_latency;
2591
9d5c8243
AK		 2592 switch (current_itr) {
2593 /* counts and packets in update_itr are dependent on these numbers */
2594 case lowest_latency:
2595 new_itr = 70000;
2596 break;
2597 case low_latency:
2598 new_itr = 20000; /* aka hwitr = ~200 */
2599 break;
2600 case bulk_latency:
2601 new_itr = 4000;
2602 break;
2603 default:
2604 break;
2605 }
2606
2607set_itr_now:
6eb5a7f1
AD		 2608 adapter->rx_ring->total_bytes = 0;
2609 adapter->rx_ring->total_packets = 0;
2610 if (adapter->rx_ring->buddy) {
2611 adapter->rx_ring->buddy->total_bytes = 0;
2612 adapter->rx_ring->buddy->total_packets = 0;
2613 }
2614
9d5c8243
AK		 2615 if (new_itr != adapter->itr) {
2616 /* this attempts to bias the interrupt rate towards Bulk
2617 * by adding intermediate steps when interrupt rate is
2618 * increasing */
2619 new_itr = new_itr > adapter->itr ?
2620 min(adapter->itr + (new_itr >> 2), new_itr) :
2621 new_itr;
2622 /* Don't write the value here; it resets the adapter's
2623 * internal timer, and causes us to delay far longer than
2624 * we should between interrupts. Instead, we write the ITR
2625 * value at the beginning of the next interrupt so the timing
2626 * ends up being correct.
2627 */
2628 adapter->itr = new_itr;
6eb5a7f1
AD		 2629 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2630 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2631 }
2632
2633 return;
2634}
2635
2636
2637#define IGB_TX_FLAGS_CSUM 0x00000001
2638#define IGB_TX_FLAGS_VLAN 0x00000002
2639#define IGB_TX_FLAGS_TSO 0x00000004
2640#define IGB_TX_FLAGS_IPV4 0x00000008
2641#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2642#define IGB_TX_FLAGS_VLAN_SHIFT 16
2643
2644static inline int igb_tso_adv(struct igb_adapter *adapter,
2645 struct igb_ring *tx_ring,
2646 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2647{
2648 struct e1000_adv_tx_context_desc *context_desc;
2649 unsigned int i;
2650 int err;
2651 struct igb_buffer *buffer_info;
2652 u32 info = 0, tu_cmd = 0;
2653 u32 mss_l4len_idx, l4len;
2654 *hdr_len = 0;
2655
2656 if (skb_header_cloned(skb)) {
2657 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2658 if (err)
2659 return err;
2660 }
2661
2662 l4len = tcp_hdrlen(skb);
2663 *hdr_len += l4len;
2664
2665 if (skb->protocol == htons(ETH_P_IP)) {
2666 struct iphdr *iph = ip_hdr(skb);
2667 iph->tot_len = 0;
2668 iph->check = 0;
2669 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2670 iph->daddr, 0,
2671 IPPROTO_TCP,
2672 0);
2673 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2674 ipv6_hdr(skb)->payload_len = 0;
2675 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2676 &ipv6_hdr(skb)->daddr,
2677 0, IPPROTO_TCP, 0);
2678 }
2679
2680 i = tx_ring->next_to_use;
2681
2682 buffer_info = &tx_ring->buffer_info[i];
2683 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2684 /* VLAN MACLEN IPLEN */
2685 if (tx_flags & IGB_TX_FLAGS_VLAN)
2686 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2687 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2688 *hdr_len += skb_network_offset(skb);
2689 info |= skb_network_header_len(skb);
2690 *hdr_len += skb_network_header_len(skb);
2691 context_desc->vlan_macip_lens = cpu_to_le32(info);
2692
2693 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2694 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2695
2696 if (skb->protocol == htons(ETH_P_IP))
2697 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2698 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2699
2700 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2701
2702 /* MSS L4LEN IDX */
2703 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2704 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2705
7dfc16fa
AD		 2706 /* Context index must be unique per ring. */
2707 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2708 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2709
2710 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2711 context_desc->seqnum_seed = 0;
2712
2713 buffer_info->time_stamp = jiffies;
0e014cb1 2714 buffer_info->next_to_watch = i;
9d5c8243
AK		 2715 buffer_info->dma = 0;
2716 i++;
2717 if (i == tx_ring->count)
2718 i = 0;
2719
2720 tx_ring->next_to_use = i;
2721
2722 return true;
2723}
2724
2725static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2726 struct igb_ring *tx_ring,
2727 struct sk_buff *skb, u32 tx_flags)
2728{
2729 struct e1000_adv_tx_context_desc *context_desc;
2730 unsigned int i;
2731 struct igb_buffer *buffer_info;
2732 u32 info = 0, tu_cmd = 0;
2733
2734 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2735 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2736 i = tx_ring->next_to_use;
2737 buffer_info = &tx_ring->buffer_info[i];
2738 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2739
2740 if (tx_flags & IGB_TX_FLAGS_VLAN)
2741 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2742 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2743 if (skb->ip_summed == CHECKSUM_PARTIAL)
2744 info |= skb_network_header_len(skb);
2745
2746 context_desc->vlan_macip_lens = cpu_to_le32(info);
2747
2748 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2749
2750 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2751 switch (skb->protocol) {
09640e63 2752 case cpu_to_be16(ETH_P_IP):
9d5c8243 2753 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2754 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2755 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2756 break;
09640e63 2757 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2758 /* XXX what about other V6 headers?? */
2759 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2760 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2761 break;
2762 default:
2763 if (unlikely(net_ratelimit()))
2764 dev_warn(&adapter->pdev->dev,
2765 "partial checksum but proto=%x!\n",
2766 skb->protocol);
2767 break;
2768 }
9d5c8243
AK		 2769 }
2770
2771 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2772 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2773 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2774 context_desc->mss_l4len_idx =
2775 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2776
2777 buffer_info->time_stamp = jiffies;
0e014cb1 2778 buffer_info->next_to_watch = i;
9d5c8243
AK		 2779 buffer_info->dma = 0;
2780
2781 i++;
2782 if (i == tx_ring->count)
2783 i = 0;
2784 tx_ring->next_to_use = i;
2785
2786 return true;
2787 }
2788
2789
2790 return false;
2791}
2792
2793#define IGB_MAX_TXD_PWR 16
2794#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2795
2796static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2797 struct igb_ring *tx_ring, struct sk_buff *skb,
2798 unsigned int first)
9d5c8243
AK		 2799{
2800 struct igb_buffer *buffer_info;
2801 unsigned int len = skb_headlen(skb);
2802 unsigned int count = 0, i;
2803 unsigned int f;
2804
2805 i = tx_ring->next_to_use;
2806
2807 buffer_info = &tx_ring->buffer_info[i];
2808 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2809 buffer_info->length = len;
2810 /* set time_stamp *before* dma to help avoid a possible race */
2811 buffer_info->time_stamp = jiffies;
0e014cb1 2812 buffer_info->next_to_watch = i;
9d5c8243
AK		 2813 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2814 PCI_DMA_TODEVICE);
2815 count++;
2816 i++;
2817 if (i == tx_ring->count)
2818 i = 0;
2819
2820 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2821 struct skb_frag_struct *frag;
2822
2823 frag = &skb_shinfo(skb)->frags[f];
2824 len = frag->size;
2825
2826 buffer_info = &tx_ring->buffer_info[i];
2827 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2828 buffer_info->length = len;
2829 buffer_info->time_stamp = jiffies;
0e014cb1 2830 buffer_info->next_to_watch = i;
9d5c8243
AK		 2831 buffer_info->dma = pci_map_page(adapter->pdev,
2832 frag->page,
2833 frag->page_offset,
2834 len,
2835 PCI_DMA_TODEVICE);
2836
2837 count++;
2838 i++;
2839 if (i == tx_ring->count)
2840 i = 0;
2841 }
2842
0e014cb1 2843 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2844 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2845 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2846
2847 return count;
2848}
2849
2850static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2851 struct igb_ring *tx_ring,
2852 int tx_flags, int count, u32 paylen,
2853 u8 hdr_len)
2854{
2855 union e1000_adv_tx_desc *tx_desc = NULL;
2856 struct igb_buffer *buffer_info;
2857 u32 olinfo_status = 0, cmd_type_len;
2858 unsigned int i;
2859
2860 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2861 E1000_ADVTXD_DCMD_DEXT);
2862
2863 if (tx_flags & IGB_TX_FLAGS_VLAN)
2864 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2865
2866 if (tx_flags & IGB_TX_FLAGS_TSO) {
2867 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2868
2869 /* insert tcp checksum */
2870 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2871
2872 /* insert ip checksum */
2873 if (tx_flags & IGB_TX_FLAGS_IPV4)
2874 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2875
2876 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2877 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2878 }
2879
7dfc16fa
AD		 2880 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2881 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2882 IGB_TX_FLAGS_VLAN)))
661086df 2883 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2884
2885 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2886
2887 i = tx_ring->next_to_use;
2888 while (count--) {
2889 buffer_info = &tx_ring->buffer_info[i];
2890 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2891 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2892 tx_desc->read.cmd_type_len =
2893 cpu_to_le32(cmd_type_len | buffer_info->length);
2894 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2895 i++;
2896 if (i == tx_ring->count)
2897 i = 0;
2898 }
2899
2900 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2901 /* Force memory writes to complete before letting h/w
2902 * know there are new descriptors to fetch. (Only
2903 * applicable for weak-ordered memory model archs,
2904 * such as IA-64). */
2905 wmb();
2906
2907 tx_ring->next_to_use = i;
2908 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2909 /* we need this if more than one processor can write to our tail
2910 * at a time, it syncronizes IO on IA64/Altix systems */
2911 mmiowb();
2912}
2913
2914static int __igb_maybe_stop_tx(struct net_device *netdev,
2915 struct igb_ring *tx_ring, int size)
2916{
2917 struct igb_adapter *adapter = netdev_priv(netdev);
2918
661086df 2919 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2920
9d5c8243
AK		 2921 /* Herbert's original patch had:
2922 * smp_mb__after_netif_stop_queue();
2923 * but since that doesn't exist yet, just open code it. */
2924 smp_mb();
2925
2926 /* We need to check again in a case another CPU has just
2927 * made room available. */
2928 if (IGB_DESC_UNUSED(tx_ring) < size)
2929 return -EBUSY;
2930
2931 /* A reprieve! */
661086df 2932 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2933 ++adapter->restart_queue;
2934 return 0;
2935}
2936
2937static int igb_maybe_stop_tx(struct net_device *netdev,
2938 struct igb_ring *tx_ring, int size)
2939{
2940 if (IGB_DESC_UNUSED(tx_ring) >= size)
2941 return 0;
2942 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2943}
2944
2945#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2946
2947static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2948 struct net_device *netdev,
2949 struct igb_ring *tx_ring)
2950{
2951 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2952 unsigned int first;
9d5c8243
AK		 2953 unsigned int tx_flags = 0;
2954 unsigned int len;
9d5c8243
AK		 2955 u8 hdr_len = 0;
2956 int tso = 0;
2957
2958 len = skb_headlen(skb);
2959
2960 if (test_bit(__IGB_DOWN, &adapter->state)) {
2961 dev_kfree_skb_any(skb);
2962 return NETDEV_TX_OK;
2963 }
2964
2965 if (skb->len <= 0) {
2966 dev_kfree_skb_any(skb);
2967 return NETDEV_TX_OK;
2968 }
2969
9d5c8243
AK		 2970 /* need: 1 descriptor per page,
2971 * + 2 desc gap to keep tail from touching head,
2972 * + 1 desc for skb->data,
2973 * + 1 desc for context descriptor,
2974 * otherwise try next time */
2975 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2976 /* this is a hard error */
9d5c8243
AK		 2977 return NETDEV_TX_BUSY;
2978 }
6eb5a7f1 2979 skb_orphan(skb);
9d5c8243
AK		 2980
2981 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2982 tx_flags |= IGB_TX_FLAGS_VLAN;
2983 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2984 }
2985
661086df
PWJ		 2986 if (skb->protocol == htons(ETH_P_IP))
2987 tx_flags |= IGB_TX_FLAGS_IPV4;
2988
0e014cb1
AD		 2989 first = tx_ring->next_to_use;
2990
9d5c8243
AK		 2991 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2992 &hdr_len) : 0;
2993
2994 if (tso < 0) {
2995 dev_kfree_skb_any(skb);
9d5c8243
AK		 2996 return NETDEV_TX_OK;
2997 }
2998
2999 if (tso)
3000 tx_flags |= IGB_TX_FLAGS_TSO;
3001 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3002 if (skb->ip_summed == CHECKSUM_PARTIAL)
3003 tx_flags |= IGB_TX_FLAGS_CSUM;
3004
9d5c8243 3005 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3006 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3007 skb->len, hdr_len);
3008
3009 netdev->trans_start = jiffies;
3010
3011 /* Make sure there is space in the ring for the next send. */
3012 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3013
9d5c8243
AK		 3014 return NETDEV_TX_OK;
3015}
3016
3017static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3018{
3019 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3020 struct igb_ring *tx_ring;
3021
661086df
PWJ		 3022 int r_idx = 0;
3023 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3024 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3025
3026 /* This goes back to the question of how to logically map a tx queue
3027 * to a flow. Right now, performance is impacted slightly negatively
3028 * if using multiple tx queues. If the stack breaks away from a
3029 * single qdisc implementation, we can look at this again. */
3030 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3031}
3032
3033/**
3034 * igb_tx_timeout - Respond to a Tx Hang
3035 * @netdev: network interface device structure
3036 **/
3037static void igb_tx_timeout(struct net_device *netdev)
3038{
3039 struct igb_adapter *adapter = netdev_priv(netdev);
3040 struct e1000_hw *hw = &adapter->hw;
3041
3042 /* Do the reset outside of interrupt context */
3043 adapter->tx_timeout_count++;
3044 schedule_work(&adapter->reset_task);
3045 wr32(E1000_EICS, adapter->eims_enable_mask &
3046 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3047}
3048
3049static void igb_reset_task(struct work_struct *work)
3050{
3051 struct igb_adapter *adapter;
3052 adapter = container_of(work, struct igb_adapter, reset_task);
3053
3054 igb_reinit_locked(adapter);
3055}
3056
3057/**
3058 * igb_get_stats - Get System Network Statistics
3059 * @netdev: network interface device structure
3060 *
3061 * Returns the address of the device statistics structure.
3062 * The statistics are actually updated from the timer callback.
3063 **/
3064static struct net_device_stats *
3065igb_get_stats(struct net_device *netdev)
3066{
3067 struct igb_adapter *adapter = netdev_priv(netdev);
3068
3069 /* only return the current stats */
3070 return &adapter->net_stats;
3071}
3072
3073/**
3074 * igb_change_mtu - Change the Maximum Transfer Unit
3075 * @netdev: network interface device structure
3076 * @new_mtu: new value for maximum frame size
3077 *
3078 * Returns 0 on success, negative on failure
3079 **/
3080static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3081{
3082 struct igb_adapter *adapter = netdev_priv(netdev);
3083 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3084
3085 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3086 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3087 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3088 return -EINVAL;
3089 }
3090
3091#define MAX_STD_JUMBO_FRAME_SIZE 9234
3092 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3093 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3094 return -EINVAL;
3095 }
3096
3097 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3098 msleep(1);
3099 /* igb_down has a dependency on max_frame_size */
3100 adapter->max_frame_size = max_frame;
3101 if (netif_running(netdev))
3102 igb_down(adapter);
3103
3104 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3105 * means we reserve 2 more, this pushes us to allocate from the next
3106 * larger slab size.
3107 * i.e. RXBUFFER_2048 --> size-4096 slab
3108 */
3109
3110 if (max_frame <= IGB_RXBUFFER_256)
3111 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3112 else if (max_frame <= IGB_RXBUFFER_512)
3113 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3114 else if (max_frame <= IGB_RXBUFFER_1024)
3115 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3116 else if (max_frame <= IGB_RXBUFFER_2048)
3117 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3118 else
bf36c1a0
AD		 3119#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3120 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3121#else
3122 adapter->rx_buffer_len = PAGE_SIZE / 2;
3123#endif
9d5c8243
AK		 3124 /* adjust allocation if LPE protects us, and we aren't using SBP */
3125 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3126 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3127 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3128
3129 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3130 netdev->mtu, new_mtu);
3131 netdev->mtu = new_mtu;
3132
3133 if (netif_running(netdev))
3134 igb_up(adapter);
3135 else
3136 igb_reset(adapter);
3137
3138 clear_bit(__IGB_RESETTING, &adapter->state);
3139
3140 return 0;
3141}
3142
3143/**
3144 * igb_update_stats - Update the board statistics counters
3145 * @adapter: board private structure
3146 **/
3147
3148void igb_update_stats(struct igb_adapter *adapter)
3149{
3150 struct e1000_hw *hw = &adapter->hw;
3151 struct pci_dev *pdev = adapter->pdev;
3152 u16 phy_tmp;
3153
3154#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3155
3156 /*
3157 * Prevent stats update while adapter is being reset, or if the pci
3158 * connection is down.
3159 */
3160 if (adapter->link_speed == 0)
3161 return;
3162 if (pci_channel_offline(pdev))
3163 return;
3164
3165 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3166 adapter->stats.gprc += rd32(E1000_GPRC);
3167 adapter->stats.gorc += rd32(E1000_GORCL);
3168 rd32(E1000_GORCH); /* clear GORCL */
3169 adapter->stats.bprc += rd32(E1000_BPRC);
3170 adapter->stats.mprc += rd32(E1000_MPRC);
3171 adapter->stats.roc += rd32(E1000_ROC);
3172
3173 adapter->stats.prc64 += rd32(E1000_PRC64);
3174 adapter->stats.prc127 += rd32(E1000_PRC127);
3175 adapter->stats.prc255 += rd32(E1000_PRC255);
3176 adapter->stats.prc511 += rd32(E1000_PRC511);
3177 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3178 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3179 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3180 adapter->stats.sec += rd32(E1000_SEC);
3181
3182 adapter->stats.mpc += rd32(E1000_MPC);
3183 adapter->stats.scc += rd32(E1000_SCC);
3184 adapter->stats.ecol += rd32(E1000_ECOL);
3185 adapter->stats.mcc += rd32(E1000_MCC);
3186 adapter->stats.latecol += rd32(E1000_LATECOL);
3187 adapter->stats.dc += rd32(E1000_DC);
3188 adapter->stats.rlec += rd32(E1000_RLEC);
3189 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3190 adapter->stats.xontxc += rd32(E1000_XONTXC);
3191 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3192 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3193 adapter->stats.fcruc += rd32(E1000_FCRUC);
3194 adapter->stats.gptc += rd32(E1000_GPTC);
3195 adapter->stats.gotc += rd32(E1000_GOTCL);
3196 rd32(E1000_GOTCH); /* clear GOTCL */
3197 adapter->stats.rnbc += rd32(E1000_RNBC);
3198 adapter->stats.ruc += rd32(E1000_RUC);
3199 adapter->stats.rfc += rd32(E1000_RFC);
3200 adapter->stats.rjc += rd32(E1000_RJC);
3201 adapter->stats.tor += rd32(E1000_TORH);
3202 adapter->stats.tot += rd32(E1000_TOTH);
3203 adapter->stats.tpr += rd32(E1000_TPR);
3204
3205 adapter->stats.ptc64 += rd32(E1000_PTC64);
3206 adapter->stats.ptc127 += rd32(E1000_PTC127);
3207 adapter->stats.ptc255 += rd32(E1000_PTC255);
3208 adapter->stats.ptc511 += rd32(E1000_PTC511);
3209 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3210 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3211
3212 adapter->stats.mptc += rd32(E1000_MPTC);
3213 adapter->stats.bptc += rd32(E1000_BPTC);
3214
3215 /* used for adaptive IFS */
3216
3217 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3218 adapter->stats.tpt += hw->mac.tx_packet_delta;
3219 hw->mac.collision_delta = rd32(E1000_COLC);
3220 adapter->stats.colc += hw->mac.collision_delta;
3221
3222 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3223 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3224 adapter->stats.tncrs += rd32(E1000_TNCRS);
3225 adapter->stats.tsctc += rd32(E1000_TSCTC);
3226 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3227
3228 adapter->stats.iac += rd32(E1000_IAC);
3229 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3230 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3231 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3232 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3233 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3234 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3235 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3236 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3237
3238 /* Fill out the OS statistics structure */
3239 adapter->net_stats.multicast = adapter->stats.mprc;
3240 adapter->net_stats.collisions = adapter->stats.colc;
3241
3242 /* Rx Errors */
3243
3244 /* RLEC on some newer hardware can be incorrect so build
3245 * our own version based on RUC and ROC */
3246 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3247 adapter->stats.crcerrs + adapter->stats.algnerrc +
3248 adapter->stats.ruc + adapter->stats.roc +
3249 adapter->stats.cexterr;
3250 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3251 adapter->stats.roc;
3252 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3253 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3254 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3255
3256 /* Tx Errors */
3257 adapter->net_stats.tx_errors = adapter->stats.ecol +
3258 adapter->stats.latecol;
3259 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3260 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3261 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3262
3263 /* Tx Dropped needs to be maintained elsewhere */
3264
3265 /* Phy Stats */
3266 if (hw->phy.media_type == e1000_media_type_copper) {
3267 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3268 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3269 &phy_tmp))) {
3270 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3271 adapter->phy_stats.idle_errors += phy_tmp;
3272 }
3273 }
3274
3275 /* Management Stats */
3276 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3277 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3278 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3279}
3280
3281
3282static irqreturn_t igb_msix_other(int irq, void *data)
3283{
3284 struct net_device *netdev = data;
3285 struct igb_adapter *adapter = netdev_priv(netdev);
3286 struct e1000_hw *hw = &adapter->hw;
844290e5 3287 u32 icr = rd32(E1000_ICR);
9d5c8243 3288
844290e5
PW		 3289 /* reading ICR causes bit 31 of EICR to be cleared */
3290 if (!(icr & E1000_ICR_LSC))
3291 goto no_link_interrupt;
3292 hw->mac.get_link_status = 1;
3293 /* guard against interrupt when we're going down */
3294 if (!test_bit(__IGB_DOWN, &adapter->state))
3295 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3296
9d5c8243
AK		 3297no_link_interrupt:
3298 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3299 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3300
3301 return IRQ_HANDLED;
3302}
3303
3304static irqreturn_t igb_msix_tx(int irq, void *data)
3305{
3306 struct igb_ring *tx_ring = data;
3307 struct igb_adapter *adapter = tx_ring->adapter;
3308 struct e1000_hw *hw = &adapter->hw;
3309
421e02f0 3310#ifdef CONFIG_IGB_DCA
7dfc16fa 3311 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3312 igb_update_tx_dca(tx_ring);
3313#endif
9d5c8243
AK		 3314 tx_ring->total_bytes = 0;
3315 tx_ring->total_packets = 0;
661086df
PWJ		 3316
3317 /* auto mask will automatically reenable the interrupt when we write
3318 * EICS */
3b644cf6 3319 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3320 /* Ring was not completely cleaned, so fire another interrupt */
3321 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3322 else
9d5c8243 3323 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3324
9d5c8243
AK		 3325 return IRQ_HANDLED;
3326}
3327
6eb5a7f1
AD		 3328static void igb_write_itr(struct igb_ring *ring)
3329{
3330 struct e1000_hw *hw = &ring->adapter->hw;
3331 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3332 switch (hw->mac.type) {
3333 case e1000_82576:
3334 wr32(ring->itr_register,
3335 ring->itr_val |
3336 0x80000000);
3337 break;
3338 default:
3339 wr32(ring->itr_register,
3340 ring->itr_val |
3341 (ring->itr_val << 16));
3342 break;
3343 }
3344 ring->set_itr = 0;
3345 }
3346}
3347
9d5c8243
AK		 3348static irqreturn_t igb_msix_rx(int irq, void *data)
3349{
3350 struct igb_ring *rx_ring = data;
9d5c8243 3351
844290e5
PW		 3352 /* Write the ITR value calculated at the end of the
3353 * previous interrupt.
3354 */
9d5c8243 3355
6eb5a7f1 3356 igb_write_itr(rx_ring);
9d5c8243 3357
288379f0
BH		 3358 if (napi_schedule_prep(&rx_ring->napi))
3359 __napi_schedule(&rx_ring->napi);
844290e5 3360
421e02f0 3361#ifdef CONFIG_IGB_DCA
8d253320 3362 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3363 igb_update_rx_dca(rx_ring);
3364#endif
3365 return IRQ_HANDLED;
3366}
3367
421e02f0 3368#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3369static void igb_update_rx_dca(struct igb_ring *rx_ring)
3370{
3371 u32 dca_rxctrl;
3372 struct igb_adapter *adapter = rx_ring->adapter;
3373 struct e1000_hw *hw = &adapter->hw;
3374 int cpu = get_cpu();
26bc19ec 3375 int q = rx_ring->reg_idx;
fe4506b6
JC		 3376
3377 if (rx_ring->cpu != cpu) {
3378 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3379 if (hw->mac.type == e1000_82576) {
3380 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3381 dca_rxctrl |= dca_get_tag(cpu) <<
3382 E1000_DCA_RXCTRL_CPUID_SHIFT;
3383 } else {
3384 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3385 dca_rxctrl |= dca_get_tag(cpu);
3386 }
fe4506b6
JC		 3387 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3388 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3389 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3390 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3391 rx_ring->cpu = cpu;
3392 }
3393 put_cpu();
3394}
3395
3396static void igb_update_tx_dca(struct igb_ring *tx_ring)
3397{
3398 u32 dca_txctrl;
3399 struct igb_adapter *adapter = tx_ring->adapter;
3400 struct e1000_hw *hw = &adapter->hw;
3401 int cpu = get_cpu();
26bc19ec 3402 int q = tx_ring->reg_idx;
fe4506b6
JC		 3403
3404 if (tx_ring->cpu != cpu) {
3405 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3406 if (hw->mac.type == e1000_82576) {
3407 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3408 dca_txctrl |= dca_get_tag(cpu) <<
3409 E1000_DCA_TXCTRL_CPUID_SHIFT;
3410 } else {
3411 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3412 dca_txctrl |= dca_get_tag(cpu);
3413 }
fe4506b6
JC		 3414 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3415 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3416 tx_ring->cpu = cpu;
3417 }
3418 put_cpu();
3419}
3420
3421static void igb_setup_dca(struct igb_adapter *adapter)
3422{
3423 int i;
3424
7dfc16fa 3425 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3426 return;
3427
3428 for (i = 0; i < adapter->num_tx_queues; i++) {
3429 adapter->tx_ring[i].cpu = -1;
3430 igb_update_tx_dca(&adapter->tx_ring[i]);
3431 }
3432 for (i = 0; i < adapter->num_rx_queues; i++) {
3433 adapter->rx_ring[i].cpu = -1;
3434 igb_update_rx_dca(&adapter->rx_ring[i]);
3435 }
3436}
3437
3438static int __igb_notify_dca(struct device *dev, void *data)
3439{
3440 struct net_device *netdev = dev_get_drvdata(dev);
3441 struct igb_adapter *adapter = netdev_priv(netdev);
3442 struct e1000_hw *hw = &adapter->hw;
3443 unsigned long event = *(unsigned long *)data;
3444
7dfc16fa
AD		 3445 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3446 goto out;
3447
fe4506b6
JC		 3448 switch (event) {
3449 case DCA_PROVIDER_ADD:
3450 /* if already enabled, don't do it again */
7dfc16fa 3451 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3452 break;
7dfc16fa 3453 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3454 /* Always use CB2 mode, difference is masked
3455 * in the CB driver. */
3456 wr32(E1000_DCA_CTRL, 2);
3457 if (dca_add_requester(dev) == 0) {
3458 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3459 igb_setup_dca(adapter);
3460 break;
3461 }
3462 /* Fall Through since DCA is disabled. */
3463 case DCA_PROVIDER_REMOVE:
7dfc16fa 3464 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3465 /* without this a class_device is left
3466 * hanging around in the sysfs model */
3467 dca_remove_requester(dev);
3468 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3469 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3470 wr32(E1000_DCA_CTRL, 1);
3471 }
3472 break;
3473 }
7dfc16fa 3474out:
fe4506b6 3475 return 0;
9d5c8243
AK		 3476}
3477
fe4506b6
JC		 3478static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3479 void *p)
3480{
3481 int ret_val;
3482
3483 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3484 __igb_notify_dca);
3485
3486 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3487}
421e02f0 3488#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3489
3490/**
3491 * igb_intr_msi - Interrupt Handler
3492 * @irq: interrupt number
3493 * @data: pointer to a network interface device structure
3494 **/
3495static irqreturn_t igb_intr_msi(int irq, void *data)
3496{
3497 struct net_device *netdev = data;
3498 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3499 struct e1000_hw *hw = &adapter->hw;
3500 /* read ICR disables interrupts using IAM */
3501 u32 icr = rd32(E1000_ICR);
3502
6eb5a7f1 3503 igb_write_itr(adapter->rx_ring);
9d5c8243 3504
9d5c8243
AK		 3505 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3506 hw->mac.get_link_status = 1;
3507 if (!test_bit(__IGB_DOWN, &adapter->state))
3508 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3509 }
3510
288379f0 3511 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3512
3513 return IRQ_HANDLED;
3514}
3515
3516/**
3517 * igb_intr - Interrupt Handler
3518 * @irq: interrupt number
3519 * @data: pointer to a network interface device structure
3520 **/
3521static irqreturn_t igb_intr(int irq, void *data)
3522{
3523 struct net_device *netdev = data;
3524 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3525 struct e1000_hw *hw = &adapter->hw;
3526 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3527 * need for the IMC write */
3528 u32 icr = rd32(E1000_ICR);
3529 u32 eicr = 0;
3530 if (!icr)
3531 return IRQ_NONE; /* Not our interrupt */
3532
6eb5a7f1 3533 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3534
3535 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3536 * not set, then the adapter didn't send an interrupt */
3537 if (!(icr & E1000_ICR_INT_ASSERTED))
3538 return IRQ_NONE;
3539
3540 eicr = rd32(E1000_EICR);
3541
3542 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3543 hw->mac.get_link_status = 1;
3544 /* guard against interrupt when we're going down */
3545 if (!test_bit(__IGB_DOWN, &adapter->state))
3546 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3547 }
3548
288379f0 3549 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3550
3551 return IRQ_HANDLED;
3552}
3553
3554/**
661086df
PWJ		 3555 * igb_poll - NAPI Rx polling callback
3556 * @napi: napi polling structure
3557 * @budget: count of how many packets we should handle
9d5c8243 3558 **/
661086df 3559static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3560{
661086df
PWJ		 3561 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3562 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3563 struct net_device *netdev = adapter->netdev;
661086df 3564 int tx_clean_complete, work_done = 0;
9d5c8243 3565
661086df 3566 /* this poll routine only supports one tx and one rx queue */
421e02f0 3567#ifdef CONFIG_IGB_DCA
7dfc16fa 3568 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3569 igb_update_tx_dca(&adapter->tx_ring[0]);
3570#endif
661086df 3571 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3572
421e02f0 3573#ifdef CONFIG_IGB_DCA
7dfc16fa 3574 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3575 igb_update_rx_dca(&adapter->rx_ring[0]);
3576#endif
661086df 3577 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3578
3579 /* If no Tx and not enough Rx work done, exit the polling mode */
3580 if ((tx_clean_complete && (work_done < budget)) ||
3581 !netif_running(netdev)) {
9d5c8243 3582 if (adapter->itr_setting & 3)
6eb5a7f1 3583 igb_set_itr(adapter);
288379f0 3584 napi_complete(napi);
9d5c8243
AK		 3585 if (!test_bit(__IGB_DOWN, &adapter->state))
3586 igb_irq_enable(adapter);
3587 return 0;
3588 }
3589
3590 return 1;
3591}
3592
3593static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3594{
3595 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3596 struct igb_adapter *adapter = rx_ring->adapter;
3597 struct e1000_hw *hw = &adapter->hw;
3598 struct net_device *netdev = adapter->netdev;
3599 int work_done = 0;
3600
421e02f0 3601#ifdef CONFIG_IGB_DCA
7dfc16fa 3602 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3603 igb_update_rx_dca(rx_ring);
3604#endif
3b644cf6 3605 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3606
3607
3608 /* If not enough Rx work done, exit the polling mode */
3609 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3610 napi_complete(napi);
9d5c8243 3611
6eb5a7f1
AD		 3612 if (adapter->itr_setting & 3) {
3613 if (adapter->num_rx_queues == 1)
3614 igb_set_itr(adapter);
3615 else
3616 igb_update_ring_itr(rx_ring);
9d5c8243 3617 }
844290e5
PW		 3618
3619 if (!test_bit(__IGB_DOWN, &adapter->state))
3620 wr32(E1000_EIMS, rx_ring->eims_value);
3621
9d5c8243
AK		 3622 return 0;
3623 }
3624
3625 return 1;
3626}
6d8126f9 3627
9d5c8243
AK		 3628/**
3629 * igb_clean_tx_irq - Reclaim resources after transmit completes
3630 * @adapter: board private structure
3631 * returns true if ring is completely cleaned
3632 **/
3b644cf6 3633static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3634{
3b644cf6 3635 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3636 struct net_device *netdev = adapter->netdev;
0e014cb1 3637 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3638 struct igb_buffer *buffer_info;
3639 struct sk_buff *skb;
0e014cb1 3640 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3641 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3642 unsigned int i, eop, count = 0;
3643 bool cleaned = false;
9d5c8243 3644
9d5c8243 3645 i = tx_ring->next_to_clean;
0e014cb1
AD		 3646 eop = tx_ring->buffer_info[i].next_to_watch;
3647 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3648
3649 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3650 (count < tx_ring->count)) {
3651 for (cleaned = false; !cleaned; count++) {
3652 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3653 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3654 cleaned = (i == eop);
9d5c8243
AK		 3655 skb = buffer_info->skb;
3656
3657 if (skb) {
3658 unsigned int segs, bytecount;
3659 /* gso_segs is currently only valid for tcp */
3660 segs = skb_shinfo(skb)->gso_segs ?: 1;
3661 /* multiply data chunks by size of headers */
3662 bytecount = ((segs - 1) * skb_headlen(skb)) +
3663 skb->len;
3664 total_packets += segs;
3665 total_bytes += bytecount;
3666 }
3667
3668 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3669 tx_desc->wb.status = 0;
9d5c8243
AK		 3670
3671 i++;
3672 if (i == tx_ring->count)
3673 i = 0;
9d5c8243 3674 }
0e014cb1
AD		 3675
3676 eop = tx_ring->buffer_info[i].next_to_watch;
3677 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3678 }
3679
9d5c8243
AK		 3680 tx_ring->next_to_clean = i;
3681
fc7d345d 3682 if (unlikely(count &&
9d5c8243
AK		 3683 netif_carrier_ok(netdev) &&
3684 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3685 /* Make sure that anybody stopping the queue after this
3686 * sees the new next_to_clean.
3687 */
3688 smp_mb();
661086df
PWJ		 3689 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3690 !(test_bit(__IGB_DOWN, &adapter->state))) {
3691 netif_wake_subqueue(netdev, tx_ring->queue_index);
3692 ++adapter->restart_queue;
3693 }
9d5c8243
AK		 3694 }
3695
3696 if (tx_ring->detect_tx_hung) {
3697 /* Detect a transmit hang in hardware, this serializes the
3698 * check with the clearing of time_stamp and movement of i */
3699 tx_ring->detect_tx_hung = false;
3700 if (tx_ring->buffer_info[i].time_stamp &&
3701 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3702 (adapter->tx_timeout_factor * HZ))
3703 && !(rd32(E1000_STATUS) &
3704 E1000_STATUS_TXOFF)) {
3705
9d5c8243
AK		 3706 /* detected Tx unit hang */
3707 dev_err(&adapter->pdev->dev,
3708 "Detected Tx Unit Hang\n"
2d064c06 3709 " Tx Queue <%d>\n"
9d5c8243
AK		 3710 " TDH <%x>\n"
3711 " TDT <%x>\n"
3712 " next_to_use <%x>\n"
3713 " next_to_clean <%x>\n"
9d5c8243
AK		 3714 "buffer_info[next_to_clean]\n"
3715 " time_stamp <%lx>\n"
0e014cb1 3716 " next_to_watch <%x>\n"
9d5c8243
AK		 3717 " jiffies <%lx>\n"
3718 " desc.status <%x>\n",
2d064c06 3719 tx_ring->queue_index,
9d5c8243
AK		 3720 readl(adapter->hw.hw_addr + tx_ring->head),
3721 readl(adapter->hw.hw_addr + tx_ring->tail),
3722 tx_ring->next_to_use,
3723 tx_ring->next_to_clean,
9d5c8243 3724 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3725 eop,
9d5c8243 3726 jiffies,
0e014cb1 3727 eop_desc->wb.status);
661086df 3728 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3729 }
3730 }
3731 tx_ring->total_bytes += total_bytes;
3732 tx_ring->total_packets += total_packets;
e21ed353
AD		 3733 tx_ring->tx_stats.bytes += total_bytes;
3734 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3735 adapter->net_stats.tx_bytes += total_bytes;
3736 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3737 return (count < tx_ring->count);
9d5c8243
AK		 3738}
3739
9d5c8243
AK		 3740/**
3741 * igb_receive_skb - helper function to handle rx indications
d3352520 3742 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3743 * @status: descriptor status field as written by hardware
3744 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3745 * @skb: pointer to sk_buff to be indicated to stack
3746 **/
d3352520
AD		 3747static void igb_receive_skb(struct igb_ring *ring, u8 status,
3748 union e1000_adv_rx_desc * rx_desc,
3749 struct sk_buff *skb)
3750{
3751 struct igb_adapter * adapter = ring->adapter;
3752 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3753
0c8dfc83 3754 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3755 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3756 if (vlan_extracted)
5c0999b7
HX		 3757 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3758 le16_to_cpu(rx_desc->wb.upper.vlan),
3759 skb);
d3352520 3760 else
5c0999b7 3761 napi_gro_receive(&ring->napi, skb);
d3352520 3762 } else {
d3352520
AD		 3763 if (vlan_extracted)
3764 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3765 le16_to_cpu(rx_desc->wb.upper.vlan));
3766 else
d3352520 3767 netif_receive_skb(skb);
d3352520 3768 }
9d5c8243
AK		 3769}
3770
3771
3772static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3773 u32 status_err, struct sk_buff *skb)
3774{
3775 skb->ip_summed = CHECKSUM_NONE;
3776
3777 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3778 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3779 return;
3780 /* TCP/UDP checksum error bit is set */
3781 if (status_err &
3782 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3783 /* let the stack verify checksum errors */
3784 adapter->hw_csum_err++;
3785 return;
3786 }
3787 /* It must be a TCP or UDP packet with a valid checksum */
3788 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3789 skb->ip_summed = CHECKSUM_UNNECESSARY;
3790
3791 adapter->hw_csum_good++;
3792}
3793
3b644cf6
MW		 3794static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3795 int *work_done, int budget)
9d5c8243 3796{
3b644cf6 3797 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3798 struct net_device *netdev = adapter->netdev;
3799 struct pci_dev *pdev = adapter->pdev;
3800 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3801 struct igb_buffer *buffer_info , *next_buffer;
3802 struct sk_buff *skb;
bf36c1a0 3803 unsigned int i;
9d5c8243
AK		 3804 u32 length, hlen, staterr;
3805 bool cleaned = false;
3806 int cleaned_count = 0;
3807 unsigned int total_bytes = 0, total_packets = 0;
3808
3809 i = rx_ring->next_to_clean;
3810 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3811 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3812
3813 while (staterr & E1000_RXD_STAT_DD) {
3814 if (*work_done >= budget)
3815 break;
3816 (*work_done)++;
3817 buffer_info = &rx_ring->buffer_info[i];
3818
3819 /* HW will not DMA in data larger than the given buffer, even
3820 * if it parses the (NFS, of course) header to be larger. In
3821 * that case, it fills the header buffer and spills the rest
3822 * into the page.
3823 */
7deb07b1
AV		 3824 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3825 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3826 if (hlen > adapter->rx_ps_hdr_size)
3827 hlen = adapter->rx_ps_hdr_size;
3828
3829 length = le16_to_cpu(rx_desc->wb.upper.length);
3830 cleaned = true;
3831 cleaned_count++;
3832
bf36c1a0
AD		 3833 skb = buffer_info->skb;
3834 prefetch(skb->data - NET_IP_ALIGN);
3835 buffer_info->skb = NULL;
3836 if (!adapter->rx_ps_hdr_size) {
3837 pci_unmap_single(pdev, buffer_info->dma,
3838 adapter->rx_buffer_len +
3839 NET_IP_ALIGN,
3840 PCI_DMA_FROMDEVICE);
3841 skb_put(skb, length);
3842 goto send_up;
9d5c8243
AK		 3843 }
3844
bf36c1a0
AD		 3845 if (!skb_shinfo(skb)->nr_frags) {
3846 pci_unmap_single(pdev, buffer_info->dma,
3847 adapter->rx_ps_hdr_size +
3848 NET_IP_ALIGN,
3849 PCI_DMA_FROMDEVICE);
3850 skb_put(skb, hlen);
3851 }
3852
3853 if (length) {
9d5c8243 3854 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3855 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3856 buffer_info->page_dma = 0;
bf36c1a0
AD		 3857
3858 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3859 buffer_info->page,
3860 buffer_info->page_offset,
3861 length);
3862
3863 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3864 (page_count(buffer_info->page) != 1))
3865 buffer_info->page = NULL;
3866 else
3867 get_page(buffer_info->page);
9d5c8243
AK		 3868
3869 skb->len += length;
3870 skb->data_len += length;
9d5c8243 3871
bf36c1a0 3872 skb->truesize += length;
9d5c8243
AK		 3873 }
3874send_up:
9d5c8243
AK		 3875 i++;
3876 if (i == rx_ring->count)
3877 i = 0;
3878 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3879 prefetch(next_rxd);
3880 next_buffer = &rx_ring->buffer_info[i];
3881
bf36c1a0 3882 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3883 buffer_info->skb = next_buffer->skb;
3884 buffer_info->dma = next_buffer->dma;
3885 next_buffer->skb = skb;
3886 next_buffer->dma = 0;
bf36c1a0
AD		 3887 goto next_desc;
3888 }
3889
9d5c8243
AK		 3890 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3891 dev_kfree_skb_irq(skb);
3892 goto next_desc;
3893 }
9d5c8243
AK		 3894
3895 total_bytes += skb->len;
3896 total_packets++;
3897
3898 igb_rx_checksum_adv(adapter, staterr, skb);
3899
3900 skb->protocol = eth_type_trans(skb, netdev);
3901
d3352520 3902 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3903
9d5c8243
AK		 3904next_desc:
3905 rx_desc->wb.upper.status_error = 0;
3906
3907 /* return some buffers to hardware, one at a time is too slow */
3908 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3909 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3910 cleaned_count = 0;
3911 }
3912
3913 /* use prefetched values */
3914 rx_desc = next_rxd;
3915 buffer_info = next_buffer;
3916
3917 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3918 }
bf36c1a0 3919
9d5c8243
AK		 3920 rx_ring->next_to_clean = i;
3921 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3922
3923 if (cleaned_count)
3b644cf6 3924 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3925
3926 rx_ring->total_packets += total_packets;
3927 rx_ring->total_bytes += total_bytes;
3928 rx_ring->rx_stats.packets += total_packets;
3929 rx_ring->rx_stats.bytes += total_bytes;
3930 adapter->net_stats.rx_bytes += total_bytes;
3931 adapter->net_stats.rx_packets += total_packets;
3932 return cleaned;
3933}
3934
3935
3936/**
3937 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3938 * @adapter: address of board private structure
3939 **/
3b644cf6 3940static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3941 int cleaned_count)
3942{
3b644cf6 3943 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3944 struct net_device *netdev = adapter->netdev;
3945 struct pci_dev *pdev = adapter->pdev;
3946 union e1000_adv_rx_desc *rx_desc;
3947 struct igb_buffer *buffer_info;
3948 struct sk_buff *skb;
3949 unsigned int i;
3950
3951 i = rx_ring->next_to_use;
3952 buffer_info = &rx_ring->buffer_info[i];
3953
3954 while (cleaned_count--) {
3955 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3956
bf36c1a0 3957 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3958 if (!buffer_info->page) {
bf36c1a0
AD		 3959 buffer_info->page = alloc_page(GFP_ATOMIC);
3960 if (!buffer_info->page) {
3961 adapter->alloc_rx_buff_failed++;
3962 goto no_buffers;
3963 }
3964 buffer_info->page_offset = 0;
3965 } else {
3966 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3967 }
3968 buffer_info->page_dma =
3969 pci_map_page(pdev,
3970 buffer_info->page,
bf36c1a0
AD		 3971 buffer_info->page_offset,
3972 PAGE_SIZE / 2,
9d5c8243
AK		 3973 PCI_DMA_FROMDEVICE);
3974 }
3975
3976 if (!buffer_info->skb) {
3977 int bufsz;
3978
3979 if (adapter->rx_ps_hdr_size)
3980 bufsz = adapter->rx_ps_hdr_size;
3981 else
3982 bufsz = adapter->rx_buffer_len;
3983 bufsz += NET_IP_ALIGN;
3984 skb = netdev_alloc_skb(netdev, bufsz);
3985
3986 if (!skb) {
3987 adapter->alloc_rx_buff_failed++;
3988 goto no_buffers;
3989 }
3990
3991 /* Make buffer alignment 2 beyond a 16 byte boundary
3992 * this will result in a 16 byte aligned IP header after
3993 * the 14 byte MAC header is removed
3994 */
3995 skb_reserve(skb, NET_IP_ALIGN);
3996
3997 buffer_info->skb = skb;
3998 buffer_info->dma = pci_map_single(pdev, skb->data,
3999 bufsz,
4000 PCI_DMA_FROMDEVICE);
4001
4002 }
4003 /* Refresh the desc even if buffer_addrs didn't change because
4004 * each write-back erases this info. */
4005 if (adapter->rx_ps_hdr_size) {
4006 rx_desc->read.pkt_addr =
4007 cpu_to_le64(buffer_info->page_dma);
4008 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4009 } else {
4010 rx_desc->read.pkt_addr =
4011 cpu_to_le64(buffer_info->dma);
4012 rx_desc->read.hdr_addr = 0;
4013 }
4014
4015 i++;
4016 if (i == rx_ring->count)
4017 i = 0;
4018 buffer_info = &rx_ring->buffer_info[i];
4019 }
4020
4021no_buffers:
4022 if (rx_ring->next_to_use != i) {
4023 rx_ring->next_to_use = i;
4024 if (i == 0)
4025 i = (rx_ring->count - 1);
4026 else
4027 i--;
4028
4029 /* Force memory writes to complete before letting h/w
4030 * know there are new descriptors to fetch. (Only
4031 * applicable for weak-ordered memory model archs,
4032 * such as IA-64). */
4033 wmb();
4034 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4035 }
4036}
4037
4038/**
4039 * igb_mii_ioctl -
4040 * @netdev:
4041 * @ifreq:
4042 * @cmd:
4043 **/
4044static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4045{
4046 struct igb_adapter *adapter = netdev_priv(netdev);
4047 struct mii_ioctl_data *data = if_mii(ifr);
4048
4049 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4050 return -EOPNOTSUPP;
4051
4052 switch (cmd) {
4053 case SIOCGMIIPHY:
4054 data->phy_id = adapter->hw.phy.addr;
4055 break;
4056 case SIOCGMIIREG:
4057 if (!capable(CAP_NET_ADMIN))
4058 return -EPERM;
f5f4cf08
AD		 4059 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4060 &data->val_out))
9d5c8243
AK		 4061 return -EIO;
4062 break;
4063 case SIOCSMIIREG:
4064 default:
4065 return -EOPNOTSUPP;
4066 }
4067 return 0;
4068}
4069
4070/**
4071 * igb_ioctl -
4072 * @netdev:
4073 * @ifreq:
4074 * @cmd:
4075 **/
4076static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4077{
4078 switch (cmd) {
4079 case SIOCGMIIPHY:
4080 case SIOCGMIIREG:
4081 case SIOCSMIIREG:
4082 return igb_mii_ioctl(netdev, ifr, cmd);
4083 default:
4084 return -EOPNOTSUPP;
4085 }
4086}
4087
4088static void igb_vlan_rx_register(struct net_device *netdev,
4089 struct vlan_group *grp)
4090{
4091 struct igb_adapter *adapter = netdev_priv(netdev);
4092 struct e1000_hw *hw = &adapter->hw;
4093 u32 ctrl, rctl;
4094
4095 igb_irq_disable(adapter);
4096 adapter->vlgrp = grp;
4097
4098 if (grp) {
4099 /* enable VLAN tag insert/strip */
4100 ctrl = rd32(E1000_CTRL);
4101 ctrl |= E1000_CTRL_VME;
4102 wr32(E1000_CTRL, ctrl);
4103
4104 /* enable VLAN receive filtering */
4105 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4106 rctl &= ~E1000_RCTL_CFIEN;
4107 wr32(E1000_RCTL, rctl);
4108 igb_update_mng_vlan(adapter);
4109 wr32(E1000_RLPML,
4110 adapter->max_frame_size + VLAN_TAG_SIZE);
4111 } else {
4112 /* disable VLAN tag insert/strip */
4113 ctrl = rd32(E1000_CTRL);
4114 ctrl &= ~E1000_CTRL_VME;
4115 wr32(E1000_CTRL, ctrl);
4116
9d5c8243
AK		 4117 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4118 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4119 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4120 }
4121 wr32(E1000_RLPML,
4122 adapter->max_frame_size);
4123 }
4124
4125 if (!test_bit(__IGB_DOWN, &adapter->state))
4126 igb_irq_enable(adapter);
4127}
4128
4129static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4130{
4131 struct igb_adapter *adapter = netdev_priv(netdev);
4132 struct e1000_hw *hw = &adapter->hw;
4133 u32 vfta, index;
4134
4135 if ((adapter->hw.mng_cookie.status &
4136 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4137 (vid == adapter->mng_vlan_id))
4138 return;
4139 /* add VID to filter table */
4140 index = (vid >> 5) & 0x7F;
4141 vfta = array_rd32(E1000_VFTA, index);
4142 vfta |= (1 << (vid & 0x1F));
4143 igb_write_vfta(&adapter->hw, index, vfta);
4144}
4145
4146static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4147{
4148 struct igb_adapter *adapter = netdev_priv(netdev);
4149 struct e1000_hw *hw = &adapter->hw;
4150 u32 vfta, index;
4151
4152 igb_irq_disable(adapter);
4153 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4154
4155 if (!test_bit(__IGB_DOWN, &adapter->state))
4156 igb_irq_enable(adapter);
4157
4158 if ((adapter->hw.mng_cookie.status &
4159 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4160 (vid == adapter->mng_vlan_id)) {
4161 /* release control to f/w */
4162 igb_release_hw_control(adapter);
4163 return;
4164 }
4165
4166 /* remove VID from filter table */
4167 index = (vid >> 5) & 0x7F;
4168 vfta = array_rd32(E1000_VFTA, index);
4169 vfta &= ~(1 << (vid & 0x1F));
4170 igb_write_vfta(&adapter->hw, index, vfta);
4171}
4172
4173static void igb_restore_vlan(struct igb_adapter *adapter)
4174{
4175 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4176
4177 if (adapter->vlgrp) {
4178 u16 vid;
4179 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4180 if (!vlan_group_get_device(adapter->vlgrp, vid))
4181 continue;
4182 igb_vlan_rx_add_vid(adapter->netdev, vid);
4183 }
4184 }
4185}
4186
4187int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4188{
4189 struct e1000_mac_info *mac = &adapter->hw.mac;
4190
4191 mac->autoneg = 0;
4192
4193 /* Fiber NICs only allow 1000 gbps Full duplex */
4194 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4195 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4196 dev_err(&adapter->pdev->dev,
4197 "Unsupported Speed/Duplex configuration\n");
4198 return -EINVAL;
4199 }
4200
4201 switch (spddplx) {
4202 case SPEED_10 + DUPLEX_HALF:
4203 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4204 break;
4205 case SPEED_10 + DUPLEX_FULL:
4206 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4207 break;
4208 case SPEED_100 + DUPLEX_HALF:
4209 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4210 break;
4211 case SPEED_100 + DUPLEX_FULL:
4212 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4213 break;
4214 case SPEED_1000 + DUPLEX_FULL:
4215 mac->autoneg = 1;
4216 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4217 break;
4218 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4219 default:
4220 dev_err(&adapter->pdev->dev,
4221 "Unsupported Speed/Duplex configuration\n");
4222 return -EINVAL;
4223 }
4224 return 0;
4225}
4226
4227
4228static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4229{
4230 struct net_device *netdev = pci_get_drvdata(pdev);
4231 struct igb_adapter *adapter = netdev_priv(netdev);
4232 struct e1000_hw *hw = &adapter->hw;
2d064c06 4233 u32 ctrl, rctl, status;
9d5c8243
AK		 4234 u32 wufc = adapter->wol;
4235#ifdef CONFIG_PM
4236 int retval = 0;
4237#endif
4238
4239 netif_device_detach(netdev);
4240
a88f10ec
AD		 4241 if (netif_running(netdev))
4242 igb_close(netdev);
4243
4244 igb_reset_interrupt_capability(adapter);
4245
4246 igb_free_queues(adapter);
9d5c8243
AK		 4247
4248#ifdef CONFIG_PM
4249 retval = pci_save_state(pdev);
4250 if (retval)
4251 return retval;
4252#endif
4253
4254 status = rd32(E1000_STATUS);
4255 if (status & E1000_STATUS_LU)
4256 wufc &= ~E1000_WUFC_LNKC;
4257
4258 if (wufc) {
4259 igb_setup_rctl(adapter);
4260 igb_set_multi(netdev);
4261
4262 /* turn on all-multi mode if wake on multicast is enabled */
4263 if (wufc & E1000_WUFC_MC) {
4264 rctl = rd32(E1000_RCTL);
4265 rctl |= E1000_RCTL_MPE;
4266 wr32(E1000_RCTL, rctl);
4267 }
4268
4269 ctrl = rd32(E1000_CTRL);
4270 /* advertise wake from D3Cold */
4271 #define E1000_CTRL_ADVD3WUC 0x00100000
4272 /* phy power management enable */
4273 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4274 ctrl |= E1000_CTRL_ADVD3WUC;
4275 wr32(E1000_CTRL, ctrl);
4276
9d5c8243
AK		 4277 /* Allow time for pending master requests to run */
4278 igb_disable_pcie_master(&adapter->hw);
4279
4280 wr32(E1000_WUC, E1000_WUC_PME_EN);
4281 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4282 } else {
4283 wr32(E1000_WUC, 0);
4284 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4285 }
4286
2d064c06
AD		 4287 /* make sure adapter isn't asleep if manageability/wol is enabled */
4288 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4289 pci_enable_wake(pdev, PCI_D3hot, 1);
4290 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4291 } else {
4292 igb_shutdown_fiber_serdes_link_82575(hw);
4293 pci_enable_wake(pdev, PCI_D3hot, 0);
4294 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4295 }
4296
4297 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4298 * would have already happened in close and is redundant. */
4299 igb_release_hw_control(adapter);
4300
4301 pci_disable_device(pdev);
4302
4303 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4304
4305 return 0;
4306}
4307
4308#ifdef CONFIG_PM
4309static int igb_resume(struct pci_dev *pdev)
4310{
4311 struct net_device *netdev = pci_get_drvdata(pdev);
4312 struct igb_adapter *adapter = netdev_priv(netdev);
4313 struct e1000_hw *hw = &adapter->hw;
4314 u32 err;
4315
4316 pci_set_power_state(pdev, PCI_D0);
4317 pci_restore_state(pdev);
42bfd33a
TI		 4318
4319 if (adapter->need_ioport)
4320 err = pci_enable_device(pdev);
4321 else
4322 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4323 if (err) {
4324 dev_err(&pdev->dev,
4325 "igb: Cannot enable PCI device from suspend\n");
4326 return err;
4327 }
4328 pci_set_master(pdev);
4329
4330 pci_enable_wake(pdev, PCI_D3hot, 0);
4331 pci_enable_wake(pdev, PCI_D3cold, 0);
4332
a88f10ec
AD		 4333 igb_set_interrupt_capability(adapter);
4334
4335 if (igb_alloc_queues(adapter)) {
4336 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4337 return -ENOMEM;
9d5c8243
AK		 4338 }
4339
4340 /* e1000_power_up_phy(adapter); */
4341
4342 igb_reset(adapter);
4343 wr32(E1000_WUS, ~0);
4344
a88f10ec
AD		 4345 if (netif_running(netdev)) {
4346 err = igb_open(netdev);
4347 if (err)
4348 return err;
4349 }
9d5c8243
AK		 4350
4351 netif_device_attach(netdev);
4352
4353 /* let the f/w know that the h/w is now under the control of the
4354 * driver. */
4355 igb_get_hw_control(adapter);
4356
4357 return 0;
4358}
4359#endif
4360
4361static void igb_shutdown(struct pci_dev *pdev)
4362{
4363 igb_suspend(pdev, PMSG_SUSPEND);
4364}
4365
4366#ifdef CONFIG_NET_POLL_CONTROLLER
4367/*
4368 * Polling 'interrupt' - used by things like netconsole to send skbs
4369 * without having to re-enable interrupts. It's not called while
4370 * the interrupt routine is executing.
4371 */
4372static void igb_netpoll(struct net_device *netdev)
4373{
4374 struct igb_adapter *adapter = netdev_priv(netdev);
4375 int i;
4376 int work_done = 0;
4377
4378 igb_irq_disable(adapter);
7dfc16fa
AD		 4379 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4380
9d5c8243 4381 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4382 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4383
4384 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4385 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4386 &work_done,
4387 adapter->rx_ring[i].napi.weight);
4388
7dfc16fa 4389 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4390 igb_irq_enable(adapter);
4391}
4392#endif /* CONFIG_NET_POLL_CONTROLLER */
4393
4394/**
4395 * igb_io_error_detected - called when PCI error is detected
4396 * @pdev: Pointer to PCI device
4397 * @state: The current pci connection state
4398 *
4399 * This function is called after a PCI bus error affecting
4400 * this device has been detected.
4401 */
4402static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4403 pci_channel_state_t state)
4404{
4405 struct net_device *netdev = pci_get_drvdata(pdev);
4406 struct igb_adapter *adapter = netdev_priv(netdev);
4407
4408 netif_device_detach(netdev);
4409
4410 if (netif_running(netdev))
4411 igb_down(adapter);
4412 pci_disable_device(pdev);
4413
4414 /* Request a slot slot reset. */
4415 return PCI_ERS_RESULT_NEED_RESET;
4416}
4417
4418/**
4419 * igb_io_slot_reset - called after the pci bus has been reset.
4420 * @pdev: Pointer to PCI device
4421 *
4422 * Restart the card from scratch, as if from a cold-boot. Implementation
4423 * resembles the first-half of the igb_resume routine.
4424 */
4425static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4426{
4427 struct net_device *netdev = pci_get_drvdata(pdev);
4428 struct igb_adapter *adapter = netdev_priv(netdev);
4429 struct e1000_hw *hw = &adapter->hw;
40a914fa 4430 pci_ers_result_t result;
42bfd33a 4431 int err;
9d5c8243 4432
42bfd33a
TI		 4433 if (adapter->need_ioport)
4434 err = pci_enable_device(pdev);
4435 else
4436 err = pci_enable_device_mem(pdev);
40a914fa 4437
42bfd33a 4438 if (err) {
9d5c8243
AK		 4439 dev_err(&pdev->dev,
4440 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4441 result = PCI_ERS_RESULT_DISCONNECT;
4442 } else {
4443 pci_set_master(pdev);
4444 pci_restore_state(pdev);
9d5c8243 4445
40a914fa
AD		 4446 pci_enable_wake(pdev, PCI_D3hot, 0);
4447 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4448
40a914fa
AD		 4449 igb_reset(adapter);
4450 wr32(E1000_WUS, ~0);
4451 result = PCI_ERS_RESULT_RECOVERED;
4452 }
9d5c8243 4453
ea943d41
JK		 4454 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4455 if (err) {
4456 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4457 "failed 0x%0x\n", err);
4458 /* non-fatal, continue */
4459 }
40a914fa
AD		 4460
4461 return result;
9d5c8243
AK		 4462}
4463
4464/**
4465 * igb_io_resume - called when traffic can start flowing again.
4466 * @pdev: Pointer to PCI device
4467 *
4468 * This callback is called when the error recovery driver tells us that
4469 * its OK to resume normal operation. Implementation resembles the
4470 * second-half of the igb_resume routine.
4471 */
4472static void igb_io_resume(struct pci_dev *pdev)
4473{
4474 struct net_device *netdev = pci_get_drvdata(pdev);
4475 struct igb_adapter *adapter = netdev_priv(netdev);
4476
9d5c8243
AK		 4477 if (netif_running(netdev)) {
4478 if (igb_up(adapter)) {
4479 dev_err(&pdev->dev, "igb_up failed after reset\n");
4480 return;
4481 }
4482 }
4483
4484 netif_device_attach(netdev);
4485
4486 /* let the f/w know that the h/w is now under the control of the
4487 * driver. */
4488 igb_get_hw_control(adapter);
9d5c8243
AK		 4489}
4490
4491/* igb_main.c */
Clone of davem's net-next-2.6 tree