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Commit | Line | Data |
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0bbaf069 | 1 | /* |
1da177e4 LT |
2 | * drivers/net/gianfar.c |
3 | * | |
4 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
5 | * This driver is designed for the non-CPM ethernet controllers |
6 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
7 | * Based on 8260_io/fcc_enet.c |
8 | * | |
9 | * Author: Andy Fleming | |
4c8d3d99 | 10 | * Maintainer: Kumar Gala |
1da177e4 | 11 | * |
e8a2b6a4 | 12 | * Copyright (c) 2002-2006 Freescale Semiconductor, Inc. |
538cc7ee | 13 | * Copyright (c) 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
1da177e4 | 64 | #include <linux/kernel.h> |
1da177e4 LT |
65 | #include <linux/string.h> |
66 | #include <linux/errno.h> | |
bb40dcbb | 67 | #include <linux/unistd.h> |
1da177e4 LT |
68 | #include <linux/slab.h> |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/init.h> | |
71 | #include <linux/delay.h> | |
72 | #include <linux/netdevice.h> | |
73 | #include <linux/etherdevice.h> | |
74 | #include <linux/skbuff.h> | |
0bbaf069 | 75 | #include <linux/if_vlan.h> |
1da177e4 LT |
76 | #include <linux/spinlock.h> |
77 | #include <linux/mm.h> | |
fe192a49 | 78 | #include <linux/of_mdio.h> |
b31a1d8b | 79 | #include <linux/of_platform.h> |
0bbaf069 KG |
80 | #include <linux/ip.h> |
81 | #include <linux/tcp.h> | |
82 | #include <linux/udp.h> | |
9c07b884 | 83 | #include <linux/in.h> |
1da177e4 LT |
84 | |
85 | #include <asm/io.h> | |
86 | #include <asm/irq.h> | |
87 | #include <asm/uaccess.h> | |
88 | #include <linux/module.h> | |
1da177e4 LT |
89 | #include <linux/dma-mapping.h> |
90 | #include <linux/crc32.h> | |
bb40dcbb AF |
91 | #include <linux/mii.h> |
92 | #include <linux/phy.h> | |
b31a1d8b AF |
93 | #include <linux/phy_fixed.h> |
94 | #include <linux/of.h> | |
1da177e4 LT |
95 | |
96 | #include "gianfar.h" | |
1577ecef | 97 | #include "fsl_pq_mdio.h" |
1da177e4 LT |
98 | |
99 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 LT |
100 | #undef BRIEF_GFAR_ERRORS |
101 | #undef VERBOSE_GFAR_ERRORS | |
102 | ||
1da177e4 | 103 | const char gfar_driver_name[] = "Gianfar Ethernet"; |
7f7f5316 | 104 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 105 | |
1da177e4 LT |
106 | static int gfar_enet_open(struct net_device *dev); |
107 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 108 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
109 | static void gfar_timeout(struct net_device *dev); |
110 | static int gfar_close(struct net_device *dev); | |
815b97c6 AF |
111 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
112 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, | |
113 | struct sk_buff *skb); | |
1da177e4 LT |
114 | static int gfar_set_mac_address(struct net_device *dev); |
115 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
116 | static irqreturn_t gfar_error(int irq, void *dev_id); |
117 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
118 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
119 | static void adjust_link(struct net_device *dev); |
120 | static void init_registers(struct net_device *dev); | |
121 | static int init_phy(struct net_device *dev); | |
b31a1d8b AF |
122 | static int gfar_probe(struct of_device *ofdev, |
123 | const struct of_device_id *match); | |
124 | static int gfar_remove(struct of_device *ofdev); | |
bb40dcbb | 125 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
126 | static void gfar_set_multi(struct net_device *dev); |
127 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 128 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 129 | static int gfar_poll(struct napi_struct *napi, int budget); |
f2d71c2d VW |
130 | #ifdef CONFIG_NET_POLL_CONTROLLER |
131 | static void gfar_netpoll(struct net_device *dev); | |
132 | #endif | |
0bbaf069 | 133 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit); |
f162b9d5 | 134 | static int gfar_clean_tx_ring(struct net_device *dev); |
2c2db48a DH |
135 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
136 | int amount_pull); | |
0bbaf069 KG |
137 | static void gfar_vlan_rx_register(struct net_device *netdev, |
138 | struct vlan_group *grp); | |
7f7f5316 | 139 | void gfar_halt(struct net_device *dev); |
d87eb127 | 140 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
141 | void gfar_start(struct net_device *dev); |
142 | static void gfar_clear_exact_match(struct net_device *dev); | |
143 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr); | |
26ccfc37 | 144 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 145 | |
1da177e4 LT |
146 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
147 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
148 | MODULE_LICENSE("GPL"); | |
149 | ||
26ccfc37 AF |
150 | static const struct net_device_ops gfar_netdev_ops = { |
151 | .ndo_open = gfar_enet_open, | |
152 | .ndo_start_xmit = gfar_start_xmit, | |
153 | .ndo_stop = gfar_close, | |
154 | .ndo_change_mtu = gfar_change_mtu, | |
155 | .ndo_set_multicast_list = gfar_set_multi, | |
156 | .ndo_tx_timeout = gfar_timeout, | |
157 | .ndo_do_ioctl = gfar_ioctl, | |
158 | .ndo_vlan_rx_register = gfar_vlan_rx_register, | |
240c102d BH |
159 | .ndo_set_mac_address = eth_mac_addr, |
160 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
161 | #ifdef CONFIG_NET_POLL_CONTROLLER |
162 | .ndo_poll_controller = gfar_netpoll, | |
163 | #endif | |
164 | }; | |
165 | ||
7f7f5316 AF |
166 | /* Returns 1 if incoming frames use an FCB */ |
167 | static inline int gfar_uses_fcb(struct gfar_private *priv) | |
0bbaf069 | 168 | { |
77ecaf2d | 169 | return priv->vlgrp || priv->rx_csum_enable; |
0bbaf069 | 170 | } |
bb40dcbb | 171 | |
b31a1d8b AF |
172 | static int gfar_of_init(struct net_device *dev) |
173 | { | |
b31a1d8b AF |
174 | const char *model; |
175 | const char *ctype; | |
176 | const void *mac_addr; | |
b31a1d8b AF |
177 | u64 addr, size; |
178 | int err = 0; | |
179 | struct gfar_private *priv = netdev_priv(dev); | |
180 | struct device_node *np = priv->node; | |
4d7902f2 AF |
181 | const u32 *stash; |
182 | const u32 *stash_len; | |
183 | const u32 *stash_idx; | |
b31a1d8b AF |
184 | |
185 | if (!np || !of_device_is_available(np)) | |
186 | return -ENODEV; | |
187 | ||
188 | /* get a pointer to the register memory */ | |
189 | addr = of_translate_address(np, of_get_address(np, 0, &size, NULL)); | |
190 | priv->regs = ioremap(addr, size); | |
191 | ||
192 | if (priv->regs == NULL) | |
193 | return -ENOMEM; | |
194 | ||
195 | priv->interruptTransmit = irq_of_parse_and_map(np, 0); | |
196 | ||
197 | model = of_get_property(np, "model", NULL); | |
198 | ||
199 | /* If we aren't the FEC we have multiple interrupts */ | |
200 | if (model && strcasecmp(model, "FEC")) { | |
201 | priv->interruptReceive = irq_of_parse_and_map(np, 1); | |
202 | ||
203 | priv->interruptError = irq_of_parse_and_map(np, 2); | |
204 | ||
205 | if (priv->interruptTransmit < 0 || | |
206 | priv->interruptReceive < 0 || | |
207 | priv->interruptError < 0) { | |
208 | err = -EINVAL; | |
209 | goto err_out; | |
210 | } | |
211 | } | |
212 | ||
4d7902f2 AF |
213 | stash = of_get_property(np, "bd-stash", NULL); |
214 | ||
215 | if(stash) { | |
216 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; | |
217 | priv->bd_stash_en = 1; | |
218 | } | |
219 | ||
220 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
221 | ||
222 | if (stash_len) | |
223 | priv->rx_stash_size = *stash_len; | |
224 | ||
225 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
226 | ||
227 | if (stash_idx) | |
228 | priv->rx_stash_index = *stash_idx; | |
229 | ||
230 | if (stash_len || stash_idx) | |
231 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
232 | ||
b31a1d8b AF |
233 | mac_addr = of_get_mac_address(np); |
234 | if (mac_addr) | |
235 | memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN); | |
236 | ||
237 | if (model && !strcasecmp(model, "TSEC")) | |
238 | priv->device_flags = | |
239 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
240 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
241 | FSL_GIANFAR_DEV_HAS_RMON | | |
242 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
243 | if (model && !strcasecmp(model, "eTSEC")) | |
244 | priv->device_flags = | |
245 | FSL_GIANFAR_DEV_HAS_GIGABIT | | |
246 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
247 | FSL_GIANFAR_DEV_HAS_RMON | | |
248 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
2c2db48a | 249 | FSL_GIANFAR_DEV_HAS_PADDING | |
b31a1d8b AF |
250 | FSL_GIANFAR_DEV_HAS_CSUM | |
251 | FSL_GIANFAR_DEV_HAS_VLAN | | |
252 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
253 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH; | |
254 | ||
255 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
256 | ||
257 | /* We only care about rgmii-id. The rest are autodetected */ | |
258 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
259 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
260 | else | |
261 | priv->interface = PHY_INTERFACE_MODE_MII; | |
262 | ||
263 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
264 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
265 | ||
fe192a49 | 266 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
267 | |
268 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 269 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
270 | |
271 | return 0; | |
272 | ||
273 | err_out: | |
274 | iounmap(priv->regs); | |
275 | return err; | |
276 | } | |
277 | ||
0faac9f7 CW |
278 | /* Ioctl MII Interface */ |
279 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
280 | { | |
281 | struct gfar_private *priv = netdev_priv(dev); | |
282 | ||
283 | if (!netif_running(dev)) | |
284 | return -EINVAL; | |
285 | ||
286 | if (!priv->phydev) | |
287 | return -ENODEV; | |
288 | ||
289 | return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); | |
290 | } | |
291 | ||
bb40dcbb AF |
292 | /* Set up the ethernet device structure, private data, |
293 | * and anything else we need before we start */ | |
b31a1d8b AF |
294 | static int gfar_probe(struct of_device *ofdev, |
295 | const struct of_device_id *match) | |
1da177e4 LT |
296 | { |
297 | u32 tempval; | |
298 | struct net_device *dev = NULL; | |
299 | struct gfar_private *priv = NULL; | |
c50a5d9a DH |
300 | int err = 0; |
301 | int len_devname; | |
1da177e4 LT |
302 | |
303 | /* Create an ethernet device instance */ | |
304 | dev = alloc_etherdev(sizeof (*priv)); | |
305 | ||
bb40dcbb | 306 | if (NULL == dev) |
1da177e4 LT |
307 | return -ENOMEM; |
308 | ||
309 | priv = netdev_priv(dev); | |
4826857f KG |
310 | priv->ndev = dev; |
311 | priv->ofdev = ofdev; | |
b31a1d8b | 312 | priv->node = ofdev->node; |
4826857f | 313 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 314 | |
b31a1d8b | 315 | err = gfar_of_init(dev); |
1da177e4 | 316 | |
b31a1d8b | 317 | if (err) |
1da177e4 | 318 | goto regs_fail; |
1da177e4 | 319 | |
fef6108d AF |
320 | spin_lock_init(&priv->txlock); |
321 | spin_lock_init(&priv->rxlock); | |
d87eb127 | 322 | spin_lock_init(&priv->bflock); |
ab939905 | 323 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 324 | |
b31a1d8b | 325 | dev_set_drvdata(&ofdev->dev, priv); |
1da177e4 LT |
326 | |
327 | /* Stop the DMA engine now, in case it was running before */ | |
328 | /* (The firmware could have used it, and left it running). */ | |
257d938a | 329 | gfar_halt(dev); |
1da177e4 LT |
330 | |
331 | /* Reset MAC layer */ | |
332 | gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); | |
333 | ||
b98ac702 AF |
334 | /* We need to delay at least 3 TX clocks */ |
335 | udelay(2); | |
336 | ||
1da177e4 LT |
337 | tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
338 | gfar_write(&priv->regs->maccfg1, tempval); | |
339 | ||
340 | /* Initialize MACCFG2. */ | |
341 | gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS); | |
342 | ||
343 | /* Initialize ECNTRL */ | |
344 | gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS); | |
345 | ||
1da177e4 LT |
346 | /* Set the dev->base_addr to the gfar reg region */ |
347 | dev->base_addr = (unsigned long) (priv->regs); | |
348 | ||
b31a1d8b | 349 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 LT |
350 | |
351 | /* Fill in the dev structure */ | |
1da177e4 | 352 | dev->watchdog_timeo = TX_TIMEOUT; |
bea3348e | 353 | netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT); |
1da177e4 | 354 | dev->mtu = 1500; |
1da177e4 | 355 | |
26ccfc37 | 356 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
357 | dev->ethtool_ops = &gfar_ethtool_ops; |
358 | ||
b31a1d8b | 359 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
0bbaf069 | 360 | priv->rx_csum_enable = 1; |
4669bc90 | 361 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA; |
0bbaf069 KG |
362 | } else |
363 | priv->rx_csum_enable = 0; | |
364 | ||
365 | priv->vlgrp = NULL; | |
1da177e4 | 366 | |
26ccfc37 | 367 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) |
0bbaf069 | 368 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; |
0bbaf069 | 369 | |
b31a1d8b | 370 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
371 | priv->extended_hash = 1; |
372 | priv->hash_width = 9; | |
373 | ||
374 | priv->hash_regs[0] = &priv->regs->igaddr0; | |
375 | priv->hash_regs[1] = &priv->regs->igaddr1; | |
376 | priv->hash_regs[2] = &priv->regs->igaddr2; | |
377 | priv->hash_regs[3] = &priv->regs->igaddr3; | |
378 | priv->hash_regs[4] = &priv->regs->igaddr4; | |
379 | priv->hash_regs[5] = &priv->regs->igaddr5; | |
380 | priv->hash_regs[6] = &priv->regs->igaddr6; | |
381 | priv->hash_regs[7] = &priv->regs->igaddr7; | |
382 | priv->hash_regs[8] = &priv->regs->gaddr0; | |
383 | priv->hash_regs[9] = &priv->regs->gaddr1; | |
384 | priv->hash_regs[10] = &priv->regs->gaddr2; | |
385 | priv->hash_regs[11] = &priv->regs->gaddr3; | |
386 | priv->hash_regs[12] = &priv->regs->gaddr4; | |
387 | priv->hash_regs[13] = &priv->regs->gaddr5; | |
388 | priv->hash_regs[14] = &priv->regs->gaddr6; | |
389 | priv->hash_regs[15] = &priv->regs->gaddr7; | |
390 | ||
391 | } else { | |
392 | priv->extended_hash = 0; | |
393 | priv->hash_width = 8; | |
394 | ||
395 | priv->hash_regs[0] = &priv->regs->gaddr0; | |
1577ecef | 396 | priv->hash_regs[1] = &priv->regs->gaddr1; |
0bbaf069 KG |
397 | priv->hash_regs[2] = &priv->regs->gaddr2; |
398 | priv->hash_regs[3] = &priv->regs->gaddr3; | |
399 | priv->hash_regs[4] = &priv->regs->gaddr4; | |
400 | priv->hash_regs[5] = &priv->regs->gaddr5; | |
401 | priv->hash_regs[6] = &priv->regs->gaddr6; | |
402 | priv->hash_regs[7] = &priv->regs->gaddr7; | |
403 | } | |
404 | ||
b31a1d8b | 405 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
406 | priv->padding = DEFAULT_PADDING; |
407 | else | |
408 | priv->padding = 0; | |
409 | ||
0bbaf069 KG |
410 | if (dev->features & NETIF_F_IP_CSUM) |
411 | dev->hard_header_len += GMAC_FCB_LEN; | |
1da177e4 LT |
412 | |
413 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; | |
1da177e4 LT |
414 | priv->tx_ring_size = DEFAULT_TX_RING_SIZE; |
415 | priv->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
4669bc90 | 416 | priv->num_txbdfree = DEFAULT_TX_RING_SIZE; |
1da177e4 LT |
417 | |
418 | priv->txcoalescing = DEFAULT_TX_COALESCE; | |
b46a8454 | 419 | priv->txic = DEFAULT_TXIC; |
1da177e4 | 420 | priv->rxcoalescing = DEFAULT_RX_COALESCE; |
b46a8454 | 421 | priv->rxic = DEFAULT_RXIC; |
1da177e4 | 422 | |
0bbaf069 KG |
423 | /* Enable most messages by default */ |
424 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
425 | ||
d3eab82b TP |
426 | /* Carrier starts down, phylib will bring it up */ |
427 | netif_carrier_off(dev); | |
428 | ||
1da177e4 LT |
429 | err = register_netdev(dev); |
430 | ||
431 | if (err) { | |
432 | printk(KERN_ERR "%s: Cannot register net device, aborting.\n", | |
433 | dev->name); | |
434 | goto register_fail; | |
435 | } | |
436 | ||
2884e5cc AV |
437 | device_init_wakeup(&dev->dev, |
438 | priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
439 | ||
c50a5d9a DH |
440 | /* fill out IRQ number and name fields */ |
441 | len_devname = strlen(dev->name); | |
442 | strncpy(&priv->int_name_tx[0], dev->name, len_devname); | |
443 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { | |
444 | strncpy(&priv->int_name_tx[len_devname], | |
445 | "_tx", sizeof("_tx") + 1); | |
446 | ||
447 | strncpy(&priv->int_name_rx[0], dev->name, len_devname); | |
448 | strncpy(&priv->int_name_rx[len_devname], | |
449 | "_rx", sizeof("_rx") + 1); | |
450 | ||
451 | strncpy(&priv->int_name_er[0], dev->name, len_devname); | |
452 | strncpy(&priv->int_name_er[len_devname], | |
453 | "_er", sizeof("_er") + 1); | |
454 | } else | |
455 | priv->int_name_tx[len_devname] = '\0'; | |
456 | ||
7f7f5316 AF |
457 | /* Create all the sysfs files */ |
458 | gfar_init_sysfs(dev); | |
459 | ||
1da177e4 | 460 | /* Print out the device info */ |
e174961c | 461 | printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr); |
1da177e4 LT |
462 | |
463 | /* Even more device info helps when determining which kernel */ | |
7f7f5316 | 464 | /* provided which set of benchmarks. */ |
1da177e4 | 465 | printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name); |
1da177e4 LT |
466 | printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n", |
467 | dev->name, priv->rx_ring_size, priv->tx_ring_size); | |
468 | ||
469 | return 0; | |
470 | ||
471 | register_fail: | |
cc8c6e37 | 472 | iounmap(priv->regs); |
1da177e4 | 473 | regs_fail: |
fe192a49 GL |
474 | if (priv->phy_node) |
475 | of_node_put(priv->phy_node); | |
476 | if (priv->tbi_node) | |
477 | of_node_put(priv->tbi_node); | |
1da177e4 | 478 | free_netdev(dev); |
bb40dcbb | 479 | return err; |
1da177e4 LT |
480 | } |
481 | ||
b31a1d8b | 482 | static int gfar_remove(struct of_device *ofdev) |
1da177e4 | 483 | { |
b31a1d8b | 484 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
1da177e4 | 485 | |
fe192a49 GL |
486 | if (priv->phy_node) |
487 | of_node_put(priv->phy_node); | |
488 | if (priv->tbi_node) | |
489 | of_node_put(priv->tbi_node); | |
490 | ||
b31a1d8b | 491 | dev_set_drvdata(&ofdev->dev, NULL); |
1da177e4 | 492 | |
d9d8e041 | 493 | unregister_netdev(priv->ndev); |
cc8c6e37 | 494 | iounmap(priv->regs); |
4826857f | 495 | free_netdev(priv->ndev); |
1da177e4 LT |
496 | |
497 | return 0; | |
498 | } | |
499 | ||
d87eb127 | 500 | #ifdef CONFIG_PM |
b31a1d8b | 501 | static int gfar_suspend(struct of_device *ofdev, pm_message_t state) |
d87eb127 | 502 | { |
b31a1d8b | 503 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 504 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
505 | unsigned long flags; |
506 | u32 tempval; | |
507 | ||
508 | int magic_packet = priv->wol_en && | |
b31a1d8b | 509 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
510 | |
511 | netif_device_detach(dev); | |
512 | ||
513 | if (netif_running(dev)) { | |
514 | spin_lock_irqsave(&priv->txlock, flags); | |
515 | spin_lock(&priv->rxlock); | |
516 | ||
517 | gfar_halt_nodisable(dev); | |
518 | ||
519 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
520 | tempval = gfar_read(&priv->regs->maccfg1); | |
521 | ||
522 | tempval &= ~MACCFG1_TX_EN; | |
523 | ||
524 | if (!magic_packet) | |
525 | tempval &= ~MACCFG1_RX_EN; | |
526 | ||
527 | gfar_write(&priv->regs->maccfg1, tempval); | |
528 | ||
529 | spin_unlock(&priv->rxlock); | |
530 | spin_unlock_irqrestore(&priv->txlock, flags); | |
531 | ||
d87eb127 | 532 | napi_disable(&priv->napi); |
d87eb127 SW |
533 | |
534 | if (magic_packet) { | |
535 | /* Enable interrupt on Magic Packet */ | |
536 | gfar_write(&priv->regs->imask, IMASK_MAG); | |
537 | ||
538 | /* Enable Magic Packet mode */ | |
539 | tempval = gfar_read(&priv->regs->maccfg2); | |
540 | tempval |= MACCFG2_MPEN; | |
541 | gfar_write(&priv->regs->maccfg2, tempval); | |
542 | } else { | |
543 | phy_stop(priv->phydev); | |
544 | } | |
545 | } | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
b31a1d8b | 550 | static int gfar_resume(struct of_device *ofdev) |
d87eb127 | 551 | { |
b31a1d8b | 552 | struct gfar_private *priv = dev_get_drvdata(&ofdev->dev); |
29ded5f7 | 553 | struct net_device *dev = priv->ndev; |
d87eb127 SW |
554 | unsigned long flags; |
555 | u32 tempval; | |
556 | int magic_packet = priv->wol_en && | |
b31a1d8b | 557 | (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); |
d87eb127 SW |
558 | |
559 | if (!netif_running(dev)) { | |
560 | netif_device_attach(dev); | |
561 | return 0; | |
562 | } | |
563 | ||
564 | if (!magic_packet && priv->phydev) | |
565 | phy_start(priv->phydev); | |
566 | ||
567 | /* Disable Magic Packet mode, in case something | |
568 | * else woke us up. | |
569 | */ | |
570 | ||
571 | spin_lock_irqsave(&priv->txlock, flags); | |
572 | spin_lock(&priv->rxlock); | |
573 | ||
574 | tempval = gfar_read(&priv->regs->maccfg2); | |
575 | tempval &= ~MACCFG2_MPEN; | |
576 | gfar_write(&priv->regs->maccfg2, tempval); | |
577 | ||
578 | gfar_start(dev); | |
579 | ||
580 | spin_unlock(&priv->rxlock); | |
581 | spin_unlock_irqrestore(&priv->txlock, flags); | |
582 | ||
583 | netif_device_attach(dev); | |
584 | ||
d87eb127 | 585 | napi_enable(&priv->napi); |
d87eb127 SW |
586 | |
587 | return 0; | |
588 | } | |
589 | #else | |
590 | #define gfar_suspend NULL | |
591 | #define gfar_resume NULL | |
592 | #endif | |
1da177e4 | 593 | |
e8a2b6a4 AF |
594 | /* Reads the controller's registers to determine what interface |
595 | * connects it to the PHY. | |
596 | */ | |
597 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
598 | { | |
599 | struct gfar_private *priv = netdev_priv(dev); | |
600 | u32 ecntrl = gfar_read(&priv->regs->ecntrl); | |
601 | ||
602 | if (ecntrl & ECNTRL_SGMII_MODE) | |
603 | return PHY_INTERFACE_MODE_SGMII; | |
604 | ||
605 | if (ecntrl & ECNTRL_TBI_MODE) { | |
606 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
607 | return PHY_INTERFACE_MODE_RTBI; | |
608 | else | |
609 | return PHY_INTERFACE_MODE_TBI; | |
610 | } | |
611 | ||
612 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
613 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) | |
614 | return PHY_INTERFACE_MODE_RMII; | |
7132ab7f | 615 | else { |
b31a1d8b | 616 | phy_interface_t interface = priv->interface; |
7132ab7f AF |
617 | |
618 | /* | |
619 | * This isn't autodetected right now, so it must | |
620 | * be set by the device tree or platform code. | |
621 | */ | |
622 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
623 | return PHY_INTERFACE_MODE_RGMII_ID; | |
624 | ||
e8a2b6a4 | 625 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 626 | } |
e8a2b6a4 AF |
627 | } |
628 | ||
b31a1d8b | 629 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
630 | return PHY_INTERFACE_MODE_GMII; |
631 | ||
632 | return PHY_INTERFACE_MODE_MII; | |
633 | } | |
634 | ||
635 | ||
bb40dcbb AF |
636 | /* Initializes driver's PHY state, and attaches to the PHY. |
637 | * Returns 0 on success. | |
1da177e4 LT |
638 | */ |
639 | static int init_phy(struct net_device *dev) | |
640 | { | |
641 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 642 | uint gigabit_support = |
b31a1d8b | 643 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
bb40dcbb | 644 | SUPPORTED_1000baseT_Full : 0; |
e8a2b6a4 | 645 | phy_interface_t interface; |
1da177e4 LT |
646 | |
647 | priv->oldlink = 0; | |
648 | priv->oldspeed = 0; | |
649 | priv->oldduplex = -1; | |
650 | ||
e8a2b6a4 AF |
651 | interface = gfar_get_interface(dev); |
652 | ||
1db780f8 AV |
653 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
654 | interface); | |
655 | if (!priv->phydev) | |
656 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
657 | interface); | |
658 | if (!priv->phydev) { | |
659 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
660 | return -ENODEV; | |
fe192a49 | 661 | } |
1da177e4 | 662 | |
d3c12873 KJ |
663 | if (interface == PHY_INTERFACE_MODE_SGMII) |
664 | gfar_configure_serdes(dev); | |
665 | ||
bb40dcbb | 666 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
667 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
668 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
669 | |
670 | return 0; | |
1da177e4 LT |
671 | } |
672 | ||
d0313587 PG |
673 | /* |
674 | * Initialize TBI PHY interface for communicating with the | |
675 | * SERDES lynx PHY on the chip. We communicate with this PHY | |
676 | * through the MDIO bus on each controller, treating it as a | |
677 | * "normal" PHY at the address found in the TBIPA register. We assume | |
678 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
679 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
680 | * value doesn't matter, as there are no other PHYs on the bus. | |
681 | */ | |
d3c12873 KJ |
682 | static void gfar_configure_serdes(struct net_device *dev) |
683 | { | |
684 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
685 | struct phy_device *tbiphy; |
686 | ||
687 | if (!priv->tbi_node) { | |
688 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
689 | "device tree specify a tbi-handle\n"); | |
690 | return; | |
691 | } | |
c132419e | 692 | |
fe192a49 GL |
693 | tbiphy = of_phy_find_device(priv->tbi_node); |
694 | if (!tbiphy) { | |
695 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
696 | return; |
697 | } | |
d3c12873 | 698 | |
b31a1d8b AF |
699 | /* |
700 | * If the link is already up, we must already be ok, and don't need to | |
bdb59f94 TP |
701 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
702 | * everything for us? Resetting it takes the link down and requires | |
703 | * several seconds for it to come back. | |
704 | */ | |
fe192a49 | 705 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 706 | return; |
d3c12873 | 707 | |
d0313587 | 708 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 709 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 710 | |
fe192a49 | 711 | phy_write(tbiphy, MII_ADVERTISE, |
d3c12873 KJ |
712 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
713 | ADVERTISE_1000XPSE_ASYM); | |
714 | ||
fe192a49 | 715 | phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE | |
d3c12873 KJ |
716 | BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000); |
717 | } | |
718 | ||
1da177e4 LT |
719 | static void init_registers(struct net_device *dev) |
720 | { | |
721 | struct gfar_private *priv = netdev_priv(dev); | |
722 | ||
723 | /* Clear IEVENT */ | |
724 | gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR); | |
725 | ||
726 | /* Initialize IMASK */ | |
727 | gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR); | |
728 | ||
729 | /* Init hash registers to zero */ | |
0bbaf069 KG |
730 | gfar_write(&priv->regs->igaddr0, 0); |
731 | gfar_write(&priv->regs->igaddr1, 0); | |
732 | gfar_write(&priv->regs->igaddr2, 0); | |
733 | gfar_write(&priv->regs->igaddr3, 0); | |
734 | gfar_write(&priv->regs->igaddr4, 0); | |
735 | gfar_write(&priv->regs->igaddr5, 0); | |
736 | gfar_write(&priv->regs->igaddr6, 0); | |
737 | gfar_write(&priv->regs->igaddr7, 0); | |
1da177e4 LT |
738 | |
739 | gfar_write(&priv->regs->gaddr0, 0); | |
740 | gfar_write(&priv->regs->gaddr1, 0); | |
741 | gfar_write(&priv->regs->gaddr2, 0); | |
742 | gfar_write(&priv->regs->gaddr3, 0); | |
743 | gfar_write(&priv->regs->gaddr4, 0); | |
744 | gfar_write(&priv->regs->gaddr5, 0); | |
745 | gfar_write(&priv->regs->gaddr6, 0); | |
746 | gfar_write(&priv->regs->gaddr7, 0); | |
747 | ||
1da177e4 | 748 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 749 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
cc8c6e37 | 750 | memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
751 | |
752 | /* Mask off the CAM interrupts */ | |
753 | gfar_write(&priv->regs->rmon.cam1, 0xffffffff); | |
754 | gfar_write(&priv->regs->rmon.cam2, 0xffffffff); | |
755 | } | |
756 | ||
757 | /* Initialize the max receive buffer length */ | |
758 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
759 | ||
1da177e4 LT |
760 | /* Initialize the Minimum Frame Length Register */ |
761 | gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS); | |
1da177e4 LT |
762 | } |
763 | ||
0bbaf069 KG |
764 | |
765 | /* Halt the receive and transmit queues */ | |
d87eb127 | 766 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
767 | { |
768 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 769 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
770 | u32 tempval; |
771 | ||
1da177e4 LT |
772 | /* Mask all interrupts */ |
773 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
774 | ||
775 | /* Clear all interrupts */ | |
776 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
777 | ||
778 | /* Stop the DMA, and wait for it to stop */ | |
779 | tempval = gfar_read(&priv->regs->dmactrl); | |
780 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) | |
781 | != (DMACTRL_GRS | DMACTRL_GTS)) { | |
782 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); | |
783 | gfar_write(&priv->regs->dmactrl, tempval); | |
784 | ||
785 | while (!(gfar_read(&priv->regs->ievent) & | |
786 | (IEVENT_GRSC | IEVENT_GTSC))) | |
787 | cpu_relax(); | |
788 | } | |
d87eb127 | 789 | } |
d87eb127 SW |
790 | |
791 | /* Halt the receive and transmit queues */ | |
792 | void gfar_halt(struct net_device *dev) | |
793 | { | |
794 | struct gfar_private *priv = netdev_priv(dev); | |
795 | struct gfar __iomem *regs = priv->regs; | |
796 | u32 tempval; | |
1da177e4 | 797 | |
2a54adc3 SW |
798 | gfar_halt_nodisable(dev); |
799 | ||
1da177e4 LT |
800 | /* Disable Rx and Tx */ |
801 | tempval = gfar_read(®s->maccfg1); | |
802 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
803 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
804 | } |
805 | ||
806 | void stop_gfar(struct net_device *dev) | |
807 | { | |
808 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 809 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
810 | unsigned long flags; |
811 | ||
bb40dcbb AF |
812 | phy_stop(priv->phydev); |
813 | ||
0bbaf069 | 814 | /* Lock it down */ |
fef6108d AF |
815 | spin_lock_irqsave(&priv->txlock, flags); |
816 | spin_lock(&priv->rxlock); | |
0bbaf069 | 817 | |
0bbaf069 | 818 | gfar_halt(dev); |
1da177e4 | 819 | |
fef6108d AF |
820 | spin_unlock(&priv->rxlock); |
821 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1da177e4 LT |
822 | |
823 | /* Free the IRQs */ | |
b31a1d8b | 824 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
1da177e4 LT |
825 | free_irq(priv->interruptError, dev); |
826 | free_irq(priv->interruptTransmit, dev); | |
827 | free_irq(priv->interruptReceive, dev); | |
828 | } else { | |
1577ecef | 829 | free_irq(priv->interruptTransmit, dev); |
1da177e4 LT |
830 | } |
831 | ||
832 | free_skb_resources(priv); | |
833 | ||
4826857f | 834 | dma_free_coherent(&priv->ofdev->dev, |
1da177e4 LT |
835 | sizeof(struct txbd8)*priv->tx_ring_size |
836 | + sizeof(struct rxbd8)*priv->rx_ring_size, | |
837 | priv->tx_bd_base, | |
0bbaf069 | 838 | gfar_read(®s->tbase0)); |
1da177e4 LT |
839 | } |
840 | ||
841 | /* If there are any tx skbs or rx skbs still around, free them. | |
842 | * Then free tx_skbuff and rx_skbuff */ | |
bb40dcbb | 843 | static void free_skb_resources(struct gfar_private *priv) |
1da177e4 LT |
844 | { |
845 | struct rxbd8 *rxbdp; | |
846 | struct txbd8 *txbdp; | |
4669bc90 | 847 | int i, j; |
1da177e4 LT |
848 | |
849 | /* Go through all the buffer descriptors and free their data buffers */ | |
850 | txbdp = priv->tx_bd_base; | |
851 | ||
852 | for (i = 0; i < priv->tx_ring_size; i++) { | |
4669bc90 DH |
853 | if (!priv->tx_skbuff[i]) |
854 | continue; | |
1da177e4 | 855 | |
4826857f | 856 | dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 DH |
857 | txbdp->length, DMA_TO_DEVICE); |
858 | txbdp->lstatus = 0; | |
859 | for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) { | |
860 | txbdp++; | |
4826857f | 861 | dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr, |
4669bc90 | 862 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 863 | } |
ad5da7ab | 864 | txbdp++; |
4669bc90 DH |
865 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
866 | priv->tx_skbuff[i] = NULL; | |
1da177e4 LT |
867 | } |
868 | ||
869 | kfree(priv->tx_skbuff); | |
870 | ||
871 | rxbdp = priv->rx_bd_base; | |
872 | ||
873 | /* rx_skbuff is not guaranteed to be allocated, so only | |
874 | * free it and its contents if it is allocated */ | |
875 | if(priv->rx_skbuff != NULL) { | |
876 | for (i = 0; i < priv->rx_ring_size; i++) { | |
877 | if (priv->rx_skbuff[i]) { | |
4826857f | 878 | dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr, |
7f7f5316 | 879 | priv->rx_buffer_size, |
1da177e4 LT |
880 | DMA_FROM_DEVICE); |
881 | ||
882 | dev_kfree_skb_any(priv->rx_skbuff[i]); | |
883 | priv->rx_skbuff[i] = NULL; | |
884 | } | |
885 | ||
5a5efed4 | 886 | rxbdp->lstatus = 0; |
1da177e4 LT |
887 | rxbdp->bufPtr = 0; |
888 | ||
889 | rxbdp++; | |
890 | } | |
891 | ||
892 | kfree(priv->rx_skbuff); | |
893 | } | |
894 | } | |
895 | ||
0bbaf069 KG |
896 | void gfar_start(struct net_device *dev) |
897 | { | |
898 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 899 | struct gfar __iomem *regs = priv->regs; |
0bbaf069 KG |
900 | u32 tempval; |
901 | ||
902 | /* Enable Rx and Tx in MACCFG1 */ | |
903 | tempval = gfar_read(®s->maccfg1); | |
904 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
905 | gfar_write(®s->maccfg1, tempval); | |
906 | ||
907 | /* Initialize DMACTRL to have WWR and WOP */ | |
908 | tempval = gfar_read(&priv->regs->dmactrl); | |
909 | tempval |= DMACTRL_INIT_SETTINGS; | |
910 | gfar_write(&priv->regs->dmactrl, tempval); | |
911 | ||
0bbaf069 KG |
912 | /* Make sure we aren't stopped */ |
913 | tempval = gfar_read(&priv->regs->dmactrl); | |
914 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); | |
915 | gfar_write(&priv->regs->dmactrl, tempval); | |
916 | ||
fef6108d AF |
917 | /* Clear THLT/RHLT, so that the DMA starts polling now */ |
918 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT); | |
919 | gfar_write(®s->rstat, RSTAT_CLEAR_RHALT); | |
920 | ||
0bbaf069 KG |
921 | /* Unmask the interrupts we look for */ |
922 | gfar_write(®s->imask, IMASK_DEFAULT); | |
12dea57b DH |
923 | |
924 | dev->trans_start = jiffies; | |
0bbaf069 KG |
925 | } |
926 | ||
1da177e4 | 927 | /* Bring the controller up and running */ |
ccc05c6e | 928 | int startup_gfar(struct net_device *ndev) |
1da177e4 LT |
929 | { |
930 | struct txbd8 *txbdp; | |
931 | struct rxbd8 *rxbdp; | |
f9663aea | 932 | dma_addr_t addr = 0; |
ccc05c6e | 933 | void *vaddr; |
1da177e4 | 934 | int i; |
ccc05c6e AV |
935 | struct gfar_private *priv = netdev_priv(ndev); |
936 | struct device *dev = &priv->ofdev->dev; | |
cc8c6e37 | 937 | struct gfar __iomem *regs = priv->regs; |
ccc05c6e | 938 | int err; |
0bbaf069 | 939 | u32 rctrl = 0; |
75c48859 | 940 | u32 tctrl = 0; |
7f7f5316 | 941 | u32 attrs = 0; |
1da177e4 LT |
942 | |
943 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
944 | ||
945 | /* Allocate memory for the buffer descriptors */ | |
ccc05c6e AV |
946 | vaddr = dma_alloc_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size + |
947 | sizeof(*rxbdp) * priv->rx_ring_size, | |
948 | &addr, GFP_KERNEL); | |
949 | if (!vaddr) { | |
0bbaf069 | 950 | if (netif_msg_ifup(priv)) |
ccc05c6e AV |
951 | pr_err("%s: Could not allocate buffer descriptors!\n", |
952 | ndev->name); | |
1da177e4 LT |
953 | return -ENOMEM; |
954 | } | |
955 | ||
ccc05c6e | 956 | priv->tx_bd_base = vaddr; |
1da177e4 LT |
957 | |
958 | /* enet DMA only understands physical addresses */ | |
0bbaf069 | 959 | gfar_write(®s->tbase0, addr); |
1da177e4 LT |
960 | |
961 | /* Start the rx descriptor ring where the tx ring leaves off */ | |
ccc05c6e AV |
962 | addr = addr + sizeof(*txbdp) * priv->tx_ring_size; |
963 | vaddr = vaddr + sizeof(*txbdp) * priv->tx_ring_size; | |
964 | priv->rx_bd_base = vaddr; | |
0bbaf069 | 965 | gfar_write(®s->rbase0, addr); |
1da177e4 LT |
966 | |
967 | /* Setup the skbuff rings */ | |
ccc05c6e AV |
968 | priv->tx_skbuff = kmalloc(sizeof(*priv->tx_skbuff) * |
969 | priv->tx_ring_size, GFP_KERNEL); | |
970 | if (!priv->tx_skbuff) { | |
0bbaf069 | 971 | if (netif_msg_ifup(priv)) |
ccc05c6e AV |
972 | pr_err("%s: Could not allocate tx_skbuff\n", |
973 | ndev->name); | |
1da177e4 LT |
974 | err = -ENOMEM; |
975 | goto tx_skb_fail; | |
976 | } | |
977 | ||
978 | for (i = 0; i < priv->tx_ring_size; i++) | |
979 | priv->tx_skbuff[i] = NULL; | |
980 | ||
ccc05c6e AV |
981 | priv->rx_skbuff = kmalloc(sizeof(*priv->rx_skbuff) * |
982 | priv->rx_ring_size, GFP_KERNEL); | |
983 | if (!priv->rx_skbuff) { | |
0bbaf069 | 984 | if (netif_msg_ifup(priv)) |
ccc05c6e AV |
985 | pr_err("%s: Could not allocate rx_skbuff\n", |
986 | ndev->name); | |
1da177e4 LT |
987 | err = -ENOMEM; |
988 | goto rx_skb_fail; | |
989 | } | |
990 | ||
991 | for (i = 0; i < priv->rx_ring_size; i++) | |
992 | priv->rx_skbuff[i] = NULL; | |
993 | ||
994 | /* Initialize some variables in our dev structure */ | |
4669bc90 | 995 | priv->num_txbdfree = priv->tx_ring_size; |
1da177e4 LT |
996 | priv->dirty_tx = priv->cur_tx = priv->tx_bd_base; |
997 | priv->cur_rx = priv->rx_bd_base; | |
998 | priv->skb_curtx = priv->skb_dirtytx = 0; | |
999 | priv->skb_currx = 0; | |
1000 | ||
1001 | /* Initialize Transmit Descriptor Ring */ | |
1002 | txbdp = priv->tx_bd_base; | |
1003 | for (i = 0; i < priv->tx_ring_size; i++) { | |
5a5efed4 | 1004 | txbdp->lstatus = 0; |
1da177e4 LT |
1005 | txbdp->bufPtr = 0; |
1006 | txbdp++; | |
1007 | } | |
1008 | ||
1009 | /* Set the last descriptor in the ring to indicate wrap */ | |
1010 | txbdp--; | |
1011 | txbdp->status |= TXBD_WRAP; | |
1012 | ||
1013 | rxbdp = priv->rx_bd_base; | |
1014 | for (i = 0; i < priv->rx_ring_size; i++) { | |
815b97c6 | 1015 | struct sk_buff *skb; |
1da177e4 | 1016 | |
ccc05c6e | 1017 | skb = gfar_new_skb(ndev); |
815b97c6 | 1018 | if (!skb) { |
ccc05c6e AV |
1019 | pr_err("%s: Can't allocate RX buffers\n", ndev->name); |
1020 | err = -ENOMEM; | |
815b97c6 AF |
1021 | goto err_rxalloc_fail; |
1022 | } | |
1da177e4 LT |
1023 | |
1024 | priv->rx_skbuff[i] = skb; | |
1025 | ||
ccc05c6e | 1026 | gfar_new_rxbdp(ndev, rxbdp, skb); |
815b97c6 | 1027 | |
1da177e4 LT |
1028 | rxbdp++; |
1029 | } | |
1030 | ||
1031 | /* Set the last descriptor in the ring to wrap */ | |
1032 | rxbdp--; | |
1033 | rxbdp->status |= RXBD_WRAP; | |
1034 | ||
1035 | /* If the device has multiple interrupts, register for | |
1036 | * them. Otherwise, only register for the one */ | |
b31a1d8b | 1037 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1038 | /* Install our interrupt handlers for Error, |
1da177e4 | 1039 | * Transmit, and Receive */ |
ccc05c6e AV |
1040 | err = request_irq(priv->interruptError, gfar_error, 0, |
1041 | priv->int_name_er, ndev); | |
1042 | if (err) { | |
0bbaf069 | 1043 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1044 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1045 | priv->interruptError); | |
1da177e4 LT |
1046 | goto err_irq_fail; |
1047 | } | |
1048 | ||
ccc05c6e AV |
1049 | err = request_irq(priv->interruptTransmit, gfar_transmit, 0, |
1050 | priv->int_name_tx, ndev); | |
1051 | if (err) { | |
0bbaf069 | 1052 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1053 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1054 | priv->interruptTransmit); | |
1da177e4 LT |
1055 | goto tx_irq_fail; |
1056 | } | |
1057 | ||
ccc05c6e AV |
1058 | err = request_irq(priv->interruptReceive, gfar_receive, 0, |
1059 | priv->int_name_rx, ndev); | |
1060 | if (err) { | |
0bbaf069 | 1061 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1062 | pr_err("%s: Can't get IRQ %d (receive0)\n", |
1063 | ndev->name, priv->interruptReceive); | |
1da177e4 LT |
1064 | goto rx_irq_fail; |
1065 | } | |
1066 | } else { | |
ccc05c6e AV |
1067 | err = request_irq(priv->interruptTransmit, gfar_interrupt, |
1068 | 0, priv->int_name_tx, ndev); | |
1069 | if (err) { | |
0bbaf069 | 1070 | if (netif_msg_intr(priv)) |
ccc05c6e AV |
1071 | pr_err("%s: Can't get IRQ %d\n", ndev->name, |
1072 | priv->interruptTransmit); | |
1da177e4 LT |
1073 | goto err_irq_fail; |
1074 | } | |
1075 | } | |
1076 | ||
bb40dcbb | 1077 | phy_start(priv->phydev); |
1da177e4 LT |
1078 | |
1079 | /* Configure the coalescing support */ | |
b46a8454 | 1080 | gfar_write(®s->txic, 0); |
1da177e4 | 1081 | if (priv->txcoalescing) |
b46a8454 | 1082 | gfar_write(®s->txic, priv->txic); |
1da177e4 | 1083 | |
b46a8454 | 1084 | gfar_write(®s->rxic, 0); |
1da177e4 | 1085 | if (priv->rxcoalescing) |
b46a8454 | 1086 | gfar_write(®s->rxic, priv->rxic); |
1da177e4 | 1087 | |
0bbaf069 KG |
1088 | if (priv->rx_csum_enable) |
1089 | rctrl |= RCTRL_CHECKSUMMING; | |
1da177e4 | 1090 | |
7f7f5316 | 1091 | if (priv->extended_hash) { |
0bbaf069 | 1092 | rctrl |= RCTRL_EXTHASH; |
1da177e4 | 1093 | |
ccc05c6e | 1094 | gfar_clear_exact_match(ndev); |
7f7f5316 AF |
1095 | rctrl |= RCTRL_EMEN; |
1096 | } | |
1097 | ||
7f7f5316 AF |
1098 | if (priv->padding) { |
1099 | rctrl &= ~RCTRL_PAL_MASK; | |
1100 | rctrl |= RCTRL_PADDING(priv->padding); | |
1101 | } | |
1102 | ||
75c48859 YZ |
1103 | /* keep vlan related bits if it's enabled */ |
1104 | if (priv->vlgrp) { | |
1105 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; | |
1106 | tctrl |= TCTRL_VLINS; | |
1107 | } | |
1108 | ||
0bbaf069 | 1109 | /* Init rctrl based on our settings */ |
ccc05c6e | 1110 | gfar_write(®s->rctrl, rctrl); |
1da177e4 | 1111 | |
ccc05c6e | 1112 | if (ndev->features & NETIF_F_IP_CSUM) |
75c48859 YZ |
1113 | tctrl |= TCTRL_INIT_CSUM; |
1114 | ||
ccc05c6e | 1115 | gfar_write(®s->tctrl, tctrl); |
1da177e4 | 1116 | |
7f7f5316 AF |
1117 | /* Set the extraction length and index */ |
1118 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
1119 | ATTRELI_EI(priv->rx_stash_index); | |
1120 | ||
ccc05c6e | 1121 | gfar_write(®s->attreli, attrs); |
7f7f5316 AF |
1122 | |
1123 | /* Start with defaults, and add stashing or locking | |
1124 | * depending on the approprate variables */ | |
1125 | attrs = ATTR_INIT_SETTINGS; | |
1126 | ||
1127 | if (priv->bd_stash_en) | |
1128 | attrs |= ATTR_BDSTASH; | |
1129 | ||
1130 | if (priv->rx_stash_size != 0) | |
1131 | attrs |= ATTR_BUFSTASH; | |
1132 | ||
ccc05c6e | 1133 | gfar_write(®s->attr, attrs); |
7f7f5316 | 1134 | |
ccc05c6e AV |
1135 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); |
1136 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
1137 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
7f7f5316 AF |
1138 | |
1139 | /* Start the controller */ | |
ccc05c6e | 1140 | gfar_start(ndev); |
1da177e4 LT |
1141 | |
1142 | return 0; | |
1143 | ||
1144 | rx_irq_fail: | |
ccc05c6e | 1145 | free_irq(priv->interruptTransmit, ndev); |
1da177e4 | 1146 | tx_irq_fail: |
ccc05c6e | 1147 | free_irq(priv->interruptError, ndev); |
1da177e4 | 1148 | err_irq_fail: |
7d2e3cb7 | 1149 | err_rxalloc_fail: |
1da177e4 LT |
1150 | rx_skb_fail: |
1151 | free_skb_resources(priv); | |
1152 | tx_skb_fail: | |
ccc05c6e AV |
1153 | dma_free_coherent(dev, sizeof(*txbdp) * priv->tx_ring_size + |
1154 | sizeof(*rxbdp) * priv->rx_ring_size, | |
1155 | priv->tx_bd_base, gfar_read(®s->tbase0)); | |
1da177e4 LT |
1156 | return err; |
1157 | } | |
1158 | ||
1159 | /* Called when something needs to use the ethernet device */ | |
1160 | /* Returns 0 for success. */ | |
1161 | static int gfar_enet_open(struct net_device *dev) | |
1162 | { | |
94e8cc35 | 1163 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1164 | int err; |
1165 | ||
bea3348e SH |
1166 | napi_enable(&priv->napi); |
1167 | ||
0fd56bb5 AF |
1168 | skb_queue_head_init(&priv->rx_recycle); |
1169 | ||
1da177e4 LT |
1170 | /* Initialize a bunch of registers */ |
1171 | init_registers(dev); | |
1172 | ||
1173 | gfar_set_mac_address(dev); | |
1174 | ||
1175 | err = init_phy(dev); | |
1176 | ||
bea3348e SH |
1177 | if(err) { |
1178 | napi_disable(&priv->napi); | |
1da177e4 | 1179 | return err; |
bea3348e | 1180 | } |
1da177e4 LT |
1181 | |
1182 | err = startup_gfar(dev); | |
db0e8e3f | 1183 | if (err) { |
bea3348e | 1184 | napi_disable(&priv->napi); |
db0e8e3f AV |
1185 | return err; |
1186 | } | |
1da177e4 LT |
1187 | |
1188 | netif_start_queue(dev); | |
1189 | ||
2884e5cc AV |
1190 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
1191 | ||
1da177e4 LT |
1192 | return err; |
1193 | } | |
1194 | ||
54dc79fe | 1195 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 1196 | { |
54dc79fe | 1197 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
1198 | |
1199 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 1200 | |
0bbaf069 KG |
1201 | return fcb; |
1202 | } | |
1203 | ||
1204 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb) | |
1205 | { | |
7f7f5316 | 1206 | u8 flags = 0; |
0bbaf069 KG |
1207 | |
1208 | /* If we're here, it's a IP packet with a TCP or UDP | |
1209 | * payload. We set it to checksum, using a pseudo-header | |
1210 | * we provide | |
1211 | */ | |
7f7f5316 | 1212 | flags = TXFCB_DEFAULT; |
0bbaf069 | 1213 | |
7f7f5316 AF |
1214 | /* Tell the controller what the protocol is */ |
1215 | /* And provide the already calculated phcs */ | |
eddc9ec5 | 1216 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 1217 | flags |= TXFCB_UDP; |
4bedb452 | 1218 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 1219 | } else |
8da32de5 | 1220 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
1221 | |
1222 | /* l3os is the distance between the start of the | |
1223 | * frame (skb->data) and the start of the IP hdr. | |
1224 | * l4os is the distance between the start of the | |
1225 | * l3 hdr and the l4 hdr */ | |
bbe735e4 | 1226 | fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN); |
cfe1fc77 | 1227 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 1228 | |
7f7f5316 | 1229 | fcb->flags = flags; |
0bbaf069 KG |
1230 | } |
1231 | ||
7f7f5316 | 1232 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 1233 | { |
7f7f5316 | 1234 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
1235 | fcb->vlctl = vlan_tx_tag_get(skb); |
1236 | } | |
1237 | ||
4669bc90 DH |
1238 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
1239 | struct txbd8 *base, int ring_size) | |
1240 | { | |
1241 | struct txbd8 *new_bd = bdp + stride; | |
1242 | ||
1243 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
1244 | } | |
1245 | ||
1246 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
1247 | int ring_size) | |
1248 | { | |
1249 | return skip_txbd(bdp, 1, base, ring_size); | |
1250 | } | |
1251 | ||
1da177e4 LT |
1252 | /* This is called by the kernel when a frame is ready for transmission. */ |
1253 | /* It is pointed to by the dev->hard_start_xmit function pointer */ | |
1254 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1255 | { | |
1256 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1257 | struct txfcb *fcb = NULL; |
4669bc90 | 1258 | struct txbd8 *txbdp, *txbdp_start, *base; |
5a5efed4 | 1259 | u32 lstatus; |
4669bc90 DH |
1260 | int i; |
1261 | u32 bufaddr; | |
fef6108d | 1262 | unsigned long flags; |
4669bc90 DH |
1263 | unsigned int nr_frags, length; |
1264 | ||
1265 | base = priv->tx_bd_base; | |
1266 | ||
5b28beaf LY |
1267 | /* make space for additional header when fcb is needed */ |
1268 | if (((skb->ip_summed == CHECKSUM_PARTIAL) || | |
1269 | (priv->vlgrp && vlan_tx_tag_present(skb))) && | |
1270 | (skb_headroom(skb) < GMAC_FCB_LEN)) { | |
54dc79fe SH |
1271 | struct sk_buff *skb_new; |
1272 | ||
1273 | skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN); | |
1274 | if (!skb_new) { | |
1275 | dev->stats.tx_errors++; | |
bd14ba84 | 1276 | kfree_skb(skb); |
54dc79fe SH |
1277 | return NETDEV_TX_OK; |
1278 | } | |
1279 | kfree_skb(skb); | |
1280 | skb = skb_new; | |
1281 | } | |
1282 | ||
4669bc90 DH |
1283 | /* total number of fragments in the SKB */ |
1284 | nr_frags = skb_shinfo(skb)->nr_frags; | |
1285 | ||
1286 | spin_lock_irqsave(&priv->txlock, flags); | |
1287 | ||
1288 | /* check if there is space to queue this packet */ | |
7958a453 | 1289 | if ((nr_frags+1) > priv->num_txbdfree) { |
4669bc90 DH |
1290 | /* no space, stop the queue */ |
1291 | netif_stop_queue(dev); | |
1292 | dev->stats.tx_fifo_errors++; | |
1293 | spin_unlock_irqrestore(&priv->txlock, flags); | |
1294 | return NETDEV_TX_BUSY; | |
1295 | } | |
1da177e4 LT |
1296 | |
1297 | /* Update transmit stats */ | |
09f75cd7 | 1298 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1299 | |
4669bc90 | 1300 | txbdp = txbdp_start = priv->cur_tx; |
1da177e4 | 1301 | |
4669bc90 DH |
1302 | if (nr_frags == 0) { |
1303 | lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1304 | } else { | |
1305 | /* Place the fragment addresses and lengths into the TxBDs */ | |
1306 | for (i = 0; i < nr_frags; i++) { | |
1307 | /* Point at the next BD, wrapping as needed */ | |
1308 | txbdp = next_txbd(txbdp, base, priv->tx_ring_size); | |
1309 | ||
1310 | length = skb_shinfo(skb)->frags[i].size; | |
1311 | ||
1312 | lstatus = txbdp->lstatus | length | | |
1313 | BD_LFLAG(TXBD_READY); | |
1314 | ||
1315 | /* Handle the last BD specially */ | |
1316 | if (i == nr_frags - 1) | |
1317 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 1318 | |
4826857f | 1319 | bufaddr = dma_map_page(&priv->ofdev->dev, |
4669bc90 DH |
1320 | skb_shinfo(skb)->frags[i].page, |
1321 | skb_shinfo(skb)->frags[i].page_offset, | |
1322 | length, | |
1323 | DMA_TO_DEVICE); | |
1324 | ||
1325 | /* set the TxBD length and buffer pointer */ | |
1326 | txbdp->bufPtr = bufaddr; | |
1327 | txbdp->lstatus = lstatus; | |
1328 | } | |
1329 | ||
1330 | lstatus = txbdp_start->lstatus; | |
1331 | } | |
1da177e4 | 1332 | |
0bbaf069 | 1333 | /* Set up checksumming */ |
12dea57b | 1334 | if (CHECKSUM_PARTIAL == skb->ip_summed) { |
54dc79fe SH |
1335 | fcb = gfar_add_fcb(skb); |
1336 | lstatus |= BD_LFLAG(TXBD_TOE); | |
1337 | gfar_tx_checksum(skb, fcb); | |
0bbaf069 KG |
1338 | } |
1339 | ||
77ecaf2d | 1340 | if (priv->vlgrp && vlan_tx_tag_present(skb)) { |
54dc79fe SH |
1341 | if (unlikely(NULL == fcb)) { |
1342 | fcb = gfar_add_fcb(skb); | |
5a5efed4 | 1343 | lstatus |= BD_LFLAG(TXBD_TOE); |
7f7f5316 | 1344 | } |
54dc79fe SH |
1345 | |
1346 | gfar_tx_vlan(skb, fcb); | |
0bbaf069 KG |
1347 | } |
1348 | ||
4669bc90 | 1349 | /* setup the TxBD length and buffer pointer for the first BD */ |
1da177e4 | 1350 | priv->tx_skbuff[priv->skb_curtx] = skb; |
4826857f | 1351 | txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
4669bc90 | 1352 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 1353 | |
4669bc90 | 1354 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); |
1da177e4 | 1355 | |
4669bc90 DH |
1356 | /* |
1357 | * The powerpc-specific eieio() is used, as wmb() has too strong | |
3b6330ce SW |
1358 | * semantics (it requires synchronization between cacheable and |
1359 | * uncacheable mappings, which eieio doesn't provide and which we | |
1360 | * don't need), thus requiring a more expensive sync instruction. At | |
1361 | * some point, the set of architecture-independent barrier functions | |
1362 | * should be expanded to include weaker barriers. | |
1363 | */ | |
3b6330ce | 1364 | eieio(); |
7f7f5316 | 1365 | |
4669bc90 DH |
1366 | txbdp_start->lstatus = lstatus; |
1367 | ||
1368 | /* Update the current skb pointer to the next entry we will use | |
1369 | * (wrapping if necessary) */ | |
1370 | priv->skb_curtx = (priv->skb_curtx + 1) & | |
1371 | TX_RING_MOD_MASK(priv->tx_ring_size); | |
1372 | ||
1373 | priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size); | |
1374 | ||
1375 | /* reduce TxBD free count */ | |
1376 | priv->num_txbdfree -= (nr_frags + 1); | |
1377 | ||
1378 | dev->trans_start = jiffies; | |
1da177e4 LT |
1379 | |
1380 | /* If the next BD still needs to be cleaned up, then the bds | |
1381 | are full. We need to tell the kernel to stop sending us stuff. */ | |
4669bc90 | 1382 | if (!priv->num_txbdfree) { |
1da177e4 LT |
1383 | netif_stop_queue(dev); |
1384 | ||
09f75cd7 | 1385 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
1386 | } |
1387 | ||
1da177e4 LT |
1388 | /* Tell the DMA to go go go */ |
1389 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
1390 | ||
1391 | /* Unlock priv */ | |
fef6108d | 1392 | spin_unlock_irqrestore(&priv->txlock, flags); |
1da177e4 | 1393 | |
54dc79fe | 1394 | return NETDEV_TX_OK; |
1da177e4 LT |
1395 | } |
1396 | ||
1397 | /* Stops the kernel queue, and halts the controller */ | |
1398 | static int gfar_close(struct net_device *dev) | |
1399 | { | |
1400 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e SH |
1401 | |
1402 | napi_disable(&priv->napi); | |
1403 | ||
0fd56bb5 | 1404 | skb_queue_purge(&priv->rx_recycle); |
ab939905 | 1405 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
1406 | stop_gfar(dev); |
1407 | ||
bb40dcbb AF |
1408 | /* Disconnect from the PHY */ |
1409 | phy_disconnect(priv->phydev); | |
1410 | priv->phydev = NULL; | |
1da177e4 LT |
1411 | |
1412 | netif_stop_queue(dev); | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1da177e4 | 1417 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 1418 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 1419 | { |
7f7f5316 | 1420 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
1421 | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | ||
0bbaf069 KG |
1426 | /* Enables and disables VLAN insertion/extraction */ |
1427 | static void gfar_vlan_rx_register(struct net_device *dev, | |
1428 | struct vlan_group *grp) | |
1429 | { | |
1430 | struct gfar_private *priv = netdev_priv(dev); | |
1431 | unsigned long flags; | |
1432 | u32 tempval; | |
1433 | ||
fef6108d | 1434 | spin_lock_irqsave(&priv->rxlock, flags); |
0bbaf069 | 1435 | |
cd1f55a5 | 1436 | priv->vlgrp = grp; |
0bbaf069 KG |
1437 | |
1438 | if (grp) { | |
1439 | /* Enable VLAN tag insertion */ | |
1440 | tempval = gfar_read(&priv->regs->tctrl); | |
1441 | tempval |= TCTRL_VLINS; | |
1442 | ||
1443 | gfar_write(&priv->regs->tctrl, tempval); | |
6aa20a22 | 1444 | |
0bbaf069 KG |
1445 | /* Enable VLAN tag extraction */ |
1446 | tempval = gfar_read(&priv->regs->rctrl); | |
77ecaf2d | 1447 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); |
0bbaf069 KG |
1448 | gfar_write(&priv->regs->rctrl, tempval); |
1449 | } else { | |
1450 | /* Disable VLAN tag insertion */ | |
1451 | tempval = gfar_read(&priv->regs->tctrl); | |
1452 | tempval &= ~TCTRL_VLINS; | |
1453 | gfar_write(&priv->regs->tctrl, tempval); | |
1454 | ||
1455 | /* Disable VLAN tag extraction */ | |
1456 | tempval = gfar_read(&priv->regs->rctrl); | |
1457 | tempval &= ~RCTRL_VLEX; | |
77ecaf2d DH |
1458 | /* If parse is no longer required, then disable parser */ |
1459 | if (tempval & RCTRL_REQ_PARSER) | |
1460 | tempval |= RCTRL_PRSDEP_INIT; | |
1461 | else | |
1462 | tempval &= ~RCTRL_PRSDEP_INIT; | |
0bbaf069 KG |
1463 | gfar_write(&priv->regs->rctrl, tempval); |
1464 | } | |
1465 | ||
77ecaf2d DH |
1466 | gfar_change_mtu(dev, dev->mtu); |
1467 | ||
fef6108d | 1468 | spin_unlock_irqrestore(&priv->rxlock, flags); |
0bbaf069 KG |
1469 | } |
1470 | ||
1da177e4 LT |
1471 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
1472 | { | |
1473 | int tempsize, tempval; | |
1474 | struct gfar_private *priv = netdev_priv(dev); | |
1475 | int oldsize = priv->rx_buffer_size; | |
0bbaf069 KG |
1476 | int frame_size = new_mtu + ETH_HLEN; |
1477 | ||
77ecaf2d | 1478 | if (priv->vlgrp) |
faa89577 | 1479 | frame_size += VLAN_HLEN; |
0bbaf069 | 1480 | |
1da177e4 | 1481 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
0bbaf069 KG |
1482 | if (netif_msg_drv(priv)) |
1483 | printk(KERN_ERR "%s: Invalid MTU setting\n", | |
1484 | dev->name); | |
1da177e4 LT |
1485 | return -EINVAL; |
1486 | } | |
1487 | ||
77ecaf2d DH |
1488 | if (gfar_uses_fcb(priv)) |
1489 | frame_size += GMAC_FCB_LEN; | |
1490 | ||
1491 | frame_size += priv->padding; | |
1492 | ||
1da177e4 LT |
1493 | tempsize = |
1494 | (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + | |
1495 | INCREMENTAL_BUFFER_SIZE; | |
1496 | ||
1497 | /* Only stop and start the controller if it isn't already | |
7f7f5316 | 1498 | * stopped, and we changed something */ |
1da177e4 LT |
1499 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
1500 | stop_gfar(dev); | |
1501 | ||
1502 | priv->rx_buffer_size = tempsize; | |
1503 | ||
1504 | dev->mtu = new_mtu; | |
1505 | ||
1506 | gfar_write(&priv->regs->mrblr, priv->rx_buffer_size); | |
1507 | gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size); | |
1508 | ||
1509 | /* If the mtu is larger than the max size for standard | |
1510 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
1511 | * to allow huge frames, and to check the length */ | |
1512 | tempval = gfar_read(&priv->regs->maccfg2); | |
1513 | ||
1514 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE) | |
1515 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1516 | else | |
1517 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
1518 | ||
1519 | gfar_write(&priv->regs->maccfg2, tempval); | |
1520 | ||
1521 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
1522 | startup_gfar(dev); | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
ab939905 | 1527 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
1528 | * transmitted after a set amount of time. |
1529 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
1530 | * starting over will fix the problem. |
1531 | */ | |
1532 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 1533 | { |
ab939905 SS |
1534 | struct gfar_private *priv = container_of(work, struct gfar_private, |
1535 | reset_task); | |
4826857f | 1536 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
1537 | |
1538 | if (dev->flags & IFF_UP) { | |
cbea2707 | 1539 | netif_stop_queue(dev); |
1da177e4 LT |
1540 | stop_gfar(dev); |
1541 | startup_gfar(dev); | |
cbea2707 | 1542 | netif_start_queue(dev); |
1da177e4 LT |
1543 | } |
1544 | ||
263ba320 | 1545 | netif_tx_schedule_all(dev); |
1da177e4 LT |
1546 | } |
1547 | ||
ab939905 SS |
1548 | static void gfar_timeout(struct net_device *dev) |
1549 | { | |
1550 | struct gfar_private *priv = netdev_priv(dev); | |
1551 | ||
1552 | dev->stats.tx_errors++; | |
1553 | schedule_work(&priv->reset_task); | |
1554 | } | |
1555 | ||
1da177e4 | 1556 | /* Interrupt Handler for Transmit complete */ |
f162b9d5 | 1557 | static int gfar_clean_tx_ring(struct net_device *dev) |
1da177e4 | 1558 | { |
d080cd63 | 1559 | struct gfar_private *priv = netdev_priv(dev); |
4669bc90 DH |
1560 | struct txbd8 *bdp; |
1561 | struct txbd8 *lbdp = NULL; | |
1562 | struct txbd8 *base = priv->tx_bd_base; | |
1563 | struct sk_buff *skb; | |
1564 | int skb_dirtytx; | |
1565 | int tx_ring_size = priv->tx_ring_size; | |
1566 | int frags = 0; | |
1567 | int i; | |
d080cd63 | 1568 | int howmany = 0; |
4669bc90 | 1569 | u32 lstatus; |
1da177e4 | 1570 | |
1da177e4 | 1571 | bdp = priv->dirty_tx; |
4669bc90 | 1572 | skb_dirtytx = priv->skb_dirtytx; |
1da177e4 | 1573 | |
4669bc90 DH |
1574 | while ((skb = priv->tx_skbuff[skb_dirtytx])) { |
1575 | frags = skb_shinfo(skb)->nr_frags; | |
1576 | lbdp = skip_txbd(bdp, frags, base, tx_ring_size); | |
1da177e4 | 1577 | |
4669bc90 | 1578 | lstatus = lbdp->lstatus; |
1da177e4 | 1579 | |
4669bc90 DH |
1580 | /* Only clean completed frames */ |
1581 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
1582 | (lstatus & BD_LENGTH_MASK)) | |
1583 | break; | |
1584 | ||
4826857f | 1585 | dma_unmap_single(&priv->ofdev->dev, |
4669bc90 DH |
1586 | bdp->bufPtr, |
1587 | bdp->length, | |
1588 | DMA_TO_DEVICE); | |
81183059 | 1589 | |
4669bc90 DH |
1590 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
1591 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 1592 | |
4669bc90 | 1593 | for (i = 0; i < frags; i++) { |
4826857f | 1594 | dma_unmap_page(&priv->ofdev->dev, |
4669bc90 DH |
1595 | bdp->bufPtr, |
1596 | bdp->length, | |
1597 | DMA_TO_DEVICE); | |
1598 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
1599 | bdp = next_txbd(bdp, base, tx_ring_size); | |
1600 | } | |
1da177e4 | 1601 | |
0fd56bb5 AF |
1602 | /* |
1603 | * If there's room in the queue (limit it to rx_buffer_size) | |
1604 | * we add this skb back into the pool, if it's the right size | |
1605 | */ | |
1606 | if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size && | |
1607 | skb_recycle_check(skb, priv->rx_buffer_size + | |
1608 | RXBUF_ALIGNMENT)) | |
1609 | __skb_queue_head(&priv->rx_recycle, skb); | |
1610 | else | |
1611 | dev_kfree_skb_any(skb); | |
1612 | ||
4669bc90 | 1613 | priv->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 1614 | |
4669bc90 DH |
1615 | skb_dirtytx = (skb_dirtytx + 1) & |
1616 | TX_RING_MOD_MASK(tx_ring_size); | |
1617 | ||
1618 | howmany++; | |
1619 | priv->num_txbdfree += frags + 1; | |
1620 | } | |
1da177e4 | 1621 | |
4669bc90 DH |
1622 | /* If we freed a buffer, we can restart transmission, if necessary */ |
1623 | if (netif_queue_stopped(dev) && priv->num_txbdfree) | |
1624 | netif_wake_queue(dev); | |
1da177e4 | 1625 | |
4669bc90 DH |
1626 | /* Update dirty indicators */ |
1627 | priv->skb_dirtytx = skb_dirtytx; | |
1628 | priv->dirty_tx = bdp; | |
1da177e4 | 1629 | |
d080cd63 DH |
1630 | dev->stats.tx_packets += howmany; |
1631 | ||
1632 | return howmany; | |
1633 | } | |
1634 | ||
8c7396ae | 1635 | static void gfar_schedule_cleanup(struct net_device *dev) |
d080cd63 | 1636 | { |
d080cd63 | 1637 | struct gfar_private *priv = netdev_priv(dev); |
a6d0b91a AV |
1638 | unsigned long flags; |
1639 | ||
1640 | spin_lock_irqsave(&priv->txlock, flags); | |
1641 | spin_lock(&priv->rxlock); | |
1642 | ||
288379f0 | 1643 | if (napi_schedule_prep(&priv->napi)) { |
8c7396ae | 1644 | gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED); |
288379f0 | 1645 | __napi_schedule(&priv->napi); |
8707bdd4 JP |
1646 | } else { |
1647 | /* | |
1648 | * Clear IEVENT, so interrupts aren't called again | |
1649 | * because of the packets that have already arrived. | |
1650 | */ | |
1651 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
2f448911 | 1652 | } |
a6d0b91a AV |
1653 | |
1654 | spin_unlock(&priv->rxlock); | |
1655 | spin_unlock_irqrestore(&priv->txlock, flags); | |
8c7396ae | 1656 | } |
1da177e4 | 1657 | |
8c7396ae DH |
1658 | /* Interrupt Handler for Transmit complete */ |
1659 | static irqreturn_t gfar_transmit(int irq, void *dev_id) | |
1660 | { | |
1661 | gfar_schedule_cleanup((struct net_device *)dev_id); | |
1da177e4 LT |
1662 | return IRQ_HANDLED; |
1663 | } | |
1664 | ||
815b97c6 AF |
1665 | static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp, |
1666 | struct sk_buff *skb) | |
1667 | { | |
1668 | struct gfar_private *priv = netdev_priv(dev); | |
5a5efed4 | 1669 | u32 lstatus; |
815b97c6 | 1670 | |
4826857f | 1671 | bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data, |
815b97c6 AF |
1672 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1673 | ||
5a5efed4 | 1674 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); |
815b97c6 AF |
1675 | |
1676 | if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1) | |
5a5efed4 | 1677 | lstatus |= BD_LFLAG(RXBD_WRAP); |
815b97c6 AF |
1678 | |
1679 | eieio(); | |
1680 | ||
5a5efed4 | 1681 | bdp->lstatus = lstatus; |
815b97c6 AF |
1682 | } |
1683 | ||
1684 | ||
1685 | struct sk_buff * gfar_new_skb(struct net_device *dev) | |
1da177e4 | 1686 | { |
7f7f5316 | 1687 | unsigned int alignamount; |
1da177e4 LT |
1688 | struct gfar_private *priv = netdev_priv(dev); |
1689 | struct sk_buff *skb = NULL; | |
1da177e4 | 1690 | |
0fd56bb5 AF |
1691 | skb = __skb_dequeue(&priv->rx_recycle); |
1692 | if (!skb) | |
1693 | skb = netdev_alloc_skb(dev, | |
1694 | priv->rx_buffer_size + RXBUF_ALIGNMENT); | |
1da177e4 | 1695 | |
815b97c6 | 1696 | if (!skb) |
1da177e4 LT |
1697 | return NULL; |
1698 | ||
7f7f5316 | 1699 | alignamount = RXBUF_ALIGNMENT - |
bea3348e | 1700 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)); |
7f7f5316 | 1701 | |
1da177e4 LT |
1702 | /* We need the data buffer to be aligned properly. We will reserve |
1703 | * as many bytes as needed to align the data properly | |
1704 | */ | |
7f7f5316 | 1705 | skb_reserve(skb, alignamount); |
1da177e4 | 1706 | |
1da177e4 LT |
1707 | return skb; |
1708 | } | |
1709 | ||
298e1a9e | 1710 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 1711 | { |
298e1a9e | 1712 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 1713 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
1714 | struct gfar_extra_stats *estats = &priv->extra_stats; |
1715 | ||
1716 | /* If the packet was truncated, none of the other errors | |
1717 | * matter */ | |
1718 | if (status & RXBD_TRUNCATED) { | |
1719 | stats->rx_length_errors++; | |
1720 | ||
1721 | estats->rx_trunc++; | |
1722 | ||
1723 | return; | |
1724 | } | |
1725 | /* Count the errors, if there were any */ | |
1726 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
1727 | stats->rx_length_errors++; | |
1728 | ||
1729 | if (status & RXBD_LARGE) | |
1730 | estats->rx_large++; | |
1731 | else | |
1732 | estats->rx_short++; | |
1733 | } | |
1734 | if (status & RXBD_NONOCTET) { | |
1735 | stats->rx_frame_errors++; | |
1736 | estats->rx_nonoctet++; | |
1737 | } | |
1738 | if (status & RXBD_CRCERR) { | |
1739 | estats->rx_crcerr++; | |
1740 | stats->rx_crc_errors++; | |
1741 | } | |
1742 | if (status & RXBD_OVERRUN) { | |
1743 | estats->rx_overrun++; | |
1744 | stats->rx_crc_errors++; | |
1745 | } | |
1746 | } | |
1747 | ||
7d12e780 | 1748 | irqreturn_t gfar_receive(int irq, void *dev_id) |
1da177e4 | 1749 | { |
8c7396ae | 1750 | gfar_schedule_cleanup((struct net_device *)dev_id); |
1da177e4 LT |
1751 | return IRQ_HANDLED; |
1752 | } | |
1753 | ||
0bbaf069 KG |
1754 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
1755 | { | |
1756 | /* If valid headers were found, and valid sums | |
1757 | * were verified, then we tell the kernel that no | |
1758 | * checksumming is necessary. Otherwise, it is */ | |
7f7f5316 | 1759 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
1760 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
1761 | else | |
1762 | skb->ip_summed = CHECKSUM_NONE; | |
1763 | } | |
1764 | ||
1765 | ||
1da177e4 LT |
1766 | /* gfar_process_frame() -- handle one incoming packet if skb |
1767 | * isn't NULL. */ | |
1768 | static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, | |
2c2db48a | 1769 | int amount_pull) |
1da177e4 LT |
1770 | { |
1771 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1772 | struct rxfcb *fcb = NULL; |
1da177e4 | 1773 | |
2c2db48a | 1774 | int ret; |
1da177e4 | 1775 | |
2c2db48a DH |
1776 | /* fcb is at the beginning if exists */ |
1777 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 1778 | |
2c2db48a DH |
1779 | /* Remove the FCB from the skb */ |
1780 | /* Remove the padded bytes, if there are any */ | |
1781 | if (amount_pull) | |
1782 | skb_pull(skb, amount_pull); | |
0bbaf069 | 1783 | |
2c2db48a DH |
1784 | if (priv->rx_csum_enable) |
1785 | gfar_rx_checksum(skb, fcb); | |
0bbaf069 | 1786 | |
2c2db48a DH |
1787 | /* Tell the skb what kind of packet this is */ |
1788 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 1789 | |
2c2db48a DH |
1790 | /* Send the packet up the stack */ |
1791 | if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) | |
1792 | ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl); | |
1793 | else | |
1794 | ret = netif_receive_skb(skb); | |
0bbaf069 | 1795 | |
2c2db48a DH |
1796 | if (NET_RX_DROP == ret) |
1797 | priv->extra_stats.kernel_dropped++; | |
1da177e4 LT |
1798 | |
1799 | return 0; | |
1800 | } | |
1801 | ||
1802 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
0bbaf069 | 1803 | * until the budget/quota has been reached. Returns the number |
1da177e4 LT |
1804 | * of frames handled |
1805 | */ | |
0bbaf069 | 1806 | int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit) |
1da177e4 | 1807 | { |
31de198b | 1808 | struct rxbd8 *bdp, *base; |
1da177e4 | 1809 | struct sk_buff *skb; |
2c2db48a DH |
1810 | int pkt_len; |
1811 | int amount_pull; | |
1da177e4 LT |
1812 | int howmany = 0; |
1813 | struct gfar_private *priv = netdev_priv(dev); | |
1814 | ||
1815 | /* Get the first full descriptor */ | |
1816 | bdp = priv->cur_rx; | |
31de198b | 1817 | base = priv->rx_bd_base; |
1da177e4 | 1818 | |
2c2db48a DH |
1819 | amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) + |
1820 | priv->padding; | |
1821 | ||
1da177e4 | 1822 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 1823 | struct sk_buff *newskb; |
3b6330ce | 1824 | rmb(); |
815b97c6 AF |
1825 | |
1826 | /* Add another skb for the future */ | |
1827 | newskb = gfar_new_skb(dev); | |
1828 | ||
1da177e4 LT |
1829 | skb = priv->rx_skbuff[priv->skb_currx]; |
1830 | ||
4826857f | 1831 | dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr, |
81183059 AF |
1832 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1833 | ||
815b97c6 AF |
1834 | /* We drop the frame if we failed to allocate a new buffer */ |
1835 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
1836 | bdp->status & RXBD_ERR)) { | |
1837 | count_errors(bdp->status, dev); | |
1838 | ||
1839 | if (unlikely(!newskb)) | |
1840 | newskb = skb; | |
4e2fd555 LB |
1841 | else if (skb) { |
1842 | /* | |
1843 | * We need to reset ->data to what it | |
1844 | * was before gfar_new_skb() re-aligned | |
1845 | * it to an RXBUF_ALIGNMENT boundary | |
1846 | * before we put the skb back on the | |
1847 | * recycle list. | |
1848 | */ | |
1849 | skb->data = skb->head + NET_SKB_PAD; | |
0fd56bb5 | 1850 | __skb_queue_head(&priv->rx_recycle, skb); |
4e2fd555 | 1851 | } |
815b97c6 | 1852 | } else { |
1da177e4 | 1853 | /* Increment the number of packets */ |
09f75cd7 | 1854 | dev->stats.rx_packets++; |
1da177e4 LT |
1855 | howmany++; |
1856 | ||
2c2db48a DH |
1857 | if (likely(skb)) { |
1858 | pkt_len = bdp->length - ETH_FCS_LEN; | |
1859 | /* Remove the FCS from the packet length */ | |
1860 | skb_put(skb, pkt_len); | |
1861 | dev->stats.rx_bytes += pkt_len; | |
1da177e4 | 1862 | |
1577ecef AF |
1863 | if (in_irq() || irqs_disabled()) |
1864 | printk("Interrupt problem!\n"); | |
2c2db48a DH |
1865 | gfar_process_frame(dev, skb, amount_pull); |
1866 | ||
1867 | } else { | |
1868 | if (netif_msg_rx_err(priv)) | |
1869 | printk(KERN_WARNING | |
1870 | "%s: Missing skb!\n", dev->name); | |
1871 | dev->stats.rx_dropped++; | |
1872 | priv->extra_stats.rx_skbmissing++; | |
1873 | } | |
1da177e4 | 1874 | |
1da177e4 LT |
1875 | } |
1876 | ||
815b97c6 | 1877 | priv->rx_skbuff[priv->skb_currx] = newskb; |
1da177e4 | 1878 | |
815b97c6 AF |
1879 | /* Setup the new bdp */ |
1880 | gfar_new_rxbdp(dev, bdp, newskb); | |
1da177e4 LT |
1881 | |
1882 | /* Update to the next pointer */ | |
31de198b | 1883 | bdp = next_bd(bdp, base, priv->rx_ring_size); |
1da177e4 LT |
1884 | |
1885 | /* update to point at the next skb */ | |
1886 | priv->skb_currx = | |
815b97c6 AF |
1887 | (priv->skb_currx + 1) & |
1888 | RX_RING_MOD_MASK(priv->rx_ring_size); | |
1da177e4 LT |
1889 | } |
1890 | ||
1891 | /* Update the current rxbd pointer to be the next one */ | |
1892 | priv->cur_rx = bdp; | |
1893 | ||
1da177e4 LT |
1894 | return howmany; |
1895 | } | |
1896 | ||
bea3348e | 1897 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 1898 | { |
bea3348e | 1899 | struct gfar_private *priv = container_of(napi, struct gfar_private, napi); |
4826857f | 1900 | struct net_device *dev = priv->ndev; |
42199884 AF |
1901 | int tx_cleaned = 0; |
1902 | int rx_cleaned = 0; | |
d080cd63 DH |
1903 | unsigned long flags; |
1904 | ||
8c7396ae DH |
1905 | /* Clear IEVENT, so interrupts aren't called again |
1906 | * because of the packets that have already arrived */ | |
1907 | gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK); | |
1908 | ||
d080cd63 DH |
1909 | /* If we fail to get the lock, don't bother with the TX BDs */ |
1910 | if (spin_trylock_irqsave(&priv->txlock, flags)) { | |
42199884 | 1911 | tx_cleaned = gfar_clean_tx_ring(dev); |
d080cd63 DH |
1912 | spin_unlock_irqrestore(&priv->txlock, flags); |
1913 | } | |
1da177e4 | 1914 | |
42199884 | 1915 | rx_cleaned = gfar_clean_rx_ring(dev, budget); |
1da177e4 | 1916 | |
42199884 AF |
1917 | if (tx_cleaned) |
1918 | return budget; | |
1919 | ||
1920 | if (rx_cleaned < budget) { | |
288379f0 | 1921 | napi_complete(napi); |
1da177e4 LT |
1922 | |
1923 | /* Clear the halt bit in RSTAT */ | |
1924 | gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT); | |
1925 | ||
1926 | gfar_write(&priv->regs->imask, IMASK_DEFAULT); | |
1927 | ||
1928 | /* If we are coalescing interrupts, update the timer */ | |
1929 | /* Otherwise, clear it */ | |
2f448911 AF |
1930 | if (likely(priv->rxcoalescing)) { |
1931 | gfar_write(&priv->regs->rxic, 0); | |
b46a8454 | 1932 | gfar_write(&priv->regs->rxic, priv->rxic); |
2f448911 | 1933 | } |
8c7396ae DH |
1934 | if (likely(priv->txcoalescing)) { |
1935 | gfar_write(&priv->regs->txic, 0); | |
1936 | gfar_write(&priv->regs->txic, priv->txic); | |
1937 | } | |
1da177e4 LT |
1938 | } |
1939 | ||
42199884 | 1940 | return rx_cleaned; |
1da177e4 | 1941 | } |
1da177e4 | 1942 | |
f2d71c2d VW |
1943 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1944 | /* | |
1945 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1946 | * without having to re-enable interrupts. It's not called while | |
1947 | * the interrupt routine is executing. | |
1948 | */ | |
1949 | static void gfar_netpoll(struct net_device *dev) | |
1950 | { | |
1951 | struct gfar_private *priv = netdev_priv(dev); | |
1952 | ||
1953 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 1954 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
f2d71c2d VW |
1955 | disable_irq(priv->interruptTransmit); |
1956 | disable_irq(priv->interruptReceive); | |
1957 | disable_irq(priv->interruptError); | |
1958 | gfar_interrupt(priv->interruptTransmit, dev); | |
1959 | enable_irq(priv->interruptError); | |
1960 | enable_irq(priv->interruptReceive); | |
1961 | enable_irq(priv->interruptTransmit); | |
1962 | } else { | |
1963 | disable_irq(priv->interruptTransmit); | |
1964 | gfar_interrupt(priv->interruptTransmit, dev); | |
1965 | enable_irq(priv->interruptTransmit); | |
1966 | } | |
1967 | } | |
1968 | #endif | |
1969 | ||
1da177e4 | 1970 | /* The interrupt handler for devices with one interrupt */ |
7d12e780 | 1971 | static irqreturn_t gfar_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1972 | { |
1973 | struct net_device *dev = dev_id; | |
1974 | struct gfar_private *priv = netdev_priv(dev); | |
1975 | ||
1976 | /* Save ievent for future reference */ | |
1977 | u32 events = gfar_read(&priv->regs->ievent); | |
1978 | ||
1da177e4 | 1979 | /* Check for reception */ |
538cc7ee | 1980 | if (events & IEVENT_RX_MASK) |
7d12e780 | 1981 | gfar_receive(irq, dev_id); |
1da177e4 LT |
1982 | |
1983 | /* Check for transmit completion */ | |
538cc7ee | 1984 | if (events & IEVENT_TX_MASK) |
7d12e780 | 1985 | gfar_transmit(irq, dev_id); |
1da177e4 | 1986 | |
538cc7ee SS |
1987 | /* Check for errors */ |
1988 | if (events & IEVENT_ERR_MASK) | |
1989 | gfar_error(irq, dev_id); | |
1da177e4 LT |
1990 | |
1991 | return IRQ_HANDLED; | |
1992 | } | |
1993 | ||
1da177e4 LT |
1994 | /* Called every time the controller might need to be made |
1995 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 1996 | * information through variables in the phydev structure, and this |
1da177e4 LT |
1997 | * function converts those variables into the appropriate |
1998 | * register values, and can bring down the device if needed. | |
1999 | */ | |
2000 | static void adjust_link(struct net_device *dev) | |
2001 | { | |
2002 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2003 | struct gfar __iomem *regs = priv->regs; |
bb40dcbb AF |
2004 | unsigned long flags; |
2005 | struct phy_device *phydev = priv->phydev; | |
2006 | int new_state = 0; | |
2007 | ||
fef6108d | 2008 | spin_lock_irqsave(&priv->txlock, flags); |
bb40dcbb AF |
2009 | if (phydev->link) { |
2010 | u32 tempval = gfar_read(®s->maccfg2); | |
7f7f5316 | 2011 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 2012 | |
1da177e4 LT |
2013 | /* Now we make sure that we can be in full duplex mode. |
2014 | * If not, we operate in half-duplex mode. */ | |
bb40dcbb AF |
2015 | if (phydev->duplex != priv->oldduplex) { |
2016 | new_state = 1; | |
2017 | if (!(phydev->duplex)) | |
1da177e4 | 2018 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 2019 | else |
1da177e4 | 2020 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 2021 | |
bb40dcbb | 2022 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
2023 | } |
2024 | ||
bb40dcbb AF |
2025 | if (phydev->speed != priv->oldspeed) { |
2026 | new_state = 1; | |
2027 | switch (phydev->speed) { | |
1da177e4 | 2028 | case 1000: |
1da177e4 LT |
2029 | tempval = |
2030 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
2031 | |
2032 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2033 | break; |
2034 | case 100: | |
2035 | case 10: | |
1da177e4 LT |
2036 | tempval = |
2037 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
2038 | |
2039 | /* Reduced mode distinguishes | |
2040 | * between 10 and 100 */ | |
2041 | if (phydev->speed == SPEED_100) | |
2042 | ecntrl |= ECNTRL_R100; | |
2043 | else | |
2044 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
2045 | break; |
2046 | default: | |
0bbaf069 KG |
2047 | if (netif_msg_link(priv)) |
2048 | printk(KERN_WARNING | |
bb40dcbb AF |
2049 | "%s: Ack! Speed (%d) is not 10/100/1000!\n", |
2050 | dev->name, phydev->speed); | |
1da177e4 LT |
2051 | break; |
2052 | } | |
2053 | ||
bb40dcbb | 2054 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
2055 | } |
2056 | ||
bb40dcbb | 2057 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 2058 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 2059 | |
1da177e4 | 2060 | if (!priv->oldlink) { |
bb40dcbb | 2061 | new_state = 1; |
1da177e4 | 2062 | priv->oldlink = 1; |
1da177e4 | 2063 | } |
bb40dcbb AF |
2064 | } else if (priv->oldlink) { |
2065 | new_state = 1; | |
2066 | priv->oldlink = 0; | |
2067 | priv->oldspeed = 0; | |
2068 | priv->oldduplex = -1; | |
1da177e4 | 2069 | } |
1da177e4 | 2070 | |
bb40dcbb AF |
2071 | if (new_state && netif_msg_link(priv)) |
2072 | phy_print_status(phydev); | |
2073 | ||
fef6108d | 2074 | spin_unlock_irqrestore(&priv->txlock, flags); |
bb40dcbb | 2075 | } |
1da177e4 LT |
2076 | |
2077 | /* Update the hash table based on the current list of multicast | |
2078 | * addresses we subscribe to. Also, change the promiscuity of | |
2079 | * the device based on the flags (this function is called | |
2080 | * whenever dev->flags is changed */ | |
2081 | static void gfar_set_multi(struct net_device *dev) | |
2082 | { | |
2083 | struct dev_mc_list *mc_ptr; | |
2084 | struct gfar_private *priv = netdev_priv(dev); | |
cc8c6e37 | 2085 | struct gfar __iomem *regs = priv->regs; |
1da177e4 LT |
2086 | u32 tempval; |
2087 | ||
2088 | if(dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2089 | /* Set RCTRL to PROM */ |
2090 | tempval = gfar_read(®s->rctrl); | |
2091 | tempval |= RCTRL_PROM; | |
2092 | gfar_write(®s->rctrl, tempval); | |
2093 | } else { | |
2094 | /* Set RCTRL to not PROM */ | |
2095 | tempval = gfar_read(®s->rctrl); | |
2096 | tempval &= ~(RCTRL_PROM); | |
2097 | gfar_write(®s->rctrl, tempval); | |
2098 | } | |
6aa20a22 | 2099 | |
1da177e4 LT |
2100 | if(dev->flags & IFF_ALLMULTI) { |
2101 | /* Set the hash to rx all multicast frames */ | |
0bbaf069 KG |
2102 | gfar_write(®s->igaddr0, 0xffffffff); |
2103 | gfar_write(®s->igaddr1, 0xffffffff); | |
2104 | gfar_write(®s->igaddr2, 0xffffffff); | |
2105 | gfar_write(®s->igaddr3, 0xffffffff); | |
2106 | gfar_write(®s->igaddr4, 0xffffffff); | |
2107 | gfar_write(®s->igaddr5, 0xffffffff); | |
2108 | gfar_write(®s->igaddr6, 0xffffffff); | |
2109 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
2110 | gfar_write(®s->gaddr0, 0xffffffff); |
2111 | gfar_write(®s->gaddr1, 0xffffffff); | |
2112 | gfar_write(®s->gaddr2, 0xffffffff); | |
2113 | gfar_write(®s->gaddr3, 0xffffffff); | |
2114 | gfar_write(®s->gaddr4, 0xffffffff); | |
2115 | gfar_write(®s->gaddr5, 0xffffffff); | |
2116 | gfar_write(®s->gaddr6, 0xffffffff); | |
2117 | gfar_write(®s->gaddr7, 0xffffffff); | |
2118 | } else { | |
7f7f5316 AF |
2119 | int em_num; |
2120 | int idx; | |
2121 | ||
1da177e4 | 2122 | /* zero out the hash */ |
0bbaf069 KG |
2123 | gfar_write(®s->igaddr0, 0x0); |
2124 | gfar_write(®s->igaddr1, 0x0); | |
2125 | gfar_write(®s->igaddr2, 0x0); | |
2126 | gfar_write(®s->igaddr3, 0x0); | |
2127 | gfar_write(®s->igaddr4, 0x0); | |
2128 | gfar_write(®s->igaddr5, 0x0); | |
2129 | gfar_write(®s->igaddr6, 0x0); | |
2130 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
2131 | gfar_write(®s->gaddr0, 0x0); |
2132 | gfar_write(®s->gaddr1, 0x0); | |
2133 | gfar_write(®s->gaddr2, 0x0); | |
2134 | gfar_write(®s->gaddr3, 0x0); | |
2135 | gfar_write(®s->gaddr4, 0x0); | |
2136 | gfar_write(®s->gaddr5, 0x0); | |
2137 | gfar_write(®s->gaddr6, 0x0); | |
2138 | gfar_write(®s->gaddr7, 0x0); | |
2139 | ||
7f7f5316 AF |
2140 | /* If we have extended hash tables, we need to |
2141 | * clear the exact match registers to prepare for | |
2142 | * setting them */ | |
2143 | if (priv->extended_hash) { | |
2144 | em_num = GFAR_EM_NUM + 1; | |
2145 | gfar_clear_exact_match(dev); | |
2146 | idx = 1; | |
2147 | } else { | |
2148 | idx = 0; | |
2149 | em_num = 0; | |
2150 | } | |
2151 | ||
1da177e4 LT |
2152 | if(dev->mc_count == 0) |
2153 | return; | |
2154 | ||
2155 | /* Parse the list, and set the appropriate bits */ | |
2156 | for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | |
7f7f5316 AF |
2157 | if (idx < em_num) { |
2158 | gfar_set_mac_for_addr(dev, idx, | |
2159 | mc_ptr->dmi_addr); | |
2160 | idx++; | |
2161 | } else | |
2162 | gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr); | |
1da177e4 LT |
2163 | } |
2164 | } | |
2165 | ||
2166 | return; | |
2167 | } | |
2168 | ||
7f7f5316 AF |
2169 | |
2170 | /* Clears each of the exact match registers to zero, so they | |
2171 | * don't interfere with normal reception */ | |
2172 | static void gfar_clear_exact_match(struct net_device *dev) | |
2173 | { | |
2174 | int idx; | |
2175 | u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0}; | |
2176 | ||
2177 | for(idx = 1;idx < GFAR_EM_NUM + 1;idx++) | |
2178 | gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr); | |
2179 | } | |
2180 | ||
1da177e4 LT |
2181 | /* Set the appropriate hash bit for the given addr */ |
2182 | /* The algorithm works like so: | |
2183 | * 1) Take the Destination Address (ie the multicast address), and | |
2184 | * do a CRC on it (little endian), and reverse the bits of the | |
2185 | * result. | |
2186 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
2187 | * table. The table is controlled through 8 32-bit registers: | |
2188 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
2189 | * gaddr7. This means that the 3 most significant bits in the | |
2190 | * hash index which gaddr register to use, and the 5 other bits | |
2191 | * indicate which bit (assuming an IBM numbering scheme, which | |
2192 | * for PowerPC (tm) is usually the case) in the register holds | |
2193 | * the entry. */ | |
2194 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) | |
2195 | { | |
2196 | u32 tempval; | |
2197 | struct gfar_private *priv = netdev_priv(dev); | |
1da177e4 | 2198 | u32 result = ether_crc(MAC_ADDR_LEN, addr); |
0bbaf069 KG |
2199 | int width = priv->hash_width; |
2200 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
2201 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
2202 | u32 value = (1 << (31-whichbit)); |
2203 | ||
0bbaf069 | 2204 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 2205 | tempval |= value; |
0bbaf069 | 2206 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
2207 | |
2208 | return; | |
2209 | } | |
2210 | ||
7f7f5316 AF |
2211 | |
2212 | /* There are multiple MAC Address register pairs on some controllers | |
2213 | * This function sets the numth pair to a given address | |
2214 | */ | |
2215 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr) | |
2216 | { | |
2217 | struct gfar_private *priv = netdev_priv(dev); | |
2218 | int idx; | |
2219 | char tmpbuf[MAC_ADDR_LEN]; | |
2220 | u32 tempval; | |
cc8c6e37 | 2221 | u32 __iomem *macptr = &priv->regs->macstnaddr1; |
7f7f5316 AF |
2222 | |
2223 | macptr += num*2; | |
2224 | ||
2225 | /* Now copy it into the mac registers backwards, cuz */ | |
2226 | /* little endian is silly */ | |
2227 | for (idx = 0; idx < MAC_ADDR_LEN; idx++) | |
2228 | tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx]; | |
2229 | ||
2230 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
2231 | ||
2232 | tempval = *((u32 *) (tmpbuf + 4)); | |
2233 | ||
2234 | gfar_write(macptr+1, tempval); | |
2235 | } | |
2236 | ||
1da177e4 | 2237 | /* GFAR error interrupt handler */ |
7d12e780 | 2238 | static irqreturn_t gfar_error(int irq, void *dev_id) |
1da177e4 LT |
2239 | { |
2240 | struct net_device *dev = dev_id; | |
2241 | struct gfar_private *priv = netdev_priv(dev); | |
2242 | ||
2243 | /* Save ievent for future reference */ | |
2244 | u32 events = gfar_read(&priv->regs->ievent); | |
2245 | ||
2246 | /* Clear IEVENT */ | |
d87eb127 SW |
2247 | gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK); |
2248 | ||
2249 | /* Magic Packet is not an error. */ | |
b31a1d8b | 2250 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
2251 | (events & IEVENT_MAG)) |
2252 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
2253 | |
2254 | /* Hmm... */ | |
0bbaf069 KG |
2255 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
2256 | printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
538cc7ee | 2257 | dev->name, events, gfar_read(&priv->regs->imask)); |
1da177e4 LT |
2258 | |
2259 | /* Update the error counters */ | |
2260 | if (events & IEVENT_TXE) { | |
09f75cd7 | 2261 | dev->stats.tx_errors++; |
1da177e4 LT |
2262 | |
2263 | if (events & IEVENT_LC) | |
09f75cd7 | 2264 | dev->stats.tx_window_errors++; |
1da177e4 | 2265 | if (events & IEVENT_CRL) |
09f75cd7 | 2266 | dev->stats.tx_aborted_errors++; |
1da177e4 | 2267 | if (events & IEVENT_XFUN) { |
0bbaf069 | 2268 | if (netif_msg_tx_err(priv)) |
538cc7ee SS |
2269 | printk(KERN_DEBUG "%s: TX FIFO underrun, " |
2270 | "packet dropped.\n", dev->name); | |
09f75cd7 | 2271 | dev->stats.tx_dropped++; |
1da177e4 LT |
2272 | priv->extra_stats.tx_underrun++; |
2273 | ||
2274 | /* Reactivate the Tx Queues */ | |
2275 | gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT); | |
2276 | } | |
0bbaf069 KG |
2277 | if (netif_msg_tx_err(priv)) |
2278 | printk(KERN_DEBUG "%s: Transmit Error\n", dev->name); | |
1da177e4 LT |
2279 | } |
2280 | if (events & IEVENT_BSY) { | |
09f75cd7 | 2281 | dev->stats.rx_errors++; |
1da177e4 LT |
2282 | priv->extra_stats.rx_bsy++; |
2283 | ||
7d12e780 | 2284 | gfar_receive(irq, dev_id); |
1da177e4 | 2285 | |
0bbaf069 | 2286 | if (netif_msg_rx_err(priv)) |
538cc7ee SS |
2287 | printk(KERN_DEBUG "%s: busy error (rstat: %x)\n", |
2288 | dev->name, gfar_read(&priv->regs->rstat)); | |
1da177e4 LT |
2289 | } |
2290 | if (events & IEVENT_BABR) { | |
09f75cd7 | 2291 | dev->stats.rx_errors++; |
1da177e4 LT |
2292 | priv->extra_stats.rx_babr++; |
2293 | ||
0bbaf069 | 2294 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2295 | printk(KERN_DEBUG "%s: babbling RX error\n", dev->name); |
1da177e4 LT |
2296 | } |
2297 | if (events & IEVENT_EBERR) { | |
2298 | priv->extra_stats.eberr++; | |
0bbaf069 | 2299 | if (netif_msg_rx_err(priv)) |
538cc7ee | 2300 | printk(KERN_DEBUG "%s: bus error\n", dev->name); |
1da177e4 | 2301 | } |
0bbaf069 | 2302 | if ((events & IEVENT_RXC) && netif_msg_rx_status(priv)) |
538cc7ee | 2303 | printk(KERN_DEBUG "%s: control frame\n", dev->name); |
1da177e4 LT |
2304 | |
2305 | if (events & IEVENT_BABT) { | |
2306 | priv->extra_stats.tx_babt++; | |
0bbaf069 | 2307 | if (netif_msg_tx_err(priv)) |
538cc7ee | 2308 | printk(KERN_DEBUG "%s: babbling TX error\n", dev->name); |
1da177e4 LT |
2309 | } |
2310 | return IRQ_HANDLED; | |
2311 | } | |
2312 | ||
72abb461 KS |
2313 | /* work with hotplug and coldplug */ |
2314 | MODULE_ALIAS("platform:fsl-gianfar"); | |
2315 | ||
b31a1d8b AF |
2316 | static struct of_device_id gfar_match[] = |
2317 | { | |
2318 | { | |
2319 | .type = "network", | |
2320 | .compatible = "gianfar", | |
2321 | }, | |
2322 | {}, | |
2323 | }; | |
2324 | ||
1da177e4 | 2325 | /* Structure for a device driver */ |
b31a1d8b AF |
2326 | static struct of_platform_driver gfar_driver = { |
2327 | .name = "fsl-gianfar", | |
2328 | .match_table = gfar_match, | |
2329 | ||
1da177e4 LT |
2330 | .probe = gfar_probe, |
2331 | .remove = gfar_remove, | |
d87eb127 SW |
2332 | .suspend = gfar_suspend, |
2333 | .resume = gfar_resume, | |
1da177e4 LT |
2334 | }; |
2335 | ||
2336 | static int __init gfar_init(void) | |
2337 | { | |
1577ecef | 2338 | return of_register_platform_driver(&gfar_driver); |
1da177e4 LT |
2339 | } |
2340 | ||
2341 | static void __exit gfar_exit(void) | |
2342 | { | |
b31a1d8b | 2343 | of_unregister_platform_driver(&gfar_driver); |
1da177e4 LT |
2344 | } |
2345 | ||
2346 | module_init(gfar_init); | |
2347 | module_exit(gfar_exit); | |
2348 |