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0bbaf069 1/*
1da177e4
LT		 2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
a12f801d
SG		 13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
1da177e4 65#include <linux/kernel.h>
1da177e4
LT		 66#include <linux/string.h>
67#include <linux/errno.h>
bb40dcbb 68#include <linux/unistd.h>
1da177e4
LT		 69#include <linux/slab.h>
70#include <linux/interrupt.h>
71#include <linux/init.h>
72#include <linux/delay.h>
73#include <linux/netdevice.h>
74#include <linux/etherdevice.h>
75#include <linux/skbuff.h>
0bbaf069 76#include <linux/if_vlan.h>
1da177e4
LT		 77#include <linux/spinlock.h>
78#include <linux/mm.h>
fe192a49 79#include <linux/of_mdio.h>
b31a1d8b 80#include <linux/of_platform.h>
0bbaf069
KG		 81#include <linux/ip.h>
82#include <linux/tcp.h>
83#include <linux/udp.h>
9c07b884 84#include <linux/in.h>
1da177e4
LT		 85
86#include <asm/io.h>
87#include <asm/irq.h>
88#include <asm/uaccess.h>
89#include <linux/module.h>
1da177e4
LT		 90#include <linux/dma-mapping.h>
91#include <linux/crc32.h>
bb40dcbb
AF		 92#include <linux/mii.h>
93#include <linux/phy.h>
b31a1d8b
AF		 94#include <linux/phy_fixed.h>
95#include <linux/of.h>
1da177e4
LT		 96
97#include "gianfar.h"
1577ecef 98#include "fsl_pq_mdio.h"
1da177e4
LT		 99
100#define TX_TIMEOUT (1*HZ)
1da177e4
LT		 101#undef BRIEF_GFAR_ERRORS
102#undef VERBOSE_GFAR_ERRORS
103
1da177e4 104const char gfar_driver_name[] = "Gianfar Ethernet";
7f7f5316 105const char gfar_driver_version[] = "1.3";
1da177e4 106
1da177e4
LT		 107static int gfar_enet_open(struct net_device *dev);
108static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 109static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 110static void gfar_timeout(struct net_device *dev);
111static int gfar_close(struct net_device *dev);
815b97c6 112struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 113static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 114 struct sk_buff *skb);
1da177e4
LT		 115static int gfar_set_mac_address(struct net_device *dev);
116static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 117static irqreturn_t gfar_error(int irq, void *dev_id);
118static irqreturn_t gfar_transmit(int irq, void *dev_id);
119static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 120static void adjust_link(struct net_device *dev);
121static void init_registers(struct net_device *dev);
122static int init_phy(struct net_device *dev);
b31a1d8b
AF		 123static int gfar_probe(struct of_device *ofdev,
124 const struct of_device_id *match);
125static int gfar_remove(struct of_device *ofdev);
bb40dcbb 126static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 127static void gfar_set_multi(struct net_device *dev);
128static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 129static void gfar_configure_serdes(struct net_device *dev);
bea3348e 130static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 131#ifdef CONFIG_NET_POLL_CONTROLLER
132static void gfar_netpoll(struct net_device *dev);
133#endif
a12f801d
SG		 134int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a
DH		 136static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull);
0bbaf069
KG		 138static void gfar_vlan_rx_register(struct net_device *netdev,
139 struct vlan_group *grp);
7f7f5316 140void gfar_halt(struct net_device *dev);
d87eb127 141static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 142void gfar_start(struct net_device *dev);
143static void gfar_clear_exact_match(struct net_device *dev);
144static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
26ccfc37 145static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
fba4ed03 146u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
214 pr_err("%s: Can't allocate RX buffers\n",
215 ndev->name);
216 goto err_rxalloc_fail;
217 }
218 rx_queue->rx_skbuff[j] = skb;
219
220 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 221 }
8728327e 222
fba4ed03 223 rxbdp++;
8728327e
AV		 224 }
225
8728327e
AV		 226 }
227
228 return 0;
fba4ed03
SG		 229
230err_rxalloc_fail:
231 free_skb_resources(priv);
232 return -ENOMEM;
8728327e
AV		 233}
234
235static int gfar_alloc_skb_resources(struct net_device *ndev)
236{
826aa4a0 237 void *vaddr;
fba4ed03
SG		 238 dma_addr_t addr;
239 int i, j, k;
826aa4a0
AV		 240 struct gfar_private *priv = netdev_priv(ndev);
241 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 242 struct gfar_priv_tx_q *tx_queue = NULL;
243 struct gfar_priv_rx_q *rx_queue = NULL;
244
fba4ed03
SG		 245 priv->total_tx_ring_size = 0;
246 for (i = 0; i < priv->num_tx_queues; i++)
247 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
248
249 priv->total_rx_ring_size = 0;
250 for (i = 0; i < priv->num_rx_queues; i++)
251 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 252
253 /* Allocate memory for the buffer descriptors */
8728327e 254 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 255 sizeof(struct txbd8) * priv->total_tx_ring_size +
256 sizeof(struct rxbd8) * priv->total_rx_ring_size,
257 &addr, GFP_KERNEL);
826aa4a0
AV		 258 if (!vaddr) {
259 if (netif_msg_ifup(priv))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
261 ndev->name);
262 return -ENOMEM;
263 }
264
fba4ed03
SG		 265 for (i = 0; i < priv->num_tx_queues; i++) {
266 tx_queue = priv->tx_queue[i];
267 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
268 tx_queue->tx_bd_dma_base = addr;
269 tx_queue->dev = ndev;
270 /* enet DMA only understands physical addresses */
271 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
272 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
273 }
826aa4a0 274
826aa4a0 275 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 276 for (i = 0; i < priv->num_rx_queues; i++) {
277 rx_queue = priv->rx_queue[i];
278 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
279 rx_queue->rx_bd_dma_base = addr;
280 rx_queue->dev = ndev;
281 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
282 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
283 }
826aa4a0
AV		 284
285 /* Setup the skbuff rings */
fba4ed03
SG		 286 for (i = 0; i < priv->num_tx_queues; i++) {
287 tx_queue = priv->tx_queue[i];
288 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 289 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03
SG		 290 if (!tx_queue->tx_skbuff) {
291 if (netif_msg_ifup(priv))
292 pr_err("%s: Could not allocate tx_skbuff\n",
293 ndev->name);
294 goto cleanup;
295 }
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 304 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 305
fba4ed03
SG		 306 if (!rx_queue->rx_skbuff) {
307 if (netif_msg_ifup(priv))
308 pr_err("%s: Could not allocate rx_skbuff\n",
309 ndev->name);
310 goto cleanup;
311 }
312
313 for (j = 0; j < rx_queue->rx_ring_size; j++)
314 rx_queue->rx_skbuff[j] = NULL;
315 }
826aa4a0 316
8728327e
AV		 317 if (gfar_init_bds(ndev))
318 goto cleanup;
826aa4a0
AV		 319
320 return 0;
321
322cleanup:
323 free_skb_resources(priv);
324 return -ENOMEM;
325}
326
fba4ed03
SG		 327static void gfar_init_tx_rx_base(struct gfar_private *priv)
328{
46ceb60c 329 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 330 u32 __iomem *baddr;
fba4ed03
SG		 331 int i;
332
333 baddr = &regs->tbase0;
334 for(i = 0; i < priv->num_tx_queues; i++) {
335 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr += 2;
337 }
338
339 baddr = &regs->rbase0;
340 for(i = 0; i < priv->num_rx_queues; i++) {
341 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 baddr += 2;
343 }
344}
345
826aa4a0
AV		 346static void gfar_init_mac(struct net_device *ndev)
347{
348 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 349 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 350 u32 rctrl = 0;
351 u32 tctrl = 0;
352 u32 attrs = 0;
353
fba4ed03
SG		 354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv);
32c513bc 356
826aa4a0 357 /* Configure the coalescing support */
46ceb60c 358 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03
SG		 359
360 if (priv->rx_filer_enable)
361 rctrl |= RCTRL_FILREN;
826aa4a0
AV		 362
363 if (priv->rx_csum_enable)
364 rctrl |= RCTRL_CHECKSUMMING;
365
366 if (priv->extended_hash) {
367 rctrl |= RCTRL_EXTHASH;
368
369 gfar_clear_exact_match(ndev);
370 rctrl |= RCTRL_EMEN;
371 }
372
373 if (priv->padding) {
374 rctrl &= ~RCTRL_PAL_MASK;
375 rctrl |= RCTRL_PADDING(priv->padding);
376 }
377
378 /* keep vlan related bits if it's enabled */
379 if (priv->vlgrp) {
380 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
381 tctrl |= TCTRL_VLINS;
382 }
383
384 /* Init rctrl based on our settings */
385 gfar_write(&regs->rctrl, rctrl);
386
387 if (ndev->features & NETIF_F_IP_CSUM)
388 tctrl |= TCTRL_INIT_CSUM;
389
fba4ed03
SG		 390 tctrl |= TCTRL_TXSCHED_PRIO;
391
826aa4a0
AV		 392 gfar_write(&regs->tctrl, tctrl);
393
394 /* Set the extraction length and index */
395 attrs = ATTRELI_EL(priv->rx_stash_size) |
396 ATTRELI_EI(priv->rx_stash_index);
397
398 gfar_write(&regs->attreli, attrs);
399
400 /* Start with defaults, and add stashing or locking
401 * depending on the approprate variables */
402 attrs = ATTR_INIT_SETTINGS;
403
404 if (priv->bd_stash_en)
405 attrs |= ATTR_BDSTASH;
406
407 if (priv->rx_stash_size != 0)
408 attrs |= ATTR_BUFSTASH;
409
410 gfar_write(&regs->attr, attrs);
411
412 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
413 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
414 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
415}
416
26ccfc37
AF		 417static const struct net_device_ops gfar_netdev_ops = {
418 .ndo_open = gfar_enet_open,
419 .ndo_start_xmit = gfar_start_xmit,
420 .ndo_stop = gfar_close,
421 .ndo_change_mtu = gfar_change_mtu,
422 .ndo_set_multicast_list = gfar_set_multi,
423 .ndo_tx_timeout = gfar_timeout,
424 .ndo_do_ioctl = gfar_ioctl,
fba4ed03 425 .ndo_select_queue = gfar_select_queue,
26ccfc37 426 .ndo_vlan_rx_register = gfar_vlan_rx_register,
240c102d
BH		 427 .ndo_set_mac_address = eth_mac_addr,
428 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 429#ifdef CONFIG_NET_POLL_CONTROLLER
430 .ndo_poll_controller = gfar_netpoll,
431#endif
432};
433
7a8b3372
SG		 434unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
435unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
436
fba4ed03
SG		 437void lock_rx_qs(struct gfar_private *priv)
438{
439 int i = 0x0;
440
441 for (i = 0; i < priv->num_rx_queues; i++)
442 spin_lock(&priv->rx_queue[i]->rxlock);
443}
444
445void lock_tx_qs(struct gfar_private *priv)
446{
447 int i = 0x0;
448
449 for (i = 0; i < priv->num_tx_queues; i++)
450 spin_lock(&priv->tx_queue[i]->txlock);
451}
452
453void unlock_rx_qs(struct gfar_private *priv)
454{
455 int i = 0x0;
456
457 for (i = 0; i < priv->num_rx_queues; i++)
458 spin_unlock(&priv->rx_queue[i]->rxlock);
459}
460
461void unlock_tx_qs(struct gfar_private *priv)
462{
463 int i = 0x0;
464
465 for (i = 0; i < priv->num_tx_queues; i++)
466 spin_unlock(&priv->tx_queue[i]->txlock);
467}
468
7f7f5316
AF		 469/* Returns 1 if incoming frames use an FCB */
470static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 471{
77ecaf2d 472 return priv->vlgrp || priv->rx_csum_enable;
0bbaf069 473}
bb40dcbb 474
fba4ed03
SG		 475u16 gfar_select_queue(struct net_device *dev, struct sk_buff *skb)
476{
477 return skb_get_queue_mapping(skb);
478}
479static void free_tx_pointers(struct gfar_private *priv)
480{
481 int i = 0;
482
483 for (i = 0; i < priv->num_tx_queues; i++)
484 kfree(priv->tx_queue[i]);
485}
486
487static void free_rx_pointers(struct gfar_private *priv)
488{
489 int i = 0;
490
491 for (i = 0; i < priv->num_rx_queues; i++)
492 kfree(priv->rx_queue[i]);
493}
494
46ceb60c
SG		 495static void unmap_group_regs(struct gfar_private *priv)
496{
497 int i = 0;
498
499 for (i = 0; i < MAXGROUPS; i++)
500 if (priv->gfargrp[i].regs)
501 iounmap(priv->gfargrp[i].regs);
502}
503
504static void disable_napi(struct gfar_private *priv)
505{
506 int i = 0;
507
508 for (i = 0; i < priv->num_grps; i++)
509 napi_disable(&priv->gfargrp[i].napi);
510}
511
512static void enable_napi(struct gfar_private *priv)
513{
514 int i = 0;
515
516 for (i = 0; i < priv->num_grps; i++)
517 napi_enable(&priv->gfargrp[i].napi);
518}
519
520static int gfar_parse_group(struct device_node *np,
521 struct gfar_private *priv, const char *model)
522{
523 u32 *queue_mask;
524 u64 addr, size;
525
526 addr = of_translate_address(np,
527 of_get_address(np, 0, &size, NULL));
528 priv->gfargrp[priv->num_grps].regs = ioremap(addr, size);
529
530 if (!priv->gfargrp[priv->num_grps].regs)
531 return -ENOMEM;
532
533 priv->gfargrp[priv->num_grps].interruptTransmit =
534 irq_of_parse_and_map(np, 0);
535
536 /* If we aren't the FEC we have multiple interrupts */
537 if (model && strcasecmp(model, "FEC")) {
538 priv->gfargrp[priv->num_grps].interruptReceive =
539 irq_of_parse_and_map(np, 1);
540 priv->gfargrp[priv->num_grps].interruptError =
541 irq_of_parse_and_map(np,2);
542 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
543 priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
544 priv->gfargrp[priv->num_grps].interruptError < 0) {
545 return -EINVAL;
546 }
547 }
548
549 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
550 priv->gfargrp[priv->num_grps].priv = priv;
551 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
552 if(priv->mode == MQ_MG_MODE) {
553 queue_mask = (u32 *)of_get_property(np,
554 "fsl,rx-bit-map", NULL);
555 priv->gfargrp[priv->num_grps].rx_bit_map =
556 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
557 queue_mask = (u32 *)of_get_property(np,
558 "fsl,tx-bit-map", NULL);
559 priv->gfargrp[priv->num_grps].tx_bit_map =
560 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
561 } else {
562 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
563 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
564 }
565 priv->num_grps++;
566
567 return 0;
568}
569
fba4ed03 570static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
b31a1d8b 571{
b31a1d8b
AF		 572 const char *model;
573 const char *ctype;
574 const void *mac_addr;
fba4ed03
SG		 575 int err = 0, i;
576 struct net_device *dev = NULL;
577 struct gfar_private *priv = NULL;
578 struct device_node *np = ofdev->node;
46ceb60c 579 struct device_node *child = NULL;
4d7902f2
AF		 580 const u32 *stash;
581 const u32 *stash_len;
582 const u32 *stash_idx;
fba4ed03
SG		 583 unsigned int num_tx_qs, num_rx_qs;
584 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 585
586 if (!np || !of_device_is_available(np))
587 return -ENODEV;
588
fba4ed03
SG		 589 /* parse the num of tx and rx queues */
590 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
591 num_tx_qs = tx_queues ? *tx_queues : 1;
592
593 if (num_tx_qs > MAX_TX_QS) {
594 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
595 num_tx_qs, MAX_TX_QS);
596 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
597 return -EINVAL;
598 }
599
600 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
601 num_rx_qs = rx_queues ? *rx_queues : 1;
602
603 if (num_rx_qs > MAX_RX_QS) {
604 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
605 num_tx_qs, MAX_TX_QS);
606 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
607 return -EINVAL;
608 }
609
610 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
611 dev = *pdev;
612 if (NULL == dev)
613 return -ENOMEM;
614
615 priv = netdev_priv(dev);
616 priv->node = ofdev->node;
617 priv->ndev = dev;
618
619 dev->num_tx_queues = num_tx_qs;
620 dev->real_num_tx_queues = num_tx_qs;
621 priv->num_tx_queues = num_tx_qs;
622 priv->num_rx_queues = num_rx_qs;
46ceb60c 623 priv->num_grps = 0x0;
b31a1d8b
AF		 624
625 model = of_get_property(np, "model", NULL);
626
46ceb60c
SG		 627 for (i = 0; i < MAXGROUPS; i++)
628 priv->gfargrp[i].regs = NULL;
b31a1d8b 629
46ceb60c
SG		 630 /* Parse and initialize group specific information */
631 if (of_device_is_compatible(np, "fsl,etsec2")) {
632 priv->mode = MQ_MG_MODE;
633 for_each_child_of_node(np, child) {
634 err = gfar_parse_group(child, priv, model);
635 if (err)
636 goto err_grp_init;
b31a1d8b 637 }
46ceb60c
SG		 638 } else {
639 priv->mode = SQ_SG_MODE;
640 err = gfar_parse_group(np, priv, model);
641 if(err)
642 goto err_grp_init;
b31a1d8b
AF		 643 }
644
fba4ed03
SG		 645 for (i = 0; i < priv->num_tx_queues; i++)
646 priv->tx_queue[i] = NULL;
647 for (i = 0; i < priv->num_rx_queues; i++)
648 priv->rx_queue[i] = NULL;
649
650 for (i = 0; i < priv->num_tx_queues; i++) {
651 priv->tx_queue[i] = (struct gfar_priv_tx_q *)kmalloc(
652 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
653 if (!priv->tx_queue[i]) {
654 err = -ENOMEM;
655 goto tx_alloc_failed;
656 }
657 priv->tx_queue[i]->tx_skbuff = NULL;
658 priv->tx_queue[i]->qindex = i;
659 priv->tx_queue[i]->dev = dev;
660 spin_lock_init(&(priv->tx_queue[i]->txlock));
661 }
662
663 for (i = 0; i < priv->num_rx_queues; i++) {
664 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kmalloc(
665 sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
666 if (!priv->rx_queue[i]) {
667 err = -ENOMEM;
668 goto rx_alloc_failed;
669 }
670 priv->rx_queue[i]->rx_skbuff = NULL;
671 priv->rx_queue[i]->qindex = i;
672 priv->rx_queue[i]->dev = dev;
673 spin_lock_init(&(priv->rx_queue[i]->rxlock));
674 }
675
676
4d7902f2
AF		 677 stash = of_get_property(np, "bd-stash", NULL);
678
a12f801d 679 if (stash) {
4d7902f2
AF		 680 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
681 priv->bd_stash_en = 1;
682 }
683
684 stash_len = of_get_property(np, "rx-stash-len", NULL);
685
686 if (stash_len)
687 priv->rx_stash_size = *stash_len;
688
689 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
690
691 if (stash_idx)
692 priv->rx_stash_index = *stash_idx;
693
694 if (stash_len || stash_idx)
695 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
696
b31a1d8b
AF		 697 mac_addr = of_get_mac_address(np);
698 if (mac_addr)
699 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
700
701 if (model && !strcasecmp(model, "TSEC"))
702 priv->device_flags =
703 FSL_GIANFAR_DEV_HAS_GIGABIT |
704 FSL_GIANFAR_DEV_HAS_COALESCE |
705 FSL_GIANFAR_DEV_HAS_RMON |
706 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
707 if (model && !strcasecmp(model, "eTSEC"))
708 priv->device_flags =
709 FSL_GIANFAR_DEV_HAS_GIGABIT |
710 FSL_GIANFAR_DEV_HAS_COALESCE |
711 FSL_GIANFAR_DEV_HAS_RMON |
712 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 713 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 714 FSL_GIANFAR_DEV_HAS_CSUM |
715 FSL_GIANFAR_DEV_HAS_VLAN |
716 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
717 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
718
719 ctype = of_get_property(np, "phy-connection-type", NULL);
720
721 /* We only care about rgmii-id. The rest are autodetected */
722 if (ctype && !strcmp(ctype, "rgmii-id"))
723 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
724 else
725 priv->interface = PHY_INTERFACE_MODE_MII;
726
727 if (of_get_property(np, "fsl,magic-packet", NULL))
728 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
729
fe192a49 730 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 731
732 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 733 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 734
735 return 0;
736
fba4ed03
SG		 737rx_alloc_failed:
738 free_rx_pointers(priv);
739tx_alloc_failed:
740 free_tx_pointers(priv);
46ceb60c
SG		 741err_grp_init:
742 unmap_group_regs(priv);
fba4ed03 743 free_netdev(dev);
b31a1d8b
AF		 744 return err;
745}
746
0faac9f7
CW		 747/* Ioctl MII Interface */
748static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
749{
750 struct gfar_private *priv = netdev_priv(dev);
751
752 if (!netif_running(dev))
753 return -EINVAL;
754
755 if (!priv->phydev)
756 return -ENODEV;
757
758 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
759}
760
fba4ed03
SG		 761static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
762{
763 unsigned int new_bit_map = 0x0;
764 int mask = 0x1 << (max_qs - 1), i;
765 for (i = 0; i < max_qs; i++) {
766 if (bit_map & mask)
767 new_bit_map = new_bit_map + (1 << i);
768 mask = mask >> 0x1;
769 }
770 return new_bit_map;
771}
7a8b3372 772
18294ad1
AV		 773static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
774 u32 class)
7a8b3372
SG		 775{
776 u32 rqfpr = FPR_FILER_MASK;
777 u32 rqfcr = 0x0;
778
779 rqfar--;
780 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
781 ftp_rqfpr[rqfar] = rqfpr;
782 ftp_rqfcr[rqfar] = rqfcr;
783 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
784
785 rqfar--;
786 rqfcr = RQFCR_CMP_NOMATCH;
787 ftp_rqfpr[rqfar] = rqfpr;
788 ftp_rqfcr[rqfar] = rqfcr;
789 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
790
791 rqfar--;
792 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
793 rqfpr = class;
794 ftp_rqfcr[rqfar] = rqfcr;
795 ftp_rqfpr[rqfar] = rqfpr;
796 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
797
798 rqfar--;
799 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
800 rqfpr = class;
801 ftp_rqfcr[rqfar] = rqfcr;
802 ftp_rqfpr[rqfar] = rqfpr;
803 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
804
805 return rqfar;
806}
807
808static void gfar_init_filer_table(struct gfar_private *priv)
809{
810 int i = 0x0;
811 u32 rqfar = MAX_FILER_IDX;
812 u32 rqfcr = 0x0;
813 u32 rqfpr = FPR_FILER_MASK;
814
815 /* Default rule */
816 rqfcr = RQFCR_CMP_MATCH;
817 ftp_rqfcr[rqfar] = rqfcr;
818 ftp_rqfpr[rqfar] = rqfpr;
819 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
820
821 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
822 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
823 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
824 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
825 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
826 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
827
828 /* cur_filer_idx indicated the fisrt non-masked rule */
829 priv->cur_filer_idx = rqfar;
830
831 /* Rest are masked rules */
832 rqfcr = RQFCR_CMP_NOMATCH;
833 for (i = 0; i < rqfar; i++) {
834 ftp_rqfcr[i] = rqfcr;
835 ftp_rqfpr[i] = rqfpr;
836 gfar_write_filer(priv, i, rqfcr, rqfpr);
837 }
838}
839
bb40dcbb
AF		 840/* Set up the ethernet device structure, private data,
841 * and anything else we need before we start */
b31a1d8b
AF		 842static int gfar_probe(struct of_device *ofdev,
843 const struct of_device_id *match)
1da177e4
LT		 844{
845 u32 tempval;
846 struct net_device *dev = NULL;
847 struct gfar_private *priv = NULL;
f4983704 848 struct gfar __iomem *regs = NULL;
46ceb60c 849 int err = 0, i, grp_idx = 0;
c50a5d9a 850 int len_devname;
fba4ed03 851 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 852 u32 isrg = 0;
18294ad1 853 u32 __iomem *baddr;
1da177e4 854
fba4ed03 855 err = gfar_of_init(ofdev, &dev);
1da177e4 856
fba4ed03
SG		 857 if (err)
858 return err;
1da177e4
LT		 859
860 priv = netdev_priv(dev);
4826857f
KG		 861 priv->ndev = dev;
862 priv->ofdev = ofdev;
b31a1d8b 863 priv->node = ofdev->node;
4826857f 864 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 865
d87eb127 866 spin_lock_init(&priv->bflock);
ab939905 867 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 868
b31a1d8b 869 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 870 regs = priv->gfargrp[0].regs;
1da177e4
LT		 871
872 /* Stop the DMA engine now, in case it was running before */
873 /* (The firmware could have used it, and left it running). */
257d938a 874 gfar_halt(dev);
1da177e4
LT		 875
876 /* Reset MAC layer */
f4983704 877 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 878
b98ac702
AF		 879 /* We need to delay at least 3 TX clocks */
880 udelay(2);
881
1da177e4 882 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 883 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 884
885 /* Initialize MACCFG2. */
f4983704 886 gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
1da177e4
LT		 887
888 /* Initialize ECNTRL */
f4983704 889 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 890
1da177e4 891 /* Set the dev->base_addr to the gfar reg region */
f4983704 892 dev->base_addr = (unsigned long) regs;
1da177e4 893
b31a1d8b 894 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 895
896 /* Fill in the dev structure */
1da177e4 897 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 898 dev->mtu = 1500;
26ccfc37 899 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 900 dev->ethtool_ops = &gfar_ethtool_ops;
901
fba4ed03 902 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 903 for (i = 0; i < priv->num_grps; i++)
904 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 905
b31a1d8b 906 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
0bbaf069 907 priv->rx_csum_enable = 1;
4669bc90 908 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
0bbaf069
KG		 909 } else
910 priv->rx_csum_enable = 0;
911
912 priv->vlgrp = NULL;
1da177e4 913
26ccfc37 914 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
0bbaf069 915 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 916
b31a1d8b 917 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 918 priv->extended_hash = 1;
919 priv->hash_width = 9;
920
f4983704
SG		 921 priv->hash_regs[0] = &regs->igaddr0;
922 priv->hash_regs[1] = &regs->igaddr1;
923 priv->hash_regs[2] = &regs->igaddr2;
924 priv->hash_regs[3] = &regs->igaddr3;
925 priv->hash_regs[4] = &regs->igaddr4;
926 priv->hash_regs[5] = &regs->igaddr5;
927 priv->hash_regs[6] = &regs->igaddr6;
928 priv->hash_regs[7] = &regs->igaddr7;
929 priv->hash_regs[8] = &regs->gaddr0;
930 priv->hash_regs[9] = &regs->gaddr1;
931 priv->hash_regs[10] = &regs->gaddr2;
932 priv->hash_regs[11] = &regs->gaddr3;
933 priv->hash_regs[12] = &regs->gaddr4;
934 priv->hash_regs[13] = &regs->gaddr5;
935 priv->hash_regs[14] = &regs->gaddr6;
936 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 937
938 } else {
939 priv->extended_hash = 0;
940 priv->hash_width = 8;
941
f4983704
SG		 942 priv->hash_regs[0] = &regs->gaddr0;
943 priv->hash_regs[1] = &regs->gaddr1;
944 priv->hash_regs[2] = &regs->gaddr2;
945 priv->hash_regs[3] = &regs->gaddr3;
946 priv->hash_regs[4] = &regs->gaddr4;
947 priv->hash_regs[5] = &regs->gaddr5;
948 priv->hash_regs[6] = &regs->gaddr6;
949 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 950 }
951
b31a1d8b 952 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 953 priv->padding = DEFAULT_PADDING;
954 else
955 priv->padding = 0;
956
0bbaf069
KG		 957 if (dev->features & NETIF_F_IP_CSUM)
958 dev->hard_header_len += GMAC_FCB_LEN;
1da177e4 959
46ceb60c
SG		 960 /* Program the isrg regs only if number of grps > 1 */
961 if (priv->num_grps > 1) {
962 baddr = &regs->isrg0;
963 for (i = 0; i < priv->num_grps; i++) {
964 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
965 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
966 gfar_write(baddr, isrg);
967 baddr++;
968 isrg = 0x0;
969 }
970 }
971
fba4ed03
SG		 972 /* Need to reverse the bit maps as bit_map's MSB is q0
973 * but, for_each_bit parses from right to left, which
974 * basically reverses the queue numbers */
46ceb60c
SG		 975 for (i = 0; i< priv->num_grps; i++) {
976 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
977 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
978 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
979 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
980 }
981
982 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
983 * also assign queues to groups */
984 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
985 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
986 for_each_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
987 priv->num_rx_queues) {
988 priv->gfargrp[grp_idx].num_rx_queues++;
989 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
990 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
991 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
992 }
993 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
994 for_each_bit (i, &priv->gfargrp[grp_idx].tx_bit_map,
995 priv->num_tx_queues) {
996 priv->gfargrp[grp_idx].num_tx_queues++;
997 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
998 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
999 tqueue = tqueue | (TQUEUE_EN0 >> i);
1000 }
1001 priv->gfargrp[grp_idx].rstat = rstat;
1002 priv->gfargrp[grp_idx].tstat = tstat;
1003 rstat = tstat =0;
fba4ed03 1004 }
fba4ed03
SG		 1005
1006 gfar_write(&regs->rqueue, rqueue);
1007 gfar_write(&regs->tqueue, tqueue);
1008
1da177e4 1009 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1010
a12f801d 1011 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1012 for (i = 0; i < priv->num_tx_queues; i++) {
1013 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1014 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1015 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1016 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1017 }
a12f801d 1018
fba4ed03
SG		 1019 for (i = 0; i < priv->num_rx_queues; i++) {
1020 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1021 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1022 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1023 }
1da177e4 1024
0bbaf069
KG		 1025 /* Enable most messages by default */
1026 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1027
d3eab82b
TP		 1028 /* Carrier starts down, phylib will bring it up */
1029 netif_carrier_off(dev);
1030
1da177e4
LT		 1031 err = register_netdev(dev);
1032
1033 if (err) {
1034 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1035 dev->name);
1036 goto register_fail;
1037 }
1038
2884e5cc
AV		 1039 device_init_wakeup(&dev->dev,
1040 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1041
c50a5d9a
DH		 1042 /* fill out IRQ number and name fields */
1043 len_devname = strlen(dev->name);
46ceb60c
SG		 1044 for (i = 0; i < priv->num_grps; i++) {
1045 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1046 len_devname);
1047 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1048 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1049 "_g", sizeof("_g"));
1050 priv->gfargrp[i].int_name_tx[
1051 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1052 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1053 priv->gfargrp[i].int_name_tx)],
1054 "_tx", sizeof("_tx") + 1);
1055
1056 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1057 len_devname);
1058 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1059 "_g", sizeof("_g"));
1060 priv->gfargrp[i].int_name_rx[
1061 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1062 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1063 priv->gfargrp[i].int_name_rx)],
1064 "_rx", sizeof("_rx") + 1);
1065
1066 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1067 len_devname);
1068 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1069 "_g", sizeof("_g"));
1070 priv->gfargrp[i].int_name_er[strlen(
1071 priv->gfargrp[i].int_name_er)] = i+48;
1072 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1073 priv->gfargrp[i].int_name_er)],
1074 "_er", sizeof("_er") + 1);
1075 } else
1076 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1077 }
c50a5d9a 1078
7a8b3372
SG		 1079 /* Initialize the filer table */
1080 gfar_init_filer_table(priv);
1081
7f7f5316
AF		 1082 /* Create all the sysfs files */
1083 gfar_init_sysfs(dev);
1084
1da177e4 1085 /* Print out the device info */
e174961c 1086 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1da177e4
LT		 1087
1088 /* Even more device info helps when determining which kernel */
7f7f5316 1089 /* provided which set of benchmarks. */
1da177e4 1090 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
fba4ed03
SG		 1091 for (i = 0; i < priv->num_rx_queues; i++)
1092 printk(KERN_INFO "%s: :RX BD ring size for Q[%d]: %d\n",
1093 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1094 for(i = 0; i < priv->num_tx_queues; i++)
1095 printk(KERN_INFO "%s:TX BD ring size for Q[%d]: %d\n",
1096 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1097
1098 return 0;
1099
1100register_fail:
46ceb60c 1101 unmap_group_regs(priv);
fba4ed03
SG		 1102 free_tx_pointers(priv);
1103 free_rx_pointers(priv);
fe192a49
GL		 1104 if (priv->phy_node)
1105 of_node_put(priv->phy_node);
1106 if (priv->tbi_node)
1107 of_node_put(priv->tbi_node);
1da177e4 1108 free_netdev(dev);
bb40dcbb 1109 return err;
1da177e4
LT		 1110}
1111
b31a1d8b 1112static int gfar_remove(struct of_device *ofdev)
1da177e4 1113{
b31a1d8b 1114 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1115
fe192a49
GL		 1116 if (priv->phy_node)
1117 of_node_put(priv->phy_node);
1118 if (priv->tbi_node)
1119 of_node_put(priv->tbi_node);
1120
b31a1d8b 1121 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1122
d9d8e041 1123 unregister_netdev(priv->ndev);
46ceb60c 1124 unmap_group_regs(priv);
4826857f 1125 free_netdev(priv->ndev);
1da177e4
LT		 1126
1127 return 0;
1128}
1129
d87eb127 1130#ifdef CONFIG_PM
be926fc4
AV		 1131
1132static int gfar_suspend(struct device *dev)
d87eb127 1133{
be926fc4
AV		 1134 struct gfar_private *priv = dev_get_drvdata(dev);
1135 struct net_device *ndev = priv->ndev;
46ceb60c 1136 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1137 unsigned long flags;
1138 u32 tempval;
1139
1140 int magic_packet = priv->wol_en &&
b31a1d8b 1141 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1142
be926fc4 1143 netif_device_detach(ndev);
d87eb127 1144
be926fc4 1145 if (netif_running(ndev)) {
fba4ed03
SG		 1146
1147 local_irq_save(flags);
1148 lock_tx_qs(priv);
1149 lock_rx_qs(priv);
d87eb127 1150
be926fc4 1151 gfar_halt_nodisable(ndev);
d87eb127
SW		 1152
1153 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1154 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1155
1156 tempval &= ~MACCFG1_TX_EN;
1157
1158 if (!magic_packet)
1159 tempval &= ~MACCFG1_RX_EN;
1160
f4983704 1161 gfar_write(&regs->maccfg1, tempval);
d87eb127 1162
fba4ed03
SG		 1163 unlock_rx_qs(priv);
1164 unlock_tx_qs(priv);
1165 local_irq_restore(flags);
d87eb127 1166
46ceb60c 1167 disable_napi(priv);
d87eb127
SW		 1168
1169 if (magic_packet) {
1170 /* Enable interrupt on Magic Packet */
f4983704 1171 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1172
1173 /* Enable Magic Packet mode */
f4983704 1174 tempval = gfar_read(&regs->maccfg2);
d87eb127 1175 tempval |= MACCFG2_MPEN;
f4983704 1176 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1177 } else {
1178 phy_stop(priv->phydev);
1179 }
1180 }
1181
1182 return 0;
1183}
1184
be926fc4 1185static int gfar_resume(struct device *dev)
d87eb127 1186{
be926fc4
AV		 1187 struct gfar_private *priv = dev_get_drvdata(dev);
1188 struct net_device *ndev = priv->ndev;
46ceb60c 1189 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1190 unsigned long flags;
1191 u32 tempval;
1192 int magic_packet = priv->wol_en &&
b31a1d8b 1193 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1194
be926fc4
AV		 1195 if (!netif_running(ndev)) {
1196 netif_device_attach(ndev);
d87eb127
SW		 1197 return 0;
1198 }
1199
1200 if (!magic_packet && priv->phydev)
1201 phy_start(priv->phydev);
1202
1203 /* Disable Magic Packet mode, in case something
1204 * else woke us up.
1205 */
fba4ed03
SG		 1206 local_irq_save(flags);
1207 lock_tx_qs(priv);
1208 lock_rx_qs(priv);
d87eb127 1209
f4983704 1210 tempval = gfar_read(&regs->maccfg2);
d87eb127 1211 tempval &= ~MACCFG2_MPEN;
f4983704 1212 gfar_write(&regs->maccfg2, tempval);
d87eb127 1213
be926fc4 1214 gfar_start(ndev);
d87eb127 1215
fba4ed03
SG		 1216 unlock_rx_qs(priv);
1217 unlock_tx_qs(priv);
1218 local_irq_restore(flags);
d87eb127 1219
be926fc4
AV		 1220 netif_device_attach(ndev);
1221
46ceb60c 1222 enable_napi(priv);
be926fc4
AV		 1223
1224 return 0;
1225}
1226
1227static int gfar_restore(struct device *dev)
1228{
1229 struct gfar_private *priv = dev_get_drvdata(dev);
1230 struct net_device *ndev = priv->ndev;
1231
1232 if (!netif_running(ndev))
1233 return 0;
1234
1235 gfar_init_bds(ndev);
1236 init_registers(ndev);
1237 gfar_set_mac_address(ndev);
1238 gfar_init_mac(ndev);
1239 gfar_start(ndev);
1240
1241 priv->oldlink = 0;
1242 priv->oldspeed = 0;
1243 priv->oldduplex = -1;
1244
1245 if (priv->phydev)
1246 phy_start(priv->phydev);
d87eb127 1247
be926fc4 1248 netif_device_attach(ndev);
5ea681d4 1249 enable_napi(priv);
d87eb127
SW		 1250
1251 return 0;
1252}
be926fc4
AV		 1253
1254static struct dev_pm_ops gfar_pm_ops = {
1255 .suspend = gfar_suspend,
1256 .resume = gfar_resume,
1257 .freeze = gfar_suspend,
1258 .thaw = gfar_resume,
1259 .restore = gfar_restore,
1260};
1261
1262#define GFAR_PM_OPS (&gfar_pm_ops)
1263
1264static int gfar_legacy_suspend(struct of_device *ofdev, pm_message_t state)
1265{
1266 return gfar_suspend(&ofdev->dev);
1267}
1268
1269static int gfar_legacy_resume(struct of_device *ofdev)
1270{
1271 return gfar_resume(&ofdev->dev);
1272}
1273
d87eb127 1274#else
be926fc4
AV		 1275
1276#define GFAR_PM_OPS NULL
1277#define gfar_legacy_suspend NULL
1278#define gfar_legacy_resume NULL
1279
d87eb127 1280#endif
1da177e4 1281
e8a2b6a4
AF		 1282/* Reads the controller's registers to determine what interface
1283 * connects it to the PHY.
1284 */
1285static phy_interface_t gfar_get_interface(struct net_device *dev)
1286{
1287 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1288 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1289 u32 ecntrl;
1290
f4983704 1291 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1292
1293 if (ecntrl & ECNTRL_SGMII_MODE)
1294 return PHY_INTERFACE_MODE_SGMII;
1295
1296 if (ecntrl & ECNTRL_TBI_MODE) {
1297 if (ecntrl & ECNTRL_REDUCED_MODE)
1298 return PHY_INTERFACE_MODE_RTBI;
1299 else
1300 return PHY_INTERFACE_MODE_TBI;
1301 }
1302
1303 if (ecntrl & ECNTRL_REDUCED_MODE) {
1304 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1305 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1306 else {
b31a1d8b 1307 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1308
1309 /*
1310 * This isn't autodetected right now, so it must
1311 * be set by the device tree or platform code.
1312 */
1313 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1314 return PHY_INTERFACE_MODE_RGMII_ID;
1315
e8a2b6a4 1316 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1317 }
e8a2b6a4
AF		 1318 }
1319
b31a1d8b 1320 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1321 return PHY_INTERFACE_MODE_GMII;
1322
1323 return PHY_INTERFACE_MODE_MII;
1324}
1325
1326
bb40dcbb
AF		 1327/* Initializes driver's PHY state, and attaches to the PHY.
1328 * Returns 0 on success.
1da177e4
LT		 1329 */
1330static int init_phy(struct net_device *dev)
1331{
1332 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1333 uint gigabit_support =
b31a1d8b 1334 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1335 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1336 phy_interface_t interface;
1da177e4
LT		 1337
1338 priv->oldlink = 0;
1339 priv->oldspeed = 0;
1340 priv->oldduplex = -1;
1341
e8a2b6a4
AF		 1342 interface = gfar_get_interface(dev);
1343
1db780f8
AV		 1344 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1345 interface);
1346 if (!priv->phydev)
1347 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1348 interface);
1349 if (!priv->phydev) {
1350 dev_err(&dev->dev, "could not attach to PHY\n");
1351 return -ENODEV;
fe192a49 1352 }
1da177e4 1353
d3c12873
KJ		 1354 if (interface == PHY_INTERFACE_MODE_SGMII)
1355 gfar_configure_serdes(dev);
1356
bb40dcbb 1357 /* Remove any features not supported by the controller */
fe192a49
GL		 1358 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1359 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1360
1361 return 0;
1da177e4
LT		 1362}
1363
d0313587
PG		 1364/*
1365 * Initialize TBI PHY interface for communicating with the
1366 * SERDES lynx PHY on the chip. We communicate with this PHY
1367 * through the MDIO bus on each controller, treating it as a
1368 * "normal" PHY at the address found in the TBIPA register. We assume
1369 * that the TBIPA register is valid. Either the MDIO bus code will set
1370 * it to a value that doesn't conflict with other PHYs on the bus, or the
1371 * value doesn't matter, as there are no other PHYs on the bus.
1372 */
d3c12873
KJ		 1373static void gfar_configure_serdes(struct net_device *dev)
1374{
1375 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1376 struct phy_device *tbiphy;
1377
1378 if (!priv->tbi_node) {
1379 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1380 "device tree specify a tbi-handle\n");
1381 return;
1382 }
c132419e 1383
fe192a49
GL		 1384 tbiphy = of_phy_find_device(priv->tbi_node);
1385 if (!tbiphy) {
1386 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1387 return;
1388 }
d3c12873 1389
b31a1d8b
AF		 1390 /*
1391 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1392 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1393 * everything for us? Resetting it takes the link down and requires
1394 * several seconds for it to come back.
1395 */
fe192a49 1396 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1397 return;
d3c12873 1398
d0313587 1399 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1400 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1401
fe192a49 1402 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1403 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1404 ADVERTISE_1000XPSE_ASYM);
1405
fe192a49 1406 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1407 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1408}
1409
1da177e4
LT		 1410static void init_registers(struct net_device *dev)
1411{
1412 struct gfar_private *priv = netdev_priv(dev);
f4983704 1413 struct gfar __iomem *regs = NULL;
46ceb60c 1414 int i = 0;
1da177e4 1415
46ceb60c
SG		 1416 for (i = 0; i < priv->num_grps; i++) {
1417 regs = priv->gfargrp[i].regs;
1418 /* Clear IEVENT */
1419 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1420
46ceb60c
SG		 1421 /* Initialize IMASK */
1422 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1423 }
1da177e4 1424
46ceb60c 1425 regs = priv->gfargrp[0].regs;
1da177e4 1426 /* Init hash registers to zero */
f4983704
SG		 1427 gfar_write(&regs->igaddr0, 0);
1428 gfar_write(&regs->igaddr1, 0);
1429 gfar_write(&regs->igaddr2, 0);
1430 gfar_write(&regs->igaddr3, 0);
1431 gfar_write(&regs->igaddr4, 0);
1432 gfar_write(&regs->igaddr5, 0);
1433 gfar_write(&regs->igaddr6, 0);
1434 gfar_write(&regs->igaddr7, 0);
1435
1436 gfar_write(&regs->gaddr0, 0);
1437 gfar_write(&regs->gaddr1, 0);
1438 gfar_write(&regs->gaddr2, 0);
1439 gfar_write(&regs->gaddr3, 0);
1440 gfar_write(&regs->gaddr4, 0);
1441 gfar_write(&regs->gaddr5, 0);
1442 gfar_write(&regs->gaddr6, 0);
1443 gfar_write(&regs->gaddr7, 0);
1da177e4 1444
1da177e4 1445 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1446 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1447 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1448
1449 /* Mask off the CAM interrupts */
f4983704
SG		 1450 gfar_write(&regs->rmon.cam1, 0xffffffff);
1451 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1452 }
1453
1454 /* Initialize the max receive buffer length */
f4983704 1455 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1456
1da177e4 1457 /* Initialize the Minimum Frame Length Register */
f4983704 1458 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1459}
1460
0bbaf069
KG		 1461
1462/* Halt the receive and transmit queues */
d87eb127 1463static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1464{
1465 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1466 struct gfar __iomem *regs = NULL;
1da177e4 1467 u32 tempval;
46ceb60c 1468 int i = 0;
1da177e4 1469
46ceb60c
SG		 1470 for (i = 0; i < priv->num_grps; i++) {
1471 regs = priv->gfargrp[i].regs;
1472 /* Mask all interrupts */
1473 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1474
46ceb60c
SG		 1475 /* Clear all interrupts */
1476 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1477 }
1da177e4 1478
46ceb60c 1479 regs = priv->gfargrp[0].regs;
1da177e4 1480 /* Stop the DMA, and wait for it to stop */
f4983704 1481 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1482 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1483 != (DMACTRL_GRS | DMACTRL_GTS)) {
1484 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1485 gfar_write(&regs->dmactrl, tempval);
1da177e4 1486
f4983704 1487 while (!(gfar_read(&regs->ievent) &
1da177e4
LT		 1488 (IEVENT_GRSC | IEVENT_GTSC)))
1489 cpu_relax();
1490 }
d87eb127 1491}
d87eb127
SW		 1492
1493/* Halt the receive and transmit queues */
1494void gfar_halt(struct net_device *dev)
1495{
1496 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1497 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1498 u32 tempval;
1da177e4 1499
2a54adc3
SW		 1500 gfar_halt_nodisable(dev);
1501
1da177e4
LT		 1502 /* Disable Rx and Tx */
1503 tempval = gfar_read(&regs->maccfg1);
1504 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1505 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1506}
1507
46ceb60c
SG		 1508static void free_grp_irqs(struct gfar_priv_grp *grp)
1509{
1510 free_irq(grp->interruptError, grp);
1511 free_irq(grp->interruptTransmit, grp);
1512 free_irq(grp->interruptReceive, grp);
1513}
1514
0bbaf069
KG		 1515void stop_gfar(struct net_device *dev)
1516{
1517 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1518 unsigned long flags;
46ceb60c 1519 int i;
0bbaf069 1520
bb40dcbb
AF		 1521 phy_stop(priv->phydev);
1522
a12f801d 1523
0bbaf069 1524 /* Lock it down */
fba4ed03
SG		 1525 local_irq_save(flags);
1526 lock_tx_qs(priv);
1527 lock_rx_qs(priv);
0bbaf069 1528
0bbaf069 1529 gfar_halt(dev);
1da177e4 1530
fba4ed03
SG		 1531 unlock_rx_qs(priv);
1532 unlock_tx_qs(priv);
1533 local_irq_restore(flags);
1da177e4
LT		 1534
1535 /* Free the IRQs */
b31a1d8b 1536 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1537 for (i = 0; i < priv->num_grps; i++)
1538 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1539 } else {
46ceb60c
SG		 1540 for (i = 0; i < priv->num_grps; i++)
1541 free_irq(priv->gfargrp[i].interruptTransmit,
1542 &priv->gfargrp[i]);
1da177e4
LT		 1543 }
1544
1545 free_skb_resources(priv);
1da177e4
LT		 1546}
1547
fba4ed03 1548static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1549{
1da177e4 1550 struct txbd8 *txbdp;
fba4ed03 1551 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1552 int i, j;
1da177e4 1553
a12f801d 1554 txbdp = tx_queue->tx_bd_base;
1da177e4 1555
a12f801d
SG		 1556 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1557 if (!tx_queue->tx_skbuff[i])
4669bc90 1558 continue;
1da177e4 1559
4826857f 1560 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1561 txbdp->length, DMA_TO_DEVICE);
1562 txbdp->lstatus = 0;
fba4ed03
SG		 1563 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1564 j++) {
4669bc90 1565 txbdp++;
4826857f 1566 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1567 txbdp->length, DMA_TO_DEVICE);
1da177e4 1568 }
ad5da7ab 1569 txbdp++;
a12f801d
SG		 1570 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1571 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1572 }
a12f801d 1573 kfree(tx_queue->tx_skbuff);
fba4ed03 1574}
1da177e4 1575
fba4ed03
SG		 1576static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1577{
1578 struct rxbd8 *rxbdp;
1579 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1580 int i;
1da177e4 1581
fba4ed03 1582 rxbdp = rx_queue->rx_bd_base;
1da177e4 1583
a12f801d
SG		 1584 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1585 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1586 dma_unmap_single(&priv->ofdev->dev,
1587 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1588 DMA_FROM_DEVICE);
a12f801d
SG		 1589 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1590 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1591 }
e69edd21
AV		 1592 rxbdp->lstatus = 0;
1593 rxbdp->bufPtr = 0;
1594 rxbdp++;
1da177e4 1595 }
a12f801d 1596 kfree(rx_queue->rx_skbuff);
fba4ed03 1597}
e69edd21 1598
fba4ed03
SG		 1599/* If there are any tx skbs or rx skbs still around, free them.
1600 * Then free tx_skbuff and rx_skbuff */
1601static void free_skb_resources(struct gfar_private *priv)
1602{
1603 struct gfar_priv_tx_q *tx_queue = NULL;
1604 struct gfar_priv_rx_q *rx_queue = NULL;
1605 int i;
1606
1607 /* Go through all the buffer descriptors and free their data buffers */
1608 for (i = 0; i < priv->num_tx_queues; i++) {
1609 tx_queue = priv->tx_queue[i];
1610 if(!tx_queue->tx_skbuff)
1611 free_skb_tx_queue(tx_queue);
1612 }
1613
1614 for (i = 0; i < priv->num_rx_queues; i++) {
1615 rx_queue = priv->rx_queue[i];
1616 if(!rx_queue->rx_skbuff)
1617 free_skb_rx_queue(rx_queue);
1618 }
1619
1620 dma_free_coherent(&priv->ofdev->dev,
1621 sizeof(struct txbd8) * priv->total_tx_ring_size +
1622 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1623 priv->tx_queue[0]->tx_bd_base,
1624 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1625}
1626
0bbaf069
KG		 1627void gfar_start(struct net_device *dev)
1628{
1629 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1630 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1631 u32 tempval;
46ceb60c 1632 int i = 0;
0bbaf069
KG		 1633
1634 /* Enable Rx and Tx in MACCFG1 */
1635 tempval = gfar_read(&regs->maccfg1);
1636 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1637 gfar_write(&regs->maccfg1, tempval);
1638
1639 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1640 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1641 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1642 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1643
0bbaf069 1644 /* Make sure we aren't stopped */
f4983704 1645 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1646 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1647 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1648
46ceb60c
SG		 1649 for (i = 0; i < priv->num_grps; i++) {
1650 regs = priv->gfargrp[i].regs;
1651 /* Clear THLT/RHLT, so that the DMA starts polling now */
1652 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1653 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1654 /* Unmask the interrupts we look for */
1655 gfar_write(&regs->imask, IMASK_DEFAULT);
1656 }
12dea57b
DH		 1657
1658 dev->trans_start = jiffies;
0bbaf069
KG		 1659}
1660
46ceb60c 1661void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1662 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1663{
46ceb60c 1664 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1665 u32 __iomem *baddr;
46ceb60c 1666 int i = 0;
1da177e4 1667
46ceb60c
SG		 1668 /* Backward compatible case ---- even if we enable
1669 * multiple queues, there's only single reg to program
1670 */
1671 gfar_write(&regs->txic, 0);
1672 if(likely(priv->tx_queue[0]->txcoalescing))
1673 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1674
46ceb60c
SG		 1675 gfar_write(&regs->rxic, 0);
1676 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1677 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1678
46ceb60c
SG		 1679 if (priv->mode == MQ_MG_MODE) {
1680 baddr = &regs->txic0;
1681 for_each_bit (i, &tx_mask, priv->num_tx_queues) {
1682 if (likely(priv->tx_queue[i]->txcoalescing)) {
1683 gfar_write(baddr + i, 0);
1684 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1685 }
1686 }
1687
1688 baddr = &regs->rxic0;
1689 for_each_bit (i, &rx_mask, priv->num_rx_queues) {
1690 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1691 gfar_write(baddr + i, 0);
1692 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1693 }
1694 }
1695 }
1696}
1697
1698static int register_grp_irqs(struct gfar_priv_grp *grp)
1699{
1700 struct gfar_private *priv = grp->priv;
1701 struct net_device *dev = priv->ndev;
1702 int err;
1da177e4 1703
1da177e4
LT		 1704 /* If the device has multiple interrupts, register for
1705 * them. Otherwise, only register for the one */
b31a1d8b 1706 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1707 /* Install our interrupt handlers for Error,
1da177e4 1708 * Transmit, and Receive */
46ceb60c
SG		 1709 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1710 grp->int_name_er,grp)) < 0) {
0bbaf069 1711 if (netif_msg_intr(priv))
46ceb60c
SG		 1712 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1713 dev->name, grp->interruptError);
1714
1715 goto err_irq_fail;
1da177e4
LT		 1716 }
1717
46ceb60c
SG		 1718 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1719 0, grp->int_name_tx, grp)) < 0) {
0bbaf069 1720 if (netif_msg_intr(priv))
46ceb60c
SG		 1721 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1722 dev->name, grp->interruptTransmit);
1da177e4
LT		 1723 goto tx_irq_fail;
1724 }
1725
46ceb60c
SG		 1726 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1727 grp->int_name_rx, grp)) < 0) {
0bbaf069 1728 if (netif_msg_intr(priv))
46ceb60c
SG		 1729 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1730 dev->name, grp->interruptReceive);
1da177e4
LT		 1731 goto rx_irq_fail;
1732 }
1733 } else {
46ceb60c
SG		 1734 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1735 grp->int_name_tx, grp)) < 0) {
0bbaf069 1736 if (netif_msg_intr(priv))
46ceb60c
SG		 1737 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1738 dev->name, grp->interruptTransmit);
1da177e4
LT		 1739 goto err_irq_fail;
1740 }
1741 }
1742
46ceb60c
SG		 1743 return 0;
1744
1745rx_irq_fail:
1746 free_irq(grp->interruptTransmit, grp);
1747tx_irq_fail:
1748 free_irq(grp->interruptError, grp);
1749err_irq_fail:
1750 return err;
1751
1752}
1753
1754/* Bring the controller up and running */
1755int startup_gfar(struct net_device *ndev)
1756{
1757 struct gfar_private *priv = netdev_priv(ndev);
1758 struct gfar __iomem *regs = NULL;
1759 int err, i, j;
1760
1761 for (i = 0; i < priv->num_grps; i++) {
1762 regs= priv->gfargrp[i].regs;
1763 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1764 }
1765
1766 regs= priv->gfargrp[0].regs;
1767 err = gfar_alloc_skb_resources(ndev);
1768 if (err)
1769 return err;
1770
1771 gfar_init_mac(ndev);
1772
1773 for (i = 0; i < priv->num_grps; i++) {
1774 err = register_grp_irqs(&priv->gfargrp[i]);
1775 if (err) {
1776 for (j = 0; j < i; j++)
1777 free_grp_irqs(&priv->gfargrp[j]);
1778 goto irq_fail;
1779 }
1780 }
1781
7f7f5316 1782 /* Start the controller */
ccc05c6e 1783 gfar_start(ndev);
1da177e4 1784
826aa4a0
AV		 1785 phy_start(priv->phydev);
1786
46ceb60c
SG		 1787 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1788
1da177e4
LT		 1789 return 0;
1790
46ceb60c 1791irq_fail:
e69edd21 1792 free_skb_resources(priv);
1da177e4
LT		 1793 return err;
1794}
1795
1796/* Called when something needs to use the ethernet device */
1797/* Returns 0 for success. */
1798static int gfar_enet_open(struct net_device *dev)
1799{
94e8cc35 1800 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1801 int err;
1802
46ceb60c 1803 enable_napi(priv);
bea3348e 1804
0fd56bb5
AF		 1805 skb_queue_head_init(&priv->rx_recycle);
1806
1da177e4
LT		 1807 /* Initialize a bunch of registers */
1808 init_registers(dev);
1809
1810 gfar_set_mac_address(dev);
1811
1812 err = init_phy(dev);
1813
a12f801d 1814 if (err) {
46ceb60c 1815 disable_napi(priv);
1da177e4 1816 return err;
bea3348e 1817 }
1da177e4
LT		 1818
1819 err = startup_gfar(dev);
db0e8e3f 1820 if (err) {
46ceb60c 1821 disable_napi(priv);
db0e8e3f
AV		 1822 return err;
1823 }
1da177e4 1824
fba4ed03 1825 netif_tx_start_all_queues(dev);
1da177e4 1826
2884e5cc
AV		 1827 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1828
1da177e4
LT		 1829 return err;
1830}
1831
54dc79fe 1832static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1833{
54dc79fe 1834 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1835
1836 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1837
0bbaf069
KG		 1838 return fcb;
1839}
1840
1841static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1842{
7f7f5316 1843 u8 flags = 0;
0bbaf069
KG		 1844
1845 /* If we're here, it's a IP packet with a TCP or UDP
1846 * payload. We set it to checksum, using a pseudo-header
1847 * we provide
1848 */
7f7f5316 1849 flags = TXFCB_DEFAULT;
0bbaf069 1850
7f7f5316
AF		 1851 /* Tell the controller what the protocol is */
1852 /* And provide the already calculated phcs */
eddc9ec5 1853 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1854 flags |= TXFCB_UDP;
4bedb452 1855 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1856 } else
8da32de5 1857 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1858
1859 /* l3os is the distance between the start of the
1860 * frame (skb->data) and the start of the IP hdr.
1861 * l4os is the distance between the start of the
1862 * l3 hdr and the l4 hdr */
bbe735e4 1863 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
cfe1fc77 1864 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1865
7f7f5316 1866 fcb->flags = flags;
0bbaf069
KG		 1867}
1868
7f7f5316 1869void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1870{
7f7f5316 1871 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1872 fcb->vlctl = vlan_tx_tag_get(skb);
1873}
1874
4669bc90
DH		 1875static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1876 struct txbd8 *base, int ring_size)
1877{
1878 struct txbd8 *new_bd = bdp + stride;
1879
1880 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1881}
1882
1883static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1884 int ring_size)
1885{
1886 return skip_txbd(bdp, 1, base, ring_size);
1887}
1888
1da177e4
LT		 1889/* This is called by the kernel when a frame is ready for transmission. */
1890/* It is pointed to by the dev->hard_start_xmit function pointer */
1891static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1892{
1893 struct gfar_private *priv = netdev_priv(dev);
a12f801d 1894 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 1895 struct netdev_queue *txq;
f4983704 1896 struct gfar __iomem *regs = NULL;
0bbaf069 1897 struct txfcb *fcb = NULL;
4669bc90 1898 struct txbd8 *txbdp, *txbdp_start, *base;
5a5efed4 1899 u32 lstatus;
fba4ed03 1900 int i, rq = 0;
4669bc90 1901 u32 bufaddr;
fef6108d 1902 unsigned long flags;
4669bc90
DH		 1903 unsigned int nr_frags, length;
1904
fba4ed03
SG		 1905
1906 rq = skb->queue_mapping;
1907 tx_queue = priv->tx_queue[rq];
1908 txq = netdev_get_tx_queue(dev, rq);
a12f801d 1909 base = tx_queue->tx_bd_base;
46ceb60c 1910 regs = tx_queue->grp->regs;
4669bc90 1911
5b28beaf
LY		 1912 /* make space for additional header when fcb is needed */
1913 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1914 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1915 (skb_headroom(skb) < GMAC_FCB_LEN)) {
54dc79fe
SH		 1916 struct sk_buff *skb_new;
1917
1918 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1919 if (!skb_new) {
1920 dev->stats.tx_errors++;
bd14ba84 1921 kfree_skb(skb);
54dc79fe
SH		 1922 return NETDEV_TX_OK;
1923 }
1924 kfree_skb(skb);
1925 skb = skb_new;
1926 }
1927
4669bc90
DH		 1928 /* total number of fragments in the SKB */
1929 nr_frags = skb_shinfo(skb)->nr_frags;
1930
4669bc90 1931 /* check if there is space to queue this packet */
a12f801d 1932 if ((nr_frags+1) > tx_queue->num_txbdfree) {
4669bc90 1933 /* no space, stop the queue */
fba4ed03 1934 netif_tx_stop_queue(txq);
4669bc90 1935 dev->stats.tx_fifo_errors++;
4669bc90
DH		 1936 return NETDEV_TX_BUSY;
1937 }
1da177e4
LT		 1938
1939 /* Update transmit stats */
09f75cd7 1940 dev->stats.tx_bytes += skb->len;
1da177e4 1941
a12f801d 1942 txbdp = txbdp_start = tx_queue->cur_tx;
1da177e4 1943
4669bc90
DH		 1944 if (nr_frags == 0) {
1945 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1946 } else {
1947 /* Place the fragment addresses and lengths into the TxBDs */
1948 for (i = 0; i < nr_frags; i++) {
1949 /* Point at the next BD, wrapping as needed */
a12f801d 1950 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 1951
1952 length = skb_shinfo(skb)->frags[i].size;
1953
1954 lstatus = txbdp->lstatus | length |
1955 BD_LFLAG(TXBD_READY);
1956
1957 /* Handle the last BD specially */
1958 if (i == nr_frags - 1)
1959 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 1960
4826857f 1961 bufaddr = dma_map_page(&priv->ofdev->dev,
4669bc90
DH		 1962 skb_shinfo(skb)->frags[i].page,
1963 skb_shinfo(skb)->frags[i].page_offset,
1964 length,
1965 DMA_TO_DEVICE);
1966
1967 /* set the TxBD length and buffer pointer */
1968 txbdp->bufPtr = bufaddr;
1969 txbdp->lstatus = lstatus;
1970 }
1971
1972 lstatus = txbdp_start->lstatus;
1973 }
1da177e4 1974
0bbaf069 1975 /* Set up checksumming */
12dea57b 1976 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe
SH		 1977 fcb = gfar_add_fcb(skb);
1978 lstatus |= BD_LFLAG(TXBD_TOE);
1979 gfar_tx_checksum(skb, fcb);
0bbaf069
KG		 1980 }
1981
77ecaf2d 1982 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
54dc79fe
SH		 1983 if (unlikely(NULL == fcb)) {
1984 fcb = gfar_add_fcb(skb);
5a5efed4 1985 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 1986 }
54dc79fe
SH		 1987
1988 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 1989 }
1990
4669bc90 1991 /* setup the TxBD length and buffer pointer for the first BD */
a12f801d 1992 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
4826857f 1993 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 1994 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 1995
4669bc90 1996 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1da177e4 1997
a3bc1f11
AV		 1998 /*
1999 * We can work in parallel with gfar_clean_tx_ring(), except
2000 * when modifying num_txbdfree. Note that we didn't grab the lock
2001 * when we were reading the num_txbdfree and checking for available
2002 * space, that's because outside of this function it can only grow,
2003 * and once we've got needed space, it cannot suddenly disappear.
2004 *
2005 * The lock also protects us from gfar_error(), which can modify
2006 * regs->tstat and thus retrigger the transfers, which is why we
2007 * also must grab the lock before setting ready bit for the first
2008 * to be transmitted BD.
2009 */
2010 spin_lock_irqsave(&tx_queue->txlock, flags);
2011
4669bc90
DH		 2012 /*
2013 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2014 * semantics (it requires synchronization between cacheable and
2015 * uncacheable mappings, which eieio doesn't provide and which we
2016 * don't need), thus requiring a more expensive sync instruction. At
2017 * some point, the set of architecture-independent barrier functions
2018 * should be expanded to include weaker barriers.
2019 */
3b6330ce 2020 eieio();
7f7f5316 2021
4669bc90
DH		 2022 txbdp_start->lstatus = lstatus;
2023
2024 /* Update the current skb pointer to the next entry we will use
2025 * (wrapping if necessary) */
a12f801d
SG		 2026 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2027 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2028
a12f801d 2029 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2030
2031 /* reduce TxBD free count */
a12f801d 2032 tx_queue->num_txbdfree -= (nr_frags + 1);
4669bc90
DH		 2033
2034 dev->trans_start = jiffies;
1da177e4
LT		 2035
2036 /* If the next BD still needs to be cleaned up, then the bds
2037 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2038 if (!tx_queue->num_txbdfree) {
fba4ed03 2039 netif_tx_stop_queue(txq);
1da177e4 2040
09f75cd7 2041 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2042 }
2043
1da177e4 2044 /* Tell the DMA to go go go */
fba4ed03 2045 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2046
2047 /* Unlock priv */
a12f801d 2048 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2049
54dc79fe 2050 return NETDEV_TX_OK;
1da177e4
LT		 2051}
2052
2053/* Stops the kernel queue, and halts the controller */
2054static int gfar_close(struct net_device *dev)
2055{
2056 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2057
46ceb60c 2058 disable_napi(priv);
bea3348e 2059
0fd56bb5 2060 skb_queue_purge(&priv->rx_recycle);
ab939905 2061 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2062 stop_gfar(dev);
2063
bb40dcbb
AF		 2064 /* Disconnect from the PHY */
2065 phy_disconnect(priv->phydev);
2066 priv->phydev = NULL;
1da177e4 2067
fba4ed03 2068 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2069
2070 return 0;
2071}
2072
1da177e4 2073/* Changes the mac address if the controller is not running. */
f162b9d5 2074static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2075{
7f7f5316 2076 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2077
2078 return 0;
2079}
2080
2081
0bbaf069
KG		 2082/* Enables and disables VLAN insertion/extraction */
2083static void gfar_vlan_rx_register(struct net_device *dev,
2084 struct vlan_group *grp)
2085{
2086 struct gfar_private *priv = netdev_priv(dev);
f4983704 2087 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2088 unsigned long flags;
2089 u32 tempval;
2090
46ceb60c 2091 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2092 local_irq_save(flags);
2093 lock_rx_qs(priv);
0bbaf069 2094
cd1f55a5 2095 priv->vlgrp = grp;
0bbaf069
KG		 2096
2097 if (grp) {
2098 /* Enable VLAN tag insertion */
f4983704 2099 tempval = gfar_read(&regs->tctrl);
0bbaf069
KG		 2100 tempval |= TCTRL_VLINS;
2101
f4983704 2102 gfar_write(&regs->tctrl, tempval);
6aa20a22 2103
0bbaf069 2104 /* Enable VLAN tag extraction */
f4983704 2105 tempval = gfar_read(&regs->rctrl);
77ecaf2d 2106 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
f4983704 2107 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2108 } else {
2109 /* Disable VLAN tag insertion */
f4983704 2110 tempval = gfar_read(&regs->tctrl);
0bbaf069 2111 tempval &= ~TCTRL_VLINS;
f4983704 2112 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2113
2114 /* Disable VLAN tag extraction */
f4983704 2115 tempval = gfar_read(&regs->rctrl);
0bbaf069 2116 tempval &= ~RCTRL_VLEX;
77ecaf2d
DH		 2117 /* If parse is no longer required, then disable parser */
2118 if (tempval & RCTRL_REQ_PARSER)
2119 tempval |= RCTRL_PRSDEP_INIT;
2120 else
2121 tempval &= ~RCTRL_PRSDEP_INIT;
f4983704 2122 gfar_write(&regs->rctrl, tempval);
0bbaf069
KG		 2123 }
2124
77ecaf2d
DH		 2125 gfar_change_mtu(dev, dev->mtu);
2126
fba4ed03
SG		 2127 unlock_rx_qs(priv);
2128 local_irq_restore(flags);
0bbaf069
KG		 2129}
2130
1da177e4
LT		 2131static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2132{
2133 int tempsize, tempval;
2134 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2135 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2136 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2137 int frame_size = new_mtu + ETH_HLEN;
2138
77ecaf2d 2139 if (priv->vlgrp)
faa89577 2140 frame_size += VLAN_HLEN;
0bbaf069 2141
1da177e4 2142 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
0bbaf069
KG		 2143 if (netif_msg_drv(priv))
2144 printk(KERN_ERR "%s: Invalid MTU setting\n",
2145 dev->name);
1da177e4
LT		 2146 return -EINVAL;
2147 }
2148
77ecaf2d
DH		 2149 if (gfar_uses_fcb(priv))
2150 frame_size += GMAC_FCB_LEN;
2151
2152 frame_size += priv->padding;
2153
1da177e4
LT		 2154 tempsize =
2155 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2156 INCREMENTAL_BUFFER_SIZE;
2157
2158 /* Only stop and start the controller if it isn't already
7f7f5316 2159 * stopped, and we changed something */
1da177e4
LT		 2160 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2161 stop_gfar(dev);
2162
2163 priv->rx_buffer_size = tempsize;
2164
2165 dev->mtu = new_mtu;
2166
f4983704
SG		 2167 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2168 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2169
2170 /* If the mtu is larger than the max size for standard
2171 * ethernet frames (ie, a jumbo frame), then set maccfg2
2172 * to allow huge frames, and to check the length */
f4983704 2173 tempval = gfar_read(&regs->maccfg2);
1da177e4
LT		 2174
2175 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2176 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2177 else
2178 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2179
f4983704 2180 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2181
2182 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2183 startup_gfar(dev);
2184
2185 return 0;
2186}
2187
ab939905 2188/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2189 * transmitted after a set amount of time.
2190 * For now, assume that clearing out all the structures, and
ab939905
SS		 2191 * starting over will fix the problem.
2192 */
2193static void gfar_reset_task(struct work_struct *work)
1da177e4 2194{
ab939905
SS		 2195 struct gfar_private *priv = container_of(work, struct gfar_private,
2196 reset_task);
4826857f 2197 struct net_device *dev = priv->ndev;
1da177e4
LT		 2198
2199 if (dev->flags & IFF_UP) {
fba4ed03 2200 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2201 stop_gfar(dev);
2202 startup_gfar(dev);
fba4ed03 2203 netif_tx_start_all_queues(dev);
1da177e4
LT		 2204 }
2205
263ba320 2206 netif_tx_schedule_all(dev);
1da177e4
LT		 2207}
2208
ab939905
SS		 2209static void gfar_timeout(struct net_device *dev)
2210{
2211 struct gfar_private *priv = netdev_priv(dev);
2212
2213 dev->stats.tx_errors++;
2214 schedule_work(&priv->reset_task);
2215}
2216
1da177e4 2217/* Interrupt Handler for Transmit complete */
a12f801d 2218static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2219{
a12f801d 2220 struct net_device *dev = tx_queue->dev;
d080cd63 2221 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2222 struct gfar_priv_rx_q *rx_queue = NULL;
4669bc90
DH		 2223 struct txbd8 *bdp;
2224 struct txbd8 *lbdp = NULL;
a12f801d 2225 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2226 struct sk_buff *skb;
2227 int skb_dirtytx;
a12f801d 2228 int tx_ring_size = tx_queue->tx_ring_size;
4669bc90
DH		 2229 int frags = 0;
2230 int i;
d080cd63 2231 int howmany = 0;
4669bc90 2232 u32 lstatus;
1da177e4 2233
fba4ed03 2234 rx_queue = priv->rx_queue[tx_queue->qindex];
a12f801d
SG		 2235 bdp = tx_queue->dirty_tx;
2236 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2237
a12f801d 2238 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2239 unsigned long flags;
2240
4669bc90
DH		 2241 frags = skb_shinfo(skb)->nr_frags;
2242 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1da177e4 2243
4669bc90 2244 lstatus = lbdp->lstatus;
1da177e4 2245
4669bc90
DH		 2246 /* Only clean completed frames */
2247 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2248 (lstatus & BD_LENGTH_MASK))
2249 break;
2250
4826857f 2251 dma_unmap_single(&priv->ofdev->dev,
4669bc90
DH		 2252 bdp->bufPtr,
2253 bdp->length,
2254 DMA_TO_DEVICE);
81183059 2255
4669bc90
DH		 2256 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2257 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2258
4669bc90 2259 for (i = 0; i < frags; i++) {
4826857f 2260 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2261 bdp->bufPtr,
2262 bdp->length,
2263 DMA_TO_DEVICE);
2264 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2265 bdp = next_txbd(bdp, base, tx_ring_size);
2266 }
1da177e4 2267
0fd56bb5
AF		 2268 /*
2269 * If there's room in the queue (limit it to rx_buffer_size)
2270 * we add this skb back into the pool, if it's the right size
2271 */
a12f801d 2272 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5
AF		 2273 skb_recycle_check(skb, priv->rx_buffer_size +
2274 RXBUF_ALIGNMENT))
2275 __skb_queue_head(&priv->rx_recycle, skb);
2276 else
2277 dev_kfree_skb_any(skb);
2278
a12f801d 2279 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2280
4669bc90
DH		 2281 skb_dirtytx = (skb_dirtytx + 1) &
2282 TX_RING_MOD_MASK(tx_ring_size);
2283
2284 howmany++;
a3bc1f11 2285 spin_lock_irqsave(&tx_queue->txlock, flags);
a12f801d 2286 tx_queue->num_txbdfree += frags + 1;
a3bc1f11 2287 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2288 }
1da177e4 2289
4669bc90 2290 /* If we freed a buffer, we can restart transmission, if necessary */
fba4ed03
SG		 2291 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2292 netif_wake_subqueue(dev, tx_queue->qindex);
1da177e4 2293
4669bc90 2294 /* Update dirty indicators */
a12f801d
SG		 2295 tx_queue->skb_dirtytx = skb_dirtytx;
2296 tx_queue->dirty_tx = bdp;
1da177e4 2297
d080cd63
DH		 2298 dev->stats.tx_packets += howmany;
2299
2300 return howmany;
2301}
2302
f4983704 2303static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2304{
a6d0b91a
AV		 2305 unsigned long flags;
2306
fba4ed03
SG		 2307 spin_lock_irqsave(&gfargrp->grplock, flags);
2308 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2309 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2310 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2311 } else {
2312 /*
2313 * Clear IEVENT, so interrupts aren't called again
2314 * because of the packets that have already arrived.
2315 */
f4983704 2316 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2317 }
fba4ed03 2318 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2319
8c7396ae 2320}
1da177e4 2321
8c7396ae 2322/* Interrupt Handler for Transmit complete */
f4983704 2323static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2324{
f4983704 2325 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2326 return IRQ_HANDLED;
2327}
2328
a12f801d 2329static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2330 struct sk_buff *skb)
2331{
a12f801d 2332 struct net_device *dev = rx_queue->dev;
815b97c6 2333 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2334 dma_addr_t buf;
815b97c6 2335
8a102fe0
AV		 2336 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2337 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2338 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2339}
2340
2341
2342struct sk_buff * gfar_new_skb(struct net_device *dev)
1da177e4 2343{
7f7f5316 2344 unsigned int alignamount;
1da177e4
LT		 2345 struct gfar_private *priv = netdev_priv(dev);
2346 struct sk_buff *skb = NULL;
1da177e4 2347
0fd56bb5
AF		 2348 skb = __skb_dequeue(&priv->rx_recycle);
2349 if (!skb)
2350 skb = netdev_alloc_skb(dev,
2351 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1da177e4 2352
815b97c6 2353 if (!skb)
1da177e4
LT		 2354 return NULL;
2355
7f7f5316 2356 alignamount = RXBUF_ALIGNMENT -
bea3348e 2357 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
7f7f5316 2358
1da177e4
LT		 2359 /* We need the data buffer to be aligned properly. We will reserve
2360 * as many bytes as needed to align the data properly
2361 */
7f7f5316 2362 skb_reserve(skb, alignamount);
1da177e4 2363
1da177e4
LT		 2364 return skb;
2365}
2366
298e1a9e 2367static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2368{
298e1a9e 2369 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2370 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2371 struct gfar_extra_stats *estats = &priv->extra_stats;
2372
2373 /* If the packet was truncated, none of the other errors
2374 * matter */
2375 if (status & RXBD_TRUNCATED) {
2376 stats->rx_length_errors++;
2377
2378 estats->rx_trunc++;
2379
2380 return;
2381 }
2382 /* Count the errors, if there were any */
2383 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2384 stats->rx_length_errors++;
2385
2386 if (status & RXBD_LARGE)
2387 estats->rx_large++;
2388 else
2389 estats->rx_short++;
2390 }
2391 if (status & RXBD_NONOCTET) {
2392 stats->rx_frame_errors++;
2393 estats->rx_nonoctet++;
2394 }
2395 if (status & RXBD_CRCERR) {
2396 estats->rx_crcerr++;
2397 stats->rx_crc_errors++;
2398 }
2399 if (status & RXBD_OVERRUN) {
2400 estats->rx_overrun++;
2401 stats->rx_crc_errors++;
2402 }
2403}
2404
f4983704 2405irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2406{
f4983704 2407 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2408 return IRQ_HANDLED;
2409}
2410
0bbaf069
KG		 2411static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2412{
2413 /* If valid headers were found, and valid sums
2414 * were verified, then we tell the kernel that no
2415 * checksumming is necessary. Otherwise, it is */
7f7f5316 2416 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2417 skb->ip_summed = CHECKSUM_UNNECESSARY;
2418 else
2419 skb->ip_summed = CHECKSUM_NONE;
2420}
2421
2422
1da177e4
LT		 2423/* gfar_process_frame() -- handle one incoming packet if skb
2424 * isn't NULL. */
2425static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2c2db48a 2426 int amount_pull)
1da177e4
LT		 2427{
2428 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2429 struct rxfcb *fcb = NULL;
1da177e4 2430
2c2db48a 2431 int ret;
1da177e4 2432
2c2db48a
DH		 2433 /* fcb is at the beginning if exists */
2434 fcb = (struct rxfcb *)skb->data;
0bbaf069 2435
2c2db48a 2436 /* Remove the FCB from the skb */
fba4ed03 2437 skb_set_queue_mapping(skb, fcb->rq);
2c2db48a
DH		 2438 /* Remove the padded bytes, if there are any */
2439 if (amount_pull)
2440 skb_pull(skb, amount_pull);
0bbaf069 2441
2c2db48a
DH		 2442 if (priv->rx_csum_enable)
2443 gfar_rx_checksum(skb, fcb);
0bbaf069 2444
2c2db48a
DH		 2445 /* Tell the skb what kind of packet this is */
2446 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2447
2c2db48a
DH		 2448 /* Send the packet up the stack */
2449 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2450 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2451 else
2452 ret = netif_receive_skb(skb);
0bbaf069 2453
2c2db48a
DH		 2454 if (NET_RX_DROP == ret)
2455 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2456
2457 return 0;
2458}
2459
2460/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2461 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2462 * of frames handled
2463 */
a12f801d 2464int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2465{
a12f801d 2466 struct net_device *dev = rx_queue->dev;
31de198b 2467 struct rxbd8 *bdp, *base;
1da177e4 2468 struct sk_buff *skb;
2c2db48a
DH		 2469 int pkt_len;
2470 int amount_pull;
1da177e4
LT		 2471 int howmany = 0;
2472 struct gfar_private *priv = netdev_priv(dev);
2473
2474 /* Get the first full descriptor */
a12f801d
SG		 2475 bdp = rx_queue->cur_rx;
2476 base = rx_queue->rx_bd_base;
1da177e4 2477
2c2db48a
DH		 2478 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
2479 priv->padding;
2480
1da177e4 2481 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2482 struct sk_buff *newskb;
3b6330ce 2483 rmb();
815b97c6
AF		 2484
2485 /* Add another skb for the future */
2486 newskb = gfar_new_skb(dev);
2487
a12f801d 2488 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2489
4826857f 2490 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2491 priv->rx_buffer_size, DMA_FROM_DEVICE);
2492
815b97c6
AF		 2493 /* We drop the frame if we failed to allocate a new buffer */
2494 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2495 bdp->status & RXBD_ERR)) {
2496 count_errors(bdp->status, dev);
2497
2498 if (unlikely(!newskb))
2499 newskb = skb;
4e2fd555
LB		 2500 else if (skb) {
2501 /*
2502 * We need to reset ->data to what it
2503 * was before gfar_new_skb() re-aligned
2504 * it to an RXBUF_ALIGNMENT boundary
2505 * before we put the skb back on the
2506 * recycle list.
2507 */
2508 skb->data = skb->head + NET_SKB_PAD;
0fd56bb5 2509 __skb_queue_head(&priv->rx_recycle, skb);
4e2fd555 2510 }
815b97c6 2511 } else {
1da177e4 2512 /* Increment the number of packets */
09f75cd7 2513 dev->stats.rx_packets++;
1da177e4
LT		 2514 howmany++;
2515
2c2db48a
DH		 2516 if (likely(skb)) {
2517 pkt_len = bdp->length - ETH_FCS_LEN;
2518 /* Remove the FCS from the packet length */
2519 skb_put(skb, pkt_len);
2520 dev->stats.rx_bytes += pkt_len;
1da177e4 2521
2c2db48a
DH		 2522 gfar_process_frame(dev, skb, amount_pull);
2523
2524 } else {
2525 if (netif_msg_rx_err(priv))
2526 printk(KERN_WARNING
2527 "%s: Missing skb!\n", dev->name);
2528 dev->stats.rx_dropped++;
2529 priv->extra_stats.rx_skbmissing++;
2530 }
1da177e4 2531
1da177e4
LT		 2532 }
2533
a12f801d 2534 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2535
815b97c6 2536 /* Setup the new bdp */
a12f801d 2537 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2538
2539 /* Update to the next pointer */
a12f801d 2540 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2541
2542 /* update to point at the next skb */
a12f801d
SG		 2543 rx_queue->skb_currx =
2544 (rx_queue->skb_currx + 1) &
2545 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2546 }
2547
2548 /* Update the current rxbd pointer to be the next one */
a12f801d 2549 rx_queue->cur_rx = bdp;
1da177e4 2550
1da177e4
LT		 2551 return howmany;
2552}
2553
bea3348e 2554static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2555{
fba4ed03
SG		 2556 struct gfar_priv_grp *gfargrp = container_of(napi,
2557 struct gfar_priv_grp, napi);
2558 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2559 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2560 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2561 struct gfar_priv_rx_q *rx_queue = NULL;
2562 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2563 int tx_cleaned = 0, i, left_over_budget = budget;
2564 unsigned long serviced_queues = 0;
fba4ed03 2565 int num_queues = 0;
d080cd63 2566
fba4ed03
SG		 2567 num_queues = gfargrp->num_rx_queues;
2568 budget_per_queue = budget/num_queues;
2569
8c7396ae
DH		 2570 /* Clear IEVENT, so interrupts aren't called again
2571 * because of the packets that have already arrived */
f4983704 2572 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2573
fba4ed03 2574 while (num_queues && left_over_budget) {
1da177e4 2575
fba4ed03
SG		 2576 budget_per_queue = left_over_budget/num_queues;
2577 left_over_budget = 0;
2578
2579 for_each_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2580 if (test_bit(i, &serviced_queues))
2581 continue;
2582 rx_queue = priv->rx_queue[i];
2583 tx_queue = priv->tx_queue[rx_queue->qindex];
2584
a3bc1f11 2585 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2586 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2587 budget_per_queue);
2588 rx_cleaned += rx_cleaned_per_queue;
2589 if(rx_cleaned_per_queue < budget_per_queue) {
2590 left_over_budget = left_over_budget +
2591 (budget_per_queue - rx_cleaned_per_queue);
2592 set_bit(i, &serviced_queues);
2593 num_queues--;
2594 }
2595 }
2596 }
1da177e4 2597
42199884
AF		 2598 if (tx_cleaned)
2599 return budget;
2600
2601 if (rx_cleaned < budget) {
288379f0 2602 napi_complete(napi);
1da177e4
LT		 2603
2604 /* Clear the halt bit in RSTAT */
fba4ed03 2605 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2606
f4983704 2607 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2608
2609 /* If we are coalescing interrupts, update the timer */
2610 /* Otherwise, clear it */
46ceb60c
SG		 2611 gfar_configure_coalescing(priv,
2612 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2613 }
2614
42199884 2615 return rx_cleaned;
1da177e4 2616}
1da177e4 2617
f2d71c2d
VW		 2618#ifdef CONFIG_NET_POLL_CONTROLLER
2619/*
2620 * Polling 'interrupt' - used by things like netconsole to send skbs
2621 * without having to re-enable interrupts. It's not called while
2622 * the interrupt routine is executing.
2623 */
2624static void gfar_netpoll(struct net_device *dev)
2625{
2626 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2627 int i = 0;
f2d71c2d
VW		 2628
2629 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2630 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2631 for (i = 0; i < priv->num_grps; i++) {
2632 disable_irq(priv->gfargrp[i].interruptTransmit);
2633 disable_irq(priv->gfargrp[i].interruptReceive);
2634 disable_irq(priv->gfargrp[i].interruptError);
2635 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2636 &priv->gfargrp[i]);
2637 enable_irq(priv->gfargrp[i].interruptError);
2638 enable_irq(priv->gfargrp[i].interruptReceive);
2639 enable_irq(priv->gfargrp[i].interruptTransmit);
2640 }
f2d71c2d 2641 } else {
46ceb60c
SG		 2642 for (i = 0; i < priv->num_grps; i++) {
2643 disable_irq(priv->gfargrp[i].interruptTransmit);
2644 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2645 &priv->gfargrp[i]);
2646 enable_irq(priv->gfargrp[i].interruptTransmit);
f2d71c2d
VW		 2647 }
2648}
2649#endif
2650
1da177e4 2651/* The interrupt handler for devices with one interrupt */
f4983704 2652static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2653{
f4983704 2654 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2655
2656 /* Save ievent for future reference */
f4983704 2657 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2658
1da177e4 2659 /* Check for reception */
538cc7ee 2660 if (events & IEVENT_RX_MASK)
f4983704 2661 gfar_receive(irq, grp_id);
1da177e4
LT		 2662
2663 /* Check for transmit completion */
538cc7ee 2664 if (events & IEVENT_TX_MASK)
f4983704 2665 gfar_transmit(irq, grp_id);
1da177e4 2666
538cc7ee
SS		 2667 /* Check for errors */
2668 if (events & IEVENT_ERR_MASK)
f4983704 2669 gfar_error(irq, grp_id);
1da177e4
LT		 2670
2671 return IRQ_HANDLED;
2672}
2673
1da177e4
LT		 2674/* Called every time the controller might need to be made
2675 * aware of new link state. The PHY code conveys this
bb40dcbb 2676 * information through variables in the phydev structure, and this
1da177e4
LT		 2677 * function converts those variables into the appropriate
2678 * register values, and can bring down the device if needed.
2679 */
2680static void adjust_link(struct net_device *dev)
2681{
2682 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2683 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2684 unsigned long flags;
2685 struct phy_device *phydev = priv->phydev;
2686 int new_state = 0;
2687
fba4ed03
SG		 2688 local_irq_save(flags);
2689 lock_tx_qs(priv);
2690
bb40dcbb
AF		 2691 if (phydev->link) {
2692 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2693 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2694
1da177e4
LT		 2695 /* Now we make sure that we can be in full duplex mode.
2696 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2697 if (phydev->duplex != priv->oldduplex) {
2698 new_state = 1;
2699 if (!(phydev->duplex))
1da177e4 2700 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2701 else
1da177e4 2702 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2703
bb40dcbb 2704 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2705 }
2706
bb40dcbb
AF		 2707 if (phydev->speed != priv->oldspeed) {
2708 new_state = 1;
2709 switch (phydev->speed) {
1da177e4 2710 case 1000:
1da177e4
LT		 2711 tempval =
2712 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2713
2714 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2715 break;
2716 case 100:
2717 case 10:
1da177e4
LT		 2718 tempval =
2719 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2720
2721 /* Reduced mode distinguishes
2722 * between 10 and 100 */
2723 if (phydev->speed == SPEED_100)
2724 ecntrl |= ECNTRL_R100;
2725 else
2726 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2727 break;
2728 default:
0bbaf069
KG		 2729 if (netif_msg_link(priv))
2730 printk(KERN_WARNING
bb40dcbb
AF		 2731 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2732 dev->name, phydev->speed);
1da177e4
LT		 2733 break;
2734 }
2735
bb40dcbb 2736 priv->oldspeed = phydev->speed;
1da177e4
LT		 2737 }
2738
bb40dcbb 2739 gfar_write(&regs->maccfg2, tempval);
7f7f5316 2740 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 2741
1da177e4 2742 if (!priv->oldlink) {
bb40dcbb 2743 new_state = 1;
1da177e4 2744 priv->oldlink = 1;
1da177e4 2745 }
bb40dcbb
AF		 2746 } else if (priv->oldlink) {
2747 new_state = 1;
2748 priv->oldlink = 0;
2749 priv->oldspeed = 0;
2750 priv->oldduplex = -1;
1da177e4 2751 }
1da177e4 2752
bb40dcbb
AF		 2753 if (new_state && netif_msg_link(priv))
2754 phy_print_status(phydev);
fba4ed03
SG		 2755 unlock_tx_qs(priv);
2756 local_irq_restore(flags);
bb40dcbb 2757}
1da177e4
LT		 2758
2759/* Update the hash table based on the current list of multicast
2760 * addresses we subscribe to. Also, change the promiscuity of
2761 * the device based on the flags (this function is called
2762 * whenever dev->flags is changed */
2763static void gfar_set_multi(struct net_device *dev)
2764{
2765 struct dev_mc_list *mc_ptr;
2766 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2767 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 2768 u32 tempval;
2769
a12f801d 2770 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 2771 /* Set RCTRL to PROM */
2772 tempval = gfar_read(&regs->rctrl);
2773 tempval |= RCTRL_PROM;
2774 gfar_write(&regs->rctrl, tempval);
2775 } else {
2776 /* Set RCTRL to not PROM */
2777 tempval = gfar_read(&regs->rctrl);
2778 tempval &= ~(RCTRL_PROM);
2779 gfar_write(&regs->rctrl, tempval);
2780 }
6aa20a22 2781
a12f801d 2782 if (dev->flags & IFF_ALLMULTI) {
1da177e4 2783 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 2784 gfar_write(&regs->igaddr0, 0xffffffff);
2785 gfar_write(&regs->igaddr1, 0xffffffff);
2786 gfar_write(&regs->igaddr2, 0xffffffff);
2787 gfar_write(&regs->igaddr3, 0xffffffff);
2788 gfar_write(&regs->igaddr4, 0xffffffff);
2789 gfar_write(&regs->igaddr5, 0xffffffff);
2790 gfar_write(&regs->igaddr6, 0xffffffff);
2791 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 2792 gfar_write(&regs->gaddr0, 0xffffffff);
2793 gfar_write(&regs->gaddr1, 0xffffffff);
2794 gfar_write(&regs->gaddr2, 0xffffffff);
2795 gfar_write(&regs->gaddr3, 0xffffffff);
2796 gfar_write(&regs->gaddr4, 0xffffffff);
2797 gfar_write(&regs->gaddr5, 0xffffffff);
2798 gfar_write(&regs->gaddr6, 0xffffffff);
2799 gfar_write(&regs->gaddr7, 0xffffffff);
2800 } else {
7f7f5316
AF		 2801 int em_num;
2802 int idx;
2803
1da177e4 2804 /* zero out the hash */
0bbaf069
KG		 2805 gfar_write(&regs->igaddr0, 0x0);
2806 gfar_write(&regs->igaddr1, 0x0);
2807 gfar_write(&regs->igaddr2, 0x0);
2808 gfar_write(&regs->igaddr3, 0x0);
2809 gfar_write(&regs->igaddr4, 0x0);
2810 gfar_write(&regs->igaddr5, 0x0);
2811 gfar_write(&regs->igaddr6, 0x0);
2812 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 2813 gfar_write(&regs->gaddr0, 0x0);
2814 gfar_write(&regs->gaddr1, 0x0);
2815 gfar_write(&regs->gaddr2, 0x0);
2816 gfar_write(&regs->gaddr3, 0x0);
2817 gfar_write(&regs->gaddr4, 0x0);
2818 gfar_write(&regs->gaddr5, 0x0);
2819 gfar_write(&regs->gaddr6, 0x0);
2820 gfar_write(&regs->gaddr7, 0x0);
2821
7f7f5316
AF		 2822 /* If we have extended hash tables, we need to
2823 * clear the exact match registers to prepare for
2824 * setting them */
2825 if (priv->extended_hash) {
2826 em_num = GFAR_EM_NUM + 1;
2827 gfar_clear_exact_match(dev);
2828 idx = 1;
2829 } else {
2830 idx = 0;
2831 em_num = 0;
2832 }
2833
a12f801d 2834 if (dev->mc_count == 0)
1da177e4
LT		 2835 return;
2836
2837 /* Parse the list, and set the appropriate bits */
2838 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
7f7f5316
AF		 2839 if (idx < em_num) {
2840 gfar_set_mac_for_addr(dev, idx,
2841 mc_ptr->dmi_addr);
2842 idx++;
2843 } else
2844 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1da177e4
LT		 2845 }
2846 }
2847
2848 return;
2849}
2850
7f7f5316
AF		 2851
2852/* Clears each of the exact match registers to zero, so they
2853 * don't interfere with normal reception */
2854static void gfar_clear_exact_match(struct net_device *dev)
2855{
2856 int idx;
2857 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2858
2859 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2860 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2861}
2862
1da177e4
LT		 2863/* Set the appropriate hash bit for the given addr */
2864/* The algorithm works like so:
2865 * 1) Take the Destination Address (ie the multicast address), and
2866 * do a CRC on it (little endian), and reverse the bits of the
2867 * result.
2868 * 2) Use the 8 most significant bits as a hash into a 256-entry
2869 * table. The table is controlled through 8 32-bit registers:
2870 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2871 * gaddr7. This means that the 3 most significant bits in the
2872 * hash index which gaddr register to use, and the 5 other bits
2873 * indicate which bit (assuming an IBM numbering scheme, which
2874 * for PowerPC (tm) is usually the case) in the register holds
2875 * the entry. */
2876static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2877{
2878 u32 tempval;
2879 struct gfar_private *priv = netdev_priv(dev);
1da177e4 2880 u32 result = ether_crc(MAC_ADDR_LEN, addr);
0bbaf069
KG		 2881 int width = priv->hash_width;
2882 u8 whichbit = (result >> (32 - width)) & 0x1f;
2883 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 2884 u32 value = (1 << (31-whichbit));
2885
0bbaf069 2886 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 2887 tempval |= value;
0bbaf069 2888 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 2889
2890 return;
2891}
2892
7f7f5316
AF		 2893
2894/* There are multiple MAC Address register pairs on some controllers
2895 * This function sets the numth pair to a given address
2896 */
2897static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2898{
2899 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2900 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316
AF		 2901 int idx;
2902 char tmpbuf[MAC_ADDR_LEN];
2903 u32 tempval;
f4983704 2904 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 2905
2906 macptr += num*2;
2907
2908 /* Now copy it into the mac registers backwards, cuz */
2909 /* little endian is silly */
2910 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2911 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2912
2913 gfar_write(macptr, *((u32 *) (tmpbuf)));
2914
2915 tempval = *((u32 *) (tmpbuf + 4));
2916
2917 gfar_write(macptr+1, tempval);
2918}
2919
1da177e4 2920/* GFAR error interrupt handler */
f4983704 2921static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 2922{
f4983704
SG		 2923 struct gfar_priv_grp *gfargrp = grp_id;
2924 struct gfar __iomem *regs = gfargrp->regs;
2925 struct gfar_private *priv= gfargrp->priv;
2926 struct net_device *dev = priv->ndev;
1da177e4
LT		 2927
2928 /* Save ievent for future reference */
f4983704 2929 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 2930
2931 /* Clear IEVENT */
f4983704 2932 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 2933
2934 /* Magic Packet is not an error. */
b31a1d8b 2935 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 2936 (events & IEVENT_MAG))
2937 events &= ~IEVENT_MAG;
1da177e4
LT		 2938
2939 /* Hmm... */
0bbaf069
KG		 2940 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2941 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
f4983704 2942 dev->name, events, gfar_read(&regs->imask));
1da177e4
LT		 2943
2944 /* Update the error counters */
2945 if (events & IEVENT_TXE) {
09f75cd7 2946 dev->stats.tx_errors++;
1da177e4
LT		 2947
2948 if (events & IEVENT_LC)
09f75cd7 2949 dev->stats.tx_window_errors++;
1da177e4 2950 if (events & IEVENT_CRL)
09f75cd7 2951 dev->stats.tx_aborted_errors++;
1da177e4 2952 if (events & IEVENT_XFUN) {
836cf7fa
AV		 2953 unsigned long flags;
2954
0bbaf069 2955 if (netif_msg_tx_err(priv))
538cc7ee
SS		 2956 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2957 "packet dropped.\n", dev->name);
09f75cd7 2958 dev->stats.tx_dropped++;
1da177e4
LT		 2959 priv->extra_stats.tx_underrun++;
2960
836cf7fa
AV		 2961 local_irq_save(flags);
2962 lock_tx_qs(priv);
2963
1da177e4 2964 /* Reactivate the Tx Queues */
fba4ed03 2965 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 2966
2967 unlock_tx_qs(priv);
2968 local_irq_restore(flags);
1da177e4 2969 }
0bbaf069
KG		 2970 if (netif_msg_tx_err(priv))
2971 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1da177e4
LT		 2972 }
2973 if (events & IEVENT_BSY) {
09f75cd7 2974 dev->stats.rx_errors++;
1da177e4
LT		 2975 priv->extra_stats.rx_bsy++;
2976
f4983704 2977 gfar_receive(irq, grp_id);
1da177e4 2978
0bbaf069 2979 if (netif_msg_rx_err(priv))
538cc7ee 2980 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
f4983704 2981 dev->name, gfar_read(&regs->rstat));
1da177e4
LT		 2982 }
2983 if (events & IEVENT_BABR) {
09f75cd7 2984 dev->stats.rx_errors++;
1da177e4
LT		 2985 priv->extra_stats.rx_babr++;
2986
0bbaf069 2987 if (netif_msg_rx_err(priv))
538cc7ee 2988 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
1da177e4
LT		 2989 }
2990 if (events & IEVENT_EBERR) {
2991 priv->extra_stats.eberr++;
0bbaf069 2992 if (netif_msg_rx_err(priv))
538cc7ee 2993 printk(KERN_DEBUG "%s: bus error\n", dev->name);
1da177e4 2994 }
0bbaf069 2995 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
538cc7ee 2996 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1da177e4
LT		 2997
2998 if (events & IEVENT_BABT) {
2999 priv->extra_stats.tx_babt++;
0bbaf069 3000 if (netif_msg_tx_err(priv))
538cc7ee 3001 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
1da177e4
LT		 3002 }
3003 return IRQ_HANDLED;
3004}
3005
b31a1d8b
AF		 3006static struct of_device_id gfar_match[] =
3007{
3008 {
3009 .type = "network",
3010 .compatible = "gianfar",
3011 },
46ceb60c
SG		 3012 {
3013 .compatible = "fsl,etsec2",
3014 },
b31a1d8b
AF		 3015 {},
3016};
e72701ac 3017MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3018
1da177e4 3019/* Structure for a device driver */
b31a1d8b
AF		 3020static struct of_platform_driver gfar_driver = {
3021 .name = "fsl-gianfar",
3022 .match_table = gfar_match,
3023
1da177e4
LT		 3024 .probe = gfar_probe,
3025 .remove = gfar_remove,
be926fc4
AV		 3026 .suspend = gfar_legacy_suspend,
3027 .resume = gfar_legacy_resume,
3028 .driver.pm = GFAR_PM_OPS,
1da177e4
LT		 3029};
3030
3031static int __init gfar_init(void)
3032{
1577ecef 3033 return of_register_platform_driver(&gfar_driver);
1da177e4
LT		 3034}
3035
3036static void __exit gfar_exit(void)
3037{
b31a1d8b 3038 of_unregister_platform_driver(&gfar_driver);
1da177e4
LT		 3039}
3040
3041module_init(gfar_init);
3042module_exit(gfar_exit);
3043
Clone of davem's net-next-2.6 tree