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e1000e: 82577/8/9 issues with device in Sx
[net-next-2.6.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
451152d9 4 Copyright(c) 1999 - 2010 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
d3738bb8
BA		 55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
bc7f75fa
AK		 57 */
58
bc7f75fa
AK		 59#include "e1000.h"
60
61#define ICH_FLASH_GFPREG 0x0000
62#define ICH_FLASH_HSFSTS 0x0004
63#define ICH_FLASH_HSFCTL 0x0006
64#define ICH_FLASH_FADDR 0x0008
65#define ICH_FLASH_FDATA0 0x0010
4a770358 66#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 67
68#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74#define ICH_CYCLE_READ 0
75#define ICH_CYCLE_WRITE 2
76#define ICH_CYCLE_ERASE 3
77
78#define FLASH_GFPREG_BASE_MASK 0x1FFF
79#define FLASH_SECTOR_ADDR_SHIFT 12
80
81#define ICH_FLASH_SEG_SIZE_256 256
82#define ICH_FLASH_SEG_SIZE_4K 4096
83#define ICH_FLASH_SEG_SIZE_8K 8192
84#define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6dfaa769
BA		 88/* FW established a valid mode */
89#define E1000_ICH_FWSM_FW_VALID 0x00008000
bc7f75fa
AK		 90
91#define E1000_ICH_MNG_IAMT_MODE 0x2
92
93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98#define E1000_ICH_NVM_SIG_WORD 0x13
99#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 102
103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105#define E1000_FEXTNVM_SW_CONFIG 1
106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
109
110#define E1000_ICH_RAR_ENTRIES 7
111
112#define PHY_PAGE_SHIFT 5
113#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
114 ((reg) & MAX_PHY_REG_ADDRESS))
115#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
116#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
117
118#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
119#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
120#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
121
a4f58f54
BA		 122#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
123
53ac5a88
BA		 124#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
125
f523d211
BA		 126/* SMBus Address Phy Register */
127#define HV_SMB_ADDR PHY_REG(768, 26)
8395ae83 128#define HV_SMB_ADDR_MASK 0x007F
f523d211
BA		 129#define HV_SMB_ADDR_PEC_EN 0x0200
130#define HV_SMB_ADDR_VALID 0x0080
131
d3738bb8
BA		 132/* PHY Power Management Control */
133#define HV_PM_CTRL PHY_REG(770, 17)
134
e52997f9
BA		 135/* PHY Low Power Idle Control */
136#define I82579_LPI_CTRL PHY_REG(772, 20)
137#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
138
f523d211
BA		 139/* Strapping Option Register - RO */
140#define E1000_STRAP 0x0000C
141#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
142#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
143
fa2ce13c
BA		 144/* OEM Bits Phy Register */
145#define HV_OEM_BITS PHY_REG(768, 25)
146#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 147#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 148#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
149
1d5846b9
BA		 150#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
151#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
152
fddaa1af
BA		 153/* KMRN Mode Control */
154#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
155#define HV_KMRN_MDIO_SLOW 0x0400
156
bc7f75fa
AK		 157/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
158/* Offset 04h HSFSTS */
159union ich8_hws_flash_status {
160 struct ich8_hsfsts {
161 u16 flcdone :1; /* bit 0 Flash Cycle Done */
162 u16 flcerr :1; /* bit 1 Flash Cycle Error */
163 u16 dael :1; /* bit 2 Direct Access error Log */
164 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
165 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
166 u16 reserved1 :2; /* bit 13:6 Reserved */
167 u16 reserved2 :6; /* bit 13:6 Reserved */
168 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
169 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
170 } hsf_status;
171 u16 regval;
172};
173
174/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
175/* Offset 06h FLCTL */
176union ich8_hws_flash_ctrl {
177 struct ich8_hsflctl {
178 u16 flcgo :1; /* 0 Flash Cycle Go */
179 u16 flcycle :2; /* 2:1 Flash Cycle */
180 u16 reserved :5; /* 7:3 Reserved */
181 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
182 u16 flockdn :6; /* 15:10 Reserved */
183 } hsf_ctrl;
184 u16 regval;
185};
186
187/* ICH Flash Region Access Permissions */
188union ich8_hws_flash_regacc {
189 struct ich8_flracc {
190 u32 grra :8; /* 0:7 GbE region Read Access */
191 u32 grwa :8; /* 8:15 GbE region Write Access */
192 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
193 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
194 } hsf_flregacc;
195 u16 regval;
196};
197
4a770358
BA		 198/* ICH Flash Protected Region */
199union ich8_flash_protected_range {
200 struct ich8_pr {
201 u32 base:13; /* 0:12 Protected Range Base */
202 u32 reserved1:2; /* 13:14 Reserved */
203 u32 rpe:1; /* 15 Read Protection Enable */
204 u32 limit:13; /* 16:28 Protected Range Limit */
205 u32 reserved2:2; /* 29:30 Reserved */
206 u32 wpe:1; /* 31 Write Protection Enable */
207 } range;
208 u32 regval;
209};
210
bc7f75fa
AK		 211static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
212static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
213static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 214static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
215static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
216 u32 offset, u8 byte);
f4187b56
BA		 217static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
218 u8 *data);
bc7f75fa
AK		 219static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
220 u16 *data);
221static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
222 u8 size, u16 *data);
223static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
224static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 225static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 226static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
227static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
228static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
229static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
230static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
231static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
232static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
233static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 234static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 235static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 236static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 237static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 238static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 239static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
240static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
bc7f75fa
AK		 241
242static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
243{
244 return readw(hw->flash_address + reg);
245}
246
247static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
248{
249 return readl(hw->flash_address + reg);
250}
251
252static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
253{
254 writew(val, hw->flash_address + reg);
255}
256
257static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
258{
259 writel(val, hw->flash_address + reg);
260}
261
262#define er16flash(reg) __er16flash(hw, (reg))
263#define er32flash(reg) __er32flash(hw, (reg))
264#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
265#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
266
a4f58f54
BA		 267/**
268 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
269 * @hw: pointer to the HW structure
270 *
271 * Initialize family-specific PHY parameters and function pointers.
272 **/
273static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
274{
275 struct e1000_phy_info *phy = &hw->phy;
6dfaa769 276 u32 ctrl;
a4f58f54
BA		 277 s32 ret_val = 0;
278
279 phy->addr = 1;
280 phy->reset_delay_us = 100;
281
94d8186a
BA		 282 phy->ops.read_reg = e1000_read_phy_reg_hv;
283 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 284 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
285 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 286 phy->ops.write_reg = e1000_write_phy_reg_hv;
287 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
17f208de
BA		 288 phy->ops.power_up = e1000_power_up_phy_copper;
289 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 290 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
291
d3738bb8
BA		 292 /*
293 * The MAC-PHY interconnect may still be in SMBus mode
294 * after Sx->S0. If the manageability engine (ME) is
295 * disabled, then toggle the LANPHYPC Value bit to force
296 * the interconnect to PCIe mode.
297 */
6dfaa769 298 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
6dfaa769
BA		 299 ctrl = er32(CTRL);
300 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
301 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
302 ew32(CTRL, ctrl);
303 udelay(10);
304 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
305 ew32(CTRL, ctrl);
306 msleep(50);
307 }
308
627c8a04
BA		 309 /*
310 * Reset the PHY before any acccess to it. Doing so, ensures that
311 * the PHY is in a known good state before we read/write PHY registers.
312 * The generic reset is sufficient here, because we haven't determined
313 * the PHY type yet.
314 */
315 ret_val = e1000e_phy_hw_reset_generic(hw);
316 if (ret_val)
317 goto out;
318
a4f58f54 319 phy->id = e1000_phy_unknown;
fddaa1af
BA		 320 ret_val = e1000e_get_phy_id(hw);
321 if (ret_val)
322 goto out;
323 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
324 /*
325 * In case the PHY needs to be in mdio slow mode (eg. 82577),
326 * set slow mode and try to get the PHY id again.
327 */
328 ret_val = e1000_set_mdio_slow_mode_hv(hw);
329 if (ret_val)
330 goto out;
331 ret_val = e1000e_get_phy_id(hw);
332 if (ret_val)
333 goto out;
334 }
a4f58f54
BA		 335 phy->type = e1000e_get_phy_type_from_id(phy->id);
336
0be84010
BA		 337 switch (phy->type) {
338 case e1000_phy_82577:
d3738bb8 339 case e1000_phy_82579:
a4f58f54
BA		 340 phy->ops.check_polarity = e1000_check_polarity_82577;
341 phy->ops.force_speed_duplex =
342 e1000_phy_force_speed_duplex_82577;
0be84010 343 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 344 phy->ops.get_info = e1000_get_phy_info_82577;
345 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 346 break;
0be84010
BA		 347 case e1000_phy_82578:
348 phy->ops.check_polarity = e1000_check_polarity_m88;
349 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
350 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
351 phy->ops.get_info = e1000e_get_phy_info_m88;
352 break;
353 default:
354 ret_val = -E1000_ERR_PHY;
355 break;
a4f58f54
BA		 356 }
357
fddaa1af 358out:
a4f58f54
BA		 359 return ret_val;
360}
361
bc7f75fa
AK		 362/**
363 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
364 * @hw: pointer to the HW structure
365 *
366 * Initialize family-specific PHY parameters and function pointers.
367 **/
368static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
369{
370 struct e1000_phy_info *phy = &hw->phy;
371 s32 ret_val;
372 u16 i = 0;
373
374 phy->addr = 1;
375 phy->reset_delay_us = 100;
376
17f208de
BA		 377 phy->ops.power_up = e1000_power_up_phy_copper;
378 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
379
97ac8cae
BA		 380 /*
381 * We may need to do this twice - once for IGP and if that fails,
382 * we'll set BM func pointers and try again
383 */
384 ret_val = e1000e_determine_phy_address(hw);
385 if (ret_val) {
94d8186a
BA		 386 phy->ops.write_reg = e1000e_write_phy_reg_bm;
387 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 388 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 389 if (ret_val) {
390 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 391 return ret_val;
9b71b419 392 }
97ac8cae
BA		 393 }
394
bc7f75fa
AK		 395 phy->id = 0;
396 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
397 (i++ < 100)) {
398 msleep(1);
399 ret_val = e1000e_get_phy_id(hw);
400 if (ret_val)
401 return ret_val;
402 }
403
404 /* Verify phy id */
405 switch (phy->id) {
406 case IGP03E1000_E_PHY_ID:
407 phy->type = e1000_phy_igp_3;
408 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 409 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
410 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 411 phy->ops.get_info = e1000e_get_phy_info_igp;
412 phy->ops.check_polarity = e1000_check_polarity_igp;
413 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 414 break;
415 case IFE_E_PHY_ID:
416 case IFE_PLUS_E_PHY_ID:
417 case IFE_C_E_PHY_ID:
418 phy->type = e1000_phy_ife;
419 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 420 phy->ops.get_info = e1000_get_phy_info_ife;
421 phy->ops.check_polarity = e1000_check_polarity_ife;
422 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 423 break;
97ac8cae
BA		 424 case BME1000_E_PHY_ID:
425 phy->type = e1000_phy_bm;
426 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 427 phy->ops.read_reg = e1000e_read_phy_reg_bm;
428 phy->ops.write_reg = e1000e_write_phy_reg_bm;
429 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 430 phy->ops.get_info = e1000e_get_phy_info_m88;
431 phy->ops.check_polarity = e1000_check_polarity_m88;
432 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 433 break;
bc7f75fa
AK		 434 default:
435 return -E1000_ERR_PHY;
436 break;
437 }
438
439 return 0;
440}
441
442/**
443 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
444 * @hw: pointer to the HW structure
445 *
446 * Initialize family-specific NVM parameters and function
447 * pointers.
448 **/
449static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
450{
451 struct e1000_nvm_info *nvm = &hw->nvm;
452 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 453 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 454 u16 i;
455
ad68076e 456 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 457 if (!hw->flash_address) {
3bb99fe2 458 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 459 return -E1000_ERR_CONFIG;
460 }
461
462 nvm->type = e1000_nvm_flash_sw;
463
464 gfpreg = er32flash(ICH_FLASH_GFPREG);
465
ad68076e
BA		 466 /*
467 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 468 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 469 * the overall size.
470 */
bc7f75fa
AK		 471 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
472 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
473
474 /* flash_base_addr is byte-aligned */
475 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
476
ad68076e
BA		 477 /*
478 * find total size of the NVM, then cut in half since the total
479 * size represents two separate NVM banks.
480 */
bc7f75fa
AK		 481 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
482 << FLASH_SECTOR_ADDR_SHIFT;
483 nvm->flash_bank_size /= 2;
484 /* Adjust to word count */
485 nvm->flash_bank_size /= sizeof(u16);
486
487 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
488
489 /* Clear shadow ram */
490 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 491 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 492 dev_spec->shadow_ram[i].value = 0xFFFF;
493 }
494
495 return 0;
496}
497
498/**
499 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
500 * @hw: pointer to the HW structure
501 *
502 * Initialize family-specific MAC parameters and function
503 * pointers.
504 **/
505static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
506{
507 struct e1000_hw *hw = &adapter->hw;
508 struct e1000_mac_info *mac = &hw->mac;
509
510 /* Set media type function pointer */
318a94d6 511 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 512
513 /* Set mta register count */
514 mac->mta_reg_count = 32;
515 /* Set rar entry count */
516 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
517 if (mac->type == e1000_ich8lan)
518 mac->rar_entry_count--;
a65a4a0d
BA		 519 /* FWSM register */
520 mac->has_fwsm = true;
521 /* ARC subsystem not supported */
522 mac->arc_subsystem_valid = false;
f464ba87
BA		 523 /* Adaptive IFS supported */
524 mac->adaptive_ifs = true;
bc7f75fa 525
a4f58f54
BA		 526 /* LED operations */
527 switch (mac->type) {
528 case e1000_ich8lan:
529 case e1000_ich9lan:
530 case e1000_ich10lan:
eb7700dc
BA		 531 /* check management mode */
532 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54
BA		 533 /* ID LED init */
534 mac->ops.id_led_init = e1000e_id_led_init;
535 /* setup LED */
536 mac->ops.setup_led = e1000e_setup_led_generic;
537 /* cleanup LED */
538 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
539 /* turn on/off LED */
540 mac->ops.led_on = e1000_led_on_ich8lan;
541 mac->ops.led_off = e1000_led_off_ich8lan;
542 break;
543 case e1000_pchlan:
d3738bb8 544 case e1000_pch2lan:
eb7700dc
BA		 545 /* check management mode */
546 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 547 /* ID LED init */
548 mac->ops.id_led_init = e1000_id_led_init_pchlan;
549 /* setup LED */
550 mac->ops.setup_led = e1000_setup_led_pchlan;
551 /* cleanup LED */
552 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
553 /* turn on/off LED */
554 mac->ops.led_on = e1000_led_on_pchlan;
555 mac->ops.led_off = e1000_led_off_pchlan;
556 break;
557 default:
558 break;
559 }
560
bc7f75fa
AK		 561 /* Enable PCS Lock-loss workaround for ICH8 */
562 if (mac->type == e1000_ich8lan)
564ea9bb 563 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa 564
d3738bb8
BA		 565 /* Disable PHY configuration by hardware, config by software */
566 if (mac->type == e1000_pch2lan) {
567 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
568
569 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
570 ew32(EXTCNF_CTRL, extcnf_ctrl);
571 }
572
bc7f75fa
AK		 573 return 0;
574}
575
e52997f9
BA		 576/**
577 * e1000_set_eee_pchlan - Enable/disable EEE support
578 * @hw: pointer to the HW structure
579 *
580 * Enable/disable EEE based on setting in dev_spec structure. The bits in
581 * the LPI Control register will remain set only if/when link is up.
582 **/
583static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
584{
585 s32 ret_val = 0;
586 u16 phy_reg;
587
588 if (hw->phy.type != e1000_phy_82579)
589 goto out;
590
591 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
592 if (ret_val)
593 goto out;
594
595 if (hw->dev_spec.ich8lan.eee_disable)
596 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
597 else
598 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
599
600 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
601out:
602 return ret_val;
603}
604
7d3cabbc
BA		 605/**
606 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
607 * @hw: pointer to the HW structure
608 *
609 * Checks to see of the link status of the hardware has changed. If a
610 * change in link status has been detected, then we read the PHY registers
611 * to get the current speed/duplex if link exists.
612 **/
613static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
614{
615 struct e1000_mac_info *mac = &hw->mac;
616 s32 ret_val;
617 bool link;
618
619 /*
620 * We only want to go out to the PHY registers to see if Auto-Neg
621 * has completed and/or if our link status has changed. The
622 * get_link_status flag is set upon receiving a Link Status
623 * Change or Rx Sequence Error interrupt.
624 */
625 if (!mac->get_link_status) {
626 ret_val = 0;
627 goto out;
628 }
629
7d3cabbc
BA		 630 /*
631 * First we want to see if the MII Status Register reports
632 * link. If so, then we want to get the current speed/duplex
633 * of the PHY.
634 */
635 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
636 if (ret_val)
637 goto out;
638
1d5846b9
BA		 639 if (hw->mac.type == e1000_pchlan) {
640 ret_val = e1000_k1_gig_workaround_hv(hw, link);
641 if (ret_val)
642 goto out;
643 }
644
7d3cabbc
BA		 645 if (!link)
646 goto out; /* No link detected */
647
648 mac->get_link_status = false;
649
650 if (hw->phy.type == e1000_phy_82578) {
651 ret_val = e1000_link_stall_workaround_hv(hw);
652 if (ret_val)
653 goto out;
654 }
655
656 /*
657 * Check if there was DownShift, must be checked
658 * immediately after link-up
659 */
660 e1000e_check_downshift(hw);
661
e52997f9
BA		 662 /* Enable/Disable EEE after link up */
663 ret_val = e1000_set_eee_pchlan(hw);
664 if (ret_val)
665 goto out;
666
7d3cabbc
BA		 667 /*
668 * If we are forcing speed/duplex, then we simply return since
669 * we have already determined whether we have link or not.
670 */
671 if (!mac->autoneg) {
672 ret_val = -E1000_ERR_CONFIG;
673 goto out;
674 }
675
676 /*
677 * Auto-Neg is enabled. Auto Speed Detection takes care
678 * of MAC speed/duplex configuration. So we only need to
679 * configure Collision Distance in the MAC.
680 */
681 e1000e_config_collision_dist(hw);
682
683 /*
684 * Configure Flow Control now that Auto-Neg has completed.
685 * First, we need to restore the desired flow control
686 * settings because we may have had to re-autoneg with a
687 * different link partner.
688 */
689 ret_val = e1000e_config_fc_after_link_up(hw);
690 if (ret_val)
3bb99fe2 691 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 692
693out:
694 return ret_val;
695}
696
69e3fd8c 697static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 698{
699 struct e1000_hw *hw = &adapter->hw;
700 s32 rc;
701
702 rc = e1000_init_mac_params_ich8lan(adapter);
703 if (rc)
704 return rc;
705
706 rc = e1000_init_nvm_params_ich8lan(hw);
707 if (rc)
708 return rc;
709
d3738bb8
BA		 710 switch (hw->mac.type) {
711 case e1000_ich8lan:
712 case e1000_ich9lan:
713 case e1000_ich10lan:
a4f58f54 714 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 715 break;
716 case e1000_pchlan:
717 case e1000_pch2lan:
718 rc = e1000_init_phy_params_pchlan(hw);
719 break;
720 default:
721 break;
722 }
bc7f75fa
AK		 723 if (rc)
724 return rc;
725
2adc55c9
BA		 726 if (adapter->hw.phy.type == e1000_phy_ife) {
727 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
728 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
729 }
730
bc7f75fa
AK		 731 if ((adapter->hw.mac.type == e1000_ich8lan) &&
732 (adapter->hw.phy.type == e1000_phy_igp_3))
733 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
734
5a86f28f
BA		 735 /* Disable EEE by default until IEEE802.3az spec is finalized */
736 if (adapter->flags2 & FLAG2_HAS_EEE)
737 adapter->hw.dev_spec.ich8lan.eee_disable = true;
738
bc7f75fa
AK		 739 return 0;
740}
741
717d438d 742static DEFINE_MUTEX(nvm_mutex);
717d438d 743
ca15df58
BA		 744/**
745 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
746 * @hw: pointer to the HW structure
747 *
748 * Acquires the mutex for performing NVM operations.
749 **/
750static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
751{
752 mutex_lock(&nvm_mutex);
753
754 return 0;
755}
756
757/**
758 * e1000_release_nvm_ich8lan - Release NVM mutex
759 * @hw: pointer to the HW structure
760 *
761 * Releases the mutex used while performing NVM operations.
762 **/
763static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
764{
765 mutex_unlock(&nvm_mutex);
ca15df58
BA		 766}
767
768static DEFINE_MUTEX(swflag_mutex);
769
bc7f75fa
AK		 770/**
771 * e1000_acquire_swflag_ich8lan - Acquire software control flag
772 * @hw: pointer to the HW structure
773 *
ca15df58
BA		 774 * Acquires the software control flag for performing PHY and select
775 * MAC CSR accesses.
bc7f75fa
AK		 776 **/
777static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
778{
373a88d7
BA		 779 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
780 s32 ret_val = 0;
bc7f75fa 781
ca15df58 782 mutex_lock(&swflag_mutex);
717d438d 783
bc7f75fa
AK		 784 while (timeout) {
785 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 786 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
787 break;
bc7f75fa 788
373a88d7
BA		 789 mdelay(1);
790 timeout--;
791 }
792
793 if (!timeout) {
3bb99fe2 794 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 795 ret_val = -E1000_ERR_CONFIG;
796 goto out;
797 }
798
53ac5a88 799 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 800
801 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
802 ew32(EXTCNF_CTRL, extcnf_ctrl);
803
804 while (timeout) {
805 extcnf_ctrl = er32(EXTCNF_CTRL);
806 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
807 break;
a4f58f54 808
bc7f75fa
AK		 809 mdelay(1);
810 timeout--;
811 }
812
813 if (!timeout) {
3bb99fe2 814 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 815 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
816 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 817 ret_val = -E1000_ERR_CONFIG;
818 goto out;
bc7f75fa
AK		 819 }
820
373a88d7
BA		 821out:
822 if (ret_val)
ca15df58 823 mutex_unlock(&swflag_mutex);
373a88d7
BA		 824
825 return ret_val;
bc7f75fa
AK		 826}
827
828/**
829 * e1000_release_swflag_ich8lan - Release software control flag
830 * @hw: pointer to the HW structure
831 *
ca15df58
BA		 832 * Releases the software control flag for performing PHY and select
833 * MAC CSR accesses.
bc7f75fa
AK		 834 **/
835static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
836{
837 u32 extcnf_ctrl;
838
839 extcnf_ctrl = er32(EXTCNF_CTRL);
840 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
841 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 842
ca15df58 843 mutex_unlock(&swflag_mutex);
bc7f75fa
AK		 844}
845
4662e82b
BA		 846/**
847 * e1000_check_mng_mode_ich8lan - Checks management mode
848 * @hw: pointer to the HW structure
849 *
eb7700dc 850 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 851 * This is a function pointer entry point only called by read/write
852 * routines for the PHY and NVM parts.
853 **/
854static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
855{
a708dd88
BA		 856 u32 fwsm;
857
858 fwsm = er32(FWSM);
eb7700dc
BA		 859 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
860 ((fwsm & E1000_FWSM_MODE_MASK) ==
861 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
862}
4662e82b 863
eb7700dc
BA		 864/**
865 * e1000_check_mng_mode_pchlan - Checks management mode
866 * @hw: pointer to the HW structure
867 *
868 * This checks if the adapter has iAMT enabled.
869 * This is a function pointer entry point only called by read/write
870 * routines for the PHY and NVM parts.
871 **/
872static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
873{
874 u32 fwsm;
875
876 fwsm = er32(FWSM);
877 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
878 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 879}
880
bc7f75fa
AK		 881/**
882 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
883 * @hw: pointer to the HW structure
884 *
885 * Checks if firmware is blocking the reset of the PHY.
886 * This is a function pointer entry point only called by
887 * reset routines.
888 **/
889static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
890{
891 u32 fwsm;
892
893 fwsm = er32(FWSM);
894
895 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
896}
897
8395ae83
BA		 898/**
899 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
900 * @hw: pointer to the HW structure
901 *
902 * Assumes semaphore already acquired.
903 *
904 **/
905static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
906{
907 u16 phy_data;
908 u32 strap = er32(STRAP);
909 s32 ret_val = 0;
910
911 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
912
913 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
914 if (ret_val)
915 goto out;
916
917 phy_data &= ~HV_SMB_ADDR_MASK;
918 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
919 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
920 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
921
922out:
923 return ret_val;
924}
925
f523d211
BA		 926/**
927 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
928 * @hw: pointer to the HW structure
929 *
930 * SW should configure the LCD from the NVM extended configuration region
931 * as a workaround for certain parts.
932 **/
933static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
934{
8b802a7e 935 struct e1000_adapter *adapter = hw->adapter;
f523d211
BA		 936 struct e1000_phy_info *phy = &hw->phy;
937 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 938 s32 ret_val = 0;
f523d211
BA		 939 u16 word_addr, reg_data, reg_addr, phy_page = 0;
940
f523d211
BA		 941 /*
942 * Initialize the PHY from the NVM on ICH platforms. This
943 * is needed due to an issue where the NVM configuration is
944 * not properly autoloaded after power transitions.
945 * Therefore, after each PHY reset, we will load the
946 * configuration data out of the NVM manually.
947 */
3f0c16e8
BA		 948 switch (hw->mac.type) {
949 case e1000_ich8lan:
950 if (phy->type != e1000_phy_igp_3)
951 return ret_val;
952
953 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
954 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
955 break;
956 }
957 /* Fall-thru */
958 case e1000_pchlan:
d3738bb8 959 case e1000_pch2lan:
8b802a7e 960 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 961 break;
962 default:
963 return ret_val;
964 }
965
966 ret_val = hw->phy.ops.acquire(hw);
967 if (ret_val)
968 return ret_val;
8b802a7e
BA		 969
970 data = er32(FEXTNVM);
971 if (!(data & sw_cfg_mask))
972 goto out;
f523d211 973
8b802a7e
BA		 974 /*
975 * Make sure HW does not configure LCD from PHY
976 * extended configuration before SW configuration
977 */
978 data = er32(EXTCNF_CTRL);
d3738bb8
BA		 979 if (!(hw->mac.type == e1000_pch2lan)) {
980 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
981 goto out;
982 }
8b802a7e
BA		 983
984 cnf_size = er32(EXTCNF_SIZE);
985 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
986 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
987 if (!cnf_size)
988 goto out;
989
990 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
991 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
992
993 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
d3738bb8
BA		 994 ((hw->mac.type == e1000_pchlan) ||
995 (hw->mac.type == e1000_pch2lan))) {
f523d211 996 /*
8b802a7e
BA		 997 * HW configures the SMBus address and LEDs when the
998 * OEM and LCD Write Enable bits are set in the NVM.
999 * When both NVM bits are cleared, SW will configure
1000 * them instead.
f523d211 1001 */
8395ae83 1002 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1003 if (ret_val)
f523d211
BA		 1004 goto out;
1005
8b802a7e
BA		 1006 data = er32(LEDCTL);
1007 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1008 (u16)data);
1009 if (ret_val)
f523d211 1010 goto out;
8b802a7e 1011 }
f523d211 1012
8b802a7e
BA		 1013 /* Configure LCD from extended configuration region. */
1014
1015 /* cnf_base_addr is in DWORD */
1016 word_addr = (u16)(cnf_base_addr << 1);
1017
1018 for (i = 0; i < cnf_size; i++) {
1019 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1020 &reg_data);
1021 if (ret_val)
1022 goto out;
1023
1024 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1025 1, &reg_addr);
1026 if (ret_val)
1027 goto out;
1028
1029 /* Save off the PHY page for future writes. */
1030 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1031 phy_page = reg_data;
1032 continue;
f523d211 1033 }
8b802a7e
BA		 1034
1035 reg_addr &= PHY_REG_MASK;
1036 reg_addr |= phy_page;
1037
1038 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1039 reg_data);
1040 if (ret_val)
1041 goto out;
f523d211
BA		 1042 }
1043
1044out:
94d8186a 1045 hw->phy.ops.release(hw);
f523d211
BA		 1046 return ret_val;
1047}
1048
1d5846b9
BA		 1049/**
1050 * e1000_k1_gig_workaround_hv - K1 Si workaround
1051 * @hw: pointer to the HW structure
1052 * @link: link up bool flag
1053 *
1054 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1055 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1056 * If link is down, the function will restore the default K1 setting located
1057 * in the NVM.
1058 **/
1059static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1060{
1061 s32 ret_val = 0;
1062 u16 status_reg = 0;
1063 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1064
1065 if (hw->mac.type != e1000_pchlan)
1066 goto out;
1067
1068 /* Wrap the whole flow with the sw flag */
94d8186a 1069 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 1070 if (ret_val)
1071 goto out;
1072
1073 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1074 if (link) {
1075 if (hw->phy.type == e1000_phy_82578) {
94d8186a 1076 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 1077 &status_reg);
1078 if (ret_val)
1079 goto release;
1080
1081 status_reg &= BM_CS_STATUS_LINK_UP |
1082 BM_CS_STATUS_RESOLVED |
1083 BM_CS_STATUS_SPEED_MASK;
1084
1085 if (status_reg == (BM_CS_STATUS_LINK_UP |
1086 BM_CS_STATUS_RESOLVED |
1087 BM_CS_STATUS_SPEED_1000))
1088 k1_enable = false;
1089 }
1090
1091 if (hw->phy.type == e1000_phy_82577) {
94d8186a 1092 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 1093 &status_reg);
1094 if (ret_val)
1095 goto release;
1096
1097 status_reg &= HV_M_STATUS_LINK_UP |
1098 HV_M_STATUS_AUTONEG_COMPLETE |
1099 HV_M_STATUS_SPEED_MASK;
1100
1101 if (status_reg == (HV_M_STATUS_LINK_UP |
1102 HV_M_STATUS_AUTONEG_COMPLETE |
1103 HV_M_STATUS_SPEED_1000))
1104 k1_enable = false;
1105 }
1106
1107 /* Link stall fix for link up */
94d8186a 1108 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1109 0x0100);
1110 if (ret_val)
1111 goto release;
1112
1113 } else {
1114 /* Link stall fix for link down */
94d8186a 1115 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1116 0x4100);
1117 if (ret_val)
1118 goto release;
1119 }
1120
1121 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1122
1123release:
94d8186a 1124 hw->phy.ops.release(hw);
1d5846b9
BA		 1125out:
1126 return ret_val;
1127}
1128
1129/**
1130 * e1000_configure_k1_ich8lan - Configure K1 power state
1131 * @hw: pointer to the HW structure
1132 * @enable: K1 state to configure
1133 *
1134 * Configure the K1 power state based on the provided parameter.
1135 * Assumes semaphore already acquired.
1136 *
1137 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1138 **/
bb436b20 1139s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1140{
1141 s32 ret_val = 0;
1142 u32 ctrl_reg = 0;
1143 u32 ctrl_ext = 0;
1144 u32 reg = 0;
1145 u16 kmrn_reg = 0;
1146
1147 ret_val = e1000e_read_kmrn_reg_locked(hw,
1148 E1000_KMRNCTRLSTA_K1_CONFIG,
1149 &kmrn_reg);
1150 if (ret_val)
1151 goto out;
1152
1153 if (k1_enable)
1154 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1155 else
1156 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1157
1158 ret_val = e1000e_write_kmrn_reg_locked(hw,
1159 E1000_KMRNCTRLSTA_K1_CONFIG,
1160 kmrn_reg);
1161 if (ret_val)
1162 goto out;
1163
1164 udelay(20);
1165 ctrl_ext = er32(CTRL_EXT);
1166 ctrl_reg = er32(CTRL);
1167
1168 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1169 reg |= E1000_CTRL_FRCSPD;
1170 ew32(CTRL, reg);
1171
1172 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1173 udelay(20);
1174 ew32(CTRL, ctrl_reg);
1175 ew32(CTRL_EXT, ctrl_ext);
1176 udelay(20);
1177
1178out:
1179 return ret_val;
1180}
1181
f523d211
BA		 1182/**
1183 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1184 * @hw: pointer to the HW structure
1185 * @d0_state: boolean if entering d0 or d3 device state
1186 *
1187 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1188 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1189 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1190 **/
1191static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1192{
1193 s32 ret_val = 0;
1194 u32 mac_reg;
1195 u16 oem_reg;
1196
d3738bb8 1197 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
f523d211
BA		 1198 return ret_val;
1199
94d8186a 1200 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1201 if (ret_val)
1202 return ret_val;
1203
d3738bb8
BA		 1204 if (!(hw->mac.type == e1000_pch2lan)) {
1205 mac_reg = er32(EXTCNF_CTRL);
1206 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1207 goto out;
1208 }
f523d211
BA		 1209
1210 mac_reg = er32(FEXTNVM);
1211 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1212 goto out;
1213
1214 mac_reg = er32(PHY_CTRL);
1215
94d8186a 1216 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1217 if (ret_val)
1218 goto out;
1219
1220 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1221
1222 if (d0_state) {
1223 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1224 oem_reg |= HV_OEM_BITS_GBE_DIS;
1225
1226 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1227 oem_reg |= HV_OEM_BITS_LPLU;
1228 } else {
1229 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1230 oem_reg |= HV_OEM_BITS_GBE_DIS;
1231
1232 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1233 oem_reg |= HV_OEM_BITS_LPLU;
1234 }
1235 /* Restart auto-neg to activate the bits */
818f3331
BA		 1236 if (!e1000_check_reset_block(hw))
1237 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1238 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1239
1240out:
94d8186a 1241 hw->phy.ops.release(hw);
f523d211
BA		 1242
1243 return ret_val;
1244}
1245
1246
fddaa1af
BA		 1247/**
1248 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1249 * @hw: pointer to the HW structure
1250 **/
1251static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1252{
1253 s32 ret_val;
1254 u16 data;
1255
1256 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1257 if (ret_val)
1258 return ret_val;
1259
1260 data |= HV_KMRN_MDIO_SLOW;
1261
1262 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1263
1264 return ret_val;
1265}
1266
a4f58f54
BA		 1267/**
1268 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1269 * done after every PHY reset.
1270 **/
1271static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1272{
1273 s32 ret_val = 0;
baf86c9d 1274 u16 phy_data;
a4f58f54
BA		 1275
1276 if (hw->mac.type != e1000_pchlan)
1277 return ret_val;
1278
fddaa1af
BA		 1279 /* Set MDIO slow mode before any other MDIO access */
1280 if (hw->phy.type == e1000_phy_82577) {
1281 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1282 if (ret_val)
1283 goto out;
1284 }
1285
a4f58f54
BA		 1286 if (((hw->phy.type == e1000_phy_82577) &&
1287 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1288 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1289 /* Disable generation of early preamble */
1290 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1291 if (ret_val)
1292 return ret_val;
1293
1294 /* Preamble tuning for SSC */
1295 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1296 if (ret_val)
1297 return ret_val;
1298 }
1299
1300 if (hw->phy.type == e1000_phy_82578) {
1301 /*
1302 * Return registers to default by doing a soft reset then
1303 * writing 0x3140 to the control register.
1304 */
1305 if (hw->phy.revision < 2) {
1306 e1000e_phy_sw_reset(hw);
1307 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1308 }
1309 }
1310
1311 /* Select page 0 */
94d8186a 1312 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1313 if (ret_val)
1314 return ret_val;
1d5846b9 1315
a4f58f54 1316 hw->phy.addr = 1;
1d5846b9 1317 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1318 hw->phy.ops.release(hw);
1d5846b9
BA		 1319 if (ret_val)
1320 goto out;
a4f58f54 1321
1d5846b9
BA		 1322 /*
1323 * Configure the K1 Si workaround during phy reset assuming there is
1324 * link so that it disables K1 if link is in 1Gbps.
1325 */
1326 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1327 if (ret_val)
1328 goto out;
1d5846b9 1329
baf86c9d
BA		 1330 /* Workaround for link disconnects on a busy hub in half duplex */
1331 ret_val = hw->phy.ops.acquire(hw);
1332 if (ret_val)
1333 goto out;
1334 ret_val = hw->phy.ops.read_reg_locked(hw,
1335 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1336 &phy_data);
1337 if (ret_val)
1338 goto release;
1339 ret_val = hw->phy.ops.write_reg_locked(hw,
1340 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1341 phy_data & 0x00FF);
1342release:
1343 hw->phy.ops.release(hw);
1d5846b9 1344out:
a4f58f54
BA		 1345 return ret_val;
1346}
1347
d3738bb8
BA		 1348/**
1349 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1350 * @hw: pointer to the HW structure
1351 **/
1352void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1353{
1354 u32 mac_reg;
1355 u16 i;
1356
1357 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1358 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1359 mac_reg = er32(RAL(i));
1360 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1361 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1362 mac_reg = er32(RAH(i));
1363 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1364 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1365 }
1366}
1367
1368static u32 e1000_calc_rx_da_crc(u8 mac[])
1369{
1370 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1371 u32 i, j, mask, crc;
1372
1373 crc = 0xffffffff;
1374 for (i = 0; i < 6; i++) {
1375 crc = crc ^ mac[i];
1376 for (j = 8; j > 0; j--) {
1377 mask = (crc & 1) * (-1);
1378 crc = (crc >> 1) ^ (poly & mask);
1379 }
1380 }
1381 return ~crc;
1382}
1383
1384/**
1385 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1386 * with 82579 PHY
1387 * @hw: pointer to the HW structure
1388 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1389 **/
1390s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1391{
1392 s32 ret_val = 0;
1393 u16 phy_reg, data;
1394 u32 mac_reg;
1395 u16 i;
1396
1397 if (hw->mac.type != e1000_pch2lan)
1398 goto out;
1399
1400 /* disable Rx path while enabling/disabling workaround */
1401 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1402 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1403 if (ret_val)
1404 goto out;
1405
1406 if (enable) {
1407 /*
1408 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1409 * SHRAL/H) and initial CRC values to the MAC
1410 */
1411 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1412 u8 mac_addr[ETH_ALEN] = {0};
1413 u32 addr_high, addr_low;
1414
1415 addr_high = er32(RAH(i));
1416 if (!(addr_high & E1000_RAH_AV))
1417 continue;
1418 addr_low = er32(RAL(i));
1419 mac_addr[0] = (addr_low & 0xFF);
1420 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1421 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1422 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1423 mac_addr[4] = (addr_high & 0xFF);
1424 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1425
1426 ew32(PCH_RAICC(i),
1427 e1000_calc_rx_da_crc(mac_addr));
1428 }
1429
1430 /* Write Rx addresses to the PHY */
1431 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1432
1433 /* Enable jumbo frame workaround in the MAC */
1434 mac_reg = er32(FFLT_DBG);
1435 mac_reg &= ~(1 << 14);
1436 mac_reg |= (7 << 15);
1437 ew32(FFLT_DBG, mac_reg);
1438
1439 mac_reg = er32(RCTL);
1440 mac_reg |= E1000_RCTL_SECRC;
1441 ew32(RCTL, mac_reg);
1442
1443 ret_val = e1000e_read_kmrn_reg(hw,
1444 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1445 &data);
1446 if (ret_val)
1447 goto out;
1448 ret_val = e1000e_write_kmrn_reg(hw,
1449 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1450 data | (1 << 0));
1451 if (ret_val)
1452 goto out;
1453 ret_val = e1000e_read_kmrn_reg(hw,
1454 E1000_KMRNCTRLSTA_HD_CTRL,
1455 &data);
1456 if (ret_val)
1457 goto out;
1458 data &= ~(0xF << 8);
1459 data |= (0xB << 8);
1460 ret_val = e1000e_write_kmrn_reg(hw,
1461 E1000_KMRNCTRLSTA_HD_CTRL,
1462 data);
1463 if (ret_val)
1464 goto out;
1465
1466 /* Enable jumbo frame workaround in the PHY */
1467 e1e_rphy(hw, PHY_REG(769, 20), &data);
1468 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1469 if (ret_val)
1470 goto out;
1471 e1e_rphy(hw, PHY_REG(769, 23), &data);
1472 data &= ~(0x7F << 5);
1473 data |= (0x37 << 5);
1474 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1475 if (ret_val)
1476 goto out;
1477 e1e_rphy(hw, PHY_REG(769, 16), &data);
1478 data &= ~(1 << 13);
1479 data |= (1 << 12);
1480 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1481 if (ret_val)
1482 goto out;
1483 e1e_rphy(hw, PHY_REG(776, 20), &data);
1484 data &= ~(0x3FF << 2);
1485 data |= (0x1A << 2);
1486 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1487 if (ret_val)
1488 goto out;
1489 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1490 if (ret_val)
1491 goto out;
1492 e1e_rphy(hw, HV_PM_CTRL, &data);
1493 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1494 if (ret_val)
1495 goto out;
1496 } else {
1497 /* Write MAC register values back to h/w defaults */
1498 mac_reg = er32(FFLT_DBG);
1499 mac_reg &= ~(0xF << 14);
1500 ew32(FFLT_DBG, mac_reg);
1501
1502 mac_reg = er32(RCTL);
1503 mac_reg &= ~E1000_RCTL_SECRC;
1504 ew32(FFLT_DBG, mac_reg);
1505
1506 ret_val = e1000e_read_kmrn_reg(hw,
1507 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1508 &data);
1509 if (ret_val)
1510 goto out;
1511 ret_val = e1000e_write_kmrn_reg(hw,
1512 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1513 data & ~(1 << 0));
1514 if (ret_val)
1515 goto out;
1516 ret_val = e1000e_read_kmrn_reg(hw,
1517 E1000_KMRNCTRLSTA_HD_CTRL,
1518 &data);
1519 if (ret_val)
1520 goto out;
1521 data &= ~(0xF << 8);
1522 data |= (0xB << 8);
1523 ret_val = e1000e_write_kmrn_reg(hw,
1524 E1000_KMRNCTRLSTA_HD_CTRL,
1525 data);
1526 if (ret_val)
1527 goto out;
1528
1529 /* Write PHY register values back to h/w defaults */
1530 e1e_rphy(hw, PHY_REG(769, 20), &data);
1531 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1532 if (ret_val)
1533 goto out;
1534 e1e_rphy(hw, PHY_REG(769, 23), &data);
1535 data &= ~(0x7F << 5);
1536 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1537 if (ret_val)
1538 goto out;
1539 e1e_rphy(hw, PHY_REG(769, 16), &data);
1540 data &= ~(1 << 12);
1541 data |= (1 << 13);
1542 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1543 if (ret_val)
1544 goto out;
1545 e1e_rphy(hw, PHY_REG(776, 20), &data);
1546 data &= ~(0x3FF << 2);
1547 data |= (0x8 << 2);
1548 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1549 if (ret_val)
1550 goto out;
1551 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1552 if (ret_val)
1553 goto out;
1554 e1e_rphy(hw, HV_PM_CTRL, &data);
1555 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1556 if (ret_val)
1557 goto out;
1558 }
1559
1560 /* re-enable Rx path after enabling/disabling workaround */
1561 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1562
1563out:
1564 return ret_val;
1565}
1566
1567/**
1568 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1569 * done after every PHY reset.
1570 **/
1571static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1572{
1573 s32 ret_val = 0;
1574
1575 if (hw->mac.type != e1000_pch2lan)
1576 goto out;
1577
1578 /* Set MDIO slow mode before any other MDIO access */
1579 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1580
1581out:
1582 return ret_val;
1583}
1584
fc0c7760
BA		 1585/**
1586 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1587 * @hw: pointer to the HW structure
1588 *
1589 * Check the appropriate indication the MAC has finished configuring the
1590 * PHY after a software reset.
1591 **/
1592static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1593{
1594 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1595
1596 /* Wait for basic configuration completes before proceeding */
1597 do {
1598 data = er32(STATUS);
1599 data &= E1000_STATUS_LAN_INIT_DONE;
1600 udelay(100);
1601 } while ((!data) && --loop);
1602
1603 /*
1604 * If basic configuration is incomplete before the above loop
1605 * count reaches 0, loading the configuration from NVM will
1606 * leave the PHY in a bad state possibly resulting in no link.
1607 */
1608 if (loop == 0)
3bb99fe2 1609 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1610
1611 /* Clear the Init Done bit for the next init event */
1612 data = er32(STATUS);
1613 data &= ~E1000_STATUS_LAN_INIT_DONE;
1614 ew32(STATUS, data);
1615}
1616
bc7f75fa 1617/**
e98cac44 1618 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 1619 * @hw: pointer to the HW structure
bc7f75fa 1620 **/
e98cac44 1621static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 1622{
f523d211
BA		 1623 s32 ret_val = 0;
1624 u16 reg;
bc7f75fa 1625
e98cac44
BA		 1626 if (e1000_check_reset_block(hw))
1627 goto out;
fc0c7760 1628
fddaa1af 1629 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 1630 switch (hw->mac.type) {
1631 case e1000_pchlan:
a4f58f54
BA		 1632 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1633 if (ret_val)
e98cac44
BA		 1634 goto out;
1635 break;
d3738bb8
BA		 1636 case e1000_pch2lan:
1637 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1638 if (ret_val)
1639 goto out;
1640 break;
e98cac44
BA		 1641 default:
1642 break;
a4f58f54
BA		 1643 }
1644
db2932ec 1645 /* Dummy read to clear the phy wakeup bit after lcd reset */
d3738bb8 1646 if (hw->mac.type >= e1000_pchlan)
db2932ec
BA		 1647 e1e_rphy(hw, BM_WUC, &reg);
1648
f523d211
BA		 1649 /* Configure the LCD with the extended configuration region in NVM */
1650 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1651 if (ret_val)
1652 goto out;
bc7f75fa 1653
f523d211 1654 /* Configure the LCD with the OEM bits in NVM */
e98cac44 1655 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1656
f523d211 1657out:
e98cac44
BA		 1658 return ret_val;
1659}
1660
1661/**
1662 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1663 * @hw: pointer to the HW structure
1664 *
1665 * Resets the PHY
1666 * This is a function pointer entry point called by drivers
1667 * or other shared routines.
1668 **/
1669static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1670{
1671 s32 ret_val = 0;
1672
1673 ret_val = e1000e_phy_hw_reset_generic(hw);
1674 if (ret_val)
1675 goto out;
1676
1677 ret_val = e1000_post_phy_reset_ich8lan(hw);
1678
1679out:
1680 return ret_val;
bc7f75fa
AK		 1681}
1682
fa2ce13c
BA		 1683/**
1684 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1685 * @hw: pointer to the HW structure
1686 * @active: true to enable LPLU, false to disable
1687 *
1688 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1689 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1690 * the phy speed. This function will manually set the LPLU bit and restart
1691 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1692 * since it configures the same bit.
1693 **/
1694static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1695{
1696 s32 ret_val = 0;
1697 u16 oem_reg;
1698
1699 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1700 if (ret_val)
1701 goto out;
1702
1703 if (active)
1704 oem_reg |= HV_OEM_BITS_LPLU;
1705 else
1706 oem_reg &= ~HV_OEM_BITS_LPLU;
1707
1708 oem_reg |= HV_OEM_BITS_RESTART_AN;
1709 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1710
1711out:
1712 return ret_val;
1713}
1714
bc7f75fa
AK		 1715/**
1716 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1717 * @hw: pointer to the HW structure
564ea9bb 1718 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1719 *
1720 * Sets the LPLU D0 state according to the active flag. When
1721 * activating LPLU this function also disables smart speed
1722 * and vice versa. LPLU will not be activated unless the
1723 * device autonegotiation advertisement meets standards of
1724 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1725 * This is a function pointer entry point only called by
1726 * PHY setup routines.
1727 **/
1728static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1729{
1730 struct e1000_phy_info *phy = &hw->phy;
1731 u32 phy_ctrl;
1732 s32 ret_val = 0;
1733 u16 data;
1734
97ac8cae 1735 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1736 return ret_val;
1737
1738 phy_ctrl = er32(PHY_CTRL);
1739
1740 if (active) {
1741 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1742 ew32(PHY_CTRL, phy_ctrl);
1743
60f1292f
BA		 1744 if (phy->type != e1000_phy_igp_3)
1745 return 0;
1746
ad68076e
BA		 1747 /*
1748 * Call gig speed drop workaround on LPLU before accessing
1749 * any PHY registers
1750 */
60f1292f 1751 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1752 e1000e_gig_downshift_workaround_ich8lan(hw);
1753
1754 /* When LPLU is enabled, we should disable SmartSpeed */
1755 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1756 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1757 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1758 if (ret_val)
1759 return ret_val;
1760 } else {
1761 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1762 ew32(PHY_CTRL, phy_ctrl);
1763
60f1292f
BA		 1764 if (phy->type != e1000_phy_igp_3)
1765 return 0;
1766
ad68076e
BA		 1767 /*
1768 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1769 * during Dx states where the power conservation is most
1770 * important. During driver activity we should enable
ad68076e
BA		 1771 * SmartSpeed, so performance is maintained.
1772 */
bc7f75fa
AK		 1773 if (phy->smart_speed == e1000_smart_speed_on) {
1774 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1775 &data);
bc7f75fa
AK		 1776 if (ret_val)
1777 return ret_val;
1778
1779 data |= IGP01E1000_PSCFR_SMART_SPEED;
1780 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1781 data);
bc7f75fa
AK		 1782 if (ret_val)
1783 return ret_val;
1784 } else if (phy->smart_speed == e1000_smart_speed_off) {
1785 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1786 &data);
bc7f75fa
AK		 1787 if (ret_val)
1788 return ret_val;
1789
1790 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1791 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1792 data);
bc7f75fa
AK		 1793 if (ret_val)
1794 return ret_val;
1795 }
1796 }
1797
1798 return 0;
1799}
1800
1801/**
1802 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1803 * @hw: pointer to the HW structure
564ea9bb 1804 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1805 *
1806 * Sets the LPLU D3 state according to the active flag. When
1807 * activating LPLU this function also disables smart speed
1808 * and vice versa. LPLU will not be activated unless the
1809 * device autonegotiation advertisement meets standards of
1810 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1811 * This is a function pointer entry point only called by
1812 * PHY setup routines.
1813 **/
1814static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1815{
1816 struct e1000_phy_info *phy = &hw->phy;
1817 u32 phy_ctrl;
1818 s32 ret_val;
1819 u16 data;
1820
1821 phy_ctrl = er32(PHY_CTRL);
1822
1823 if (!active) {
1824 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1825 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1826
1827 if (phy->type != e1000_phy_igp_3)
1828 return 0;
1829
ad68076e
BA		 1830 /*
1831 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1832 * during Dx states where the power conservation is most
1833 * important. During driver activity we should enable
ad68076e
BA		 1834 * SmartSpeed, so performance is maintained.
1835 */
bc7f75fa 1836 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1837 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1838 &data);
bc7f75fa
AK		 1839 if (ret_val)
1840 return ret_val;
1841
1842 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1843 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1844 data);
bc7f75fa
AK		 1845 if (ret_val)
1846 return ret_val;
1847 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1848 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1849 &data);
bc7f75fa
AK		 1850 if (ret_val)
1851 return ret_val;
1852
1853 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1854 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1855 data);
bc7f75fa
AK		 1856 if (ret_val)
1857 return ret_val;
1858 }
1859 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1860 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1861 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1862 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1863 ew32(PHY_CTRL, phy_ctrl);
1864
60f1292f
BA		 1865 if (phy->type != e1000_phy_igp_3)
1866 return 0;
1867
ad68076e
BA		 1868 /*
1869 * Call gig speed drop workaround on LPLU before accessing
1870 * any PHY registers
1871 */
60f1292f 1872 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1873 e1000e_gig_downshift_workaround_ich8lan(hw);
1874
1875 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1876 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1877 if (ret_val)
1878 return ret_val;
1879
1880 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1881 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1882 }
1883
1884 return 0;
1885}
1886
f4187b56
BA		 1887/**
1888 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1889 * @hw: pointer to the HW structure
1890 * @bank: pointer to the variable that returns the active bank
1891 *
1892 * Reads signature byte from the NVM using the flash access registers.
e243455d 1893 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1894 **/
1895static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1896{
e243455d 1897 u32 eecd;
f4187b56 1898 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1899 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1900 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1901 u8 sig_byte = 0;
1902 s32 ret_val = 0;
f4187b56 1903
e243455d
BA		 1904 switch (hw->mac.type) {
1905 case e1000_ich8lan:
1906 case e1000_ich9lan:
1907 eecd = er32(EECD);
1908 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1909 E1000_EECD_SEC1VAL_VALID_MASK) {
1910 if (eecd & E1000_EECD_SEC1VAL)
1911 *bank = 1;
1912 else
1913 *bank = 0;
1914
1915 return 0;
1916 }
3bb99fe2 1917 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 1918 "reading flash signature\n");
1919 /* fall-thru */
1920 default:
1921 /* set bank to 0 in case flash read fails */
1922 *bank = 0;
1923
1924 /* Check bank 0 */
1925 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1926 &sig_byte);
1927 if (ret_val)
1928 return ret_val;
1929 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1930 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 1931 *bank = 0;
e243455d
BA		 1932 return 0;
1933 }
f4187b56 1934
e243455d
BA		 1935 /* Check bank 1 */
1936 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1937 bank1_offset,
1938 &sig_byte);
1939 if (ret_val)
1940 return ret_val;
1941 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1942 E1000_ICH_NVM_SIG_VALUE) {
1943 *bank = 1;
1944 return 0;
f4187b56 1945 }
e243455d 1946
3bb99fe2 1947 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 1948 return -E1000_ERR_NVM;
f4187b56
BA		 1949 }
1950
1951 return 0;
1952}
1953
bc7f75fa
AK		 1954/**
1955 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1956 * @hw: pointer to the HW structure
1957 * @offset: The offset (in bytes) of the word(s) to read.
1958 * @words: Size of data to read in words
1959 * @data: Pointer to the word(s) to read at offset.
1960 *
1961 * Reads a word(s) from the NVM using the flash access registers.
1962 **/
1963static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1964 u16 *data)
1965{
1966 struct e1000_nvm_info *nvm = &hw->nvm;
1967 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1968 u32 act_offset;
148675a7 1969 s32 ret_val = 0;
f4187b56 1970 u32 bank = 0;
bc7f75fa
AK		 1971 u16 i, word;
1972
1973 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1974 (words == 0)) {
3bb99fe2 1975 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 1976 ret_val = -E1000_ERR_NVM;
1977 goto out;
bc7f75fa
AK		 1978 }
1979
94d8186a 1980 nvm->ops.acquire(hw);
bc7f75fa 1981
f4187b56 1982 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 1983 if (ret_val) {
3bb99fe2 1984 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 1985 bank = 0;
1986 }
f4187b56
BA		 1987
1988 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 1989 act_offset += offset;
1990
148675a7 1991 ret_val = 0;
bc7f75fa
AK		 1992 for (i = 0; i < words; i++) {
1993 if ((dev_spec->shadow_ram) &&
1994 (dev_spec->shadow_ram[offset+i].modified)) {
1995 data[i] = dev_spec->shadow_ram[offset+i].value;
1996 } else {
1997 ret_val = e1000_read_flash_word_ich8lan(hw,
1998 act_offset + i,
1999 &word);
2000 if (ret_val)
2001 break;
2002 data[i] = word;
2003 }
2004 }
2005
94d8186a 2006 nvm->ops.release(hw);
bc7f75fa 2007
e243455d
BA		 2008out:
2009 if (ret_val)
3bb99fe2 2010 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2011
bc7f75fa
AK		 2012 return ret_val;
2013}
2014
2015/**
2016 * e1000_flash_cycle_init_ich8lan - Initialize flash
2017 * @hw: pointer to the HW structure
2018 *
2019 * This function does initial flash setup so that a new read/write/erase cycle
2020 * can be started.
2021 **/
2022static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2023{
2024 union ich8_hws_flash_status hsfsts;
2025 s32 ret_val = -E1000_ERR_NVM;
2026 s32 i = 0;
2027
2028 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2029
2030 /* Check if the flash descriptor is valid */
2031 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 2032 e_dbg("Flash descriptor invalid. "
2c73e1fe 2033 "SW Sequencing must be used.\n");
bc7f75fa
AK		 2034 return -E1000_ERR_NVM;
2035 }
2036
2037 /* Clear FCERR and DAEL in hw status by writing 1 */
2038 hsfsts.hsf_status.flcerr = 1;
2039 hsfsts.hsf_status.dael = 1;
2040
2041 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2042
ad68076e
BA		 2043 /*
2044 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2045 * bit to check against, in order to start a new cycle or
2046 * FDONE bit should be changed in the hardware so that it
489815ce 2047 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2048 * indication whether a cycle is in progress or has been
2049 * completed.
2050 */
2051
2052 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 2053 /*
2054 * There is no cycle running at present,
5ff5b664 2055 * so we can start a cycle.
ad68076e
BA		 2056 * Begin by setting Flash Cycle Done.
2057 */
bc7f75fa
AK		 2058 hsfsts.hsf_status.flcdone = 1;
2059 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2060 ret_val = 0;
2061 } else {
ad68076e 2062 /*
5ff5b664 2063 * Otherwise poll for sometime so the current
ad68076e
BA		 2064 * cycle has a chance to end before giving up.
2065 */
bc7f75fa
AK		 2066 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2067 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2068 if (hsfsts.hsf_status.flcinprog == 0) {
2069 ret_val = 0;
2070 break;
2071 }
2072 udelay(1);
2073 }
2074 if (ret_val == 0) {
ad68076e
BA		 2075 /*
2076 * Successful in waiting for previous cycle to timeout,
2077 * now set the Flash Cycle Done.
2078 */
bc7f75fa
AK		 2079 hsfsts.hsf_status.flcdone = 1;
2080 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2081 } else {
2c73e1fe 2082 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2083 }
2084 }
2085
2086 return ret_val;
2087}
2088
2089/**
2090 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2091 * @hw: pointer to the HW structure
2092 * @timeout: maximum time to wait for completion
2093 *
2094 * This function starts a flash cycle and waits for its completion.
2095 **/
2096static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2097{
2098 union ich8_hws_flash_ctrl hsflctl;
2099 union ich8_hws_flash_status hsfsts;
2100 s32 ret_val = -E1000_ERR_NVM;
2101 u32 i = 0;
2102
2103 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2104 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2105 hsflctl.hsf_ctrl.flcgo = 1;
2106 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2107
2108 /* wait till FDONE bit is set to 1 */
2109 do {
2110 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2111 if (hsfsts.hsf_status.flcdone == 1)
2112 break;
2113 udelay(1);
2114 } while (i++ < timeout);
2115
2116 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2117 return 0;
2118
2119 return ret_val;
2120}
2121
2122/**
2123 * e1000_read_flash_word_ich8lan - Read word from flash
2124 * @hw: pointer to the HW structure
2125 * @offset: offset to data location
2126 * @data: pointer to the location for storing the data
2127 *
2128 * Reads the flash word at offset into data. Offset is converted
2129 * to bytes before read.
2130 **/
2131static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2132 u16 *data)
2133{
2134 /* Must convert offset into bytes. */
2135 offset <<= 1;
2136
2137 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2138}
2139
f4187b56
BA		 2140/**
2141 * e1000_read_flash_byte_ich8lan - Read byte from flash
2142 * @hw: pointer to the HW structure
2143 * @offset: The offset of the byte to read.
2144 * @data: Pointer to a byte to store the value read.
2145 *
2146 * Reads a single byte from the NVM using the flash access registers.
2147 **/
2148static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2149 u8 *data)
2150{
2151 s32 ret_val;
2152 u16 word = 0;
2153
2154 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2155 if (ret_val)
2156 return ret_val;
2157
2158 *data = (u8)word;
2159
2160 return 0;
2161}
2162
bc7f75fa
AK		 2163/**
2164 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2165 * @hw: pointer to the HW structure
2166 * @offset: The offset (in bytes) of the byte or word to read.
2167 * @size: Size of data to read, 1=byte 2=word
2168 * @data: Pointer to the word to store the value read.
2169 *
2170 * Reads a byte or word from the NVM using the flash access registers.
2171 **/
2172static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2173 u8 size, u16 *data)
2174{
2175 union ich8_hws_flash_status hsfsts;
2176 union ich8_hws_flash_ctrl hsflctl;
2177 u32 flash_linear_addr;
2178 u32 flash_data = 0;
2179 s32 ret_val = -E1000_ERR_NVM;
2180 u8 count = 0;
2181
2182 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2183 return -E1000_ERR_NVM;
2184
2185 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2186 hw->nvm.flash_base_addr;
2187
2188 do {
2189 udelay(1);
2190 /* Steps */
2191 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2192 if (ret_val != 0)
2193 break;
2194
2195 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2196 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2197 hsflctl.hsf_ctrl.fldbcount = size - 1;
2198 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2199 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2200
2201 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2202
2203 ret_val = e1000_flash_cycle_ich8lan(hw,
2204 ICH_FLASH_READ_COMMAND_TIMEOUT);
2205
ad68076e
BA		 2206 /*
2207 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2208 * and try the whole sequence a few more times, else
2209 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2210 * least significant byte first msb to lsb
2211 */
bc7f75fa
AK		 2212 if (ret_val == 0) {
2213 flash_data = er32flash(ICH_FLASH_FDATA0);
2214 if (size == 1) {
2215 *data = (u8)(flash_data & 0x000000FF);
2216 } else if (size == 2) {
2217 *data = (u16)(flash_data & 0x0000FFFF);
2218 }
2219 break;
2220 } else {
ad68076e
BA		 2221 /*
2222 * If we've gotten here, then things are probably
bc7f75fa
AK		 2223 * completely hosed, but if the error condition is
2224 * detected, it won't hurt to give it another try...
2225 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2226 */
2227 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2228 if (hsfsts.hsf_status.flcerr == 1) {
2229 /* Repeat for some time before giving up. */
2230 continue;
2231 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2232 e_dbg("Timeout error - flash cycle "
2c73e1fe 2233 "did not complete.\n");
bc7f75fa
AK		 2234 break;
2235 }
2236 }
2237 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2238
2239 return ret_val;
2240}
2241
2242/**
2243 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2244 * @hw: pointer to the HW structure
2245 * @offset: The offset (in bytes) of the word(s) to write.
2246 * @words: Size of data to write in words
2247 * @data: Pointer to the word(s) to write at offset.
2248 *
2249 * Writes a byte or word to the NVM using the flash access registers.
2250 **/
2251static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2252 u16 *data)
2253{
2254 struct e1000_nvm_info *nvm = &hw->nvm;
2255 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2256 u16 i;
2257
2258 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2259 (words == 0)) {
3bb99fe2 2260 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2261 return -E1000_ERR_NVM;
2262 }
2263
94d8186a 2264 nvm->ops.acquire(hw);
ca15df58 2265
bc7f75fa 2266 for (i = 0; i < words; i++) {
564ea9bb 2267 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 2268 dev_spec->shadow_ram[offset+i].value = data[i];
2269 }
2270
94d8186a 2271 nvm->ops.release(hw);
ca15df58 2272
bc7f75fa
AK		 2273 return 0;
2274}
2275
2276/**
2277 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2278 * @hw: pointer to the HW structure
2279 *
2280 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2281 * which writes the checksum to the shadow ram. The changes in the shadow
2282 * ram are then committed to the EEPROM by processing each bank at a time
2283 * checking for the modified bit and writing only the pending changes.
489815ce 2284 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2285 * future writes.
2286 **/
2287static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2288{
2289 struct e1000_nvm_info *nvm = &hw->nvm;
2290 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2291 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2292 s32 ret_val;
2293 u16 data;
2294
2295 ret_val = e1000e_update_nvm_checksum_generic(hw);
2296 if (ret_val)
e243455d 2297 goto out;
bc7f75fa
AK		 2298
2299 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2300 goto out;
bc7f75fa 2301
94d8186a 2302 nvm->ops.acquire(hw);
bc7f75fa 2303
ad68076e
BA		 2304 /*
2305 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2306 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2307 * is going to be written
2308 */
f4187b56 2309 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 2310 if (ret_val) {
3bb99fe2 2311 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2312 bank = 0;
e243455d 2313 }
f4187b56
BA		 2314
2315 if (bank == 0) {
bc7f75fa
AK		 2316 new_bank_offset = nvm->flash_bank_size;
2317 old_bank_offset = 0;
e243455d 2318 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 2319 if (ret_val)
2320 goto release;
bc7f75fa
AK		 2321 } else {
2322 old_bank_offset = nvm->flash_bank_size;
2323 new_bank_offset = 0;
e243455d 2324 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 2325 if (ret_val)
2326 goto release;
bc7f75fa
AK		 2327 }
2328
2329 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 2330 /*
2331 * Determine whether to write the value stored
bc7f75fa 2332 * in the other NVM bank or a modified value stored
ad68076e
BA		 2333 * in the shadow RAM
2334 */
bc7f75fa
AK		 2335 if (dev_spec->shadow_ram[i].modified) {
2336 data = dev_spec->shadow_ram[i].value;
2337 } else {
e243455d
BA		 2338 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2339 old_bank_offset,
2340 &data);
2341 if (ret_val)
2342 break;
bc7f75fa
AK		 2343 }
2344
ad68076e
BA		 2345 /*
2346 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2347 * (15:14) are 11b until the commit has completed.
2348 * This will allow us to write 10b which indicates the
2349 * signature is valid. We want to do this after the write
2350 * has completed so that we don't mark the segment valid
ad68076e
BA		 2351 * while the write is still in progress
2352 */
bc7f75fa
AK		 2353 if (i == E1000_ICH_NVM_SIG_WORD)
2354 data |= E1000_ICH_NVM_SIG_MASK;
2355
2356 /* Convert offset to bytes. */
2357 act_offset = (i + new_bank_offset) << 1;
2358
2359 udelay(100);
2360 /* Write the bytes to the new bank. */
2361 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2362 act_offset,
2363 (u8)data);
2364 if (ret_val)
2365 break;
2366
2367 udelay(100);
2368 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2369 act_offset + 1,
2370 (u8)(data >> 8));
2371 if (ret_val)
2372 break;
2373 }
2374
ad68076e
BA		 2375 /*
2376 * Don't bother writing the segment valid bits if sector
2377 * programming failed.
2378 */
bc7f75fa 2379 if (ret_val) {
4a770358 2380 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2381 e_dbg("Flash commit failed.\n");
9c5e209d 2382 goto release;
bc7f75fa
AK		 2383 }
2384
ad68076e
BA		 2385 /*
2386 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2387 * to 10b in word 0x13 , this can be done without an
2388 * erase as well since these bits are 11 to start with
ad68076e
BA		 2389 * and we need to change bit 14 to 0b
2390 */
bc7f75fa 2391 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2392 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2393 if (ret_val)
2394 goto release;
2395
bc7f75fa
AK		 2396 data &= 0xBFFF;
2397 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2398 act_offset * 2 + 1,
2399 (u8)(data >> 8));
9c5e209d
BA		 2400 if (ret_val)
2401 goto release;
bc7f75fa 2402
ad68076e
BA		 2403 /*
2404 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2405 * its signature word (0x13) high_byte to 0b. This can be
2406 * done without an erase because flash erase sets all bits
ad68076e
BA		 2407 * to 1's. We can write 1's to 0's without an erase
2408 */
bc7f75fa
AK		 2409 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2410 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2411 if (ret_val)
2412 goto release;
bc7f75fa
AK		 2413
2414 /* Great! Everything worked, we can now clear the cached entries. */
2415 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2416 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2417 dev_spec->shadow_ram[i].value = 0xFFFF;
2418 }
2419
9c5e209d 2420release:
94d8186a 2421 nvm->ops.release(hw);
bc7f75fa 2422
ad68076e
BA		 2423 /*
2424 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2425 * until after the next adapter reset.
2426 */
9c5e209d
BA		 2427 if (!ret_val) {
2428 e1000e_reload_nvm(hw);
2429 msleep(10);
2430 }
bc7f75fa 2431
e243455d
BA		 2432out:
2433 if (ret_val)
3bb99fe2 2434 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2435
bc7f75fa
AK		 2436 return ret_val;
2437}
2438
2439/**
2440 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2441 * @hw: pointer to the HW structure
2442 *
2443 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2444 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2445 * calculated, in which case we need to calculate the checksum and set bit 6.
2446 **/
2447static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2448{
2449 s32 ret_val;
2450 u16 data;
2451
ad68076e
BA		 2452 /*
2453 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2454 * needs to be fixed. This bit is an indication that the NVM
2455 * was prepared by OEM software and did not calculate the
2456 * checksum...a likely scenario.
2457 */
2458 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2459 if (ret_val)
2460 return ret_val;
2461
2462 if ((data & 0x40) == 0) {
2463 data |= 0x40;
2464 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2465 if (ret_val)
2466 return ret_val;
2467 ret_val = e1000e_update_nvm_checksum(hw);
2468 if (ret_val)
2469 return ret_val;
2470 }
2471
2472 return e1000e_validate_nvm_checksum_generic(hw);
2473}
2474
4a770358
BA		 2475/**
2476 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2477 * @hw: pointer to the HW structure
2478 *
2479 * To prevent malicious write/erase of the NVM, set it to be read-only
2480 * so that the hardware ignores all write/erase cycles of the NVM via
2481 * the flash control registers. The shadow-ram copy of the NVM will
2482 * still be updated, however any updates to this copy will not stick
2483 * across driver reloads.
2484 **/
2485void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2486{
ca15df58 2487 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2488 union ich8_flash_protected_range pr0;
2489 union ich8_hws_flash_status hsfsts;
2490 u32 gfpreg;
4a770358 2491
94d8186a 2492 nvm->ops.acquire(hw);
4a770358
BA		 2493
2494 gfpreg = er32flash(ICH_FLASH_GFPREG);
2495
2496 /* Write-protect GbE Sector of NVM */
2497 pr0.regval = er32flash(ICH_FLASH_PR0);
2498 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2499 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2500 pr0.range.wpe = true;
2501 ew32flash(ICH_FLASH_PR0, pr0.regval);
2502
2503 /*
2504 * Lock down a subset of GbE Flash Control Registers, e.g.
2505 * PR0 to prevent the write-protection from being lifted.
2506 * Once FLOCKDN is set, the registers protected by it cannot
2507 * be written until FLOCKDN is cleared by a hardware reset.
2508 */
2509 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2510 hsfsts.hsf_status.flockdn = true;
2511 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2512
94d8186a 2513 nvm->ops.release(hw);
4a770358
BA		 2514}
2515
bc7f75fa
AK		 2516/**
2517 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2518 * @hw: pointer to the HW structure
2519 * @offset: The offset (in bytes) of the byte/word to read.
2520 * @size: Size of data to read, 1=byte 2=word
2521 * @data: The byte(s) to write to the NVM.
2522 *
2523 * Writes one/two bytes to the NVM using the flash access registers.
2524 **/
2525static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2526 u8 size, u16 data)
2527{
2528 union ich8_hws_flash_status hsfsts;
2529 union ich8_hws_flash_ctrl hsflctl;
2530 u32 flash_linear_addr;
2531 u32 flash_data = 0;
2532 s32 ret_val;
2533 u8 count = 0;
2534
2535 if (size < 1 || size > 2 || data > size * 0xff ||
2536 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2537 return -E1000_ERR_NVM;
2538
2539 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2540 hw->nvm.flash_base_addr;
2541
2542 do {
2543 udelay(1);
2544 /* Steps */
2545 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2546 if (ret_val)
2547 break;
2548
2549 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2550 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2551 hsflctl.hsf_ctrl.fldbcount = size -1;
2552 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2553 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2554
2555 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2556
2557 if (size == 1)
2558 flash_data = (u32)data & 0x00FF;
2559 else
2560 flash_data = (u32)data;
2561
2562 ew32flash(ICH_FLASH_FDATA0, flash_data);
2563
ad68076e
BA		 2564 /*
2565 * check if FCERR is set to 1 , if set to 1, clear it
2566 * and try the whole sequence a few more times else done
2567 */
bc7f75fa
AK		 2568 ret_val = e1000_flash_cycle_ich8lan(hw,
2569 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2570 if (!ret_val)
2571 break;
2572
ad68076e
BA		 2573 /*
2574 * If we're here, then things are most likely
bc7f75fa
AK		 2575 * completely hosed, but if the error condition
2576 * is detected, it won't hurt to give it another
2577 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2578 */
2579 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2580 if (hsfsts.hsf_status.flcerr == 1)
2581 /* Repeat for some time before giving up. */
2582 continue;
2583 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2584 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2585 "did not complete.");
2586 break;
2587 }
2588 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2589
2590 return ret_val;
2591}
2592
2593/**
2594 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2595 * @hw: pointer to the HW structure
2596 * @offset: The index of the byte to read.
2597 * @data: The byte to write to the NVM.
2598 *
2599 * Writes a single byte to the NVM using the flash access registers.
2600 **/
2601static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2602 u8 data)
2603{
2604 u16 word = (u16)data;
2605
2606 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2607}
2608
2609/**
2610 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2611 * @hw: pointer to the HW structure
2612 * @offset: The offset of the byte to write.
2613 * @byte: The byte to write to the NVM.
2614 *
2615 * Writes a single byte to the NVM using the flash access registers.
2616 * Goes through a retry algorithm before giving up.
2617 **/
2618static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2619 u32 offset, u8 byte)
2620{
2621 s32 ret_val;
2622 u16 program_retries;
2623
2624 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2625 if (!ret_val)
2626 return ret_val;
2627
2628 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2629 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2630 udelay(100);
2631 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2632 if (!ret_val)
2633 break;
2634 }
2635 if (program_retries == 100)
2636 return -E1000_ERR_NVM;
2637
2638 return 0;
2639}
2640
2641/**
2642 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2643 * @hw: pointer to the HW structure
2644 * @bank: 0 for first bank, 1 for second bank, etc.
2645 *
2646 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2647 * bank N is 4096 * N + flash_reg_addr.
2648 **/
2649static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2650{
2651 struct e1000_nvm_info *nvm = &hw->nvm;
2652 union ich8_hws_flash_status hsfsts;
2653 union ich8_hws_flash_ctrl hsflctl;
2654 u32 flash_linear_addr;
2655 /* bank size is in 16bit words - adjust to bytes */
2656 u32 flash_bank_size = nvm->flash_bank_size * 2;
2657 s32 ret_val;
2658 s32 count = 0;
a708dd88 2659 s32 j, iteration, sector_size;
bc7f75fa
AK		 2660
2661 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2662
ad68076e
BA		 2663 /*
2664 * Determine HW Sector size: Read BERASE bits of hw flash status
2665 * register
2666 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2667 * consecutive sectors. The start index for the nth Hw sector
2668 * can be calculated as = bank * 4096 + n * 256
2669 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2670 * The start index for the nth Hw sector can be calculated
2671 * as = bank * 4096
2672 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2673 * (ich9 only, otherwise error condition)
2674 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2675 */
2676 switch (hsfsts.hsf_status.berasesz) {
2677 case 0:
2678 /* Hw sector size 256 */
2679 sector_size = ICH_FLASH_SEG_SIZE_256;
2680 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2681 break;
2682 case 1:
2683 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2684 iteration = 1;
bc7f75fa
AK		 2685 break;
2686 case 2:
148675a7
BA		 2687 sector_size = ICH_FLASH_SEG_SIZE_8K;
2688 iteration = 1;
bc7f75fa
AK		 2689 break;
2690 case 3:
2691 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2692 iteration = 1;
bc7f75fa
AK		 2693 break;
2694 default:
2695 return -E1000_ERR_NVM;
2696 }
2697
2698 /* Start with the base address, then add the sector offset. */
2699 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2700 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2701
2702 for (j = 0; j < iteration ; j++) {
2703 do {
2704 /* Steps */
2705 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2706 if (ret_val)
2707 return ret_val;
2708
ad68076e
BA		 2709 /*
2710 * Write a value 11 (block Erase) in Flash
2711 * Cycle field in hw flash control
2712 */
bc7f75fa
AK		 2713 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2714 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2715 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2716
ad68076e
BA		 2717 /*
2718 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2719 * block into Flash Linear address field in Flash
2720 * Address.
2721 */
2722 flash_linear_addr += (j * sector_size);
2723 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2724
2725 ret_val = e1000_flash_cycle_ich8lan(hw,
2726 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2727 if (ret_val == 0)
2728 break;
2729
ad68076e
BA		 2730 /*
2731 * Check if FCERR is set to 1. If 1,
bc7f75fa 2732 * clear it and try the whole sequence
ad68076e
BA		 2733 * a few more times else Done
2734 */
bc7f75fa
AK		 2735 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2736 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2737 /* repeat for some time before giving up */
bc7f75fa
AK		 2738 continue;
2739 else if (hsfsts.hsf_status.flcdone == 0)
2740 return ret_val;
2741 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2742 }
2743
2744 return 0;
2745}
2746
2747/**
2748 * e1000_valid_led_default_ich8lan - Set the default LED settings
2749 * @hw: pointer to the HW structure
2750 * @data: Pointer to the LED settings
2751 *
2752 * Reads the LED default settings from the NVM to data. If the NVM LED
2753 * settings is all 0's or F's, set the LED default to a valid LED default
2754 * setting.
2755 **/
2756static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2757{
2758 s32 ret_val;
2759
2760 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2761 if (ret_val) {
3bb99fe2 2762 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2763 return ret_val;
2764 }
2765
2766 if (*data == ID_LED_RESERVED_0000 ||
2767 *data == ID_LED_RESERVED_FFFF)
2768 *data = ID_LED_DEFAULT_ICH8LAN;
2769
2770 return 0;
2771}
2772
a4f58f54
BA		 2773/**
2774 * e1000_id_led_init_pchlan - store LED configurations
2775 * @hw: pointer to the HW structure
2776 *
2777 * PCH does not control LEDs via the LEDCTL register, rather it uses
2778 * the PHY LED configuration register.
2779 *
2780 * PCH also does not have an "always on" or "always off" mode which
2781 * complicates the ID feature. Instead of using the "on" mode to indicate
2782 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2783 * use "link_up" mode. The LEDs will still ID on request if there is no
2784 * link based on logic in e1000_led_[on|off]_pchlan().
2785 **/
2786static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2787{
2788 struct e1000_mac_info *mac = &hw->mac;
2789 s32 ret_val;
2790 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2791 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2792 u16 data, i, temp, shift;
2793
2794 /* Get default ID LED modes */
2795 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2796 if (ret_val)
2797 goto out;
2798
2799 mac->ledctl_default = er32(LEDCTL);
2800 mac->ledctl_mode1 = mac->ledctl_default;
2801 mac->ledctl_mode2 = mac->ledctl_default;
2802
2803 for (i = 0; i < 4; i++) {
2804 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2805 shift = (i * 5);
2806 switch (temp) {
2807 case ID_LED_ON1_DEF2:
2808 case ID_LED_ON1_ON2:
2809 case ID_LED_ON1_OFF2:
2810 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2811 mac->ledctl_mode1 |= (ledctl_on << shift);
2812 break;
2813 case ID_LED_OFF1_DEF2:
2814 case ID_LED_OFF1_ON2:
2815 case ID_LED_OFF1_OFF2:
2816 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2817 mac->ledctl_mode1 |= (ledctl_off << shift);
2818 break;
2819 default:
2820 /* Do nothing */
2821 break;
2822 }
2823 switch (temp) {
2824 case ID_LED_DEF1_ON2:
2825 case ID_LED_ON1_ON2:
2826 case ID_LED_OFF1_ON2:
2827 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2828 mac->ledctl_mode2 |= (ledctl_on << shift);
2829 break;
2830 case ID_LED_DEF1_OFF2:
2831 case ID_LED_ON1_OFF2:
2832 case ID_LED_OFF1_OFF2:
2833 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2834 mac->ledctl_mode2 |= (ledctl_off << shift);
2835 break;
2836 default:
2837 /* Do nothing */
2838 break;
2839 }
2840 }
2841
2842out:
2843 return ret_val;
2844}
2845
bc7f75fa
AK		 2846/**
2847 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2848 * @hw: pointer to the HW structure
2849 *
2850 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2851 * register, so the the bus width is hard coded.
2852 **/
2853static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2854{
2855 struct e1000_bus_info *bus = &hw->bus;
2856 s32 ret_val;
2857
2858 ret_val = e1000e_get_bus_info_pcie(hw);
2859
ad68076e
BA		 2860 /*
2861 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2862 * a configuration space, but do not contain
2863 * PCI Express Capability registers, so bus width
2864 * must be hardcoded.
2865 */
2866 if (bus->width == e1000_bus_width_unknown)
2867 bus->width = e1000_bus_width_pcie_x1;
2868
2869 return ret_val;
2870}
2871
2872/**
2873 * e1000_reset_hw_ich8lan - Reset the hardware
2874 * @hw: pointer to the HW structure
2875 *
2876 * Does a full reset of the hardware which includes a reset of the PHY and
2877 * MAC.
2878 **/
2879static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2880{
1d5846b9 2881 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2882 u16 reg;
bc7f75fa
AK		 2883 u32 ctrl, icr, kab;
2884 s32 ret_val;
2885
ad68076e
BA		 2886 /*
2887 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2888 * on the last TLP read/write transaction when MAC is reset.
2889 */
2890 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 2891 if (ret_val)
3bb99fe2 2892 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 2893
3bb99fe2 2894 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2895 ew32(IMC, 0xffffffff);
2896
ad68076e
BA		 2897 /*
2898 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2899 * any pending transactions to complete before we hit the MAC
2900 * with the global reset.
2901 */
2902 ew32(RCTL, 0);
2903 ew32(TCTL, E1000_TCTL_PSP);
2904 e1e_flush();
2905
2906 msleep(10);
2907
2908 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2909 if (hw->mac.type == e1000_ich8lan) {
2910 /* Set Tx and Rx buffer allocation to 8k apiece. */
2911 ew32(PBA, E1000_PBA_8K);
2912 /* Set Packet Buffer Size to 16k. */
2913 ew32(PBS, E1000_PBS_16K);
2914 }
2915
1d5846b9
BA		 2916 if (hw->mac.type == e1000_pchlan) {
2917 /* Save the NVM K1 bit setting*/
2918 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2919 if (ret_val)
2920 return ret_val;
2921
2922 if (reg & E1000_NVM_K1_ENABLE)
2923 dev_spec->nvm_k1_enabled = true;
2924 else
2925 dev_spec->nvm_k1_enabled = false;
2926 }
2927
bc7f75fa
AK		 2928 ctrl = er32(CTRL);
2929
2930 if (!e1000_check_reset_block(hw)) {
ad68076e 2931 /*
e98cac44 2932 * Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 2933 * time to make sure the interface between MAC and the
2934 * external PHY is reset.
2935 */
2936 ctrl |= E1000_CTRL_PHY_RST;
2937 }
2938 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 2939 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 2940 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2941 msleep(20);
2942
fc0c7760 2943 if (!ret_val)
30bb0e0d 2944 e1000_release_swflag_ich8lan(hw);
37f40239 2945
e98cac44 2946 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 2947 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44
BA		 2948 if (ret_val)
2949 goto out;
fc0c7760 2950
e98cac44 2951 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211
BA		 2952 if (ret_val)
2953 goto out;
2954 }
e98cac44 2955
7d3cabbc
BA		 2956 /*
2957 * For PCH, this write will make sure that any noise
2958 * will be detected as a CRC error and be dropped rather than show up
2959 * as a bad packet to the DMA engine.
2960 */
2961 if (hw->mac.type == e1000_pchlan)
2962 ew32(CRC_OFFSET, 0x65656565);
2963
bc7f75fa
AK		 2964 ew32(IMC, 0xffffffff);
2965 icr = er32(ICR);
2966
2967 kab = er32(KABGTXD);
2968 kab |= E1000_KABGTXD_BGSQLBIAS;
2969 ew32(KABGTXD, kab);
2970
f523d211 2971out:
bc7f75fa
AK		 2972 return ret_val;
2973}
2974
2975/**
2976 * e1000_init_hw_ich8lan - Initialize the hardware
2977 * @hw: pointer to the HW structure
2978 *
2979 * Prepares the hardware for transmit and receive by doing the following:
2980 * - initialize hardware bits
2981 * - initialize LED identification
2982 * - setup receive address registers
2983 * - setup flow control
489815ce 2984 * - setup transmit descriptors
bc7f75fa
AK		 2985 * - clear statistics
2986 **/
2987static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2988{
2989 struct e1000_mac_info *mac = &hw->mac;
2990 u32 ctrl_ext, txdctl, snoop;
2991 s32 ret_val;
2992 u16 i;
2993
2994 e1000_initialize_hw_bits_ich8lan(hw);
2995
2996 /* Initialize identification LED */
a4f58f54 2997 ret_val = mac->ops.id_led_init(hw);
de39b752 2998 if (ret_val)
3bb99fe2 2999 e_dbg("Error initializing identification LED\n");
de39b752 3000 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 3001
3002 /* Setup the receive address. */
3003 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3004
3005 /* Zero out the Multicast HASH table */
3bb99fe2 3006 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3007 for (i = 0; i < mac->mta_reg_count; i++)
3008 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3009
fc0c7760
BA		 3010 /*
3011 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3012 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3013 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3014 */
3015 if (hw->phy.type == e1000_phy_82578) {
94d8186a 3016 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 3017 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3018 if (ret_val)
3019 return ret_val;
3020 }
3021
bc7f75fa
AK		 3022 /* Setup link and flow control */
3023 ret_val = e1000_setup_link_ich8lan(hw);
3024
3025 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3026 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 3027 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3028 E1000_TXDCTL_FULL_TX_DESC_WB;
3029 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3030 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 3031 ew32(TXDCTL(0), txdctl);
3032 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 3033 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3034 E1000_TXDCTL_FULL_TX_DESC_WB;
3035 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3036 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 3037 ew32(TXDCTL(1), txdctl);
bc7f75fa 3038
ad68076e
BA		 3039 /*
3040 * ICH8 has opposite polarity of no_snoop bits.
3041 * By default, we should use snoop behavior.
3042 */
bc7f75fa
AK		 3043 if (mac->type == e1000_ich8lan)
3044 snoop = PCIE_ICH8_SNOOP_ALL;
3045 else
3046 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3047 e1000e_set_pcie_no_snoop(hw, snoop);
3048
3049 ctrl_ext = er32(CTRL_EXT);
3050 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3051 ew32(CTRL_EXT, ctrl_ext);
3052
ad68076e
BA		 3053 /*
3054 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3055 * important that we do this after we have tried to establish link
3056 * because the symbol error count will increment wildly if there
3057 * is no link.
3058 */
3059 e1000_clear_hw_cntrs_ich8lan(hw);
3060
3061 return 0;
3062}
3063/**
3064 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3065 * @hw: pointer to the HW structure
3066 *
3067 * Sets/Clears required hardware bits necessary for correctly setting up the
3068 * hardware for transmit and receive.
3069 **/
3070static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3071{
3072 u32 reg;
3073
3074 /* Extended Device Control */
3075 reg = er32(CTRL_EXT);
3076 reg |= (1 << 22);
a4f58f54
BA		 3077 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3078 if (hw->mac.type >= e1000_pchlan)
3079 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3080 ew32(CTRL_EXT, reg);
3081
3082 /* Transmit Descriptor Control 0 */
e9ec2c0f 3083 reg = er32(TXDCTL(0));
bc7f75fa 3084 reg |= (1 << 22);
e9ec2c0f 3085 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3086
3087 /* Transmit Descriptor Control 1 */
e9ec2c0f 3088 reg = er32(TXDCTL(1));
bc7f75fa 3089 reg |= (1 << 22);
e9ec2c0f 3090 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3091
3092 /* Transmit Arbitration Control 0 */
e9ec2c0f 3093 reg = er32(TARC(0));
bc7f75fa
AK		 3094 if (hw->mac.type == e1000_ich8lan)
3095 reg |= (1 << 28) | (1 << 29);
3096 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3097 ew32(TARC(0), reg);
bc7f75fa
AK		 3098
3099 /* Transmit Arbitration Control 1 */
e9ec2c0f 3100 reg = er32(TARC(1));
bc7f75fa
AK		 3101 if (er32(TCTL) & E1000_TCTL_MULR)
3102 reg &= ~(1 << 28);
3103 else
3104 reg |= (1 << 28);
3105 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3106 ew32(TARC(1), reg);
bc7f75fa
AK		 3107
3108 /* Device Status */
3109 if (hw->mac.type == e1000_ich8lan) {
3110 reg = er32(STATUS);
3111 reg &= ~(1 << 31);
3112 ew32(STATUS, reg);
3113 }
a80483d3
JB		 3114
3115 /*
3116 * work-around descriptor data corruption issue during nfs v2 udp
3117 * traffic, just disable the nfs filtering capability
3118 */
3119 reg = er32(RFCTL);
3120 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3121 ew32(RFCTL, reg);
bc7f75fa
AK		 3122}
3123
3124/**
3125 * e1000_setup_link_ich8lan - Setup flow control and link settings
3126 * @hw: pointer to the HW structure
3127 *
3128 * Determines which flow control settings to use, then configures flow
3129 * control. Calls the appropriate media-specific link configuration
3130 * function. Assuming the adapter has a valid link partner, a valid link
3131 * should be established. Assumes the hardware has previously been reset
3132 * and the transmitter and receiver are not enabled.
3133 **/
3134static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3135{
bc7f75fa
AK		 3136 s32 ret_val;
3137
3138 if (e1000_check_reset_block(hw))
3139 return 0;
3140
ad68076e
BA		 3141 /*
3142 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3143 * the default flow control setting, so we explicitly
3144 * set it to full.
3145 */
37289d9c
BA		 3146 if (hw->fc.requested_mode == e1000_fc_default) {
3147 /* Workaround h/w hang when Tx flow control enabled */
3148 if (hw->mac.type == e1000_pchlan)
3149 hw->fc.requested_mode = e1000_fc_rx_pause;
3150 else
3151 hw->fc.requested_mode = e1000_fc_full;
3152 }
bc7f75fa 3153
5c48ef3e
BA		 3154 /*
3155 * Save off the requested flow control mode for use later. Depending
3156 * on the link partner's capabilities, we may or may not use this mode.
3157 */
3158 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3159
3bb99fe2 3160 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 3161 hw->fc.current_mode);
bc7f75fa
AK		 3162
3163 /* Continue to configure the copper link. */
3164 ret_val = e1000_setup_copper_link_ich8lan(hw);
3165 if (ret_val)
3166 return ret_val;
3167
318a94d6 3168 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3169 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3170 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3171 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3172 ew32(FCRTV_PCH, hw->fc.refresh_time);
3173
94d8186a 3174 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 3175 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3176 hw->fc.pause_time);
3177 if (ret_val)
3178 return ret_val;
3179 }
bc7f75fa
AK		 3180
3181 return e1000e_set_fc_watermarks(hw);
3182}
3183
3184/**
3185 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3186 * @hw: pointer to the HW structure
3187 *
3188 * Configures the kumeran interface to the PHY to wait the appropriate time
3189 * when polling the PHY, then call the generic setup_copper_link to finish
3190 * configuring the copper link.
3191 **/
3192static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3193{
3194 u32 ctrl;
3195 s32 ret_val;
3196 u16 reg_data;
3197
3198 ctrl = er32(CTRL);
3199 ctrl |= E1000_CTRL_SLU;
3200 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3201 ew32(CTRL, ctrl);
3202
ad68076e
BA		 3203 /*
3204 * Set the mac to wait the maximum time between each iteration
bc7f75fa 3205 * and increase the max iterations when polling the phy;
ad68076e
BA		 3206 * this fixes erroneous timeouts at 10Mbps.
3207 */
07818950 3208 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3209 if (ret_val)
3210 return ret_val;
07818950
BA		 3211 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3212 &reg_data);
bc7f75fa
AK		 3213 if (ret_val)
3214 return ret_val;
3215 reg_data |= 0x3F;
07818950
BA		 3216 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3217 reg_data);
bc7f75fa
AK		 3218 if (ret_val)
3219 return ret_val;
3220
a4f58f54
BA		 3221 switch (hw->phy.type) {
3222 case e1000_phy_igp_3:
bc7f75fa
AK		 3223 ret_val = e1000e_copper_link_setup_igp(hw);
3224 if (ret_val)
3225 return ret_val;
a4f58f54
BA		 3226 break;
3227 case e1000_phy_bm:
3228 case e1000_phy_82578:
97ac8cae
BA		 3229 ret_val = e1000e_copper_link_setup_m88(hw);
3230 if (ret_val)
3231 return ret_val;
a4f58f54
BA		 3232 break;
3233 case e1000_phy_82577:
d3738bb8 3234 case e1000_phy_82579:
a4f58f54
BA		 3235 ret_val = e1000_copper_link_setup_82577(hw);
3236 if (ret_val)
3237 return ret_val;
3238 break;
3239 case e1000_phy_ife:
94d8186a 3240 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3241 &reg_data);
97ac8cae
BA		 3242 if (ret_val)
3243 return ret_val;
3244
3245 reg_data &= ~IFE_PMC_AUTO_MDIX;
3246
3247 switch (hw->phy.mdix) {
3248 case 1:
3249 reg_data &= ~IFE_PMC_FORCE_MDIX;
3250 break;
3251 case 2:
3252 reg_data |= IFE_PMC_FORCE_MDIX;
3253 break;
3254 case 0:
3255 default:
3256 reg_data |= IFE_PMC_AUTO_MDIX;
3257 break;
3258 }
94d8186a 3259 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3260 reg_data);
97ac8cae
BA		 3261 if (ret_val)
3262 return ret_val;
a4f58f54
BA		 3263 break;
3264 default:
3265 break;
97ac8cae 3266 }
bc7f75fa
AK		 3267 return e1000e_setup_copper_link(hw);
3268}
3269
3270/**
3271 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3272 * @hw: pointer to the HW structure
3273 * @speed: pointer to store current link speed
3274 * @duplex: pointer to store the current link duplex
3275 *
ad68076e 3276 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 3277 * information and then calls the Kumeran lock loss workaround for links at
3278 * gigabit speeds.
3279 **/
3280static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3281 u16 *duplex)
3282{
3283 s32 ret_val;
3284
3285 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3286 if (ret_val)
3287 return ret_val;
3288
3289 if ((hw->mac.type == e1000_ich8lan) &&
3290 (hw->phy.type == e1000_phy_igp_3) &&
3291 (*speed == SPEED_1000)) {
3292 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3293 }
3294
3295 return ret_val;
3296}
3297
3298/**
3299 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3300 * @hw: pointer to the HW structure
3301 *
3302 * Work-around for 82566 Kumeran PCS lock loss:
3303 * On link status change (i.e. PCI reset, speed change) and link is up and
3304 * speed is gigabit-
3305 * 0) if workaround is optionally disabled do nothing
3306 * 1) wait 1ms for Kumeran link to come up
3307 * 2) check Kumeran Diagnostic register PCS lock loss bit
3308 * 3) if not set the link is locked (all is good), otherwise...
3309 * 4) reset the PHY
3310 * 5) repeat up to 10 times
3311 * Note: this is only called for IGP3 copper when speed is 1gb.
3312 **/
3313static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3314{
3315 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3316 u32 phy_ctrl;
3317 s32 ret_val;
3318 u16 i, data;
3319 bool link;
3320
3321 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3322 return 0;
3323
ad68076e
BA		 3324 /*
3325 * Make sure link is up before proceeding. If not just return.
bc7f75fa 3326 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3327 * stability
3328 */
bc7f75fa
AK		 3329 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3330 if (!link)
3331 return 0;
3332
3333 for (i = 0; i < 10; i++) {
3334 /* read once to clear */
3335 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3336 if (ret_val)
3337 return ret_val;
3338 /* and again to get new status */
3339 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3340 if (ret_val)
3341 return ret_val;
3342
3343 /* check for PCS lock */
3344 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3345 return 0;
3346
3347 /* Issue PHY reset */
3348 e1000_phy_hw_reset(hw);
3349 mdelay(5);
3350 }
3351 /* Disable GigE link negotiation */
3352 phy_ctrl = er32(PHY_CTRL);
3353 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3354 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3355 ew32(PHY_CTRL, phy_ctrl);
3356
ad68076e
BA		 3357 /*
3358 * Call gig speed drop workaround on Gig disable before accessing
3359 * any PHY registers
3360 */
bc7f75fa
AK		 3361 e1000e_gig_downshift_workaround_ich8lan(hw);
3362
3363 /* unable to acquire PCS lock */
3364 return -E1000_ERR_PHY;
3365}
3366
3367/**
ad68076e 3368 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3369 * @hw: pointer to the HW structure
489815ce 3370 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3371 *
564ea9bb
BA		 3372 * If ICH8, set the current Kumeran workaround state (enabled - true
3373 * /disabled - false).
bc7f75fa
AK		 3374 **/
3375void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3376 bool state)
3377{
3378 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3379
3380 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3381 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3382 return;
3383 }
3384
3385 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3386}
3387
3388/**
3389 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3390 * @hw: pointer to the HW structure
3391 *
3392 * Workaround for 82566 power-down on D3 entry:
3393 * 1) disable gigabit link
3394 * 2) write VR power-down enable
3395 * 3) read it back
3396 * Continue if successful, else issue LCD reset and repeat
3397 **/
3398void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3399{
3400 u32 reg;
3401 u16 data;
3402 u8 retry = 0;
3403
3404 if (hw->phy.type != e1000_phy_igp_3)
3405 return;
3406
3407 /* Try the workaround twice (if needed) */
3408 do {
3409 /* Disable link */
3410 reg = er32(PHY_CTRL);
3411 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3412 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3413 ew32(PHY_CTRL, reg);
3414
ad68076e
BA		 3415 /*
3416 * Call gig speed drop workaround on Gig disable before
3417 * accessing any PHY registers
3418 */
bc7f75fa
AK		 3419 if (hw->mac.type == e1000_ich8lan)
3420 e1000e_gig_downshift_workaround_ich8lan(hw);
3421
3422 /* Write VR power-down enable */
3423 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3424 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3425 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3426
3427 /* Read it back and test */
3428 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3429 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3430 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3431 break;
3432
3433 /* Issue PHY reset and repeat at most one more time */
3434 reg = er32(CTRL);
3435 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3436 retry++;
3437 } while (retry);
3438}
3439
3440/**
3441 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3442 * @hw: pointer to the HW structure
3443 *
3444 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3445 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3446 * 1) Set Kumeran Near-end loopback
3447 * 2) Clear Kumeran Near-end loopback
3448 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3449 **/
3450void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3451{
3452 s32 ret_val;
3453 u16 reg_data;
3454
3455 if ((hw->mac.type != e1000_ich8lan) ||
3456 (hw->phy.type != e1000_phy_igp_3))
3457 return;
3458
3459 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3460 &reg_data);
3461 if (ret_val)
3462 return;
3463 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3464 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3465 reg_data);
3466 if (ret_val)
3467 return;
3468 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3469 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3470 reg_data);
3471}
3472
97ac8cae
BA		 3473/**
3474 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3475 * @hw: pointer to the HW structure
3476 *
3477 * During S0 to Sx transition, it is possible the link remains at gig
3478 * instead of negotiating to a lower speed. Before going to Sx, set
3479 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3480 * to a lower speed.
3481 *
a4f58f54 3482 * Should only be called for applicable parts.
97ac8cae
BA		 3483 **/
3484void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3485{
3486 u32 phy_ctrl;
8395ae83 3487 s32 ret_val;
97ac8cae 3488
17f085df
BA		 3489 phy_ctrl = er32(PHY_CTRL);
3490 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3491 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3492
8395ae83
BA		 3493 if (hw->mac.type >= e1000_pchlan) {
3494 e1000_oem_bits_config_ich8lan(hw, true);
3495 ret_val = hw->phy.ops.acquire(hw);
3496 if (ret_val)
3497 return;
3498 e1000_write_smbus_addr(hw);
3499 hw->phy.ops.release(hw);
3500 }
97ac8cae
BA		 3501}
3502
bc7f75fa
AK		 3503/**
3504 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3505 * @hw: pointer to the HW structure
3506 *
3507 * Return the LED back to the default configuration.
3508 **/
3509static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3510{
3511 if (hw->phy.type == e1000_phy_ife)
3512 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3513
3514 ew32(LEDCTL, hw->mac.ledctl_default);
3515 return 0;
3516}
3517
3518/**
489815ce 3519 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3520 * @hw: pointer to the HW structure
3521 *
489815ce 3522 * Turn on the LEDs.
bc7f75fa
AK		 3523 **/
3524static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3525{
3526 if (hw->phy.type == e1000_phy_ife)
3527 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3528 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3529
3530 ew32(LEDCTL, hw->mac.ledctl_mode2);
3531 return 0;
3532}
3533
3534/**
489815ce 3535 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3536 * @hw: pointer to the HW structure
3537 *
489815ce 3538 * Turn off the LEDs.
bc7f75fa
AK		 3539 **/
3540static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3541{
3542 if (hw->phy.type == e1000_phy_ife)
3543 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3544 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3545
3546 ew32(LEDCTL, hw->mac.ledctl_mode1);
3547 return 0;
3548}
3549
a4f58f54
BA		 3550/**
3551 * e1000_setup_led_pchlan - Configures SW controllable LED
3552 * @hw: pointer to the HW structure
3553 *
3554 * This prepares the SW controllable LED for use.
3555 **/
3556static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3557{
94d8186a 3558 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3559 (u16)hw->mac.ledctl_mode1);
3560}
3561
3562/**
3563 * e1000_cleanup_led_pchlan - Restore the default LED operation
3564 * @hw: pointer to the HW structure
3565 *
3566 * Return the LED back to the default configuration.
3567 **/
3568static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3569{
94d8186a 3570 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3571 (u16)hw->mac.ledctl_default);
3572}
3573
3574/**
3575 * e1000_led_on_pchlan - Turn LEDs on
3576 * @hw: pointer to the HW structure
3577 *
3578 * Turn on the LEDs.
3579 **/
3580static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3581{
3582 u16 data = (u16)hw->mac.ledctl_mode2;
3583 u32 i, led;
3584
3585 /*
3586 * If no link, then turn LED on by setting the invert bit
3587 * for each LED that's mode is "link_up" in ledctl_mode2.
3588 */
3589 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3590 for (i = 0; i < 3; i++) {
3591 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3592 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3593 E1000_LEDCTL_MODE_LINK_UP)
3594 continue;
3595 if (led & E1000_PHY_LED0_IVRT)
3596 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3597 else
3598 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3599 }
3600 }
3601
94d8186a 3602 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3603}
3604
3605/**
3606 * e1000_led_off_pchlan - Turn LEDs off
3607 * @hw: pointer to the HW structure
3608 *
3609 * Turn off the LEDs.
3610 **/
3611static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3612{
3613 u16 data = (u16)hw->mac.ledctl_mode1;
3614 u32 i, led;
3615
3616 /*
3617 * If no link, then turn LED off by clearing the invert bit
3618 * for each LED that's mode is "link_up" in ledctl_mode1.
3619 */
3620 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3621 for (i = 0; i < 3; i++) {
3622 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3623 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3624 E1000_LEDCTL_MODE_LINK_UP)
3625 continue;
3626 if (led & E1000_PHY_LED0_IVRT)
3627 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3628 else
3629 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3630 }
3631 }
3632
94d8186a 3633 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3634}
3635
f4187b56 3636/**
e98cac44 3637 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 3638 * @hw: pointer to the HW structure
3639 *
e98cac44
BA		 3640 * Read appropriate register for the config done bit for completion status
3641 * and configure the PHY through s/w for EEPROM-less parts.
3642 *
3643 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3644 * config done bit, so only an error is logged and continues. If we were
3645 * to return with error, EEPROM-less silicon would not be able to be reset
3646 * or change link.
f4187b56
BA		 3647 **/
3648static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3649{
e98cac44 3650 s32 ret_val = 0;
f4187b56 3651 u32 bank = 0;
e98cac44 3652 u32 status;
f4187b56 3653
e98cac44 3654 e1000e_get_cfg_done(hw);
fc0c7760 3655
e98cac44
BA		 3656 /* Wait for indication from h/w that it has completed basic config */
3657 if (hw->mac.type >= e1000_ich10lan) {
3658 e1000_lan_init_done_ich8lan(hw);
3659 } else {
3660 ret_val = e1000e_get_auto_rd_done(hw);
3661 if (ret_val) {
3662 /*
3663 * When auto config read does not complete, do not
3664 * return with an error. This can happen in situations
3665 * where there is no eeprom and prevents getting link.
3666 */
3667 e_dbg("Auto Read Done did not complete\n");
3668 ret_val = 0;
3669 }
fc0c7760
BA		 3670 }
3671
e98cac44
BA		 3672 /* Clear PHY Reset Asserted bit */
3673 status = er32(STATUS);
3674 if (status & E1000_STATUS_PHYRA)
3675 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3676 else
3677 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 3678
3679 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 3680 if (hw->mac.type <= e1000_ich9lan) {
f4187b56
BA		 3681 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3682 (hw->phy.type == e1000_phy_igp_3)) {
3683 e1000e_phy_init_script_igp3(hw);
3684 }
3685 } else {
3686 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3687 /* Maybe we should do a basic PHY config */
3bb99fe2 3688 e_dbg("EEPROM not present\n");
e98cac44 3689 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 3690 }
3691 }
3692
e98cac44 3693 return ret_val;
f4187b56
BA		 3694}
3695
17f208de
BA		 3696/**
3697 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3698 * @hw: pointer to the HW structure
3699 *
3700 * In the case of a PHY power down to save power, or to turn off link during a
3701 * driver unload, or wake on lan is not enabled, remove the link.
3702 **/
3703static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3704{
3705 /* If the management interface is not enabled, then power down */
3706 if (!(hw->mac.ops.check_mng_mode(hw) ||
3707 hw->phy.ops.check_reset_block(hw)))
3708 e1000_power_down_phy_copper(hw);
17f208de
BA		 3709}
3710
bc7f75fa
AK		 3711/**
3712 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3713 * @hw: pointer to the HW structure
3714 *
3715 * Clears hardware counters specific to the silicon family and calls
3716 * clear_hw_cntrs_generic to clear all general purpose counters.
3717 **/
3718static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3719{
a4f58f54 3720 u16 phy_data;
bc7f75fa
AK		 3721
3722 e1000e_clear_hw_cntrs_base(hw);
3723
99673d9b
BA		 3724 er32(ALGNERRC);
3725 er32(RXERRC);
3726 er32(TNCRS);
3727 er32(CEXTERR);
3728 er32(TSCTC);
3729 er32(TSCTFC);
bc7f75fa 3730
99673d9b
BA		 3731 er32(MGTPRC);
3732 er32(MGTPDC);
3733 er32(MGTPTC);
bc7f75fa 3734
99673d9b
BA		 3735 er32(IAC);
3736 er32(ICRXOC);
bc7f75fa 3737
a4f58f54
BA		 3738 /* Clear PHY statistics registers */
3739 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3740 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3741 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3742 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3743 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3744 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3745 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3746 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3747 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3748 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3749 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3750 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3751 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3752 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3753 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3754 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3755 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3756 }
bc7f75fa
AK		 3757}
3758
3759static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3760 .id_led_init = e1000e_id_led_init,
eb7700dc 3761 /* check_mng_mode dependent on mac type */
7d3cabbc 3762 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3763 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3764 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3765 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 3766 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 3767 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3768 /* led_on dependent on mac type */
3769 /* led_off dependent on mac type */
e2de3eb6 3770 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3771 .reset_hw = e1000_reset_hw_ich8lan,
3772 .init_hw = e1000_init_hw_ich8lan,
3773 .setup_link = e1000_setup_link_ich8lan,
3774 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3775 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3776};
3777
3778static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3779 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3780 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3781 .commit = NULL,
f4187b56 3782 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3783 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3784 .read_reg = e1000e_read_phy_reg_igp,
3785 .release = e1000_release_swflag_ich8lan,
3786 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3787 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3788 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3789 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3790};
3791
3792static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3793 .acquire = e1000_acquire_nvm_ich8lan,
3794 .read = e1000_read_nvm_ich8lan,
3795 .release = e1000_release_nvm_ich8lan,
3796 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3797 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3798 .validate = e1000_validate_nvm_checksum_ich8lan,
3799 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3800};
3801
3802struct e1000_info e1000_ich8_info = {
3803 .mac = e1000_ich8lan,
3804 .flags = FLAG_HAS_WOL
97ac8cae 3805 | FLAG_IS_ICH
bc7f75fa
AK		 3806 | FLAG_RX_CSUM_ENABLED
3807 | FLAG_HAS_CTRLEXT_ON_LOAD
3808 | FLAG_HAS_AMT
3809 | FLAG_HAS_FLASH
3810 | FLAG_APME_IN_WUC,
3811 .pba = 8,
2adc55c9 3812 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3813 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3814 .mac_ops = &ich8_mac_ops,
3815 .phy_ops = &ich8_phy_ops,
3816 .nvm_ops = &ich8_nvm_ops,
3817};
3818
3819struct e1000_info e1000_ich9_info = {
3820 .mac = e1000_ich9lan,
3821 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3822 | FLAG_IS_ICH
bc7f75fa
AK		 3823 | FLAG_HAS_WOL
3824 | FLAG_RX_CSUM_ENABLED
3825 | FLAG_HAS_CTRLEXT_ON_LOAD
3826 | FLAG_HAS_AMT
3827 | FLAG_HAS_ERT
3828 | FLAG_HAS_FLASH
3829 | FLAG_APME_IN_WUC,
3830 .pba = 10,
2adc55c9 3831 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3832 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3833 .mac_ops = &ich8_mac_ops,
3834 .phy_ops = &ich8_phy_ops,
3835 .nvm_ops = &ich8_nvm_ops,
3836};
3837
f4187b56
BA		 3838struct e1000_info e1000_ich10_info = {
3839 .mac = e1000_ich10lan,
3840 .flags = FLAG_HAS_JUMBO_FRAMES
3841 | FLAG_IS_ICH
3842 | FLAG_HAS_WOL
3843 | FLAG_RX_CSUM_ENABLED
3844 | FLAG_HAS_CTRLEXT_ON_LOAD
3845 | FLAG_HAS_AMT
3846 | FLAG_HAS_ERT
3847 | FLAG_HAS_FLASH
3848 | FLAG_APME_IN_WUC,
3849 .pba = 10,
2adc55c9 3850 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3851 .get_variants = e1000_get_variants_ich8lan,
3852 .mac_ops = &ich8_mac_ops,
3853 .phy_ops = &ich8_phy_ops,
3854 .nvm_ops = &ich8_nvm_ops,
3855};
a4f58f54
BA		 3856
3857struct e1000_info e1000_pch_info = {
3858 .mac = e1000_pchlan,
3859 .flags = FLAG_IS_ICH
3860 | FLAG_HAS_WOL
3861 | FLAG_RX_CSUM_ENABLED
3862 | FLAG_HAS_CTRLEXT_ON_LOAD
3863 | FLAG_HAS_AMT
3864 | FLAG_HAS_FLASH
3865 | FLAG_HAS_JUMBO_FRAMES
38eb394e 3866 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 3867 | FLAG_APME_IN_WUC,
8c7bbb92 3868 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 3869 .pba = 26,
3870 .max_hw_frame_size = 4096,
3871 .get_variants = e1000_get_variants_ich8lan,
3872 .mac_ops = &ich8_mac_ops,
3873 .phy_ops = &ich8_phy_ops,
3874 .nvm_ops = &ich8_nvm_ops,
3875};
d3738bb8
BA		 3876
3877struct e1000_info e1000_pch2_info = {
3878 .mac = e1000_pch2lan,
3879 .flags = FLAG_IS_ICH
3880 | FLAG_HAS_WOL
3881 | FLAG_RX_CSUM_ENABLED
3882 | FLAG_HAS_CTRLEXT_ON_LOAD
3883 | FLAG_HAS_AMT
3884 | FLAG_HAS_FLASH
3885 | FLAG_HAS_JUMBO_FRAMES
3886 | FLAG_APME_IN_WUC,
e52997f9
BA		 3887 .flags2 = FLAG2_HAS_PHY_STATS
3888 | FLAG2_HAS_EEE,
d3738bb8
BA		 3889 .pba = 18,
3890 .max_hw_frame_size = DEFAULT_JUMBO,
3891 .get_variants = e1000_get_variants_ich8lan,
3892 .mac_ops = &ich8_mac_ops,
3893 .phy_ops = &ich8_phy_ops,
3894 .nvm_ops = &ich8_nvm_ops,
3895};
Clone of davem's net-next-2.6 tree