[net-next-2.6.git] / drivers / net / davinci_cpdma.h

/*
 * Texas Instruments CPDMA Driver
 *
 * Copyright (C) 2010 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __DAVINCI_CPDMA_H__
#define __DAVINCI_CPDMA_H__

#define CPDMA_MAX_CHANNELS	BITS_PER_LONG

#define tx_chan_num(chan)	(chan)
#define rx_chan_num(chan)	((chan) + CPDMA_MAX_CHANNELS)
#define is_rx_chan(chan)	((chan)->chan_num >= CPDMA_MAX_CHANNELS)
#define is_tx_chan(chan)	(!is_rx_chan(chan))
#define __chan_linear(chan_num)	((chan_num) & (CPDMA_MAX_CHANNELS - 1))
#define chan_linear(chan)	__chan_linear((chan)->chan_num)

struct cpdma_params {
	struct device		*dev;
	void __iomem		*dmaregs;
	void __iomem		*txhdp, *rxhdp, *txcp, *rxcp;
	void __iomem		*rxthresh, *rxfree;
	int			num_chan;
	bool			has_soft_reset;
	int			min_packet_size;
	u32			desc_mem_phys;
	int			desc_mem_size;
	int			desc_align;

	/*
	 * Some instances of embedded cpdma controllers have extra control and
	 * status registers.  The following flag enables access to these
	 * "extended" registers.
	 */
	bool			has_ext_regs;
};

struct cpdma_chan_stats {
	u32			head_enqueue;
	u32			tail_enqueue;
	u32			pad_enqueue;
	u32			misqueued;
	u32			desc_alloc_fail;
	u32			pad_alloc_fail;
	u32			runt_receive_buff;
	u32			runt_transmit_buff;
	u32			empty_dequeue;
	u32			busy_dequeue;
	u32			good_dequeue;
	u32			requeue;
	u32			teardown_dequeue;
};

struct cpdma_ctlr;
struct cpdma_chan;

typedef void (*cpdma_handler_fn)(void *token, int len, int status);

struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr);

struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
				     cpdma_handler_fn handler);
int cpdma_chan_destroy(struct cpdma_chan *chan);
int cpdma_chan_start(struct cpdma_chan *chan);
int cpdma_chan_stop(struct cpdma_chan *chan);
int cpdma_chan_dump(struct cpdma_chan *chan);

int cpdma_chan_get_stats(struct cpdma_chan *chan,
			 struct cpdma_chan_stats *stats);
int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
		      int len, gfp_t gfp_mask);
int cpdma_chan_process(struct cpdma_chan *chan, int quota);

int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);

enum cpdma_control {
	CPDMA_CMD_IDLE,			/* write-only */
	CPDMA_COPY_ERROR_FRAMES,	/* read-write */
	CPDMA_RX_OFF_LEN_UPDATE,	/* read-write */
	CPDMA_RX_OWNERSHIP_FLIP,	/* read-write */
	CPDMA_TX_PRIO_FIXED,		/* read-write */
	CPDMA_STAT_IDLE,		/* read-only */
	CPDMA_STAT_TX_ERR_CHAN,		/* read-only */
	CPDMA_STAT_TX_ERR_CODE,		/* read-only */
	CPDMA_STAT_RX_ERR_CHAN,		/* read-only */
	CPDMA_STAT_RX_ERR_CODE,		/* read-only */
	CPDMA_RX_BUFFER_OFFSET,		/* read-write */
};

int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);

#endif
Commit	Line	Data
ef8c2dab CC	1	/*
	2	* Texas Instruments CPDMA Driver
	3	*
	4	* Copyright (C) 2010 Texas Instruments
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15	#ifndef __DAVINCI_CPDMA_H__
	16	#define __DAVINCI_CPDMA_H__
	17
	18	#define CPDMA_MAX_CHANNELS BITS_PER_LONG
	19
	20	#define tx_chan_num(chan) (chan)
	21	#define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS)
	22	#define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS)
	23	#define is_tx_chan(chan) (!is_rx_chan(chan))
	24	#define __chan_linear(chan_num) ((chan_num) & (CPDMA_MAX_CHANNELS - 1))
	25	#define chan_linear(chan) __chan_linear((chan)->chan_num)
	26
	27	struct cpdma_params {
	28	struct device *dev;
	29	void __iomem *dmaregs;
	30	void __iomem txhdp, rxhdp, txcp, rxcp;
	31	void __iomem rxthresh, rxfree;
	32	int num_chan;
	33	bool has_soft_reset;
	34	int min_packet_size;
	35	u32 desc_mem_phys;
	36	int desc_mem_size;
	37	int desc_align;
	38
	39	/*
	40	* Some instances of embedded cpdma controllers have extra control and
	41	* status registers. The following flag enables access to these
	42	* "extended" registers.
	43	*/
	44	bool has_ext_regs;
	45	};
	46
	47	struct cpdma_chan_stats {
	48	u32 head_enqueue;
	49	u32 tail_enqueue;
	50	u32 pad_enqueue;
	51	u32 misqueued;
	52	u32 desc_alloc_fail;
	53	u32 pad_alloc_fail;
	54	u32 runt_receive_buff;
	55	u32 runt_transmit_buff;
	56	u32 empty_dequeue;
	57	u32 busy_dequeue;
	58	u32 good_dequeue;
	59	u32 requeue;
	60	u32 teardown_dequeue;
	61	};
	62
	63	struct cpdma_ctlr;
	64	struct cpdma_chan;
65
66	typedef void (cpdma_handler_fn)(void token, int len, int status);
67
68	struct cpdma_ctlr cpdma_ctlr_create(struct cpdma_params params);
69	int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
70	int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
71	int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
72	int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr);
73
74	struct cpdma_chan cpdma_chan_create(struct cpdma_ctlr ctlr, int chan_num,
75	cpdma_handler_fn handler);
76	int cpdma_chan_destroy(struct cpdma_chan *chan);
77	int cpdma_chan_start(struct cpdma_chan *chan);
78	int cpdma_chan_stop(struct cpdma_chan *chan);
79	int cpdma_chan_dump(struct cpdma_chan *chan);
80
81	int cpdma_chan_get_stats(struct cpdma_chan *chan,
82	struct cpdma_chan_stats *stats);
83	int cpdma_chan_submit(struct cpdma_chan chan, void token, void *data,
84	int len, gfp_t gfp_mask);
85	int cpdma_chan_process(struct cpdma_chan *chan, int quota);
86
87	int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
88	void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr);
89	int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
90
91	enum cpdma_control {
92	CPDMA_CMD_IDLE, /* write-only */
93	CPDMA_COPY_ERROR_FRAMES, /* read-write */
94	CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
95	CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
96	CPDMA_TX_PRIO_FIXED, /* read-write */
97	CPDMA_STAT_IDLE, /* read-only */
98	CPDMA_STAT_TX_ERR_CHAN, /* read-only */
99	CPDMA_STAT_TX_ERR_CODE, /* read-only */
100	CPDMA_STAT_RX_ERR_CHAN, /* read-only */
101	CPDMA_STAT_RX_ERR_CODE, /* read-only */
102	CPDMA_RX_BUFFER_OFFSET, /* read-write */
103	};
104
105	int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
106	int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
107
108	#endif