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d95b39c3
MC		 1/*
2 * Copyright (C) 2006, 2007 Eugene Konev
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/moduleparam.h>
22
23#include <linux/sched.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/errno.h>
27#include <linux/types.h>
28#include <linux/delay.h>
29#include <linux/version.h>
30
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/skbuff.h>
35#include <linux/mii.h>
36#include <linux/phy.h>
b88219f8 37#include <linux/phy_fixed.h>
d95b39c3
MC		 38#include <linux/platform_device.h>
39#include <linux/dma-mapping.h>
40#include <asm/gpio.h>
41
42MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
43MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44MODULE_LICENSE("GPL");
45
46static int debug_level = 8;
47static int dumb_switch;
48
49/* Next 2 are only used in cpmac_probe, so it's pointless to change them */
50module_param(debug_level, int, 0444);
51module_param(dumb_switch, int, 0444);
52
53MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
54MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
55
56#define CPMAC_VERSION "0.5.0"
d95b39c3
MC		 57/* frame size + 802.1q tag */
58#define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
59#define CPMAC_QUEUES 8
60
61/* Ethernet registers */
62#define CPMAC_TX_CONTROL 0x0004
63#define CPMAC_TX_TEARDOWN 0x0008
64#define CPMAC_RX_CONTROL 0x0014
65#define CPMAC_RX_TEARDOWN 0x0018
66#define CPMAC_MBP 0x0100
67# define MBP_RXPASSCRC 0x40000000
68# define MBP_RXQOS 0x20000000
69# define MBP_RXNOCHAIN 0x10000000
70# define MBP_RXCMF 0x01000000
71# define MBP_RXSHORT 0x00800000
72# define MBP_RXCEF 0x00400000
73# define MBP_RXPROMISC 0x00200000
74# define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
75# define MBP_RXBCAST 0x00002000
76# define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
77# define MBP_RXMCAST 0x00000020
78# define MBP_MCASTCHAN(channel) ((channel) & 0x7)
79#define CPMAC_UNICAST_ENABLE 0x0104
80#define CPMAC_UNICAST_CLEAR 0x0108
81#define CPMAC_MAX_LENGTH 0x010c
82#define CPMAC_BUFFER_OFFSET 0x0110
83#define CPMAC_MAC_CONTROL 0x0160
84# define MAC_TXPTYPE 0x00000200
85# define MAC_TXPACE 0x00000040
86# define MAC_MII 0x00000020
87# define MAC_TXFLOW 0x00000010
88# define MAC_RXFLOW 0x00000008
89# define MAC_MTEST 0x00000004
90# define MAC_LOOPBACK 0x00000002
91# define MAC_FDX 0x00000001
92#define CPMAC_MAC_STATUS 0x0164
93# define MAC_STATUS_QOS 0x00000004
94# define MAC_STATUS_RXFLOW 0x00000002
95# define MAC_STATUS_TXFLOW 0x00000001
96#define CPMAC_TX_INT_ENABLE 0x0178
97#define CPMAC_TX_INT_CLEAR 0x017c
98#define CPMAC_MAC_INT_VECTOR 0x0180
99# define MAC_INT_STATUS 0x00080000
100# define MAC_INT_HOST 0x00040000
101# define MAC_INT_RX 0x00020000
102# define MAC_INT_TX 0x00010000
103#define CPMAC_MAC_EOI_VECTOR 0x0184
104#define CPMAC_RX_INT_ENABLE 0x0198
105#define CPMAC_RX_INT_CLEAR 0x019c
106#define CPMAC_MAC_INT_ENABLE 0x01a8
107#define CPMAC_MAC_INT_CLEAR 0x01ac
108#define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
109#define CPMAC_MAC_ADDR_MID 0x01d0
110#define CPMAC_MAC_ADDR_HI 0x01d4
111#define CPMAC_MAC_HASH_LO 0x01d8
112#define CPMAC_MAC_HASH_HI 0x01dc
113#define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
114#define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
115#define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
116#define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
117#define CPMAC_REG_END 0x0680
118/*
119 * Rx/Tx statistics
120 * TODO: use some of them to fill stats in cpmac_stats()
121 */
122#define CPMAC_STATS_RX_GOOD 0x0200
123#define CPMAC_STATS_RX_BCAST 0x0204
124#define CPMAC_STATS_RX_MCAST 0x0208
125#define CPMAC_STATS_RX_PAUSE 0x020c
126#define CPMAC_STATS_RX_CRC 0x0210
127#define CPMAC_STATS_RX_ALIGN 0x0214
128#define CPMAC_STATS_RX_OVER 0x0218
129#define CPMAC_STATS_RX_JABBER 0x021c
130#define CPMAC_STATS_RX_UNDER 0x0220
131#define CPMAC_STATS_RX_FRAG 0x0224
132#define CPMAC_STATS_RX_FILTER 0x0228
133#define CPMAC_STATS_RX_QOSFILTER 0x022c
134#define CPMAC_STATS_RX_OCTETS 0x0230
135
136#define CPMAC_STATS_TX_GOOD 0x0234
137#define CPMAC_STATS_TX_BCAST 0x0238
138#define CPMAC_STATS_TX_MCAST 0x023c
139#define CPMAC_STATS_TX_PAUSE 0x0240
140#define CPMAC_STATS_TX_DEFER 0x0244
141#define CPMAC_STATS_TX_COLLISION 0x0248
142#define CPMAC_STATS_TX_SINGLECOLL 0x024c
143#define CPMAC_STATS_TX_MULTICOLL 0x0250
144#define CPMAC_STATS_TX_EXCESSCOLL 0x0254
145#define CPMAC_STATS_TX_LATECOLL 0x0258
146#define CPMAC_STATS_TX_UNDERRUN 0x025c
147#define CPMAC_STATS_TX_CARRIERSENSE 0x0260
148#define CPMAC_STATS_TX_OCTETS 0x0264
149
150#define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
151#define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
152 (reg)))
153
154/* MDIO bus */
155#define CPMAC_MDIO_VERSION 0x0000
156#define CPMAC_MDIO_CONTROL 0x0004
157# define MDIOC_IDLE 0x80000000
158# define MDIOC_ENABLE 0x40000000
159# define MDIOC_PREAMBLE 0x00100000
160# define MDIOC_FAULT 0x00080000
161# define MDIOC_FAULTDETECT 0x00040000
162# define MDIOC_INTTEST 0x00020000
163# define MDIOC_CLKDIV(div) ((div) & 0xff)
164#define CPMAC_MDIO_ALIVE 0x0008
165#define CPMAC_MDIO_LINK 0x000c
166#define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
167# define MDIO_BUSY 0x80000000
168# define MDIO_WRITE 0x40000000
169# define MDIO_REG(reg) (((reg) & 0x1f) << 21)
170# define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
171# define MDIO_DATA(data) ((data) & 0xffff)
172#define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
173# define PHYSEL_LINKSEL 0x00000040
174# define PHYSEL_LINKINT 0x00000020
175
176struct cpmac_desc {
177 u32 hw_next;
178 u32 hw_data;
179 u16 buflen;
180 u16 bufflags;
181 u16 datalen;
182 u16 dataflags;
183#define CPMAC_SOP 0x8000
184#define CPMAC_EOP 0x4000
185#define CPMAC_OWN 0x2000
186#define CPMAC_EOQ 0x1000
187 struct sk_buff *skb;
188 struct cpmac_desc *next;
189 dma_addr_t mapping;
190 dma_addr_t data_mapping;
191};
192
193struct cpmac_priv {
194 spinlock_t lock;
195 spinlock_t rx_lock;
196 struct cpmac_desc *rx_head;
197 int ring_size;
198 struct cpmac_desc *desc_ring;
199 dma_addr_t dma_ring;
200 void __iomem *regs;
201 struct mii_bus *mii_bus;
202 struct phy_device *phy;
203 char phy_name[BUS_ID_SIZE];
204 int oldlink, oldspeed, oldduplex;
205 u32 msg_enable;
206 struct net_device *dev;
207 struct work_struct reset_work;
208 struct platform_device *pdev;
67d129d1 209 struct napi_struct napi;
d95b39c3
MC		 210};
211
212static irqreturn_t cpmac_irq(int, void *);
213static void cpmac_hw_start(struct net_device *dev);
214static void cpmac_hw_stop(struct net_device *dev);
215static int cpmac_stop(struct net_device *dev);
216static int cpmac_open(struct net_device *dev);
217
218static void cpmac_dump_regs(struct net_device *dev)
219{
220 int i;
221 struct cpmac_priv *priv = netdev_priv(dev);
222 for (i = 0; i < CPMAC_REG_END; i += 4) {
223 if (i % 16 == 0) {
224 if (i)
225 printk("\n");
226 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
227 priv->regs + i);
228 }
229 printk(" %08x", cpmac_read(priv->regs, i));
230 }
231 printk("\n");
232}
233
234static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
235{
236 int i;
237 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
238 for (i = 0; i < sizeof(*desc) / 4; i++)
239 printk(" %08x", ((u32 *)desc)[i]);
240 printk("\n");
241}
242
243static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
244{
245 int i;
246 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
247 for (i = 0; i < skb->len; i++) {
248 if (i % 16 == 0) {
249 if (i)
250 printk("\n");
251 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
252 skb->data + i);
253 }
254 printk(" %02x", ((u8 *)skb->data)[i]);
255 }
256 printk("\n");
257}
258
259static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
260{
261 u32 val;
262
263 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
264 cpu_relax();
265 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
266 MDIO_PHY(phy_id));
267 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
268 cpu_relax();
269 return MDIO_DATA(val);
270}
271
272static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
273 int reg, u16 val)
274{
275 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
276 cpu_relax();
277 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
278 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
279 return 0;
280}
281
282static int cpmac_mdio_reset(struct mii_bus *bus)
283{
284 ar7_device_reset(AR7_RESET_BIT_MDIO);
285 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
286 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
287 return 0;
288}
289
290static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
291
292static struct mii_bus cpmac_mii = {
293 .name = "cpmac-mii",
294 .read = cpmac_mdio_read,
295 .write = cpmac_mdio_write,
296 .reset = cpmac_mdio_reset,
297 .irq = mii_irqs,
298};
299
300static int cpmac_config(struct net_device *dev, struct ifmap *map)
301{
302 if (dev->flags & IFF_UP)
303 return -EBUSY;
304
305 /* Don't allow changing the I/O address */
306 if (map->base_addr != dev->base_addr)
307 return -EOPNOTSUPP;
308
309 /* ignore other fields */
310 return 0;
311}
312
313static void cpmac_set_multicast_list(struct net_device *dev)
314{
315 struct dev_mc_list *iter;
316 int i;
317 u8 tmp;
318 u32 mbp, bit, hash[2] = { 0, };
319 struct cpmac_priv *priv = netdev_priv(dev);
320
321 mbp = cpmac_read(priv->regs, CPMAC_MBP);
322 if (dev->flags & IFF_PROMISC) {
323 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
324 MBP_RXPROMISC);
325 } else {
326 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
327 if (dev->flags & IFF_ALLMULTI) {
328 /* enable all multicast mode */
329 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
330 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
331 } else {
332 /*
333 * cpmac uses some strange mac address hashing
334 * (not crc32)
335 */
336 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
337 i++, iter = iter->next) {
338 bit = 0;
339 tmp = iter->dmi_addr[0];
340 bit ^= (tmp >> 2) ^ (tmp << 4);
341 tmp = iter->dmi_addr[1];
342 bit ^= (tmp >> 4) ^ (tmp << 2);
343 tmp = iter->dmi_addr[2];
344 bit ^= (tmp >> 6) ^ tmp;
345 tmp = iter->dmi_addr[3];
346 bit ^= (tmp >> 2) ^ (tmp << 4);
347 tmp = iter->dmi_addr[4];
348 bit ^= (tmp >> 4) ^ (tmp << 2);
349 tmp = iter->dmi_addr[5];
350 bit ^= (tmp >> 6) ^ tmp;
351 bit &= 0x3f;
352 hash[bit / 32] |= 1 << (bit % 32);
353 }
354
355 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
356 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
357 }
358 }
359}
360
67d129d1 361static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
d95b39c3
MC		 362 struct cpmac_desc *desc)
363{
364 struct sk_buff *skb, *result = NULL;
365
366 if (unlikely(netif_msg_hw(priv)))
67d129d1 367 cpmac_dump_desc(priv->dev, desc);
d95b39c3
MC		 368 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
369 if (unlikely(!desc->datalen)) {
370 if (netif_msg_rx_err(priv) && net_ratelimit())
371 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
67d129d1 372 priv->dev->name);
d95b39c3
MC		 373 return NULL;
374 }
375
67d129d1 376 skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
d95b39c3
MC		 377 if (likely(skb)) {
378 skb_reserve(skb, 2);
379 skb_put(desc->skb, desc->datalen);
67d129d1 380 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
d95b39c3 381 desc->skb->ip_summed = CHECKSUM_NONE;
67d129d1
EK		 382 priv->dev->stats.rx_packets++;
383 priv->dev->stats.rx_bytes += desc->datalen;
d95b39c3 384 result = desc->skb;
67d129d1
EK		 385 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
386 CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
d95b39c3 387 desc->skb = skb;
67d129d1 388 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
d95b39c3
MC		 389 CPMAC_SKB_SIZE,
390 DMA_FROM_DEVICE);
391 desc->hw_data = (u32)desc->data_mapping;
392 if (unlikely(netif_msg_pktdata(priv))) {
67d129d1
EK		 393 printk(KERN_DEBUG "%s: received packet:\n",
394 priv->dev->name);
395 cpmac_dump_skb(priv->dev, result);
d95b39c3
MC		 396 }
397 } else {
398 if (netif_msg_rx_err(priv) && net_ratelimit())
399 printk(KERN_WARNING
67d129d1
EK		 400 "%s: low on skbs, dropping packet\n",
401 priv->dev->name);
402 priv->dev->stats.rx_dropped++;
d95b39c3
MC		 403 }
404
405 desc->buflen = CPMAC_SKB_SIZE;
406 desc->dataflags = CPMAC_OWN;
407
408 return result;
409}
410
67d129d1 411static int cpmac_poll(struct napi_struct *napi, int budget)
d95b39c3
MC		 412{
413 struct sk_buff *skb;
414 struct cpmac_desc *desc;
67d129d1
EK		 415 int received = 0;
416 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
d95b39c3
MC		 417
418 spin_lock(&priv->rx_lock);
419 if (unlikely(!priv->rx_head)) {
420 if (netif_msg_rx_err(priv) && net_ratelimit())
421 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
67d129d1
EK		 422 priv->dev->name);
423 netif_rx_complete(priv->dev, napi);
d95b39c3
MC		 424 return 0;
425 }
426
427 desc = priv->rx_head;
67d129d1
EK		 428 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
429 skb = cpmac_rx_one(priv, desc);
d95b39c3
MC		 430 if (likely(skb)) {
431 netif_receive_skb(skb);
432 received++;
433 }
434 desc = desc->next;
435 }
436
437 priv->rx_head = desc;
438 spin_unlock(&priv->rx_lock);
d95b39c3 439 if (unlikely(netif_msg_rx_status(priv)))
67d129d1
EK		 440 printk(KERN_DEBUG "%s: poll processed %d packets\n",
441 priv->dev->name, received);
d95b39c3 442 if (desc->dataflags & CPMAC_OWN) {
67d129d1 443 netif_rx_complete(priv->dev, napi);
d95b39c3
MC		 444 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
445 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
446 return 0;
447 }
448
449 return 1;
450}
451
452static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
453{
454 int queue, len;
455 struct cpmac_desc *desc;
456 struct cpmac_priv *priv = netdev_priv(dev);
457
6cd043d9
MC		 458 if (unlikely(skb_padto(skb, ETH_ZLEN)))
459 return NETDEV_TX_OK;
d95b39c3
MC		 460
461 len = max(skb->len, ETH_ZLEN);
6cd043d9 462 queue = skb->queue_mapping;
d95b39c3
MC		 463#ifdef CONFIG_NETDEVICES_MULTIQUEUE
464 netif_stop_subqueue(dev, queue);
465#else
466 netif_stop_queue(dev);
467#endif
468
469 desc = &priv->desc_ring[queue];
470 if (unlikely(desc->dataflags & CPMAC_OWN)) {
471 if (netif_msg_tx_err(priv) && net_ratelimit())
6cd043d9 472 printk(KERN_WARNING "%s: tx dma ring full\n",
d95b39c3 473 dev->name);
6cd043d9 474 return NETDEV_TX_BUSY;
d95b39c3
MC		 475 }
476
477 spin_lock(&priv->lock);
478 dev->trans_start = jiffies;
479 spin_unlock(&priv->lock);
480 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
481 desc->skb = skb;
482 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
483 DMA_TO_DEVICE);
484 desc->hw_data = (u32)desc->data_mapping;
485 desc->datalen = len;
486 desc->buflen = len;
487 if (unlikely(netif_msg_tx_queued(priv)))
488 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
489 skb->len);
490 if (unlikely(netif_msg_hw(priv)))
491 cpmac_dump_desc(dev, desc);
492 if (unlikely(netif_msg_pktdata(priv)))
493 cpmac_dump_skb(dev, skb);
494 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
495
6cd043d9 496 return NETDEV_TX_OK;
d95b39c3
MC		 497}
498
499static void cpmac_end_xmit(struct net_device *dev, int queue)
500{
501 struct cpmac_desc *desc;
502 struct cpmac_priv *priv = netdev_priv(dev);
503
504 desc = &priv->desc_ring[queue];
505 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
506 if (likely(desc->skb)) {
507 spin_lock(&priv->lock);
508 dev->stats.tx_packets++;
509 dev->stats.tx_bytes += desc->skb->len;
510 spin_unlock(&priv->lock);
511 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
512 DMA_TO_DEVICE);
513
514 if (unlikely(netif_msg_tx_done(priv)))
515 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
516 desc->skb, desc->skb->len);
517
518 dev_kfree_skb_irq(desc->skb);
519 desc->skb = NULL;
520#ifdef CONFIG_NETDEVICES_MULTIQUEUE
521 if (netif_subqueue_stopped(dev, queue))
522 netif_wake_subqueue(dev, queue);
523#else
524 if (netif_queue_stopped(dev))
525 netif_wake_queue(dev);
526#endif
527 } else {
528 if (netif_msg_tx_err(priv) && net_ratelimit())
529 printk(KERN_WARNING
530 "%s: end_xmit: spurious interrupt\n", dev->name);
531#ifdef CONFIG_NETDEVICES_MULTIQUEUE
532 if (netif_subqueue_stopped(dev, queue))
533 netif_wake_subqueue(dev, queue);
534#else
535 if (netif_queue_stopped(dev))
536 netif_wake_queue(dev);
537#endif
538 }
539}
540
541static void cpmac_hw_stop(struct net_device *dev)
542{
543 int i;
544 struct cpmac_priv *priv = netdev_priv(dev);
545 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
546
547 ar7_device_reset(pdata->reset_bit);
548 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
549 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
550 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
551 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
552 for (i = 0; i < 8; i++) {
553 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
554 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
555 }
556 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
557 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
558 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
559 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
560 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
561 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
562}
563
564static void cpmac_hw_start(struct net_device *dev)
565{
566 int i;
567 struct cpmac_priv *priv = netdev_priv(dev);
568 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
569
570 ar7_device_reset(pdata->reset_bit);
571 for (i = 0; i < 8; i++) {
572 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
573 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
574 }
575 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
576
577 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
578 MBP_RXMCAST);
579 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
580 for (i = 0; i < 8; i++)
581 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
582 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
583 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
584 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
585 (dev->dev_addr[3] << 24));
586 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
587 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
588 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
589 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
590 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
591 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
592 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
593 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
594 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
595
596 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
597 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
598 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
599 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
600 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
601 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
602 MAC_FDX);
603}
604
605static void cpmac_clear_rx(struct net_device *dev)
606{
607 struct cpmac_priv *priv = netdev_priv(dev);
608 struct cpmac_desc *desc;
609 int i;
610 if (unlikely(!priv->rx_head))
611 return;
612 desc = priv->rx_head;
613 for (i = 0; i < priv->ring_size; i++) {
614 if ((desc->dataflags & CPMAC_OWN) == 0) {
615 if (netif_msg_rx_err(priv) && net_ratelimit())
616 printk(KERN_WARNING "%s: packet dropped\n",
617 dev->name);
618 if (unlikely(netif_msg_hw(priv)))
619 cpmac_dump_desc(dev, desc);
620 desc->dataflags = CPMAC_OWN;
621 dev->stats.rx_dropped++;
622 }
623 desc = desc->next;
624 }
625}
626
627static void cpmac_clear_tx(struct net_device *dev)
628{
629 struct cpmac_priv *priv = netdev_priv(dev);
630 int i;
631 if (unlikely(!priv->desc_ring))
632 return;
6cd043d9
MC		 633 for (i = 0; i < CPMAC_QUEUES; i++) {
634 priv->desc_ring[i].dataflags = 0;
d95b39c3
MC		 635 if (priv->desc_ring[i].skb) {
636 dev_kfree_skb_any(priv->desc_ring[i].skb);
637 if (netif_subqueue_stopped(dev, i))
638 netif_wake_subqueue(dev, i);
639 }
6cd043d9 640 }
d95b39c3
MC		 641}
642
643static void cpmac_hw_error(struct work_struct *work)
644{
645 struct cpmac_priv *priv =
646 container_of(work, struct cpmac_priv, reset_work);
647
648 spin_lock(&priv->rx_lock);
649 cpmac_clear_rx(priv->dev);
650 spin_unlock(&priv->rx_lock);
651 cpmac_clear_tx(priv->dev);
652 cpmac_hw_start(priv->dev);
67d129d1 653 napi_enable(&priv->napi);
d95b39c3
MC		 654 netif_start_queue(priv->dev);
655}
656
657static irqreturn_t cpmac_irq(int irq, void *dev_id)
658{
659 struct net_device *dev = dev_id;
660 struct cpmac_priv *priv;
661 int queue;
662 u32 status;
663
664 if (!dev)
665 return IRQ_NONE;
666
667 priv = netdev_priv(dev);
668
669 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
670
671 if (unlikely(netif_msg_intr(priv)))
672 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
673 status);
674
675 if (status & MAC_INT_TX)
676 cpmac_end_xmit(dev, (status & 7));
677
678 if (status & MAC_INT_RX) {
679 queue = (status >> 8) & 7;
67d129d1
EK		 680 if (netif_rx_schedule_prep(dev, &priv->napi)) {
681 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
682 __netif_rx_schedule(dev, &priv->napi);
683 }
d95b39c3
MC		 684 }
685
686 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
687
688 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS))) {
689 if (netif_msg_drv(priv) && net_ratelimit())
690 printk(KERN_ERR "%s: hw error, resetting...\n",
691 dev->name);
692 netif_stop_queue(dev);
67d129d1 693 napi_disable(&priv->napi);
d95b39c3
MC		 694 cpmac_hw_stop(dev);
695 schedule_work(&priv->reset_work);
696 if (unlikely(netif_msg_hw(priv)))
697 cpmac_dump_regs(dev);
698 }
699
700 return IRQ_HANDLED;
701}
702
703static void cpmac_tx_timeout(struct net_device *dev)
704{
705 struct cpmac_priv *priv = netdev_priv(dev);
706 int i;
707
708 spin_lock(&priv->lock);
709 dev->stats.tx_errors++;
710 spin_unlock(&priv->lock);
711 if (netif_msg_tx_err(priv) && net_ratelimit())
712 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
713 /*
714 * FIXME: waking up random queue is not the best thing to
715 * do... on the other hand why we got here at all?
716 */
717#ifdef CONFIG_NETDEVICES_MULTIQUEUE
718 for (i = 0; i < CPMAC_QUEUES; i++)
719 if (priv->desc_ring[i].skb) {
6cd043d9 720 priv->desc_ring[i].dataflags = 0;
d95b39c3
MC		 721 dev_kfree_skb_any(priv->desc_ring[i].skb);
722 netif_wake_subqueue(dev, i);
723 break;
724 }
725#else
6cd043d9 726 priv->desc_ring[0].dataflags = 0;
d95b39c3
MC		 727 if (priv->desc_ring[0].skb)
728 dev_kfree_skb_any(priv->desc_ring[0].skb);
729 netif_wake_queue(dev);
730#endif
731}
732
733static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
734{
735 struct cpmac_priv *priv = netdev_priv(dev);
736 if (!(netif_running(dev)))
737 return -EINVAL;
738 if (!priv->phy)
739 return -EINVAL;
740 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
741 (cmd == SIOCSMIIREG))
742 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
743
744 return -EOPNOTSUPP;
745}
746
747static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
748{
749 struct cpmac_priv *priv = netdev_priv(dev);
750
751 if (priv->phy)
752 return phy_ethtool_gset(priv->phy, cmd);
753
754 return -EINVAL;
755}
756
757static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
758{
759 struct cpmac_priv *priv = netdev_priv(dev);
760
761 if (!capable(CAP_NET_ADMIN))
762 return -EPERM;
763
764 if (priv->phy)
765 return phy_ethtool_sset(priv->phy, cmd);
766
767 return -EINVAL;
768}
769
770static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
771{
772 struct cpmac_priv *priv = netdev_priv(dev);
773
774 ring->rx_max_pending = 1024;
775 ring->rx_mini_max_pending = 1;
776 ring->rx_jumbo_max_pending = 1;
777 ring->tx_max_pending = 1;
778
779 ring->rx_pending = priv->ring_size;
780 ring->rx_mini_pending = 1;
781 ring->rx_jumbo_pending = 1;
782 ring->tx_pending = 1;
783}
784
785static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
786{
787 struct cpmac_priv *priv = netdev_priv(dev);
788
6cd043d9 789 if (netif_running(dev))
d95b39c3
MC		 790 return -EBUSY;
791 priv->ring_size = ring->rx_pending;
792 return 0;
793}
794
795static void cpmac_get_drvinfo(struct net_device *dev,
796 struct ethtool_drvinfo *info)
797{
798 strcpy(info->driver, "cpmac");
799 strcpy(info->version, CPMAC_VERSION);
800 info->fw_version[0] = '\0';
801 sprintf(info->bus_info, "%s", "cpmac");
802 info->regdump_len = 0;
803}
804
805static const struct ethtool_ops cpmac_ethtool_ops = {
806 .get_settings = cpmac_get_settings,
807 .set_settings = cpmac_set_settings,
808 .get_drvinfo = cpmac_get_drvinfo,
809 .get_link = ethtool_op_get_link,
810 .get_ringparam = cpmac_get_ringparam,
811 .set_ringparam = cpmac_set_ringparam,
812};
813
814static void cpmac_adjust_link(struct net_device *dev)
815{
816 struct cpmac_priv *priv = netdev_priv(dev);
817 int new_state = 0;
818
819 spin_lock(&priv->lock);
820 if (priv->phy->link) {
821 netif_start_queue(dev);
822 if (priv->phy->duplex != priv->oldduplex) {
823 new_state = 1;
824 priv->oldduplex = priv->phy->duplex;
825 }
826
827 if (priv->phy->speed != priv->oldspeed) {
828 new_state = 1;
829 priv->oldspeed = priv->phy->speed;
830 }
831
832 if (!priv->oldlink) {
833 new_state = 1;
834 priv->oldlink = 1;
835 netif_schedule(dev);
836 }
837 } else if (priv->oldlink) {
838 netif_stop_queue(dev);
839 new_state = 1;
840 priv->oldlink = 0;
841 priv->oldspeed = 0;
842 priv->oldduplex = -1;
843 }
844
845 if (new_state && netif_msg_link(priv) && net_ratelimit())
846 phy_print_status(priv->phy);
847
848 spin_unlock(&priv->lock);
849}
850
b88219f8
EK		 851static int cpmac_link_update(struct net_device *dev,
852 struct fixed_phy_status *status)
853{
854 status->link = 1;
855 status->speed = 100;
856 status->duplex = 1;
857 return 0;
858}
859
d95b39c3
MC		 860static int cpmac_open(struct net_device *dev)
861{
862 int i, size, res;
863 struct cpmac_priv *priv = netdev_priv(dev);
864 struct resource *mem;
865 struct cpmac_desc *desc;
866 struct sk_buff *skb;
867
d95b39c3
MC		 868 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
869 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
870 if (netif_msg_drv(priv))
871 printk(KERN_ERR "%s: failed to request registers\n",
872 dev->name);
873 res = -ENXIO;
874 goto fail_reserve;
875 }
876
877 priv->regs = ioremap(mem->start, mem->end - mem->start);
878 if (!priv->regs) {
879 if (netif_msg_drv(priv))
880 printk(KERN_ERR "%s: failed to remap registers\n",
881 dev->name);
882 res = -ENXIO;
883 goto fail_remap;
884 }
885
886 size = priv->ring_size + CPMAC_QUEUES;
887 priv->desc_ring = dma_alloc_coherent(&dev->dev,
888 sizeof(struct cpmac_desc) * size,
889 &priv->dma_ring,
890 GFP_KERNEL);
891 if (!priv->desc_ring) {
892 res = -ENOMEM;
893 goto fail_alloc;
894 }
895
896 for (i = 0; i < size; i++)
897 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
898
899 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
900 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
901 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
902 if (unlikely(!skb)) {
903 res = -ENOMEM;
904 goto fail_desc;
905 }
906 skb_reserve(skb, 2);
907 desc->skb = skb;
908 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
909 CPMAC_SKB_SIZE,
910 DMA_FROM_DEVICE);
911 desc->hw_data = (u32)desc->data_mapping;
912 desc->buflen = CPMAC_SKB_SIZE;
913 desc->dataflags = CPMAC_OWN;
914 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
915 desc->hw_next = (u32)desc->next->mapping;
916 }
917
918 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
919 dev->name, dev))) {
920 if (netif_msg_drv(priv))
921 printk(KERN_ERR "%s: failed to obtain irq\n",
922 dev->name);
923 goto fail_irq;
924 }
925
926 INIT_WORK(&priv->reset_work, cpmac_hw_error);
927 cpmac_hw_start(dev);
928
67d129d1 929 napi_enable(&priv->napi);
d95b39c3
MC		 930 priv->phy->state = PHY_CHANGELINK;
931 phy_start(priv->phy);
932
933 return 0;
934
935fail_irq:
936fail_desc:
937 for (i = 0; i < priv->ring_size; i++) {
938 if (priv->rx_head[i].skb) {
939 dma_unmap_single(&dev->dev,
940 priv->rx_head[i].data_mapping,
941 CPMAC_SKB_SIZE,
942 DMA_FROM_DEVICE);
943 kfree_skb(priv->rx_head[i].skb);
944 }
945 }
946fail_alloc:
947 kfree(priv->desc_ring);
948 iounmap(priv->regs);
949
950fail_remap:
951 release_mem_region(mem->start, mem->end - mem->start);
952
953fail_reserve:
d95b39c3
MC		 954 return res;
955}
956
957static int cpmac_stop(struct net_device *dev)
958{
959 int i;
960 struct cpmac_priv *priv = netdev_priv(dev);
961 struct resource *mem;
962
963 netif_stop_queue(dev);
964
965 cancel_work_sync(&priv->reset_work);
67d129d1 966 napi_disable(&priv->napi);
d95b39c3 967 phy_stop(priv->phy);
d95b39c3
MC		 968
969 cpmac_hw_stop(dev);
970
971 for (i = 0; i < 8; i++)
972 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
973 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
974 cpmac_write(priv->regs, CPMAC_MBP, 0);
975
976 free_irq(dev->irq, dev);
977 iounmap(priv->regs);
978 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
979 release_mem_region(mem->start, mem->end - mem->start);
980 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
981 for (i = 0; i < priv->ring_size; i++) {
982 if (priv->rx_head[i].skb) {
983 dma_unmap_single(&dev->dev,
984 priv->rx_head[i].data_mapping,
985 CPMAC_SKB_SIZE,
986 DMA_FROM_DEVICE);
987 kfree_skb(priv->rx_head[i].skb);
988 }
989 }
990
991 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
992 (CPMAC_QUEUES + priv->ring_size),
993 priv->desc_ring, priv->dma_ring);
994 return 0;
995}
996
997static int external_switch;
998
999static int __devinit cpmac_probe(struct platform_device *pdev)
1000{
b88219f8 1001 int rc, phy_id, i;
d95b39c3
MC		 1002 struct resource *mem;
1003 struct cpmac_priv *priv;
1004 struct net_device *dev;
1005 struct plat_cpmac_data *pdata;
b88219f8 1006 struct fixed_info *fixed_phy;
df523b5c 1007 DECLARE_MAC_BUF(mac);
d95b39c3
MC		 1008
1009 pdata = pdev->dev.platform_data;
1010
1011 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1012 if (!(pdata->phy_mask & (1 << phy_id)))
1013 continue;
1014 if (!cpmac_mii.phy_map[phy_id])
1015 continue;
1016 break;
1017 }
1018
1019 if (phy_id == PHY_MAX_ADDR) {
1020 if (external_switch || dumb_switch)
1021 phy_id = 0;
1022 else {
1023 printk(KERN_ERR "cpmac: no PHY present\n");
1024 return -ENODEV;
1025 }
1026 }
1027
1028 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1029
1030 if (!dev) {
1031 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1032 return -ENOMEM;
1033 }
1034
1035 platform_set_drvdata(pdev, dev);
1036 priv = netdev_priv(dev);
1037
1038 priv->pdev = pdev;
1039 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1040 if (!mem) {
1041 rc = -ENODEV;
1042 goto fail;
1043 }
1044
1045 dev->irq = platform_get_irq_byname(pdev, "irq");
1046
1047 dev->open = cpmac_open;
1048 dev->stop = cpmac_stop;
1049 dev->set_config = cpmac_config;
1050 dev->hard_start_xmit = cpmac_start_xmit;
1051 dev->do_ioctl = cpmac_ioctl;
1052 dev->set_multicast_list = cpmac_set_multicast_list;
1053 dev->tx_timeout = cpmac_tx_timeout;
1054 dev->ethtool_ops = &cpmac_ethtool_ops;
d95b39c3
MC		 1055 dev->features |= NETIF_F_MULTI_QUEUE;
1056
67d129d1
EK		 1057 netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1058
d95b39c3
MC		 1059 spin_lock_init(&priv->lock);
1060 spin_lock_init(&priv->rx_lock);
1061 priv->dev = dev;
1062 priv->ring_size = 64;
1063 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1064 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
b88219f8 1065
d95b39c3 1066 if (phy_id == 31) {
b88219f8
EK		 1067 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, cpmac_mii.id,
1068 phy_id);
1069 } else {
1070 /* Let's try to get a free fixed phy... */
1071 for (i = 0; i < MAX_PHY_AMNT; i++) {
1072 fixed_phy = fixed_mdio_get_phydev(i);
1073 if (!fixed_phy)
1074 continue;
1075 if (!fixed_phy->phydev->attached_dev) {
1076 strncpy(priv->phy_name,
1077 fixed_phy->phydev->dev.bus_id,
1078 BUS_ID_SIZE);
1079 fixed_mdio_set_link_update(fixed_phy->phydev,
1080 &cpmac_link_update);
1081 goto phy_found;
1082 }
1083 }
1084 if (netif_msg_drv(priv))
1085 printk(KERN_ERR "%s: Could not find fixed PHY\n",
1086 dev->name);
1087 rc = -ENODEV;
1088 goto fail;
1089 }
1090
1091phy_found:
1092 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
1093 PHY_INTERFACE_MODE_MII);
1094 if (IS_ERR(priv->phy)) {
1095 if (netif_msg_drv(priv))
1096 printk(KERN_ERR "%s: Could not attach to PHY\n",
1097 dev->name);
1098 return PTR_ERR(priv->phy);
1099 }
d95b39c3
MC		 1100
1101 if ((rc = register_netdev(dev))) {
1102 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1103 dev->name);
1104 goto fail;
1105 }
1106
1107 if (netif_msg_probe(priv)) {
1108 printk(KERN_INFO
df523b5c
EK		 1109 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1110 "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1111 priv->phy_name, print_mac(mac, dev->dev_addr));
d95b39c3
MC		 1112 }
1113 return 0;
1114
1115fail:
1116 free_netdev(dev);
1117 return rc;
1118}
1119
1120static int __devexit cpmac_remove(struct platform_device *pdev)
1121{
1122 struct net_device *dev = platform_get_drvdata(pdev);
1123 unregister_netdev(dev);
1124 free_netdev(dev);
1125 return 0;
1126}
1127
1128static struct platform_driver cpmac_driver = {
1129 .driver.name = "cpmac",
1130 .probe = cpmac_probe,
1131 .remove = __devexit_p(cpmac_remove),
1132};
1133
1134int __devinit cpmac_init(void)
1135{
1136 u32 mask;
1137 int i, res;
1138
1139 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1140
1141 if (!cpmac_mii.priv) {
1142 printk(KERN_ERR "Can't ioremap mdio registers\n");
1143 return -ENXIO;
1144 }
1145
1146#warning FIXME: unhardcode gpio&reset bits
1147 ar7_gpio_disable(26);
1148 ar7_gpio_disable(27);
1149 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1150 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1151 ar7_device_reset(AR7_RESET_BIT_EPHY);
1152
1153 cpmac_mii.reset(&cpmac_mii);
1154
1155 for (i = 0; i < 300000; i++)
1156 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1157 break;
1158 else
1159 cpu_relax();
1160
1161 mask &= 0x7fffffff;
1162 if (mask & (mask - 1)) {
1163 external_switch = 1;
1164 mask = 0;
1165 }
1166
1167 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1168
1169 res = mdiobus_register(&cpmac_mii);
1170 if (res)
1171 goto fail_mii;
1172
1173 res = platform_driver_register(&cpmac_driver);
1174 if (res)
1175 goto fail_cpmac;
1176
1177 return 0;
1178
1179fail_cpmac:
1180 mdiobus_unregister(&cpmac_mii);
1181
1182fail_mii:
1183 iounmap(cpmac_mii.priv);
1184
1185 return res;
1186}
1187
1188void __devexit cpmac_exit(void)
1189{
1190 platform_driver_unregister(&cpmac_driver);
1191 mdiobus_unregister(&cpmac_mii);
1192 iounmap(cpmac_mii.priv);
1193}
1194
1195module_init(cpmac_init);
1196module_exit(cpmac_exit);
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