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1 | /* |
2 | * Copyright (C) 1999 - 2010 Intel Corporation. | |
3 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/interrupt.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/sched.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/skbuff.h> | |
31 | #include <linux/can.h> | |
32 | #include <linux/can/dev.h> | |
33 | #include <linux/can/error.h> | |
34 | ||
35 | #define MAX_MSG_OBJ 32 | |
36 | #define MSG_OBJ_RX 0 /* The receive message object flag. */ | |
37 | #define MSG_OBJ_TX 1 /* The transmit message object flag. */ | |
38 | ||
39 | #define ENABLE 1 /* The enable flag */ | |
40 | #define DISABLE 0 /* The disable flag */ | |
41 | #define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */ | |
42 | #define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */ | |
43 | #define CAN_CTRL_IE_SIE_EIE 0x000e | |
44 | #define CAN_CTRL_CCE 0x0040 | |
45 | #define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */ | |
46 | #define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */ | |
47 | #define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */ | |
48 | #define CAN_CMASK_RX_TX_SET 0x00f3 | |
49 | #define CAN_CMASK_RX_TX_GET 0x0073 | |
50 | #define CAN_CMASK_ALL 0xff | |
51 | #define CAN_CMASK_RDWR 0x80 | |
52 | #define CAN_CMASK_ARB 0x20 | |
53 | #define CAN_CMASK_CTRL 0x10 | |
54 | #define CAN_CMASK_MASK 0x40 | |
55 | #define CAN_CMASK_NEWDAT 0x04 | |
56 | #define CAN_CMASK_CLRINTPND 0x08 | |
57 | ||
58 | #define CAN_IF_MCONT_NEWDAT 0x8000 | |
59 | #define CAN_IF_MCONT_INTPND 0x2000 | |
60 | #define CAN_IF_MCONT_UMASK 0x1000 | |
61 | #define CAN_IF_MCONT_TXIE 0x0800 | |
62 | #define CAN_IF_MCONT_RXIE 0x0400 | |
63 | #define CAN_IF_MCONT_RMTEN 0x0200 | |
64 | #define CAN_IF_MCONT_TXRQXT 0x0100 | |
65 | #define CAN_IF_MCONT_EOB 0x0080 | |
66 | #define CAN_IF_MCONT_DLC 0x000f | |
67 | #define CAN_IF_MCONT_MSGLOST 0x4000 | |
68 | #define CAN_MASK2_MDIR_MXTD 0xc000 | |
69 | #define CAN_ID2_DIR 0x2000 | |
70 | #define CAN_ID_MSGVAL 0x8000 | |
71 | ||
72 | #define CAN_STATUS_INT 0x8000 | |
73 | #define CAN_IF_CREQ_BUSY 0x8000 | |
74 | #define CAN_ID2_XTD 0x4000 | |
75 | ||
76 | #define CAN_REC 0x00007f00 | |
77 | #define CAN_TEC 0x000000ff | |
78 | ||
79 | #define PCH_RX_OK 0x00000010 | |
80 | #define PCH_TX_OK 0x00000008 | |
81 | #define PCH_BUS_OFF 0x00000080 | |
82 | #define PCH_EWARN 0x00000040 | |
83 | #define PCH_EPASSIV 0x00000020 | |
84 | #define PCH_LEC0 0x00000001 | |
85 | #define PCH_LEC1 0x00000002 | |
86 | #define PCH_LEC2 0x00000004 | |
87 | #define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2) | |
88 | #define PCH_STUF_ERR PCH_LEC0 | |
89 | #define PCH_FORM_ERR PCH_LEC1 | |
90 | #define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1) | |
91 | #define PCH_BIT1_ERR PCH_LEC2 | |
92 | #define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2) | |
93 | #define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2) | |
94 | ||
95 | /* bit position of certain controller bits. */ | |
96 | #define BIT_BITT_BRP 0 | |
97 | #define BIT_BITT_SJW 6 | |
98 | #define BIT_BITT_TSEG1 8 | |
99 | #define BIT_BITT_TSEG2 12 | |
100 | #define BIT_IF1_MCONT_RXIE 10 | |
101 | #define BIT_IF2_MCONT_TXIE 11 | |
102 | #define BIT_BRPE_BRPE 6 | |
103 | #define BIT_ES_TXERRCNT 0 | |
104 | #define BIT_ES_RXERRCNT 8 | |
105 | #define MSK_BITT_BRP 0x3f | |
106 | #define MSK_BITT_SJW 0xc0 | |
107 | #define MSK_BITT_TSEG1 0xf00 | |
108 | #define MSK_BITT_TSEG2 0x7000 | |
109 | #define MSK_BRPE_BRPE 0x3c0 | |
110 | #define MSK_BRPE_GET 0x0f | |
111 | #define MSK_CTRL_IE_SIE_EIE 0x07 | |
112 | #define MSK_MCONT_TXIE 0x08 | |
113 | #define MSK_MCONT_RXIE 0x10 | |
114 | #define PCH_CAN_NO_TX_BUFF 1 | |
115 | #define COUNTER_LIMIT 10 | |
116 | ||
117 | #define PCH_CAN_CLK 50000000 /* 50MHz */ | |
118 | ||
119 | /* Define the number of message object. | |
120 | * PCH CAN communications are done via Message RAM. | |
121 | * The Message RAM consists of 32 message objects. */ | |
122 | #define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/ | |
123 | #define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/ | |
124 | #define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM) | |
125 | ||
126 | #define PCH_FIFO_THRESH 16 | |
127 | ||
128 | enum pch_can_mode { | |
129 | PCH_CAN_ENABLE, | |
130 | PCH_CAN_DISABLE, | |
131 | PCH_CAN_ALL, | |
132 | PCH_CAN_NONE, | |
133 | PCH_CAN_STOP, | |
134 | PCH_CAN_RUN | |
135 | }; | |
136 | ||
137 | struct pch_can_regs { | |
138 | u32 cont; | |
139 | u32 stat; | |
140 | u32 errc; | |
141 | u32 bitt; | |
142 | u32 intr; | |
143 | u32 opt; | |
144 | u32 brpe; | |
145 | u32 reserve1; | |
146 | u32 if1_creq; | |
147 | u32 if1_cmask; | |
148 | u32 if1_mask1; | |
149 | u32 if1_mask2; | |
150 | u32 if1_id1; | |
151 | u32 if1_id2; | |
152 | u32 if1_mcont; | |
153 | u32 if1_dataa1; | |
154 | u32 if1_dataa2; | |
155 | u32 if1_datab1; | |
156 | u32 if1_datab2; | |
157 | u32 reserve2; | |
158 | u32 reserve3[12]; | |
159 | u32 if2_creq; | |
160 | u32 if2_cmask; | |
161 | u32 if2_mask1; | |
162 | u32 if2_mask2; | |
163 | u32 if2_id1; | |
164 | u32 if2_id2; | |
165 | u32 if2_mcont; | |
166 | u32 if2_dataa1; | |
167 | u32 if2_dataa2; | |
168 | u32 if2_datab1; | |
169 | u32 if2_datab2; | |
170 | u32 reserve4; | |
171 | u32 reserve5[20]; | |
172 | u32 treq1; | |
173 | u32 treq2; | |
174 | u32 reserve6[2]; | |
175 | u32 reserve7[56]; | |
176 | u32 reserve8[3]; | |
177 | u32 srst; | |
178 | }; | |
179 | ||
180 | struct pch_can_priv { | |
181 | struct can_priv can; | |
182 | unsigned int can_num; | |
183 | struct pci_dev *dev; | |
184 | unsigned int tx_enable[MAX_MSG_OBJ]; | |
185 | unsigned int rx_enable[MAX_MSG_OBJ]; | |
186 | unsigned int rx_link[MAX_MSG_OBJ]; | |
187 | unsigned int int_enables; | |
188 | unsigned int int_stat; | |
189 | struct net_device *ndev; | |
190 | spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/ | |
191 | unsigned int msg_obj[MAX_MSG_OBJ]; | |
192 | struct pch_can_regs __iomem *regs; | |
193 | struct napi_struct napi; | |
194 | unsigned int tx_obj; /* Point next Tx Obj index */ | |
195 | unsigned int use_msi; | |
196 | }; | |
197 | ||
198 | static struct can_bittiming_const pch_can_bittiming_const = { | |
199 | .name = KBUILD_MODNAME, | |
200 | .tseg1_min = 1, | |
201 | .tseg1_max = 16, | |
202 | .tseg2_min = 1, | |
203 | .tseg2_max = 8, | |
204 | .sjw_max = 4, | |
205 | .brp_min = 1, | |
206 | .brp_max = 1024, /* 6bit + extended 4bit */ | |
207 | .brp_inc = 1, | |
208 | }; | |
209 | ||
210 | static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = { | |
211 | {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,}, | |
212 | {0,} | |
213 | }; | |
214 | MODULE_DEVICE_TABLE(pci, pch_pci_tbl); | |
215 | ||
216 | static inline void pch_can_bit_set(u32 *addr, u32 mask) | |
217 | { | |
218 | iowrite32(ioread32(addr) | mask, addr); | |
219 | } | |
220 | ||
221 | static inline void pch_can_bit_clear(u32 *addr, u32 mask) | |
222 | { | |
223 | iowrite32(ioread32(addr) & ~mask, addr); | |
224 | } | |
225 | ||
226 | static void pch_can_set_run_mode(struct pch_can_priv *priv, | |
227 | enum pch_can_mode mode) | |
228 | { | |
229 | switch (mode) { | |
230 | case PCH_CAN_RUN: | |
231 | pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT); | |
232 | break; | |
233 | ||
234 | case PCH_CAN_STOP: | |
235 | pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT); | |
236 | break; | |
237 | ||
238 | default: | |
239 | dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__); | |
240 | break; | |
241 | } | |
242 | } | |
243 | ||
244 | static void pch_can_set_optmode(struct pch_can_priv *priv) | |
245 | { | |
246 | u32 reg_val = ioread32(&priv->regs->opt); | |
247 | ||
248 | if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) | |
249 | reg_val |= CAN_OPT_SILENT; | |
250 | ||
251 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) | |
252 | reg_val |= CAN_OPT_LBACK; | |
253 | ||
254 | pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT); | |
255 | iowrite32(reg_val, &priv->regs->opt); | |
256 | } | |
257 | ||
258 | static void pch_can_set_int_custom(struct pch_can_priv *priv) | |
259 | { | |
260 | /* Clearing the IE, SIE and EIE bits of Can control register. */ | |
261 | pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); | |
262 | ||
263 | /* Appropriately setting them. */ | |
264 | pch_can_bit_set(&priv->regs->cont, | |
265 | ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1)); | |
266 | } | |
267 | ||
268 | /* This function retrieves interrupt enabled for the CAN device. */ | |
269 | static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables) | |
270 | { | |
271 | /* Obtaining the status of IE, SIE and EIE interrupt bits. */ | |
272 | *enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1); | |
273 | } | |
274 | ||
275 | static void pch_can_set_int_enables(struct pch_can_priv *priv, | |
276 | enum pch_can_mode interrupt_no) | |
277 | { | |
278 | switch (interrupt_no) { | |
279 | case PCH_CAN_ENABLE: | |
280 | pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE); | |
281 | break; | |
282 | ||
283 | case PCH_CAN_DISABLE: | |
284 | pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE); | |
285 | break; | |
286 | ||
287 | case PCH_CAN_ALL: | |
288 | pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); | |
289 | break; | |
290 | ||
291 | case PCH_CAN_NONE: | |
292 | pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE); | |
293 | break; | |
294 | ||
295 | default: | |
296 | dev_err(&priv->ndev->dev, "Invalid interrupt number.\n"); | |
297 | break; | |
298 | } | |
299 | } | |
300 | ||
301 | static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num) | |
302 | { | |
303 | u32 counter = COUNTER_LIMIT; | |
304 | u32 ifx_creq; | |
305 | ||
306 | iowrite32(num, creq_addr); | |
307 | while (counter) { | |
308 | ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY; | |
309 | if (!ifx_creq) | |
310 | break; | |
311 | counter--; | |
312 | udelay(1); | |
313 | } | |
314 | if (!counter) | |
315 | pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__); | |
316 | } | |
317 | ||
318 | static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num, | |
319 | u32 set) | |
320 | { | |
321 | unsigned long flags; | |
322 | ||
323 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
324 | /* Reading the receive buffer data from RAM to Interface1 registers */ | |
325 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
326 | pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); | |
327 | ||
328 | /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */ | |
329 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
330 | &priv->regs->if1_cmask); | |
331 | ||
332 | if (set == ENABLE) { | |
333 | /* Setting the MsgVal and RxIE bits */ | |
334 | pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE); | |
335 | pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL); | |
336 | ||
337 | } else if (set == DISABLE) { | |
338 | /* Resetting the MsgVal and RxIE bits */ | |
339 | pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE); | |
340 | pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL); | |
341 | } | |
342 | ||
343 | pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); | |
344 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
345 | } | |
346 | ||
347 | static void pch_can_rx_enable_all(struct pch_can_priv *priv) | |
348 | { | |
349 | int i; | |
350 | ||
351 | /* Traversing to obtain the object configured as receivers. */ | |
352 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
353 | if (priv->msg_obj[i] == MSG_OBJ_RX) | |
354 | pch_can_set_rx_enable(priv, i + 1, ENABLE); | |
355 | } | |
356 | } | |
357 | ||
358 | static void pch_can_rx_disable_all(struct pch_can_priv *priv) | |
359 | { | |
360 | int i; | |
361 | ||
362 | /* Traversing to obtain the object configured as receivers. */ | |
363 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
364 | if (priv->msg_obj[i] == MSG_OBJ_RX) | |
365 | pch_can_set_rx_enable(priv, i + 1, DISABLE); | |
366 | } | |
367 | } | |
368 | ||
369 | static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num, | |
370 | u32 set) | |
371 | { | |
372 | unsigned long flags; | |
373 | ||
374 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
375 | /* Reading the Msg buffer from Message RAM to Interface2 registers. */ | |
376 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); | |
377 | pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); | |
378 | ||
379 | /* Setting the IF2CMASK register for accessing the | |
380 | MsgVal and TxIE bits */ | |
381 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
382 | &priv->regs->if2_cmask); | |
383 | ||
384 | if (set == ENABLE) { | |
385 | /* Setting the MsgVal and TxIE bits */ | |
386 | pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE); | |
387 | pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL); | |
388 | } else if (set == DISABLE) { | |
389 | /* Resetting the MsgVal and TxIE bits. */ | |
390 | pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE); | |
391 | pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL); | |
392 | } | |
393 | ||
394 | pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); | |
395 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
396 | } | |
397 | ||
398 | static void pch_can_tx_enable_all(struct pch_can_priv *priv) | |
399 | { | |
400 | int i; | |
401 | ||
402 | /* Traversing to obtain the object configured as transmit object. */ | |
403 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
404 | if (priv->msg_obj[i] == MSG_OBJ_TX) | |
405 | pch_can_set_tx_enable(priv, i + 1, ENABLE); | |
406 | } | |
407 | } | |
408 | ||
409 | static void pch_can_tx_disable_all(struct pch_can_priv *priv) | |
410 | { | |
411 | int i; | |
412 | ||
413 | /* Traversing to obtain the object configured as transmit object. */ | |
414 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
415 | if (priv->msg_obj[i] == MSG_OBJ_TX) | |
416 | pch_can_set_tx_enable(priv, i + 1, DISABLE); | |
417 | } | |
418 | } | |
419 | ||
420 | static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num, | |
421 | u32 *enable) | |
422 | { | |
423 | unsigned long flags; | |
424 | ||
425 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
426 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
427 | pch_can_check_if_busy(&priv->regs->if1_creq, buff_num); | |
428 | ||
429 | if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) && | |
430 | ((ioread32(&priv->regs->if1_mcont)) & | |
431 | CAN_IF_MCONT_RXIE)) | |
432 | *enable = ENABLE; | |
433 | else | |
434 | *enable = DISABLE; | |
435 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
436 | } | |
437 | ||
438 | static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num, | |
439 | u32 *enable) | |
440 | { | |
441 | unsigned long flags; | |
442 | ||
443 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
444 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); | |
445 | pch_can_check_if_busy(&priv->regs->if2_creq, buff_num); | |
446 | ||
447 | if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) && | |
448 | ((ioread32(&priv->regs->if2_mcont)) & | |
449 | CAN_IF_MCONT_TXIE)) { | |
450 | *enable = ENABLE; | |
451 | } else { | |
452 | *enable = DISABLE; | |
453 | } | |
454 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
455 | } | |
456 | ||
457 | static int pch_can_int_pending(struct pch_can_priv *priv) | |
458 | { | |
459 | return ioread32(&priv->regs->intr) & 0xffff; | |
460 | } | |
461 | ||
462 | static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv, | |
463 | u32 buffer_num, u32 set) | |
464 | { | |
465 | unsigned long flags; | |
466 | ||
467 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
468 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
469 | pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); | |
470 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask); | |
471 | if (set == ENABLE) | |
472 | pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB); | |
473 | else | |
474 | pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB); | |
475 | ||
476 | pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); | |
477 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
478 | } | |
479 | ||
480 | static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv, | |
481 | u32 buffer_num, u32 *link) | |
482 | { | |
483 | unsigned long flags; | |
484 | ||
485 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
486 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
487 | pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num); | |
488 | ||
489 | if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB) | |
490 | *link = DISABLE; | |
491 | else | |
492 | *link = ENABLE; | |
493 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
494 | } | |
495 | ||
496 | static void pch_can_clear_buffers(struct pch_can_priv *priv) | |
497 | { | |
498 | int i; | |
499 | ||
500 | for (i = 0; i < PCH_RX_OBJ_NUM; i++) { | |
501 | iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask); | |
502 | iowrite32(0xffff, &priv->regs->if1_mask1); | |
503 | iowrite32(0xffff, &priv->regs->if1_mask2); | |
504 | iowrite32(0x0, &priv->regs->if1_id1); | |
505 | iowrite32(0x0, &priv->regs->if1_id2); | |
506 | iowrite32(0x0, &priv->regs->if1_mcont); | |
507 | iowrite32(0x0, &priv->regs->if1_dataa1); | |
508 | iowrite32(0x0, &priv->regs->if1_dataa2); | |
509 | iowrite32(0x0, &priv->regs->if1_datab1); | |
510 | iowrite32(0x0, &priv->regs->if1_datab2); | |
511 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | | |
512 | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
513 | &priv->regs->if1_cmask); | |
514 | pch_can_check_if_busy(&priv->regs->if1_creq, i+1); | |
515 | } | |
516 | ||
517 | for (i = i; i < PCH_OBJ_NUM; i++) { | |
518 | iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask); | |
519 | iowrite32(0xffff, &priv->regs->if2_mask1); | |
520 | iowrite32(0xffff, &priv->regs->if2_mask2); | |
521 | iowrite32(0x0, &priv->regs->if2_id1); | |
522 | iowrite32(0x0, &priv->regs->if2_id2); | |
523 | iowrite32(0x0, &priv->regs->if2_mcont); | |
524 | iowrite32(0x0, &priv->regs->if2_dataa1); | |
525 | iowrite32(0x0, &priv->regs->if2_dataa2); | |
526 | iowrite32(0x0, &priv->regs->if2_datab1); | |
527 | iowrite32(0x0, &priv->regs->if2_datab2); | |
528 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | | |
529 | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
530 | &priv->regs->if2_cmask); | |
531 | pch_can_check_if_busy(&priv->regs->if2_creq, i+1); | |
532 | } | |
533 | } | |
534 | ||
535 | static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv) | |
536 | { | |
537 | int i; | |
538 | unsigned long flags; | |
539 | ||
540 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
541 | ||
542 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
543 | if (priv->msg_obj[i] == MSG_OBJ_RX) { | |
544 | iowrite32(CAN_CMASK_RX_TX_GET, | |
545 | &priv->regs->if1_cmask); | |
546 | pch_can_check_if_busy(&priv->regs->if1_creq, i+1); | |
547 | ||
548 | iowrite32(0x0, &priv->regs->if1_id1); | |
549 | iowrite32(0x0, &priv->regs->if1_id2); | |
550 | ||
551 | pch_can_bit_set(&priv->regs->if1_mcont, | |
552 | CAN_IF_MCONT_UMASK); | |
553 | ||
554 | /* Set FIFO mode set to 0 except last Rx Obj*/ | |
555 | pch_can_bit_clear(&priv->regs->if1_mcont, | |
556 | CAN_IF_MCONT_EOB); | |
557 | /* In case FIFO mode, Last EoB of Rx Obj must be 1 */ | |
558 | if (i == (PCH_RX_OBJ_NUM - 1)) | |
559 | pch_can_bit_set(&priv->regs->if1_mcont, | |
560 | CAN_IF_MCONT_EOB); | |
561 | ||
562 | iowrite32(0, &priv->regs->if1_mask1); | |
563 | pch_can_bit_clear(&priv->regs->if1_mask2, | |
564 | 0x1fff | CAN_MASK2_MDIR_MXTD); | |
565 | ||
566 | /* Setting CMASK for writing */ | |
567 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | | |
568 | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
569 | &priv->regs->if1_cmask); | |
570 | ||
571 | pch_can_check_if_busy(&priv->regs->if1_creq, i+1); | |
572 | } else if (priv->msg_obj[i] == MSG_OBJ_TX) { | |
573 | iowrite32(CAN_CMASK_RX_TX_GET, | |
574 | &priv->regs->if2_cmask); | |
575 | pch_can_check_if_busy(&priv->regs->if2_creq, i+1); | |
576 | ||
577 | /* Resetting DIR bit for reception */ | |
578 | iowrite32(0x0, &priv->regs->if2_id1); | |
579 | iowrite32(0x0, &priv->regs->if2_id2); | |
580 | pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR); | |
581 | ||
582 | /* Setting EOB bit for transmitter */ | |
583 | iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont); | |
584 | ||
585 | pch_can_bit_set(&priv->regs->if2_mcont, | |
586 | CAN_IF_MCONT_UMASK); | |
587 | ||
588 | iowrite32(0, &priv->regs->if2_mask1); | |
589 | pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff); | |
590 | ||
591 | /* Setting CMASK for writing */ | |
592 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | | |
593 | CAN_CMASK_ARB | CAN_CMASK_CTRL, | |
594 | &priv->regs->if2_cmask); | |
595 | ||
596 | pch_can_check_if_busy(&priv->regs->if2_creq, i+1); | |
597 | } | |
598 | } | |
599 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
600 | } | |
601 | ||
602 | static void pch_can_init(struct pch_can_priv *priv) | |
603 | { | |
604 | /* Stopping the Can device. */ | |
605 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
606 | ||
607 | /* Clearing all the message object buffers. */ | |
608 | pch_can_clear_buffers(priv); | |
609 | ||
610 | /* Configuring the respective message object as either rx/tx object. */ | |
611 | pch_can_config_rx_tx_buffers(priv); | |
612 | ||
613 | /* Enabling the interrupts. */ | |
614 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
615 | } | |
616 | ||
617 | static void pch_can_release(struct pch_can_priv *priv) | |
618 | { | |
619 | /* Stooping the CAN device. */ | |
620 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
621 | ||
622 | /* Disabling the interrupts. */ | |
623 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
624 | ||
625 | /* Disabling all the receive object. */ | |
626 | pch_can_rx_disable_all(priv); | |
627 | ||
628 | /* Disabling all the transmit object. */ | |
629 | pch_can_tx_disable_all(priv); | |
630 | } | |
631 | ||
632 | /* This function clears interrupt(s) from the CAN device. */ | |
633 | static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) | |
634 | { | |
635 | if (mask == CAN_STATUS_INT) { | |
636 | ioread32(&priv->regs->stat); | |
637 | return; | |
638 | } | |
639 | ||
640 | /* Clear interrupt for transmit object */ | |
641 | if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) { | |
642 | /* Setting CMASK for clearing interrupts for | |
643 | frame transmission. */ | |
644 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB, | |
645 | &priv->regs->if2_cmask); | |
646 | ||
647 | /* Resetting the ID registers. */ | |
648 | pch_can_bit_set(&priv->regs->if2_id2, | |
649 | CAN_ID2_DIR | (0x7ff << 2)); | |
650 | iowrite32(0x0, &priv->regs->if2_id1); | |
651 | ||
652 | /* Claring NewDat, TxRqst & IntPnd */ | |
653 | pch_can_bit_clear(&priv->regs->if2_mcont, | |
654 | CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND | | |
655 | CAN_IF_MCONT_TXRQXT); | |
656 | pch_can_check_if_busy(&priv->regs->if2_creq, mask); | |
657 | } else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) { | |
658 | /* Setting CMASK for clearing the reception interrupts. */ | |
659 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB, | |
660 | &priv->regs->if1_cmask); | |
661 | ||
662 | /* Clearing the Dir bit. */ | |
663 | pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR); | |
664 | ||
665 | /* Clearing NewDat & IntPnd */ | |
666 | pch_can_bit_clear(&priv->regs->if1_mcont, | |
667 | CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND); | |
668 | ||
669 | pch_can_check_if_busy(&priv->regs->if1_creq, mask); | |
670 | } | |
671 | } | |
672 | ||
673 | static int pch_can_get_buffer_status(struct pch_can_priv *priv) | |
674 | { | |
675 | return (ioread32(&priv->regs->treq1) & 0xffff) | | |
676 | ((ioread32(&priv->regs->treq2) & 0xffff) << 16); | |
677 | } | |
678 | ||
679 | static void pch_can_reset(struct pch_can_priv *priv) | |
680 | { | |
681 | /* write to sw reset register */ | |
682 | iowrite32(1, &priv->regs->srst); | |
683 | iowrite32(0, &priv->regs->srst); | |
684 | } | |
685 | ||
686 | static void pch_can_error(struct net_device *ndev, u32 status) | |
687 | { | |
688 | struct sk_buff *skb; | |
689 | struct pch_can_priv *priv = netdev_priv(ndev); | |
690 | struct can_frame *cf; | |
691 | u32 errc; | |
692 | struct net_device_stats *stats = &(priv->ndev->stats); | |
693 | enum can_state state = priv->can.state; | |
694 | ||
695 | skb = alloc_can_err_skb(ndev, &cf); | |
696 | if (!skb) | |
697 | return; | |
698 | ||
699 | if (status & PCH_BUS_OFF) { | |
700 | pch_can_tx_disable_all(priv); | |
701 | pch_can_rx_disable_all(priv); | |
702 | state = CAN_STATE_BUS_OFF; | |
703 | cf->can_id |= CAN_ERR_BUSOFF; | |
704 | can_bus_off(ndev); | |
705 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
706 | dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); | |
707 | } | |
708 | ||
709 | /* Warning interrupt. */ | |
710 | if (status & PCH_EWARN) { | |
711 | state = CAN_STATE_ERROR_WARNING; | |
712 | priv->can.can_stats.error_warning++; | |
713 | cf->can_id |= CAN_ERR_CRTL; | |
714 | errc = ioread32(&priv->regs->errc); | |
715 | if (((errc & CAN_REC) >> 8) > 96) | |
716 | cf->data[1] |= CAN_ERR_CRTL_RX_WARNING; | |
717 | if ((errc & CAN_TEC) > 96) | |
718 | cf->data[1] |= CAN_ERR_CRTL_TX_WARNING; | |
719 | dev_warn(&ndev->dev, | |
720 | "%s -> Error Counter is more than 96.\n", __func__); | |
721 | } | |
722 | /* Error passive interrupt. */ | |
723 | if (status & PCH_EPASSIV) { | |
724 | priv->can.can_stats.error_passive++; | |
725 | state = CAN_STATE_ERROR_PASSIVE; | |
726 | cf->can_id |= CAN_ERR_CRTL; | |
727 | errc = ioread32(&priv->regs->errc); | |
728 | if (((errc & CAN_REC) >> 8) > 127) | |
729 | cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
730 | if ((errc & CAN_TEC) > 127) | |
731 | cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; | |
732 | dev_err(&ndev->dev, | |
733 | "%s -> CAN controller is ERROR PASSIVE .\n", __func__); | |
734 | } | |
735 | ||
736 | if (status & PCH_LEC_ALL) { | |
737 | priv->can.can_stats.bus_error++; | |
738 | stats->rx_errors++; | |
739 | switch (status & PCH_LEC_ALL) { | |
740 | case PCH_STUF_ERR: | |
741 | cf->data[2] |= CAN_ERR_PROT_STUFF; | |
742 | break; | |
743 | case PCH_FORM_ERR: | |
744 | cf->data[2] |= CAN_ERR_PROT_FORM; | |
745 | break; | |
746 | case PCH_ACK_ERR: | |
747 | cf->data[2] |= CAN_ERR_PROT_LOC_ACK | | |
748 | CAN_ERR_PROT_LOC_ACK_DEL; | |
749 | break; | |
750 | case PCH_BIT1_ERR: | |
751 | case PCH_BIT0_ERR: | |
752 | cf->data[2] |= CAN_ERR_PROT_BIT; | |
753 | break; | |
754 | case PCH_CRC_ERR: | |
755 | cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ | | |
756 | CAN_ERR_PROT_LOC_CRC_DEL; | |
757 | break; | |
758 | default: | |
759 | iowrite32(status | PCH_LEC_ALL, &priv->regs->stat); | |
760 | break; | |
761 | } | |
762 | ||
763 | } | |
764 | ||
765 | priv->can.state = state; | |
766 | netif_rx(skb); | |
767 | ||
768 | stats->rx_packets++; | |
769 | stats->rx_bytes += cf->can_dlc; | |
770 | } | |
771 | ||
772 | static irqreturn_t pch_can_interrupt(int irq, void *dev_id) | |
773 | { | |
774 | struct net_device *ndev = (struct net_device *)dev_id; | |
775 | struct pch_can_priv *priv = netdev_priv(ndev); | |
776 | ||
777 | pch_can_set_int_enables(priv, PCH_CAN_NONE); | |
778 | ||
779 | napi_schedule(&priv->napi); | |
780 | ||
781 | return IRQ_HANDLED; | |
782 | } | |
783 | ||
784 | static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat) | |
785 | { | |
786 | u32 reg; | |
787 | canid_t id; | |
788 | u32 ide; | |
789 | u32 rtr; | |
790 | int i, j, k; | |
791 | int rcv_pkts = 0; | |
792 | struct sk_buff *skb; | |
793 | struct can_frame *cf; | |
794 | struct pch_can_priv *priv = netdev_priv(ndev); | |
795 | struct net_device_stats *stats = &(priv->ndev->stats); | |
796 | ||
797 | /* Reading the messsage object from the Message RAM */ | |
798 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
799 | pch_can_check_if_busy(&priv->regs->if1_creq, int_stat); | |
800 | ||
801 | /* Reading the MCONT register. */ | |
802 | reg = ioread32(&priv->regs->if1_mcont); | |
803 | reg &= 0xffff; | |
804 | ||
805 | for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) { | |
806 | /* If MsgLost bit set. */ | |
807 | if (reg & CAN_IF_MCONT_MSGLOST) { | |
808 | dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n"); | |
809 | pch_can_bit_clear(&priv->regs->if1_mcont, | |
810 | CAN_IF_MCONT_MSGLOST); | |
811 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, | |
812 | &priv->regs->if1_cmask); | |
813 | pch_can_check_if_busy(&priv->regs->if1_creq, k); | |
814 | ||
815 | skb = alloc_can_err_skb(ndev, &cf); | |
816 | if (!skb) | |
817 | return -ENOMEM; | |
818 | ||
819 | priv->can.can_stats.error_passive++; | |
820 | priv->can.state = CAN_STATE_ERROR_PASSIVE; | |
821 | cf->can_id |= CAN_ERR_CRTL; | |
822 | cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; | |
823 | cf->data[2] |= CAN_ERR_PROT_OVERLOAD; | |
824 | stats->rx_packets++; | |
825 | stats->rx_bytes += cf->can_dlc; | |
826 | ||
827 | netif_receive_skb(skb); | |
828 | rcv_pkts++; | |
829 | goto RX_NEXT; | |
830 | } | |
831 | if (!(reg & CAN_IF_MCONT_NEWDAT)) | |
832 | goto RX_NEXT; | |
833 | ||
834 | skb = alloc_can_skb(priv->ndev, &cf); | |
835 | if (!skb) | |
836 | return -ENOMEM; | |
837 | ||
838 | /* Get Received data */ | |
839 | ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14; | |
840 | if (ide) { | |
841 | id = (ioread32(&priv->regs->if1_id1) & 0xffff); | |
842 | id |= (((ioread32(&priv->regs->if1_id2)) & | |
843 | 0x1fff) << 16); | |
844 | cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG; | |
845 | } else { | |
846 | id = (((ioread32(&priv->regs->if1_id2)) & | |
847 | (CAN_SFF_MASK << 2)) >> 2); | |
848 | cf->can_id = (id & CAN_SFF_MASK); | |
849 | } | |
850 | ||
851 | rtr = (ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR); | |
852 | if (rtr) { | |
853 | cf->can_dlc = 0; | |
854 | cf->can_id |= CAN_RTR_FLAG; | |
855 | } else { | |
856 | cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) & | |
857 | 0x0f); | |
858 | } | |
859 | ||
860 | for (i = 0, j = 0; i < cf->can_dlc; j++) { | |
861 | reg = ioread32(&priv->regs->if1_dataa1 + j*4); | |
862 | cf->data[i++] = cpu_to_le32(reg & 0xff); | |
863 | if (i == cf->can_dlc) | |
864 | break; | |
865 | cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff); | |
866 | } | |
867 | ||
868 | netif_receive_skb(skb); | |
869 | rcv_pkts++; | |
870 | stats->rx_packets++; | |
871 | stats->rx_bytes += cf->can_dlc; | |
872 | ||
873 | if (k < PCH_FIFO_THRESH) { | |
874 | iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | | |
875 | CAN_CMASK_ARB, &priv->regs->if1_cmask); | |
876 | ||
877 | /* Clearing the Dir bit. */ | |
878 | pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR); | |
879 | ||
880 | /* Clearing NewDat & IntPnd */ | |
881 | pch_can_bit_clear(&priv->regs->if1_mcont, | |
882 | CAN_IF_MCONT_INTPND); | |
883 | pch_can_check_if_busy(&priv->regs->if1_creq, k); | |
884 | } else if (k > PCH_FIFO_THRESH) { | |
885 | pch_can_int_clr(priv, k); | |
886 | } else if (k == PCH_FIFO_THRESH) { | |
887 | int cnt; | |
888 | for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++) | |
889 | pch_can_int_clr(priv, cnt+1); | |
890 | } | |
891 | RX_NEXT: | |
892 | /* Reading the messsage object from the Message RAM */ | |
893 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask); | |
894 | pch_can_check_if_busy(&priv->regs->if1_creq, k + 1); | |
895 | reg = ioread32(&priv->regs->if1_mcont); | |
896 | } | |
897 | ||
898 | return rcv_pkts; | |
899 | } | |
900 | static int pch_can_rx_poll(struct napi_struct *napi, int quota) | |
901 | { | |
902 | struct net_device *ndev = napi->dev; | |
903 | struct pch_can_priv *priv = netdev_priv(ndev); | |
904 | struct net_device_stats *stats = &(priv->ndev->stats); | |
905 | u32 dlc; | |
906 | u32 int_stat; | |
907 | int rcv_pkts = 0; | |
908 | u32 reg_stat; | |
909 | unsigned long flags; | |
910 | ||
911 | int_stat = pch_can_int_pending(priv); | |
912 | if (!int_stat) | |
913 | return 0; | |
914 | ||
915 | INT_STAT: | |
916 | if (int_stat == CAN_STATUS_INT) { | |
917 | reg_stat = ioread32(&priv->regs->stat); | |
918 | if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { | |
919 | if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) | |
920 | pch_can_error(ndev, reg_stat); | |
921 | } | |
922 | ||
923 | if (reg_stat & PCH_TX_OK) { | |
924 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
925 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); | |
926 | pch_can_check_if_busy(&priv->regs->if2_creq, | |
927 | ioread32(&priv->regs->intr)); | |
928 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
929 | pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK); | |
930 | } | |
931 | ||
932 | if (reg_stat & PCH_RX_OK) | |
933 | pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK); | |
934 | ||
935 | int_stat = pch_can_int_pending(priv); | |
936 | if (int_stat == CAN_STATUS_INT) | |
937 | goto INT_STAT; | |
938 | } | |
939 | ||
940 | MSG_OBJ: | |
941 | if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) { | |
942 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
943 | rcv_pkts = pch_can_rx_normal(ndev, int_stat); | |
944 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
945 | if (rcv_pkts < 0) | |
946 | return 0; | |
947 | } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) { | |
948 | if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) { | |
949 | /* Handle transmission interrupt */ | |
950 | can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1); | |
951 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
952 | iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND, | |
953 | &priv->regs->if2_cmask); | |
954 | dlc = ioread32(&priv->regs->if2_mcont) & | |
955 | CAN_IF_MCONT_DLC; | |
956 | pch_can_check_if_busy(&priv->regs->if2_creq, int_stat); | |
957 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
958 | if (dlc > 8) | |
959 | dlc = 8; | |
960 | stats->tx_bytes += dlc; | |
961 | stats->tx_packets++; | |
962 | } | |
963 | } | |
964 | ||
965 | int_stat = pch_can_int_pending(priv); | |
966 | if (int_stat == CAN_STATUS_INT) | |
967 | goto INT_STAT; | |
968 | else if (int_stat >= 1 && int_stat <= 32) | |
969 | goto MSG_OBJ; | |
970 | ||
971 | napi_complete(napi); | |
972 | pch_can_set_int_enables(priv, PCH_CAN_ALL); | |
973 | ||
974 | return rcv_pkts; | |
975 | } | |
976 | ||
977 | static int pch_set_bittiming(struct net_device *ndev) | |
978 | { | |
979 | struct pch_can_priv *priv = netdev_priv(ndev); | |
980 | const struct can_bittiming *bt = &priv->can.bittiming; | |
981 | u32 canbit; | |
982 | u32 bepe; | |
983 | u32 brp; | |
984 | ||
985 | /* Setting the CCE bit for accessing the Can Timing register. */ | |
986 | pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE); | |
987 | ||
988 | brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1; | |
989 | canbit = brp & MSK_BITT_BRP; | |
990 | canbit |= (bt->sjw - 1) << BIT_BITT_SJW; | |
991 | canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1; | |
992 | canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2; | |
993 | bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE; | |
994 | iowrite32(canbit, &priv->regs->bitt); | |
995 | iowrite32(bepe, &priv->regs->brpe); | |
996 | pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | static void pch_can_start(struct net_device *ndev) | |
1002 | { | |
1003 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1004 | ||
1005 | if (priv->can.state != CAN_STATE_STOPPED) | |
1006 | pch_can_reset(priv); | |
1007 | ||
1008 | pch_set_bittiming(ndev); | |
1009 | pch_can_set_optmode(priv); | |
1010 | ||
1011 | pch_can_tx_enable_all(priv); | |
1012 | pch_can_rx_enable_all(priv); | |
1013 | ||
1014 | /* Setting the CAN to run mode. */ | |
1015 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
1016 | ||
1017 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1018 | ||
1019 | return; | |
1020 | } | |
1021 | ||
1022 | static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode) | |
1023 | { | |
1024 | int ret = 0; | |
1025 | ||
1026 | switch (mode) { | |
1027 | case CAN_MODE_START: | |
1028 | pch_can_start(ndev); | |
1029 | netif_wake_queue(ndev); | |
1030 | break; | |
1031 | default: | |
1032 | ret = -EOPNOTSUPP; | |
1033 | break; | |
1034 | } | |
1035 | ||
1036 | return ret; | |
1037 | } | |
1038 | ||
1039 | static int pch_can_open(struct net_device *ndev) | |
1040 | { | |
1041 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1042 | int retval; | |
1043 | ||
1044 | retval = pci_enable_msi(priv->dev); | |
1045 | if (retval) { | |
1046 | dev_info(&ndev->dev, "PCH CAN opened without MSI\n"); | |
1047 | priv->use_msi = 0; | |
1048 | } else { | |
1049 | dev_info(&ndev->dev, "PCH CAN opened with MSI\n"); | |
1050 | priv->use_msi = 1; | |
1051 | } | |
1052 | ||
1053 | /* Regsitering the interrupt. */ | |
1054 | retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED, | |
1055 | ndev->name, ndev); | |
1056 | if (retval) { | |
1057 | dev_err(&ndev->dev, "request_irq failed.\n"); | |
1058 | goto req_irq_err; | |
1059 | } | |
1060 | ||
1061 | /* Open common can device */ | |
1062 | retval = open_candev(ndev); | |
1063 | if (retval) { | |
1064 | dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval); | |
1065 | goto err_open_candev; | |
1066 | } | |
1067 | ||
1068 | pch_can_init(priv); | |
1069 | pch_can_start(ndev); | |
1070 | napi_enable(&priv->napi); | |
1071 | netif_start_queue(ndev); | |
1072 | ||
1073 | return 0; | |
1074 | ||
1075 | err_open_candev: | |
1076 | free_irq(priv->dev->irq, ndev); | |
1077 | req_irq_err: | |
1078 | if (priv->use_msi) | |
1079 | pci_disable_msi(priv->dev); | |
1080 | ||
1081 | pch_can_release(priv); | |
1082 | ||
1083 | return retval; | |
1084 | } | |
1085 | ||
1086 | static int pch_close(struct net_device *ndev) | |
1087 | { | |
1088 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1089 | ||
1090 | netif_stop_queue(ndev); | |
1091 | napi_disable(&priv->napi); | |
1092 | pch_can_release(priv); | |
1093 | free_irq(priv->dev->irq, ndev); | |
1094 | if (priv->use_msi) | |
1095 | pci_disable_msi(priv->dev); | |
1096 | close_candev(ndev); | |
1097 | priv->can.state = CAN_STATE_STOPPED; | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id) | |
1102 | { | |
1103 | u32 buffer_status = 0; | |
1104 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1105 | ||
1106 | /* Getting the message object status. */ | |
1107 | buffer_status = (u32) pch_can_get_buffer_status(priv); | |
1108 | ||
1109 | return buffer_status & obj_id; | |
1110 | } | |
1111 | ||
1112 | ||
1113 | static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1114 | { | |
1115 | int i, j; | |
1116 | unsigned long flags; | |
1117 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1118 | struct can_frame *cf = (struct can_frame *)skb->data; | |
1119 | int tx_buffer_avail = 0; | |
1120 | ||
1121 | if (can_dropped_invalid_skb(ndev, skb)) | |
1122 | return NETDEV_TX_OK; | |
1123 | ||
1124 | if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */ | |
1125 | while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) << | |
1126 | PCH_RX_OBJ_NUM))) | |
1127 | udelay(500); | |
1128 | ||
1129 | priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */ | |
1130 | tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */ | |
1131 | } else { | |
1132 | tx_buffer_avail = priv->tx_obj; | |
1133 | } | |
1134 | priv->tx_obj++; | |
1135 | ||
1136 | /* Attaining the lock. */ | |
1137 | spin_lock_irqsave(&priv->msgif_reg_lock, flags); | |
1138 | ||
1139 | /* Reading the Msg Obj from the Msg RAM to the Interface register. */ | |
1140 | iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask); | |
1141 | pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail); | |
1142 | ||
1143 | /* Setting the CMASK register. */ | |
1144 | pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL); | |
1145 | ||
1146 | /* If ID extended is set. */ | |
1147 | pch_can_bit_clear(&priv->regs->if2_id1, 0xffff); | |
1148 | pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD); | |
1149 | if (cf->can_id & CAN_EFF_FLAG) { | |
1150 | pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff); | |
1151 | pch_can_bit_set(&priv->regs->if2_id2, | |
1152 | ((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD); | |
1153 | } else { | |
1154 | pch_can_bit_set(&priv->regs->if2_id1, 0); | |
1155 | pch_can_bit_set(&priv->regs->if2_id2, | |
1156 | (cf->can_id & CAN_SFF_MASK) << 2); | |
1157 | } | |
1158 | ||
1159 | /* If remote frame has to be transmitted.. */ | |
1160 | if (cf->can_id & CAN_RTR_FLAG) | |
1161 | pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR); | |
1162 | ||
1163 | for (i = 0, j = 0; i < cf->can_dlc; j++) { | |
1164 | iowrite32(le32_to_cpu(cf->data[i++]), | |
1165 | (&priv->regs->if2_dataa1) + j*4); | |
1166 | if (i == cf->can_dlc) | |
1167 | break; | |
1168 | iowrite32(le32_to_cpu(cf->data[i++] << 8), | |
1169 | (&priv->regs->if2_dataa1) + j*4); | |
1170 | } | |
1171 | ||
1172 | can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1); | |
1173 | ||
1174 | /* Updating the size of the data. */ | |
1175 | pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f); | |
1176 | pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc); | |
1177 | ||
1178 | /* Clearing IntPend, NewDat & TxRqst */ | |
1179 | pch_can_bit_clear(&priv->regs->if2_mcont, | |
1180 | CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND | | |
1181 | CAN_IF_MCONT_TXRQXT); | |
1182 | ||
1183 | /* Setting NewDat, TxRqst bits */ | |
1184 | pch_can_bit_set(&priv->regs->if2_mcont, | |
1185 | CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT); | |
1186 | ||
1187 | pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail); | |
1188 | ||
1189 | spin_unlock_irqrestore(&priv->msgif_reg_lock, flags); | |
1190 | ||
1191 | return NETDEV_TX_OK; | |
1192 | } | |
1193 | ||
1194 | static const struct net_device_ops pch_can_netdev_ops = { | |
1195 | .ndo_open = pch_can_open, | |
1196 | .ndo_stop = pch_close, | |
1197 | .ndo_start_xmit = pch_xmit, | |
1198 | }; | |
1199 | ||
1200 | static void __devexit pch_can_remove(struct pci_dev *pdev) | |
1201 | { | |
1202 | struct net_device *ndev = pci_get_drvdata(pdev); | |
1203 | struct pch_can_priv *priv = netdev_priv(ndev); | |
1204 | ||
1205 | unregister_candev(priv->ndev); | |
1206 | free_candev(priv->ndev); | |
1207 | pci_iounmap(pdev, priv->regs); | |
1208 | pci_release_regions(pdev); | |
1209 | pci_disable_device(pdev); | |
1210 | pci_set_drvdata(pdev, NULL); | |
1211 | pch_can_reset(priv); | |
1212 | } | |
1213 | ||
1214 | #ifdef CONFIG_PM | |
1215 | static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state) | |
1216 | { | |
1217 | int i; /* Counter variable. */ | |
1218 | int retval; /* Return value. */ | |
1219 | u32 buf_stat; /* Variable for reading the transmit buffer status. */ | |
1220 | u32 counter = 0xFFFFFF; | |
1221 | ||
1222 | struct net_device *dev = pci_get_drvdata(pdev); | |
1223 | struct pch_can_priv *priv = netdev_priv(dev); | |
1224 | ||
1225 | /* Stop the CAN controller */ | |
1226 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1227 | ||
1228 | /* Indicate that we are aboutto/in suspend */ | |
1229 | priv->can.state = CAN_STATE_SLEEPING; | |
1230 | ||
1231 | /* Waiting for all transmission to complete. */ | |
1232 | while (counter) { | |
1233 | buf_stat = pch_can_get_buffer_status(priv); | |
1234 | if (!buf_stat) | |
1235 | break; | |
1236 | counter--; | |
1237 | udelay(1); | |
1238 | } | |
1239 | if (!counter) | |
1240 | dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__); | |
1241 | ||
1242 | /* Save interrupt configuration and then disable them */ | |
1243 | pch_can_get_int_enables(priv, &(priv->int_enables)); | |
1244 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1245 | ||
1246 | /* Save Tx buffer enable state */ | |
1247 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
1248 | if (priv->msg_obj[i] == MSG_OBJ_TX) | |
1249 | pch_can_get_tx_enable(priv, i + 1, | |
1250 | &(priv->tx_enable[i])); | |
1251 | } | |
1252 | ||
1253 | /* Disable all Transmit buffers */ | |
1254 | pch_can_tx_disable_all(priv); | |
1255 | ||
1256 | /* Save Rx buffer enable state */ | |
1257 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
1258 | if (priv->msg_obj[i] == MSG_OBJ_RX) { | |
1259 | pch_can_get_rx_enable(priv, i + 1, | |
1260 | &(priv->rx_enable[i])); | |
1261 | pch_can_get_rx_buffer_link(priv, i + 1, | |
1262 | &(priv->rx_link[i])); | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | /* Disable all Receive buffers */ | |
1267 | pch_can_rx_disable_all(priv); | |
1268 | retval = pci_save_state(pdev); | |
1269 | if (retval) { | |
1270 | dev_err(&pdev->dev, "pci_save_state failed.\n"); | |
1271 | } else { | |
1272 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1273 | pci_disable_device(pdev); | |
1274 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1275 | } | |
1276 | ||
1277 | return retval; | |
1278 | } | |
1279 | ||
1280 | static int pch_can_resume(struct pci_dev *pdev) | |
1281 | { | |
1282 | int i; /* Counter variable. */ | |
1283 | int retval; /* Return variable. */ | |
1284 | struct net_device *dev = pci_get_drvdata(pdev); | |
1285 | struct pch_can_priv *priv = netdev_priv(dev); | |
1286 | ||
1287 | pci_set_power_state(pdev, PCI_D0); | |
1288 | pci_restore_state(pdev); | |
1289 | retval = pci_enable_device(pdev); | |
1290 | if (retval) { | |
1291 | dev_err(&pdev->dev, "pci_enable_device failed.\n"); | |
1292 | return retval; | |
1293 | } | |
1294 | ||
1295 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1296 | ||
1297 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
1298 | ||
1299 | /* Disabling all interrupts. */ | |
1300 | pch_can_set_int_enables(priv, PCH_CAN_DISABLE); | |
1301 | ||
1302 | /* Setting the CAN device in Stop Mode. */ | |
1303 | pch_can_set_run_mode(priv, PCH_CAN_STOP); | |
1304 | ||
1305 | /* Configuring the transmit and receive buffers. */ | |
1306 | pch_can_config_rx_tx_buffers(priv); | |
1307 | ||
1308 | /* Restore the CAN state */ | |
1309 | pch_set_bittiming(dev); | |
1310 | ||
1311 | /* Listen/Active */ | |
1312 | pch_can_set_optmode(priv); | |
1313 | ||
1314 | /* Enabling the transmit buffer. */ | |
1315 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
1316 | if (priv->msg_obj[i] == MSG_OBJ_TX) { | |
1317 | pch_can_set_tx_enable(priv, i + 1, | |
1318 | priv->tx_enable[i]); | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | /* Configuring the receive buffer and enabling them. */ | |
1323 | for (i = 0; i < PCH_OBJ_NUM; i++) { | |
1324 | if (priv->msg_obj[i] == MSG_OBJ_RX) { | |
1325 | /* Restore buffer link */ | |
1326 | pch_can_set_rx_buffer_link(priv, i + 1, | |
1327 | priv->rx_link[i]); | |
1328 | ||
1329 | /* Restore buffer enables */ | |
1330 | pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | /* Enable CAN Interrupts */ | |
1335 | pch_can_set_int_custom(priv); | |
1336 | ||
1337 | /* Restore Run Mode */ | |
1338 | pch_can_set_run_mode(priv, PCH_CAN_RUN); | |
1339 | ||
1340 | return retval; | |
1341 | } | |
1342 | #else | |
1343 | #define pch_can_suspend NULL | |
1344 | #define pch_can_resume NULL | |
1345 | #endif | |
1346 | ||
1347 | static int pch_can_get_berr_counter(const struct net_device *dev, | |
1348 | struct can_berr_counter *bec) | |
1349 | { | |
1350 | struct pch_can_priv *priv = netdev_priv(dev); | |
1351 | ||
1352 | bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC; | |
1353 | bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8; | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int __devinit pch_can_probe(struct pci_dev *pdev, | |
1359 | const struct pci_device_id *id) | |
1360 | { | |
1361 | struct net_device *ndev; | |
1362 | struct pch_can_priv *priv; | |
1363 | int rc; | |
1364 | int index; | |
1365 | void __iomem *addr; | |
1366 | ||
1367 | rc = pci_enable_device(pdev); | |
1368 | if (rc) { | |
1369 | dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc); | |
1370 | goto probe_exit_endev; | |
1371 | } | |
1372 | ||
1373 | rc = pci_request_regions(pdev, KBUILD_MODNAME); | |
1374 | if (rc) { | |
1375 | dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc); | |
1376 | goto probe_exit_pcireq; | |
1377 | } | |
1378 | ||
1379 | addr = pci_iomap(pdev, 1, 0); | |
1380 | if (!addr) { | |
1381 | rc = -EIO; | |
1382 | dev_err(&pdev->dev, "Failed pci_iomap\n"); | |
1383 | goto probe_exit_ipmap; | |
1384 | } | |
1385 | ||
1386 | ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM); | |
1387 | if (!ndev) { | |
1388 | rc = -ENOMEM; | |
1389 | dev_err(&pdev->dev, "Failed alloc_candev\n"); | |
1390 | goto probe_exit_alloc_candev; | |
1391 | } | |
1392 | ||
1393 | priv = netdev_priv(ndev); | |
1394 | priv->ndev = ndev; | |
1395 | priv->regs = addr; | |
1396 | priv->dev = pdev; | |
1397 | priv->can.bittiming_const = &pch_can_bittiming_const; | |
1398 | priv->can.do_set_mode = pch_can_do_set_mode; | |
1399 | priv->can.do_get_berr_counter = pch_can_get_berr_counter; | |
1400 | priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY | | |
1401 | CAN_CTRLMODE_LOOPBACK; | |
1402 | priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */ | |
1403 | ||
1404 | ndev->irq = pdev->irq; | |
1405 | ndev->flags |= IFF_ECHO; | |
1406 | ||
1407 | pci_set_drvdata(pdev, ndev); | |
1408 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1409 | ndev->netdev_ops = &pch_can_netdev_ops; | |
1410 | ||
1411 | priv->can.clock.freq = PCH_CAN_CLK; /* Hz */ | |
1412 | for (index = 0; index < PCH_RX_OBJ_NUM;) | |
1413 | priv->msg_obj[index++] = MSG_OBJ_RX; | |
1414 | ||
1415 | for (index = index; index < PCH_OBJ_NUM;) | |
1416 | priv->msg_obj[index++] = MSG_OBJ_TX; | |
1417 | ||
1418 | netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM); | |
1419 | ||
1420 | rc = register_candev(ndev); | |
1421 | if (rc) { | |
1422 | dev_err(&pdev->dev, "Failed register_candev %d\n", rc); | |
1423 | goto probe_exit_reg_candev; | |
1424 | } | |
1425 | ||
1426 | return 0; | |
1427 | ||
1428 | probe_exit_reg_candev: | |
1429 | free_candev(ndev); | |
1430 | probe_exit_alloc_candev: | |
1431 | pci_iounmap(pdev, addr); | |
1432 | probe_exit_ipmap: | |
1433 | pci_release_regions(pdev); | |
1434 | probe_exit_pcireq: | |
1435 | pci_disable_device(pdev); | |
1436 | probe_exit_endev: | |
1437 | return rc; | |
1438 | } | |
1439 | ||
1440 | static struct pci_driver pch_can_pcidev = { | |
1441 | .name = "pch_can", | |
1442 | .id_table = pch_pci_tbl, | |
1443 | .probe = pch_can_probe, | |
1444 | .remove = __devexit_p(pch_can_remove), | |
1445 | .suspend = pch_can_suspend, | |
1446 | .resume = pch_can_resume, | |
1447 | }; | |
1448 | ||
1449 | static int __init pch_can_pci_init(void) | |
1450 | { | |
1451 | return pci_register_driver(&pch_can_pcidev); | |
1452 | } | |
1453 | module_init(pch_can_pci_init); | |
1454 | ||
1455 | static void __exit pch_can_pci_exit(void) | |
1456 | { | |
1457 | pci_unregister_driver(&pch_can_pcidev); | |
1458 | } | |
1459 | module_exit(pch_can_pci_exit); | |
1460 | ||
1461 | MODULE_DESCRIPTION("Controller Area Network Driver"); | |
1462 | MODULE_LICENSE("GPL v2"); | |
1463 | MODULE_VERSION("0.94"); |