]>
Commit | Line | Data |
---|---|---|
afa17a50 WS |
1 | /* |
2 | * CAN bus driver for the alone generic (as possible as) MSCAN controller. | |
3 | * | |
4 | * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>, | |
5 | * Varma Electronics Oy | |
6 | * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com> | |
7 | * Copytight (C) 2008-2009 Pengutronix <kernel@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the version 2 of the GNU General Public License | |
11 | * as published by the Free Software Foundation | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/if_arp.h> | |
29 | #include <linux/if_ether.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/can.h> | |
32 | #include <linux/can/dev.h> | |
33 | #include <linux/can/error.h> | |
34 | #include <linux/io.h> | |
35 | ||
36 | #include "mscan.h" | |
37 | ||
afa17a50 WS |
38 | static struct can_bittiming_const mscan_bittiming_const = { |
39 | .name = "mscan", | |
40 | .tseg1_min = 4, | |
41 | .tseg1_max = 16, | |
42 | .tseg2_min = 2, | |
43 | .tseg2_max = 8, | |
44 | .sjw_max = 4, | |
45 | .brp_min = 1, | |
46 | .brp_max = 64, | |
47 | .brp_inc = 1, | |
48 | }; | |
49 | ||
50 | struct mscan_state { | |
51 | u8 mode; | |
52 | u8 canrier; | |
53 | u8 cantier; | |
54 | }; | |
55 | ||
afa17a50 WS |
56 | static enum can_state state_map[] = { |
57 | CAN_STATE_ERROR_ACTIVE, | |
58 | CAN_STATE_ERROR_WARNING, | |
59 | CAN_STATE_ERROR_PASSIVE, | |
60 | CAN_STATE_BUS_OFF | |
61 | }; | |
62 | ||
63 | static int mscan_set_mode(struct net_device *dev, u8 mode) | |
64 | { | |
65 | struct mscan_priv *priv = netdev_priv(dev); | |
66 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
67 | int ret = 0; | |
68 | int i; | |
69 | u8 canctl1; | |
70 | ||
71 | if (mode != MSCAN_NORMAL_MODE) { | |
afa17a50 WS |
72 | if (priv->tx_active) { |
73 | /* Abort transfers before going to sleep */# | |
74 | out_8(®s->cantarq, priv->tx_active); | |
75 | /* Suppress TX done interrupts */ | |
76 | out_8(®s->cantier, 0); | |
77 | } | |
78 | ||
79 | canctl1 = in_8(®s->canctl1); | |
0285e7ce | 80 | if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) { |
afa17a50 WS |
81 | out_8(®s->canctl0, |
82 | in_8(®s->canctl0) | MSCAN_SLPRQ); | |
83 | for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { | |
84 | if (in_8(®s->canctl1) & MSCAN_SLPAK) | |
85 | break; | |
86 | udelay(100); | |
87 | } | |
88 | /* | |
89 | * The mscan controller will fail to enter sleep mode, | |
90 | * while there are irregular activities on bus, like | |
91 | * somebody keeps retransmitting. This behavior is | |
92 | * undocumented and seems to differ between mscan built | |
93 | * in mpc5200b and mpc5200. We proceed in that case, | |
94 | * since otherwise the slprq will be kept set and the | |
95 | * controller will get stuck. NOTE: INITRQ or CSWAI | |
96 | * will abort all active transmit actions, if still | |
97 | * any, at once. | |
98 | */ | |
99 | if (i >= MSCAN_SET_MODE_RETRIES) | |
100 | dev_dbg(dev->dev.parent, | |
101 | "device failed to enter sleep mode. " | |
102 | "We proceed anyhow.\n"); | |
103 | else | |
104 | priv->can.state = CAN_STATE_SLEEPING; | |
105 | } | |
106 | ||
0285e7ce | 107 | if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) { |
afa17a50 WS |
108 | out_8(®s->canctl0, |
109 | in_8(®s->canctl0) | MSCAN_INITRQ); | |
110 | for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { | |
111 | if (in_8(®s->canctl1) & MSCAN_INITAK) | |
112 | break; | |
113 | } | |
114 | if (i >= MSCAN_SET_MODE_RETRIES) | |
115 | ret = -ENODEV; | |
116 | } | |
117 | if (!ret) | |
118 | priv->can.state = CAN_STATE_STOPPED; | |
119 | ||
120 | if (mode & MSCAN_CSWAI) | |
121 | out_8(®s->canctl0, | |
122 | in_8(®s->canctl0) | MSCAN_CSWAI); | |
123 | ||
124 | } else { | |
125 | canctl1 = in_8(®s->canctl1); | |
126 | if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) { | |
127 | out_8(®s->canctl0, in_8(®s->canctl0) & | |
128 | ~(MSCAN_SLPRQ | MSCAN_INITRQ)); | |
129 | for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) { | |
130 | canctl1 = in_8(®s->canctl1); | |
131 | if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK))) | |
132 | break; | |
133 | } | |
134 | if (i >= MSCAN_SET_MODE_RETRIES) | |
135 | ret = -ENODEV; | |
136 | else | |
137 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
138 | } | |
139 | } | |
140 | return ret; | |
141 | } | |
142 | ||
143 | static int mscan_start(struct net_device *dev) | |
144 | { | |
145 | struct mscan_priv *priv = netdev_priv(dev); | |
146 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
147 | u8 canrflg; | |
148 | int err; | |
149 | ||
150 | out_8(®s->canrier, 0); | |
151 | ||
152 | INIT_LIST_HEAD(&priv->tx_head); | |
153 | priv->prev_buf_id = 0; | |
154 | priv->cur_pri = 0; | |
155 | priv->tx_active = 0; | |
156 | priv->shadow_canrier = 0; | |
157 | priv->flags = 0; | |
158 | ||
159 | err = mscan_set_mode(dev, MSCAN_NORMAL_MODE); | |
160 | if (err) | |
161 | return err; | |
162 | ||
163 | canrflg = in_8(®s->canrflg); | |
164 | priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; | |
165 | priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg), | |
166 | MSCAN_STATE_TX(canrflg))]; | |
167 | out_8(®s->cantier, 0); | |
168 | ||
169 | /* Enable receive interrupts. */ | |
170 | out_8(®s->canrier, MSCAN_OVRIE | MSCAN_RXFIE | MSCAN_CSCIE | | |
171 | MSCAN_RSTATE1 | MSCAN_RSTATE0 | MSCAN_TSTATE1 | MSCAN_TSTATE0); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
177 | { | |
178 | struct can_frame *frame = (struct can_frame *)skb->data; | |
179 | struct mscan_priv *priv = netdev_priv(dev); | |
180 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
181 | int i, rtr, buf_id; | |
182 | u32 can_id; | |
183 | ||
184 | if (frame->can_dlc > 8) | |
185 | return -EINVAL; | |
186 | ||
187 | out_8(®s->cantier, 0); | |
188 | ||
189 | i = ~priv->tx_active & MSCAN_TXE; | |
190 | buf_id = ffs(i) - 1; | |
191 | switch (hweight8(i)) { | |
192 | case 0: | |
193 | netif_stop_queue(dev); | |
194 | dev_err(dev->dev.parent, "Tx Ring full when queue awake!\n"); | |
195 | return NETDEV_TX_BUSY; | |
196 | case 1: | |
197 | /* | |
198 | * if buf_id < 3, then current frame will be send out of order, | |
199 | * since buffer with lower id have higher priority (hell..) | |
200 | */ | |
201 | netif_stop_queue(dev); | |
202 | case 2: | |
203 | if (buf_id < priv->prev_buf_id) { | |
204 | priv->cur_pri++; | |
205 | if (priv->cur_pri == 0xff) { | |
206 | set_bit(F_TX_WAIT_ALL, &priv->flags); | |
207 | netif_stop_queue(dev); | |
208 | } | |
209 | } | |
210 | set_bit(F_TX_PROGRESS, &priv->flags); | |
211 | break; | |
212 | } | |
213 | priv->prev_buf_id = buf_id; | |
214 | out_8(®s->cantbsel, i); | |
215 | ||
216 | rtr = frame->can_id & CAN_RTR_FLAG; | |
217 | ||
218 | if (frame->can_id & CAN_EFF_FLAG) { | |
219 | can_id = (frame->can_id & CAN_EFF_MASK) << 1; | |
220 | if (rtr) | |
221 | can_id |= 1; | |
222 | out_be16(®s->tx.idr3_2, can_id); | |
223 | ||
224 | can_id >>= 16; | |
225 | can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) | (3 << 3); | |
226 | } else { | |
227 | can_id = (frame->can_id & CAN_SFF_MASK) << 5; | |
228 | if (rtr) | |
229 | can_id |= 1 << 4; | |
230 | } | |
231 | out_be16(®s->tx.idr1_0, can_id); | |
232 | ||
233 | if (!rtr) { | |
234 | void __iomem *data = ®s->tx.dsr1_0; | |
0285e7ce WS |
235 | u16 *payload = (u16 *)frame->data; |
236 | ||
afa17a50 WS |
237 | /* It is safe to write into dsr[dlc+1] */ |
238 | for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { | |
239 | out_be16(data, *payload++); | |
240 | data += 2 + _MSCAN_RESERVED_DSR_SIZE; | |
241 | } | |
242 | } | |
243 | ||
244 | out_8(®s->tx.dlr, frame->can_dlc); | |
245 | out_8(®s->tx.tbpr, priv->cur_pri); | |
246 | ||
247 | /* Start transmission. */ | |
248 | out_8(®s->cantflg, 1 << buf_id); | |
249 | ||
250 | if (!test_bit(F_TX_PROGRESS, &priv->flags)) | |
251 | dev->trans_start = jiffies; | |
252 | ||
253 | list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head); | |
254 | ||
255 | can_put_echo_skb(skb, dev, buf_id); | |
256 | ||
257 | /* Enable interrupt. */ | |
258 | priv->tx_active |= 1 << buf_id; | |
259 | out_8(®s->cantier, priv->tx_active); | |
260 | ||
261 | return NETDEV_TX_OK; | |
262 | } | |
263 | ||
264 | /* This function returns the old state to see where we came from */ | |
265 | static enum can_state check_set_state(struct net_device *dev, u8 canrflg) | |
266 | { | |
267 | struct mscan_priv *priv = netdev_priv(dev); | |
268 | enum can_state state, old_state = priv->can.state; | |
269 | ||
270 | if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) { | |
271 | state = state_map[max(MSCAN_STATE_RX(canrflg), | |
272 | MSCAN_STATE_TX(canrflg))]; | |
273 | priv->can.state = state; | |
274 | } | |
275 | return old_state; | |
276 | } | |
277 | ||
278 | static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame) | |
279 | { | |
280 | struct mscan_priv *priv = netdev_priv(dev); | |
281 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
282 | u32 can_id; | |
283 | int i; | |
284 | ||
285 | can_id = in_be16(®s->rx.idr1_0); | |
286 | if (can_id & (1 << 3)) { | |
287 | frame->can_id = CAN_EFF_FLAG; | |
288 | can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2)); | |
289 | can_id = ((can_id & 0xffe00000) | | |
290 | ((can_id & 0x7ffff) << 2)) >> 2; | |
291 | } else { | |
292 | can_id >>= 4; | |
293 | frame->can_id = 0; | |
294 | } | |
295 | ||
296 | frame->can_id |= can_id >> 1; | |
297 | if (can_id & 1) | |
298 | frame->can_id |= CAN_RTR_FLAG; | |
299 | frame->can_dlc = in_8(®s->rx.dlr) & 0xf; | |
300 | ||
301 | if (!(frame->can_id & CAN_RTR_FLAG)) { | |
302 | void __iomem *data = ®s->rx.dsr1_0; | |
0285e7ce WS |
303 | u16 *payload = (u16 *)frame->data; |
304 | ||
afa17a50 WS |
305 | for (i = 0; i < (frame->can_dlc + 1) / 2; i++) { |
306 | *payload++ = in_be16(data); | |
307 | data += 2 + _MSCAN_RESERVED_DSR_SIZE; | |
308 | } | |
309 | } | |
310 | ||
311 | out_8(®s->canrflg, MSCAN_RXF); | |
312 | } | |
313 | ||
314 | static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame, | |
315 | u8 canrflg) | |
316 | { | |
317 | struct mscan_priv *priv = netdev_priv(dev); | |
318 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
319 | struct net_device_stats *stats = &dev->stats; | |
320 | enum can_state old_state; | |
321 | ||
322 | dev_dbg(dev->dev.parent, "error interrupt (canrflg=%#x)\n", canrflg); | |
323 | frame->can_id = CAN_ERR_FLAG; | |
324 | ||
325 | if (canrflg & MSCAN_OVRIF) { | |
326 | frame->can_id |= CAN_ERR_CRTL; | |
327 | frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; | |
328 | stats->rx_over_errors++; | |
329 | stats->rx_errors++; | |
0285e7ce | 330 | } else { |
afa17a50 | 331 | frame->data[1] = 0; |
0285e7ce | 332 | } |
afa17a50 WS |
333 | |
334 | old_state = check_set_state(dev, canrflg); | |
335 | /* State changed */ | |
336 | if (old_state != priv->can.state) { | |
337 | switch (priv->can.state) { | |
338 | case CAN_STATE_ERROR_WARNING: | |
339 | frame->can_id |= CAN_ERR_CRTL; | |
340 | priv->can.can_stats.error_warning++; | |
341 | if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) < | |
342 | (canrflg & MSCAN_RSTAT_MSK)) | |
343 | frame->data[1] |= CAN_ERR_CRTL_RX_WARNING; | |
afa17a50 WS |
344 | if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) < |
345 | (canrflg & MSCAN_TSTAT_MSK)) | |
346 | frame->data[1] |= CAN_ERR_CRTL_TX_WARNING; | |
347 | break; | |
348 | case CAN_STATE_ERROR_PASSIVE: | |
349 | frame->can_id |= CAN_ERR_CRTL; | |
350 | priv->can.can_stats.error_passive++; | |
351 | frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; | |
352 | break; | |
353 | case CAN_STATE_BUS_OFF: | |
354 | frame->can_id |= CAN_ERR_BUSOFF; | |
355 | /* | |
356 | * The MSCAN on the MPC5200 does recover from bus-off | |
357 | * automatically. To avoid that we stop the chip doing | |
358 | * a light-weight stop (we are in irq-context). | |
359 | */ | |
360 | out_8(®s->cantier, 0); | |
361 | out_8(®s->canrier, 0); | |
362 | out_8(®s->canctl0, in_8(®s->canctl0) | | |
363 | MSCAN_SLPRQ | MSCAN_INITRQ); | |
364 | can_bus_off(dev); | |
365 | break; | |
366 | default: | |
367 | break; | |
368 | } | |
369 | } | |
370 | priv->shadow_statflg = canrflg & MSCAN_STAT_MSK; | |
371 | frame->can_dlc = CAN_ERR_DLC; | |
372 | out_8(®s->canrflg, MSCAN_ERR_IF); | |
373 | } | |
374 | ||
375 | static int mscan_rx_poll(struct napi_struct *napi, int quota) | |
376 | { | |
377 | struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi); | |
378 | struct net_device *dev = napi->dev; | |
379 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
380 | struct net_device_stats *stats = &dev->stats; | |
381 | int npackets = 0; | |
382 | int ret = 1; | |
383 | struct sk_buff *skb; | |
384 | struct can_frame *frame; | |
385 | u8 canrflg; | |
386 | ||
387 | while (npackets < quota && ((canrflg = in_8(®s->canrflg)) & | |
388 | (MSCAN_RXF | MSCAN_ERR_IF))) { | |
389 | ||
390 | skb = alloc_can_skb(dev, &frame); | |
391 | if (!skb) { | |
392 | if (printk_ratelimit()) | |
393 | dev_notice(dev->dev.parent, "packet dropped\n"); | |
394 | stats->rx_dropped++; | |
395 | out_8(®s->canrflg, canrflg); | |
396 | continue; | |
397 | } | |
398 | ||
399 | if (canrflg & MSCAN_RXF) | |
400 | mscan_get_rx_frame(dev, frame); | |
0285e7ce | 401 | else if (canrflg & MSCAN_ERR_IF) |
afa17a50 WS |
402 | mscan_get_err_frame(dev, frame, canrflg); |
403 | ||
404 | stats->rx_packets++; | |
405 | stats->rx_bytes += frame->can_dlc; | |
406 | npackets++; | |
407 | netif_receive_skb(skb); | |
408 | } | |
409 | ||
410 | if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) { | |
411 | napi_complete(&priv->napi); | |
412 | clear_bit(F_RX_PROGRESS, &priv->flags); | |
413 | if (priv->can.state < CAN_STATE_BUS_OFF) | |
414 | out_8(®s->canrier, priv->shadow_canrier); | |
415 | ret = 0; | |
416 | } | |
417 | return ret; | |
418 | } | |
419 | ||
420 | static irqreturn_t mscan_isr(int irq, void *dev_id) | |
421 | { | |
422 | struct net_device *dev = (struct net_device *)dev_id; | |
423 | struct mscan_priv *priv = netdev_priv(dev); | |
424 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
425 | struct net_device_stats *stats = &dev->stats; | |
426 | u8 cantier, cantflg, canrflg; | |
427 | irqreturn_t ret = IRQ_NONE; | |
428 | ||
429 | cantier = in_8(®s->cantier) & MSCAN_TXE; | |
430 | cantflg = in_8(®s->cantflg) & cantier; | |
431 | ||
432 | if (cantier && cantflg) { | |
afa17a50 WS |
433 | struct list_head *tmp, *pos; |
434 | ||
435 | list_for_each_safe(pos, tmp, &priv->tx_head) { | |
436 | struct tx_queue_entry *entry = | |
437 | list_entry(pos, struct tx_queue_entry, list); | |
438 | u8 mask = entry->mask; | |
439 | ||
440 | if (!(cantflg & mask)) | |
441 | continue; | |
442 | ||
443 | out_8(®s->cantbsel, mask); | |
444 | stats->tx_bytes += in_8(®s->tx.dlr); | |
445 | stats->tx_packets++; | |
446 | can_get_echo_skb(dev, entry->id); | |
447 | priv->tx_active &= ~mask; | |
448 | list_del(pos); | |
449 | } | |
450 | ||
451 | if (list_empty(&priv->tx_head)) { | |
452 | clear_bit(F_TX_WAIT_ALL, &priv->flags); | |
453 | clear_bit(F_TX_PROGRESS, &priv->flags); | |
454 | priv->cur_pri = 0; | |
0285e7ce | 455 | } else { |
afa17a50 | 456 | dev->trans_start = jiffies; |
0285e7ce | 457 | } |
afa17a50 WS |
458 | |
459 | if (!test_bit(F_TX_WAIT_ALL, &priv->flags)) | |
460 | netif_wake_queue(dev); | |
461 | ||
462 | out_8(®s->cantier, priv->tx_active); | |
463 | ret = IRQ_HANDLED; | |
464 | } | |
465 | ||
466 | canrflg = in_8(®s->canrflg); | |
467 | if ((canrflg & ~MSCAN_STAT_MSK) && | |
468 | !test_and_set_bit(F_RX_PROGRESS, &priv->flags)) { | |
469 | if (canrflg & ~MSCAN_STAT_MSK) { | |
470 | priv->shadow_canrier = in_8(®s->canrier); | |
471 | out_8(®s->canrier, 0); | |
472 | napi_schedule(&priv->napi); | |
473 | ret = IRQ_HANDLED; | |
0285e7ce | 474 | } else { |
afa17a50 | 475 | clear_bit(F_RX_PROGRESS, &priv->flags); |
0285e7ce | 476 | } |
afa17a50 WS |
477 | } |
478 | return ret; | |
479 | } | |
480 | ||
481 | static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode) | |
482 | { | |
afa17a50 WS |
483 | struct mscan_priv *priv = netdev_priv(dev); |
484 | int ret = 0; | |
485 | ||
486 | if (!priv->open_time) | |
487 | return -EINVAL; | |
488 | ||
489 | switch (mode) { | |
490 | case CAN_MODE_SLEEP: | |
491 | case CAN_MODE_STOP: | |
492 | netif_stop_queue(dev); | |
493 | mscan_set_mode(dev, | |
494 | (mode == | |
495 | CAN_MODE_STOP) ? MSCAN_INIT_MODE : | |
496 | MSCAN_SLEEP_MODE); | |
497 | break; | |
498 | case CAN_MODE_START: | |
499 | if (priv->can.state <= CAN_STATE_BUS_OFF) | |
500 | mscan_set_mode(dev, MSCAN_INIT_MODE); | |
501 | ret = mscan_start(dev); | |
502 | if (ret) | |
503 | break; | |
504 | if (netif_queue_stopped(dev)) | |
505 | netif_wake_queue(dev); | |
506 | break; | |
507 | ||
508 | default: | |
509 | ret = -EOPNOTSUPP; | |
510 | break; | |
511 | } | |
512 | return ret; | |
513 | } | |
514 | ||
515 | static int mscan_do_set_bittiming(struct net_device *dev) | |
516 | { | |
517 | struct mscan_priv *priv = netdev_priv(dev); | |
518 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
519 | struct can_bittiming *bt = &priv->can.bittiming; | |
520 | u8 btr0, btr1; | |
521 | ||
522 | btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw); | |
523 | btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) | | |
524 | BTR1_SET_TSEG2(bt->phase_seg2) | | |
525 | BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)); | |
526 | ||
527 | dev_info(dev->dev.parent, "setting BTR0=0x%02x BTR1=0x%02x\n", | |
528 | btr0, btr1); | |
529 | ||
530 | out_8(®s->canbtr0, btr0); | |
531 | out_8(®s->canbtr1, btr1); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int mscan_open(struct net_device *dev) | |
537 | { | |
538 | int ret; | |
539 | struct mscan_priv *priv = netdev_priv(dev); | |
540 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
541 | ||
542 | /* common open */ | |
543 | ret = open_candev(dev); | |
544 | if (ret) | |
545 | return ret; | |
546 | ||
547 | napi_enable(&priv->napi); | |
548 | ||
549 | ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev); | |
550 | if (ret < 0) { | |
551 | napi_disable(&priv->napi); | |
552 | printk(KERN_ERR "%s - failed to attach interrupt\n", | |
553 | dev->name); | |
554 | return ret; | |
555 | } | |
556 | ||
557 | priv->open_time = jiffies; | |
558 | ||
559 | out_8(®s->canctl1, in_8(®s->canctl1) & ~MSCAN_LISTEN); | |
560 | ||
561 | ret = mscan_start(dev); | |
562 | if (ret) | |
563 | return ret; | |
564 | ||
565 | netif_start_queue(dev); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static int mscan_close(struct net_device *dev) | |
571 | { | |
572 | struct mscan_priv *priv = netdev_priv(dev); | |
573 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
574 | ||
575 | netif_stop_queue(dev); | |
576 | napi_disable(&priv->napi); | |
577 | ||
578 | out_8(®s->cantier, 0); | |
579 | out_8(®s->canrier, 0); | |
580 | mscan_set_mode(dev, MSCAN_INIT_MODE); | |
581 | close_candev(dev); | |
582 | free_irq(dev->irq, dev); | |
583 | priv->open_time = 0; | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static const struct net_device_ops mscan_netdev_ops = { | |
589 | .ndo_open = mscan_open, | |
590 | .ndo_stop = mscan_close, | |
591 | .ndo_start_xmit = mscan_start_xmit, | |
592 | }; | |
593 | ||
594 | int register_mscandev(struct net_device *dev, int clock_src) | |
595 | { | |
596 | struct mscan_priv *priv = netdev_priv(dev); | |
597 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
598 | u8 ctl1; | |
599 | ||
600 | ctl1 = in_8(®s->canctl1); | |
601 | if (clock_src) | |
602 | ctl1 |= MSCAN_CLKSRC; | |
603 | else | |
604 | ctl1 &= ~MSCAN_CLKSRC; | |
605 | ||
606 | ctl1 |= MSCAN_CANE; | |
607 | out_8(®s->canctl1, ctl1); | |
608 | udelay(100); | |
609 | ||
610 | /* acceptance mask/acceptance code (accept everything) */ | |
611 | out_be16(®s->canidar1_0, 0); | |
612 | out_be16(®s->canidar3_2, 0); | |
613 | out_be16(®s->canidar5_4, 0); | |
614 | out_be16(®s->canidar7_6, 0); | |
615 | ||
616 | out_be16(®s->canidmr1_0, 0xffff); | |
617 | out_be16(®s->canidmr3_2, 0xffff); | |
618 | out_be16(®s->canidmr5_4, 0xffff); | |
619 | out_be16(®s->canidmr7_6, 0xffff); | |
620 | /* Two 32 bit Acceptance Filters */ | |
621 | out_8(®s->canidac, MSCAN_AF_32BIT); | |
622 | ||
623 | mscan_set_mode(dev, MSCAN_INIT_MODE); | |
624 | ||
625 | return register_candev(dev); | |
626 | } | |
627 | EXPORT_SYMBOL_GPL(register_mscandev); | |
628 | ||
629 | void unregister_mscandev(struct net_device *dev) | |
630 | { | |
631 | struct mscan_priv *priv = netdev_priv(dev); | |
632 | struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base; | |
633 | mscan_set_mode(dev, MSCAN_INIT_MODE); | |
634 | out_8(®s->canctl1, in_8(®s->canctl1) & ~MSCAN_CANE); | |
635 | unregister_candev(dev); | |
636 | } | |
637 | EXPORT_SYMBOL_GPL(unregister_mscandev); | |
638 | ||
639 | struct net_device *alloc_mscandev(void) | |
640 | { | |
641 | struct net_device *dev; | |
642 | struct mscan_priv *priv; | |
643 | int i; | |
644 | ||
645 | dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX); | |
646 | if (!dev) | |
647 | return NULL; | |
648 | priv = netdev_priv(dev); | |
649 | ||
650 | dev->netdev_ops = &mscan_netdev_ops; | |
651 | ||
652 | dev->flags |= IFF_ECHO; /* we support local echo */ | |
653 | ||
654 | netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8); | |
655 | ||
656 | priv->can.bittiming_const = &mscan_bittiming_const; | |
657 | priv->can.do_set_bittiming = mscan_do_set_bittiming; | |
658 | priv->can.do_set_mode = mscan_do_set_mode; | |
659 | ||
660 | for (i = 0; i < TX_QUEUE_SIZE; i++) { | |
661 | priv->tx_queue[i].id = i; | |
662 | priv->tx_queue[i].mask = 1 << i; | |
663 | } | |
664 | ||
665 | return dev; | |
666 | } | |
667 | EXPORT_SYMBOL_GPL(alloc_mscandev); | |
668 | ||
669 | MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>"); | |
670 | MODULE_LICENSE("GPL v2"); | |
671 | MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips"); |