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e0000163 CP |
1 | /* |
2 | * CAN bus driver for Microchip 251x CAN Controller with SPI Interface | |
3 | * | |
4 | * MCP2510 support and bug fixes by Christian Pellegrin | |
5 | * <chripell@evolware.org> | |
6 | * | |
7 | * Copyright 2009 Christian Pellegrin EVOL S.r.l. | |
8 | * | |
9 | * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. | |
10 | * Written under contract by: | |
11 | * Chris Elston, Katalix Systems, Ltd. | |
12 | * | |
13 | * Based on Microchip MCP251x CAN controller driver written by | |
14 | * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. | |
15 | * | |
16 | * Based on CAN bus driver for the CCAN controller written by | |
17 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix | |
18 | * - Simon Kallweit, intefo AG | |
19 | * Copyright 2007 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify | |
22 | * it under the terms of the version 2 of the GNU General Public License | |
23 | * as published by the Free Software Foundation | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
33 | * | |
34 | * | |
35 | * | |
36 | * Your platform definition file should specify something like: | |
37 | * | |
38 | * static struct mcp251x_platform_data mcp251x_info = { | |
39 | * .oscillator_frequency = 8000000, | |
40 | * .board_specific_setup = &mcp251x_setup, | |
41 | * .model = CAN_MCP251X_MCP2510, | |
42 | * .power_enable = mcp251x_power_enable, | |
43 | * .transceiver_enable = NULL, | |
44 | * }; | |
45 | * | |
46 | * static struct spi_board_info spi_board_info[] = { | |
47 | * { | |
48 | * .modalias = "mcp251x", | |
49 | * .platform_data = &mcp251x_info, | |
50 | * .irq = IRQ_EINT13, | |
51 | * .max_speed_hz = 2*1000*1000, | |
52 | * .chip_select = 2, | |
53 | * }, | |
54 | * }; | |
55 | * | |
56 | * Please see mcp251x.h for a description of the fields in | |
57 | * struct mcp251x_platform_data. | |
58 | * | |
59 | */ | |
60 | ||
e0000163 CP |
61 | #include <linux/can/core.h> |
62 | #include <linux/can/dev.h> | |
63 | #include <linux/can/platform/mcp251x.h> | |
64 | #include <linux/completion.h> | |
65 | #include <linux/delay.h> | |
66 | #include <linux/device.h> | |
67 | #include <linux/dma-mapping.h> | |
68 | #include <linux/freezer.h> | |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/io.h> | |
71 | #include <linux/kernel.h> | |
72 | #include <linux/module.h> | |
73 | #include <linux/netdevice.h> | |
74 | #include <linux/platform_device.h> | |
5a0e3ad6 | 75 | #include <linux/slab.h> |
e0000163 CP |
76 | #include <linux/spi/spi.h> |
77 | #include <linux/uaccess.h> | |
78 | ||
79 | /* SPI interface instruction set */ | |
80 | #define INSTRUCTION_WRITE 0x02 | |
81 | #define INSTRUCTION_READ 0x03 | |
82 | #define INSTRUCTION_BIT_MODIFY 0x05 | |
83 | #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) | |
84 | #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) | |
85 | #define INSTRUCTION_RESET 0xC0 | |
86 | ||
87 | /* MPC251x registers */ | |
88 | #define CANSTAT 0x0e | |
89 | #define CANCTRL 0x0f | |
90 | # define CANCTRL_REQOP_MASK 0xe0 | |
91 | # define CANCTRL_REQOP_CONF 0x80 | |
92 | # define CANCTRL_REQOP_LISTEN_ONLY 0x60 | |
93 | # define CANCTRL_REQOP_LOOPBACK 0x40 | |
94 | # define CANCTRL_REQOP_SLEEP 0x20 | |
95 | # define CANCTRL_REQOP_NORMAL 0x00 | |
96 | # define CANCTRL_OSM 0x08 | |
97 | # define CANCTRL_ABAT 0x10 | |
98 | #define TEC 0x1c | |
99 | #define REC 0x1d | |
100 | #define CNF1 0x2a | |
101 | # define CNF1_SJW_SHIFT 6 | |
102 | #define CNF2 0x29 | |
103 | # define CNF2_BTLMODE 0x80 | |
104 | # define CNF2_SAM 0x40 | |
105 | # define CNF2_PS1_SHIFT 3 | |
106 | #define CNF3 0x28 | |
107 | # define CNF3_SOF 0x08 | |
108 | # define CNF3_WAKFIL 0x04 | |
109 | # define CNF3_PHSEG2_MASK 0x07 | |
110 | #define CANINTE 0x2b | |
111 | # define CANINTE_MERRE 0x80 | |
112 | # define CANINTE_WAKIE 0x40 | |
113 | # define CANINTE_ERRIE 0x20 | |
114 | # define CANINTE_TX2IE 0x10 | |
115 | # define CANINTE_TX1IE 0x08 | |
116 | # define CANINTE_TX0IE 0x04 | |
117 | # define CANINTE_RX1IE 0x02 | |
118 | # define CANINTE_RX0IE 0x01 | |
119 | #define CANINTF 0x2c | |
120 | # define CANINTF_MERRF 0x80 | |
121 | # define CANINTF_WAKIF 0x40 | |
122 | # define CANINTF_ERRIF 0x20 | |
123 | # define CANINTF_TX2IF 0x10 | |
124 | # define CANINTF_TX1IF 0x08 | |
125 | # define CANINTF_TX0IF 0x04 | |
126 | # define CANINTF_RX1IF 0x02 | |
127 | # define CANINTF_RX0IF 0x01 | |
128 | #define EFLG 0x2d | |
129 | # define EFLG_EWARN 0x01 | |
130 | # define EFLG_RXWAR 0x02 | |
131 | # define EFLG_TXWAR 0x04 | |
132 | # define EFLG_RXEP 0x08 | |
133 | # define EFLG_TXEP 0x10 | |
134 | # define EFLG_TXBO 0x20 | |
135 | # define EFLG_RX0OVR 0x40 | |
136 | # define EFLG_RX1OVR 0x80 | |
137 | #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) | |
138 | # define TXBCTRL_ABTF 0x40 | |
139 | # define TXBCTRL_MLOA 0x20 | |
140 | # define TXBCTRL_TXERR 0x10 | |
141 | # define TXBCTRL_TXREQ 0x08 | |
142 | #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) | |
143 | # define SIDH_SHIFT 3 | |
144 | #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) | |
145 | # define SIDL_SID_MASK 7 | |
146 | # define SIDL_SID_SHIFT 5 | |
147 | # define SIDL_EXIDE_SHIFT 3 | |
148 | # define SIDL_EID_SHIFT 16 | |
149 | # define SIDL_EID_MASK 3 | |
150 | #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) | |
151 | #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) | |
152 | #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) | |
153 | # define DLC_RTR_SHIFT 6 | |
154 | #define TXBCTRL_OFF 0 | |
155 | #define TXBSIDH_OFF 1 | |
156 | #define TXBSIDL_OFF 2 | |
157 | #define TXBEID8_OFF 3 | |
158 | #define TXBEID0_OFF 4 | |
159 | #define TXBDLC_OFF 5 | |
160 | #define TXBDAT_OFF 6 | |
161 | #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) | |
162 | # define RXBCTRL_BUKT 0x04 | |
163 | # define RXBCTRL_RXM0 0x20 | |
164 | # define RXBCTRL_RXM1 0x40 | |
165 | #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) | |
166 | # define RXBSIDH_SHIFT 3 | |
167 | #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) | |
168 | # define RXBSIDL_IDE 0x08 | |
169 | # define RXBSIDL_EID 3 | |
170 | # define RXBSIDL_SHIFT 5 | |
171 | #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) | |
172 | #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) | |
173 | #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) | |
174 | # define RXBDLC_LEN_MASK 0x0f | |
175 | # define RXBDLC_RTR 0x40 | |
176 | #define RXBCTRL_OFF 0 | |
177 | #define RXBSIDH_OFF 1 | |
178 | #define RXBSIDL_OFF 2 | |
179 | #define RXBEID8_OFF 3 | |
180 | #define RXBEID0_OFF 4 | |
181 | #define RXBDLC_OFF 5 | |
182 | #define RXBDAT_OFF 6 | |
bf66f373 CP |
183 | #define RXFSIDH(n) ((n) * 4) |
184 | #define RXFSIDL(n) ((n) * 4 + 1) | |
185 | #define RXFEID8(n) ((n) * 4 + 2) | |
186 | #define RXFEID0(n) ((n) * 4 + 3) | |
187 | #define RXMSIDH(n) ((n) * 4 + 0x20) | |
188 | #define RXMSIDL(n) ((n) * 4 + 0x21) | |
189 | #define RXMEID8(n) ((n) * 4 + 0x22) | |
190 | #define RXMEID0(n) ((n) * 4 + 0x23) | |
e0000163 CP |
191 | |
192 | #define GET_BYTE(val, byte) \ | |
193 | (((val) >> ((byte) * 8)) & 0xff) | |
194 | #define SET_BYTE(val, byte) \ | |
195 | (((val) & 0xff) << ((byte) * 8)) | |
196 | ||
197 | /* | |
198 | * Buffer size required for the largest SPI transfer (i.e., reading a | |
199 | * frame) | |
200 | */ | |
201 | #define CAN_FRAME_MAX_DATA_LEN 8 | |
202 | #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) | |
203 | #define CAN_FRAME_MAX_BITS 128 | |
204 | ||
205 | #define TX_ECHO_SKB_MAX 1 | |
206 | ||
207 | #define DEVICE_NAME "mcp251x" | |
208 | ||
209 | static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ | |
210 | module_param(mcp251x_enable_dma, int, S_IRUGO); | |
211 | MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); | |
212 | ||
213 | static struct can_bittiming_const mcp251x_bittiming_const = { | |
214 | .name = DEVICE_NAME, | |
215 | .tseg1_min = 3, | |
216 | .tseg1_max = 16, | |
217 | .tseg2_min = 2, | |
218 | .tseg2_max = 8, | |
219 | .sjw_max = 4, | |
220 | .brp_min = 1, | |
221 | .brp_max = 64, | |
222 | .brp_inc = 1, | |
223 | }; | |
224 | ||
225 | struct mcp251x_priv { | |
226 | struct can_priv can; | |
227 | struct net_device *net; | |
228 | struct spi_device *spi; | |
229 | ||
bf66f373 CP |
230 | struct mutex mcp_lock; /* SPI device lock */ |
231 | ||
e0000163 CP |
232 | u8 *spi_tx_buf; |
233 | u8 *spi_rx_buf; | |
234 | dma_addr_t spi_tx_dma; | |
235 | dma_addr_t spi_rx_dma; | |
236 | ||
237 | struct sk_buff *tx_skb; | |
238 | int tx_len; | |
bf66f373 | 239 | |
e0000163 CP |
240 | struct workqueue_struct *wq; |
241 | struct work_struct tx_work; | |
bf66f373 CP |
242 | struct work_struct restart_work; |
243 | ||
e0000163 CP |
244 | int force_quit; |
245 | int after_suspend; | |
246 | #define AFTER_SUSPEND_UP 1 | |
247 | #define AFTER_SUSPEND_DOWN 2 | |
248 | #define AFTER_SUSPEND_POWER 4 | |
249 | #define AFTER_SUSPEND_RESTART 8 | |
250 | int restart_tx; | |
251 | }; | |
252 | ||
253 | static void mcp251x_clean(struct net_device *net) | |
254 | { | |
255 | struct mcp251x_priv *priv = netdev_priv(net); | |
256 | ||
bf66f373 CP |
257 | if (priv->tx_skb || priv->tx_len) |
258 | net->stats.tx_errors++; | |
e0000163 CP |
259 | if (priv->tx_skb) |
260 | dev_kfree_skb(priv->tx_skb); | |
261 | if (priv->tx_len) | |
262 | can_free_echo_skb(priv->net, 0); | |
263 | priv->tx_skb = NULL; | |
264 | priv->tx_len = 0; | |
265 | } | |
266 | ||
267 | /* | |
268 | * Note about handling of error return of mcp251x_spi_trans: accessing | |
269 | * registers via SPI is not really different conceptually than using | |
270 | * normal I/O assembler instructions, although it's much more | |
271 | * complicated from a practical POV. So it's not advisable to always | |
272 | * check the return value of this function. Imagine that every | |
273 | * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) | |
274 | * error();", it would be a great mess (well there are some situation | |
275 | * when exception handling C++ like could be useful after all). So we | |
276 | * just check that transfers are OK at the beginning of our | |
277 | * conversation with the chip and to avoid doing really nasty things | |
278 | * (like injecting bogus packets in the network stack). | |
279 | */ | |
280 | static int mcp251x_spi_trans(struct spi_device *spi, int len) | |
281 | { | |
282 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
283 | struct spi_transfer t = { | |
284 | .tx_buf = priv->spi_tx_buf, | |
285 | .rx_buf = priv->spi_rx_buf, | |
286 | .len = len, | |
287 | .cs_change = 0, | |
288 | }; | |
289 | struct spi_message m; | |
290 | int ret; | |
291 | ||
292 | spi_message_init(&m); | |
293 | ||
294 | if (mcp251x_enable_dma) { | |
295 | t.tx_dma = priv->spi_tx_dma; | |
296 | t.rx_dma = priv->spi_rx_dma; | |
297 | m.is_dma_mapped = 1; | |
298 | } | |
299 | ||
300 | spi_message_add_tail(&t, &m); | |
301 | ||
302 | ret = spi_sync(spi, &m); | |
303 | if (ret) | |
304 | dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); | |
305 | return ret; | |
306 | } | |
307 | ||
308 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) | |
309 | { | |
310 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
311 | u8 val = 0; | |
312 | ||
e0000163 CP |
313 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
314 | priv->spi_tx_buf[1] = reg; | |
315 | ||
316 | mcp251x_spi_trans(spi, 3); | |
317 | val = priv->spi_rx_buf[2]; | |
318 | ||
e0000163 CP |
319 | return val; |
320 | } | |
321 | ||
322 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) | |
323 | { | |
324 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
325 | ||
e0000163 CP |
326 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; |
327 | priv->spi_tx_buf[1] = reg; | |
328 | priv->spi_tx_buf[2] = val; | |
329 | ||
330 | mcp251x_spi_trans(spi, 3); | |
e0000163 CP |
331 | } |
332 | ||
333 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, | |
334 | u8 mask, uint8_t val) | |
335 | { | |
336 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
337 | ||
e0000163 CP |
338 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; |
339 | priv->spi_tx_buf[1] = reg; | |
340 | priv->spi_tx_buf[2] = mask; | |
341 | priv->spi_tx_buf[3] = val; | |
342 | ||
343 | mcp251x_spi_trans(spi, 4); | |
e0000163 CP |
344 | } |
345 | ||
346 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, | |
347 | int len, int tx_buf_idx) | |
348 | { | |
349 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
350 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
351 | ||
352 | if (pdata->model == CAN_MCP251X_MCP2510) { | |
353 | int i; | |
354 | ||
355 | for (i = 1; i < TXBDAT_OFF + len; i++) | |
356 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, | |
357 | buf[i]); | |
358 | } else { | |
e0000163 CP |
359 | memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); |
360 | mcp251x_spi_trans(spi, TXBDAT_OFF + len); | |
e0000163 CP |
361 | } |
362 | } | |
363 | ||
364 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, | |
365 | int tx_buf_idx) | |
366 | { | |
367 | u32 sid, eid, exide, rtr; | |
368 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
369 | ||
370 | exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ | |
371 | if (exide) | |
372 | sid = (frame->can_id & CAN_EFF_MASK) >> 18; | |
373 | else | |
374 | sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ | |
375 | eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ | |
376 | rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ | |
377 | ||
378 | buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); | |
379 | buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; | |
380 | buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | | |
381 | (exide << SIDL_EXIDE_SHIFT) | | |
382 | ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); | |
383 | buf[TXBEID8_OFF] = GET_BYTE(eid, 1); | |
384 | buf[TXBEID0_OFF] = GET_BYTE(eid, 0); | |
385 | buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; | |
386 | memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); | |
387 | mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); | |
388 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx), TXBCTRL_TXREQ); | |
389 | } | |
390 | ||
391 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, | |
392 | int buf_idx) | |
393 | { | |
394 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
395 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
396 | ||
397 | if (pdata->model == CAN_MCP251X_MCP2510) { | |
398 | int i, len; | |
399 | ||
400 | for (i = 1; i < RXBDAT_OFF; i++) | |
401 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
c7cd606f OH |
402 | |
403 | len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); | |
e0000163 CP |
404 | for (; i < (RXBDAT_OFF + len); i++) |
405 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
406 | } else { | |
e0000163 CP |
407 | priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); |
408 | mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); | |
409 | memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); | |
e0000163 CP |
410 | } |
411 | } | |
412 | ||
413 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) | |
414 | { | |
415 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
416 | struct sk_buff *skb; | |
417 | struct can_frame *frame; | |
418 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
419 | ||
420 | skb = alloc_can_skb(priv->net, &frame); | |
421 | if (!skb) { | |
422 | dev_err(&spi->dev, "cannot allocate RX skb\n"); | |
423 | priv->net->stats.rx_dropped++; | |
424 | return; | |
425 | } | |
426 | ||
427 | mcp251x_hw_rx_frame(spi, buf, buf_idx); | |
428 | if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { | |
429 | /* Extended ID format */ | |
430 | frame->can_id = CAN_EFF_FLAG; | |
431 | frame->can_id |= | |
432 | /* Extended ID part */ | |
433 | SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | | |
434 | SET_BYTE(buf[RXBEID8_OFF], 1) | | |
435 | SET_BYTE(buf[RXBEID0_OFF], 0) | | |
436 | /* Standard ID part */ | |
437 | (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
438 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); | |
439 | /* Remote transmission request */ | |
440 | if (buf[RXBDLC_OFF] & RXBDLC_RTR) | |
441 | frame->can_id |= CAN_RTR_FLAG; | |
442 | } else { | |
443 | /* Standard ID format */ | |
444 | frame->can_id = | |
445 | (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
446 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); | |
447 | } | |
448 | /* Data length */ | |
c7cd606f | 449 | frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); |
e0000163 CP |
450 | memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); |
451 | ||
452 | priv->net->stats.rx_packets++; | |
453 | priv->net->stats.rx_bytes += frame->can_dlc; | |
454 | netif_rx(skb); | |
455 | } | |
456 | ||
457 | static void mcp251x_hw_sleep(struct spi_device *spi) | |
458 | { | |
459 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); | |
460 | } | |
461 | ||
e0000163 CP |
462 | static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, |
463 | struct net_device *net) | |
464 | { | |
465 | struct mcp251x_priv *priv = netdev_priv(net); | |
466 | struct spi_device *spi = priv->spi; | |
467 | ||
468 | if (priv->tx_skb || priv->tx_len) { | |
469 | dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); | |
e0000163 CP |
470 | return NETDEV_TX_BUSY; |
471 | } | |
472 | ||
3ccd4c61 | 473 | if (can_dropped_invalid_skb(net, skb)) |
e0000163 | 474 | return NETDEV_TX_OK; |
e0000163 CP |
475 | |
476 | netif_stop_queue(net); | |
477 | priv->tx_skb = skb; | |
478 | net->trans_start = jiffies; | |
479 | queue_work(priv->wq, &priv->tx_work); | |
480 | ||
481 | return NETDEV_TX_OK; | |
482 | } | |
483 | ||
484 | static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) | |
485 | { | |
486 | struct mcp251x_priv *priv = netdev_priv(net); | |
487 | ||
488 | switch (mode) { | |
489 | case CAN_MODE_START: | |
bf66f373 | 490 | mcp251x_clean(net); |
e0000163 CP |
491 | /* We have to delay work since SPI I/O may sleep */ |
492 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
493 | priv->restart_tx = 1; | |
494 | if (priv->can.restart_ms == 0) | |
495 | priv->after_suspend = AFTER_SUSPEND_RESTART; | |
bf66f373 | 496 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
497 | break; |
498 | default: | |
499 | return -EOPNOTSUPP; | |
500 | } | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
bf66f373 | 505 | static int mcp251x_set_normal_mode(struct spi_device *spi) |
e0000163 CP |
506 | { |
507 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
508 | unsigned long timeout; | |
509 | ||
510 | /* Enable interrupts */ | |
511 | mcp251x_write_reg(spi, CANINTE, | |
512 | CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | | |
bf66f373 | 513 | CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); |
e0000163 CP |
514 | |
515 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
516 | /* Put device into loopback mode */ | |
517 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); | |
ad72c347 CP |
518 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
519 | /* Put device into listen-only mode */ | |
520 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); | |
e0000163 CP |
521 | } else { |
522 | /* Put device into normal mode */ | |
bf66f373 | 523 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); |
e0000163 CP |
524 | |
525 | /* Wait for the device to enter normal mode */ | |
526 | timeout = jiffies + HZ; | |
527 | while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { | |
528 | schedule(); | |
529 | if (time_after(jiffies, timeout)) { | |
530 | dev_err(&spi->dev, "MCP251x didn't" | |
531 | " enter in normal mode\n"); | |
bf66f373 | 532 | return -EBUSY; |
e0000163 CP |
533 | } |
534 | } | |
535 | } | |
536 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
bf66f373 | 537 | return 0; |
e0000163 CP |
538 | } |
539 | ||
540 | static int mcp251x_do_set_bittiming(struct net_device *net) | |
541 | { | |
542 | struct mcp251x_priv *priv = netdev_priv(net); | |
543 | struct can_bittiming *bt = &priv->can.bittiming; | |
544 | struct spi_device *spi = priv->spi; | |
545 | ||
546 | mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | | |
547 | (bt->brp - 1)); | |
548 | mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | | |
549 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? | |
550 | CNF2_SAM : 0) | | |
551 | ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | | |
552 | (bt->prop_seg - 1)); | |
553 | mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, | |
554 | (bt->phase_seg2 - 1)); | |
555 | dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", | |
556 | mcp251x_read_reg(spi, CNF1), | |
557 | mcp251x_read_reg(spi, CNF2), | |
558 | mcp251x_read_reg(spi, CNF3)); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv, | |
564 | struct spi_device *spi) | |
565 | { | |
615534bc | 566 | mcp251x_do_set_bittiming(net); |
e0000163 | 567 | |
bf66f373 CP |
568 | mcp251x_write_reg(spi, RXBCTRL(0), |
569 | RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
570 | mcp251x_write_reg(spi, RXBCTRL(1), | |
571 | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
e0000163 CP |
572 | return 0; |
573 | } | |
574 | ||
bf66f373 | 575 | static int mcp251x_hw_reset(struct spi_device *spi) |
e0000163 CP |
576 | { |
577 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
578 | int ret; | |
bf66f373 | 579 | unsigned long timeout; |
e0000163 CP |
580 | |
581 | priv->spi_tx_buf[0] = INSTRUCTION_RESET; | |
e0000163 | 582 | ret = spi_write(spi, priv->spi_tx_buf, 1); |
bf66f373 | 583 | if (ret) { |
e0000163 | 584 | dev_err(&spi->dev, "reset failed: ret = %d\n", ret); |
bf66f373 CP |
585 | return -EIO; |
586 | } | |
587 | ||
e0000163 | 588 | /* Wait for reset to finish */ |
bf66f373 | 589 | timeout = jiffies + HZ; |
e0000163 | 590 | mdelay(10); |
bf66f373 CP |
591 | while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) |
592 | != CANCTRL_REQOP_CONF) { | |
593 | schedule(); | |
594 | if (time_after(jiffies, timeout)) { | |
595 | dev_err(&spi->dev, "MCP251x didn't" | |
596 | " enter in conf mode after reset\n"); | |
597 | return -EBUSY; | |
598 | } | |
599 | } | |
600 | return 0; | |
e0000163 CP |
601 | } |
602 | ||
603 | static int mcp251x_hw_probe(struct spi_device *spi) | |
604 | { | |
605 | int st1, st2; | |
606 | ||
607 | mcp251x_hw_reset(spi); | |
608 | ||
609 | /* | |
610 | * Please note that these are "magic values" based on after | |
611 | * reset defaults taken from data sheet which allows us to see | |
612 | * if we really have a chip on the bus (we avoid common all | |
613 | * zeroes or all ones situations) | |
614 | */ | |
615 | st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE; | |
616 | st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17; | |
617 | ||
618 | dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2); | |
619 | ||
620 | /* Check for power up default values */ | |
621 | return (st1 == 0x80 && st2 == 0x07) ? 1 : 0; | |
622 | } | |
623 | ||
bf66f373 | 624 | static void mcp251x_open_clean(struct net_device *net) |
e0000163 CP |
625 | { |
626 | struct mcp251x_priv *priv = netdev_priv(net); | |
627 | struct spi_device *spi = priv->spi; | |
628 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
615534bc | 629 | |
bf66f373 CP |
630 | free_irq(spi->irq, priv); |
631 | mcp251x_hw_sleep(spi); | |
e0000163 | 632 | if (pdata->transceiver_enable) |
bf66f373 CP |
633 | pdata->transceiver_enable(0); |
634 | close_candev(net); | |
e0000163 CP |
635 | } |
636 | ||
637 | static int mcp251x_stop(struct net_device *net) | |
638 | { | |
639 | struct mcp251x_priv *priv = netdev_priv(net); | |
640 | struct spi_device *spi = priv->spi; | |
641 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
642 | ||
643 | close_candev(net); | |
644 | ||
bf66f373 CP |
645 | priv->force_quit = 1; |
646 | free_irq(spi->irq, priv); | |
647 | destroy_workqueue(priv->wq); | |
648 | priv->wq = NULL; | |
649 | ||
650 | mutex_lock(&priv->mcp_lock); | |
651 | ||
e0000163 CP |
652 | /* Disable and clear pending interrupts */ |
653 | mcp251x_write_reg(spi, CANINTE, 0x00); | |
654 | mcp251x_write_reg(spi, CANINTF, 0x00); | |
655 | ||
e0000163 | 656 | mcp251x_write_reg(spi, TXBCTRL(0), 0); |
bf66f373 | 657 | mcp251x_clean(net); |
e0000163 CP |
658 | |
659 | mcp251x_hw_sleep(spi); | |
660 | ||
661 | if (pdata->transceiver_enable) | |
662 | pdata->transceiver_enable(0); | |
663 | ||
664 | priv->can.state = CAN_STATE_STOPPED; | |
665 | ||
bf66f373 CP |
666 | mutex_unlock(&priv->mcp_lock); |
667 | ||
e0000163 CP |
668 | return 0; |
669 | } | |
670 | ||
bf66f373 CP |
671 | static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) |
672 | { | |
673 | struct sk_buff *skb; | |
674 | struct can_frame *frame; | |
675 | ||
676 | skb = alloc_can_err_skb(net, &frame); | |
677 | if (skb) { | |
678 | frame->can_id = can_id; | |
679 | frame->data[1] = data1; | |
680 | netif_rx(skb); | |
681 | } else { | |
682 | dev_err(&net->dev, | |
683 | "cannot allocate error skb\n"); | |
684 | } | |
685 | } | |
686 | ||
e0000163 CP |
687 | static void mcp251x_tx_work_handler(struct work_struct *ws) |
688 | { | |
689 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
690 | tx_work); | |
691 | struct spi_device *spi = priv->spi; | |
692 | struct net_device *net = priv->net; | |
693 | struct can_frame *frame; | |
694 | ||
bf66f373 | 695 | mutex_lock(&priv->mcp_lock); |
e0000163 | 696 | if (priv->tx_skb) { |
e0000163 CP |
697 | if (priv->can.state == CAN_STATE_BUS_OFF) { |
698 | mcp251x_clean(net); | |
bf66f373 CP |
699 | } else { |
700 | frame = (struct can_frame *)priv->tx_skb->data; | |
701 | ||
702 | if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) | |
703 | frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; | |
704 | mcp251x_hw_tx(spi, frame, 0); | |
705 | priv->tx_len = 1 + frame->can_dlc; | |
706 | can_put_echo_skb(priv->tx_skb, net, 0); | |
707 | priv->tx_skb = NULL; | |
e0000163 | 708 | } |
e0000163 | 709 | } |
bf66f373 | 710 | mutex_unlock(&priv->mcp_lock); |
e0000163 CP |
711 | } |
712 | ||
bf66f373 | 713 | static void mcp251x_restart_work_handler(struct work_struct *ws) |
e0000163 CP |
714 | { |
715 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
bf66f373 | 716 | restart_work); |
e0000163 CP |
717 | struct spi_device *spi = priv->spi; |
718 | struct net_device *net = priv->net; | |
e0000163 | 719 | |
bf66f373 | 720 | mutex_lock(&priv->mcp_lock); |
e0000163 CP |
721 | if (priv->after_suspend) { |
722 | mdelay(10); | |
723 | mcp251x_hw_reset(spi); | |
724 | mcp251x_setup(net, priv, spi); | |
725 | if (priv->after_suspend & AFTER_SUSPEND_RESTART) { | |
726 | mcp251x_set_normal_mode(spi); | |
727 | } else if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
728 | netif_device_attach(net); | |
bf66f373 | 729 | mcp251x_clean(net); |
e0000163 | 730 | mcp251x_set_normal_mode(spi); |
bf66f373 | 731 | netif_wake_queue(net); |
e0000163 CP |
732 | } else { |
733 | mcp251x_hw_sleep(spi); | |
734 | } | |
735 | priv->after_suspend = 0; | |
bf66f373 | 736 | priv->force_quit = 0; |
e0000163 CP |
737 | } |
738 | ||
bf66f373 CP |
739 | if (priv->restart_tx) { |
740 | priv->restart_tx = 0; | |
741 | mcp251x_write_reg(spi, TXBCTRL(0), 0); | |
742 | mcp251x_clean(net); | |
743 | netif_wake_queue(net); | |
744 | mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); | |
745 | } | |
746 | mutex_unlock(&priv->mcp_lock); | |
747 | } | |
e0000163 | 748 | |
bf66f373 CP |
749 | static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) |
750 | { | |
751 | struct mcp251x_priv *priv = dev_id; | |
752 | struct spi_device *spi = priv->spi; | |
753 | struct net_device *net = priv->net; | |
e0000163 | 754 | |
bf66f373 CP |
755 | mutex_lock(&priv->mcp_lock); |
756 | while (!priv->force_quit) { | |
757 | enum can_state new_state; | |
758 | u8 intf = mcp251x_read_reg(spi, CANINTF); | |
759 | u8 eflag; | |
760 | int can_id = 0, data1 = 0; | |
e0000163 | 761 | |
bf66f373 CP |
762 | if (intf & CANINTF_RX0IF) { |
763 | mcp251x_hw_rx(spi, 0); | |
764 | /* Free one buffer ASAP */ | |
765 | mcp251x_write_bits(spi, CANINTF, intf & CANINTF_RX0IF, | |
766 | 0x00); | |
e0000163 CP |
767 | } |
768 | ||
bf66f373 CP |
769 | if (intf & CANINTF_RX1IF) |
770 | mcp251x_hw_rx(spi, 1); | |
e0000163 | 771 | |
e0000163 CP |
772 | mcp251x_write_bits(spi, CANINTF, intf, 0x00); |
773 | ||
bf66f373 CP |
774 | eflag = mcp251x_read_reg(spi, EFLG); |
775 | mcp251x_write_reg(spi, EFLG, 0x00); | |
776 | ||
e0000163 CP |
777 | /* Update can state */ |
778 | if (eflag & EFLG_TXBO) { | |
779 | new_state = CAN_STATE_BUS_OFF; | |
780 | can_id |= CAN_ERR_BUSOFF; | |
781 | } else if (eflag & EFLG_TXEP) { | |
782 | new_state = CAN_STATE_ERROR_PASSIVE; | |
783 | can_id |= CAN_ERR_CRTL; | |
784 | data1 |= CAN_ERR_CRTL_TX_PASSIVE; | |
785 | } else if (eflag & EFLG_RXEP) { | |
786 | new_state = CAN_STATE_ERROR_PASSIVE; | |
787 | can_id |= CAN_ERR_CRTL; | |
788 | data1 |= CAN_ERR_CRTL_RX_PASSIVE; | |
789 | } else if (eflag & EFLG_TXWAR) { | |
790 | new_state = CAN_STATE_ERROR_WARNING; | |
791 | can_id |= CAN_ERR_CRTL; | |
792 | data1 |= CAN_ERR_CRTL_TX_WARNING; | |
793 | } else if (eflag & EFLG_RXWAR) { | |
794 | new_state = CAN_STATE_ERROR_WARNING; | |
795 | can_id |= CAN_ERR_CRTL; | |
796 | data1 |= CAN_ERR_CRTL_RX_WARNING; | |
797 | } else { | |
798 | new_state = CAN_STATE_ERROR_ACTIVE; | |
799 | } | |
800 | ||
801 | /* Update can state statistics */ | |
802 | switch (priv->can.state) { | |
803 | case CAN_STATE_ERROR_ACTIVE: | |
804 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
805 | new_state <= CAN_STATE_BUS_OFF) | |
806 | priv->can.can_stats.error_warning++; | |
807 | case CAN_STATE_ERROR_WARNING: /* fallthrough */ | |
808 | if (new_state >= CAN_STATE_ERROR_PASSIVE && | |
809 | new_state <= CAN_STATE_BUS_OFF) | |
810 | priv->can.can_stats.error_passive++; | |
811 | break; | |
812 | default: | |
813 | break; | |
814 | } | |
815 | priv->can.state = new_state; | |
816 | ||
bf66f373 CP |
817 | if (intf & CANINTF_ERRIF) { |
818 | /* Handle overflow counters */ | |
819 | if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { | |
820 | if (eflag & EFLG_RX0OVR) | |
821 | net->stats.rx_over_errors++; | |
822 | if (eflag & EFLG_RX1OVR) | |
823 | net->stats.rx_over_errors++; | |
824 | can_id |= CAN_ERR_CRTL; | |
825 | data1 |= CAN_ERR_CRTL_RX_OVERFLOW; | |
e0000163 | 826 | } |
bf66f373 | 827 | mcp251x_error_skb(net, can_id, data1); |
e0000163 CP |
828 | } |
829 | ||
830 | if (priv->can.state == CAN_STATE_BUS_OFF) { | |
831 | if (priv->can.restart_ms == 0) { | |
bf66f373 | 832 | priv->force_quit = 1; |
e0000163 CP |
833 | can_bus_off(net); |
834 | mcp251x_hw_sleep(spi); | |
bf66f373 | 835 | break; |
e0000163 CP |
836 | } |
837 | } | |
838 | ||
839 | if (intf == 0) | |
840 | break; | |
841 | ||
e0000163 CP |
842 | if (intf & (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)) { |
843 | net->stats.tx_packets++; | |
844 | net->stats.tx_bytes += priv->tx_len - 1; | |
845 | if (priv->tx_len) { | |
846 | can_get_echo_skb(net, 0); | |
847 | priv->tx_len = 0; | |
848 | } | |
849 | netif_wake_queue(net); | |
850 | } | |
851 | ||
bf66f373 CP |
852 | } |
853 | mutex_unlock(&priv->mcp_lock); | |
854 | return IRQ_HANDLED; | |
855 | } | |
e0000163 | 856 | |
bf66f373 CP |
857 | static int mcp251x_open(struct net_device *net) |
858 | { | |
859 | struct mcp251x_priv *priv = netdev_priv(net); | |
860 | struct spi_device *spi = priv->spi; | |
861 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
862 | int ret; | |
863 | ||
864 | ret = open_candev(net); | |
865 | if (ret) { | |
866 | dev_err(&spi->dev, "unable to set initial baudrate!\n"); | |
867 | return ret; | |
868 | } | |
869 | ||
870 | mutex_lock(&priv->mcp_lock); | |
871 | if (pdata->transceiver_enable) | |
872 | pdata->transceiver_enable(1); | |
873 | ||
874 | priv->force_quit = 0; | |
875 | priv->tx_skb = NULL; | |
876 | priv->tx_len = 0; | |
877 | ||
878 | ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, | |
879 | IRQF_TRIGGER_FALLING, DEVICE_NAME, priv); | |
880 | if (ret) { | |
881 | dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); | |
882 | if (pdata->transceiver_enable) | |
883 | pdata->transceiver_enable(0); | |
884 | close_candev(net); | |
885 | goto open_unlock; | |
886 | } | |
887 | ||
888 | priv->wq = create_freezeable_workqueue("mcp251x_wq"); | |
889 | INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); | |
890 | INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); | |
891 | ||
892 | ret = mcp251x_hw_reset(spi); | |
893 | if (ret) { | |
894 | mcp251x_open_clean(net); | |
895 | goto open_unlock; | |
896 | } | |
897 | ret = mcp251x_setup(net, priv, spi); | |
898 | if (ret) { | |
899 | mcp251x_open_clean(net); | |
900 | goto open_unlock; | |
e0000163 | 901 | } |
bf66f373 CP |
902 | ret = mcp251x_set_normal_mode(spi); |
903 | if (ret) { | |
904 | mcp251x_open_clean(net); | |
905 | goto open_unlock; | |
906 | } | |
907 | netif_wake_queue(net); | |
908 | ||
909 | open_unlock: | |
910 | mutex_unlock(&priv->mcp_lock); | |
911 | return ret; | |
e0000163 CP |
912 | } |
913 | ||
914 | static const struct net_device_ops mcp251x_netdev_ops = { | |
915 | .ndo_open = mcp251x_open, | |
916 | .ndo_stop = mcp251x_stop, | |
917 | .ndo_start_xmit = mcp251x_hard_start_xmit, | |
918 | }; | |
919 | ||
920 | static int __devinit mcp251x_can_probe(struct spi_device *spi) | |
921 | { | |
922 | struct net_device *net; | |
923 | struct mcp251x_priv *priv; | |
924 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
e446630c | 925 | int model = spi_get_device_id(spi)->driver_data; |
e0000163 CP |
926 | int ret = -ENODEV; |
927 | ||
928 | if (!pdata) | |
929 | /* Platform data is required for osc freq */ | |
930 | goto error_out; | |
931 | ||
e446630c MZ |
932 | if (model) |
933 | pdata->model = model; | |
934 | ||
e0000163 CP |
935 | /* Allocate can/net device */ |
936 | net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); | |
937 | if (!net) { | |
938 | ret = -ENOMEM; | |
939 | goto error_alloc; | |
940 | } | |
941 | ||
942 | net->netdev_ops = &mcp251x_netdev_ops; | |
943 | net->flags |= IFF_ECHO; | |
944 | ||
945 | priv = netdev_priv(net); | |
946 | priv->can.bittiming_const = &mcp251x_bittiming_const; | |
947 | priv->can.do_set_mode = mcp251x_do_set_mode; | |
948 | priv->can.clock.freq = pdata->oscillator_frequency / 2; | |
ad72c347 CP |
949 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | |
950 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; | |
e0000163 CP |
951 | priv->net = net; |
952 | dev_set_drvdata(&spi->dev, priv); | |
953 | ||
954 | priv->spi = spi; | |
bf66f373 | 955 | mutex_init(&priv->mcp_lock); |
e0000163 CP |
956 | |
957 | /* If requested, allocate DMA buffers */ | |
958 | if (mcp251x_enable_dma) { | |
959 | spi->dev.coherent_dma_mask = ~0; | |
960 | ||
961 | /* | |
962 | * Minimum coherent DMA allocation is PAGE_SIZE, so allocate | |
963 | * that much and share it between Tx and Rx DMA buffers. | |
964 | */ | |
965 | priv->spi_tx_buf = dma_alloc_coherent(&spi->dev, | |
966 | PAGE_SIZE, | |
967 | &priv->spi_tx_dma, | |
968 | GFP_DMA); | |
969 | ||
970 | if (priv->spi_tx_buf) { | |
971 | priv->spi_rx_buf = (u8 *)(priv->spi_tx_buf + | |
972 | (PAGE_SIZE / 2)); | |
973 | priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + | |
974 | (PAGE_SIZE / 2)); | |
975 | } else { | |
976 | /* Fall back to non-DMA */ | |
977 | mcp251x_enable_dma = 0; | |
978 | } | |
979 | } | |
980 | ||
981 | /* Allocate non-DMA buffers */ | |
982 | if (!mcp251x_enable_dma) { | |
983 | priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
984 | if (!priv->spi_tx_buf) { | |
985 | ret = -ENOMEM; | |
986 | goto error_tx_buf; | |
987 | } | |
988 | priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL); | |
ce739b47 | 989 | if (!priv->spi_rx_buf) { |
e0000163 CP |
990 | ret = -ENOMEM; |
991 | goto error_rx_buf; | |
992 | } | |
993 | } | |
994 | ||
995 | if (pdata->power_enable) | |
996 | pdata->power_enable(1); | |
997 | ||
998 | /* Call out to platform specific setup */ | |
999 | if (pdata->board_specific_setup) | |
1000 | pdata->board_specific_setup(spi); | |
1001 | ||
1002 | SET_NETDEV_DEV(net, &spi->dev); | |
1003 | ||
e0000163 CP |
1004 | /* Configure the SPI bus */ |
1005 | spi->mode = SPI_MODE_0; | |
1006 | spi->bits_per_word = 8; | |
1007 | spi_setup(spi); | |
1008 | ||
bf66f373 | 1009 | /* Here is OK to not lock the MCP, no one knows about it yet */ |
e0000163 CP |
1010 | if (!mcp251x_hw_probe(spi)) { |
1011 | dev_info(&spi->dev, "Probe failed\n"); | |
1012 | goto error_probe; | |
1013 | } | |
1014 | mcp251x_hw_sleep(spi); | |
1015 | ||
1016 | if (pdata->transceiver_enable) | |
1017 | pdata->transceiver_enable(0); | |
1018 | ||
1019 | ret = register_candev(net); | |
1020 | if (!ret) { | |
1021 | dev_info(&spi->dev, "probed\n"); | |
1022 | return ret; | |
1023 | } | |
1024 | error_probe: | |
1025 | if (!mcp251x_enable_dma) | |
1026 | kfree(priv->spi_rx_buf); | |
1027 | error_rx_buf: | |
1028 | if (!mcp251x_enable_dma) | |
1029 | kfree(priv->spi_tx_buf); | |
1030 | error_tx_buf: | |
1031 | free_candev(net); | |
1032 | if (mcp251x_enable_dma) | |
1033 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1034 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1035 | error_alloc: | |
1036 | if (pdata->power_enable) | |
1037 | pdata->power_enable(0); | |
1038 | dev_err(&spi->dev, "probe failed\n"); | |
1039 | error_out: | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | static int __devexit mcp251x_can_remove(struct spi_device *spi) | |
1044 | { | |
1045 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1046 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1047 | struct net_device *net = priv->net; | |
1048 | ||
1049 | unregister_candev(net); | |
1050 | free_candev(net); | |
1051 | ||
e0000163 CP |
1052 | if (mcp251x_enable_dma) { |
1053 | dma_free_coherent(&spi->dev, PAGE_SIZE, | |
1054 | priv->spi_tx_buf, priv->spi_tx_dma); | |
1055 | } else { | |
1056 | kfree(priv->spi_tx_buf); | |
1057 | kfree(priv->spi_rx_buf); | |
1058 | } | |
1059 | ||
1060 | if (pdata->power_enable) | |
1061 | pdata->power_enable(0); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | #ifdef CONFIG_PM | |
1067 | static int mcp251x_can_suspend(struct spi_device *spi, pm_message_t state) | |
1068 | { | |
1069 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1070 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1071 | struct net_device *net = priv->net; | |
1072 | ||
bf66f373 CP |
1073 | priv->force_quit = 1; |
1074 | disable_irq(spi->irq); | |
1075 | /* | |
1076 | * Note: at this point neither IST nor workqueues are running. | |
1077 | * open/stop cannot be called anyway so locking is not needed | |
1078 | */ | |
e0000163 CP |
1079 | if (netif_running(net)) { |
1080 | netif_device_detach(net); | |
1081 | ||
1082 | mcp251x_hw_sleep(spi); | |
1083 | if (pdata->transceiver_enable) | |
1084 | pdata->transceiver_enable(0); | |
1085 | priv->after_suspend = AFTER_SUSPEND_UP; | |
1086 | } else { | |
1087 | priv->after_suspend = AFTER_SUSPEND_DOWN; | |
1088 | } | |
1089 | ||
1090 | if (pdata->power_enable) { | |
1091 | pdata->power_enable(0); | |
1092 | priv->after_suspend |= AFTER_SUSPEND_POWER; | |
1093 | } | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | static int mcp251x_can_resume(struct spi_device *spi) | |
1099 | { | |
1100 | struct mcp251x_platform_data *pdata = spi->dev.platform_data; | |
1101 | struct mcp251x_priv *priv = dev_get_drvdata(&spi->dev); | |
1102 | ||
1103 | if (priv->after_suspend & AFTER_SUSPEND_POWER) { | |
1104 | pdata->power_enable(1); | |
bf66f373 | 1105 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1106 | } else { |
1107 | if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
1108 | if (pdata->transceiver_enable) | |
1109 | pdata->transceiver_enable(1); | |
bf66f373 | 1110 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
1111 | } else { |
1112 | priv->after_suspend = 0; | |
1113 | } | |
1114 | } | |
bf66f373 CP |
1115 | priv->force_quit = 0; |
1116 | enable_irq(spi->irq); | |
e0000163 CP |
1117 | return 0; |
1118 | } | |
1119 | #else | |
1120 | #define mcp251x_can_suspend NULL | |
1121 | #define mcp251x_can_resume NULL | |
1122 | #endif | |
1123 | ||
e446630c MZ |
1124 | static struct spi_device_id mcp251x_id_table[] = { |
1125 | { "mcp251x", 0 /* Use pdata.model */ }, | |
1126 | { "mcp2510", CAN_MCP251X_MCP2510 }, | |
1127 | { "mcp2515", CAN_MCP251X_MCP2515 }, | |
1128 | { }, | |
1129 | }; | |
1130 | ||
1131 | MODULE_DEVICE_TABLE(spi, mcp251x_id_table); | |
1132 | ||
e0000163 CP |
1133 | static struct spi_driver mcp251x_can_driver = { |
1134 | .driver = { | |
1135 | .name = DEVICE_NAME, | |
1136 | .bus = &spi_bus_type, | |
1137 | .owner = THIS_MODULE, | |
1138 | }, | |
1139 | ||
e446630c | 1140 | .id_table = mcp251x_id_table, |
e0000163 CP |
1141 | .probe = mcp251x_can_probe, |
1142 | .remove = __devexit_p(mcp251x_can_remove), | |
1143 | .suspend = mcp251x_can_suspend, | |
1144 | .resume = mcp251x_can_resume, | |
1145 | }; | |
1146 | ||
1147 | static int __init mcp251x_can_init(void) | |
1148 | { | |
1149 | return spi_register_driver(&mcp251x_can_driver); | |
1150 | } | |
1151 | ||
1152 | static void __exit mcp251x_can_exit(void) | |
1153 | { | |
1154 | spi_unregister_driver(&mcp251x_can_driver); | |
1155 | } | |
1156 | ||
1157 | module_init(mcp251x_can_init); | |
1158 | module_exit(mcp251x_can_exit); | |
1159 | ||
1160 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " | |
1161 | "Christian Pellegrin <chripell@evolware.org>"); | |
1162 | MODULE_DESCRIPTION("Microchip 251x CAN driver"); | |
1163 | MODULE_LICENSE("GPL v2"); |