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bnx2x, cnic, bnx2i: use new FW/HSI
[net-next-2.6.git] / drivers / net / bnx2x / bnx2x_stats.c
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6c719d00
DK		 1/* bnx2x_stats.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17 #include "bnx2x_cmn.h"
18 #include "bnx2x_stats.h"
19
20/* Statistics */
21
22/****************************************************************************
23* Macros
24****************************************************************************/
25
26/* sum[hi:lo] += add[hi:lo] */
27#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
28 do { \
29 s_lo += a_lo; \
30 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
31 } while (0)
32
33/* difference = minuend - subtrahend */
34#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
35 do { \
36 if (m_lo < s_lo) { \
37 /* underflow */ \
38 d_hi = m_hi - s_hi; \
39 if (d_hi > 0) { \
40 /* we can 'loan' 1 */ \
41 d_hi--; \
42 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
43 } else { \
44 /* m_hi <= s_hi */ \
45 d_hi = 0; \
46 d_lo = 0; \
47 } \
48 } else { \
49 /* m_lo >= s_lo */ \
50 if (m_hi < s_hi) { \
51 d_hi = 0; \
52 d_lo = 0; \
53 } else { \
54 /* m_hi >= s_hi */ \
55 d_hi = m_hi - s_hi; \
56 d_lo = m_lo - s_lo; \
57 } \
58 } \
59 } while (0)
60
61#define UPDATE_STAT64(s, t) \
62 do { \
63 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
64 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
65 pstats->mac_stx[0].t##_hi = new->s##_hi; \
66 pstats->mac_stx[0].t##_lo = new->s##_lo; \
67 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
68 pstats->mac_stx[1].t##_lo, diff.lo); \
69 } while (0)
70
71#define UPDATE_STAT64_NIG(s, t) \
72 do { \
73 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
74 diff.lo, new->s##_lo, old->s##_lo); \
75 ADD_64(estats->t##_hi, diff.hi, \
76 estats->t##_lo, diff.lo); \
77 } while (0)
78
79/* sum[hi:lo] += add */
80#define ADD_EXTEND_64(s_hi, s_lo, a) \
81 do { \
82 s_lo += a; \
83 s_hi += (s_lo < a) ? 1 : 0; \
84 } while (0)
85
86#define UPDATE_EXTEND_STAT(s) \
87 do { \
88 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
89 pstats->mac_stx[1].s##_lo, \
90 new->s); \
91 } while (0)
92
93#define UPDATE_EXTEND_TSTAT(s, t) \
94 do { \
95 diff = le32_to_cpu(tclient->s) - le32_to_cpu(old_tclient->s); \
96 old_tclient->s = tclient->s; \
97 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
98 } while (0)
99
100#define UPDATE_EXTEND_USTAT(s, t) \
101 do { \
102 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
103 old_uclient->s = uclient->s; \
104 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
105 } while (0)
106
107#define UPDATE_EXTEND_XSTAT(s, t) \
108 do { \
109 diff = le32_to_cpu(xclient->s) - le32_to_cpu(old_xclient->s); \
110 old_xclient->s = xclient->s; \
111 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
112 } while (0)
113
114/* minuend -= subtrahend */
115#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
116 do { \
117 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
118 } while (0)
119
120/* minuend[hi:lo] -= subtrahend */
121#define SUB_EXTEND_64(m_hi, m_lo, s) \
122 do { \
123 SUB_64(m_hi, 0, m_lo, s); \
124 } while (0)
125
126#define SUB_EXTEND_USTAT(s, t) \
127 do { \
128 diff = le32_to_cpu(uclient->s) - le32_to_cpu(old_uclient->s); \
129 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
130 } while (0)
131
132/*
133 * General service functions
134 */
135
136static inline long bnx2x_hilo(u32 *hiref)
137{
138 u32 lo = *(hiref + 1);
139#if (BITS_PER_LONG == 64)
140 u32 hi = *hiref;
141
142 return HILO_U64(hi, lo);
143#else
144 return lo;
145#endif
146}
147
148/*
149 * Init service functions
150 */
151
152
153static void bnx2x_storm_stats_post(struct bnx2x *bp)
154{
155 if (!bp->stats_pending) {
523224a3 156 struct common_query_ramrod_data ramrod_data = {0};
6c719d00
DK		 157 int i, rc;
158
bb7e95c8
DM		 159 spin_lock_bh(&bp->stats_lock);
160
6c719d00
DK		 161 ramrod_data.drv_counter = bp->stats_counter++;
162 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
163 for_each_queue(bp, i)
164 ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
165
523224a3 166 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
6c719d00 167 ((u32 *)&ramrod_data)[1],
523224a3 168 ((u32 *)&ramrod_data)[0], 1);
6c719d00
DK		 169 if (rc == 0) {
170 /* stats ramrod has it's own slot on the spq */
171 bp->spq_left++;
172 bp->stats_pending = 1;
173 }
bb7e95c8
DM		 174
175 spin_unlock_bh(&bp->stats_lock);
6c719d00
DK		 176 }
177}
178
179static void bnx2x_hw_stats_post(struct bnx2x *bp)
180{
181 struct dmae_command *dmae = &bp->stats_dmae;
182 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
183
184 *stats_comp = DMAE_COMP_VAL;
185 if (CHIP_REV_IS_SLOW(bp))
186 return;
187
188 /* loader */
189 if (bp->executer_idx) {
190 int loader_idx = PMF_DMAE_C(bp);
191
192 memset(dmae, 0, sizeof(struct dmae_command));
193
194 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
195 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
196 DMAE_CMD_DST_RESET |
197#ifdef __BIG_ENDIAN
198 DMAE_CMD_ENDIANITY_B_DW_SWAP |
199#else
200 DMAE_CMD_ENDIANITY_DW_SWAP |
201#endif
202 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
203 DMAE_CMD_PORT_0) |
204 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
205 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
206 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
207 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
208 sizeof(struct dmae_command) *
209 (loader_idx + 1)) >> 2;
210 dmae->dst_addr_hi = 0;
211 dmae->len = sizeof(struct dmae_command) >> 2;
212 if (CHIP_IS_E1(bp))
213 dmae->len--;
214 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
215 dmae->comp_addr_hi = 0;
216 dmae->comp_val = 1;
217
218 *stats_comp = 0;
219 bnx2x_post_dmae(bp, dmae, loader_idx);
220
221 } else if (bp->func_stx) {
222 *stats_comp = 0;
223 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
224 }
225}
226
227static int bnx2x_stats_comp(struct bnx2x *bp)
228{
229 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
230 int cnt = 10;
231
232 might_sleep();
233 while (*stats_comp != DMAE_COMP_VAL) {
234 if (!cnt) {
235 BNX2X_ERR("timeout waiting for stats finished\n");
236 break;
237 }
238 cnt--;
239 msleep(1);
240 }
241 return 1;
242}
243
244/*
245 * Statistics service functions
246 */
247
248static void bnx2x_stats_pmf_update(struct bnx2x *bp)
249{
250 struct dmae_command *dmae;
251 u32 opcode;
252 int loader_idx = PMF_DMAE_C(bp);
253 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
254
255 /* sanity */
256 if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
257 BNX2X_ERR("BUG!\n");
258 return;
259 }
260
261 bp->executer_idx = 0;
262
263 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
264 DMAE_CMD_C_ENABLE |
265 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
266#ifdef __BIG_ENDIAN
267 DMAE_CMD_ENDIANITY_B_DW_SWAP |
268#else
269 DMAE_CMD_ENDIANITY_DW_SWAP |
270#endif
271 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
272 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
273
274 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
275 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
276 dmae->src_addr_lo = bp->port.port_stx >> 2;
277 dmae->src_addr_hi = 0;
278 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
279 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
280 dmae->len = DMAE_LEN32_RD_MAX;
281 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
282 dmae->comp_addr_hi = 0;
283 dmae->comp_val = 1;
284
285 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
286 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
287 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
288 dmae->src_addr_hi = 0;
289 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
290 DMAE_LEN32_RD_MAX * 4);
291 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
292 DMAE_LEN32_RD_MAX * 4);
293 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
294 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
295 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
296 dmae->comp_val = DMAE_COMP_VAL;
297
298 *stats_comp = 0;
299 bnx2x_hw_stats_post(bp);
300 bnx2x_stats_comp(bp);
301}
302
303static void bnx2x_port_stats_init(struct bnx2x *bp)
304{
305 struct dmae_command *dmae;
306 int port = BP_PORT(bp);
307 int vn = BP_E1HVN(bp);
308 u32 opcode;
309 int loader_idx = PMF_DMAE_C(bp);
310 u32 mac_addr;
311 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
312
313 /* sanity */
314 if (!bp->link_vars.link_up || !bp->port.pmf) {
315 BNX2X_ERR("BUG!\n");
316 return;
317 }
318
319 bp->executer_idx = 0;
320
321 /* MCP */
322 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
323 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
324 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
325#ifdef __BIG_ENDIAN
326 DMAE_CMD_ENDIANITY_B_DW_SWAP |
327#else
328 DMAE_CMD_ENDIANITY_DW_SWAP |
329#endif
330 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
331 (vn << DMAE_CMD_E1HVN_SHIFT));
332
333 if (bp->port.port_stx) {
334
335 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
336 dmae->opcode = opcode;
337 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
338 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
339 dmae->dst_addr_lo = bp->port.port_stx >> 2;
340 dmae->dst_addr_hi = 0;
341 dmae->len = sizeof(struct host_port_stats) >> 2;
342 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
343 dmae->comp_addr_hi = 0;
344 dmae->comp_val = 1;
345 }
346
347 if (bp->func_stx) {
348
349 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
350 dmae->opcode = opcode;
351 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
352 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
353 dmae->dst_addr_lo = bp->func_stx >> 2;
354 dmae->dst_addr_hi = 0;
355 dmae->len = sizeof(struct host_func_stats) >> 2;
356 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
357 dmae->comp_addr_hi = 0;
358 dmae->comp_val = 1;
359 }
360
361 /* MAC */
362 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
363 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
364 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
365#ifdef __BIG_ENDIAN
366 DMAE_CMD_ENDIANITY_B_DW_SWAP |
367#else
368 DMAE_CMD_ENDIANITY_DW_SWAP |
369#endif
370 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
371 (vn << DMAE_CMD_E1HVN_SHIFT));
372
373 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
374
375 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
376 NIG_REG_INGRESS_BMAC0_MEM);
377
378 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
379 BIGMAC_REGISTER_TX_STAT_GTBYT */
380 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
381 dmae->opcode = opcode;
382 dmae->src_addr_lo = (mac_addr +
383 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
384 dmae->src_addr_hi = 0;
385 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
386 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
387 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
388 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
389 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
390 dmae->comp_addr_hi = 0;
391 dmae->comp_val = 1;
392
393 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
394 BIGMAC_REGISTER_RX_STAT_GRIPJ */
395 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
396 dmae->opcode = opcode;
397 dmae->src_addr_lo = (mac_addr +
398 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
399 dmae->src_addr_hi = 0;
400 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
523224a3 401 offsetof(struct bmac1_stats, rx_stat_gr64_lo));
6c719d00 402 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
523224a3 403 offsetof(struct bmac1_stats, rx_stat_gr64_lo));
6c719d00
DK		 404 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
405 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
406 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
407 dmae->comp_addr_hi = 0;
408 dmae->comp_val = 1;
409
410 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
411
412 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
413
414 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
415 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
416 dmae->opcode = opcode;
417 dmae->src_addr_lo = (mac_addr +
418 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
419 dmae->src_addr_hi = 0;
420 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
421 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
422 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
423 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
424 dmae->comp_addr_hi = 0;
425 dmae->comp_val = 1;
426
427 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
428 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
429 dmae->opcode = opcode;
430 dmae->src_addr_lo = (mac_addr +
431 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
432 dmae->src_addr_hi = 0;
433 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
434 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
435 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
436 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
437 dmae->len = 1;
438 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
439 dmae->comp_addr_hi = 0;
440 dmae->comp_val = 1;
441
442 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
443 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
444 dmae->opcode = opcode;
445 dmae->src_addr_lo = (mac_addr +
446 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
447 dmae->src_addr_hi = 0;
448 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
449 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
450 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
451 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
452 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
453 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
454 dmae->comp_addr_hi = 0;
455 dmae->comp_val = 1;
456 }
457
458 /* NIG */
459 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
460 dmae->opcode = opcode;
461 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
462 NIG_REG_STAT0_BRB_DISCARD) >> 2;
463 dmae->src_addr_hi = 0;
464 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
465 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
466 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
467 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
468 dmae->comp_addr_hi = 0;
469 dmae->comp_val = 1;
470
471 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
472 dmae->opcode = opcode;
473 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
474 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
475 dmae->src_addr_hi = 0;
476 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
477 offsetof(struct nig_stats, egress_mac_pkt0_lo));
478 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
479 offsetof(struct nig_stats, egress_mac_pkt0_lo));
480 dmae->len = (2*sizeof(u32)) >> 2;
481 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
482 dmae->comp_addr_hi = 0;
483 dmae->comp_val = 1;
484
485 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
486 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
487 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
488 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
489#ifdef __BIG_ENDIAN
490 DMAE_CMD_ENDIANITY_B_DW_SWAP |
491#else
492 DMAE_CMD_ENDIANITY_DW_SWAP |
493#endif
494 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
495 (vn << DMAE_CMD_E1HVN_SHIFT));
496 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
497 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
498 dmae->src_addr_hi = 0;
499 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
500 offsetof(struct nig_stats, egress_mac_pkt1_lo));
501 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
502 offsetof(struct nig_stats, egress_mac_pkt1_lo));
503 dmae->len = (2*sizeof(u32)) >> 2;
504 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
505 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
506 dmae->comp_val = DMAE_COMP_VAL;
507
508 *stats_comp = 0;
509}
510
511static void bnx2x_func_stats_init(struct bnx2x *bp)
512{
513 struct dmae_command *dmae = &bp->stats_dmae;
514 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
515
516 /* sanity */
517 if (!bp->func_stx) {
518 BNX2X_ERR("BUG!\n");
519 return;
520 }
521
522 bp->executer_idx = 0;
523 memset(dmae, 0, sizeof(struct dmae_command));
524
525 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
526 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
527 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
528#ifdef __BIG_ENDIAN
529 DMAE_CMD_ENDIANITY_B_DW_SWAP |
530#else
531 DMAE_CMD_ENDIANITY_DW_SWAP |
532#endif
533 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
534 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
535 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
536 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
537 dmae->dst_addr_lo = bp->func_stx >> 2;
538 dmae->dst_addr_hi = 0;
539 dmae->len = sizeof(struct host_func_stats) >> 2;
540 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
541 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
542 dmae->comp_val = DMAE_COMP_VAL;
543
544 *stats_comp = 0;
545}
546
547static void bnx2x_stats_start(struct bnx2x *bp)
548{
549 if (bp->port.pmf)
550 bnx2x_port_stats_init(bp);
551
552 else if (bp->func_stx)
553 bnx2x_func_stats_init(bp);
554
555 bnx2x_hw_stats_post(bp);
556 bnx2x_storm_stats_post(bp);
557}
558
559static void bnx2x_stats_pmf_start(struct bnx2x *bp)
560{
561 bnx2x_stats_comp(bp);
562 bnx2x_stats_pmf_update(bp);
563 bnx2x_stats_start(bp);
564}
565
566static void bnx2x_stats_restart(struct bnx2x *bp)
567{
568 bnx2x_stats_comp(bp);
569 bnx2x_stats_start(bp);
570}
571
572static void bnx2x_bmac_stats_update(struct bnx2x *bp)
573{
523224a3 574 struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
6c719d00
DK		 575 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
576 struct bnx2x_eth_stats *estats = &bp->eth_stats;
577 struct {
578 u32 lo;
579 u32 hi;
580 } diff;
581
582 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
583 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
584 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
585 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
586 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
587 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
588 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
589 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
590 UPDATE_STAT64(rx_stat_grxpf, rx_stat_bmac_xpf);
591 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
592 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
593 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
594 UPDATE_STAT64(tx_stat_gt127,
595 tx_stat_etherstatspkts65octetsto127octets);
596 UPDATE_STAT64(tx_stat_gt255,
597 tx_stat_etherstatspkts128octetsto255octets);
598 UPDATE_STAT64(tx_stat_gt511,
599 tx_stat_etherstatspkts256octetsto511octets);
600 UPDATE_STAT64(tx_stat_gt1023,
601 tx_stat_etherstatspkts512octetsto1023octets);
602 UPDATE_STAT64(tx_stat_gt1518,
603 tx_stat_etherstatspkts1024octetsto1522octets);
604 UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
605 UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
606 UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
607 UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
608 UPDATE_STAT64(tx_stat_gterr,
609 tx_stat_dot3statsinternalmactransmiterrors);
610 UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
611
612 estats->pause_frames_received_hi =
613 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
614 estats->pause_frames_received_lo =
615 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
616
617 estats->pause_frames_sent_hi =
618 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
619 estats->pause_frames_sent_lo =
620 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
621}
622
623static void bnx2x_emac_stats_update(struct bnx2x *bp)
624{
625 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
626 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
627 struct bnx2x_eth_stats *estats = &bp->eth_stats;
628
629 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
630 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
631 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
632 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
633 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
634 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
635 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
636 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
637 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
638 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
639 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
640 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
641 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
642 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
643 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
644 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
645 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
646 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
647 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
648 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
649 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
650 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
651 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
652 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
653 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
654 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
655 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
656 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
657 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
658 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
659 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
660
661 estats->pause_frames_received_hi =
662 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
663 estats->pause_frames_received_lo =
664 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
665 ADD_64(estats->pause_frames_received_hi,
666 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
667 estats->pause_frames_received_lo,
668 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
669
670 estats->pause_frames_sent_hi =
671 pstats->mac_stx[1].tx_stat_outxonsent_hi;
672 estats->pause_frames_sent_lo =
673 pstats->mac_stx[1].tx_stat_outxonsent_lo;
674 ADD_64(estats->pause_frames_sent_hi,
675 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
676 estats->pause_frames_sent_lo,
677 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
678}
679
680static int bnx2x_hw_stats_update(struct bnx2x *bp)
681{
682 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
683 struct nig_stats *old = &(bp->port.old_nig_stats);
684 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
685 struct bnx2x_eth_stats *estats = &bp->eth_stats;
686 struct {
687 u32 lo;
688 u32 hi;
689 } diff;
690
691 if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
692 bnx2x_bmac_stats_update(bp);
693
694 else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
695 bnx2x_emac_stats_update(bp);
696
697 else { /* unreached */
698 BNX2X_ERR("stats updated by DMAE but no MAC active\n");
699 return -1;
700 }
701
702 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
703 new->brb_discard - old->brb_discard);
704 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
705 new->brb_truncate - old->brb_truncate);
706
707 UPDATE_STAT64_NIG(egress_mac_pkt0,
708 etherstatspkts1024octetsto1522octets);
709 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
710
711 memcpy(old, new, sizeof(struct nig_stats));
712
713 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
714 sizeof(struct mac_stx));
715 estats->brb_drop_hi = pstats->brb_drop_hi;
716 estats->brb_drop_lo = pstats->brb_drop_lo;
717
718 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
719
720 if (!BP_NOMCP(bp)) {
721 u32 nig_timer_max =
722 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
723 if (nig_timer_max != estats->nig_timer_max) {
724 estats->nig_timer_max = nig_timer_max;
725 BNX2X_ERR("NIG timer max (%u)\n",
726 estats->nig_timer_max);
727 }
728 }
729
730 return 0;
731}
732
733static int bnx2x_storm_stats_update(struct bnx2x *bp)
734{
735 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
736 struct tstorm_per_port_stats *tport =
737 &stats->tstorm_common.port_statistics;
738 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
739 struct bnx2x_eth_stats *estats = &bp->eth_stats;
740 int i;
bb7e95c8
DM		 741 u16 cur_stats_counter;
742
743 /* Make sure we use the value of the counter
744 * used for sending the last stats ramrod.
745 */
746 spin_lock_bh(&bp->stats_lock);
747 cur_stats_counter = bp->stats_counter - 1;
748 spin_unlock_bh(&bp->stats_lock);
6c719d00
DK		 749
750 memcpy(&(fstats->total_bytes_received_hi),
751 &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
752 sizeof(struct host_func_stats) - 2*sizeof(u32));
753 estats->error_bytes_received_hi = 0;
754 estats->error_bytes_received_lo = 0;
755 estats->etherstatsoverrsizepkts_hi = 0;
756 estats->etherstatsoverrsizepkts_lo = 0;
757 estats->no_buff_discard_hi = 0;
758 estats->no_buff_discard_lo = 0;
759
760 for_each_queue(bp, i) {
761 struct bnx2x_fastpath *fp = &bp->fp[i];
762 int cl_id = fp->cl_id;
763 struct tstorm_per_client_stats *tclient =
764 &stats->tstorm_common.client_statistics[cl_id];
765 struct tstorm_per_client_stats *old_tclient = &fp->old_tclient;
766 struct ustorm_per_client_stats *uclient =
767 &stats->ustorm_common.client_statistics[cl_id];
768 struct ustorm_per_client_stats *old_uclient = &fp->old_uclient;
769 struct xstorm_per_client_stats *xclient =
770 &stats->xstorm_common.client_statistics[cl_id];
771 struct xstorm_per_client_stats *old_xclient = &fp->old_xclient;
772 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
773 u32 diff;
774
775 /* are storm stats valid? */
bb7e95c8 776 if (le16_to_cpu(xclient->stats_counter) != cur_stats_counter) {
6c719d00
DK		 777 DP(BNX2X_MSG_STATS, "[%d] stats not updated by xstorm"
778 " xstorm counter (0x%x) != stats_counter (0x%x)\n",
bb7e95c8 779 i, xclient->stats_counter, cur_stats_counter + 1);
6c719d00
DK		 780 return -1;
781 }
bb7e95c8 782 if (le16_to_cpu(tclient->stats_counter) != cur_stats_counter) {
6c719d00
DK		 783 DP(BNX2X_MSG_STATS, "[%d] stats not updated by tstorm"
784 " tstorm counter (0x%x) != stats_counter (0x%x)\n",
bb7e95c8 785 i, tclient->stats_counter, cur_stats_counter + 1);
6c719d00
DK		 786 return -2;
787 }
bb7e95c8 788 if (le16_to_cpu(uclient->stats_counter) != cur_stats_counter) {
6c719d00
DK		 789 DP(BNX2X_MSG_STATS, "[%d] stats not updated by ustorm"
790 " ustorm counter (0x%x) != stats_counter (0x%x)\n",
bb7e95c8 791 i, uclient->stats_counter, cur_stats_counter + 1);
6c719d00
DK		 792 return -4;
793 }
794
795 qstats->total_bytes_received_hi =
796 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
797 qstats->total_bytes_received_lo =
798 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
799
800 ADD_64(qstats->total_bytes_received_hi,
801 le32_to_cpu(tclient->rcv_multicast_bytes.hi),
802 qstats->total_bytes_received_lo,
803 le32_to_cpu(tclient->rcv_multicast_bytes.lo));
804
805 ADD_64(qstats->total_bytes_received_hi,
806 le32_to_cpu(tclient->rcv_unicast_bytes.hi),
807 qstats->total_bytes_received_lo,
808 le32_to_cpu(tclient->rcv_unicast_bytes.lo));
809
810 SUB_64(qstats->total_bytes_received_hi,
811 le32_to_cpu(uclient->bcast_no_buff_bytes.hi),
812 qstats->total_bytes_received_lo,
813 le32_to_cpu(uclient->bcast_no_buff_bytes.lo));
814
815 SUB_64(qstats->total_bytes_received_hi,
816 le32_to_cpu(uclient->mcast_no_buff_bytes.hi),
817 qstats->total_bytes_received_lo,
818 le32_to_cpu(uclient->mcast_no_buff_bytes.lo));
819
820 SUB_64(qstats->total_bytes_received_hi,
821 le32_to_cpu(uclient->ucast_no_buff_bytes.hi),
822 qstats->total_bytes_received_lo,
823 le32_to_cpu(uclient->ucast_no_buff_bytes.lo));
824
825 qstats->valid_bytes_received_hi =
826 qstats->total_bytes_received_hi;
827 qstats->valid_bytes_received_lo =
828 qstats->total_bytes_received_lo;
829
830 qstats->error_bytes_received_hi =
831 le32_to_cpu(tclient->rcv_error_bytes.hi);
832 qstats->error_bytes_received_lo =
833 le32_to_cpu(tclient->rcv_error_bytes.lo);
834
835 ADD_64(qstats->total_bytes_received_hi,
836 qstats->error_bytes_received_hi,
837 qstats->total_bytes_received_lo,
838 qstats->error_bytes_received_lo);
839
840 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
841 total_unicast_packets_received);
842 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
843 total_multicast_packets_received);
844 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
845 total_broadcast_packets_received);
846 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
847 etherstatsoverrsizepkts);
848 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
849
850 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
851 total_unicast_packets_received);
852 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
853 total_multicast_packets_received);
854 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
855 total_broadcast_packets_received);
856 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
857 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
858 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
859
860 qstats->total_bytes_transmitted_hi =
861 le32_to_cpu(xclient->unicast_bytes_sent.hi);
862 qstats->total_bytes_transmitted_lo =
863 le32_to_cpu(xclient->unicast_bytes_sent.lo);
864
865 ADD_64(qstats->total_bytes_transmitted_hi,
866 le32_to_cpu(xclient->multicast_bytes_sent.hi),
867 qstats->total_bytes_transmitted_lo,
868 le32_to_cpu(xclient->multicast_bytes_sent.lo));
869
870 ADD_64(qstats->total_bytes_transmitted_hi,
871 le32_to_cpu(xclient->broadcast_bytes_sent.hi),
872 qstats->total_bytes_transmitted_lo,
873 le32_to_cpu(xclient->broadcast_bytes_sent.lo));
874
875 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
876 total_unicast_packets_transmitted);
877 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
878 total_multicast_packets_transmitted);
879 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
880 total_broadcast_packets_transmitted);
881
882 old_tclient->checksum_discard = tclient->checksum_discard;
883 old_tclient->ttl0_discard = tclient->ttl0_discard;
884
885 ADD_64(fstats->total_bytes_received_hi,
886 qstats->total_bytes_received_hi,
887 fstats->total_bytes_received_lo,
888 qstats->total_bytes_received_lo);
889 ADD_64(fstats->total_bytes_transmitted_hi,
890 qstats->total_bytes_transmitted_hi,
891 fstats->total_bytes_transmitted_lo,
892 qstats->total_bytes_transmitted_lo);
893 ADD_64(fstats->total_unicast_packets_received_hi,
894 qstats->total_unicast_packets_received_hi,
895 fstats->total_unicast_packets_received_lo,
896 qstats->total_unicast_packets_received_lo);
897 ADD_64(fstats->total_multicast_packets_received_hi,
898 qstats->total_multicast_packets_received_hi,
899 fstats->total_multicast_packets_received_lo,
900 qstats->total_multicast_packets_received_lo);
901 ADD_64(fstats->total_broadcast_packets_received_hi,
902 qstats->total_broadcast_packets_received_hi,
903 fstats->total_broadcast_packets_received_lo,
904 qstats->total_broadcast_packets_received_lo);
905 ADD_64(fstats->total_unicast_packets_transmitted_hi,
906 qstats->total_unicast_packets_transmitted_hi,
907 fstats->total_unicast_packets_transmitted_lo,
908 qstats->total_unicast_packets_transmitted_lo);
909 ADD_64(fstats->total_multicast_packets_transmitted_hi,
910 qstats->total_multicast_packets_transmitted_hi,
911 fstats->total_multicast_packets_transmitted_lo,
912 qstats->total_multicast_packets_transmitted_lo);
913 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
914 qstats->total_broadcast_packets_transmitted_hi,
915 fstats->total_broadcast_packets_transmitted_lo,
916 qstats->total_broadcast_packets_transmitted_lo);
917 ADD_64(fstats->valid_bytes_received_hi,
918 qstats->valid_bytes_received_hi,
919 fstats->valid_bytes_received_lo,
920 qstats->valid_bytes_received_lo);
921
922 ADD_64(estats->error_bytes_received_hi,
923 qstats->error_bytes_received_hi,
924 estats->error_bytes_received_lo,
925 qstats->error_bytes_received_lo);
926 ADD_64(estats->etherstatsoverrsizepkts_hi,
927 qstats->etherstatsoverrsizepkts_hi,
928 estats->etherstatsoverrsizepkts_lo,
929 qstats->etherstatsoverrsizepkts_lo);
930 ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
931 estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
932 }
933
934 ADD_64(fstats->total_bytes_received_hi,
935 estats->rx_stat_ifhcinbadoctets_hi,
936 fstats->total_bytes_received_lo,
937 estats->rx_stat_ifhcinbadoctets_lo);
938
939 memcpy(estats, &(fstats->total_bytes_received_hi),
940 sizeof(struct host_func_stats) - 2*sizeof(u32));
941
942 ADD_64(estats->etherstatsoverrsizepkts_hi,
943 estats->rx_stat_dot3statsframestoolong_hi,
944 estats->etherstatsoverrsizepkts_lo,
945 estats->rx_stat_dot3statsframestoolong_lo);
946 ADD_64(estats->error_bytes_received_hi,
947 estats->rx_stat_ifhcinbadoctets_hi,
948 estats->error_bytes_received_lo,
949 estats->rx_stat_ifhcinbadoctets_lo);
950
951 if (bp->port.pmf) {
952 estats->mac_filter_discard =
953 le32_to_cpu(tport->mac_filter_discard);
954 estats->xxoverflow_discard =
955 le32_to_cpu(tport->xxoverflow_discard);
956 estats->brb_truncate_discard =
957 le32_to_cpu(tport->brb_truncate_discard);
958 estats->mac_discard = le32_to_cpu(tport->mac_discard);
959 }
960
961 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
962
963 bp->stats_pending = 0;
964
965 return 0;
966}
967
968static void bnx2x_net_stats_update(struct bnx2x *bp)
969{
970 struct bnx2x_eth_stats *estats = &bp->eth_stats;
971 struct net_device_stats *nstats = &bp->dev->stats;
c6a056a3 972 unsigned long tmp;
6c719d00
DK		 973 int i;
974
975 nstats->rx_packets =
976 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
977 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
978 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
979
980 nstats->tx_packets =
981 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
982 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
983 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
984
985 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
986
987 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
988
c6a056a3 989 tmp = estats->mac_discard;
6c719d00 990 for_each_queue(bp, i)
c6a056a3
ED		 991 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
992 nstats->rx_dropped = tmp;
6c719d00
DK		 993
994 nstats->tx_dropped = 0;
995
996 nstats->multicast =
997 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
998
999 nstats->collisions =
1000 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
1001
1002 nstats->rx_length_errors =
1003 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
1004 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
1005 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
1006 bnx2x_hilo(&estats->brb_truncate_hi);
1007 nstats->rx_crc_errors =
1008 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
1009 nstats->rx_frame_errors =
1010 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
1011 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
1012 nstats->rx_missed_errors = estats->xxoverflow_discard;
1013
1014 nstats->rx_errors = nstats->rx_length_errors +
1015 nstats->rx_over_errors +
1016 nstats->rx_crc_errors +
1017 nstats->rx_frame_errors +
1018 nstats->rx_fifo_errors +
1019 nstats->rx_missed_errors;
1020
1021 nstats->tx_aborted_errors =
1022 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
1023 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
1024 nstats->tx_carrier_errors =
1025 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
1026 nstats->tx_fifo_errors = 0;
1027 nstats->tx_heartbeat_errors = 0;
1028 nstats->tx_window_errors = 0;
1029
1030 nstats->tx_errors = nstats->tx_aborted_errors +
1031 nstats->tx_carrier_errors +
1032 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
1033}
1034
1035static void bnx2x_drv_stats_update(struct bnx2x *bp)
1036{
1037 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1038 int i;
1039
1040 estats->driver_xoff = 0;
1041 estats->rx_err_discard_pkt = 0;
1042 estats->rx_skb_alloc_failed = 0;
1043 estats->hw_csum_err = 0;
1044 for_each_queue(bp, i) {
1045 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
1046
1047 estats->driver_xoff += qstats->driver_xoff;
1048 estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
1049 estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
1050 estats->hw_csum_err += qstats->hw_csum_err;
1051 }
1052}
1053
1054static void bnx2x_stats_update(struct bnx2x *bp)
1055{
1056 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1057
1058 if (*stats_comp != DMAE_COMP_VAL)
1059 return;
1060
1061 if (bp->port.pmf)
1062 bnx2x_hw_stats_update(bp);
1063
1064 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
1065 BNX2X_ERR("storm stats were not updated for 3 times\n");
1066 bnx2x_panic();
1067 return;
1068 }
1069
1070 bnx2x_net_stats_update(bp);
1071 bnx2x_drv_stats_update(bp);
1072
1073 if (netif_msg_timer(bp)) {
1074 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1075 int i;
1076
1077 printk(KERN_DEBUG "%s: brb drops %u brb truncate %u\n",
1078 bp->dev->name,
1079 estats->brb_drop_lo, estats->brb_truncate_lo);
1080
1081 for_each_queue(bp, i) {
1082 struct bnx2x_fastpath *fp = &bp->fp[i];
1083 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1084
1085 printk(KERN_DEBUG "%s: rx usage(%4u) *rx_cons_sb(%u)"
1086 " rx pkt(%lu) rx calls(%lu %lu)\n",
1087 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1088 fp->rx_comp_cons),
1089 le16_to_cpu(*fp->rx_cons_sb),
1090 bnx2x_hilo(&qstats->
1091 total_unicast_packets_received_hi),
1092 fp->rx_calls, fp->rx_pkt);
1093 }
1094
1095 for_each_queue(bp, i) {
1096 struct bnx2x_fastpath *fp = &bp->fp[i];
1097 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1098 struct netdev_queue *txq =
1099 netdev_get_tx_queue(bp->dev, i);
1100
1101 printk(KERN_DEBUG "%s: tx avail(%4u) *tx_cons_sb(%u)"
1102 " tx pkt(%lu) tx calls (%lu)"
1103 " %s (Xoff events %u)\n",
1104 fp->name, bnx2x_tx_avail(fp),
1105 le16_to_cpu(*fp->tx_cons_sb),
1106 bnx2x_hilo(&qstats->
1107 total_unicast_packets_transmitted_hi),
1108 fp->tx_pkt,
1109 (netif_tx_queue_stopped(txq) ? "Xoff" : "Xon"),
1110 qstats->driver_xoff);
1111 }
1112 }
1113
1114 bnx2x_hw_stats_post(bp);
1115 bnx2x_storm_stats_post(bp);
1116}
1117
1118static void bnx2x_port_stats_stop(struct bnx2x *bp)
1119{
1120 struct dmae_command *dmae;
1121 u32 opcode;
1122 int loader_idx = PMF_DMAE_C(bp);
1123 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1124
1125 bp->executer_idx = 0;
1126
1127 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
1128 DMAE_CMD_C_ENABLE |
1129 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
1130#ifdef __BIG_ENDIAN
1131 DMAE_CMD_ENDIANITY_B_DW_SWAP |
1132#else
1133 DMAE_CMD_ENDIANITY_DW_SWAP |
1134#endif
1135 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
1136 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
1137
1138 if (bp->port.port_stx) {
1139
1140 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1141 if (bp->func_stx)
1142 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
1143 else
1144 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
1145 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1146 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1147 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1148 dmae->dst_addr_hi = 0;
1149 dmae->len = sizeof(struct host_port_stats) >> 2;
1150 if (bp->func_stx) {
1151 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
1152 dmae->comp_addr_hi = 0;
1153 dmae->comp_val = 1;
1154 } else {
1155 dmae->comp_addr_lo =
1156 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1157 dmae->comp_addr_hi =
1158 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1159 dmae->comp_val = DMAE_COMP_VAL;
1160
1161 *stats_comp = 0;
1162 }
1163 }
1164
1165 if (bp->func_stx) {
1166
1167 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1168 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
1169 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1170 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1171 dmae->dst_addr_lo = bp->func_stx >> 2;
1172 dmae->dst_addr_hi = 0;
1173 dmae->len = sizeof(struct host_func_stats) >> 2;
1174 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1175 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1176 dmae->comp_val = DMAE_COMP_VAL;
1177
1178 *stats_comp = 0;
1179 }
1180}
1181
1182static void bnx2x_stats_stop(struct bnx2x *bp)
1183{
1184 int update = 0;
1185
1186 bnx2x_stats_comp(bp);
1187
1188 if (bp->port.pmf)
1189 update = (bnx2x_hw_stats_update(bp) == 0);
1190
1191 update |= (bnx2x_storm_stats_update(bp) == 0);
1192
1193 if (update) {
1194 bnx2x_net_stats_update(bp);
1195
1196 if (bp->port.pmf)
1197 bnx2x_port_stats_stop(bp);
1198
1199 bnx2x_hw_stats_post(bp);
1200 bnx2x_stats_comp(bp);
1201 }
1202}
1203
1204static void bnx2x_stats_do_nothing(struct bnx2x *bp)
1205{
1206}
1207
1208static const struct {
1209 void (*action)(struct bnx2x *bp);
1210 enum bnx2x_stats_state next_state;
1211} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1212/* state event */
1213{
1214/* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
1215/* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
1216/* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
1217/* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
1218},
1219{
1220/* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
1221/* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
1222/* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
1223/* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
1224}
1225};
1226
1227void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
1228{
bb7e95c8 1229 enum bnx2x_stats_state state;
6c719d00
DK		 1230
1231 if (unlikely(bp->panic))
1232 return;
1233
bb7e95c8
DM		 1234 /* Protect a state change flow */
1235 spin_lock_bh(&bp->stats_lock);
1236 state = bp->stats_state;
6c719d00 1237 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
bb7e95c8 1238 spin_unlock_bh(&bp->stats_lock);
6c719d00 1239
bb7e95c8 1240 bnx2x_stats_stm[state][event].action(bp);
6c719d00
DK		 1241
1242 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
1243 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
1244 state, event, bp->stats_state);
1245}
1246
1247static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1248{
1249 struct dmae_command *dmae;
1250 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1251
1252 /* sanity */
1253 if (!bp->port.pmf || !bp->port.port_stx) {
1254 BNX2X_ERR("BUG!\n");
1255 return;
1256 }
1257
1258 bp->executer_idx = 0;
1259
1260 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1261 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
1262 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
1263 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
1264#ifdef __BIG_ENDIAN
1265 DMAE_CMD_ENDIANITY_B_DW_SWAP |
1266#else
1267 DMAE_CMD_ENDIANITY_DW_SWAP |
1268#endif
1269 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
1270 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
1271 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1272 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1273 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1274 dmae->dst_addr_hi = 0;
1275 dmae->len = sizeof(struct host_port_stats) >> 2;
1276 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1277 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1278 dmae->comp_val = DMAE_COMP_VAL;
1279
1280 *stats_comp = 0;
1281 bnx2x_hw_stats_post(bp);
1282 bnx2x_stats_comp(bp);
1283}
1284
1285static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1286{
1287 int vn, vn_max = IS_E1HMF(bp) ? E1HVN_MAX : E1VN_MAX;
1288 int port = BP_PORT(bp);
1289 int func;
1290 u32 func_stx;
1291
1292 /* sanity */
1293 if (!bp->port.pmf || !bp->func_stx) {
1294 BNX2X_ERR("BUG!\n");
1295 return;
1296 }
1297
1298 /* save our func_stx */
1299 func_stx = bp->func_stx;
1300
1301 for (vn = VN_0; vn < vn_max; vn++) {
1302 func = 2*vn + port;
1303
1304 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
1305 bnx2x_func_stats_init(bp);
1306 bnx2x_hw_stats_post(bp);
1307 bnx2x_stats_comp(bp);
1308 }
1309
1310 /* restore our func_stx */
1311 bp->func_stx = func_stx;
1312}
1313
1314static void bnx2x_func_stats_base_update(struct bnx2x *bp)
1315{
1316 struct dmae_command *dmae = &bp->stats_dmae;
1317 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1318
1319 /* sanity */
1320 if (!bp->func_stx) {
1321 BNX2X_ERR("BUG!\n");
1322 return;
1323 }
1324
1325 bp->executer_idx = 0;
1326 memset(dmae, 0, sizeof(struct dmae_command));
1327
1328 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
1329 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
1330 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
1331#ifdef __BIG_ENDIAN
1332 DMAE_CMD_ENDIANITY_B_DW_SWAP |
1333#else
1334 DMAE_CMD_ENDIANITY_DW_SWAP |
1335#endif
1336 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
1337 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
1338 dmae->src_addr_lo = bp->func_stx >> 2;
1339 dmae->src_addr_hi = 0;
1340 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
1341 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
1342 dmae->len = sizeof(struct host_func_stats) >> 2;
1343 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1344 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1345 dmae->comp_val = DMAE_COMP_VAL;
1346
1347 *stats_comp = 0;
1348 bnx2x_hw_stats_post(bp);
1349 bnx2x_stats_comp(bp);
1350}
1351
1352void bnx2x_stats_init(struct bnx2x *bp)
1353{
1354 int port = BP_PORT(bp);
1355 int func = BP_FUNC(bp);
1356 int i;
1357
1358 bp->stats_pending = 0;
1359 bp->executer_idx = 0;
1360 bp->stats_counter = 0;
1361
1362 /* port and func stats for management */
1363 if (!BP_NOMCP(bp)) {
1364 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
1365 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
1366
1367 } else {
1368 bp->port.port_stx = 0;
1369 bp->func_stx = 0;
1370 }
1371 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
1372 bp->port.port_stx, bp->func_stx);
1373
1374 /* port stats */
1375 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
1376 bp->port.old_nig_stats.brb_discard =
1377 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1378 bp->port.old_nig_stats.brb_truncate =
1379 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1380 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1381 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1382 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1383 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1384
1385 /* function stats */
1386 for_each_queue(bp, i) {
1387 struct bnx2x_fastpath *fp = &bp->fp[i];
1388
1389 memset(&fp->old_tclient, 0,
1390 sizeof(struct tstorm_per_client_stats));
1391 memset(&fp->old_uclient, 0,
1392 sizeof(struct ustorm_per_client_stats));
1393 memset(&fp->old_xclient, 0,
1394 sizeof(struct xstorm_per_client_stats));
1395 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
1396 }
1397
1398 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
1399 memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
1400
1401 bp->stats_state = STATS_STATE_DISABLED;
1402
1403 if (bp->port.pmf) {
1404 if (bp->port.port_stx)
1405 bnx2x_port_stats_base_init(bp);
1406
1407 if (bp->func_stx)
1408 bnx2x_func_stats_base_init(bp);
1409
1410 } else if (bp->func_stx)
1411 bnx2x_func_stats_base_update(bp);
1412}
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