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bnx2x: move msix table initialization to probe()
[net-next-2.6.git] / drivers / net / bnx2x / bnx2x_cmn.h
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9f6c9258
DK		 1/* bnx2x_cmn.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#ifndef BNX2X_CMN_H
18#define BNX2X_CMN_H
19
20#include <linux/types.h>
21#include <linux/netdevice.h>
22
23
24#include "bnx2x.h"
25
d6214d7a 26extern int num_queues;
9f6c9258
DK		 27
28/*********************** Interfaces ****************************
29 * Functions that need to be implemented by each driver version
30 */
31
32/**
33 * Initialize link parameters structure variables.
34 *
35 * @param bp
36 * @param load_mode
37 *
38 * @return u8
39 */
40u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
41
42/**
43 * Configure hw according to link parameters structure.
44 *
45 * @param bp
46 */
47void bnx2x_link_set(struct bnx2x *bp);
48
49/**
50 * Query link status
51 *
52 * @param bp
a22f0788 53 * @param is_serdes
9f6c9258
DK		 54 *
55 * @return 0 - link is UP
56 */
a22f0788 57u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
9f6c9258
DK		 58
59/**
60 * Handles link status change
61 *
62 * @param bp
63 */
64void bnx2x__link_status_update(struct bnx2x *bp);
65
66/**
67 * MSI-X slowpath interrupt handler
68 *
69 * @param irq
70 * @param dev_instance
71 *
72 * @return irqreturn_t
73 */
74irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
75
76/**
77 * non MSI-X interrupt handler
78 *
79 * @param irq
80 * @param dev_instance
81 *
82 * @return irqreturn_t
83 */
84irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
85#ifdef BCM_CNIC
86
87/**
88 * Send command to cnic driver
89 *
90 * @param bp
91 * @param cmd
92 */
93int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
94
95/**
96 * Provides cnic information for proper interrupt handling
97 *
98 * @param bp
99 */
100void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
101#endif
102
103/**
104 * Enable HW interrupts.
105 *
106 * @param bp
107 */
108void bnx2x_int_enable(struct bnx2x *bp);
109
523224a3
DK		 110/**
111 * Disable HW interrupts.
112 *
113 * @param bp
114 */
115void bnx2x_int_disable(struct bnx2x *bp);
116
9f6c9258
DK		 117/**
118 * Disable interrupts. This function ensures that there are no
119 * ISRs or SP DPCs (sp_task) are running after it returns.
120 *
121 * @param bp
122 * @param disable_hw if true, disable HW interrupts.
123 */
124void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
125
6891dd25
DK		 126/**
127 * Loads device firmware
128 *
129 * @param bp
130 *
131 * @return int
132 */
133int bnx2x_init_firmware(struct bnx2x *bp);
134
9f6c9258
DK		 135/**
136 * Init HW blocks according to current initialization stage:
137 * COMMON, PORT or FUNCTION.
138 *
139 * @param bp
140 * @param load_code: COMMON, PORT or FUNCTION
141 *
142 * @return int
143 */
144int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
145
146/**
147 * Init driver internals:
148 * - rings
149 * - status blocks
150 * - etc.
151 *
152 * @param bp
153 * @param load_code COMMON, PORT or FUNCTION
154 */
155void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
156
157/**
158 * Allocate driver's memory.
159 *
160 * @param bp
161 *
162 * @return int
163 */
164int bnx2x_alloc_mem(struct bnx2x *bp);
165
166/**
167 * Release driver's memory.
168 *
169 * @param bp
170 */
171void bnx2x_free_mem(struct bnx2x *bp);
172
173/**
523224a3 174 * Setup eth Client.
9f6c9258
DK		 175 *
176 * @param bp
523224a3
DK		 177 * @param fp
178 * @param is_leading
9f6c9258
DK		 179 *
180 * @return int
181 */
523224a3
DK		 182int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
183 int is_leading);
9f6c9258
DK		 184
185/**
523224a3 186 * Bring down an eth client.
9f6c9258
DK		 187 *
188 * @param bp
523224a3 189 * @param p
9f6c9258
DK		 190 *
191 * @return int
192 */
523224a3
DK		 193int bnx2x_stop_fw_client(struct bnx2x *bp,
194 struct bnx2x_client_ramrod_params *p);
9f6c9258
DK		 195
196/**
d6214d7a 197 * Set number of queues according to mode
9f6c9258
DK		 198 *
199 * @param bp
200 *
201 */
d6214d7a 202void bnx2x_set_num_queues(struct bnx2x *bp);
9f6c9258
DK		 203
204/**
205 * Cleanup chip internals:
206 * - Cleanup MAC configuration.
207 * - Close clients.
208 * - etc.
209 *
210 * @param bp
211 * @param unload_mode
212 */
213void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
214
215/**
216 * Acquire HW lock.
217 *
218 * @param bp
219 * @param resource Resource bit which was locked
220 *
221 * @return int
222 */
223int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
224
225/**
226 * Release HW lock.
227 *
228 * @param bp driver handle
229 * @param resource Resource bit which was locked
230 *
231 * @return int
232 */
233int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
234
235/**
236 * Configure eth MAC address in the HW according to the value in
237 * netdev->dev_addr for 57711
238 *
239 * @param bp driver handle
240 * @param set
241 */
523224a3 242void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
9f6c9258
DK		 243
244#ifdef BCM_CNIC
245/**
246 * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
247 * MAC(s). The function will wait until the ramrod completion
248 * returns.
249 *
250 * @param bp driver handle
251 * @param set set or clear the CAM entry
252 *
253 * @return 0 if cussess, -ENODEV if ramrod doesn't return.
254 */
255int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set);
256#endif
257
258/**
259 * Initialize status block in FW and HW
260 *
261 * @param bp driver handle
9f6c9258
DK		 262 * @param dma_addr_t mapping
263 * @param int sb_id
523224a3
DK		 264 * @param int vfid
265 * @param u8 vf_valid
266 * @param int fw_sb_id
267 * @param int igu_sb_id
9f6c9258 268 */
523224a3
DK		 269void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
270 u8 vf_valid, int fw_sb_id, int igu_sb_id);
9f6c9258
DK		 271
272/**
273 * Reconfigure FW/HW according to dev->flags rx mode
274 *
275 * @param dev net_device
276 *
277 */
278void bnx2x_set_rx_mode(struct net_device *dev);
279
280/**
281 * Configure MAC filtering rules in a FW.
282 *
283 * @param bp driver handle
284 */
285void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
286
287/* Parity errors related */
288void bnx2x_inc_load_cnt(struct bnx2x *bp);
289u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
290bool bnx2x_chk_parity_attn(struct bnx2x *bp);
291bool bnx2x_reset_is_done(struct bnx2x *bp);
292void bnx2x_disable_close_the_gate(struct bnx2x *bp);
293
294/**
295 * Perform statistics handling according to event
296 *
297 * @param bp driver handle
298 * @param even tbnx2x_stats_event
299 */
300void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
301
9f6c9258
DK		 302/**
303 * Handle sp events
304 *
305 * @param fp fastpath handle for the event
306 * @param rr_cqe eth_rx_cqe
307 */
308void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
309
523224a3
DK		 310/**
311 * Init/halt function before/after sending
312 * CLIENT_SETUP/CFC_DEL for the first/last client.
313 *
314 * @param bp
315 *
316 * @return int
317 */
318int bnx2x_func_start(struct bnx2x *bp);
319int bnx2x_func_stop(struct bnx2x *bp);
320
321/**
322 * Prepare ILT configurations according to current driver
323 * parameters.
324 *
325 * @param bp
326 */
327void bnx2x_ilt_set_info(struct bnx2x *bp);
9f6c9258 328
d6214d7a
DK		 329/**
330 * Fill msix_table, request vectors, update num_queues according
331 * to number of available vectors
332 *
333 * @param bp
334 *
335 * @return int
336 */
337int bnx2x_enable_msix(struct bnx2x *bp);
338
339/**
340 * Request msi mode from OS, updated internals accordingly
341 *
342 * @param bp
343 *
344 * @return int
345 */
346int bnx2x_enable_msi(struct bnx2x *bp);
347
348/**
349 * Request IRQ vectors from OS.
350 *
351 * @param bp
352 *
353 * @return int
354 */
355int bnx2x_setup_irqs(struct bnx2x *bp);
356/**
357 * NAPI callback
358 *
359 * @param napi
360 * @param budget
361 *
362 * @return int
363 */
364int bnx2x_poll(struct napi_struct *napi, int budget);
9f6c9258
DK		 365static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
366{
9f6c9258 367 barrier(); /* status block is written to by the chip */
523224a3 368 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
9f6c9258
DK		 369}
370
371static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
372 struct bnx2x_fastpath *fp,
373 u16 bd_prod, u16 rx_comp_prod,
374 u16 rx_sge_prod)
375{
376 struct ustorm_eth_rx_producers rx_prods = {0};
377 int i;
378
379 /* Update producers */
380 rx_prods.bd_prod = bd_prod;
381 rx_prods.cqe_prod = rx_comp_prod;
382 rx_prods.sge_prod = rx_sge_prod;
383
384 /*
385 * Make sure that the BD and SGE data is updated before updating the
386 * producers since FW might read the BD/SGE right after the producer
387 * is updated.
388 * This is only applicable for weak-ordered memory model archs such
389 * as IA-64. The following barrier is also mandatory since FW will
390 * assumes BDs must have buffers.
391 */
392 wmb();
393
394 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
523224a3
DK		 395 REG_WR(bp,
396 BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
9f6c9258
DK		 397 ((u32 *)&rx_prods)[i]);
398
399 mmiowb(); /* keep prod updates ordered */
400
401 DP(NETIF_MSG_RX_STATUS,
402 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
403 fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
404}
405
f2e0899f
DK		 406static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
407 u8 segment, u16 index, u8 op,
408 u8 update, u32 igu_addr)
409{
410 struct igu_regular cmd_data = {0};
411
412 cmd_data.sb_id_and_flags =
413 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
414 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
415 (update << IGU_REGULAR_BUPDATE_SHIFT) |
416 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
417
418 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
419 cmd_data.sb_id_and_flags, igu_addr);
420 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
421
422 /* Make sure that ACK is written */
423 mmiowb();
424 barrier();
425}
426
427static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
428 u8 idu_sb_id, bool is_Pf)
429{
430 u32 data, ctl, cnt = 100;
431 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
432 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
433 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
434 u32 sb_bit = 1 << (idu_sb_id%32);
435 u32 func_encode = BP_FUNC(bp) |
436 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
437 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
438
439 /* Not supported in BC mode */
440 if (CHIP_INT_MODE_IS_BC(bp))
441 return;
442
443 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
444 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
445 IGU_REGULAR_CLEANUP_SET |
446 IGU_REGULAR_BCLEANUP;
447
448 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
449 func_encode << IGU_CTRL_REG_FID_SHIFT |
450 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
9f6c9258 451
f2e0899f
DK		 452 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
453 data, igu_addr_data);
454 REG_WR(bp, igu_addr_data, data);
455 mmiowb();
456 barrier();
457 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
458 ctl, igu_addr_ctl);
459 REG_WR(bp, igu_addr_ctl, ctl);
460 mmiowb();
461 barrier();
9f6c9258 462
f2e0899f
DK		 463 /* wait for clean up to finish */
464 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
465 msleep(20);
466
467
468 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
469 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
470 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
471 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
472 }
473}
474
475static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
476 u8 storm, u16 index, u8 op, u8 update)
9f6c9258
DK		 477{
478 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
479 COMMAND_REG_INT_ACK);
480 struct igu_ack_register igu_ack;
481
482 igu_ack.status_block_index = index;
483 igu_ack.sb_id_and_flags =
484 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
485 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
486 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
487 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
488
489 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
490 (*(u32 *)&igu_ack), hc_addr);
491 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
492
493 /* Make sure that ACK is written */
494 mmiowb();
495 barrier();
496}
f2e0899f
DK		 497
498static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
499 u16 index, u8 op, u8 update)
500{
501 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
502
503 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
504 igu_addr);
505}
506
507static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
508 u16 index, u8 op, u8 update)
509{
510 if (bp->common.int_block == INT_BLOCK_HC)
511 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
512 else {
513 u8 segment;
514
515 if (CHIP_INT_MODE_IS_BC(bp))
516 segment = storm;
517 else if (igu_sb_id != bp->igu_dsb_id)
518 segment = IGU_SEG_ACCESS_DEF;
519 else if (storm == ATTENTION_ID)
520 segment = IGU_SEG_ACCESS_ATTN;
521 else
522 segment = IGU_SEG_ACCESS_DEF;
523 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
524 }
525}
526
527static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
9f6c9258
DK		 528{
529 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
530 COMMAND_REG_SIMD_MASK);
531 u32 result = REG_RD(bp, hc_addr);
532
533 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
534 result, hc_addr);
535
f2e0899f 536 barrier();
9f6c9258
DK		 537 return result;
538}
539
f2e0899f
DK		 540static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
541{
542 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
543 u32 result = REG_RD(bp, igu_addr);
544
545 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
546 result, igu_addr);
547
548 barrier();
549 return result;
550}
551
552static inline u16 bnx2x_ack_int(struct bnx2x *bp)
553{
554 barrier();
555 if (bp->common.int_block == INT_BLOCK_HC)
556 return bnx2x_hc_ack_int(bp);
557 else
558 return bnx2x_igu_ack_int(bp);
559}
560
9f6c9258
DK		 561/*
562 * fast path service functions
563 */
9f6c9258
DK		 564static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
565{
566 /* Tell compiler that consumer and producer can change */
567 barrier();
807540ba 568 return fp->tx_pkt_prod != fp->tx_pkt_cons;
9f6c9258
DK		 569}
570
571static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
572{
573 s16 used;
574 u16 prod;
575 u16 cons;
576
577 prod = fp->tx_bd_prod;
578 cons = fp->tx_bd_cons;
579
580 /* NUM_TX_RINGS = number of "next-page" entries
581 It will be used as a threshold */
582 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
583
584#ifdef BNX2X_STOP_ON_ERROR
585 WARN_ON(used < 0);
586 WARN_ON(used > fp->bp->tx_ring_size);
587 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
588#endif
589
590 return (s16)(fp->bp->tx_ring_size) - used;
591}
592
593static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
594{
595 u16 hw_cons;
596
597 /* Tell compiler that status block fields can change */
598 barrier();
599 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
600 return hw_cons != fp->tx_pkt_cons;
601}
602
523224a3
DK		 603static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
604{
605 u16 rx_cons_sb;
606
607 /* Tell compiler that status block fields can change */
608 barrier();
609 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
610 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
611 rx_cons_sb++;
612 return (fp->rx_comp_cons != rx_cons_sb);
613}
f2e0899f
DK		 614/**
615 * disables tx from stack point of view
616 *
617 * @param bp
618 */
619static inline void bnx2x_tx_disable(struct bnx2x *bp)
620{
621 netif_tx_disable(bp->dev);
622 netif_carrier_off(bp->dev);
623}
624
9f6c9258
DK		 625static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
626 struct bnx2x_fastpath *fp, u16 index)
627{
628 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
629 struct page *page = sw_buf->page;
630 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
631
632 /* Skip "next page" elements */
633 if (!page)
634 return;
635
636 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
4bca60f4 637 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
9f6c9258
DK		 638 __free_pages(page, PAGES_PER_SGE_SHIFT);
639
640 sw_buf->page = NULL;
641 sge->addr_hi = 0;
642 sge->addr_lo = 0;
643}
644
d6214d7a
DK		 645static inline void bnx2x_add_all_napi(struct bnx2x *bp)
646{
647 int i;
523224a3 648
d6214d7a
DK		 649 /* Add NAPI objects */
650 for_each_queue(bp, i)
651 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
652 bnx2x_poll, BNX2X_NAPI_WEIGHT);
653}
523224a3 654
d6214d7a
DK		 655static inline void bnx2x_del_all_napi(struct bnx2x *bp)
656{
657 int i;
658
659 for_each_queue(bp, i)
660 netif_napi_del(&bnx2x_fp(bp, i, napi));
661}
523224a3 662
d6214d7a
DK		 663static inline void bnx2x_disable_msi(struct bnx2x *bp)
664{
665 if (bp->flags & USING_MSIX_FLAG) {
666 pci_disable_msix(bp->pdev);
667 bp->flags &= ~USING_MSIX_FLAG;
668 } else if (bp->flags & USING_MSI_FLAG) {
669 pci_disable_msi(bp->pdev);
670 bp->flags &= ~USING_MSI_FLAG;
671 }
672}
673
674static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
675{
676 return num_queues ?
677 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
678 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
679}
523224a3
DK		 680
681static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
9f6c9258 682{
523224a3 683 int i, j;
9f6c9258 684
523224a3
DK		 685 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
686 int idx = RX_SGE_CNT * i - 1;
687
688 for (j = 0; j < 2; j++) {
689 SGE_MASK_CLEAR_BIT(fp, idx);
690 idx--;
691 }
692 }
693}
694
695static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
696{
697 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
698 memset(fp->sge_mask, 0xff,
699 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
700
701 /* Clear the two last indices in the page to 1:
702 these are the indices that correspond to the "next" element,
703 hence will never be indicated and should be removed from
704 the calculations. */
705 bnx2x_clear_sge_mask_next_elems(fp);
9f6c9258
DK		 706}
707
708static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
709 struct bnx2x_fastpath *fp, u16 index)
710{
711 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
712 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
713 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
714 dma_addr_t mapping;
715
716 if (unlikely(page == NULL))
717 return -ENOMEM;
718
719 mapping = dma_map_page(&bp->pdev->dev, page, 0,
720 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
721 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
722 __free_pages(page, PAGES_PER_SGE_SHIFT);
723 return -ENOMEM;
724 }
725
726 sw_buf->page = page;
727 dma_unmap_addr_set(sw_buf, mapping, mapping);
728
729 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
730 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
731
732 return 0;
733}
734static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
735 struct bnx2x_fastpath *fp, u16 index)
736{
737 struct sk_buff *skb;
738 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
739 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
740 dma_addr_t mapping;
741
742 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
743 if (unlikely(skb == NULL))
744 return -ENOMEM;
745
746 mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
747 DMA_FROM_DEVICE);
748 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
749 dev_kfree_skb(skb);
750 return -ENOMEM;
751 }
752
753 rx_buf->skb = skb;
754 dma_unmap_addr_set(rx_buf, mapping, mapping);
755
756 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
757 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
758
759 return 0;
760}
761
762/* note that we are not allocating a new skb,
763 * we are just moving one from cons to prod
764 * we are not creating a new mapping,
765 * so there is no need to check for dma_mapping_error().
766 */
767static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
749a8503 768 u16 cons, u16 prod)
9f6c9258
DK		 769{
770 struct bnx2x *bp = fp->bp;
771 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
772 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
773 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
774 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
775
776 dma_sync_single_for_device(&bp->pdev->dev,
777 dma_unmap_addr(cons_rx_buf, mapping),
778 RX_COPY_THRESH, DMA_FROM_DEVICE);
779
780 prod_rx_buf->skb = cons_rx_buf->skb;
781 dma_unmap_addr_set(prod_rx_buf, mapping,
782 dma_unmap_addr(cons_rx_buf, mapping));
783 *prod_bd = *cons_bd;
784}
523224a3
DK		 785static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
786 struct bnx2x_fastpath *fp, int last)
9f6c9258 787{
523224a3 788 int i;
9f6c9258 789
523224a3
DK		 790 for (i = 0; i < last; i++)
791 bnx2x_free_rx_sge(bp, fp, i);
9f6c9258
DK		 792}
793
9f6c9258
DK		 794static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
795 struct bnx2x_fastpath *fp, int last)
796{
797 int i;
798
799 for (i = 0; i < last; i++) {
800 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
801 struct sk_buff *skb = rx_buf->skb;
802
803 if (skb == NULL) {
804 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
805 continue;
806 }
807
808 if (fp->tpa_state[i] == BNX2X_TPA_START)
809 dma_unmap_single(&bp->pdev->dev,
810 dma_unmap_addr(rx_buf, mapping),
811 bp->rx_buf_size, DMA_FROM_DEVICE);
812
813 dev_kfree_skb(skb);
814 rx_buf->skb = NULL;
815 }
816}
817
818
523224a3 819static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
9f6c9258
DK		 820{
821 int i, j;
822
823 for_each_queue(bp, j) {
824 struct bnx2x_fastpath *fp = &bp->fp[j];
825
826 for (i = 1; i <= NUM_TX_RINGS; i++) {
827 struct eth_tx_next_bd *tx_next_bd =
828 &fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
829
830 tx_next_bd->addr_hi =
831 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
832 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
833 tx_next_bd->addr_lo =
834 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
835 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
836 }
837
523224a3 838 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
9f6c9258
DK		 839 fp->tx_db.data.zero_fill1 = 0;
840 fp->tx_db.data.prod = 0;
841
842 fp->tx_pkt_prod = 0;
843 fp->tx_pkt_cons = 0;
844 fp->tx_bd_prod = 0;
845 fp->tx_bd_cons = 0;
9f6c9258
DK		 846 fp->tx_pkt = 0;
847 }
848}
523224a3 849static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
9f6c9258 850{
523224a3 851 int i;
9f6c9258 852
523224a3
DK		 853 for (i = 1; i <= NUM_RX_RINGS; i++) {
854 struct eth_rx_bd *rx_bd;
855
856 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
857 rx_bd->addr_hi =
858 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
859 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
860 rx_bd->addr_lo =
861 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
862 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
863 }
9f6c9258
DK		 864}
865
523224a3
DK		 866static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
867{
868 int i;
869
870 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
871 struct eth_rx_sge *sge;
872
873 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
874 sge->addr_hi =
875 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
876 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
877
878 sge->addr_lo =
879 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
880 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
881 }
882}
883
884static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
885{
886 int i;
887 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
888 struct eth_rx_cqe_next_page *nextpg;
889
890 nextpg = (struct eth_rx_cqe_next_page *)
891 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
892 nextpg->addr_hi =
893 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
894 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
895 nextpg->addr_lo =
896 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
897 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
898 }
899}
900
901
902
903static inline void __storm_memset_struct(struct bnx2x *bp,
904 u32 addr, size_t size, u32 *data)
905{
906 int i;
907 for (i = 0; i < size/4; i++)
908 REG_WR(bp, addr + (i * 4), data[i]);
909}
910
911static inline void storm_memset_mac_filters(struct bnx2x *bp,
912 struct tstorm_eth_mac_filter_config *mac_filters,
913 u16 abs_fid)
914{
915 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
916
917 u32 addr = BAR_TSTRORM_INTMEM +
918 TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
919
920 __storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
921}
922
923static inline void storm_memset_cmng(struct bnx2x *bp,
924 struct cmng_struct_per_port *cmng,
925 u8 port)
926{
927 size_t size = sizeof(struct cmng_struct_per_port);
928
929 u32 addr = BAR_XSTRORM_INTMEM +
930 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
931
932 __storm_memset_struct(bp, addr, size, (u32 *)cmng);
933}
9f6c9258
DK		 934/* HW Lock for shared dual port PHYs */
935void bnx2x_acquire_phy_lock(struct bnx2x *bp);
936void bnx2x_release_phy_lock(struct bnx2x *bp);
937
938void bnx2x_link_report(struct bnx2x *bp);
939int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
940int bnx2x_tx_int(struct bnx2x_fastpath *fp);
941void bnx2x_init_rx_rings(struct bnx2x *bp);
942netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
943
944int bnx2x_change_mac_addr(struct net_device *dev, void *p);
945void bnx2x_tx_timeout(struct net_device *dev);
946void bnx2x_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp);
947void bnx2x_netif_start(struct bnx2x *bp);
948void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
d6214d7a 949void bnx2x_free_irq(struct bnx2x *bp);
9f6c9258
DK		 950int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
951int bnx2x_resume(struct pci_dev *pdev);
952void bnx2x_free_skbs(struct bnx2x *bp);
953int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
954int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
955int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
956int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
957
523224a3
DK		 958/**
959 * Allocate/release memories outsize main driver structure
960 *
961 * @param bp
962 *
963 * @return int
964 */
965int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
966void bnx2x_free_mem_bp(struct bnx2x *bp);
967
968#define BNX2X_FW_IP_HDR_ALIGN_PAD 2 /* FW places hdr with this padding */
969
9f6c9258 970#endif /* BNX2X_CMN_H */
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