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e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
2fb9d6f5 4 * Copyright 2004-2007 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/crc32.h>
23#include <linux/device.h>
24#include <linux/spinlock.h>
e190d6b1 25#include <linux/mii.h>
4ae5a3ad 26#include <linux/phy.h>
e190d6b1
BW
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
679dce39 29#include <linux/ethtool.h>
e190d6b1 30#include <linux/skbuff.h>
e190d6b1 31#include <linux/platform_device.h>
e190d6b1
BW
32
33#include <asm/dma.h>
34#include <linux/dma-mapping.h>
35
98f672ca 36#include <asm/dpmc.h>
e190d6b1
BW
37#include <asm/blackfin.h>
38#include <asm/cacheflush.h>
39#include <asm/portmux.h>
40
41#include "bfin_mac.h"
42
43#define DRV_NAME "bfin_mac"
44#define DRV_VERSION "1.1"
45#define DRV_AUTHOR "Bryan Wu, Luke Yang"
7ef0a7ee 46#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
e190d6b1
BW
47
48MODULE_AUTHOR(DRV_AUTHOR);
49MODULE_LICENSE("GPL");
50MODULE_DESCRIPTION(DRV_DESC);
72abb461 51MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW
52
53#if defined(CONFIG_BFIN_MAC_USE_L1)
54# define bfin_mac_alloc(dma_handle, size) l1_data_sram_zalloc(size)
55# define bfin_mac_free(dma_handle, ptr) l1_data_sram_free(ptr)
56#else
57# define bfin_mac_alloc(dma_handle, size) \
58 dma_alloc_coherent(NULL, size, dma_handle, GFP_KERNEL)
59# define bfin_mac_free(dma_handle, ptr) \
60 dma_free_coherent(NULL, sizeof(*ptr), ptr, dma_handle)
61#endif
62
63#define PKT_BUF_SZ 1580
64
65#define MAX_TIMEOUT_CNT 500
66
67/* pointers to maintain transmit list */
68static struct net_dma_desc_tx *tx_list_head;
69static struct net_dma_desc_tx *tx_list_tail;
70static struct net_dma_desc_rx *rx_list_head;
71static struct net_dma_desc_rx *rx_list_tail;
72static struct net_dma_desc_rx *current_rx_ptr;
73static struct net_dma_desc_tx *current_tx_ptr;
74static struct net_dma_desc_tx *tx_desc;
75static struct net_dma_desc_rx *rx_desc;
76
7ef0a7ee
BW
77#if defined(CONFIG_BFIN_MAC_RMII)
78static u16 pin_req[] = P_RMII0;
79#else
80static u16 pin_req[] = P_MII0;
81#endif
82
83static void bfin_mac_disable(void);
84static void bfin_mac_enable(void);
4ae5a3ad 85
e190d6b1
BW
86static void desc_list_free(void)
87{
88 struct net_dma_desc_rx *r;
89 struct net_dma_desc_tx *t;
90 int i;
91#if !defined(CONFIG_BFIN_MAC_USE_L1)
92 dma_addr_t dma_handle = 0;
93#endif
94
95 if (tx_desc) {
96 t = tx_list_head;
97 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
98 if (t) {
99 if (t->skb) {
100 dev_kfree_skb(t->skb);
101 t->skb = NULL;
102 }
103 t = t->next;
104 }
105 }
106 bfin_mac_free(dma_handle, tx_desc);
107 }
108
109 if (rx_desc) {
110 r = rx_list_head;
111 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
112 if (r) {
113 if (r->skb) {
114 dev_kfree_skb(r->skb);
115 r->skb = NULL;
116 }
117 r = r->next;
118 }
119 }
120 bfin_mac_free(dma_handle, rx_desc);
121 }
122}
123
124static int desc_list_init(void)
125{
126 int i;
127 struct sk_buff *new_skb;
128#if !defined(CONFIG_BFIN_MAC_USE_L1)
129 /*
130 * This dma_handle is useless in Blackfin dma_alloc_coherent().
131 * The real dma handler is the return value of dma_alloc_coherent().
132 */
133 dma_addr_t dma_handle;
134#endif
135
136 tx_desc = bfin_mac_alloc(&dma_handle,
137 sizeof(struct net_dma_desc_tx) *
138 CONFIG_BFIN_TX_DESC_NUM);
139 if (tx_desc == NULL)
140 goto init_error;
141
142 rx_desc = bfin_mac_alloc(&dma_handle,
143 sizeof(struct net_dma_desc_rx) *
144 CONFIG_BFIN_RX_DESC_NUM);
145 if (rx_desc == NULL)
146 goto init_error;
147
148 /* init tx_list */
149 tx_list_head = tx_list_tail = tx_desc;
150
151 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
152 struct net_dma_desc_tx *t = tx_desc + i;
153 struct dma_descriptor *a = &(t->desc_a);
154 struct dma_descriptor *b = &(t->desc_b);
155
156 /*
157 * disable DMA
158 * read from memory WNR = 0
159 * wordsize is 32 bits
160 * 6 half words is desc size
161 * large desc flow
162 */
163 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
164 a->start_addr = (unsigned long)t->packet;
165 a->x_count = 0;
166 a->next_dma_desc = b;
167
168 /*
169 * enabled DMA
170 * write to memory WNR = 1
171 * wordsize is 32 bits
172 * disable interrupt
173 * 6 half words is desc size
174 * large desc flow
175 */
176 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
177 b->start_addr = (unsigned long)(&(t->status));
178 b->x_count = 0;
179
180 t->skb = NULL;
181 tx_list_tail->desc_b.next_dma_desc = a;
182 tx_list_tail->next = t;
183 tx_list_tail = t;
184 }
185 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
186 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
187 current_tx_ptr = tx_list_head;
188
189 /* init rx_list */
190 rx_list_head = rx_list_tail = rx_desc;
191
192 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
193 struct net_dma_desc_rx *r = rx_desc + i;
194 struct dma_descriptor *a = &(r->desc_a);
195 struct dma_descriptor *b = &(r->desc_b);
196
197 /* allocate a new skb for next time receive */
015dac88 198 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1
BW
199 if (!new_skb) {
200 printk(KERN_NOTICE DRV_NAME
201 ": init: low on mem - packet dropped\n");
202 goto init_error;
203 }
015dac88 204 skb_reserve(new_skb, NET_IP_ALIGN);
e190d6b1
BW
205 r->skb = new_skb;
206
207 /*
208 * enabled DMA
209 * write to memory WNR = 1
210 * wordsize is 32 bits
211 * disable interrupt
212 * 6 half words is desc size
213 * large desc flow
214 */
215 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
216 /* since RXDWA is enabled */
217 a->start_addr = (unsigned long)new_skb->data - 2;
218 a->x_count = 0;
219 a->next_dma_desc = b;
220
221 /*
222 * enabled DMA
223 * write to memory WNR = 1
224 * wordsize is 32 bits
225 * enable interrupt
226 * 6 half words is desc size
227 * large desc flow
228 */
229 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
230 NDSIZE_6 | DMAFLOW_LARGE;
231 b->start_addr = (unsigned long)(&(r->status));
232 b->x_count = 0;
233
234 rx_list_tail->desc_b.next_dma_desc = a;
235 rx_list_tail->next = r;
236 rx_list_tail = r;
237 }
238 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
239 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
240 current_rx_ptr = rx_list_head;
241
242 return 0;
243
244init_error:
245 desc_list_free();
246 printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
247 return -ENOMEM;
248}
249
250
251/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
252
4ae5a3ad
BW
253/*
254 * MII operations
255 */
e190d6b1 256/* Wait until the previous MDC/MDIO transaction has completed */
0ed0563e 257static void bfin_mdio_poll(void)
e190d6b1
BW
258{
259 int timeout_cnt = MAX_TIMEOUT_CNT;
260
261 /* poll the STABUSY bit */
262 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 263 udelay(1);
e190d6b1
BW
264 if (timeout_cnt-- < 0) {
265 printk(KERN_ERR DRV_NAME
266 ": wait MDC/MDIO transaction to complete timeout\n");
267 break;
268 }
269 }
270}
271
272/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 273static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 274{
0ed0563e 275 bfin_mdio_poll();
4ae5a3ad 276
e190d6b1 277 /* read mode */
4ae5a3ad
BW
278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
e190d6b1 280 STABUSY);
e190d6b1 281
0ed0563e 282 bfin_mdio_poll();
4ae5a3ad
BW
283
284 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW
285}
286
287/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB
288static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
289 u16 value)
e190d6b1 290{
0ed0563e 291 bfin_mdio_poll();
4ae5a3ad
BW
292
293 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW
294
295 /* write mode */
4ae5a3ad
BW
296 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
297 SET_REGAD((u16) regnum) |
e190d6b1
BW
298 STAOP |
299 STABUSY);
300
0ed0563e 301 bfin_mdio_poll();
4ae5a3ad
BW
302
303 return 0;
e190d6b1
BW
304}
305
0ed0563e 306static int bfin_mdiobus_reset(struct mii_bus *bus)
e190d6b1 307{
4ae5a3ad 308 return 0;
e190d6b1
BW
309}
310
7ef0a7ee 311static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 312{
7ef0a7ee 313 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW
314 struct phy_device *phydev = lp->phydev;
315 unsigned long flags;
316 int new_state = 0;
317
318 spin_lock_irqsave(&lp->lock, flags);
319 if (phydev->link) {
320 /* Now we make sure that we can be in full duplex mode.
321 * If not, we operate in half-duplex mode. */
322 if (phydev->duplex != lp->old_duplex) {
323 u32 opmode = bfin_read_EMAC_OPMODE();
324 new_state = 1;
325
326 if (phydev->duplex)
327 opmode |= FDMODE;
328 else
329 opmode &= ~(FDMODE);
330
331 bfin_write_EMAC_OPMODE(opmode);
332 lp->old_duplex = phydev->duplex;
333 }
e190d6b1 334
4ae5a3ad
BW
335 if (phydev->speed != lp->old_speed) {
336#if defined(CONFIG_BFIN_MAC_RMII)
337 u32 opmode = bfin_read_EMAC_OPMODE();
4ae5a3ad
BW
338 switch (phydev->speed) {
339 case 10:
340 opmode |= RMII_10;
341 break;
342 case 100:
343 opmode &= ~(RMII_10);
344 break;
345 default:
346 printk(KERN_WARNING
347 "%s: Ack! Speed (%d) is not 10/100!\n",
348 DRV_NAME, phydev->speed);
349 break;
350 }
351 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 352#endif
e190d6b1 353
4ae5a3ad
BW
354 new_state = 1;
355 lp->old_speed = phydev->speed;
356 }
e190d6b1 357
4ae5a3ad
BW
358 if (!lp->old_link) {
359 new_state = 1;
360 lp->old_link = 1;
4ae5a3ad
BW
361 }
362 } else if (lp->old_link) {
363 new_state = 1;
364 lp->old_link = 0;
365 lp->old_speed = 0;
366 lp->old_duplex = -1;
e190d6b1
BW
367 }
368
4ae5a3ad
BW
369 if (new_state) {
370 u32 opmode = bfin_read_EMAC_OPMODE();
371 phy_print_status(phydev);
372 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 373 }
4ae5a3ad
BW
374
375 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW
376}
377
7cc8f381
BW
378/* MDC = 2.5 MHz */
379#define MDC_CLK 2500000
380
4ae5a3ad 381static int mii_probe(struct net_device *dev)
e190d6b1 382{
7ef0a7ee 383 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW
384 struct phy_device *phydev = NULL;
385 unsigned short sysctl;
386 int i;
7cc8f381 387 u32 sclk, mdc_div;
e190d6b1 388
4ae5a3ad 389 /* Enable PHY output early */
98f672ca
MF
390 if (!(bfin_read_VR_CTL() & CLKBUFOE))
391 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 392
7cc8f381
BW
393 sclk = get_sclk();
394 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
395
4ae5a3ad 396 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 397 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 398 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 399
4ae5a3ad
BW
400 /* search for connect PHY device */
401 for (i = 0; i < PHY_MAX_ADDR; i++) {
298cf9be 402 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
e190d6b1 403
4ae5a3ad
BW
404 if (!tmp_phydev)
405 continue; /* no PHY here... */
e190d6b1 406
4ae5a3ad
BW
407 phydev = tmp_phydev;
408 break; /* found it */
409 }
410
411 /* now we are supposed to have a proper phydev, to attach to... */
412 if (!phydev) {
413 printk(KERN_INFO "%s: Don't found any phy device at all\n",
414 dev->name);
415 return -ENODEV;
e190d6b1
BW
416 }
417
418#if defined(CONFIG_BFIN_MAC_RMII)
c2313557
KS
419 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
420 0, PHY_INTERFACE_MODE_RMII);
4ae5a3ad 421#else
c2313557
KS
422 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
423 0, PHY_INTERFACE_MODE_MII);
e190d6b1
BW
424#endif
425
4ae5a3ad
BW
426 if (IS_ERR(phydev)) {
427 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
428 return PTR_ERR(phydev);
429 }
430
431 /* mask with MAC supported features */
432 phydev->supported &= (SUPPORTED_10baseT_Half
433 | SUPPORTED_10baseT_Full
434 | SUPPORTED_100baseT_Half
435 | SUPPORTED_100baseT_Full
436 | SUPPORTED_Autoneg
437 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
438 | SUPPORTED_MII
439 | SUPPORTED_TP);
440
441 phydev->advertising = phydev->supported;
442
443 lp->old_link = 0;
444 lp->old_speed = 0;
445 lp->old_duplex = -1;
446 lp->phydev = phydev;
447
448 printk(KERN_INFO "%s: attached PHY driver [%s] "
7cc8f381
BW
449 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
450 "@sclk=%dMHz)\n",
c2313557 451 DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
7cc8f381 452 MDC_CLK, mdc_div, sclk/1000000);
4ae5a3ad
BW
453
454 return 0;
455}
456
679dce39
BW
457/*
458 * Ethtool support
459 */
460
461static int
462bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
463{
464 struct bfin_mac_local *lp = netdev_priv(dev);
465
466 if (lp->phydev)
467 return phy_ethtool_gset(lp->phydev, cmd);
468
469 return -EINVAL;
470}
471
472static int
473bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
474{
475 struct bfin_mac_local *lp = netdev_priv(dev);
476
477 if (!capable(CAP_NET_ADMIN))
478 return -EPERM;
479
480 if (lp->phydev)
481 return phy_ethtool_sset(lp->phydev, cmd);
482
483 return -EINVAL;
484}
485
486static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
487 struct ethtool_drvinfo *info)
488{
489 strcpy(info->driver, DRV_NAME);
490 strcpy(info->version, DRV_VERSION);
491 strcpy(info->fw_version, "N/A");
c2313557 492 strcpy(info->bus_info, dev_name(&dev->dev));
679dce39
BW
493}
494
0fc0b732 495static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW
496 .get_settings = bfin_mac_ethtool_getsettings,
497 .set_settings = bfin_mac_ethtool_setsettings,
498 .get_link = ethtool_op_get_link,
499 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
500};
501
4ae5a3ad
BW
502/**************************************************************************/
503void setup_system_regs(struct net_device *dev)
504{
505 unsigned short sysctl;
506
507 /*
508 * Odd word alignment for Receive Frame DMA word
509 * Configure checksum support and rcve frame word alignment
510 */
511 sysctl = bfin_read_EMAC_SYSCTL();
512#if defined(BFIN_MAC_CSUM_OFFLOAD)
513 sysctl |= RXDWA | RXCKS;
514#else
515 sysctl |= RXDWA;
516#endif
517 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW
518
519 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
520
521 /* Initialize the TX DMA channel registers */
522 bfin_write_DMA2_X_COUNT(0);
523 bfin_write_DMA2_X_MODIFY(4);
524 bfin_write_DMA2_Y_COUNT(0);
525 bfin_write_DMA2_Y_MODIFY(0);
526
527 /* Initialize the RX DMA channel registers */
528 bfin_write_DMA1_X_COUNT(0);
529 bfin_write_DMA1_X_MODIFY(4);
530 bfin_write_DMA1_Y_COUNT(0);
531 bfin_write_DMA1_Y_MODIFY(0);
532}
533
73f83182 534static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW
535{
536 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
537 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
538
539 /* this depends on a little-endian machine */
540 bfin_write_EMAC_ADDRLO(addr_low);
541 bfin_write_EMAC_ADDRHI(addr_hi);
542}
543
7ef0a7ee 544static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL
545{
546 struct sockaddr *addr = p;
547 if (netif_running(dev))
548 return -EBUSY;
549 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
550 setup_mac_addr(dev->dev_addr);
551 return 0;
552}
553
e190d6b1
BW
554static void adjust_tx_list(void)
555{
556 int timeout_cnt = MAX_TIMEOUT_CNT;
557
8e95a202
JP
558 if (tx_list_head->status.status_word != 0 &&
559 current_tx_ptr != tx_list_head) {
e190d6b1
BW
560 goto adjust_head; /* released something, just return; */
561 }
562
563 /*
564 * if nothing released, check wait condition
565 * current's next can not be the head,
566 * otherwise the dma will not stop as we want
567 */
568 if (current_tx_ptr->next->next == tx_list_head) {
569 while (tx_list_head->status.status_word == 0) {
015dac88 570 udelay(10);
8e95a202
JP
571 if (tx_list_head->status.status_word != 0 ||
572 !(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) {
e190d6b1
BW
573 goto adjust_head;
574 }
575 if (timeout_cnt-- < 0) {
576 printk(KERN_ERR DRV_NAME
577 ": wait for adjust tx list head timeout\n");
578 break;
579 }
580 }
581 if (tx_list_head->status.status_word != 0) {
582 goto adjust_head;
583 }
584 }
585
586 return;
587
588adjust_head:
589 do {
590 tx_list_head->desc_a.config &= ~DMAEN;
591 tx_list_head->status.status_word = 0;
592 if (tx_list_head->skb) {
593 dev_kfree_skb(tx_list_head->skb);
594 tx_list_head->skb = NULL;
595 } else {
596 printk(KERN_ERR DRV_NAME
597 ": no sk_buff in a transmitted frame!\n");
598 }
599 tx_list_head = tx_list_head->next;
8e95a202
JP
600 } while (tx_list_head->status.status_word != 0 &&
601 current_tx_ptr != tx_list_head);
e190d6b1
BW
602 return;
603
604}
605
7ef0a7ee 606static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW
607 struct net_device *dev)
608{
a50c0c05 609 u16 *data;
015dac88 610 u32 data_align = (unsigned long)(skb->data) & 0x3;
e190d6b1
BW
611 current_tx_ptr->skb = skb;
612
015dac88
MH
613 if (data_align == 0x2) {
614 /* move skb->data to current_tx_ptr payload */
615 data = (u16 *)(skb->data) - 1;
616 *data = (u16)(skb->len);
617 current_tx_ptr->desc_a.start_addr = (u32)data;
618 /* this is important! */
619 blackfin_dcache_flush_range((u32)data,
620 (u32)((u8 *)data + skb->len + 4));
e190d6b1 621 } else {
015dac88
MH
622 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
623 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
624 skb->len);
625 current_tx_ptr->desc_a.start_addr =
626 (u32)current_tx_ptr->packet;
627 if (current_tx_ptr->status.status_word != 0)
628 current_tx_ptr->status.status_word = 0;
629 blackfin_dcache_flush_range(
630 (u32)current_tx_ptr->packet,
631 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW
632 }
633
805a8ab3
SZ
634 /* make sure the internal data buffers in the core are drained
635 * so that the DMA descriptors are completely written when the
636 * DMA engine goes to fetch them below
637 */
638 SSYNC();
639
e190d6b1
BW
640 /* enable this packet's dma */
641 current_tx_ptr->desc_a.config |= DMAEN;
642
643 /* tx dma is running, just return */
015dac88 644 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW
645 goto out;
646
647 /* tx dma is not running */
648 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
649 /* dma enabled, read from memory, size is 6 */
650 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
651 /* Turn on the EMAC tx */
652 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
653
654out:
655 adjust_tx_list();
656 current_tx_ptr = current_tx_ptr->next;
657 dev->trans_start = jiffies;
09f75cd7
JG
658 dev->stats.tx_packets++;
659 dev->stats.tx_bytes += (skb->len);
6ed10654 660 return NETDEV_TX_OK;
e190d6b1
BW
661}
662
7ef0a7ee 663static void bfin_mac_rx(struct net_device *dev)
e190d6b1
BW
664{
665 struct sk_buff *skb, *new_skb;
e190d6b1
BW
666 unsigned short len;
667
668 /* allocate a new skb for next time receive */
669 skb = current_rx_ptr->skb;
015dac88 670 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1
BW
671 if (!new_skb) {
672 printk(KERN_NOTICE DRV_NAME
673 ": rx: low on mem - packet dropped\n");
09f75cd7 674 dev->stats.rx_dropped++;
e190d6b1
BW
675 goto out;
676 }
677 /* reserve 2 bytes for RXDWA padding */
015dac88 678 skb_reserve(new_skb, NET_IP_ALIGN);
e190d6b1
BW
679 current_rx_ptr->skb = new_skb;
680 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
681
6e01d1a4
AD
682 /* Invidate the data cache of skb->data range when it is write back
683 * cache. It will prevent overwritting the new data from DMA
684 */
685 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
686 (unsigned long)new_skb->end);
687
e190d6b1
BW
688 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
689 skb_put(skb, len);
690 blackfin_dcache_invalidate_range((unsigned long)skb->head,
691 (unsigned long)skb->tail);
692
e190d6b1
BW
693 skb->protocol = eth_type_trans(skb, dev);
694#if defined(BFIN_MAC_CSUM_OFFLOAD)
695 skb->csum = current_rx_ptr->status.ip_payload_csum;
00ff49a9 696 skb->ip_summed = CHECKSUM_COMPLETE;
e190d6b1
BW
697#endif
698
699 netif_rx(skb);
09f75cd7
JG
700 dev->stats.rx_packets++;
701 dev->stats.rx_bytes += len;
e190d6b1
BW
702 current_rx_ptr->status.status_word = 0x00000000;
703 current_rx_ptr = current_rx_ptr->next;
704
705out:
706 return;
707}
708
709/* interrupt routine to handle rx and error signal */
7ef0a7ee 710static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1
BW
711{
712 struct net_device *dev = dev_id;
713 int number = 0;
714
715get_one_packet:
716 if (current_rx_ptr->status.status_word == 0) {
717 /* no more new packet received */
718 if (number == 0) {
719 if (current_rx_ptr->next->status.status_word != 0) {
720 current_rx_ptr = current_rx_ptr->next;
721 goto real_rx;
722 }
723 }
724 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
725 DMA_DONE | DMA_ERR);
726 return IRQ_HANDLED;
727 }
728
729real_rx:
7ef0a7ee 730 bfin_mac_rx(dev);
e190d6b1
BW
731 number++;
732 goto get_one_packet;
733}
734
735#ifdef CONFIG_NET_POLL_CONTROLLER
7ef0a7ee 736static void bfin_mac_poll(struct net_device *dev)
e190d6b1
BW
737{
738 disable_irq(IRQ_MAC_RX);
7ef0a7ee 739 bfin_mac_interrupt(IRQ_MAC_RX, dev);
e190d6b1
BW
740 enable_irq(IRQ_MAC_RX);
741}
742#endif /* CONFIG_NET_POLL_CONTROLLER */
743
7ef0a7ee 744static void bfin_mac_disable(void)
e190d6b1
BW
745{
746 unsigned int opmode;
747
748 opmode = bfin_read_EMAC_OPMODE();
749 opmode &= (~RE);
750 opmode &= (~TE);
751 /* Turn off the EMAC */
752 bfin_write_EMAC_OPMODE(opmode);
753}
754
755/*
756 * Enable Interrupts, Receive, and Transmit
757 */
7ef0a7ee 758static void bfin_mac_enable(void)
e190d6b1
BW
759{
760 u32 opmode;
761
b39d66a8 762 pr_debug("%s: %s\n", DRV_NAME, __func__);
e190d6b1
BW
763
764 /* Set RX DMA */
765 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
766 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
767
768 /* Wait MII done */
0ed0563e 769 bfin_mdio_poll();
e190d6b1
BW
770
771 /* We enable only RX here */
772 /* ASTP : Enable Automatic Pad Stripping
773 PR : Promiscuous Mode for test
774 PSF : Receive frames with total length less than 64 bytes.
775 FDMODE : Full Duplex Mode
776 LB : Internal Loopback for test
777 RE : Receiver Enable */
778 opmode = bfin_read_EMAC_OPMODE();
779 if (opmode & FDMODE)
780 opmode |= PSF;
781 else
782 opmode |= DRO | DC | PSF;
783 opmode |= RE;
784
785#if defined(CONFIG_BFIN_MAC_RMII)
786 opmode |= RMII; /* For Now only 100MBit are supported */
6893ff1c 787#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) && CONFIG_BF_REV_0_2
e190d6b1
BW
788 opmode |= TE;
789#endif
790#endif
791 /* Turn on the EMAC rx */
792 bfin_write_EMAC_OPMODE(opmode);
e190d6b1
BW
793}
794
795/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 796static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 797{
b39d66a8 798 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 799
7ef0a7ee 800 bfin_mac_disable();
e190d6b1
BW
801
802 /* reset tx queue */
803 tx_list_tail = tx_list_head->next;
804
7ef0a7ee 805 bfin_mac_enable();
e190d6b1
BW
806
807 /* We can accept TX packets again */
808 dev->trans_start = jiffies;
809 netif_wake_queue(dev);
810}
811
7ef0a7ee 812static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW
813{
814 u32 emac_hashhi, emac_hashlo;
815 struct dev_mc_list *dmi = dev->mc_list;
816 char *addrs;
817 int i;
818 u32 crc;
819
820 emac_hashhi = emac_hashlo = 0;
821
822 for (i = 0; i < dev->mc_count; i++) {
823 addrs = dmi->dmi_addr;
824 dmi = dmi->next;
825
826 /* skip non-multicast addresses */
827 if (!(*addrs & 1))
828 continue;
829
830 crc = ether_crc(ETH_ALEN, addrs);
831 crc >>= 26;
832
833 if (crc & 0x20)
834 emac_hashhi |= 1 << (crc & 0x1f);
835 else
836 emac_hashlo |= 1 << (crc & 0x1f);
837 }
838
839 bfin_write_EMAC_HASHHI(emac_hashhi);
840 bfin_write_EMAC_HASHLO(emac_hashlo);
841
842 return;
843}
844
e190d6b1
BW
845/*
846 * This routine will, depending on the values passed to it,
847 * either make it accept multicast packets, go into
848 * promiscuous mode (for TCPDUMP and cousins) or accept
849 * a select set of multicast packets
850 */
7ef0a7ee 851static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW
852{
853 u32 sysctl;
854
855 if (dev->flags & IFF_PROMISC) {
856 printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
857 sysctl = bfin_read_EMAC_OPMODE();
858 sysctl |= RAF;
859 bfin_write_EMAC_OPMODE(sysctl);
775919bc 860 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW
861 /* accept all multicast */
862 sysctl = bfin_read_EMAC_OPMODE();
863 sysctl |= PAM;
864 bfin_write_EMAC_OPMODE(sysctl);
775919bc
AW
865 } else if (dev->mc_count) {
866 /* set up multicast hash table */
867 sysctl = bfin_read_EMAC_OPMODE();
868 sysctl |= HM;
869 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 870 bfin_mac_multicast_hash(dev);
e190d6b1
BW
871 } else {
872 /* clear promisc or multicast mode */
873 sysctl = bfin_read_EMAC_OPMODE();
874 sysctl &= ~(RAF | PAM);
875 bfin_write_EMAC_OPMODE(sysctl);
876 }
877}
878
879/*
880 * this puts the device in an inactive state
881 */
7ef0a7ee 882static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW
883{
884 /* Turn off the EMAC */
885 bfin_write_EMAC_OPMODE(0x00000000);
886 /* Turn off the EMAC RX DMA */
887 bfin_write_DMA1_CONFIG(0x0000);
888 bfin_write_DMA2_CONFIG(0x0000);
889}
890
891/*
892 * Open and Initialize the interface
893 *
894 * Set up everything, reset the card, etc..
895 */
7ef0a7ee 896static int bfin_mac_open(struct net_device *dev)
e190d6b1 897{
7ef0a7ee 898 struct bfin_mac_local *lp = netdev_priv(dev);
4af4b840 899 int retval;
b39d66a8 900 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW
901
902 /*
903 * Check that the address is valid. If its not, refuse
904 * to bring the device up. The user must specify an
905 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
906 */
907 if (!is_valid_ether_addr(dev->dev_addr)) {
908 printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
909 return -EINVAL;
910 }
911
912 /* initial rx and tx list */
4af4b840
MH
913 retval = desc_list_init();
914
915 if (retval)
916 return retval;
e190d6b1 917
4ae5a3ad 918 phy_start(lp->phydev);
136492b2 919 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
e190d6b1 920 setup_system_regs(dev);
ee02fee8 921 setup_mac_addr(dev->dev_addr);
7ef0a7ee
BW
922 bfin_mac_disable();
923 bfin_mac_enable();
e190d6b1
BW
924 pr_debug("hardware init finished\n");
925 netif_start_queue(dev);
926 netif_carrier_on(dev);
927
928 return 0;
929}
930
931/*
e190d6b1
BW
932 * this makes the board clean up everything that it can
933 * and not talk to the outside world. Caused by
934 * an 'ifconfig ethX down'
935 */
7ef0a7ee 936static int bfin_mac_close(struct net_device *dev)
e190d6b1 937{
7ef0a7ee 938 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 939 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW
940
941 netif_stop_queue(dev);
942 netif_carrier_off(dev);
943
4ae5a3ad 944 phy_stop(lp->phydev);
136492b2 945 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 946
e190d6b1 947 /* clear everything */
7ef0a7ee 948 bfin_mac_shutdown(dev);
e190d6b1
BW
949
950 /* free the rx/tx buffers */
951 desc_list_free();
952
953 return 0;
954}
955
b63dc8fe
MF
956static const struct net_device_ops bfin_mac_netdev_ops = {
957 .ndo_open = bfin_mac_open,
958 .ndo_stop = bfin_mac_close,
959 .ndo_start_xmit = bfin_mac_hard_start_xmit,
960 .ndo_set_mac_address = bfin_mac_set_mac_address,
961 .ndo_tx_timeout = bfin_mac_timeout,
962 .ndo_set_multicast_list = bfin_mac_set_multicast_list,
963 .ndo_validate_addr = eth_validate_addr,
964 .ndo_change_mtu = eth_change_mtu,
965#ifdef CONFIG_NET_POLL_CONTROLLER
966 .ndo_poll_controller = bfin_mac_poll,
967#endif
968};
969
d7b843d3 970static int __devinit bfin_mac_probe(struct platform_device *pdev)
e190d6b1 971{
7ef0a7ee
BW
972 struct net_device *ndev;
973 struct bfin_mac_local *lp;
080c8255
GY
974 struct platform_device *pd;
975 int rc;
7ef0a7ee
BW
976
977 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
978 if (!ndev) {
979 dev_err(&pdev->dev, "Cannot allocate net device!\n");
980 return -ENOMEM;
981 }
982
983 SET_NETDEV_DEV(ndev, &pdev->dev);
984 platform_set_drvdata(pdev, ndev);
985 lp = netdev_priv(ndev);
e190d6b1
BW
986
987 /* Grab the MAC address in the MAC */
7ef0a7ee
BW
988 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
989 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW
990
991 /* probe mac */
992 /*todo: how to proble? which is revision_register */
993 bfin_write_EMAC_ADDRLO(0x12345678);
994 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW
995 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
996 rc = -ENODEV;
997 goto out_err_probe_mac;
e190d6b1
BW
998 }
999
e190d6b1 1000
7ef0a7ee
BW
1001 /*
1002 * Is it valid? (Did bootloader initialize it?)
1003 * Grab the MAC from the board somehow
1004 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1005 */
1006 if (!is_valid_ether_addr(ndev->dev_addr))
1007 bfin_get_ether_addr(ndev->dev_addr);
1008
e190d6b1 1009 /* If still not valid, get a random one */
7ef0a7ee
BW
1010 if (!is_valid_ether_addr(ndev->dev_addr))
1011 random_ether_addr(ndev->dev_addr);
e190d6b1 1012
7ef0a7ee 1013 setup_mac_addr(ndev->dev_addr);
e190d6b1 1014
080c8255
GY
1015 if (!pdev->dev.platform_data) {
1016 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1017 rc = -ENODEV;
1018 goto out_err_probe_mac;
7ef0a7ee 1019 }
080c8255
GY
1020 pd = pdev->dev.platform_data;
1021 lp->mii_bus = platform_get_drvdata(pd);
1022 lp->mii_bus->priv = ndev;
4ae5a3ad 1023
7ef0a7ee
BW
1024 rc = mii_probe(ndev);
1025 if (rc) {
1026 dev_err(&pdev->dev, "MII Probe failed!\n");
1027 goto out_err_mii_probe;
1028 }
4ae5a3ad 1029
e190d6b1 1030 /* Fill in the fields of the device structure with ethernet values. */
7ef0a7ee
BW
1031 ether_setup(ndev);
1032
149da651 1033 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1034 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1035
e190d6b1
BW
1036 spin_lock_init(&lp->lock);
1037
1038 /* now, enable interrupts */
1039 /* register irq handler */
7ef0a7ee 1040 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
91a455f0 1041 IRQF_DISABLED, "EMAC_RX", ndev);
7ef0a7ee
BW
1042 if (rc) {
1043 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1044 rc = -EBUSY;
1045 goto out_err_request_irq;
e190d6b1
BW
1046 }
1047
7ef0a7ee
BW
1048 rc = register_netdev(ndev);
1049 if (rc) {
1050 dev_err(&pdev->dev, "Cannot register net device!\n");
1051 goto out_err_reg_ndev;
e190d6b1
BW
1052 }
1053
7ef0a7ee
BW
1054 /* now, print out the card info, in a short format.. */
1055 dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1056
7ef0a7ee 1057 return 0;
e190d6b1 1058
7ef0a7ee
BW
1059out_err_reg_ndev:
1060 free_irq(IRQ_MAC_RX, ndev);
1061out_err_request_irq:
1062out_err_mii_probe:
298cf9be 1063 mdiobus_unregister(lp->mii_bus);
298cf9be 1064 mdiobus_free(lp->mii_bus);
7ef0a7ee 1065 peripheral_free_list(pin_req);
7ef0a7ee
BW
1066out_err_probe_mac:
1067 platform_set_drvdata(pdev, NULL);
1068 free_netdev(ndev);
e190d6b1 1069
7ef0a7ee 1070 return rc;
e190d6b1
BW
1071}
1072
d7b843d3 1073static int __devexit bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW
1074{
1075 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1076 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1
BW
1077
1078 platform_set_drvdata(pdev, NULL);
1079
080c8255 1080 lp->mii_bus->priv = NULL;
7ef0a7ee 1081
e190d6b1
BW
1082 unregister_netdev(ndev);
1083
1084 free_irq(IRQ_MAC_RX, ndev);
1085
1086 free_netdev(ndev);
1087
7ef0a7ee 1088 peripheral_free_list(pin_req);
e190d6b1
BW
1089
1090 return 0;
1091}
1092
496a34c2
BW
1093#ifdef CONFIG_PM
1094static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1095{
496a34c2
BW
1096 struct net_device *net_dev = platform_get_drvdata(pdev);
1097
1098 if (netif_running(net_dev))
7ef0a7ee 1099 bfin_mac_close(net_dev);
496a34c2 1100
e190d6b1
BW
1101 return 0;
1102}
1103
1104static int bfin_mac_resume(struct platform_device *pdev)
1105{
496a34c2
BW
1106 struct net_device *net_dev = platform_get_drvdata(pdev);
1107
1108 if (netif_running(net_dev))
7ef0a7ee 1109 bfin_mac_open(net_dev);
496a34c2 1110
e190d6b1
BW
1111 return 0;
1112}
496a34c2
BW
1113#else
1114#define bfin_mac_suspend NULL
1115#define bfin_mac_resume NULL
1116#endif /* CONFIG_PM */
e190d6b1 1117
080c8255
GY
1118static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1119{
1120 struct mii_bus *miibus;
1121 int rc, i;
1122
1123 /*
1124 * We are setting up a network card,
1125 * so set the GPIO pins to Ethernet mode
1126 */
1127 rc = peripheral_request_list(pin_req, DRV_NAME);
1128 if (rc) {
1129 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1130 return rc;
1131 }
1132
1133 rc = -ENOMEM;
1134 miibus = mdiobus_alloc();
1135 if (miibus == NULL)
1136 goto out_err_alloc;
1137 miibus->read = bfin_mdiobus_read;
1138 miibus->write = bfin_mdiobus_write;
1139 miibus->reset = bfin_mdiobus_reset;
1140
1141 miibus->parent = &pdev->dev;
1142 miibus->name = "bfin_mii_bus";
1143 snprintf(miibus->id, MII_BUS_ID_SIZE, "0");
1144 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1145 if (miibus->irq == NULL)
1146 goto out_err_alloc;
1147 for (i = 0; i < PHY_MAX_ADDR; ++i)
1148 miibus->irq[i] = PHY_POLL;
1149
1150 rc = mdiobus_register(miibus);
1151 if (rc) {
1152 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1153 goto out_err_mdiobus_register;
1154 }
1155
1156 platform_set_drvdata(pdev, miibus);
1157 return 0;
1158
1159out_err_mdiobus_register:
1160 mdiobus_free(miibus);
1161out_err_alloc:
1162 peripheral_free_list(pin_req);
1163
1164 return rc;
1165}
1166
1167static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1168{
1169 struct mii_bus *miibus = platform_get_drvdata(pdev);
1170 platform_set_drvdata(pdev, NULL);
1171 mdiobus_unregister(miibus);
1172 mdiobus_free(miibus);
1173 peripheral_free_list(pin_req);
1174 return 0;
1175}
1176
1177static struct platform_driver bfin_mii_bus_driver = {
1178 .probe = bfin_mii_bus_probe,
1179 .remove = __devexit_p(bfin_mii_bus_remove),
1180 .driver = {
1181 .name = "bfin_mii_bus",
1182 .owner = THIS_MODULE,
1183 },
1184};
1185
e190d6b1
BW
1186static struct platform_driver bfin_mac_driver = {
1187 .probe = bfin_mac_probe,
d7b843d3 1188 .remove = __devexit_p(bfin_mac_remove),
e190d6b1
BW
1189 .resume = bfin_mac_resume,
1190 .suspend = bfin_mac_suspend,
1191 .driver = {
72abb461
KS
1192 .name = DRV_NAME,
1193 .owner = THIS_MODULE,
1194 },
e190d6b1
BW
1195};
1196
1197static int __init bfin_mac_init(void)
1198{
080c8255
GY
1199 int ret;
1200 ret = platform_driver_register(&bfin_mii_bus_driver);
1201 if (!ret)
1202 return platform_driver_register(&bfin_mac_driver);
1203 return -ENODEV;
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1204}
1205
1206module_init(bfin_mac_init);
1207
1208static void __exit bfin_mac_cleanup(void)
1209{
1210 platform_driver_unregister(&bfin_mac_driver);
080c8255 1211 platform_driver_unregister(&bfin_mii_bus_driver);
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1212}
1213
1214module_exit(bfin_mac_cleanup);
72abb461 1215