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[net-next-2.6.git] / drivers / net / b44.c
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1da177e4
LT		 1/* b44.c: Broadcom 4400 device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
5 *
6 * Distribute under GPL.
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/types.h>
13#include <linux/netdevice.h>
14#include <linux/ethtool.h>
15#include <linux/mii.h>
16#include <linux/if_ether.h>
17#include <linux/etherdevice.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/init.h>
89358f90 21#include <linux/dma-mapping.h>
1da177e4
LT		 22
23#include <asm/uaccess.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include "b44.h"
28
29#define DRV_MODULE_NAME "b44"
30#define PFX DRV_MODULE_NAME ": "
981d9c17
FR		 31#define DRV_MODULE_VERSION "0.97"
32#define DRV_MODULE_RELDATE "Nov 30, 2005"
1da177e4
LT		 33
34#define B44_DEF_MSG_ENABLE \
35 (NETIF_MSG_DRV | \
36 NETIF_MSG_PROBE | \
37 NETIF_MSG_LINK | \
38 NETIF_MSG_TIMER | \
39 NETIF_MSG_IFDOWN | \
40 NETIF_MSG_IFUP | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR)
43
44/* length of time before we decide the hardware is borked,
45 * and dev->tx_timeout() should be called to fix the problem
46 */
47#define B44_TX_TIMEOUT (5 * HZ)
48
49/* hardware minimum and maximum for a single frame's data payload */
50#define B44_MIN_MTU 60
51#define B44_MAX_MTU 1500
52
53#define B44_RX_RING_SIZE 512
54#define B44_DEF_RX_RING_PENDING 200
55#define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
56 B44_RX_RING_SIZE)
57#define B44_TX_RING_SIZE 512
58#define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
59#define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
60 B44_TX_RING_SIZE)
61#define B44_DMA_MASK 0x3fffffff
62
63#define TX_RING_GAP(BP) \
64 (B44_TX_RING_SIZE - (BP)->tx_pending)
65#define TX_BUFFS_AVAIL(BP) \
66 (((BP)->tx_cons <= (BP)->tx_prod) ? \
67 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
68 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
69#define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
70
71#define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
72#define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
73
74/* minimum number of free TX descriptors required to wake up TX process */
75#define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
76
77static char version[] __devinitdata =
78 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79
80MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
81MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
82MODULE_LICENSE("GPL");
83MODULE_VERSION(DRV_MODULE_VERSION);
84
85static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
86module_param(b44_debug, int, 0);
87MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
88
89static struct pci_device_id b44_pci_tbl[] = {
90 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
91 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
92 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
93 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
94 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
95 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
96 { } /* terminate list with empty entry */
97};
98
99MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
100
101static void b44_halt(struct b44 *);
102static void b44_init_rings(struct b44 *);
103static void b44_init_hw(struct b44 *);
1da177e4 104
9f38c636
JL		 105static int dma_desc_align_mask;
106static int dma_desc_sync_size;
107
3353930d
FR		 108static const char b44_gstrings[][ETH_GSTRING_LEN] = {
109#define _B44(x...) # x,
110B44_STAT_REG_DECLARE
111#undef _B44
112};
113
9f38c636
JL		 114static inline void b44_sync_dma_desc_for_device(struct pci_dev *pdev,
115 dma_addr_t dma_base,
116 unsigned long offset,
117 enum dma_data_direction dir)
118{
119 dma_sync_single_range_for_device(&pdev->dev, dma_base,
120 offset & dma_desc_align_mask,
121 dma_desc_sync_size, dir);
122}
123
124static inline void b44_sync_dma_desc_for_cpu(struct pci_dev *pdev,
125 dma_addr_t dma_base,
126 unsigned long offset,
127 enum dma_data_direction dir)
128{
129 dma_sync_single_range_for_cpu(&pdev->dev, dma_base,
130 offset & dma_desc_align_mask,
131 dma_desc_sync_size, dir);
132}
133
1da177e4
LT		 134static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
135{
136 return readl(bp->regs + reg);
137}
138
139static inline void bw32(const struct b44 *bp,
140 unsigned long reg, unsigned long val)
141{
142 writel(val, bp->regs + reg);
143}
144
145static int b44_wait_bit(struct b44 *bp, unsigned long reg,
146 u32 bit, unsigned long timeout, const int clear)
147{
148 unsigned long i;
149
150 for (i = 0; i < timeout; i++) {
151 u32 val = br32(bp, reg);
152
153 if (clear && !(val & bit))
154 break;
155 if (!clear && (val & bit))
156 break;
157 udelay(10);
158 }
159 if (i == timeout) {
160 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
161 "%lx to %s.\n",
162 bp->dev->name,
163 bit, reg,
164 (clear ? "clear" : "set"));
165 return -ENODEV;
166 }
167 return 0;
168}
169
170/* Sonics SiliconBackplane support routines. ROFL, you should see all the
171 * buzz words used on this company's website :-)
172 *
173 * All of these routines must be invoked with bp->lock held and
174 * interrupts disabled.
175 */
176
177#define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
178#define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
179
180static u32 ssb_get_core_rev(struct b44 *bp)
181{
182 return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
183}
184
185static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
186{
187 u32 bar_orig, pci_rev, val;
188
189 pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
190 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
191 pci_rev = ssb_get_core_rev(bp);
192
193 val = br32(bp, B44_SBINTVEC);
194 val |= cores;
195 bw32(bp, B44_SBINTVEC, val);
196
197 val = br32(bp, SSB_PCI_TRANS_2);
198 val |= SSB_PCI_PREF | SSB_PCI_BURST;
199 bw32(bp, SSB_PCI_TRANS_2, val);
200
201 pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
202
203 return pci_rev;
204}
205
206static void ssb_core_disable(struct b44 *bp)
207{
208 if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
209 return;
210
211 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
212 b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
213 b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
214 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
215 SBTMSLOW_REJECT | SBTMSLOW_RESET));
216 br32(bp, B44_SBTMSLOW);
217 udelay(1);
218 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
219 br32(bp, B44_SBTMSLOW);
220 udelay(1);
221}
222
223static void ssb_core_reset(struct b44 *bp)
224{
225 u32 val;
226
227 ssb_core_disable(bp);
228 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
229 br32(bp, B44_SBTMSLOW);
230 udelay(1);
231
232 /* Clear SERR if set, this is a hw bug workaround. */
233 if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
234 bw32(bp, B44_SBTMSHIGH, 0);
235
236 val = br32(bp, B44_SBIMSTATE);
237 if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
238 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
239
240 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
241 br32(bp, B44_SBTMSLOW);
242 udelay(1);
243
244 bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
245 br32(bp, B44_SBTMSLOW);
246 udelay(1);
247}
248
249static int ssb_core_unit(struct b44 *bp)
250{
251#if 0
252 u32 val = br32(bp, B44_SBADMATCH0);
253 u32 base;
254
255 type = val & SBADMATCH0_TYPE_MASK;
256 switch (type) {
257 case 0:
258 base = val & SBADMATCH0_BS0_MASK;
259 break;
260
261 case 1:
262 base = val & SBADMATCH0_BS1_MASK;
263 break;
264
265 case 2:
266 default:
267 base = val & SBADMATCH0_BS2_MASK;
268 break;
269 };
270#endif
271 return 0;
272}
273
274static int ssb_is_core_up(struct b44 *bp)
275{
276 return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
277 == SBTMSLOW_CLOCK);
278}
279
280static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
281{
282 u32 val;
283
284 val = ((u32) data[2]) << 24;
285 val |= ((u32) data[3]) << 16;
286 val |= ((u32) data[4]) << 8;
287 val |= ((u32) data[5]) << 0;
288 bw32(bp, B44_CAM_DATA_LO, val);
289 val = (CAM_DATA_HI_VALID |
290 (((u32) data[0]) << 8) |
291 (((u32) data[1]) << 0));
292 bw32(bp, B44_CAM_DATA_HI, val);
293 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
294 (index << CAM_CTRL_INDEX_SHIFT)));
295 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
296}
297
298static inline void __b44_disable_ints(struct b44 *bp)
299{
300 bw32(bp, B44_IMASK, 0);
301}
302
303static void b44_disable_ints(struct b44 *bp)
304{
305 __b44_disable_ints(bp);
306
307 /* Flush posted writes. */
308 br32(bp, B44_IMASK);
309}
310
311static void b44_enable_ints(struct b44 *bp)
312{
313 bw32(bp, B44_IMASK, bp->imask);
314}
315
316static int b44_readphy(struct b44 *bp, int reg, u32 *val)
317{
318 int err;
319
320 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
321 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
322 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
323 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
324 (reg << MDIO_DATA_RA_SHIFT) |
325 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
326 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
327 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
328
329 return err;
330}
331
332static int b44_writephy(struct b44 *bp, int reg, u32 val)
333{
334 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
335 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
336 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
337 (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
338 (reg << MDIO_DATA_RA_SHIFT) |
339 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
340 (val & MDIO_DATA_DATA)));
341 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
342}
343
344/* miilib interface */
345/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
346 * due to code existing before miilib use was added to this driver.
347 * Someone should remove this artificial driver limitation in
348 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
349 */
350static int b44_mii_read(struct net_device *dev, int phy_id, int location)
351{
352 u32 val;
353 struct b44 *bp = netdev_priv(dev);
354 int rc = b44_readphy(bp, location, &val);
355 if (rc)
356 return 0xffffffff;
357 return val;
358}
359
360static void b44_mii_write(struct net_device *dev, int phy_id, int location,
361 int val)
362{
363 struct b44 *bp = netdev_priv(dev);
364 b44_writephy(bp, location, val);
365}
366
367static int b44_phy_reset(struct b44 *bp)
368{
369 u32 val;
370 int err;
371
372 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
373 if (err)
374 return err;
375 udelay(100);
376 err = b44_readphy(bp, MII_BMCR, &val);
377 if (!err) {
378 if (val & BMCR_RESET) {
379 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
380 bp->dev->name);
381 err = -ENODEV;
382 }
383 }
384
385 return 0;
386}
387
388static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
389{
390 u32 val;
391
392 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
393 bp->flags |= pause_flags;
394
395 val = br32(bp, B44_RXCONFIG);
396 if (pause_flags & B44_FLAG_RX_PAUSE)
397 val |= RXCONFIG_FLOW;
398 else
399 val &= ~RXCONFIG_FLOW;
400 bw32(bp, B44_RXCONFIG, val);
401
402 val = br32(bp, B44_MAC_FLOW);
403 if (pause_flags & B44_FLAG_TX_PAUSE)
404 val |= (MAC_FLOW_PAUSE_ENAB |
405 (0xc0 & MAC_FLOW_RX_HI_WATER));
406 else
407 val &= ~MAC_FLOW_PAUSE_ENAB;
408 bw32(bp, B44_MAC_FLOW, val);
409}
410
411static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
412{
413 u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
414 B44_FLAG_RX_PAUSE);
415
416 if (local & ADVERTISE_PAUSE_CAP) {
417 if (local & ADVERTISE_PAUSE_ASYM) {
418 if (remote & LPA_PAUSE_CAP)
419 pause_enab |= (B44_FLAG_TX_PAUSE |
420 B44_FLAG_RX_PAUSE);
421 else if (remote & LPA_PAUSE_ASYM)
422 pause_enab |= B44_FLAG_RX_PAUSE;
423 } else {
424 if (remote & LPA_PAUSE_CAP)
425 pause_enab |= (B44_FLAG_TX_PAUSE |
426 B44_FLAG_RX_PAUSE);
427 }
428 } else if (local & ADVERTISE_PAUSE_ASYM) {
429 if ((remote & LPA_PAUSE_CAP) &&
430 (remote & LPA_PAUSE_ASYM))
431 pause_enab |= B44_FLAG_TX_PAUSE;
432 }
433
434 __b44_set_flow_ctrl(bp, pause_enab);
435}
436
437static int b44_setup_phy(struct b44 *bp)
438{
439 u32 val;
440 int err;
441
442 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
443 goto out;
444 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
445 val & MII_ALEDCTRL_ALLMSK)) != 0)
446 goto out;
447 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
448 goto out;
449 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
450 val | MII_TLEDCTRL_ENABLE)) != 0)
451 goto out;
452
453 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
454 u32 adv = ADVERTISE_CSMA;
455
456 if (bp->flags & B44_FLAG_ADV_10HALF)
457 adv |= ADVERTISE_10HALF;
458 if (bp->flags & B44_FLAG_ADV_10FULL)
459 adv |= ADVERTISE_10FULL;
460 if (bp->flags & B44_FLAG_ADV_100HALF)
461 adv |= ADVERTISE_100HALF;
462 if (bp->flags & B44_FLAG_ADV_100FULL)
463 adv |= ADVERTISE_100FULL;
464
465 if (bp->flags & B44_FLAG_PAUSE_AUTO)
466 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
467
468 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
469 goto out;
470 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
471 BMCR_ANRESTART))) != 0)
472 goto out;
473 } else {
474 u32 bmcr;
475
476 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
477 goto out;
478 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
479 if (bp->flags & B44_FLAG_100_BASE_T)
480 bmcr |= BMCR_SPEED100;
481 if (bp->flags & B44_FLAG_FULL_DUPLEX)
482 bmcr |= BMCR_FULLDPLX;
483 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
484 goto out;
485
486 /* Since we will not be negotiating there is no safe way
487 * to determine if the link partner supports flow control
488 * or not. So just disable it completely in this case.
489 */
490 b44_set_flow_ctrl(bp, 0, 0);
491 }
492
493out:
494 return err;
495}
496
497static void b44_stats_update(struct b44 *bp)
498{
499 unsigned long reg;
500 u32 *val;
501
502 val = &bp->hw_stats.tx_good_octets;
503 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
504 *val++ += br32(bp, reg);
505 }
3353930d
FR		 506
507 /* Pad */
508 reg += 8*4UL;
509
1da177e4
LT		 510 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
511 *val++ += br32(bp, reg);
512 }
513}
514
515static void b44_link_report(struct b44 *bp)
516{
517 if (!netif_carrier_ok(bp->dev)) {
518 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
519 } else {
520 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
521 bp->dev->name,
522 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
523 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
524
525 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
526 "%s for RX.\n",
527 bp->dev->name,
528 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
529 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
530 }
531}
532
533static void b44_check_phy(struct b44 *bp)
534{
535 u32 bmsr, aux;
536
537 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
538 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
539 (bmsr != 0xffff)) {
540 if (aux & MII_AUXCTRL_SPEED)
541 bp->flags |= B44_FLAG_100_BASE_T;
542 else
543 bp->flags &= ~B44_FLAG_100_BASE_T;
544 if (aux & MII_AUXCTRL_DUPLEX)
545 bp->flags |= B44_FLAG_FULL_DUPLEX;
546 else
547 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
548
549 if (!netif_carrier_ok(bp->dev) &&
550 (bmsr & BMSR_LSTATUS)) {
551 u32 val = br32(bp, B44_TX_CTRL);
552 u32 local_adv, remote_adv;
553
554 if (bp->flags & B44_FLAG_FULL_DUPLEX)
555 val |= TX_CTRL_DUPLEX;
556 else
557 val &= ~TX_CTRL_DUPLEX;
558 bw32(bp, B44_TX_CTRL, val);
559
560 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
561 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
562 !b44_readphy(bp, MII_LPA, &remote_adv))
563 b44_set_flow_ctrl(bp, local_adv, remote_adv);
564
565 /* Link now up */
566 netif_carrier_on(bp->dev);
567 b44_link_report(bp);
568 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
569 /* Link now down */
570 netif_carrier_off(bp->dev);
571 b44_link_report(bp);
572 }
573
574 if (bmsr & BMSR_RFAULT)
575 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
576 bp->dev->name);
577 if (bmsr & BMSR_JCD)
578 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
579 bp->dev->name);
580 }
581}
582
583static void b44_timer(unsigned long __opaque)
584{
585 struct b44 *bp = (struct b44 *) __opaque;
586
587 spin_lock_irq(&bp->lock);
588
589 b44_check_phy(bp);
590
591 b44_stats_update(bp);
592
593 spin_unlock_irq(&bp->lock);
594
595 bp->timer.expires = jiffies + HZ;
596 add_timer(&bp->timer);
597}
598
599static void b44_tx(struct b44 *bp)
600{
601 u32 cur, cons;
602
603 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
604 cur /= sizeof(struct dma_desc);
605
606 /* XXX needs updating when NETIF_F_SG is supported */
607 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
608 struct ring_info *rp = &bp->tx_buffers[cons];
609 struct sk_buff *skb = rp->skb;
610
611 if (unlikely(skb == NULL))
612 BUG();
613
614 pci_unmap_single(bp->pdev,
615 pci_unmap_addr(rp, mapping),
616 skb->len,
617 PCI_DMA_TODEVICE);
618 rp->skb = NULL;
619 dev_kfree_skb_irq(skb);
620 }
621
622 bp->tx_cons = cons;
623 if (netif_queue_stopped(bp->dev) &&
624 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
625 netif_wake_queue(bp->dev);
626
627 bw32(bp, B44_GPTIMER, 0);
628}
629
630/* Works like this. This chip writes a 'struct rx_header" 30 bytes
631 * before the DMA address you give it. So we allocate 30 more bytes
632 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
633 * point the chip at 30 bytes past where the rx_header will go.
634 */
635static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
636{
637 struct dma_desc *dp;
638 struct ring_info *src_map, *map;
639 struct rx_header *rh;
640 struct sk_buff *skb;
641 dma_addr_t mapping;
642 int dest_idx;
643 u32 ctrl;
644
645 src_map = NULL;
646 if (src_idx >= 0)
647 src_map = &bp->rx_buffers[src_idx];
648 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
649 map = &bp->rx_buffers[dest_idx];
650 skb = dev_alloc_skb(RX_PKT_BUF_SZ);
651 if (skb == NULL)
652 return -ENOMEM;
653
654 mapping = pci_map_single(bp->pdev, skb->data,
655 RX_PKT_BUF_SZ,
656 PCI_DMA_FROMDEVICE);
657
658 /* Hardware bug work-around, the chip is unable to do PCI DMA
659 to/from anything above 1GB :-( */
874a6214 660 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
1da177e4
LT		 661 /* Sigh... */
662 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
663 dev_kfree_skb_any(skb);
664 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
665 if (skb == NULL)
666 return -ENOMEM;
667 mapping = pci_map_single(bp->pdev, skb->data,
668 RX_PKT_BUF_SZ,
669 PCI_DMA_FROMDEVICE);
874a6214 670 if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
1da177e4
LT		 671 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
672 dev_kfree_skb_any(skb);
673 return -ENOMEM;
674 }
675 }
676
677 skb->dev = bp->dev;
678 skb_reserve(skb, bp->rx_offset);
679
680 rh = (struct rx_header *)
681 (skb->data - bp->rx_offset);
682 rh->len = 0;
683 rh->flags = 0;
684
685 map->skb = skb;
686 pci_unmap_addr_set(map, mapping, mapping);
687
688 if (src_map != NULL)
689 src_map->skb = NULL;
690
691 ctrl = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
692 if (dest_idx == (B44_RX_RING_SIZE - 1))
693 ctrl |= DESC_CTRL_EOT;
694
695 dp = &bp->rx_ring[dest_idx];
696 dp->ctrl = cpu_to_le32(ctrl);
697 dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
698
9f38c636
JL		 699 if (bp->flags & B44_FLAG_RX_RING_HACK)
700 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
701 dest_idx * sizeof(dp),
702 DMA_BIDIRECTIONAL);
703
1da177e4
LT		 704 return RX_PKT_BUF_SZ;
705}
706
707static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
708{
709 struct dma_desc *src_desc, *dest_desc;
710 struct ring_info *src_map, *dest_map;
711 struct rx_header *rh;
712 int dest_idx;
713 u32 ctrl;
714
715 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
716 dest_desc = &bp->rx_ring[dest_idx];
717 dest_map = &bp->rx_buffers[dest_idx];
718 src_desc = &bp->rx_ring[src_idx];
719 src_map = &bp->rx_buffers[src_idx];
720
721 dest_map->skb = src_map->skb;
722 rh = (struct rx_header *) src_map->skb->data;
723 rh->len = 0;
724 rh->flags = 0;
725 pci_unmap_addr_set(dest_map, mapping,
726 pci_unmap_addr(src_map, mapping));
727
9f38c636
JL		 728 if (bp->flags & B44_FLAG_RX_RING_HACK)
729 b44_sync_dma_desc_for_cpu(bp->pdev, bp->rx_ring_dma,
730 src_idx * sizeof(src_desc),
731 DMA_BIDIRECTIONAL);
732
1da177e4
LT		 733 ctrl = src_desc->ctrl;
734 if (dest_idx == (B44_RX_RING_SIZE - 1))
735 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
736 else
737 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
738
739 dest_desc->ctrl = ctrl;
740 dest_desc->addr = src_desc->addr;
9f38c636 741
1da177e4
LT		 742 src_map->skb = NULL;
743
9f38c636
JL		 744 if (bp->flags & B44_FLAG_RX_RING_HACK)
745 b44_sync_dma_desc_for_device(bp->pdev, bp->rx_ring_dma,
746 dest_idx * sizeof(dest_desc),
747 DMA_BIDIRECTIONAL);
748
1da177e4
LT		 749 pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
750 RX_PKT_BUF_SZ,
751 PCI_DMA_FROMDEVICE);
752}
753
754static int b44_rx(struct b44 *bp, int budget)
755{
756 int received;
757 u32 cons, prod;
758
759 received = 0;
760 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
761 prod /= sizeof(struct dma_desc);
762 cons = bp->rx_cons;
763
764 while (cons != prod && budget > 0) {
765 struct ring_info *rp = &bp->rx_buffers[cons];
766 struct sk_buff *skb = rp->skb;
767 dma_addr_t map = pci_unmap_addr(rp, mapping);
768 struct rx_header *rh;
769 u16 len;
770
771 pci_dma_sync_single_for_cpu(bp->pdev, map,
772 RX_PKT_BUF_SZ,
773 PCI_DMA_FROMDEVICE);
774 rh = (struct rx_header *) skb->data;
775 len = cpu_to_le16(rh->len);
776 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
777 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
778 drop_it:
779 b44_recycle_rx(bp, cons, bp->rx_prod);
780 drop_it_no_recycle:
781 bp->stats.rx_dropped++;
782 goto next_pkt;
783 }
784
785 if (len == 0) {
786 int i = 0;
787
788 do {
789 udelay(2);
790 barrier();
791 len = cpu_to_le16(rh->len);
792 } while (len == 0 && i++ < 5);
793 if (len == 0)
794 goto drop_it;
795 }
796
797 /* Omit CRC. */
798 len -= 4;
799
800 if (len > RX_COPY_THRESHOLD) {
801 int skb_size;
802 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
803 if (skb_size < 0)
804 goto drop_it;
805 pci_unmap_single(bp->pdev, map,
806 skb_size, PCI_DMA_FROMDEVICE);
807 /* Leave out rx_header */
808 skb_put(skb, len+bp->rx_offset);
809 skb_pull(skb,bp->rx_offset);
810 } else {
811 struct sk_buff *copy_skb;
812
813 b44_recycle_rx(bp, cons, bp->rx_prod);
814 copy_skb = dev_alloc_skb(len + 2);
815 if (copy_skb == NULL)
816 goto drop_it_no_recycle;
817
818 copy_skb->dev = bp->dev;
819 skb_reserve(copy_skb, 2);
820 skb_put(copy_skb, len);
821 /* DMA sync done above, copy just the actual packet */
822 memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
823
824 skb = copy_skb;
825 }
826 skb->ip_summed = CHECKSUM_NONE;
827 skb->protocol = eth_type_trans(skb, bp->dev);
828 netif_receive_skb(skb);
829 bp->dev->last_rx = jiffies;
830 received++;
831 budget--;
832 next_pkt:
833 bp->rx_prod = (bp->rx_prod + 1) &
834 (B44_RX_RING_SIZE - 1);
835 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
836 }
837
838 bp->rx_cons = cons;
839 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
840
841 return received;
842}
843
844static int b44_poll(struct net_device *netdev, int *budget)
845{
846 struct b44 *bp = netdev_priv(netdev);
847 int done;
848
849 spin_lock_irq(&bp->lock);
850
851 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
852 /* spin_lock(&bp->tx_lock); */
853 b44_tx(bp);
854 /* spin_unlock(&bp->tx_lock); */
855 }
856 spin_unlock_irq(&bp->lock);
857
858 done = 1;
859 if (bp->istat & ISTAT_RX) {
860 int orig_budget = *budget;
861 int work_done;
862
863 if (orig_budget > netdev->quota)
864 orig_budget = netdev->quota;
865
866 work_done = b44_rx(bp, orig_budget);
867
868 *budget -= work_done;
869 netdev->quota -= work_done;
870
871 if (work_done >= orig_budget)
872 done = 0;
873 }
874
875 if (bp->istat & ISTAT_ERRORS) {
876 spin_lock_irq(&bp->lock);
877 b44_halt(bp);
878 b44_init_rings(bp);
879 b44_init_hw(bp);
880 netif_wake_queue(bp->dev);
881 spin_unlock_irq(&bp->lock);
882 done = 1;
883 }
884
885 if (done) {
886 netif_rx_complete(netdev);
887 b44_enable_ints(bp);
888 }
889
890 return (done ? 0 : 1);
891}
892
893static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
894{
895 struct net_device *dev = dev_id;
896 struct b44 *bp = netdev_priv(dev);
1da177e4
LT		 897 u32 istat, imask;
898 int handled = 0;
899
65b984f2 900 spin_lock(&bp->lock);
1da177e4
LT		 901
902 istat = br32(bp, B44_ISTAT);
903 imask = br32(bp, B44_IMASK);
904
905 /* ??? What the fuck is the purpose of the interrupt mask
906 * ??? register if we have to mask it out by hand anyways?
907 */
908 istat &= imask;
909 if (istat) {
910 handled = 1;
ba5eec9c
FR		 911
912 if (unlikely(!netif_running(dev))) {
913 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
914 goto irq_ack;
915 }
916
1da177e4
LT		 917 if (netif_rx_schedule_prep(dev)) {
918 /* NOTE: These writes are posted by the readback of
919 * the ISTAT register below.
920 */
921 bp->istat = istat;
922 __b44_disable_ints(bp);
923 __netif_rx_schedule(dev);
924 } else {
925 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
926 dev->name);
927 }
928
ba5eec9c 929irq_ack:
1da177e4
LT		 930 bw32(bp, B44_ISTAT, istat);
931 br32(bp, B44_ISTAT);
932 }
65b984f2 933 spin_unlock(&bp->lock);
1da177e4
LT		 934 return IRQ_RETVAL(handled);
935}
936
937static void b44_tx_timeout(struct net_device *dev)
938{
939 struct b44 *bp = netdev_priv(dev);
940
941 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
942 dev->name);
943
944 spin_lock_irq(&bp->lock);
945
946 b44_halt(bp);
947 b44_init_rings(bp);
948 b44_init_hw(bp);
949
950 spin_unlock_irq(&bp->lock);
951
952 b44_enable_ints(bp);
953
954 netif_wake_queue(dev);
955}
956
957static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
958{
959 struct b44 *bp = netdev_priv(dev);
960 struct sk_buff *bounce_skb;
c7193693 961 int rc = NETDEV_TX_OK;
1da177e4
LT		 962 dma_addr_t mapping;
963 u32 len, entry, ctrl;
964
965 len = skb->len;
966 spin_lock_irq(&bp->lock);
967
968 /* This is a hard error, log it. */
969 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
970 netif_stop_queue(dev);
1da177e4
LT		 971 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
972 dev->name);
c7193693 973 goto err_out;
1da177e4
LT		 974 }
975
976 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
874a6214 977 if (mapping + len > B44_DMA_MASK) {
1da177e4
LT		 978 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
979 pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
980
981 bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
982 GFP_ATOMIC|GFP_DMA);
983 if (!bounce_skb)
c7193693 984 goto err_out;
1da177e4
LT		 985
986 mapping = pci_map_single(bp->pdev, bounce_skb->data,
987 len, PCI_DMA_TODEVICE);
874a6214 988 if (mapping + len > B44_DMA_MASK) {
1da177e4
LT		 989 pci_unmap_single(bp->pdev, mapping,
990 len, PCI_DMA_TODEVICE);
991 dev_kfree_skb_any(bounce_skb);
c7193693 992 goto err_out;
1da177e4
LT		 993 }
994
995 memcpy(skb_put(bounce_skb, len), skb->data, skb->len);
996 dev_kfree_skb_any(skb);
997 skb = bounce_skb;
998 }
999
1000 entry = bp->tx_prod;
1001 bp->tx_buffers[entry].skb = skb;
1002 pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
1003
1004 ctrl = (len & DESC_CTRL_LEN);
1005 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1006 if (entry == (B44_TX_RING_SIZE - 1))
1007 ctrl |= DESC_CTRL_EOT;
1008
1009 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1010 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1011
9f38c636
JL		 1012 if (bp->flags & B44_FLAG_TX_RING_HACK)
1013 b44_sync_dma_desc_for_device(bp->pdev, bp->tx_ring_dma,
1014 entry * sizeof(bp->tx_ring[0]),
1015 DMA_TO_DEVICE);
1016
1da177e4
LT		 1017 entry = NEXT_TX(entry);
1018
1019 bp->tx_prod = entry;
1020
1021 wmb();
1022
1023 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1024 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1025 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1026 if (bp->flags & B44_FLAG_REORDER_BUG)
1027 br32(bp, B44_DMATX_PTR);
1028
1029 if (TX_BUFFS_AVAIL(bp) < 1)
1030 netif_stop_queue(dev);
1031
c7193693
FR		 1032 dev->trans_start = jiffies;
1033
1034out_unlock:
1da177e4
LT		 1035 spin_unlock_irq(&bp->lock);
1036
c7193693 1037 return rc;
1da177e4 1038
c7193693
FR		 1039err_out:
1040 rc = NETDEV_TX_BUSY;
1041 goto out_unlock;
1da177e4
LT		 1042}
1043
1044static int b44_change_mtu(struct net_device *dev, int new_mtu)
1045{
1046 struct b44 *bp = netdev_priv(dev);
1047
1048 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1049 return -EINVAL;
1050
1051 if (!netif_running(dev)) {
1052 /* We'll just catch it later when the
1053 * device is up'd.
1054 */
1055 dev->mtu = new_mtu;
1056 return 0;
1057 }
1058
1059 spin_lock_irq(&bp->lock);
1060 b44_halt(bp);
1061 dev->mtu = new_mtu;
1062 b44_init_rings(bp);
1063 b44_init_hw(bp);
1064 spin_unlock_irq(&bp->lock);
1065
1066 b44_enable_ints(bp);
1067
1068 return 0;
1069}
1070
1071/* Free up pending packets in all rx/tx rings.
1072 *
1073 * The chip has been shut down and the driver detached from
1074 * the networking, so no interrupts or new tx packets will
1075 * end up in the driver. bp->lock is not held and we are not
1076 * in an interrupt context and thus may sleep.
1077 */
1078static void b44_free_rings(struct b44 *bp)
1079{
1080 struct ring_info *rp;
1081 int i;
1082
1083 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1084 rp = &bp->rx_buffers[i];
1085
1086 if (rp->skb == NULL)
1087 continue;
1088 pci_unmap_single(bp->pdev,
1089 pci_unmap_addr(rp, mapping),
1090 RX_PKT_BUF_SZ,
1091 PCI_DMA_FROMDEVICE);
1092 dev_kfree_skb_any(rp->skb);
1093 rp->skb = NULL;
1094 }
1095
1096 /* XXX needs changes once NETIF_F_SG is set... */
1097 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1098 rp = &bp->tx_buffers[i];
1099
1100 if (rp->skb == NULL)
1101 continue;
1102 pci_unmap_single(bp->pdev,
1103 pci_unmap_addr(rp, mapping),
1104 rp->skb->len,
1105 PCI_DMA_TODEVICE);
1106 dev_kfree_skb_any(rp->skb);
1107 rp->skb = NULL;
1108 }
1109}
1110
1111/* Initialize tx/rx rings for packet processing.
1112 *
1113 * The chip has been shut down and the driver detached from
1114 * the networking, so no interrupts or new tx packets will
874a6214 1115 * end up in the driver.
1da177e4
LT		 1116 */
1117static void b44_init_rings(struct b44 *bp)
1118{
1119 int i;
1120
1121 b44_free_rings(bp);
1122
1123 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1124 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1125
9f38c636
JL		 1126 if (bp->flags & B44_FLAG_RX_RING_HACK)
1127 dma_sync_single_for_device(&bp->pdev->dev, bp->rx_ring_dma,
1128 DMA_TABLE_BYTES,
1129 PCI_DMA_BIDIRECTIONAL);
1130
1131 if (bp->flags & B44_FLAG_TX_RING_HACK)
1132 dma_sync_single_for_device(&bp->pdev->dev, bp->tx_ring_dma,
1133 DMA_TABLE_BYTES,
1134 PCI_DMA_TODEVICE);
1135
1da177e4
LT		 1136 for (i = 0; i < bp->rx_pending; i++) {
1137 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1138 break;
1139 }
1140}
1141
1142/*
1143 * Must not be invoked with interrupt sources disabled and
1144 * the hardware shutdown down.
1145 */
1146static void b44_free_consistent(struct b44 *bp)
1147{
b4558ea9
JJ		 1148 kfree(bp->rx_buffers);
1149 bp->rx_buffers = NULL;
1150 kfree(bp->tx_buffers);
1151 bp->tx_buffers = NULL;
1da177e4 1152 if (bp->rx_ring) {
9f38c636
JL		 1153 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1154 dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
1155 DMA_TABLE_BYTES,
1156 DMA_BIDIRECTIONAL);
1157 kfree(bp->rx_ring);
1158 } else
1159 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1160 bp->rx_ring, bp->rx_ring_dma);
1da177e4 1161 bp->rx_ring = NULL;
9f38c636 1162 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1da177e4
LT		 1163 }
1164 if (bp->tx_ring) {
9f38c636
JL		 1165 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1166 dma_unmap_single(&bp->pdev->dev, bp->tx_ring_dma,
1167 DMA_TABLE_BYTES,
1168 DMA_TO_DEVICE);
1169 kfree(bp->tx_ring);
1170 } else
1171 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1172 bp->tx_ring, bp->tx_ring_dma);
1da177e4 1173 bp->tx_ring = NULL;
9f38c636 1174 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1da177e4
LT		 1175 }
1176}
1177
1178/*
1179 * Must not be invoked with interrupt sources disabled and
1180 * the hardware shutdown down. Can sleep.
1181 */
1182static int b44_alloc_consistent(struct b44 *bp)
1183{
1184 int size;
1185
1186 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
874a6214 1187 bp->rx_buffers = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1188 if (!bp->rx_buffers)
1189 goto out_err;
1da177e4
LT		 1190
1191 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
874a6214 1192 bp->tx_buffers = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1193 if (!bp->tx_buffers)
1194 goto out_err;
1da177e4
LT		 1195
1196 size = DMA_TABLE_BYTES;
1197 bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
9f38c636
JL		 1198 if (!bp->rx_ring) {
1199 /* Allocation may have failed due to pci_alloc_consistent
1200 insisting on use of GFP_DMA, which is more restrictive
1201 than necessary... */
1202 struct dma_desc *rx_ring;
1203 dma_addr_t rx_ring_dma;
1204
874a6214
FR		 1205 rx_ring = kzalloc(size, GFP_KERNEL);
1206 if (!rx_ring)
9f38c636
JL		 1207 goto out_err;
1208
9f38c636
JL		 1209 rx_ring_dma = dma_map_single(&bp->pdev->dev, rx_ring,
1210 DMA_TABLE_BYTES,
1211 DMA_BIDIRECTIONAL);
1212
1213 if (rx_ring_dma + size > B44_DMA_MASK) {
1214 kfree(rx_ring);
1215 goto out_err;
1216 }
1217
1218 bp->rx_ring = rx_ring;
1219 bp->rx_ring_dma = rx_ring_dma;
1220 bp->flags |= B44_FLAG_RX_RING_HACK;
1221 }
1da177e4
LT		 1222
1223 bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
9f38c636
JL		 1224 if (!bp->tx_ring) {
1225 /* Allocation may have failed due to pci_alloc_consistent
1226 insisting on use of GFP_DMA, which is more restrictive
1227 than necessary... */
1228 struct dma_desc *tx_ring;
1229 dma_addr_t tx_ring_dma;
1230
874a6214
FR		 1231 tx_ring = kzalloc(size, GFP_KERNEL);
1232 if (!tx_ring)
9f38c636
JL		 1233 goto out_err;
1234
9f38c636
JL		 1235 tx_ring_dma = dma_map_single(&bp->pdev->dev, tx_ring,
1236 DMA_TABLE_BYTES,
1237 DMA_TO_DEVICE);
1238
1239 if (tx_ring_dma + size > B44_DMA_MASK) {
1240 kfree(tx_ring);
1241 goto out_err;
1242 }
1243
1244 bp->tx_ring = tx_ring;
1245 bp->tx_ring_dma = tx_ring_dma;
1246 bp->flags |= B44_FLAG_TX_RING_HACK;
1247 }
1da177e4
LT		 1248
1249 return 0;
1250
1251out_err:
1252 b44_free_consistent(bp);
1253 return -ENOMEM;
1254}
1255
1256/* bp->lock is held. */
1257static void b44_clear_stats(struct b44 *bp)
1258{
1259 unsigned long reg;
1260
1261 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1262 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1263 br32(bp, reg);
1264 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1265 br32(bp, reg);
1266}
1267
1268/* bp->lock is held. */
1269static void b44_chip_reset(struct b44 *bp)
1270{
1271 if (ssb_is_core_up(bp)) {
1272 bw32(bp, B44_RCV_LAZY, 0);
1273 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1274 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1275 bw32(bp, B44_DMATX_CTRL, 0);
1276 bp->tx_prod = bp->tx_cons = 0;
1277 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1278 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1279 100, 0);
1280 }
1281 bw32(bp, B44_DMARX_CTRL, 0);
1282 bp->rx_prod = bp->rx_cons = 0;
1283 } else {
1284 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1285 SBINTVEC_ENET0 :
1286 SBINTVEC_ENET1));
1287 }
1288
1289 ssb_core_reset(bp);
1290
1291 b44_clear_stats(bp);
1292
1293 /* Make PHY accessible. */
1294 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1295 (0x0d & MDIO_CTRL_MAXF_MASK)));
1296 br32(bp, B44_MDIO_CTRL);
1297
1298 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1299 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1300 br32(bp, B44_ENET_CTRL);
1301 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1302 } else {
1303 u32 val = br32(bp, B44_DEVCTRL);
1304
1305 if (val & DEVCTRL_EPR) {
1306 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1307 br32(bp, B44_DEVCTRL);
1308 udelay(100);
1309 }
1310 bp->flags |= B44_FLAG_INTERNAL_PHY;
1311 }
1312}
1313
1314/* bp->lock is held. */
1315static void b44_halt(struct b44 *bp)
1316{
1317 b44_disable_ints(bp);
1318 b44_chip_reset(bp);
1319}
1320
1321/* bp->lock is held. */
1322static void __b44_set_mac_addr(struct b44 *bp)
1323{
1324 bw32(bp, B44_CAM_CTRL, 0);
1325 if (!(bp->dev->flags & IFF_PROMISC)) {
1326 u32 val;
1327
1328 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1329 val = br32(bp, B44_CAM_CTRL);
1330 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1331 }
1332}
1333
1334static int b44_set_mac_addr(struct net_device *dev, void *p)
1335{
1336 struct b44 *bp = netdev_priv(dev);
1337 struct sockaddr *addr = p;
1338
1339 if (netif_running(dev))
1340 return -EBUSY;
1341
1342 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1343
1344 spin_lock_irq(&bp->lock);
1345 __b44_set_mac_addr(bp);
1346 spin_unlock_irq(&bp->lock);
1347
1348 return 0;
1349}
1350
1351/* Called at device open time to get the chip ready for
1352 * packet processing. Invoked with bp->lock held.
1353 */
1354static void __b44_set_rx_mode(struct net_device *);
1355static void b44_init_hw(struct b44 *bp)
1356{
1357 u32 val;
1358
1359 b44_chip_reset(bp);
1360 b44_phy_reset(bp);
1361 b44_setup_phy(bp);
1362
1363 /* Enable CRC32, set proper LED modes and power on PHY */
1364 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1365 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1366
1367 /* This sets the MAC address too. */
1368 __b44_set_rx_mode(bp->dev);
1369
1370 /* MTU + eth header + possible VLAN tag + struct rx_header */
1371 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1372 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1373
1374 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1375 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1376 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1377 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1378 (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1379 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1380
1381 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1382 bp->rx_prod = bp->rx_pending;
1383
1384 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1385
1386 val = br32(bp, B44_ENET_CTRL);
1387 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1388}
1389
1390static int b44_open(struct net_device *dev)
1391{
1392 struct b44 *bp = netdev_priv(dev);
1393 int err;
1394
1395 err = b44_alloc_consistent(bp);
1396 if (err)
6c2f4267 1397 goto out;
1da177e4
LT		 1398
1399 b44_init_rings(bp);
1400 b44_init_hw(bp);
1da177e4 1401
e254e9bf
JL		 1402 netif_carrier_off(dev);
1403 b44_check_phy(bp);
1404
6c2f4267
FR		 1405 err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1406 if (unlikely(err < 0)) {
1407 b44_chip_reset(bp);
1408 b44_free_rings(bp);
1409 b44_free_consistent(bp);
1410 goto out;
1411 }
1da177e4
LT		 1412
1413 init_timer(&bp->timer);
1414 bp->timer.expires = jiffies + HZ;
1415 bp->timer.data = (unsigned long) bp;
1416 bp->timer.function = b44_timer;
1417 add_timer(&bp->timer);
1418
1419 b44_enable_ints(bp);
d9e2d185 1420 netif_start_queue(dev);
6c2f4267 1421out:
1da177e4
LT		 1422 return err;
1423}
1424
1425#if 0
1426/*static*/ void b44_dump_state(struct b44 *bp)
1427{
1428 u32 val32, val32_2, val32_3, val32_4, val32_5;
1429 u16 val16;
1430
1431 pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1432 printk("DEBUG: PCI status [%04x] \n", val16);
1433
1434}
1435#endif
1436
1437#ifdef CONFIG_NET_POLL_CONTROLLER
1438/*
1439 * Polling receive - used by netconsole and other diagnostic tools
1440 * to allow network i/o with interrupts disabled.
1441 */
1442static void b44_poll_controller(struct net_device *dev)
1443{
1444 disable_irq(dev->irq);
1445 b44_interrupt(dev->irq, dev, NULL);
1446 enable_irq(dev->irq);
1447}
1448#endif
1449
1450static int b44_close(struct net_device *dev)
1451{
1452 struct b44 *bp = netdev_priv(dev);
1453
1454 netif_stop_queue(dev);
1455
ba5eec9c
FR		 1456 netif_poll_disable(dev);
1457
1da177e4
LT		 1458 del_timer_sync(&bp->timer);
1459
1460 spin_lock_irq(&bp->lock);
1461
1462#if 0
1463 b44_dump_state(bp);
1464#endif
1465 b44_halt(bp);
1466 b44_free_rings(bp);
1da177e4
LT		 1467 netif_carrier_off(bp->dev);
1468
1469 spin_unlock_irq(&bp->lock);
1470
1471 free_irq(dev->irq, dev);
1472
ba5eec9c
FR		 1473 netif_poll_enable(dev);
1474
1da177e4
LT		 1475 b44_free_consistent(bp);
1476
1477 return 0;
1478}
1479
1480static struct net_device_stats *b44_get_stats(struct net_device *dev)
1481{
1482 struct b44 *bp = netdev_priv(dev);
1483 struct net_device_stats *nstat = &bp->stats;
1484 struct b44_hw_stats *hwstat = &bp->hw_stats;
1485
1486 /* Convert HW stats into netdevice stats. */
1487 nstat->rx_packets = hwstat->rx_pkts;
1488 nstat->tx_packets = hwstat->tx_pkts;
1489 nstat->rx_bytes = hwstat->rx_octets;
1490 nstat->tx_bytes = hwstat->tx_octets;
1491 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1492 hwstat->tx_oversize_pkts +
1493 hwstat->tx_underruns +
1494 hwstat->tx_excessive_cols +
1495 hwstat->tx_late_cols);
1496 nstat->multicast = hwstat->tx_multicast_pkts;
1497 nstat->collisions = hwstat->tx_total_cols;
1498
1499 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1500 hwstat->rx_undersize);
1501 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1502 nstat->rx_frame_errors = hwstat->rx_align_errs;
1503 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1504 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1505 hwstat->rx_oversize_pkts +
1506 hwstat->rx_missed_pkts +
1507 hwstat->rx_crc_align_errs +
1508 hwstat->rx_undersize +
1509 hwstat->rx_crc_errs +
1510 hwstat->rx_align_errs +
1511 hwstat->rx_symbol_errs);
1512
1513 nstat->tx_aborted_errors = hwstat->tx_underruns;
1514#if 0
1515 /* Carrier lost counter seems to be broken for some devices */
1516 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1517#endif
1518
1519 return nstat;
1520}
1521
1522static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1523{
1524 struct dev_mc_list *mclist;
1525 int i, num_ents;
1526
1527 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1528 mclist = dev->mc_list;
1529 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1530 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1531 }
1532 return i+1;
1533}
1534
1535static void __b44_set_rx_mode(struct net_device *dev)
1536{
1537 struct b44 *bp = netdev_priv(dev);
1538 u32 val;
1da177e4
LT		 1539
1540 val = br32(bp, B44_RXCONFIG);
1541 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1542 if (dev->flags & IFF_PROMISC) {
1543 val |= RXCONFIG_PROMISC;
1544 bw32(bp, B44_RXCONFIG, val);
1545 } else {
874a6214
FR		 1546 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1547 int i = 0;
1548
1da177e4
LT		 1549 __b44_set_mac_addr(bp);
1550
1551 if (dev->flags & IFF_ALLMULTI)
1552 val |= RXCONFIG_ALLMULTI;
1553 else
874a6214 1554 i = __b44_load_mcast(bp, dev);
1da177e4 1555
874a6214 1556 for (; i < 64; i++) {
1da177e4
LT		 1557 __b44_cam_write(bp, zero, i);
1558 }
1559 bw32(bp, B44_RXCONFIG, val);
1560 val = br32(bp, B44_CAM_CTRL);
1561 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1562 }
1563}
1564
1565static void b44_set_rx_mode(struct net_device *dev)
1566{
1567 struct b44 *bp = netdev_priv(dev);
1568
1569 spin_lock_irq(&bp->lock);
1570 __b44_set_rx_mode(dev);
1571 spin_unlock_irq(&bp->lock);
1572}
1573
1574static u32 b44_get_msglevel(struct net_device *dev)
1575{
1576 struct b44 *bp = netdev_priv(dev);
1577 return bp->msg_enable;
1578}
1579
1580static void b44_set_msglevel(struct net_device *dev, u32 value)
1581{
1582 struct b44 *bp = netdev_priv(dev);
1583 bp->msg_enable = value;
1584}
1585
1586static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1587{
1588 struct b44 *bp = netdev_priv(dev);
1589 struct pci_dev *pci_dev = bp->pdev;
1590
1591 strcpy (info->driver, DRV_MODULE_NAME);
1592 strcpy (info->version, DRV_MODULE_VERSION);
1593 strcpy (info->bus_info, pci_name(pci_dev));
1594}
1595
1596static int b44_nway_reset(struct net_device *dev)
1597{
1598 struct b44 *bp = netdev_priv(dev);
1599 u32 bmcr;
1600 int r;
1601
1602 spin_lock_irq(&bp->lock);
1603 b44_readphy(bp, MII_BMCR, &bmcr);
1604 b44_readphy(bp, MII_BMCR, &bmcr);
1605 r = -EINVAL;
1606 if (bmcr & BMCR_ANENABLE) {
1607 b44_writephy(bp, MII_BMCR,
1608 bmcr | BMCR_ANRESTART);
1609 r = 0;
1610 }
1611 spin_unlock_irq(&bp->lock);
1612
1613 return r;
1614}
1615
1616static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1617{
1618 struct b44 *bp = netdev_priv(dev);
1619
b9dcbb40 1620 if (!netif_running(dev))
1da177e4
LT		 1621 return -EAGAIN;
1622 cmd->supported = (SUPPORTED_Autoneg);
1623 cmd->supported |= (SUPPORTED_100baseT_Half |
1624 SUPPORTED_100baseT_Full |
1625 SUPPORTED_10baseT_Half |
1626 SUPPORTED_10baseT_Full |
1627 SUPPORTED_MII);
1628
1629 cmd->advertising = 0;
1630 if (bp->flags & B44_FLAG_ADV_10HALF)
adf6e000 1631 cmd->advertising |= ADVERTISED_10baseT_Half;
1da177e4 1632 if (bp->flags & B44_FLAG_ADV_10FULL)
adf6e000 1633 cmd->advertising |= ADVERTISED_10baseT_Full;
1da177e4 1634 if (bp->flags & B44_FLAG_ADV_100HALF)
adf6e000 1635 cmd->advertising |= ADVERTISED_100baseT_Half;
1da177e4 1636 if (bp->flags & B44_FLAG_ADV_100FULL)
adf6e000
MW		 1637 cmd->advertising |= ADVERTISED_100baseT_Full;
1638 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1da177e4
LT		 1639 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1640 SPEED_100 : SPEED_10;
1641 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1642 DUPLEX_FULL : DUPLEX_HALF;
1643 cmd->port = 0;
1644 cmd->phy_address = bp->phy_addr;
1645 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1646 XCVR_INTERNAL : XCVR_EXTERNAL;
1647 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1648 AUTONEG_DISABLE : AUTONEG_ENABLE;
1649 cmd->maxtxpkt = 0;
1650 cmd->maxrxpkt = 0;
1651 return 0;
1652}
1653
1654static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1655{
1656 struct b44 *bp = netdev_priv(dev);
1657
b9dcbb40 1658 if (!netif_running(dev))
1da177e4
LT		 1659 return -EAGAIN;
1660
1661 /* We do not support gigabit. */
1662 if (cmd->autoneg == AUTONEG_ENABLE) {
1663 if (cmd->advertising &
1664 (ADVERTISED_1000baseT_Half |
1665 ADVERTISED_1000baseT_Full))
1666 return -EINVAL;
1667 } else if ((cmd->speed != SPEED_100 &&
1668 cmd->speed != SPEED_10) ||
1669 (cmd->duplex != DUPLEX_HALF &&
1670 cmd->duplex != DUPLEX_FULL)) {
1671 return -EINVAL;
1672 }
1673
1674 spin_lock_irq(&bp->lock);
1675
1676 if (cmd->autoneg == AUTONEG_ENABLE) {
1677 bp->flags &= ~B44_FLAG_FORCE_LINK;
1678 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1679 B44_FLAG_ADV_10FULL |
1680 B44_FLAG_ADV_100HALF |
1681 B44_FLAG_ADV_100FULL);
1682 if (cmd->advertising & ADVERTISE_10HALF)
1683 bp->flags |= B44_FLAG_ADV_10HALF;
1684 if (cmd->advertising & ADVERTISE_10FULL)
1685 bp->flags |= B44_FLAG_ADV_10FULL;
1686 if (cmd->advertising & ADVERTISE_100HALF)
1687 bp->flags |= B44_FLAG_ADV_100HALF;
1688 if (cmd->advertising & ADVERTISE_100FULL)
1689 bp->flags |= B44_FLAG_ADV_100FULL;
1690 } else {
1691 bp->flags |= B44_FLAG_FORCE_LINK;
1692 if (cmd->speed == SPEED_100)
1693 bp->flags |= B44_FLAG_100_BASE_T;
1694 if (cmd->duplex == DUPLEX_FULL)
1695 bp->flags |= B44_FLAG_FULL_DUPLEX;
1696 }
1697
1698 b44_setup_phy(bp);
1699
1700 spin_unlock_irq(&bp->lock);
1701
1702 return 0;
1703}
1704
1705static void b44_get_ringparam(struct net_device *dev,
1706 struct ethtool_ringparam *ering)
1707{
1708 struct b44 *bp = netdev_priv(dev);
1709
1710 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1711 ering->rx_pending = bp->rx_pending;
1712
1713 /* XXX ethtool lacks a tx_max_pending, oops... */
1714}
1715
1716static int b44_set_ringparam(struct net_device *dev,
1717 struct ethtool_ringparam *ering)
1718{
1719 struct b44 *bp = netdev_priv(dev);
1720
1721 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1722 (ering->rx_mini_pending != 0) ||
1723 (ering->rx_jumbo_pending != 0) ||
1724 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1725 return -EINVAL;
1726
1727 spin_lock_irq(&bp->lock);
1728
1729 bp->rx_pending = ering->rx_pending;
1730 bp->tx_pending = ering->tx_pending;
1731
1732 b44_halt(bp);
1733 b44_init_rings(bp);
1734 b44_init_hw(bp);
1735 netif_wake_queue(bp->dev);
1736 spin_unlock_irq(&bp->lock);
1737
1738 b44_enable_ints(bp);
1739
1740 return 0;
1741}
1742
1743static void b44_get_pauseparam(struct net_device *dev,
1744 struct ethtool_pauseparam *epause)
1745{
1746 struct b44 *bp = netdev_priv(dev);
1747
1748 epause->autoneg =
1749 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1750 epause->rx_pause =
1751 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1752 epause->tx_pause =
1753 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1754}
1755
1756static int b44_set_pauseparam(struct net_device *dev,
1757 struct ethtool_pauseparam *epause)
1758{
1759 struct b44 *bp = netdev_priv(dev);
1760
1761 spin_lock_irq(&bp->lock);
1762 if (epause->autoneg)
1763 bp->flags |= B44_FLAG_PAUSE_AUTO;
1764 else
1765 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1766 if (epause->rx_pause)
1767 bp->flags |= B44_FLAG_RX_PAUSE;
1768 else
1769 bp->flags &= ~B44_FLAG_RX_PAUSE;
1770 if (epause->tx_pause)
1771 bp->flags |= B44_FLAG_TX_PAUSE;
1772 else
1773 bp->flags &= ~B44_FLAG_TX_PAUSE;
1774 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1775 b44_halt(bp);
1776 b44_init_rings(bp);
1777 b44_init_hw(bp);
1778 } else {
1779 __b44_set_flow_ctrl(bp, bp->flags);
1780 }
1781 spin_unlock_irq(&bp->lock);
1782
1783 b44_enable_ints(bp);
1784
1785 return 0;
1786}
1787
3353930d
FR		 1788static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1789{
1790 switch(stringset) {
1791 case ETH_SS_STATS:
1792 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1793 break;
1794 }
1795}
1796
1797static int b44_get_stats_count(struct net_device *dev)
1798{
1799 return ARRAY_SIZE(b44_gstrings);
1800}
1801
1802static void b44_get_ethtool_stats(struct net_device *dev,
1803 struct ethtool_stats *stats, u64 *data)
1804{
1805 struct b44 *bp = netdev_priv(dev);
1806 u32 *val = &bp->hw_stats.tx_good_octets;
1807 u32 i;
1808
1809 spin_lock_irq(&bp->lock);
1810
1811 b44_stats_update(bp);
1812
1813 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
1814 *data++ = *val++;
1815
1816 spin_unlock_irq(&bp->lock);
1817}
1818
1da177e4
LT		 1819static struct ethtool_ops b44_ethtool_ops = {
1820 .get_drvinfo = b44_get_drvinfo,
1821 .get_settings = b44_get_settings,
1822 .set_settings = b44_set_settings,
1823 .nway_reset = b44_nway_reset,
1824 .get_link = ethtool_op_get_link,
1825 .get_ringparam = b44_get_ringparam,
1826 .set_ringparam = b44_set_ringparam,
1827 .get_pauseparam = b44_get_pauseparam,
1828 .set_pauseparam = b44_set_pauseparam,
1829 .get_msglevel = b44_get_msglevel,
1830 .set_msglevel = b44_set_msglevel,
3353930d
FR		 1831 .get_strings = b44_get_strings,
1832 .get_stats_count = b44_get_stats_count,
1833 .get_ethtool_stats = b44_get_ethtool_stats,
2160de53 1834 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1835};
1836
1837static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1838{
1839 struct mii_ioctl_data *data = if_mii(ifr);
1840 struct b44 *bp = netdev_priv(dev);
3410572d
FR		 1841 int err = -EINVAL;
1842
1843 if (!netif_running(dev))
1844 goto out;
1da177e4
LT		 1845
1846 spin_lock_irq(&bp->lock);
1847 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1848 spin_unlock_irq(&bp->lock);
3410572d 1849out:
1da177e4
LT		 1850 return err;
1851}
1852
1853/* Read 128-bytes of EEPROM. */
1854static int b44_read_eeprom(struct b44 *bp, u8 *data)
1855{
1856 long i;
1857 u16 *ptr = (u16 *) data;
1858
1859 for (i = 0; i < 128; i += 2)
1860 ptr[i / 2] = readw(bp->regs + 4096 + i);
1861
1862 return 0;
1863}
1864
1865static int __devinit b44_get_invariants(struct b44 *bp)
1866{
1867 u8 eeprom[128];
1868 int err;
1869
1870 err = b44_read_eeprom(bp, &eeprom[0]);
1871 if (err)
1872 goto out;
1873
1874 bp->dev->dev_addr[0] = eeprom[79];
1875 bp->dev->dev_addr[1] = eeprom[78];
1876 bp->dev->dev_addr[2] = eeprom[81];
1877 bp->dev->dev_addr[3] = eeprom[80];
1878 bp->dev->dev_addr[4] = eeprom[83];
1879 bp->dev->dev_addr[5] = eeprom[82];
2160de53 1880 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
1da177e4
LT		 1881
1882 bp->phy_addr = eeprom[90] & 0x1f;
1883
1884 /* With this, plus the rx_header prepended to the data by the
1885 * hardware, we'll land the ethernet header on a 2-byte boundary.
1886 */
1887 bp->rx_offset = 30;
1888
1889 bp->imask = IMASK_DEF;
1890
1891 bp->core_unit = ssb_core_unit(bp);
1892 bp->dma_offset = SB_PCI_DMA;
1893
1894 /* XXX - really required?
1895 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1896 */
1897out:
1898 return err;
1899}
1900
1901static int __devinit b44_init_one(struct pci_dev *pdev,
1902 const struct pci_device_id *ent)
1903{
1904 static int b44_version_printed = 0;
1905 unsigned long b44reg_base, b44reg_len;
1906 struct net_device *dev;
1907 struct b44 *bp;
1908 int err, i;
1909
1910 if (b44_version_printed++ == 0)
1911 printk(KERN_INFO "%s", version);
1912
1913 err = pci_enable_device(pdev);
1914 if (err) {
1915 printk(KERN_ERR PFX "Cannot enable PCI device, "
1916 "aborting.\n");
1917 return err;
1918 }
1919
1920 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1921 printk(KERN_ERR PFX "Cannot find proper PCI device "
1922 "base address, aborting.\n");
1923 err = -ENODEV;
1924 goto err_out_disable_pdev;
1925 }
1926
1927 err = pci_request_regions(pdev, DRV_MODULE_NAME);
1928 if (err) {
1929 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1930 "aborting.\n");
1931 goto err_out_disable_pdev;
1932 }
1933
1934 pci_set_master(pdev);
1935
1936 err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1937 if (err) {
1938 printk(KERN_ERR PFX "No usable DMA configuration, "
1939 "aborting.\n");
1940 goto err_out_free_res;
1941 }
1942
1943 err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1944 if (err) {
874a6214
FR		 1945 printk(KERN_ERR PFX "No usable DMA configuration, "
1946 "aborting.\n");
1947 goto err_out_free_res;
1da177e4
LT		 1948 }
1949
1950 b44reg_base = pci_resource_start(pdev, 0);
1951 b44reg_len = pci_resource_len(pdev, 0);
1952
1953 dev = alloc_etherdev(sizeof(*bp));
1954 if (!dev) {
1955 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1956 err = -ENOMEM;
1957 goto err_out_free_res;
1958 }
1959
1960 SET_MODULE_OWNER(dev);
1961 SET_NETDEV_DEV(dev,&pdev->dev);
1962
1963 /* No interesting netdevice features in this card... */
1964 dev->features |= 0;
1965
1966 bp = netdev_priv(dev);
1967 bp->pdev = pdev;
1968 bp->dev = dev;
874a6214
FR		 1969
1970 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
1da177e4
LT		 1971
1972 spin_lock_init(&bp->lock);
1973
1974 bp->regs = ioremap(b44reg_base, b44reg_len);
1975 if (bp->regs == 0UL) {
1976 printk(KERN_ERR PFX "Cannot map device registers, "
1977 "aborting.\n");
1978 err = -ENOMEM;
1979 goto err_out_free_dev;
1980 }
1981
1982 bp->rx_pending = B44_DEF_RX_RING_PENDING;
1983 bp->tx_pending = B44_DEF_TX_RING_PENDING;
1984
1985 dev->open = b44_open;
1986 dev->stop = b44_close;
1987 dev->hard_start_xmit = b44_start_xmit;
1988 dev->get_stats = b44_get_stats;
1989 dev->set_multicast_list = b44_set_rx_mode;
1990 dev->set_mac_address = b44_set_mac_addr;
1991 dev->do_ioctl = b44_ioctl;
1992 dev->tx_timeout = b44_tx_timeout;
1993 dev->poll = b44_poll;
1994 dev->weight = 64;
1995 dev->watchdog_timeo = B44_TX_TIMEOUT;
1996#ifdef CONFIG_NET_POLL_CONTROLLER
1997 dev->poll_controller = b44_poll_controller;
1998#endif
1999 dev->change_mtu = b44_change_mtu;
2000 dev->irq = pdev->irq;
2001 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2002
2003 err = b44_get_invariants(bp);
2004 if (err) {
2005 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
2006 "aborting.\n");
2007 goto err_out_iounmap;
2008 }
2009
2010 bp->mii_if.dev = dev;
2011 bp->mii_if.mdio_read = b44_mii_read;
2012 bp->mii_if.mdio_write = b44_mii_write;
2013 bp->mii_if.phy_id = bp->phy_addr;
2014 bp->mii_if.phy_id_mask = 0x1f;
2015 bp->mii_if.reg_num_mask = 0x1f;
2016
2017 /* By default, advertise all speed/duplex settings. */
2018 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2019 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2020
2021 /* By default, auto-negotiate PAUSE. */
2022 bp->flags |= B44_FLAG_PAUSE_AUTO;
2023
2024 err = register_netdev(dev);
2025 if (err) {
2026 printk(KERN_ERR PFX "Cannot register net device, "
2027 "aborting.\n");
2028 goto err_out_iounmap;
2029 }
2030
2031 pci_set_drvdata(pdev, dev);
2032
2033 pci_save_state(bp->pdev);
2034
2035 printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
2036 for (i = 0; i < 6; i++)
2037 printk("%2.2x%c", dev->dev_addr[i],
2038 i == 5 ? '\n' : ':');
2039
2040 return 0;
2041
2042err_out_iounmap:
2043 iounmap(bp->regs);
2044
2045err_out_free_dev:
2046 free_netdev(dev);
2047
2048err_out_free_res:
2049 pci_release_regions(pdev);
2050
2051err_out_disable_pdev:
2052 pci_disable_device(pdev);
2053 pci_set_drvdata(pdev, NULL);
2054 return err;
2055}
2056
2057static void __devexit b44_remove_one(struct pci_dev *pdev)
2058{
2059 struct net_device *dev = pci_get_drvdata(pdev);
874a6214 2060 struct b44 *bp = netdev_priv(dev);
1da177e4 2061
874a6214
FR		 2062 unregister_netdev(dev);
2063 iounmap(bp->regs);
2064 free_netdev(dev);
2065 pci_release_regions(pdev);
2066 pci_disable_device(pdev);
2067 pci_set_drvdata(pdev, NULL);
1da177e4
LT		 2068}
2069
2070static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
2071{
2072 struct net_device *dev = pci_get_drvdata(pdev);
2073 struct b44 *bp = netdev_priv(dev);
2074
2075 if (!netif_running(dev))
2076 return 0;
2077
2078 del_timer_sync(&bp->timer);
2079
2080 spin_lock_irq(&bp->lock);
2081
2082 b44_halt(bp);
2083 netif_carrier_off(bp->dev);
2084 netif_device_detach(bp->dev);
2085 b44_free_rings(bp);
2086
2087 spin_unlock_irq(&bp->lock);
46e17853
PM		 2088
2089 free_irq(dev->irq, dev);
d58da590 2090 pci_disable_device(pdev);
1da177e4
LT		 2091 return 0;
2092}
2093
2094static int b44_resume(struct pci_dev *pdev)
2095{
2096 struct net_device *dev = pci_get_drvdata(pdev);
2097 struct b44 *bp = netdev_priv(dev);
2098
2099 pci_restore_state(pdev);
d58da590
DSL		 2100 pci_enable_device(pdev);
2101 pci_set_master(pdev);
1da177e4
LT		 2102
2103 if (!netif_running(dev))
2104 return 0;
2105
46e17853
PM		 2106 if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
2107 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2108
1da177e4
LT		 2109 spin_lock_irq(&bp->lock);
2110
2111 b44_init_rings(bp);
2112 b44_init_hw(bp);
2113 netif_device_attach(bp->dev);
2114 spin_unlock_irq(&bp->lock);
2115
2116 bp->timer.expires = jiffies + HZ;
2117 add_timer(&bp->timer);
2118
2119 b44_enable_ints(bp);
d9e2d185 2120 netif_wake_queue(dev);
1da177e4
LT		 2121 return 0;
2122}
2123
2124static struct pci_driver b44_driver = {
2125 .name = DRV_MODULE_NAME,
2126 .id_table = b44_pci_tbl,
2127 .probe = b44_init_one,
2128 .remove = __devexit_p(b44_remove_one),
2129 .suspend = b44_suspend,
2130 .resume = b44_resume,
2131};
2132
2133static int __init b44_init(void)
2134{
9f38c636
JL		 2135 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2136
2137 /* Setup paramaters for syncing RX/TX DMA descriptors */
2138 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2139 dma_desc_sync_size = max(dma_desc_align_size, sizeof(struct dma_desc));
2140
1da177e4
LT		 2141 return pci_module_init(&b44_driver);
2142}
2143
2144static void __exit b44_cleanup(void)
2145{
2146 pci_unregister_driver(&b44_driver);
2147}
2148
2149module_init(b44_init);
2150module_exit(b44_cleanup);
2151
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