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Merge branch 'fix/asoc' into for-linus
[net-next-2.6.git] / drivers / net / atlx / atl1.c
CommitLineData
f3cc28c7
JC		 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
305282ba 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
e8f720fd 4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
f3cc28c7
JC		 5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
c8f2d9bc
JC		 27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
f3cc28c7
JC		 29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
c8f2d9bc 32 * This version is adapted from the Attansic reference driver.
f3cc28c7
JC		 33 *
34 * TODO:
53ffb42c 35 * Add more ethtool functions.
f3cc28c7
JC		 36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
305282ba
JC		 47#include <asm/atomic.h>
48#include <asm/byteorder.h>
49
50#include <linux/compiler.h>
51#include <linux/crc32.h>
52#include <linux/delay.h>
53#include <linux/dma-mapping.h>
f3cc28c7 54#include <linux/etherdevice.h>
f3cc28c7 55#include <linux/hardirq.h>
305282ba
JC		 56#include <linux/if_ether.h>
57#include <linux/if_vlan.h>
58#include <linux/in.h>
f3cc28c7 59#include <linux/interrupt.h>
305282ba 60#include <linux/ip.h>
f3cc28c7 61#include <linux/irqflags.h>
305282ba
JC		 62#include <linux/irqreturn.h>
63#include <linux/jiffies.h>
64#include <linux/mii.h>
65#include <linux/module.h>
66#include <linux/moduleparam.h>
f3cc28c7 67#include <linux/net.h>
305282ba
JC		 68#include <linux/netdevice.h>
69#include <linux/pci.h>
70#include <linux/pci_ids.h>
f3cc28c7 71#include <linux/pm.h>
305282ba
JC		 72#include <linux/skbuff.h>
73#include <linux/slab.h>
74#include <linux/spinlock.h>
75#include <linux/string.h>
f3cc28c7 76#include <linux/tcp.h>
305282ba
JC		 77#include <linux/timer.h>
78#include <linux/types.h>
79#include <linux/workqueue.h>
f3cc28c7 80
f3cc28c7
JC		 81#include <net/checksum.h>
82
f3cc28c7
JC		 83#include "atl1.h"
84
5ad18900
AC		 85#define ATLX_DRIVER_VERSION "2.1.3"
86MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
44ebb952 87Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
5ad18900
AC		 88MODULE_LICENSE("GPL");
89MODULE_VERSION(ATLX_DRIVER_VERSION);
90
305282ba
JC		 91/* Temporary hack for merging atl1 and atl2 */
92#include "atlx.c"
f3cc28c7 93
8ec7226a
CS		 94/*
95 * This is the only thing that needs to be changed to adjust the
96 * maximum number of ports that the driver can manage.
97 */
98#define ATL1_MAX_NIC 4
99
100#define OPTION_UNSET -1
101#define OPTION_DISABLED 0
102#define OPTION_ENABLED 1
103
104#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
105
106/*
107 * Interrupt Moderate Timer in units of 2 us
108 *
109 * Valid Range: 10-65535
110 *
111 * Default Value: 100 (200us)
112 */
113static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
b79d8fff 114static unsigned int num_int_mod_timer;
8ec7226a
CS		 115module_param_array_named(int_mod_timer, int_mod_timer, int,
116 &num_int_mod_timer, 0);
117MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
118
119#define DEFAULT_INT_MOD_CNT 100 /* 200us */
120#define MAX_INT_MOD_CNT 65000
121#define MIN_INT_MOD_CNT 50
122
123struct atl1_option {
124 enum { enable_option, range_option, list_option } type;
125 char *name;
126 char *err;
127 int def;
128 union {
129 struct { /* range_option info */
130 int min;
131 int max;
132 } r;
133 struct { /* list_option info */
134 int nr;
135 struct atl1_opt_list {
136 int i;
137 char *str;
138 } *p;
139 } l;
140 } arg;
141};
142
143static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
144 struct pci_dev *pdev)
145{
146 if (*value == OPTION_UNSET) {
147 *value = opt->def;
148 return 0;
149 }
150
151 switch (opt->type) {
152 case enable_option:
153 switch (*value) {
154 case OPTION_ENABLED:
155 dev_info(&pdev->dev, "%s enabled\n", opt->name);
156 return 0;
157 case OPTION_DISABLED:
158 dev_info(&pdev->dev, "%s disabled\n", opt->name);
159 return 0;
160 }
161 break;
162 case range_option:
163 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
164 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
165 *value);
166 return 0;
167 }
168 break;
169 case list_option:{
170 int i;
171 struct atl1_opt_list *ent;
172
173 for (i = 0; i < opt->arg.l.nr; i++) {
174 ent = &opt->arg.l.p[i];
175 if (*value == ent->i) {
176 if (ent->str[0] != '\0')
177 dev_info(&pdev->dev, "%s\n",
178 ent->str);
179 return 0;
180 }
181 }
182 }
183 break;
184
185 default:
186 break;
187 }
188
189 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
190 opt->name, *value, opt->err);
191 *value = opt->def;
192 return -1;
193}
194
195/*
196 * atl1_check_options - Range Checking for Command Line Parameters
197 * @adapter: board private structure
198 *
199 * This routine checks all command line parameters for valid user
200 * input. If an invalid value is given, or if no user specified
201 * value exists, a default value is used. The final value is stored
202 * in a variable in the adapter structure.
203 */
9dc20f55 204static void __devinit atl1_check_options(struct atl1_adapter *adapter)
8ec7226a
CS		 205{
206 struct pci_dev *pdev = adapter->pdev;
207 int bd = adapter->bd_number;
208 if (bd >= ATL1_MAX_NIC) {
209 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
210 dev_notice(&pdev->dev, "using defaults for all values\n");
211 }
212 { /* Interrupt Moderate Timer */
213 struct atl1_option opt = {
214 .type = range_option,
215 .name = "Interrupt Moderator Timer",
216 .err = "using default of "
217 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
218 .def = DEFAULT_INT_MOD_CNT,
219 .arg = {.r = {.min = MIN_INT_MOD_CNT,
220 .max = MAX_INT_MOD_CNT} }
221 };
222 int val;
223 if (num_int_mod_timer > bd) {
224 val = int_mod_timer[bd];
225 atl1_validate_option(&val, &opt, pdev);
226 adapter->imt = (u16) val;
227 } else
228 adapter->imt = (u16) (opt.def);
229 }
230}
231
f3cc28c7
JC		 232/*
233 * atl1_pci_tbl - PCI Device ID Table
234 */
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
e81e557a 236 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
f3cc28c7
JC		 237 /* required last entry */
238 {0,}
239};
f3cc28c7
JC		 240MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
241
460578bf
JC		 242static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
243 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
244
245static int debug = -1;
246module_param(debug, int, 0);
247MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
248
f3cc28c7 249/*
6446a860
JC		 250 * Reset the transmit and receive units; mask and clear all interrupts.
251 * hw - Struct containing variables accessed by shared code
252 * return : 0 or idle status (if error)
f3cc28c7 253 */
6446a860 254static s32 atl1_reset_hw(struct atl1_hw *hw)
f3cc28c7 255{
6446a860
JC		 256 struct pci_dev *pdev = hw->back->pdev;
257 struct atl1_adapter *adapter = hw->back;
258 u32 icr;
259 int i;
f3cc28c7 260
6446a860
JC		 261 /*
262 * Clear Interrupt mask to stop board from generating
263 * interrupts & Clear any pending interrupt events
264 */
265 /*
266 * iowrite32(0, hw->hw_addr + REG_IMR);
267 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
268 */
f3cc28c7 269
6446a860
JC		 270 /*
271 * Issue Soft Reset to the MAC. This will reset the chip's
272 * transmit, receive, DMA. It will not effect
273 * the current PCI configuration. The global reset bit is self-
274 * clearing, and should clear within a microsecond.
275 */
276 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
277 ioread32(hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 278
6446a860
JC		 279 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
280 ioread16(hw->hw_addr + REG_PHY_ENABLE);
f3cc28c7 281
6446a860
JC		 282 /* delay about 1ms */
283 msleep(1);
f3cc28c7 284
6446a860
JC		 285 /* Wait at least 10ms for All module to be Idle */
286 for (i = 0; i < 10; i++) {
287 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
288 if (!icr)
289 break;
290 /* delay 1 ms */
291 msleep(1);
292 /* FIXME: still the right way to do this? */
293 cpu_relax();
294 }
05ffdd7b 295
6446a860
JC		 296 if (icr) {
297 if (netif_msg_hw(adapter))
298 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
299 return icr;
300 }
05ffdd7b 301
6446a860 302 return 0;
05ffdd7b
JC		 303}
304
6446a860
JC		 305/* function about EEPROM
306 *
307 * check_eeprom_exist
308 * return 0 if eeprom exist
309 */
310static int atl1_check_eeprom_exist(struct atl1_hw *hw)
05ffdd7b 311{
6446a860
JC		 312 u32 value;
313 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
314 if (value & SPI_FLASH_CTRL_EN_VPD) {
315 value &= ~SPI_FLASH_CTRL_EN_VPD;
316 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
317 }
05ffdd7b 318
6446a860
JC		 319 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
320 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
05ffdd7b
JC		 321}
322
6446a860 323static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
05ffdd7b 324{
6446a860
JC		 325 int i;
326 u32 control;
05ffdd7b 327
6446a860
JC		 328 if (offset & 3)
329 /* address do not align */
330 return false;
05ffdd7b 331
6446a860
JC		 332 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
333 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
334 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
335 ioread32(hw->hw_addr + REG_VPD_CAP);
05ffdd7b 336
6446a860
JC		 337 for (i = 0; i < 10; i++) {
338 msleep(2);
339 control = ioread32(hw->hw_addr + REG_VPD_CAP);
340 if (control & VPD_CAP_VPD_FLAG)
341 break;
342 }
343 if (control & VPD_CAP_VPD_FLAG) {
344 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
345 return true;
346 }
347 /* timeout */
348 return false;
05ffdd7b
JC		 349}
350
f3cc28c7 351/*
6446a860
JC		 352 * Reads the value from a PHY register
353 * hw - Struct containing variables accessed by shared code
354 * reg_addr - address of the PHY register to read
f3cc28c7 355 */
6446a860 356s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
f3cc28c7 357{
6446a860
JC		 358 u32 val;
359 int i;
f3cc28c7 360
6446a860
JC		 361 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
362 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
363 MDIO_CLK_SEL_SHIFT;
364 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
365 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 366
6446a860
JC		 367 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
368 udelay(2);
369 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
370 if (!(val & (MDIO_START | MDIO_BUSY)))
371 break;
372 }
373 if (!(val & (MDIO_START | MDIO_BUSY))) {
374 *phy_data = (u16) val;
375 return 0;
f3cc28c7 376 }
6446a860
JC		 377 return ATLX_ERR_PHY;
378}
f3cc28c7 379
6446a860
JC		 380#define CUSTOM_SPI_CS_SETUP 2
381#define CUSTOM_SPI_CLK_HI 2
382#define CUSTOM_SPI_CLK_LO 2
383#define CUSTOM_SPI_CS_HOLD 2
384#define CUSTOM_SPI_CS_HI 3
f3cc28c7 385
6446a860
JC		 386static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
387{
388 int i;
389 u32 value;
f3cc28c7 390
6446a860
JC		 391 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
392 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
2ca13da7 393
6446a860
JC		 394 value = SPI_FLASH_CTRL_WAIT_READY |
395 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
396 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
397 SPI_FLASH_CTRL_CLK_HI_MASK) <<
398 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
399 SPI_FLASH_CTRL_CLK_LO_MASK) <<
400 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
401 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
402 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
403 SPI_FLASH_CTRL_CS_HI_MASK) <<
404 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
405 SPI_FLASH_CTRL_INS_SHIFT;
f3cc28c7 406
6446a860 407 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 408
6446a860
JC		 409 value |= SPI_FLASH_CTRL_START;
410 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
411 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 412
6446a860
JC		 413 for (i = 0; i < 10; i++) {
414 msleep(1);
415 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
416 if (!(value & SPI_FLASH_CTRL_START))
417 break;
418 }
f3cc28c7 419
6446a860
JC		 420 if (value & SPI_FLASH_CTRL_START)
421 return false;
f3cc28c7 422
6446a860 423 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
2ca13da7 424
6446a860 425 return true;
f3cc28c7
JC		 426}
427
f3cc28c7 428/*
6446a860
JC		 429 * get_permanent_address
430 * return 0 if get valid mac address,
f3cc28c7 431 */
6446a860 432static int atl1_get_permanent_address(struct atl1_hw *hw)
f3cc28c7 433{
6446a860
JC		 434 u32 addr[2];
435 u32 i, control;
436 u16 reg;
437 u8 eth_addr[ETH_ALEN];
438 bool key_valid;
f3cc28c7 439
6446a860
JC		 440 if (is_valid_ether_addr(hw->perm_mac_addr))
441 return 0;
442
443 /* init */
444 addr[0] = addr[1] = 0;
445
446 if (!atl1_check_eeprom_exist(hw)) {
447 reg = 0;
448 key_valid = false;
449 /* Read out all EEPROM content */
450 i = 0;
451 while (1) {
452 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
453 if (key_valid) {
454 if (reg == REG_MAC_STA_ADDR)
455 addr[0] = control;
456 else if (reg == (REG_MAC_STA_ADDR + 4))
457 addr[1] = control;
458 key_valid = false;
459 } else if ((control & 0xff) == 0x5A) {
460 key_valid = true;
461 reg = (u16) (control >> 16);
462 } else
463 break;
464 } else
465 /* read error */
466 break;
467 i += 4;
05ffdd7b 468 }
6446a860
JC		 469
470 *(u32 *) &eth_addr[2] = swab32(addr[0]);
471 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
472 if (is_valid_ether_addr(eth_addr)) {
473 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
474 return 0;
05ffdd7b
JC		 475 }
476 }
f3cc28c7 477
6446a860
JC		 478 /* see if SPI FLAGS exist ? */
479 addr[0] = addr[1] = 0;
480 reg = 0;
481 key_valid = false;
482 i = 0;
483 while (1) {
484 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
485 if (key_valid) {
486 if (reg == REG_MAC_STA_ADDR)
487 addr[0] = control;
488 else if (reg == (REG_MAC_STA_ADDR + 4))
489 addr[1] = control;
490 key_valid = false;
491 } else if ((control & 0xff) == 0x5A) {
492 key_valid = true;
493 reg = (u16) (control >> 16);
494 } else
495 /* data end */
496 break;
497 } else
498 /* read error */
499 break;
500 i += 4;
501 }
f3cc28c7 502
6446a860
JC		 503 *(u32 *) &eth_addr[2] = swab32(addr[0]);
504 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
505 if (is_valid_ether_addr(eth_addr)) {
506 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
507 return 0;
508 }
f3cc28c7 509
6446a860
JC		 510 /*
511 * On some motherboards, the MAC address is written by the
512 * BIOS directly to the MAC register during POST, and is
513 * not stored in eeprom. If all else thus far has failed
514 * to fetch the permanent MAC address, try reading it directly.
515 */
516 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
517 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
518 *(u32 *) &eth_addr[2] = swab32(addr[0]);
519 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
520 if (is_valid_ether_addr(eth_addr)) {
521 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
522 return 0;
523 }
f3cc28c7 524
6446a860 525 return 1;
f3cc28c7
JC		 526}
527
05ffdd7b 528/*
6446a860
JC		 529 * Reads the adapter's MAC address from the EEPROM
530 * hw - Struct containing variables accessed by shared code
05ffdd7b 531 */
9dc20f55 532static s32 atl1_read_mac_addr(struct atl1_hw *hw)
f3cc28c7 533{
6446a860 534 u16 i;
f3cc28c7 535
6446a860
JC		 536 if (atl1_get_permanent_address(hw))
537 random_ether_addr(hw->perm_mac_addr);
f3cc28c7 538
6446a860
JC		 539 for (i = 0; i < ETH_ALEN; i++)
540 hw->mac_addr[i] = hw->perm_mac_addr[i];
541 return 0;
f3cc28c7
JC		 542}
543
544/*
6446a860
JC		 545 * Hashes an address to determine its location in the multicast table
546 * hw - Struct containing variables accessed by shared code
547 * mc_addr - the multicast address to hash
05ffdd7b 548 *
6446a860
JC		 549 * atl1_hash_mc_addr
550 * purpose
551 * set hash value for a multicast address
552 * hash calcu processing :
553 * 1. calcu 32bit CRC for multicast address
554 * 2. reverse crc with MSB to LSB
f3cc28c7 555 */
6446a860 556u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
f3cc28c7 557{
6446a860
JC		 558 u32 crc32, value = 0;
559 int i;
f3cc28c7 560
6446a860
JC		 561 crc32 = ether_crc_le(6, mc_addr);
562 for (i = 0; i < 32; i++)
563 value |= (((crc32 >> i) & 1) << (31 - i));
f3cc28c7 564
6446a860 565 return value;
f3cc28c7
JC		 566}
567
6446a860
JC		 568/*
569 * Sets the bit in the multicast table corresponding to the hash value.
570 * hw - Struct containing variables accessed by shared code
571 * hash_value - Multicast address hash value
572 */
573void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
f3cc28c7 574{
6446a860
JC		 575 u32 hash_bit, hash_reg;
576 u32 mta;
577
578 /*
579 * The HASH Table is a register array of 2 32-bit registers.
580 * It is treated like an array of 64 bits. We want to set
581 * bit BitArray[hash_value]. So we figure out what register
582 * the bit is in, read it, OR in the new bit, then write
583 * back the new value. The register is determined by the
584 * upper 7 bits of the hash value and the bit within that
585 * register are determined by the lower 5 bits of the value.
05ffdd7b 586 */
6446a860
JC		 587 hash_reg = (hash_value >> 31) & 0x1;
588 hash_bit = (hash_value >> 26) & 0x1F;
589 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
590 mta |= (1 << hash_bit);
591 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
05ffdd7b 592}
f3cc28c7 593
6446a860
JC		 594/*
595 * Writes a value to a PHY register
596 * hw - Struct containing variables accessed by shared code
597 * reg_addr - address of the PHY register to write
598 * data - data to write to the PHY
599 */
600static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
05ffdd7b 601{
6446a860
JC		 602 int i;
603 u32 val;
f3cc28c7 604
6446a860
JC		 605 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
606 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
607 MDIO_SUP_PREAMBLE |
608 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
609 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
610 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 611
6446a860
JC		 612 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
613 udelay(2);
614 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
615 if (!(val & (MDIO_START | MDIO_BUSY)))
616 break;
05ffdd7b 617 }
f3cc28c7 618
6446a860 619 if (!(val & (MDIO_START | MDIO_BUSY)))
305282ba 620 return 0;
f3cc28c7 621
6446a860
JC		 622 return ATLX_ERR_PHY;
623}
f3cc28c7 624
6446a860
JC		 625/*
626 * Make L001's PHY out of Power Saving State (bug)
627 * hw - Struct containing variables accessed by shared code
628 * when power on, L001's PHY always on Power saving State
629 * (Gigabit Link forbidden)
630 */
631static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
632{
633 s32 ret;
634 ret = atl1_write_phy_reg(hw, 29, 0x0029);
635 if (ret)
636 return ret;
637 return atl1_write_phy_reg(hw, 30, 0);
638}
639
6446a860
JC		 640/*
641 * Resets the PHY and make all config validate
642 * hw - Struct containing variables accessed by shared code
643 *
644 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
645 */
646static s32 atl1_phy_reset(struct atl1_hw *hw)
647{
648 struct pci_dev *pdev = hw->back->pdev;
649 struct atl1_adapter *adapter = hw->back;
650 s32 ret_val;
651 u16 phy_data;
652
653 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
654 hw->media_type == MEDIA_TYPE_1000M_FULL)
655 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
656 else {
05ffdd7b
JC		 657 switch (hw->media_type) {
658 case MEDIA_TYPE_100M_FULL:
6446a860
JC		 659 phy_data =
660 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
661 MII_CR_RESET;
05ffdd7b
JC		 662 break;
663 case MEDIA_TYPE_100M_HALF:
664 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
665 break;
666 case MEDIA_TYPE_10M_FULL:
667 phy_data =
668 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
669 break;
305282ba
JC		 670 default:
671 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 672 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
673 break;
f3cc28c7 674 }
f3cc28c7 675 }
f3cc28c7 676
6446a860
JC		 677 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
678 if (ret_val) {
679 u32 val;
680 int i;
681 /* pcie serdes link may be down! */
682 if (netif_msg_hw(adapter))
683 dev_dbg(&pdev->dev, "pcie phy link down\n");
684
685 for (i = 0; i < 25; i++) {
686 msleep(1);
687 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
688 if (!(val & (MDIO_START | MDIO_BUSY)))
689 break;
690 }
f3cc28c7 691
6446a860
JC		 692 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
693 if (netif_msg_hw(adapter))
694 dev_warn(&pdev->dev,
695 "pcie link down at least 25ms\n");
696 return ret_val;
697 }
698 }
305282ba 699 return 0;
2ca13da7
JC		 700}
701
6446a860
JC		 702/*
703 * Configures PHY autoneg and flow control advertisement settings
704 * hw - Struct containing variables accessed by shared code
705 */
706static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
05ffdd7b 707{
6446a860
JC		 708 s32 ret_val;
709 s16 mii_autoneg_adv_reg;
710 s16 mii_1000t_ctrl_reg;
f3cc28c7 711
6446a860
JC		 712 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
713 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
f3cc28c7 714
6446a860
JC		 715 /* Read the MII 1000Base-T Control Register (Address 9). */
716 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
f3cc28c7 717
6446a860
JC		 718 /*
719 * First we clear all the 10/100 mb speed bits in the Auto-Neg
720 * Advertisement Register (Address 4) and the 1000 mb speed bits in
721 * the 1000Base-T Control Register (Address 9).
722 */
723 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
724 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
f3cc28c7 725
6446a860
JC		 726 /*
727 * Need to parse media_type and set up
728 * the appropriate PHY registers.
729 */
730 switch (hw->media_type) {
731 case MEDIA_TYPE_AUTO_SENSOR:
732 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
733 MII_AR_10T_FD_CAPS |
734 MII_AR_100TX_HD_CAPS |
735 MII_AR_100TX_FD_CAPS);
736 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
737 break;
f3cc28c7 738
6446a860
JC		 739 case MEDIA_TYPE_1000M_FULL:
740 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
741 break;
f3cc28c7 742
6446a860
JC		 743 case MEDIA_TYPE_100M_FULL:
744 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
745 break;
f3cc28c7 746
6446a860
JC		 747 case MEDIA_TYPE_100M_HALF:
748 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
749 break;
f3cc28c7 750
6446a860
JC		 751 case MEDIA_TYPE_10M_FULL:
752 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
05ffdd7b 753 break;
6446a860 754
05ffdd7b 755 default:
6446a860 756 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
05ffdd7b 757 break;
f3cc28c7 758 }
f3cc28c7 759
6446a860
JC		 760 /* flow control fixed to enable all */
761 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
f3cc28c7 762
6446a860
JC		 763 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
764 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
f3cc28c7 765
6446a860
JC		 766 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
767 if (ret_val)
768 return ret_val;
f3cc28c7 769
6446a860
JC		 770 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
771 if (ret_val)
772 return ret_val;
f3cc28c7 773
6446a860 774 return 0;
f3cc28c7 775}
f3cc28c7 776
05ffdd7b 777/*
6446a860
JC		 778 * Configures link settings.
779 * hw - Struct containing variables accessed by shared code
780 * Assumes the hardware has previously been reset and the
781 * transmitter and receiver are not enabled.
05ffdd7b 782 */
6446a860 783static s32 atl1_setup_link(struct atl1_hw *hw)
f3cc28c7 784{
6446a860
JC		 785 struct pci_dev *pdev = hw->back->pdev;
786 struct atl1_adapter *adapter = hw->back;
787 s32 ret_val;
f3cc28c7 788
6446a860
JC		 789 /*
790 * Options:
791 * PHY will advertise value(s) parsed from
792 * autoneg_advertised and fc
793 * no matter what autoneg is , We will not wait link result.
794 */
795 ret_val = atl1_phy_setup_autoneg_adv(hw);
796 if (ret_val) {
797 if (netif_msg_link(adapter))
798 dev_dbg(&pdev->dev,
799 "error setting up autonegotiation\n");
800 return ret_val;
801 }
802 /* SW.Reset , En-Auto-Neg if needed */
803 ret_val = atl1_phy_reset(hw);
804 if (ret_val) {
805 if (netif_msg_link(adapter))
806 dev_dbg(&pdev->dev, "error resetting phy\n");
807 return ret_val;
808 }
809 hw->phy_configured = true;
810 return ret_val;
811}
f3cc28c7 812
6446a860 813static void atl1_init_flash_opcode(struct atl1_hw *hw)
f3cc28c7 814{
6446a860
JC		 815 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
816 /* Atmel */
817 hw->flash_vendor = 0;
f3cc28c7 818
6446a860
JC		 819 /* Init OP table */
820 iowrite8(flash_table[hw->flash_vendor].cmd_program,
821 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
822 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
823 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
824 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
825 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
826 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
827 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
828 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
829 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
830 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
831 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
832 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
833 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
834 iowrite8(flash_table[hw->flash_vendor].cmd_read,
835 hw->hw_addr + REG_SPI_FLASH_OP_READ);
f3cc28c7 836}
f3cc28c7 837
6446a860
JC		 838/*
839 * Performs basic configuration of the adapter.
840 * hw - Struct containing variables accessed by shared code
841 * Assumes that the controller has previously been reset and is in a
842 * post-reset uninitialized state. Initializes multicast table,
843 * and Calls routines to setup link
844 * Leaves the transmit and receive units disabled and uninitialized.
845 */
846static s32 atl1_init_hw(struct atl1_hw *hw)
05ffdd7b 847{
6446a860 848 u32 ret_val = 0;
f3cc28c7 849
6446a860
JC		 850 /* Zero out the Multicast HASH table */
851 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
852 /* clear the old settings from the multicast hash table */
853 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
f3cc28c7 854
6446a860 855 atl1_init_flash_opcode(hw);
f3cc28c7 856
6446a860
JC		 857 if (!hw->phy_configured) {
858 /* enable GPHY LinkChange Interrrupt */
859 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
860 if (ret_val)
861 return ret_val;
862 /* make PHY out of power-saving state */
863 ret_val = atl1_phy_leave_power_saving(hw);
864 if (ret_val)
865 return ret_val;
866 /* Call a subroutine to configure the link */
867 ret_val = atl1_setup_link(hw);
868 }
869 return ret_val;
f3cc28c7 870}
f3cc28c7
JC		 871
872/*
6446a860
JC		 873 * Detects the current speed and duplex settings of the hardware.
874 * hw - Struct containing variables accessed by shared code
875 * speed - Speed of the connection
876 * duplex - Duplex setting of the connection
f3cc28c7 877 */
6446a860 878static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
f3cc28c7 879{
6446a860
JC		 880 struct pci_dev *pdev = hw->back->pdev;
881 struct atl1_adapter *adapter = hw->back;
882 s32 ret_val;
883 u16 phy_data;
f3cc28c7 884
6446a860
JC		 885 /* ; --- Read PHY Specific Status Register (17) */
886 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
887 if (ret_val)
888 return ret_val;
f3cc28c7 889
6446a860
JC		 890 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
891 return ATLX_ERR_PHY_RES;
f3cc28c7 892
6446a860
JC		 893 switch (phy_data & MII_ATLX_PSSR_SPEED) {
894 case MII_ATLX_PSSR_1000MBS:
895 *speed = SPEED_1000;
896 break;
897 case MII_ATLX_PSSR_100MBS:
898 *speed = SPEED_100;
899 break;
900 case MII_ATLX_PSSR_10MBS:
901 *speed = SPEED_10;
902 break;
903 default:
904 if (netif_msg_hw(adapter))
905 dev_dbg(&pdev->dev, "error getting speed\n");
906 return ATLX_ERR_PHY_SPEED;
907 break;
f3cc28c7 908 }
6446a860
JC		 909 if (phy_data & MII_ATLX_PSSR_DPLX)
910 *duplex = FULL_DUPLEX;
911 else
912 *duplex = HALF_DUPLEX;
913
914 return 0;
05ffdd7b 915}
f3cc28c7 916
6446a860 917void atl1_set_mac_addr(struct atl1_hw *hw)
05ffdd7b 918{
6446a860
JC		 919 u32 value;
920 /*
921 * 00-0B-6A-F6-00-DC
922 * 0: 6AF600DC 1: 000B
923 * low dword
924 */
925 value = (((u32) hw->mac_addr[2]) << 24) |
926 (((u32) hw->mac_addr[3]) << 16) |
927 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
928 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
929 /* high dword */
930 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
931 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
05ffdd7b 932}
f3cc28c7
JC		 933
934/*
935 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
936 * @adapter: board private structure to initialize
937 *
938 * atl1_sw_init initializes the Adapter private data structure.
939 * Fields are initialized based on PCI device information and
940 * OS network device settings (MTU size).
941 */
942static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
943{
944 struct atl1_hw *hw = &adapter->hw;
945 struct net_device *netdev = adapter->netdev;
f3cc28c7 946
2a49128f 947 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
a3093d9b 948 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
f3cc28c7
JC		 949
950 adapter->wol = 0;
951 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
6446a860 952 adapter->ict = 50000; /* 100ms */
f3cc28c7
JC		 953 adapter->link_speed = SPEED_0; /* hardware init */
954 adapter->link_duplex = FULL_DUPLEX;
955
956 hw->phy_configured = false;
957 hw->preamble_len = 7;
958 hw->ipgt = 0x60;
959 hw->min_ifg = 0x50;
960 hw->ipgr1 = 0x40;
961 hw->ipgr2 = 0x60;
962 hw->max_retry = 0xf;
963 hw->lcol = 0x37;
964 hw->jam_ipg = 7;
965 hw->rfd_burst = 8;
966 hw->rrd_burst = 8;
967 hw->rfd_fetch_gap = 1;
968 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
969 hw->rx_jumbo_lkah = 1;
970 hw->rrd_ret_timer = 16;
971 hw->tpd_burst = 4;
972 hw->tpd_fetch_th = 16;
973 hw->txf_burst = 0x100;
974 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
975 hw->tpd_fetch_gap = 1;
976 hw->rcb_value = atl1_rcb_64;
977 hw->dma_ord = atl1_dma_ord_enh;
978 hw->dmar_block = atl1_dma_req_256;
979 hw->dmaw_block = atl1_dma_req_256;
980 hw->cmb_rrd = 4;
981 hw->cmb_tpd = 4;
982 hw->cmb_rx_timer = 1; /* about 2us */
983 hw->cmb_tx_timer = 1; /* about 2us */
984 hw->smb_timer = 100000; /* about 200ms */
985
f3cc28c7
JC		 986 spin_lock_init(&adapter->lock);
987 spin_lock_init(&adapter->mb_lock);
988
989 return 0;
990}
991
05ffdd7b
JC		 992static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
993{
994 struct atl1_adapter *adapter = netdev_priv(netdev);
995 u16 result;
996
997 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
998
999 return result;
1000}
1001
1002static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1003 int val)
1004{
1005 struct atl1_adapter *adapter = netdev_priv(netdev);
1006
1007 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1008}
1009
1010/*
1011 * atl1_mii_ioctl -
1012 * @netdev:
1013 * @ifreq:
1014 * @cmd:
1015 */
1016static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1017{
1018 struct atl1_adapter *adapter = netdev_priv(netdev);
1019 unsigned long flags;
1020 int retval;
1021
1022 if (!netif_running(netdev))
1023 return -EINVAL;
1024
1025 spin_lock_irqsave(&adapter->lock, flags);
1026 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1027 spin_unlock_irqrestore(&adapter->lock, flags);
1028
1029 return retval;
1030}
1031
f3cc28c7
JC		 1032/*
1033 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1034 * @adapter: board private structure
1035 *
1036 * Return 0 on success, negative on failure
1037 */
6446a860 1038static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
f3cc28c7
JC		 1039{
1040 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1041 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1042 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1043 struct atl1_ring_header *ring_header = &adapter->ring_header;
1044 struct pci_dev *pdev = adapter->pdev;
1045 int size;
1046 u8 offset = 0;
1047
1048 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1049 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1050 if (unlikely(!tpd_ring->buffer_info)) {
6446a860
JC		 1051 if (netif_msg_drv(adapter))
1052 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1053 size);
f3cc28c7
JC		 1054 goto err_nomem;
1055 }
1056 rfd_ring->buffer_info =
53ffb42c 1057 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
f3cc28c7 1058
6446a860
JC		 1059 /*
1060 * real ring DMA buffer
53ffb42c
JC		 1061 * each ring/block may need up to 8 bytes for alignment, hence the
1062 * additional 40 bytes tacked onto the end.
1063 */
1064 ring_header->size = size =
1065 sizeof(struct tx_packet_desc) * tpd_ring->count
1066 + sizeof(struct rx_free_desc) * rfd_ring->count
1067 + sizeof(struct rx_return_desc) * rrd_ring->count
1068 + sizeof(struct coals_msg_block)
1069 + sizeof(struct stats_msg_block)
1070 + 40;
f3cc28c7
JC		 1071
1072 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
53ffb42c 1073 &ring_header->dma);
f3cc28c7 1074 if (unlikely(!ring_header->desc)) {
6446a860
JC		 1075 if (netif_msg_drv(adapter))
1076 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
f3cc28c7
JC		 1077 goto err_nomem;
1078 }
1079
1080 memset(ring_header->desc, 0, ring_header->size);
1081
1082 /* init TPD ring */
1083 tpd_ring->dma = ring_header->dma;
1084 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1085 tpd_ring->dma += offset;
1086 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1087 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
f3cc28c7
JC		 1088
1089 /* init RFD ring */
1090 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1091 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1092 rfd_ring->dma += offset;
1093 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1094 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
2ca13da7 1095
f3cc28c7
JC		 1096
1097 /* init RRD ring */
1098 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1099 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1100 rrd_ring->dma += offset;
1101 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1102 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
2ca13da7 1103
f3cc28c7
JC		 1104
1105 /* init CMB */
1106 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1107 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1108 adapter->cmb.dma += offset;
53ffb42c
JC		 1109 adapter->cmb.cmb = (struct coals_msg_block *)
1110 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
f3cc28c7
JC		 1111
1112 /* init SMB */
1113 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1114 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1115 adapter->smb.dma += offset;
1116 adapter->smb.smb = (struct stats_msg_block *)
53ffb42c
JC		 1117 ((u8 *) adapter->cmb.cmb +
1118 (sizeof(struct coals_msg_block) + offset));
f3cc28c7 1119
6446a860 1120 return 0;
f3cc28c7
JC		 1121
1122err_nomem:
1123 kfree(tpd_ring->buffer_info);
1124 return -ENOMEM;
1125}
1126
3d2557f6 1127static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
f3cc28c7 1128{
2ca13da7
JC		 1129 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1130 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1131 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
f3cc28c7 1132
2ca13da7
JC		 1133 atomic_set(&tpd_ring->next_to_use, 0);
1134 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7 1135
2ca13da7
JC		 1136 rfd_ring->next_to_clean = 0;
1137 atomic_set(&rfd_ring->next_to_use, 0);
1138
1139 rrd_ring->next_to_use = 0;
1140 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1141}
1142
f3cc28c7 1143/*
05ffdd7b 1144 * atl1_clean_rx_ring - Free RFD Buffers
f3cc28c7
JC		 1145 * @adapter: board private structure
1146 */
05ffdd7b 1147static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
f3cc28c7 1148{
05ffdd7b
JC		 1149 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1150 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1151 struct atl1_buffer *buffer_info;
1152 struct pci_dev *pdev = adapter->pdev;
1153 unsigned long size;
1154 unsigned int i;
f3cc28c7 1155
05ffdd7b
JC		 1156 /* Free all the Rx ring sk_buffs */
1157 for (i = 0; i < rfd_ring->count; i++) {
1158 buffer_info = &rfd_ring->buffer_info[i];
1159 if (buffer_info->dma) {
1160 pci_unmap_page(pdev, buffer_info->dma,
1161 buffer_info->length, PCI_DMA_FROMDEVICE);
1162 buffer_info->dma = 0;
1163 }
1164 if (buffer_info->skb) {
1165 dev_kfree_skb(buffer_info->skb);
1166 buffer_info->skb = NULL;
1167 }
1168 }
f3cc28c7 1169
05ffdd7b
JC		 1170 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1171 memset(rfd_ring->buffer_info, 0, size);
f3cc28c7 1172
05ffdd7b
JC		 1173 /* Zero out the descriptor ring */
1174 memset(rfd_ring->desc, 0, rfd_ring->size);
f3cc28c7 1175
05ffdd7b
JC		 1176 rfd_ring->next_to_clean = 0;
1177 atomic_set(&rfd_ring->next_to_use, 0);
f3cc28c7 1178
05ffdd7b
JC		 1179 rrd_ring->next_to_use = 0;
1180 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1181}
1182
05ffdd7b
JC		 1183/*
1184 * atl1_clean_tx_ring - Free Tx Buffers
1185 * @adapter: board private structure
1186 */
1187static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
f3cc28c7 1188{
05ffdd7b
JC		 1189 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1190 struct atl1_buffer *buffer_info;
53ffb42c 1191 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1192 unsigned long size;
1193 unsigned int i;
f3cc28c7 1194
05ffdd7b
JC		 1195 /* Free all the Tx ring sk_buffs */
1196 for (i = 0; i < tpd_ring->count; i++) {
1197 buffer_info = &tpd_ring->buffer_info[i];
1198 if (buffer_info->dma) {
1199 pci_unmap_page(pdev, buffer_info->dma,
1200 buffer_info->length, PCI_DMA_TODEVICE);
1201 buffer_info->dma = 0;
f3cc28c7
JC		 1202 }
1203 }
1204
05ffdd7b
JC		 1205 for (i = 0; i < tpd_ring->count; i++) {
1206 buffer_info = &tpd_ring->buffer_info[i];
1207 if (buffer_info->skb) {
1208 dev_kfree_skb_any(buffer_info->skb);
1209 buffer_info->skb = NULL;
f3cc28c7 1210 }
f3cc28c7
JC		 1211 }
1212
05ffdd7b
JC		 1213 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1214 memset(tpd_ring->buffer_info, 0, size);
f3cc28c7 1215
05ffdd7b
JC		 1216 /* Zero out the descriptor ring */
1217 memset(tpd_ring->desc, 0, tpd_ring->size);
f3cc28c7 1218
05ffdd7b
JC		 1219 atomic_set(&tpd_ring->next_to_use, 0);
1220 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7
JC		 1221}
1222
1223/*
05ffdd7b
JC		 1224 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1225 * @adapter: board private structure
1226 *
1227 * Free all transmit software resources
f3cc28c7 1228 */
6446a860 1229static void atl1_free_ring_resources(struct atl1_adapter *adapter)
f3cc28c7 1230{
f3cc28c7 1231 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1232 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1233 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1234 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1235 struct atl1_ring_header *ring_header = &adapter->ring_header;
f3cc28c7 1236
05ffdd7b
JC		 1237 atl1_clean_tx_ring(adapter);
1238 atl1_clean_rx_ring(adapter);
f3cc28c7 1239
05ffdd7b
JC		 1240 kfree(tpd_ring->buffer_info);
1241 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1242 ring_header->dma);
f3cc28c7 1243
05ffdd7b
JC		 1244 tpd_ring->buffer_info = NULL;
1245 tpd_ring->desc = NULL;
1246 tpd_ring->dma = 0;
f3cc28c7 1247
05ffdd7b
JC		 1248 rfd_ring->buffer_info = NULL;
1249 rfd_ring->desc = NULL;
1250 rfd_ring->dma = 0;
f3cc28c7 1251
05ffdd7b
JC		 1252 rrd_ring->desc = NULL;
1253 rrd_ring->dma = 0;
3f5a2a71
LT		 1254
1255 adapter->cmb.dma = 0;
1256 adapter->cmb.cmb = NULL;
1257
1258 adapter->smb.dma = 0;
1259 adapter->smb.smb = NULL;
f3cc28c7
JC		 1260}
1261
05ffdd7b 1262static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
f3cc28c7 1263{
f3cc28c7 1264 u32 value;
05ffdd7b
JC		 1265 struct atl1_hw *hw = &adapter->hw;
1266 struct net_device *netdev = adapter->netdev;
1267 /* Config MAC CTRL Register */
1268 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1269 /* duplex */
1270 if (FULL_DUPLEX == adapter->link_duplex)
1271 value |= MAC_CTRL_DUPLX;
1272 /* speed */
1273 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1274 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1275 MAC_CTRL_SPEED_SHIFT);
1276 /* flow control */
1277 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1278 /* PAD & CRC */
1279 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1280 /* preamble length */
1281 value |= (((u32) adapter->hw.preamble_len
1282 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1283 /* vlan */
1284 if (adapter->vlgrp)
1285 value |= MAC_CTRL_RMV_VLAN;
1286 /* rx checksum
1287 if (adapter->rx_csum)
1288 value |= MAC_CTRL_RX_CHKSUM_EN;
1289 */
1290 /* filter mode */
1291 value |= MAC_CTRL_BC_EN;
1292 if (netdev->flags & IFF_PROMISC)
1293 value |= MAC_CTRL_PROMIS_EN;
1294 else if (netdev->flags & IFF_ALLMULTI)
1295 value |= MAC_CTRL_MC_ALL_EN;
1296 /* value |= MAC_CTRL_LOOPBACK; */
1297 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1298}
f3cc28c7 1299
05ffdd7b
JC		 1300static u32 atl1_check_link(struct atl1_adapter *adapter)
1301{
1302 struct atl1_hw *hw = &adapter->hw;
1303 struct net_device *netdev = adapter->netdev;
1304 u32 ret_val;
1305 u16 speed, duplex, phy_data;
1306 int reconfig = 0;
f3cc28c7 1307
05ffdd7b
JC		 1308 /* MII_BMSR must read twice */
1309 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1310 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
6446a860
JC		 1311 if (!(phy_data & BMSR_LSTATUS)) {
1312 /* link down */
1313 if (netif_carrier_ok(netdev)) {
1314 /* old link state: Up */
1315 if (netif_msg_link(adapter))
1316 dev_info(&adapter->pdev->dev, "link is down\n");
05ffdd7b
JC		 1317 adapter->link_speed = SPEED_0;
1318 netif_carrier_off(netdev);
f3cc28c7 1319 }
6446a860 1320 return 0;
f3cc28c7
JC		 1321 }
1322
05ffdd7b
JC		 1323 /* Link Up */
1324 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1325 if (ret_val)
1326 return ret_val;
f3cc28c7 1327
05ffdd7b
JC		 1328 switch (hw->media_type) {
1329 case MEDIA_TYPE_1000M_FULL:
1330 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1331 reconfig = 1;
1332 break;
1333 case MEDIA_TYPE_100M_FULL:
1334 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1335 reconfig = 1;
1336 break;
1337 case MEDIA_TYPE_100M_HALF:
1338 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1339 reconfig = 1;
1340 break;
1341 case MEDIA_TYPE_10M_FULL:
1342 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1343 reconfig = 1;
1344 break;
1345 case MEDIA_TYPE_10M_HALF:
1346 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1347 reconfig = 1;
1348 break;
1349 }
f3cc28c7 1350
05ffdd7b
JC		 1351 /* link result is our setting */
1352 if (!reconfig) {
8e95a202
JP		 1353 if (adapter->link_speed != speed ||
1354 adapter->link_duplex != duplex) {
05ffdd7b
JC		 1355 adapter->link_speed = speed;
1356 adapter->link_duplex = duplex;
1357 atl1_setup_mac_ctrl(adapter);
6446a860
JC		 1358 if (netif_msg_link(adapter))
1359 dev_info(&adapter->pdev->dev,
1360 "%s link is up %d Mbps %s\n",
1361 netdev->name, adapter->link_speed,
1362 adapter->link_duplex == FULL_DUPLEX ?
1363 "full duplex" : "half duplex");
05ffdd7b 1364 }
6446a860
JC		 1365 if (!netif_carrier_ok(netdev)) {
1366 /* Link down -> Up */
05ffdd7b 1367 netif_carrier_on(netdev);
05ffdd7b 1368 }
6446a860 1369 return 0;
f3cc28c7 1370 }
f3cc28c7 1371
6446a860 1372 /* change original link status */
05ffdd7b
JC		 1373 if (netif_carrier_ok(netdev)) {
1374 adapter->link_speed = SPEED_0;
1375 netif_carrier_off(netdev);
1376 netif_stop_queue(netdev);
f3cc28c7 1377 }
f3cc28c7 1378
05ffdd7b
JC		 1379 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1380 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1381 switch (hw->media_type) {
1382 case MEDIA_TYPE_100M_FULL:
1383 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1384 MII_CR_RESET;
1385 break;
1386 case MEDIA_TYPE_100M_HALF:
1387 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1388 break;
1389 case MEDIA_TYPE_10M_FULL:
1390 phy_data =
1391 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1392 break;
6446a860
JC		 1393 default:
1394 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 1395 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1396 break;
f3cc28c7 1397 }
05ffdd7b 1398 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
6446a860 1399 return 0;
f3cc28c7 1400 }
f3cc28c7 1401
05ffdd7b
JC		 1402 /* auto-neg, insert timer to re-config phy */
1403 if (!adapter->phy_timer_pending) {
1404 adapter->phy_timer_pending = true;
e053b628
SH		 1405 mod_timer(&adapter->phy_config_timer,
1406 round_jiffies(jiffies + 3 * HZ));
f3cc28c7 1407 }
f3cc28c7 1408
05ffdd7b
JC		 1409 return 0;
1410}
f3cc28c7 1411
05ffdd7b
JC		 1412static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1413{
1414 u32 hi, lo, value;
f3cc28c7 1415
05ffdd7b
JC		 1416 /* RFD Flow Control */
1417 value = adapter->rfd_ring.count;
1418 hi = value / 16;
1419 if (hi < 2)
1420 hi = 2;
1421 lo = value * 7 / 8;
f3cc28c7 1422
05ffdd7b
JC		 1423 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1424 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1425 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
f3cc28c7 1426
05ffdd7b
JC		 1427 /* RRD Flow Control */
1428 value = adapter->rrd_ring.count;
1429 lo = value / 16;
1430 hi = value * 7 / 8;
1431 if (lo < 2)
1432 lo = 2;
1433 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1434 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1435 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1436}
f3cc28c7 1437
05ffdd7b
JC		 1438static void set_flow_ctrl_new(struct atl1_hw *hw)
1439{
1440 u32 hi, lo, value;
1441
1442 /* RXF Flow Control */
1443 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1444 lo = value / 16;
1445 if (lo < 192)
1446 lo = 192;
1447 hi = value * 7 / 8;
1448 if (hi < lo)
1449 hi = lo + 16;
1450 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1451 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1452 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1453
1454 /* RRD Flow Control */
1455 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1456 lo = value / 8;
1457 hi = value * 7 / 8;
1458 if (lo < 2)
1459 lo = 2;
1460 if (hi < lo)
1461 hi = lo + 3;
1462 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1463 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1464 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1465}
1466
1467/*
1468 * atl1_configure - Configure Transmit&Receive Unit after Reset
1469 * @adapter: board private structure
1470 *
1471 * Configure the Tx /Rx unit of the MAC after a reset.
1472 */
1473static u32 atl1_configure(struct atl1_adapter *adapter)
1474{
1475 struct atl1_hw *hw = &adapter->hw;
1476 u32 value;
1477
1478 /* clear interrupt status */
1479 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1480
1481 /* set MAC Address */
1482 value = (((u32) hw->mac_addr[2]) << 24) |
1483 (((u32) hw->mac_addr[3]) << 16) |
1484 (((u32) hw->mac_addr[4]) << 8) |
1485 (((u32) hw->mac_addr[5]));
1486 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1487 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1488 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1489
1490 /* tx / rx ring */
f3cc28c7 1491
05ffdd7b
JC		 1492 /* HI base address */
1493 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1494 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1495 /* LO base address */
1496 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1497 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1498 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1499 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1500 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1501 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1502 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1503 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1504 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1505 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
f3cc28c7 1506
05ffdd7b
JC		 1507 /* element count */
1508 value = adapter->rrd_ring.count;
1509 value <<= 16;
1510 value += adapter->rfd_ring.count;
1511 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1512 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1513 REG_DESC_TPD_RING_SIZE);
f3cc28c7 1514
05ffdd7b
JC		 1515 /* Load Ptr */
1516 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
f3cc28c7 1517
05ffdd7b
JC		 1518 /* config Mailbox */
1519 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1520 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1521 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1522 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1523 ((atomic_read(&adapter->rfd_ring.next_to_use)
1524 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1525 iowrite32(value, hw->hw_addr + REG_MAILBOX);
f3cc28c7 1526
05ffdd7b
JC		 1527 /* config IPG/IFG */
1528 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1529 << MAC_IPG_IFG_IPGT_SHIFT) |
1530 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1531 << MAC_IPG_IFG_MIFG_SHIFT) |
1532 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1533 << MAC_IPG_IFG_IPGR1_SHIFT) |
1534 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1535 << MAC_IPG_IFG_IPGR2_SHIFT);
1536 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
f3cc28c7 1537
05ffdd7b
JC		 1538 /* config Half-Duplex Control */
1539 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1540 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1541 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1542 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1543 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1544 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1545 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1546 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
f3cc28c7 1547
05ffdd7b
JC		 1548 /* set Interrupt Moderator Timer */
1549 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1550 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 1551
05ffdd7b
JC		 1552 /* set Interrupt Clear Timer */
1553 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
f3cc28c7 1554
2a49128f
JC		 1555 /* set max frame size hw will accept */
1556 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
f3cc28c7 1557
05ffdd7b
JC		 1558 /* jumbo size & rrd retirement timer */
1559 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1560 << RXQ_JMBOSZ_TH_SHIFT) |
1561 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1562 << RXQ_JMBO_LKAH_SHIFT) |
1563 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1564 << RXQ_RRD_TIMER_SHIFT);
1565 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
f3cc28c7 1566
05ffdd7b
JC		 1567 /* Flow Control */
1568 switch (hw->dev_rev) {
1569 case 0x8001:
1570 case 0x9001:
1571 case 0x9002:
1572 case 0x9003:
1573 set_flow_ctrl_old(adapter);
1574 break;
1575 default:
1576 set_flow_ctrl_new(hw);
1577 break;
f3cc28c7 1578 }
f3cc28c7 1579
05ffdd7b
JC		 1580 /* config TXQ */
1581 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1582 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1583 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1584 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1585 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1586 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1587 TXQ_CTRL_EN;
1588 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
f3cc28c7 1589
05ffdd7b
JC		 1590 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1591 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1592 << TX_JUMBO_TASK_TH_SHIFT) |
1593 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1594 << TX_TPD_MIN_IPG_SHIFT);
1595 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
f3cc28c7 1596
05ffdd7b
JC		 1597 /* config RXQ */
1598 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1599 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1600 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1601 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1602 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1603 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1604 RXQ_CTRL_EN;
1605 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
f3cc28c7 1606
05ffdd7b
JC		 1607 /* config DMA Engine */
1608 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1609 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
3f516c00
JC		 1610 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1611 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
05ffdd7b
JC		 1612 DMA_CTRL_DMAW_EN;
1613 value |= (u32) hw->dma_ord;
1614 if (atl1_rcb_128 == hw->rcb_value)
1615 value |= DMA_CTRL_RCB_VALUE;
1616 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
f3cc28c7 1617
05ffdd7b 1618 /* config CMB / SMB */
91a500ac
JC		 1619 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1620 hw->cmb_tpd : adapter->tpd_ring.count;
1621 value <<= 16;
1622 value |= hw->cmb_rrd;
05ffdd7b
JC		 1623 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1624 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1625 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1626 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
f3cc28c7 1627
05ffdd7b
JC		 1628 /* --- enable CMB / SMB */
1629 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1630 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
f3cc28c7 1631
05ffdd7b
JC		 1632 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1633 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1634 value = 1; /* config failed */
1635 else
1636 value = 0;
f3cc28c7 1637
05ffdd7b
JC		 1638 /* clear all interrupt status */
1639 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1640 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1641 return value;
f3cc28c7 1642}
f3cc28c7 1643
05ffdd7b
JC		 1644/*
1645 * atl1_pcie_patch - Patch for PCIE module
1646 */
1647static void atl1_pcie_patch(struct atl1_adapter *adapter)
f3cc28c7 1648{
05ffdd7b 1649 u32 value;
f3cc28c7 1650
05ffdd7b
JC		 1651 /* much vendor magic here */
1652 value = 0x6500;
1653 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1654 /* pcie flow control mode change */
1655 value = ioread32(adapter->hw.hw_addr + 0x1008);
1656 value |= 0x8000;
1657 iowrite32(value, adapter->hw.hw_addr + 0x1008);
f3cc28c7 1658}
f3cc28c7 1659
f3cc28c7 1660/*
05ffdd7b
JC		 1661 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1662 * on PCI Command register is disable.
1663 * The function enable this bit.
1664 * Brackett, 2006/03/15
f3cc28c7 1665 */
05ffdd7b 1666static void atl1_via_workaround(struct atl1_adapter *adapter)
f3cc28c7 1667{
05ffdd7b 1668 unsigned long value;
f3cc28c7 1669
05ffdd7b
JC		 1670 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1671 if (value & PCI_COMMAND_INTX_DISABLE)
1672 value &= ~PCI_COMMAND_INTX_DISABLE;
1673 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
f3cc28c7
JC		 1674}
1675
05ffdd7b
JC		 1676static void atl1_inc_smb(struct atl1_adapter *adapter)
1677{
02e71731 1678 struct net_device *netdev = adapter->netdev;
05ffdd7b 1679 struct stats_msg_block *smb = adapter->smb.smb;
f3cc28c7 1680
05ffdd7b
JC		 1681 /* Fill out the OS statistics structure */
1682 adapter->soft_stats.rx_packets += smb->rx_ok;
1683 adapter->soft_stats.tx_packets += smb->tx_ok;
1684 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1685 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1686 adapter->soft_stats.multicast += smb->rx_mcast;
1687 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1688 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
f3cc28c7 1689
05ffdd7b
JC		 1690 /* Rx Errors */
1691 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1692 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1693 smb->rx_rrd_ov + smb->rx_align_err);
1694 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1695 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1696 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1697 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1698 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1699 smb->rx_rxf_ov);
f3cc28c7 1700
05ffdd7b
JC		 1701 adapter->soft_stats.rx_pause += smb->rx_pause;
1702 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1703 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
f3cc28c7 1704
05ffdd7b
JC		 1705 /* Tx Errors */
1706 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1707 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1708 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1709 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1710 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
f3cc28c7 1711
05ffdd7b
JC		 1712 adapter->soft_stats.excecol += smb->tx_abort_col;
1713 adapter->soft_stats.deffer += smb->tx_defer;
1714 adapter->soft_stats.scc += smb->tx_1_col;
1715 adapter->soft_stats.mcc += smb->tx_2_col;
1716 adapter->soft_stats.latecol += smb->tx_late_col;
1717 adapter->soft_stats.tx_underun += smb->tx_underrun;
1718 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1719 adapter->soft_stats.tx_pause += smb->tx_pause;
f3cc28c7 1720
02e71731
SH		 1721 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1722 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1723 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1724 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1725 netdev->stats.multicast = adapter->soft_stats.multicast;
1726 netdev->stats.collisions = adapter->soft_stats.collisions;
1727 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1728 netdev->stats.rx_over_errors =
05ffdd7b 1729 adapter->soft_stats.rx_missed_errors;
02e71731 1730 netdev->stats.rx_length_errors =
05ffdd7b 1731 adapter->soft_stats.rx_length_errors;
02e71731
SH		 1732 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1733 netdev->stats.rx_frame_errors =
05ffdd7b 1734 adapter->soft_stats.rx_frame_errors;
02e71731
SH		 1735 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1736 netdev->stats.rx_missed_errors =
05ffdd7b 1737 adapter->soft_stats.rx_missed_errors;
02e71731
SH		 1738 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1739 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1740 netdev->stats.tx_aborted_errors =
05ffdd7b 1741 adapter->soft_stats.tx_aborted_errors;
02e71731 1742 netdev->stats.tx_window_errors =
05ffdd7b 1743 adapter->soft_stats.tx_window_errors;
02e71731 1744 netdev->stats.tx_carrier_errors =
05ffdd7b 1745 adapter->soft_stats.tx_carrier_errors;
f3cc28c7
JC		 1746}
1747
05ffdd7b 1748static void atl1_update_mailbox(struct atl1_adapter *adapter)
f3cc28c7 1749{
05ffdd7b
JC		 1750 unsigned long flags;
1751 u32 tpd_next_to_use;
1752 u32 rfd_next_to_use;
1753 u32 rrd_next_to_clean;
f3cc28c7 1754 u32 value;
f3cc28c7 1755
05ffdd7b 1756 spin_lock_irqsave(&adapter->mb_lock, flags);
f3cc28c7 1757
05ffdd7b
JC		 1758 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1759 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1760 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
f3cc28c7 1761
05ffdd7b
JC		 1762 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1763 MB_RFD_PROD_INDX_SHIFT) |
1764 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1765 MB_RRD_CONS_INDX_SHIFT) |
1766 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1767 MB_TPD_PROD_INDX_SHIFT);
1768 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
f3cc28c7 1769
05ffdd7b 1770 spin_unlock_irqrestore(&adapter->mb_lock, flags);
f3cc28c7
JC		 1771}
1772
05ffdd7b
JC		 1773static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1774 struct rx_return_desc *rrd, u16 offset)
f3cc28c7 1775{
05ffdd7b 1776 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
f3cc28c7 1777
05ffdd7b
JC		 1778 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1779 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1780 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1781 rfd_ring->next_to_clean = 0;
f3cc28c7 1782 }
f3cc28c7 1783 }
05ffdd7b 1784}
f3cc28c7 1785
05ffdd7b
JC		 1786static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1787 struct rx_return_desc *rrd)
1788{
1789 u16 num_buf;
f3cc28c7 1790
05ffdd7b
JC		 1791 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1792 adapter->rx_buffer_len;
1793 if (rrd->num_buf == num_buf)
1794 /* clean alloc flag for bad rrd */
1795 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1796}
f3cc28c7 1797
05ffdd7b
JC		 1798static void atl1_rx_checksum(struct atl1_adapter *adapter,
1799 struct rx_return_desc *rrd, struct sk_buff *skb)
1800{
1801 struct pci_dev *pdev = adapter->pdev;
f3cc28c7 1802
c2ac3ef3
JC		 1803 /*
1804 * The L1 hardware contains a bug that erroneously sets the
1805 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1806 * fragmented IP packet is received, even though the packet
1807 * is perfectly valid and its checksum is correct. There's
1808 * no way to distinguish between one of these good packets
1809 * and a packet that actually contains a TCP/UDP checksum
1810 * error, so all we can do is allow it to be handed up to
1811 * the higher layers and let it be sorted out there.
1812 */
1813
05ffdd7b 1814 skb->ip_summed = CHECKSUM_NONE;
f3cc28c7 1815
05ffdd7b
JC		 1816 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1817 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1818 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1819 adapter->hw_csum_err++;
6446a860
JC		 1820 if (netif_msg_rx_err(adapter))
1821 dev_printk(KERN_DEBUG, &pdev->dev,
1822 "rx checksum error\n");
05ffdd7b 1823 return;
f3cc28c7 1824 }
f3cc28c7
JC		 1825 }
1826
05ffdd7b
JC		 1827 /* not IPv4 */
1828 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1829 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1830 return;
1831
1832 /* IPv4 packet */
1833 if (likely(!(rrd->err_flg &
1834 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1835 skb->ip_summed = CHECKSUM_UNNECESSARY;
1836 adapter->hw_csum_good++;
1837 return;
f3cc28c7 1838 }
f3cc28c7
JC		 1839}
1840
05ffdd7b
JC		 1841/*
1842 * atl1_alloc_rx_buffers - Replace used receive buffers
1843 * @adapter: address of board private structure
1844 */
1845static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
f3cc28c7 1846{
05ffdd7b
JC		 1847 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1848 struct pci_dev *pdev = adapter->pdev;
1849 struct page *page;
1850 unsigned long offset;
1851 struct atl1_buffer *buffer_info, *next_info;
1852 struct sk_buff *skb;
1853 u16 num_alloc = 0;
1854 u16 rfd_next_to_use, next_next;
1855 struct rx_free_desc *rfd_desc;
f3cc28c7 1856
05ffdd7b
JC		 1857 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1858 if (++next_next == rfd_ring->count)
1859 next_next = 0;
1860 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1861 next_info = &rfd_ring->buffer_info[next_next];
f3cc28c7 1862
05ffdd7b
JC		 1863 while (!buffer_info->alloced && !next_info->alloced) {
1864 if (buffer_info->skb) {
1865 buffer_info->alloced = 1;
1866 goto next;
1867 }
f3cc28c7 1868
05ffdd7b 1869 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
f3cc28c7 1870
89d71a66
ED		 1871 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1872 adapter->rx_buffer_len);
6446a860
JC		 1873 if (unlikely(!skb)) {
1874 /* Better luck next round */
02e71731 1875 adapter->netdev->stats.rx_dropped++;
05ffdd7b
JC		 1876 break;
1877 }
f3cc28c7 1878
05ffdd7b
JC		 1879 buffer_info->alloced = 1;
1880 buffer_info->skb = skb;
1881 buffer_info->length = (u16) adapter->rx_buffer_len;
1882 page = virt_to_page(skb->data);
1883 offset = (unsigned long)skb->data & ~PAGE_MASK;
1884 buffer_info->dma = pci_map_page(pdev, page, offset,
1885 adapter->rx_buffer_len,
1886 PCI_DMA_FROMDEVICE);
1887 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1888 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1889 rfd_desc->coalese = 0;
f3cc28c7 1890
05ffdd7b
JC		 1891next:
1892 rfd_next_to_use = next_next;
1893 if (unlikely(++next_next == rfd_ring->count))
1894 next_next = 0;
f3cc28c7 1895
05ffdd7b
JC		 1896 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1897 next_info = &rfd_ring->buffer_info[next_next];
1898 num_alloc++;
1899 }
f3cc28c7 1900
05ffdd7b
JC		 1901 if (num_alloc) {
1902 /*
1903 * Force memory writes to complete before letting h/w
1904 * know there are new descriptors to fetch. (Only
1905 * applicable for weak-ordered memory model archs,
1906 * such as IA-64).
1907 */
1908 wmb();
1909 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1910 }
1911 return num_alloc;
f3cc28c7
JC		 1912}
1913
05ffdd7b 1914static void atl1_intr_rx(struct atl1_adapter *adapter)
f3cc28c7 1915{
05ffdd7b
JC		 1916 int i, count;
1917 u16 length;
1918 u16 rrd_next_to_clean;
f3cc28c7 1919 u32 value;
05ffdd7b
JC		 1920 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1921 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1922 struct atl1_buffer *buffer_info;
1923 struct rx_return_desc *rrd;
1924 struct sk_buff *skb;
f3cc28c7 1925
05ffdd7b 1926 count = 0;
f3cc28c7 1927
05ffdd7b 1928 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
f3cc28c7 1929
05ffdd7b
JC		 1930 while (1) {
1931 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1932 i = 1;
1933 if (likely(rrd->xsz.valid)) { /* packet valid */
1934chk_rrd:
1935 /* check rrd status */
1936 if (likely(rrd->num_buf == 1))
1937 goto rrd_ok;
6446a860
JC		 1938 else if (netif_msg_rx_err(adapter)) {
1939 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1940 "unexpected RRD buffer count\n");
1941 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1942 "rx_buf_len = %d\n",
1943 adapter->rx_buffer_len);
1944 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1945 "RRD num_buf = %d\n",
1946 rrd->num_buf);
1947 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1948 "RRD pkt_len = %d\n",
1949 rrd->xsz.xsum_sz.pkt_size);
1950 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1951 "RRD pkt_flg = 0x%08X\n",
1952 rrd->pkt_flg);
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "RRD err_flg = 0x%08X\n",
1955 rrd->err_flg);
1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1957 "RRD vlan_tag = 0x%08X\n",
1958 rrd->vlan_tag);
1959 }
f3cc28c7 1960
05ffdd7b
JC		 1961 /* rrd seems to be bad */
1962 if (unlikely(i-- > 0)) {
1963 /* rrd may not be DMAed completely */
05ffdd7b
JC		 1964 udelay(1);
1965 goto chk_rrd;
1966 }
1967 /* bad rrd */
6446a860
JC		 1968 if (netif_msg_rx_err(adapter))
1969 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1970 "bad RRD\n");
05ffdd7b
JC		 1971 /* see if update RFD index */
1972 if (rrd->num_buf > 1)
1973 atl1_update_rfd_index(adapter, rrd);
f3cc28c7 1974
05ffdd7b
JC		 1975 /* update rrd */
1976 rrd->xsz.valid = 0;
1977 if (++rrd_next_to_clean == rrd_ring->count)
1978 rrd_next_to_clean = 0;
1979 count++;
1980 continue;
1981 } else { /* current rrd still not be updated */
f3cc28c7 1982
05ffdd7b
JC		 1983 break;
1984 }
1985rrd_ok:
1986 /* clean alloc flag for bad rrd */
1987 atl1_clean_alloc_flag(adapter, rrd, 0);
f3cc28c7 1988
05ffdd7b
JC		 1989 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1990 if (++rfd_ring->next_to_clean == rfd_ring->count)
1991 rfd_ring->next_to_clean = 0;
f3cc28c7 1992
05ffdd7b
JC		 1993 /* update rrd next to clean */
1994 if (++rrd_next_to_clean == rrd_ring->count)
1995 rrd_next_to_clean = 0;
1996 count++;
f3cc28c7 1997
05ffdd7b
JC		 1998 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1999 if (!(rrd->err_flg &
2000 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2001 | ERR_FLAG_LEN))) {
2002 /* packet error, don't need upstream */
2003 buffer_info->alloced = 0;
2004 rrd->xsz.valid = 0;
2005 continue;
2006 }
2007 }
f3cc28c7 2008
05ffdd7b
JC		 2009 /* Good Receive */
2010 pci_unmap_page(adapter->pdev, buffer_info->dma,
2011 buffer_info->length, PCI_DMA_FROMDEVICE);
aefdbf1a 2012 buffer_info->dma = 0;
05ffdd7b
JC		 2013 skb = buffer_info->skb;
2014 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
f3cc28c7 2015
a3093d9b 2016 skb_put(skb, length - ETH_FCS_LEN);
f3cc28c7 2017
05ffdd7b
JC		 2018 /* Receive Checksum Offload */
2019 atl1_rx_checksum(adapter, rrd, skb);
2020 skb->protocol = eth_type_trans(skb, adapter->netdev);
f3cc28c7 2021
05ffdd7b
JC		 2022 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2023 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2024 ((rrd->vlan_tag & 7) << 13) |
2025 ((rrd->vlan_tag & 8) << 9);
2026 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2027 } else
2028 netif_rx(skb);
f3cc28c7 2029
05ffdd7b
JC		 2030 /* let protocol layer free skb */
2031 buffer_info->skb = NULL;
2032 buffer_info->alloced = 0;
2033 rrd->xsz.valid = 0;
05ffdd7b 2034 }
f3cc28c7 2035
05ffdd7b 2036 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
f3cc28c7 2037
05ffdd7b 2038 atl1_alloc_rx_buffers(adapter);
f3cc28c7 2039
05ffdd7b
JC		 2040 /* update mailbox ? */
2041 if (count) {
2042 u32 tpd_next_to_use;
2043 u32 rfd_next_to_use;
f3cc28c7 2044
05ffdd7b 2045 spin_lock(&adapter->mb_lock);
f3cc28c7 2046
05ffdd7b
JC		 2047 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2048 rfd_next_to_use =
2049 atomic_read(&adapter->rfd_ring.next_to_use);
2050 rrd_next_to_clean =
2051 atomic_read(&adapter->rrd_ring.next_to_clean);
2052 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2053 MB_RFD_PROD_INDX_SHIFT) |
2054 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2055 MB_RRD_CONS_INDX_SHIFT) |
2056 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2057 MB_TPD_PROD_INDX_SHIFT);
2058 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2059 spin_unlock(&adapter->mb_lock);
2060 }
f3cc28c7
JC		 2061}
2062
05ffdd7b 2063static void atl1_intr_tx(struct atl1_adapter *adapter)
f3cc28c7 2064{
05ffdd7b
JC		 2065 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2066 struct atl1_buffer *buffer_info;
2067 u16 sw_tpd_next_to_clean;
2068 u16 cmb_tpd_next_to_clean;
f3cc28c7 2069
05ffdd7b
JC		 2070 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2071 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
f3cc28c7 2072
05ffdd7b
JC		 2073 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2074 struct tx_packet_desc *tpd;
f3cc28c7 2075
05ffdd7b
JC		 2076 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2077 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2078 if (buffer_info->dma) {
2079 pci_unmap_page(adapter->pdev, buffer_info->dma,
2080 buffer_info->length, PCI_DMA_TODEVICE);
2081 buffer_info->dma = 0;
2082 }
f3cc28c7 2083
05ffdd7b
JC		 2084 if (buffer_info->skb) {
2085 dev_kfree_skb_irq(buffer_info->skb);
2086 buffer_info->skb = NULL;
2087 }
f3cc28c7 2088
05ffdd7b
JC		 2089 if (++sw_tpd_next_to_clean == tpd_ring->count)
2090 sw_tpd_next_to_clean = 0;
2091 }
2092 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2093
8e95a202
JP		 2094 if (netif_queue_stopped(adapter->netdev) &&
2095 netif_carrier_ok(adapter->netdev))
05ffdd7b 2096 netif_wake_queue(adapter->netdev);
f3cc28c7
JC		 2097}
2098
e6a7ff4a 2099static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
f3cc28c7
JC		 2100{
2101 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2102 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
53ffb42c
JC		 2103 return ((next_to_clean > next_to_use) ?
2104 next_to_clean - next_to_use - 1 :
2105 tpd_ring->count + next_to_clean - next_to_use - 1);
f3cc28c7
JC		 2106}
2107
2108static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2109 struct tx_packet_desc *ptpd)
f3cc28c7 2110{
6446a860
JC		 2111 u8 hdr_len, ip_off;
2112 u32 real_len;
f3cc28c7
JC		 2113 int err;
2114
2115 if (skb_shinfo(skb)->gso_size) {
2116 if (skb_header_cloned(skb)) {
2117 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2118 if (unlikely(err))
6446a860 2119 return -1;
f3cc28c7
JC		 2120 }
2121
d63ddcec 2122 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2123 struct iphdr *iph = ip_hdr(skb);
2124
6446a860
JC		 2125 real_len = (((unsigned char *)iph - skb->data) +
2126 ntohs(iph->tot_len));
2127 if (real_len < skb->len)
2128 pskb_trim(skb, real_len);
2129 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2130 if (skb->len == hdr_len) {
2131 iph->check = 0;
2132 tcp_hdr(skb)->check =
2133 ~csum_tcpudp_magic(iph->saddr,
2134 iph->daddr, tcp_hdrlen(skb),
2135 IPPROTO_TCP, 0);
2136 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2137 TPD_IPHL_SHIFT;
2138 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2139 TPD_TCPHDRLEN_MASK) <<
2140 TPD_TCPHDRLEN_SHIFT;
2141 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2142 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2143 return 1;
2144 }
2145
eddc9ec5 2146 iph->check = 0;
aa8223c7 2147 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6446a860
JC		 2148 iph->daddr, 0, IPPROTO_TCP, 0);
2149 ip_off = (unsigned char *)iph -
2150 (unsigned char *) skb_network_header(skb);
2151 if (ip_off == 8) /* 802.3-SNAP frame */
2152 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2153 else if (ip_off != 0)
2154 return -2;
2155
2156 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2157 TPD_IPHL_SHIFT;
2158 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2159 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2160 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2161 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2162 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2163 return 3;
f3cc28c7
JC		 2164 }
2165 }
2166 return false;
2167}
2168
2169static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2170 struct tx_packet_desc *ptpd)
f3cc28c7
JC		 2171{
2172 u8 css, cso;
2173
2174 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
6446a860
JC		 2175 css = (u8) (skb->csum_start - skb_headroom(skb));
2176 cso = css + (u8) skb->csum_offset;
2177 if (unlikely(css & 0x1)) {
2178 /* L1 hardware requires an even number here */
2179 if (netif_msg_tx_err(adapter))
2180 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2181 "payload offset not an even number\n");
f3cc28c7
JC		 2182 return -1;
2183 }
6446a860
JC		 2184 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2185 TPD_PLOADOFFSET_SHIFT;
2186 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2187 TPD_CCSUMOFFSET_SHIFT;
2188 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
f3cc28c7
JC		 2189 return true;
2190 }
6446a860 2191 return 0;
f3cc28c7
JC		 2192}
2193
53ffb42c 2194static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2195 struct tx_packet_desc *ptpd)
f3cc28c7 2196{
f3cc28c7
JC		 2197 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2198 struct atl1_buffer *buffer_info;
6446a860 2199 u16 buf_len = skb->len;
f3cc28c7 2200 struct page *page;
f3cc28c7
JC		 2201 unsigned long offset;
2202 unsigned int nr_frags;
2203 unsigned int f;
6446a860
JC		 2204 int retval;
2205 u16 next_to_use;
2206 u16 data_len;
2207 u8 hdr_len;
f3cc28c7 2208
6446a860 2209 buf_len -= skb->data_len;
f3cc28c7 2210 nr_frags = skb_shinfo(skb)->nr_frags;
6446a860
JC		 2211 next_to_use = atomic_read(&tpd_ring->next_to_use);
2212 buffer_info = &tpd_ring->buffer_info[next_to_use];
0ee904c3 2213 BUG_ON(buffer_info->skb);
6446a860
JC		 2214 /* put skb in last TPD */
2215 buffer_info->skb = NULL;
f3cc28c7 2216
6446a860
JC		 2217 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2218 if (retval) {
2219 /* TSO */
2220 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2221 buffer_info->length = hdr_len;
f3cc28c7
JC		 2222 page = virt_to_page(skb->data);
2223 offset = (unsigned long)skb->data & ~PAGE_MASK;
2224 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860 2225 offset, hdr_len,
f3cc28c7
JC		 2226 PCI_DMA_TODEVICE);
2227
6446a860
JC		 2228 if (++next_to_use == tpd_ring->count)
2229 next_to_use = 0;
f3cc28c7 2230
6446a860
JC		 2231 if (buf_len > hdr_len) {
2232 int i, nseg;
ddfce6bb 2233
6446a860
JC		 2234 data_len = buf_len - hdr_len;
2235 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
53ffb42c 2236 ATL1_MAX_TX_BUF_LEN;
6446a860 2237 for (i = 0; i < nseg; i++) {
f3cc28c7 2238 buffer_info =
6446a860 2239 &tpd_ring->buffer_info[next_to_use];
f3cc28c7
JC		 2240 buffer_info->skb = NULL;
2241 buffer_info->length =
2b116145 2242 (ATL1_MAX_TX_BUF_LEN >=
6446a860
JC		 2243 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2244 data_len -= buffer_info->length;
f3cc28c7 2245 page = virt_to_page(skb->data +
6446a860 2246 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
f3cc28c7 2247 offset = (unsigned long)(skb->data +
6446a860
JC		 2248 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2249 ~PAGE_MASK;
53ffb42c
JC		 2250 buffer_info->dma = pci_map_page(adapter->pdev,
2251 page, offset, buffer_info->length,
2252 PCI_DMA_TODEVICE);
6446a860
JC		 2253 if (++next_to_use == tpd_ring->count)
2254 next_to_use = 0;
f3cc28c7
JC		 2255 }
2256 }
2257 } else {
6446a860
JC		 2258 /* not TSO */
2259 buffer_info->length = buf_len;
f3cc28c7
JC		 2260 page = virt_to_page(skb->data);
2261 offset = (unsigned long)skb->data & ~PAGE_MASK;
2262 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860
JC		 2263 offset, buf_len, PCI_DMA_TODEVICE);
2264 if (++next_to_use == tpd_ring->count)
2265 next_to_use = 0;
f3cc28c7
JC		 2266 }
2267
2268 for (f = 0; f < nr_frags; f++) {
2269 struct skb_frag_struct *frag;
6446a860 2270 u16 i, nseg;
f3cc28c7
JC		 2271
2272 frag = &skb_shinfo(skb)->frags[f];
6446a860 2273 buf_len = frag->size;
f3cc28c7 2274
6446a860
JC		 2275 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2276 ATL1_MAX_TX_BUF_LEN;
2277 for (i = 0; i < nseg; i++) {
2278 buffer_info = &tpd_ring->buffer_info[next_to_use];
0ee904c3
AB		 2279 BUG_ON(buffer_info->skb);
2280
f3cc28c7 2281 buffer_info->skb = NULL;
6446a860
JC		 2282 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2283 ATL1_MAX_TX_BUF_LEN : buf_len;
2284 buf_len -= buffer_info->length;
53ffb42c
JC		 2285 buffer_info->dma = pci_map_page(adapter->pdev,
2286 frag->page,
2287 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2288 buffer_info->length, PCI_DMA_TODEVICE);
f3cc28c7 2289
6446a860
JC		 2290 if (++next_to_use == tpd_ring->count)
2291 next_to_use = 0;
f3cc28c7
JC		 2292 }
2293 }
2294
2295 /* last tpd's buffer-info */
2296 buffer_info->skb = skb;
2297}
2298
6446a860
JC		 2299static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2300 struct tx_packet_desc *ptpd)
f3cc28c7 2301{
f3cc28c7 2302 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
f3cc28c7
JC		 2303 struct atl1_buffer *buffer_info;
2304 struct tx_packet_desc *tpd;
6446a860
JC		 2305 u16 j;
2306 u32 val;
2307 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
f3cc28c7
JC		 2308
2309 for (j = 0; j < count; j++) {
6446a860
JC		 2310 buffer_info = &tpd_ring->buffer_info[next_to_use];
2311 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2312 if (tpd != ptpd)
2313 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
f3cc28c7 2314 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
dc5596d9
JC		 2315 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2316 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
6446a860 2317 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
f3cc28c7 2318
6446a860
JC		 2319 /*
2320 * if this is the first packet in a TSO chain, set
2321 * TPD_HDRFLAG, otherwise, clear it.
2322 */
2323 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2324 TPD_SEGMENT_EN_MASK;
2325 if (val) {
2326 if (!j)
2327 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2328 else
2329 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2330 }
f3cc28c7
JC		 2331
2332 if (j == (count - 1))
6446a860 2333 tpd->word3 |= 1 << TPD_EOP_SHIFT;
f3cc28c7 2334
6446a860
JC		 2335 if (++next_to_use == tpd_ring->count)
2336 next_to_use = 0;
f3cc28c7
JC		 2337 }
2338 /*
2339 * Force memory writes to complete before letting h/w
2340 * know there are new descriptors to fetch. (Only
2341 * applicable for weak-ordered memory model archs,
2342 * such as IA-64).
2343 */
2344 wmb();
2345
6446a860 2346 atomic_set(&tpd_ring->next_to_use, next_to_use);
f3cc28c7
JC		 2347}
2348
61357325
SH		 2349static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2350 struct net_device *netdev)
f3cc28c7
JC		 2351{
2352 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2353 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
e743d313 2354 int len;
f3cc28c7
JC		 2355 int tso;
2356 int count = 1;
2357 int ret_val;
6446a860 2358 struct tx_packet_desc *ptpd;
f3cc28c7
JC		 2359 u16 frag_size;
2360 u16 vlan_tag;
f3cc28c7
JC		 2361 unsigned int nr_frags = 0;
2362 unsigned int mss = 0;
2363 unsigned int f;
2364 unsigned int proto_hdr_len;
2365
e743d313 2366 len = skb_headlen(skb);
f3cc28c7 2367
6446a860 2368 if (unlikely(skb->len <= 0)) {
f3cc28c7
JC		 2369 dev_kfree_skb_any(skb);
2370 return NETDEV_TX_OK;
2371 }
2372
f3cc28c7
JC		 2373 nr_frags = skb_shinfo(skb)->nr_frags;
2374 for (f = 0; f < nr_frags; f++) {
2375 frag_size = skb_shinfo(skb)->frags[f].size;
2376 if (frag_size)
53ffb42c
JC		 2377 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2378 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2379 }
2380
f3cc28c7
JC		 2381 mss = skb_shinfo(skb)->gso_size;
2382 if (mss) {
17d0cdfa 2383 if (skb->protocol == htons(ETH_P_IP)) {
ea2ae17d 2384 proto_hdr_len = (skb_transport_offset(skb) +
ab6a5bb6 2385 tcp_hdrlen(skb));
f3cc28c7
JC		 2386 if (unlikely(proto_hdr_len > len)) {
2387 dev_kfree_skb_any(skb);
2388 return NETDEV_TX_OK;
2389 }
2390 /* need additional TPD ? */
2391 if (proto_hdr_len != len)
2392 count += (len - proto_hdr_len +
53ffb42c
JC		 2393 ATL1_MAX_TX_BUF_LEN - 1) /
2394 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2395 }
2396 }
2397
e6a7ff4a 2398 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
f3cc28c7
JC		 2399 /* not enough descriptors */
2400 netif_stop_queue(netdev);
6446a860
JC		 2401 if (netif_msg_tx_queued(adapter))
2402 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2403 "tx busy\n");
f3cc28c7
JC		 2404 return NETDEV_TX_BUSY;
2405 }
2406
6446a860
JC		 2407 ptpd = ATL1_TPD_DESC(tpd_ring,
2408 (u16) atomic_read(&tpd_ring->next_to_use));
2409 memset(ptpd, 0, sizeof(struct tx_packet_desc));
f3cc28c7
JC		 2410
2411 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2412 vlan_tag = vlan_tx_tag_get(skb);
2413 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2414 ((vlan_tag >> 9) & 0x8);
6446a860 2415 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
dc5596d9
JC		 2416 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2417 TPD_VLANTAG_SHIFT;
f3cc28c7
JC		 2418 }
2419
6446a860 2420 tso = atl1_tso(adapter, skb, ptpd);
f3cc28c7 2421 if (tso < 0) {
f3cc28c7
JC		 2422 dev_kfree_skb_any(skb);
2423 return NETDEV_TX_OK;
2424 }
2425
2426 if (!tso) {
6446a860 2427 ret_val = atl1_tx_csum(adapter, skb, ptpd);
f3cc28c7 2428 if (ret_val < 0) {
f3cc28c7
JC		 2429 dev_kfree_skb_any(skb);
2430 return NETDEV_TX_OK;
2431 }
2432 }
2433
6446a860
JC		 2434 atl1_tx_map(adapter, skb, ptpd);
2435 atl1_tx_queue(adapter, count, ptpd);
f3cc28c7 2436 atl1_update_mailbox(adapter);
e1098328 2437 mmiowb();
f3cc28c7
JC		 2438 return NETDEV_TX_OK;
2439}
2440
2441/*
05ffdd7b
JC		 2442 * atl1_intr - Interrupt Handler
2443 * @irq: interrupt number
2444 * @data: pointer to a network interface device structure
2445 * @pt_regs: CPU registers structure
f3cc28c7 2446 */
05ffdd7b 2447static irqreturn_t atl1_intr(int irq, void *data)
f3cc28c7 2448{
05ffdd7b
JC		 2449 struct atl1_adapter *adapter = netdev_priv(data);
2450 u32 status;
05ffdd7b 2451 int max_ints = 10;
f3cc28c7 2452
05ffdd7b
JC		 2453 status = adapter->cmb.cmb->int_stats;
2454 if (!status)
2455 return IRQ_NONE;
f3cc28c7 2456
05ffdd7b
JC		 2457 do {
2458 /* clear CMB interrupt status at once */
2459 adapter->cmb.cmb->int_stats = 0;
2460
2461 if (status & ISR_GPHY) /* clear phy status */
6446a860 2462 atlx_clear_phy_int(adapter);
05ffdd7b
JC		 2463
2464 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2465 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2466
2467 /* check if SMB intr */
2468 if (status & ISR_SMB)
2469 atl1_inc_smb(adapter);
2470
2471 /* check if PCIE PHY Link down */
2472 if (status & ISR_PHY_LINKDOWN) {
6446a860
JC		 2473 if (netif_msg_intr(adapter))
2474 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2475 "pcie phy link down %x\n", status);
05ffdd7b
JC		 2476 if (netif_running(adapter->netdev)) { /* reset MAC */
2477 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2478 schedule_work(&adapter->pcie_dma_to_rst_task);
2479 return IRQ_HANDLED;
2480 }
f3cc28c7 2481 }
05ffdd7b
JC		 2482
2483 /* check if DMA read/write error ? */
2484 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
6446a860
JC		 2485 if (netif_msg_intr(adapter))
2486 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2487 "pcie DMA r/w error (status = 0x%x)\n",
2488 status);
05ffdd7b
JC		 2489 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2490 schedule_work(&adapter->pcie_dma_to_rst_task);
2491 return IRQ_HANDLED;
f3cc28c7 2492 }
f3cc28c7 2493
05ffdd7b
JC		 2494 /* link event */
2495 if (status & ISR_GPHY) {
2496 adapter->soft_stats.tx_carrier_errors++;
2497 atl1_check_for_link(adapter);
2498 }
f3cc28c7 2499
05ffdd7b
JC		 2500 /* transmit event */
2501 if (status & ISR_CMB_TX)
2502 atl1_intr_tx(adapter);
f3cc28c7 2503
05ffdd7b
JC		 2504 /* rx exception */
2505 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2506 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2507 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2508 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2509 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2510 ISR_HOST_RRD_OV))
6446a860
JC		 2511 if (netif_msg_intr(adapter))
2512 dev_printk(KERN_DEBUG,
2513 &adapter->pdev->dev,
2514 "rx exception, ISR = 0x%x\n",
2515 status);
05ffdd7b
JC		 2516 atl1_intr_rx(adapter);
2517 }
f3cc28c7 2518
05ffdd7b
JC		 2519 if (--max_ints < 0)
2520 break;
2521
2522 } while ((status = adapter->cmb.cmb->int_stats));
2523
2524 /* re-enable Interrupt */
2525 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2526 return IRQ_HANDLED;
f3cc28c7
JC		 2527}
2528
f3cc28c7 2529
05ffdd7b
JC		 2530/*
2531 * atl1_phy_config - Timer Call-back
2532 * @data: pointer to netdev cast into an unsigned long
2533 */
2534static void atl1_phy_config(unsigned long data)
2535{
6446a860
JC		 2536 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2537 struct atl1_hw *hw = &adapter->hw;
05ffdd7b 2538 unsigned long flags;
f3cc28c7 2539
05ffdd7b 2540 spin_lock_irqsave(&adapter->lock, flags);
6446a860
JC		 2541 adapter->phy_timer_pending = false;
2542 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2543 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2544 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
05ffdd7b
JC		 2545 spin_unlock_irqrestore(&adapter->lock, flags);
2546}
2547
6446a860
JC		 2548/*
2549 * Orphaned vendor comment left intact here:
2550 * <vendor comment>
2551 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2552 * will assert. We do soft reset <0x1400=1> according
2553 * with the SPEC. BUT, it seemes that PCIE or DMA
2554 * state-machine will not be reset. DMAR_TO_INT will
2555 * assert again and again.
2556 * </vendor comment>
2557 */
05ffdd7b 2558
6446a860 2559static int atl1_reset(struct atl1_adapter *adapter)
05ffdd7b
JC		 2560{
2561 int ret;
05ffdd7b 2562 ret = atl1_reset_hw(&adapter->hw);
6446a860 2563 if (ret)
05ffdd7b
JC		 2564 return ret;
2565 return atl1_init_hw(&adapter->hw);
f3cc28c7
JC		 2566}
2567
6446a860 2568static s32 atl1_up(struct atl1_adapter *adapter)
f3cc28c7
JC		 2569{
2570 struct net_device *netdev = adapter->netdev;
2571 int err;
2572 int irq_flags = IRQF_SAMPLE_RANDOM;
2573
2574 /* hardware has been reset, we need to reload some things */
6446a860 2575 atlx_set_multi(netdev);
2ca13da7 2576 atl1_init_ring_ptrs(adapter);
6446a860 2577 atlx_restore_vlan(adapter);
f3cc28c7 2578 err = atl1_alloc_rx_buffers(adapter);
6446a860
JC		 2579 if (unlikely(!err))
2580 /* no RX BUFFER allocated */
f3cc28c7
JC		 2581 return -ENOMEM;
2582
2583 if (unlikely(atl1_configure(adapter))) {
2584 err = -EIO;
2585 goto err_up;
2586 }
2587
2588 err = pci_enable_msi(adapter->pdev);
2589 if (err) {
6446a860
JC		 2590 if (netif_msg_ifup(adapter))
2591 dev_info(&adapter->pdev->dev,
2592 "Unable to enable MSI: %d\n", err);
f3cc28c7
JC		 2593 irq_flags |= IRQF_SHARED;
2594 }
2595
a0607fd3 2596 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
f3cc28c7
JC		 2597 netdev->name, netdev);
2598 if (unlikely(err))
2599 goto err_up;
2600
6446a860 2601 atlx_irq_enable(adapter);
f3cc28c7 2602 atl1_check_link(adapter);
39d48157 2603 netif_start_queue(netdev);
f3cc28c7
JC		 2604 return 0;
2605
f3cc28c7
JC		 2606err_up:
2607 pci_disable_msi(adapter->pdev);
2608 /* free rx_buffers */
2609 atl1_clean_rx_ring(adapter);
2610 return err;
2611}
2612
6446a860 2613static void atl1_down(struct atl1_adapter *adapter)
f3cc28c7
JC		 2614{
2615 struct net_device *netdev = adapter->netdev;
2616
b29be6d3 2617 netif_stop_queue(netdev);
f3cc28c7
JC		 2618 del_timer_sync(&adapter->phy_config_timer);
2619 adapter->phy_timer_pending = false;
2620
6446a860 2621 atlx_irq_disable(adapter);
f3cc28c7
JC		 2622 free_irq(adapter->pdev->irq, netdev);
2623 pci_disable_msi(adapter->pdev);
2624 atl1_reset_hw(&adapter->hw);
2625 adapter->cmb.cmb->int_stats = 0;
2626
2627 adapter->link_speed = SPEED_0;
2628 adapter->link_duplex = -1;
2629 netif_carrier_off(netdev);
f3cc28c7 2630
f3cc28c7
JC		 2631 atl1_clean_tx_ring(adapter);
2632 atl1_clean_rx_ring(adapter);
f3cc28c7
JC		 2633}
2634
6446a860
JC		 2635static void atl1_tx_timeout_task(struct work_struct *work)
2636{
2637 struct atl1_adapter *adapter =
2638 container_of(work, struct atl1_adapter, tx_timeout_task);
2639 struct net_device *netdev = adapter->netdev;
2640
2641 netif_device_detach(netdev);
2642 atl1_down(adapter);
305282ba 2643 atl1_up(adapter);
6446a860 2644 netif_device_attach(netdev);
305282ba
JC		 2645}
2646
6446a860
JC		 2647/*
2648 * atl1_change_mtu - Change the Maximum Transfer Unit
2649 * @netdev: network interface device structure
2650 * @new_mtu: new value for maximum frame size
2651 *
2652 * Returns 0 on success, negative on failure
2653 */
2654static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
305282ba
JC		 2655{
2656 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860
JC		 2657 int old_mtu = netdev->mtu;
2658 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
305282ba 2659
6446a860
JC		 2660 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2661 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2662 if (netif_msg_link(adapter))
2663 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2664 return -EINVAL;
305282ba 2665 }
6446a860
JC		 2666
2667 adapter->hw.max_frame_size = max_frame;
2668 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2669 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2670 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2671
2672 netdev->mtu = new_mtu;
2673 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2674 atl1_down(adapter);
2675 atl1_up(adapter);
2676 }
2677
2678 return 0;
305282ba
JC		 2679}
2680
f3cc28c7
JC		 2681/*
2682 * atl1_open - Called when a network interface is made active
2683 * @netdev: network interface device structure
2684 *
2685 * Returns 0 on success, negative value on failure
2686 *
2687 * The open entry point is called when a network interface is made
2688 * active by the system (IFF_UP). At this point all resources needed
2689 * for transmit and receive operations are allocated, the interrupt
2690 * handler is registered with the OS, the watchdog timer is started,
2691 * and the stack is notified that the interface is ready.
2692 */
2693static int atl1_open(struct net_device *netdev)
2694{
2695 struct atl1_adapter *adapter = netdev_priv(netdev);
2696 int err;
2697
b29be6d3
JC		 2698 netif_carrier_off(netdev);
2699
f3cc28c7
JC		 2700 /* allocate transmit descriptors */
2701 err = atl1_setup_ring_resources(adapter);
2702 if (err)
2703 return err;
2704
2705 err = atl1_up(adapter);
2706 if (err)
2707 goto err_up;
2708
2709 return 0;
2710
2711err_up:
2712 atl1_reset(adapter);
2713 return err;
2714}
2715
2716/*
2717 * atl1_close - Disables a network interface
2718 * @netdev: network interface device structure
2719 *
2720 * Returns 0, this is not allowed to fail
2721 *
2722 * The close entry point is called when an interface is de-activated
2723 * by the OS. The hardware is still under the drivers control, but
2724 * needs to be disabled. A global MAC reset is issued to stop the
2725 * hardware, and all transmit and receive resources are freed.
2726 */
2727static int atl1_close(struct net_device *netdev)
2728{
2729 struct atl1_adapter *adapter = netdev_priv(netdev);
2730 atl1_down(adapter);
2731 atl1_free_ring_resources(adapter);
2732 return 0;
2733}
2734
05ffdd7b
JC		 2735#ifdef CONFIG_PM
2736static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
f3cc28c7 2737{
05ffdd7b
JC		 2738 struct net_device *netdev = pci_get_drvdata(pdev);
2739 struct atl1_adapter *adapter = netdev_priv(netdev);
2740 struct atl1_hw *hw = &adapter->hw;
2741 u32 ctrl = 0;
2742 u32 wufc = adapter->wol;
08e0f1dc
JC		 2743 u32 val;
2744 int retval;
2745 u16 speed;
2746 u16 duplex;
f3cc28c7
JC		 2747
2748 netif_device_detach(netdev);
05ffdd7b
JC		 2749 if (netif_running(netdev))
2750 atl1_down(adapter);
f3cc28c7 2751
08e0f1dc
JC		 2752 retval = pci_save_state(pdev);
2753 if (retval)
2754 return retval;
2755
05ffdd7b
JC		 2756 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2757 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
08e0f1dc
JC		 2758 val = ctrl & BMSR_LSTATUS;
2759 if (val)
6446a860 2760 wufc &= ~ATLX_WUFC_LNKC;
f3cc28c7 2761
08e0f1dc
JC		 2762 if (val && wufc) {
2763 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2764 if (val) {
2765 if (netif_msg_ifdown(adapter))
2766 dev_printk(KERN_DEBUG, &pdev->dev,
2767 "error getting speed/duplex\n");
2768 goto disable_wol;
2769 }
05ffdd7b
JC		 2770
2771 ctrl = 0;
05ffdd7b 2772
08e0f1dc
JC		 2773 /* enable magic packet WOL */
2774 if (wufc & ATLX_WUFC_MAG)
2775 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
05ffdd7b 2776 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
08e0f1dc
JC		 2777 ioread32(hw->hw_addr + REG_WOL_CTRL);
2778
2779 /* configure the mac */
2780 ctrl = MAC_CTRL_RX_EN;
2781 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2782 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2783 if (duplex == FULL_DUPLEX)
2784 ctrl |= MAC_CTRL_DUPLX;
2785 ctrl |= (((u32)adapter->hw.preamble_len &
2786 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2787 if (adapter->vlgrp)
2788 ctrl |= MAC_CTRL_RMV_VLAN;
2789 if (wufc & ATLX_WUFC_MAG)
05ffdd7b 2790 ctrl |= MAC_CTRL_BC_EN;
05ffdd7b 2791 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
08e0f1dc
JC		 2792 ioread32(hw->hw_addr + REG_MAC_CTRL);
2793
2794 /* poke the PHY */
2795 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2796 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2797 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2798 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2799
2800 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2801 goto exit;
05ffdd7b
JC		 2802 }
2803
08e0f1dc
JC		 2804 if (!val && wufc) {
2805 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2806 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2807 ioread32(hw->hw_addr + REG_WOL_CTRL);
2808 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2809 ioread32(hw->hw_addr + REG_MAC_CTRL);
2810 hw->phy_configured = false;
2811 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2812 goto exit;
2813 }
05ffdd7b 2814
08e0f1dc
JC		 2815disable_wol:
2816 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2817 ioread32(hw->hw_addr + REG_WOL_CTRL);
2818 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2819 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2820 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2821 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
08e0f1dc
JC		 2822 hw->phy_configured = false;
2823 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2824exit:
2825 if (netif_running(netdev))
2826 pci_disable_msi(adapter->pdev);
2827 pci_disable_device(pdev);
2828 pci_set_power_state(pdev, pci_choose_state(pdev, state));
05ffdd7b
JC		 2829
2830 return 0;
f3cc28c7
JC		 2831}
2832
05ffdd7b 2833static int atl1_resume(struct pci_dev *pdev)
f3cc28c7 2834{
05ffdd7b
JC		 2835 struct net_device *netdev = pci_get_drvdata(pdev);
2836 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2837 u32 err;
53ffb42c 2838
6446a860 2839 pci_set_power_state(pdev, PCI_D0);
05ffdd7b
JC		 2840 pci_restore_state(pdev);
2841
6446a860 2842 err = pci_enable_device(pdev);
08e0f1dc
JC		 2843 if (err) {
2844 if (netif_msg_ifup(adapter))
2845 dev_printk(KERN_DEBUG, &pdev->dev,
2846 "error enabling pci device\n");
2847 return err;
2848 }
2849
2850 pci_set_master(pdev);
2851 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
05ffdd7b
JC		 2852 pci_enable_wake(pdev, PCI_D3hot, 0);
2853 pci_enable_wake(pdev, PCI_D3cold, 0);
2854
08e0f1dc 2855 atl1_reset_hw(&adapter->hw);
05ffdd7b 2856
ec5a32f6
LT		 2857 if (netif_running(netdev)) {
2858 adapter->cmb.cmb->int_stats = 0;
05ffdd7b 2859 atl1_up(adapter);
ec5a32f6 2860 }
05ffdd7b 2861 netif_device_attach(netdev);
05ffdd7b
JC		 2862
2863 return 0;
f3cc28c7 2864}
05ffdd7b
JC		 2865#else
2866#define atl1_suspend NULL
2867#define atl1_resume NULL
2868#endif
f3cc28c7 2869
bf455a22
JC		 2870static void atl1_shutdown(struct pci_dev *pdev)
2871{
2872#ifdef CONFIG_PM
2873 atl1_suspend(pdev, PMSG_SUSPEND);
2874#endif
2875}
2876
05ffdd7b
JC		 2877#ifdef CONFIG_NET_POLL_CONTROLLER
2878static void atl1_poll_controller(struct net_device *netdev)
f3cc28c7 2879{
05ffdd7b
JC		 2880 disable_irq(netdev->irq);
2881 atl1_intr(netdev->irq, netdev);
2882 enable_irq(netdev->irq);
f3cc28c7 2883}
05ffdd7b 2884#endif
f3cc28c7 2885
825a84d1
SH		 2886static const struct net_device_ops atl1_netdev_ops = {
2887 .ndo_open = atl1_open,
2888 .ndo_stop = atl1_close,
00829823 2889 .ndo_start_xmit = atl1_xmit_frame,
825a84d1
SH		 2890 .ndo_set_multicast_list = atlx_set_multi,
2891 .ndo_validate_addr = eth_validate_addr,
2892 .ndo_set_mac_address = atl1_set_mac,
2893 .ndo_change_mtu = atl1_change_mtu,
2894 .ndo_do_ioctl = atlx_ioctl,
00829823 2895 .ndo_tx_timeout = atlx_tx_timeout,
825a84d1
SH		 2896 .ndo_vlan_rx_register = atlx_vlan_rx_register,
2897#ifdef CONFIG_NET_POLL_CONTROLLER
2898 .ndo_poll_controller = atl1_poll_controller,
2899#endif
2900};
2901
f3cc28c7
JC		 2902/*
2903 * atl1_probe - Device Initialization Routine
2904 * @pdev: PCI device information struct
2905 * @ent: entry in atl1_pci_tbl
2906 *
2907 * Returns 0 on success, negative on failure
2908 *
2909 * atl1_probe initializes an adapter identified by a pci_dev structure.
2910 * The OS initialization, configuring of the adapter private structure,
2911 * and a hardware reset occur.
2912 */
2913static int __devinit atl1_probe(struct pci_dev *pdev,
53ffb42c 2914 const struct pci_device_id *ent)
f3cc28c7
JC		 2915{
2916 struct net_device *netdev;
2917 struct atl1_adapter *adapter;
2918 static int cards_found = 0;
f3cc28c7
JC		 2919 int err;
2920
2921 err = pci_enable_device(pdev);
2922 if (err)
2923 return err;
2924
5f08e46b 2925 /*
cdcc520d
CS		 2926 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2927 * shared register for the high 32 bits, so only a single, aligned,
2928 * 4 GB physical address range can be used at a time.
2929 *
2930 * Supporting 64-bit DMA on this hardware is more trouble than it's
2931 * worth. It is far easier to limit to 32-bit DMA than update
2932 * various kernel subsystems to support the mechanics required by a
2933 * fixed-high-32-bit system.
5f08e46b 2934 */
284901a9 2935 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
f3cc28c7 2936 if (err) {
5f08e46b
LT		 2937 dev_err(&pdev->dev, "no usable DMA configuration\n");
2938 goto err_dma;
f3cc28c7 2939 }
6446a860
JC		 2940 /*
2941 * Mark all PCI regions associated with PCI device
f3cc28c7
JC		 2942 * pdev as being reserved by owner atl1_driver_name
2943 */
6446a860 2944 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
f3cc28c7
JC		 2945 if (err)
2946 goto err_request_regions;
2947
6446a860
JC		 2948 /*
2949 * Enables bus-mastering on the device and calls
f3cc28c7
JC		 2950 * pcibios_set_master to do the needed arch specific settings
2951 */
2952 pci_set_master(pdev);
2953
2954 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2955 if (!netdev) {
2956 err = -ENOMEM;
2957 goto err_alloc_etherdev;
2958 }
f3cc28c7
JC		 2959 SET_NETDEV_DEV(netdev, &pdev->dev);
2960
2961 pci_set_drvdata(pdev, netdev);
2962 adapter = netdev_priv(netdev);
2963 adapter->netdev = netdev;
2964 adapter->pdev = pdev;
2965 adapter->hw.back = adapter;
6446a860 2966 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
f3cc28c7
JC		 2967
2968 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2969 if (!adapter->hw.hw_addr) {
2970 err = -EIO;
2971 goto err_pci_iomap;
2972 }
2973 /* get device revision number */
1e006364 2974 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
53ffb42c 2975 (REG_MASTER_CTRL + 2));
6446a860
JC		 2976 if (netif_msg_probe(adapter))
2977 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
f3cc28c7
JC		 2978
2979 /* set default ring resource counts */
2980 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2981 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2982
2983 adapter->mii.dev = netdev;
2984 adapter->mii.mdio_read = mdio_read;
2985 adapter->mii.mdio_write = mdio_write;
2986 adapter->mii.phy_id_mask = 0x1f;
2987 adapter->mii.reg_num_mask = 0x1f;
2988
825a84d1 2989 netdev->netdev_ops = &atl1_netdev_ops;
f3cc28c7 2990 netdev->watchdog_timeo = 5 * HZ;
cb434e38 2991
f3cc28c7
JC		 2992 netdev->ethtool_ops = &atl1_ethtool_ops;
2993 adapter->bd_number = cards_found;
f3cc28c7
JC		 2994
2995 /* setup the private structure */
2996 err = atl1_sw_init(adapter);
2997 if (err)
2998 goto err_common;
2999
3000 netdev->features = NETIF_F_HW_CSUM;
3001 netdev->features |= NETIF_F_SG;
3002 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
f3cc28c7
JC		 3003
3004 /*
3005 * patch for some L1 of old version,
3006 * the final version of L1 may not need these
3007 * patches
3008 */
3009 /* atl1_pcie_patch(adapter); */
3010
3011 /* really reset GPHY core */
6446a860 3012 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3013
3014 /*
3015 * reset the controller to
3016 * put the device in a known good starting state
3017 */
3018 if (atl1_reset_hw(&adapter->hw)) {
3019 err = -EIO;
3020 goto err_common;
3021 }
3022
3023 /* copy the MAC address out of the EEPROM */
3024 atl1_read_mac_addr(&adapter->hw);
3025 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3026
3027 if (!is_valid_ether_addr(netdev->dev_addr)) {
3028 err = -EIO;
3029 goto err_common;
3030 }
3031
3032 atl1_check_options(adapter);
3033
3034 /* pre-init the MAC, and setup link */
3035 err = atl1_init_hw(&adapter->hw);
3036 if (err) {
3037 err = -EIO;
3038 goto err_common;
3039 }
3040
3041 atl1_pcie_patch(adapter);
3042 /* assume we have no link for now */
3043 netif_carrier_off(netdev);
3044 netif_stop_queue(netdev);
3045
e053b628
SH		 3046 setup_timer(&adapter->phy_config_timer, &atl1_phy_config,
3047 (unsigned long)adapter);
f3cc28c7
JC		 3048 adapter->phy_timer_pending = false;
3049
3050 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3051
6446a860 3052 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
f3cc28c7
JC		 3053
3054 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3055
3056 err = register_netdev(netdev);
3057 if (err)
3058 goto err_common;
3059
3060 cards_found++;
3061 atl1_via_workaround(adapter);
3062 return 0;
3063
3064err_common:
3065 pci_iounmap(pdev, adapter->hw.hw_addr);
3066err_pci_iomap:
3067 free_netdev(netdev);
3068err_alloc_etherdev:
3069 pci_release_regions(pdev);
3070err_dma:
3071err_request_regions:
3072 pci_disable_device(pdev);
3073 return err;
3074}
3075
3076/*
3077 * atl1_remove - Device Removal Routine
3078 * @pdev: PCI device information struct
3079 *
3080 * atl1_remove is called by the PCI subsystem to alert the driver
3081 * that it should release a PCI device. The could be caused by a
3082 * Hot-Plug event, or because the driver is going to be removed from
3083 * memory.
3084 */
3085static void __devexit atl1_remove(struct pci_dev *pdev)
3086{
3087 struct net_device *netdev = pci_get_drvdata(pdev);
3088 struct atl1_adapter *adapter;
3089 /* Device not available. Return. */
3090 if (!netdev)
3091 return;
3092
3093 adapter = netdev_priv(netdev);
8c754a04 3094
6446a860
JC		 3095 /*
3096 * Some atl1 boards lack persistent storage for their MAC, and get it
8c754a04
CS		 3097 * from the BIOS during POST. If we've been messing with the MAC
3098 * address, we need to save the permanent one.
3099 */
3100 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
53ffb42c
JC		 3101 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3102 ETH_ALEN);
8c754a04
CS		 3103 atl1_set_mac_addr(&adapter->hw);
3104 }
3105
6446a860 3106 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3107 unregister_netdev(netdev);
3108 pci_iounmap(pdev, adapter->hw.hw_addr);
3109 pci_release_regions(pdev);
3110 free_netdev(netdev);
3111 pci_disable_device(pdev);
3112}
3113
f3cc28c7 3114static struct pci_driver atl1_driver = {
6446a860 3115 .name = ATLX_DRIVER_NAME,
f3cc28c7
JC		 3116 .id_table = atl1_pci_tbl,
3117 .probe = atl1_probe,
3118 .remove = __devexit_p(atl1_remove),
f3cc28c7 3119 .suspend = atl1_suspend,
bf455a22
JC		 3120 .resume = atl1_resume,
3121 .shutdown = atl1_shutdown
f3cc28c7
JC		 3122};
3123
3124/*
3125 * atl1_exit_module - Driver Exit Cleanup Routine
3126 *
3127 * atl1_exit_module is called just before the driver is removed
3128 * from memory.
3129 */
3130static void __exit atl1_exit_module(void)
3131{
3132 pci_unregister_driver(&atl1_driver);
3133}
3134
3135/*
3136 * atl1_init_module - Driver Registration Routine
3137 *
3138 * atl1_init_module is the first routine called when the driver is
3139 * loaded. All it does is register with the PCI subsystem.
3140 */
3141static int __init atl1_init_module(void)
3142{
f3cc28c7
JC		 3143 return pci_register_driver(&atl1_driver);
3144}
3145
3146module_init(atl1_init_module);
3147module_exit(atl1_exit_module);
6446a860
JC		 3148
3149struct atl1_stats {
3150 char stat_string[ETH_GSTRING_LEN];
3151 int sizeof_stat;
3152 int stat_offset;
3153};
3154
3155#define ATL1_STAT(m) \
3156 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3157
3158static struct atl1_stats atl1_gstrings_stats[] = {
3159 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3160 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3161 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3162 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3163 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3164 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
6446a860
JC		 3165 {"multicast", ATL1_STAT(soft_stats.multicast)},
3166 {"collisions", ATL1_STAT(soft_stats.collisions)},
3167 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3168 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3169 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3170 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3171 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3172 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3173 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3174 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3175 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3176 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3177 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3178 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3179 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3180 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3181 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3182 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3183 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3184 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3185 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3186 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3187 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3188};
3189
3190static void atl1_get_ethtool_stats(struct net_device *netdev,
3191 struct ethtool_stats *stats, u64 *data)
305282ba 3192{
6446a860 3193 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3194 int i;
6446a860 3195 char *p;
305282ba 3196
6446a860
JC		 3197 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3198 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3199 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3200 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
305282ba
JC		 3201 }
3202
305282ba
JC		 3203}
3204
6446a860 3205static int atl1_get_sset_count(struct net_device *netdev, int sset)
305282ba 3206{
6446a860
JC		 3207 switch (sset) {
3208 case ETH_SS_STATS:
3209 return ARRAY_SIZE(atl1_gstrings_stats);
3210 default:
3211 return -EOPNOTSUPP;
3212 }
305282ba
JC		 3213}
3214
6446a860
JC		 3215static int atl1_get_settings(struct net_device *netdev,
3216 struct ethtool_cmd *ecmd)
305282ba 3217{
6446a860
JC		 3218 struct atl1_adapter *adapter = netdev_priv(netdev);
3219 struct atl1_hw *hw = &adapter->hw;
3220
3221 ecmd->supported = (SUPPORTED_10baseT_Half |
3222 SUPPORTED_10baseT_Full |
3223 SUPPORTED_100baseT_Half |
3224 SUPPORTED_100baseT_Full |
3225 SUPPORTED_1000baseT_Full |
3226 SUPPORTED_Autoneg | SUPPORTED_TP);
3227 ecmd->advertising = ADVERTISED_TP;
3228 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3229 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3230 ecmd->advertising |= ADVERTISED_Autoneg;
3231 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3232 ecmd->advertising |= ADVERTISED_Autoneg;
3233 ecmd->advertising |=
3234 (ADVERTISED_10baseT_Half |
3235 ADVERTISED_10baseT_Full |
3236 ADVERTISED_100baseT_Half |
3237 ADVERTISED_100baseT_Full |
3238 ADVERTISED_1000baseT_Full);
3239 } else
3240 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3241 }
3242 ecmd->port = PORT_TP;
3243 ecmd->phy_address = 0;
3244 ecmd->transceiver = XCVR_INTERNAL;
3245
3246 if (netif_carrier_ok(adapter->netdev)) {
3247 u16 link_speed, link_duplex;
3248 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3249 ecmd->speed = link_speed;
3250 if (link_duplex == FULL_DUPLEX)
3251 ecmd->duplex = DUPLEX_FULL;
3252 else
3253 ecmd->duplex = DUPLEX_HALF;
3254 } else {
3255 ecmd->speed = -1;
3256 ecmd->duplex = -1;
3257 }
3258 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3259 hw->media_type == MEDIA_TYPE_1000M_FULL)
3260 ecmd->autoneg = AUTONEG_ENABLE;
3261 else
3262 ecmd->autoneg = AUTONEG_DISABLE;
305282ba 3263
305282ba
JC		 3264 return 0;
3265}
3266
6446a860
JC		 3267static int atl1_set_settings(struct net_device *netdev,
3268 struct ethtool_cmd *ecmd)
305282ba 3269{
6446a860
JC		 3270 struct atl1_adapter *adapter = netdev_priv(netdev);
3271 struct atl1_hw *hw = &adapter->hw;
305282ba 3272 u16 phy_data;
6446a860
JC		 3273 int ret_val = 0;
3274 u16 old_media_type = hw->media_type;
305282ba 3275
6446a860
JC		 3276 if (netif_running(adapter->netdev)) {
3277 if (netif_msg_link(adapter))
3278 dev_dbg(&adapter->pdev->dev,
3279 "ethtool shutting down adapter\n");
3280 atl1_down(adapter);
3281 }
3282
3283 if (ecmd->autoneg == AUTONEG_ENABLE)
3284 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3285 else {
3286 if (ecmd->speed == SPEED_1000) {
3287 if (ecmd->duplex != DUPLEX_FULL) {
3288 if (netif_msg_link(adapter))
3289 dev_warn(&adapter->pdev->dev,
3290 "1000M half is invalid\n");
3291 ret_val = -EINVAL;
3292 goto exit_sset;
3293 }
3294 hw->media_type = MEDIA_TYPE_1000M_FULL;
3295 } else if (ecmd->speed == SPEED_100) {
3296 if (ecmd->duplex == DUPLEX_FULL)
3297 hw->media_type = MEDIA_TYPE_100M_FULL;
3298 else
3299 hw->media_type = MEDIA_TYPE_100M_HALF;
3300 } else {
3301 if (ecmd->duplex == DUPLEX_FULL)
3302 hw->media_type = MEDIA_TYPE_10M_FULL;
3303 else
3304 hw->media_type = MEDIA_TYPE_10M_HALF;
3305 }
3306 }
3307 switch (hw->media_type) {
3308 case MEDIA_TYPE_AUTO_SENSOR:
3309 ecmd->advertising =
3310 ADVERTISED_10baseT_Half |
3311 ADVERTISED_10baseT_Full |
3312 ADVERTISED_100baseT_Half |
3313 ADVERTISED_100baseT_Full |
3314 ADVERTISED_1000baseT_Full |
3315 ADVERTISED_Autoneg | ADVERTISED_TP;
3316 break;
3317 case MEDIA_TYPE_1000M_FULL:
3318 ecmd->advertising =
3319 ADVERTISED_1000baseT_Full |
3320 ADVERTISED_Autoneg | ADVERTISED_TP;
3321 break;
3322 default:
3323 ecmd->advertising = 0;
3324 break;
3325 }
3326 if (atl1_phy_setup_autoneg_adv(hw)) {
3327 ret_val = -EINVAL;
3328 if (netif_msg_link(adapter))
3329 dev_warn(&adapter->pdev->dev,
3330 "invalid ethtool speed/duplex setting\n");
3331 goto exit_sset;
3332 }
305282ba
JC		 3333 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3334 hw->media_type == MEDIA_TYPE_1000M_FULL)
3335 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3336 else {
3337 switch (hw->media_type) {
3338 case MEDIA_TYPE_100M_FULL:
3339 phy_data =
3340 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3341 MII_CR_RESET;
3342 break;
3343 case MEDIA_TYPE_100M_HALF:
3344 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3345 break;
3346 case MEDIA_TYPE_10M_FULL:
3347 phy_data =
3348 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3349 break;
3350 default:
3351 /* MEDIA_TYPE_10M_HALF: */
3352 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3353 break;
3354 }
3355 }
6446a860
JC		 3356 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3357exit_sset:
3358 if (ret_val)
3359 hw->media_type = old_media_type;
305282ba 3360
6446a860
JC		 3361 if (netif_running(adapter->netdev)) {
3362 if (netif_msg_link(adapter))
3363 dev_dbg(&adapter->pdev->dev,
3364 "ethtool starting adapter\n");
3365 atl1_up(adapter);
3366 } else if (!ret_val) {
3367 if (netif_msg_link(adapter))
3368 dev_dbg(&adapter->pdev->dev,
3369 "ethtool resetting adapter\n");
3370 atl1_reset(adapter);
3371 }
3372 return ret_val;
3373}
305282ba 3374
6446a860
JC		 3375static void atl1_get_drvinfo(struct net_device *netdev,
3376 struct ethtool_drvinfo *drvinfo)
3377{
3378 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3379
082ba88a
RK		 3380 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3381 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
6446a860 3382 sizeof(drvinfo->version));
082ba88a
RK		 3383 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3384 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
6446a860
JC		 3385 sizeof(drvinfo->bus_info));
3386 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3387}
3388
3389static void atl1_get_wol(struct net_device *netdev,
3390 struct ethtool_wolinfo *wol)
3391{
3392 struct atl1_adapter *adapter = netdev_priv(netdev);
3393
3b259e36 3394 wol->supported = WAKE_MAGIC;
6446a860 3395 wol->wolopts = 0;
6446a860
JC		 3396 if (adapter->wol & ATLX_WUFC_MAG)
3397 wol->wolopts |= WAKE_MAGIC;
6446a860
JC		 3398}
3399
3400static int atl1_set_wol(struct net_device *netdev,
3401 struct ethtool_wolinfo *wol)
3402{
3403 struct atl1_adapter *adapter = netdev_priv(netdev);
3404
3b259e36
C		 3405 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3406 WAKE_ARP | WAKE_MAGICSECURE))
6446a860
JC		 3407 return -EOPNOTSUPP;
3408 adapter->wol = 0;
6446a860
JC		 3409 if (wol->wolopts & WAKE_MAGIC)
3410 adapter->wol |= ATLX_WUFC_MAG;
305282ba
JC		 3411 return 0;
3412}
3413
6446a860 3414static u32 atl1_get_msglevel(struct net_device *netdev)
305282ba 3415{
6446a860
JC		 3416 struct atl1_adapter *adapter = netdev_priv(netdev);
3417 return adapter->msg_enable;
3418}
305282ba 3419
6446a860
JC		 3420static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3421{
3422 struct atl1_adapter *adapter = netdev_priv(netdev);
3423 adapter->msg_enable = value;
3424}
305282ba 3425
6446a860
JC		 3426static int atl1_get_regs_len(struct net_device *netdev)
3427{
3428 return ATL1_REG_COUNT * sizeof(u32);
3429}
305282ba 3430
6446a860
JC		 3431static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3432 void *p)
3433{
3434 struct atl1_adapter *adapter = netdev_priv(netdev);
3435 struct atl1_hw *hw = &adapter->hw;
3436 unsigned int i;
3437 u32 *regbuf = p;
305282ba 3438
6446a860
JC		 3439 for (i = 0; i < ATL1_REG_COUNT; i++) {
3440 /*
3441 * This switch statement avoids reserved regions
3442 * of register space.
3443 */
3444 switch (i) {
3445 case 6 ... 9:
3446 case 14:
3447 case 29 ... 31:
3448 case 34 ... 63:
3449 case 75 ... 127:
3450 case 136 ... 1023:
3451 case 1027 ... 1087:
3452 case 1091 ... 1151:
3453 case 1194 ... 1195:
3454 case 1200 ... 1201:
3455 case 1206 ... 1213:
3456 case 1216 ... 1279:
3457 case 1290 ... 1311:
3458 case 1323 ... 1343:
3459 case 1358 ... 1359:
3460 case 1368 ... 1375:
3461 case 1378 ... 1383:
3462 case 1388 ... 1391:
3463 case 1393 ... 1395:
3464 case 1402 ... 1403:
3465 case 1410 ... 1471:
3466 case 1522 ... 1535:
3467 /* reserved region; don't read it */
3468 regbuf[i] = 0;
3469 break;
3470 default:
3471 /* unreserved region */
3472 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3473 }
3474 }
3475}
305282ba 3476
6446a860
JC		 3477static void atl1_get_ringparam(struct net_device *netdev,
3478 struct ethtool_ringparam *ring)
3479{
3480 struct atl1_adapter *adapter = netdev_priv(netdev);
3481 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3482 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
305282ba 3483
6446a860
JC		 3484 ring->rx_max_pending = ATL1_MAX_RFD;
3485 ring->tx_max_pending = ATL1_MAX_TPD;
3486 ring->rx_mini_max_pending = 0;
3487 ring->rx_jumbo_max_pending = 0;
3488 ring->rx_pending = rxdr->count;
3489 ring->tx_pending = txdr->count;
3490 ring->rx_mini_pending = 0;
3491 ring->rx_jumbo_pending = 0;
3492}
305282ba 3493
6446a860
JC		 3494static int atl1_set_ringparam(struct net_device *netdev,
3495 struct ethtool_ringparam *ring)
3496{
3497 struct atl1_adapter *adapter = netdev_priv(netdev);
3498 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3499 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3500 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
305282ba 3501
6446a860
JC		 3502 struct atl1_tpd_ring tpd_old, tpd_new;
3503 struct atl1_rfd_ring rfd_old, rfd_new;
3504 struct atl1_rrd_ring rrd_old, rrd_new;
3505 struct atl1_ring_header rhdr_old, rhdr_new;
3506 int err;
305282ba 3507
6446a860
JC		 3508 tpd_old = adapter->tpd_ring;
3509 rfd_old = adapter->rfd_ring;
3510 rrd_old = adapter->rrd_ring;
3511 rhdr_old = adapter->ring_header;
305282ba 3512
6446a860
JC		 3513 if (netif_running(adapter->netdev))
3514 atl1_down(adapter);
305282ba 3515
6446a860
JC		 3516 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3517 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3518 rfdr->count;
3519 rfdr->count = (rfdr->count + 3) & ~3;
3520 rrdr->count = rfdr->count;
305282ba 3521
6446a860
JC		 3522 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3523 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3524 tpdr->count;
3525 tpdr->count = (tpdr->count + 3) & ~3;
3526
3527 if (netif_running(adapter->netdev)) {
3528 /* try to get new resources before deleting old */
3529 err = atl1_setup_ring_resources(adapter);
3530 if (err)
3531 goto err_setup_ring;
3532
3533 /*
3534 * save the new, restore the old in order to free it,
3535 * then restore the new back again
3536 */
305282ba 3537
6446a860
JC		 3538 rfd_new = adapter->rfd_ring;
3539 rrd_new = adapter->rrd_ring;
3540 tpd_new = adapter->tpd_ring;
3541 rhdr_new = adapter->ring_header;
3542 adapter->rfd_ring = rfd_old;
3543 adapter->rrd_ring = rrd_old;
3544 adapter->tpd_ring = tpd_old;
3545 adapter->ring_header = rhdr_old;
3546 atl1_free_ring_resources(adapter);
3547 adapter->rfd_ring = rfd_new;
3548 adapter->rrd_ring = rrd_new;
3549 adapter->tpd_ring = tpd_new;
3550 adapter->ring_header = rhdr_new;
305282ba 3551
6446a860
JC		 3552 err = atl1_up(adapter);
3553 if (err)
3554 return err;
3555 }
305282ba 3556 return 0;
6446a860
JC		 3557
3558err_setup_ring:
3559 adapter->rfd_ring = rfd_old;
3560 adapter->rrd_ring = rrd_old;
3561 adapter->tpd_ring = tpd_old;
3562 adapter->ring_header = rhdr_old;
3563 atl1_up(adapter);
3564 return err;
305282ba
JC		 3565}
3566
6446a860
JC		 3567static void atl1_get_pauseparam(struct net_device *netdev,
3568 struct ethtool_pauseparam *epause)
305282ba 3569{
6446a860
JC		 3570 struct atl1_adapter *adapter = netdev_priv(netdev);
3571 struct atl1_hw *hw = &adapter->hw;
305282ba 3572
6446a860
JC		 3573 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3574 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3575 epause->autoneg = AUTONEG_ENABLE;
3576 } else {
3577 epause->autoneg = AUTONEG_DISABLE;
305282ba 3578 }
6446a860
JC		 3579 epause->rx_pause = 1;
3580 epause->tx_pause = 1;
305282ba
JC		 3581}
3582
6446a860
JC		 3583static int atl1_set_pauseparam(struct net_device *netdev,
3584 struct ethtool_pauseparam *epause)
305282ba 3585{
6446a860
JC		 3586 struct atl1_adapter *adapter = netdev_priv(netdev);
3587 struct atl1_hw *hw = &adapter->hw;
305282ba 3588
6446a860
JC		 3589 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3590 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3591 epause->autoneg = AUTONEG_ENABLE;
3592 } else {
3593 epause->autoneg = AUTONEG_DISABLE;
3594 }
3595
3596 epause->rx_pause = 1;
3597 epause->tx_pause = 1;
3598
3599 return 0;
305282ba
JC		 3600}
3601
6446a860
JC		 3602/* FIXME: is this right? -- CHS */
3603static u32 atl1_get_rx_csum(struct net_device *netdev)
305282ba 3604{
6446a860
JC		 3605 return 1;
3606}
305282ba 3607
6446a860
JC		 3608static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3609 u8 *data)
3610{
3611 u8 *p = data;
3612 int i;
305282ba 3613
6446a860
JC		 3614 switch (stringset) {
3615 case ETH_SS_STATS:
3616 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3617 memcpy(p, atl1_gstrings_stats[i].stat_string,
3618 ETH_GSTRING_LEN);
3619 p += ETH_GSTRING_LEN;
3620 }
3621 break;
305282ba 3622 }
305282ba
JC		 3623}
3624
6446a860 3625static int atl1_nway_reset(struct net_device *netdev)
305282ba 3626{
6446a860
JC		 3627 struct atl1_adapter *adapter = netdev_priv(netdev);
3628 struct atl1_hw *hw = &adapter->hw;
305282ba 3629
6446a860
JC		 3630 if (netif_running(netdev)) {
3631 u16 phy_data;
3632 atl1_down(adapter);
305282ba 3633
6446a860
JC		 3634 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3635 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3636 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3637 } else {
3638 switch (hw->media_type) {
3639 case MEDIA_TYPE_100M_FULL:
3640 phy_data = MII_CR_FULL_DUPLEX |
3641 MII_CR_SPEED_100 | MII_CR_RESET;
3642 break;
3643 case MEDIA_TYPE_100M_HALF:
3644 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3645 break;
3646 case MEDIA_TYPE_10M_FULL:
3647 phy_data = MII_CR_FULL_DUPLEX |
3648 MII_CR_SPEED_10 | MII_CR_RESET;
3649 break;
3650 default:
3651 /* MEDIA_TYPE_10M_HALF */
3652 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3653 }
3654 }
3655 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3656 atl1_up(adapter);
305282ba 3657 }
305282ba
JC		 3658 return 0;
3659}
3660
6446a860
JC		 3661const struct ethtool_ops atl1_ethtool_ops = {
3662 .get_settings = atl1_get_settings,
3663 .set_settings = atl1_set_settings,
3664 .get_drvinfo = atl1_get_drvinfo,
3665 .get_wol = atl1_get_wol,
3666 .set_wol = atl1_set_wol,
3667 .get_msglevel = atl1_get_msglevel,
3668 .set_msglevel = atl1_set_msglevel,
3669 .get_regs_len = atl1_get_regs_len,
3670 .get_regs = atl1_get_regs,
3671 .get_ringparam = atl1_get_ringparam,
3672 .set_ringparam = atl1_set_ringparam,
3673 .get_pauseparam = atl1_get_pauseparam,
3674 .set_pauseparam = atl1_set_pauseparam,
3675 .get_rx_csum = atl1_get_rx_csum,
3676 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3677 .get_link = ethtool_op_get_link,
3678 .set_sg = ethtool_op_set_sg,
3679 .get_strings = atl1_get_strings,
3680 .nway_reset = atl1_nway_reset,
3681 .get_ethtool_stats = atl1_get_ethtool_stats,
3682 .get_sset_count = atl1_get_sset_count,
3683 .set_tso = ethtool_op_set_tso,
3684};
Clone of davem's net-next-2.6 tree