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dma-mapping: replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)
[net-next-2.6.git] / drivers / net / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
1da177e4
LT		 70
71#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72#include <linux/if_vlan.h>
73#endif
74
75#ifdef SIOCETHTOOL
76#include <linux/ethtool.h>
77#endif
78
79#include <net/sock.h>
80#include <net/ip.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84#include <asm/irq.h>
85#include <asm/byteorder.h>
86#include <asm/uaccess.h>
87
88
89#define DRV_NAME "acenic"
90
91#undef INDEX_DEBUG
92
93#ifdef CONFIG_ACENIC_OMIT_TIGON_I
94#define ACE_IS_TIGON_I(ap) 0
95#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96#else
97#define ACE_IS_TIGON_I(ap) (ap->version == 1)
98#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99#endif
100
101#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 102#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 103#endif
104#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107#endif
108#ifndef PCI_DEVICE_ID_3COM_3C985
109#define PCI_DEVICE_ID_3COM_3C985 0x0001
110#endif
111#ifndef PCI_VENDOR_ID_NETGEAR
112#define PCI_VENDOR_ID_NETGEAR 0x1385
113#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114#endif
115#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117#endif
118
119
120/*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126#endif
127#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129#endif
130#ifndef PCI_VENDOR_ID_SGI
131#define PCI_VENDOR_ID_SGI 0x10a9
132#endif
133#ifndef PCI_DEVICE_ID_SGI_ACENIC
134#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135#endif
136
137static struct pci_device_id acenic_pci_tbl[] = {
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159};
160MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
1da177e4 162#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 163
164#ifndef offset_in_page
165#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
166#endif
167
168#define ACE_MAX_MOD_PARMS 8
169#define BOARD_IDX_STATIC 0
170#define BOARD_IDX_OVERFLOW -1
171
172#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
173 defined(NETIF_F_HW_VLAN_RX)
174#define ACENIC_DO_VLAN 1
175#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
176#else
177#define ACENIC_DO_VLAN 0
178#define ACE_RCB_VLAN_FLAG 0
179#endif
180
181#include "acenic.h"
182
183/*
184 * These must be defined before the firmware is included.
185 */
186#define MAX_TEXT_LEN 96*1024
187#define MAX_RODATA_LEN 8*1024
188#define MAX_DATA_LEN 2*1024
189
1da177e4
LT		 190#ifndef tigon2FwReleaseLocal
191#define tigon2FwReleaseLocal 0
192#endif
193
194/*
195 * This driver currently supports Tigon I and Tigon II based cards
196 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
197 * GA620. The driver should also work on the SGI, DEC and Farallon
198 * versions of the card, however I have not been able to test that
199 * myself.
200 *
201 * This card is really neat, it supports receive hardware checksumming
202 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
203 * firmware. Also the programming interface is quite neat, except for
204 * the parts dealing with the i2c eeprom on the card ;-)
205 *
206 * Using jumbo frames:
207 *
208 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
209 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
210 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
211 * interface number and <MTU> being the MTU value.
212 *
213 * Module parameters:
214 *
215 * When compiled as a loadable module, the driver allows for a number
216 * of module parameters to be specified. The driver supports the
217 * following module parameters:
218 *
219 * trace=<val> - Firmware trace level. This requires special traced
220 * firmware to replace the firmware supplied with
221 * the driver - for debugging purposes only.
222 *
223 * link=<val> - Link state. Normally you want to use the default link
224 * parameters set by the driver. This can be used to
225 * override these in case your switch doesn't negotiate
226 * the link properly. Valid values are:
227 * 0x0001 - Force half duplex link.
228 * 0x0002 - Do not negotiate line speed with the other end.
229 * 0x0010 - 10Mbit/sec link.
230 * 0x0020 - 100Mbit/sec link.
231 * 0x0040 - 1000Mbit/sec link.
232 * 0x0100 - Do not negotiate flow control.
233 * 0x0200 - Enable RX flow control Y
234 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
235 * Default value is 0x0270, ie. enable link+flow
236 * control negotiation. Negotiating the highest
237 * possible link speed with RX flow control enabled.
238 *
239 * When disabling link speed negotiation, only one link
240 * speed is allowed to be specified!
241 *
242 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
243 * to wait for more packets to arive before
244 * interrupting the host, from the time the first
245 * packet arrives.
246 *
247 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
248 * to wait for more packets to arive in the transmit ring,
249 * before interrupting the host, after transmitting the
250 * first packet in the ring.
251 *
252 * max_tx_desc=<val> - maximum number of transmit descriptors
253 * (packets) transmitted before interrupting the host.
254 *
255 * max_rx_desc=<val> - maximum number of receive descriptors
256 * (packets) received before interrupting the host.
257 *
258 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
259 * increments of the NIC's on board memory to be used for
260 * transmit and receive buffers. For the 1MB NIC app. 800KB
261 * is available, on the 1/2MB NIC app. 300KB is available.
262 * 68KB will always be available as a minimum for both
263 * directions. The default value is a 50/50 split.
264 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
265 * operations, default (1) is to always disable this as
266 * that is what Alteon does on NT. I have not been able
267 * to measure any real performance differences with
268 * this on my systems. Set <val>=0 if you want to
269 * enable these operations.
270 *
271 * If you use more than one NIC, specify the parameters for the
272 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
273 * run tracing on NIC #2 but not on NIC #1 and #3.
274 *
275 * TODO:
276 *
277 * - Proper multicast support.
278 * - NIC dump support.
279 * - More tuning parameters.
280 *
281 * The mini ring is not used under Linux and I am not sure it makes sense
282 * to actually use it.
283 *
284 * New interrupt handler strategy:
285 *
286 * The old interrupt handler worked using the traditional method of
287 * replacing an skbuff with a new one when a packet arrives. However
288 * the rx rings do not need to contain a static number of buffer
289 * descriptors, thus it makes sense to move the memory allocation out
290 * of the main interrupt handler and do it in a bottom half handler
291 * and only allocate new buffers when the number of buffers in the
292 * ring is below a certain threshold. In order to avoid starving the
293 * NIC under heavy load it is however necessary to force allocation
294 * when hitting a minimum threshold. The strategy for alloction is as
295 * follows:
296 *
297 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
298 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
299 * the buffers in the interrupt handler
300 * RX_RING_THRES - maximum number of buffers in the rx ring
301 * RX_MINI_THRES - maximum number of buffers in the mini ring
302 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
303 *
304 * One advantagous side effect of this allocation approach is that the
305 * entire rx processing can be done without holding any spin lock
306 * since the rx rings and registers are totally independent of the tx
307 * ring and its registers. This of course includes the kmalloc's of
308 * new skb's. Thus start_xmit can run in parallel with rx processing
309 * and the memory allocation on SMP systems.
310 *
311 * Note that running the skb reallocation in a bottom half opens up
312 * another can of races which needs to be handled properly. In
313 * particular it can happen that the interrupt handler tries to run
314 * the reallocation while the bottom half is either running on another
315 * CPU or was interrupted on the same CPU. To get around this the
316 * driver uses bitops to prevent the reallocation routines from being
317 * reentered.
318 *
319 * TX handling can also be done without holding any spin lock, wheee
320 * this is fun! since tx_ret_csm is only written to by the interrupt
321 * handler. The case to be aware of is when shutting down the device
322 * and cleaning up where it is necessary to make sure that
323 * start_xmit() is not running while this is happening. Well DaveM
324 * informs me that this case is already protected against ... bye bye
325 * Mr. Spin Lock, it was nice to know you.
326 *
327 * TX interrupts are now partly disabled so the NIC will only generate
328 * TX interrupts for the number of coal ticks, not for the number of
329 * TX packets in the queue. This should reduce the number of TX only,
330 * ie. when no RX processing is done, interrupts seen.
331 */
332
333/*
334 * Threshold values for RX buffer allocation - the low water marks for
335 * when to start refilling the rings are set to 75% of the ring
336 * sizes. It seems to make sense to refill the rings entirely from the
337 * intrrupt handler once it gets below the panic threshold, that way
338 * we don't risk that the refilling is moved to another CPU when the
339 * one running the interrupt handler just got the slab code hot in its
340 * cache.
341 */
342#define RX_RING_SIZE 72
343#define RX_MINI_SIZE 64
344#define RX_JUMBO_SIZE 48
345
346#define RX_PANIC_STD_THRES 16
347#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
348#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
349#define RX_PANIC_MINI_THRES 12
350#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
351#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
352#define RX_PANIC_JUMBO_THRES 6
353#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
354#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
355
356
357/*
358 * Size of the mini ring entries, basically these just should be big
359 * enough to take TCP ACKs
360 */
361#define ACE_MINI_SIZE 100
362
363#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
364#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
365#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
366
367/*
368 * There seems to be a magic difference in the effect between 995 and 996
369 * but little difference between 900 and 995 ... no idea why.
370 *
371 * There is now a default set of tuning parameters which is set, depending
372 * on whether or not the user enables Jumbo frames. It's assumed that if
373 * Jumbo frames are enabled, the user wants optimal tuning for that case.
374 */
375#define DEF_TX_COAL 400 /* 996 */
376#define DEF_TX_MAX_DESC 60 /* was 40 */
377#define DEF_RX_COAL 120 /* 1000 */
378#define DEF_RX_MAX_DESC 25
379#define DEF_TX_RATIO 21 /* 24 */
380
381#define DEF_JUMBO_TX_COAL 20
382#define DEF_JUMBO_TX_MAX_DESC 60
383#define DEF_JUMBO_RX_COAL 30
384#define DEF_JUMBO_RX_MAX_DESC 6
385#define DEF_JUMBO_TX_RATIO 21
386
387#if tigon2FwReleaseLocal < 20001118
388/*
389 * Standard firmware and early modifications duplicate
390 * IRQ load without this flag (coal timer is never reset).
391 * Note that with this flag tx_coal should be less than
392 * time to xmit full tx ring.
393 * 400usec is not so bad for tx ring size of 128.
394 */
395#define TX_COAL_INTS_ONLY 1 /* worth it */
396#else
397/*
398 * With modified firmware, this is not necessary, but still useful.
399 */
400#define TX_COAL_INTS_ONLY 1
401#endif
402
403#define DEF_TRACE 0
404#define DEF_STAT (2 * TICKS_PER_SEC)
405
406
ddfce6bb 407static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 408static int trace[ACE_MAX_MOD_PARMS];
409static int tx_coal_tick[ACE_MAX_MOD_PARMS];
410static int rx_coal_tick[ACE_MAX_MOD_PARMS];
411static int max_tx_desc[ACE_MAX_MOD_PARMS];
412static int max_rx_desc[ACE_MAX_MOD_PARMS];
413static int tx_ratio[ACE_MAX_MOD_PARMS];
414static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
415
416MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
417MODULE_LICENSE("GPL");
418MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 419#ifndef CONFIG_ACENIC_OMIT_TIGON_I
420MODULE_FIRMWARE("acenic/tg1.bin");
421#endif
422MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 423
ddfce6bb 424module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 425module_param_array(trace, int, NULL, 0);
426module_param_array(tx_coal_tick, int, NULL, 0);
427module_param_array(max_tx_desc, int, NULL, 0);
428module_param_array(rx_coal_tick, int, NULL, 0);
429module_param_array(max_rx_desc, int, NULL, 0);
430module_param_array(tx_ratio, int, NULL, 0);
431MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
432MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
433MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
434MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
435MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
436MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
437MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
438
439
da38075c 440static const char version[] __devinitconst =
1da177e4
LT		 441 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
442 " http://home.cern.ch/~jes/gige/acenic.html\n";
443
444static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
445static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
446static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
447
7282d491 448static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 449 .get_settings = ace_get_settings,
450 .set_settings = ace_set_settings,
451 .get_drvinfo = ace_get_drvinfo,
452};
453
454static void ace_watchdog(struct net_device *dev);
455
d8b83c57
SH		 456static const struct net_device_ops ace_netdev_ops = {
457 .ndo_open = ace_open,
458 .ndo_stop = ace_close,
459 .ndo_tx_timeout = ace_watchdog,
460 .ndo_get_stats = ace_get_stats,
00829823 461 .ndo_start_xmit = ace_start_xmit,
d8b83c57 462 .ndo_set_multicast_list = ace_set_multicast_list,
52255bbe 463 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 464 .ndo_set_mac_address = ace_set_mac_addr,
465 .ndo_change_mtu = ace_change_mtu,
00829823 466#if ACENIC_DO_VLAN
d8b83c57 467 .ndo_vlan_rx_register = ace_vlan_rx_register,
00829823 468#endif
d8b83c57
SH		 469};
470
1da177e4
LT		 471static int __devinit acenic_probe_one(struct pci_dev *pdev,
472 const struct pci_device_id *id)
473{
474 struct net_device *dev;
475 struct ace_private *ap;
476 static int boards_found;
477
478 dev = alloc_etherdev(sizeof(struct ace_private));
479 if (dev == NULL) {
480 printk(KERN_ERR "acenic: Unable to allocate "
481 "net_device structure!\n");
482 return -ENOMEM;
483 }
484
1da177e4
LT		 485 SET_NETDEV_DEV(dev, &pdev->dev);
486
454d7c9b 487 ap = netdev_priv(dev);
1da177e4
LT		 488 ap->pdev = pdev;
489 ap->name = pci_name(pdev);
490
491 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
492#if ACENIC_DO_VLAN
493 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 494#endif
25805dcf 495
25805dcf 496 dev->watchdog_timeo = 5*HZ;
1da177e4 497
d8b83c57 498 dev->netdev_ops = &ace_netdev_ops;
1da177e4 499 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 500
501 /* we only display this string ONCE */
502 if (!boards_found)
503 printk(version);
504
505 if (pci_enable_device(pdev))
506 goto fail_free_netdev;
507
508 /*
509 * Enable master mode before we start playing with the
510 * pci_command word since pci_set_master() will modify
511 * it.
512 */
513 pci_set_master(pdev);
514
515 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
516
6aa20a22 517 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 518 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
519 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
520 "access - was not enabled by BIOS/Firmware\n",
521 ap->name);
522 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
523 pci_write_config_word(ap->pdev, PCI_COMMAND,
524 ap->pci_command);
525 wmb();
526 }
527
528 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
529 if (ap->pci_latency <= 0x40) {
530 ap->pci_latency = 0x40;
531 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
532 }
533
534 /*
535 * Remap the regs into kernel space - this is abuse of
536 * dev->base_addr since it was means for I/O port
537 * addresses but who gives a damn.
538 */
539 dev->base_addr = pci_resource_start(pdev, 0);
540 ap->regs = ioremap(dev->base_addr, 0x4000);
541 if (!ap->regs) {
542 printk(KERN_ERR "%s: Unable to map I/O register, "
543 "AceNIC %i will be disabled.\n",
544 ap->name, boards_found);
545 goto fail_free_netdev;
546 }
547
548 switch(pdev->vendor) {
549 case PCI_VENDOR_ID_ALTEON:
550 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
551 printk(KERN_INFO "%s: Farallon PN9100-T ",
552 ap->name);
553 } else {
554 printk(KERN_INFO "%s: Alteon AceNIC ",
555 ap->name);
556 }
557 break;
558 case PCI_VENDOR_ID_3COM:
559 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
560 break;
561 case PCI_VENDOR_ID_NETGEAR:
562 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
563 break;
564 case PCI_VENDOR_ID_DEC:
565 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
566 printk(KERN_INFO "%s: Farallon PN9000-SX ",
567 ap->name);
568 break;
569 }
570 case PCI_VENDOR_ID_SGI:
571 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
572 break;
573 default:
574 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
575 break;
576 }
577
578 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 579 printk("irq %d\n", pdev->irq);
1da177e4
LT		 580
581#ifdef CONFIG_ACENIC_OMIT_TIGON_I
582 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
583 printk(KERN_ERR "%s: Driver compiled without Tigon I"
584 " support - NIC disabled\n", dev->name);
585 goto fail_uninit;
586 }
587#endif
588
589 if (ace_allocate_descriptors(dev))
590 goto fail_free_netdev;
591
592#ifdef MODULE
593 if (boards_found >= ACE_MAX_MOD_PARMS)
594 ap->board_idx = BOARD_IDX_OVERFLOW;
595 else
596 ap->board_idx = boards_found;
597#else
598 ap->board_idx = BOARD_IDX_STATIC;
599#endif
600
601 if (ace_init(dev))
602 goto fail_free_netdev;
603
604 if (register_netdev(dev)) {
605 printk(KERN_ERR "acenic: device registration failed\n");
606 goto fail_uninit;
607 }
608 ap->name = dev->name;
609
610 if (ap->pci_using_dac)
611 dev->features |= NETIF_F_HIGHDMA;
612
613 pci_set_drvdata(pdev, dev);
614
615 boards_found++;
616 return 0;
617
618 fail_uninit:
619 ace_init_cleanup(dev);
620 fail_free_netdev:
621 free_netdev(dev);
622 return -ENODEV;
623}
624
625static void __devexit acenic_remove_one(struct pci_dev *pdev)
626{
627 struct net_device *dev = pci_get_drvdata(pdev);
628 struct ace_private *ap = netdev_priv(dev);
629 struct ace_regs __iomem *regs = ap->regs;
630 short i;
631
632 unregister_netdev(dev);
633
634 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
635 if (ap->version >= 2)
636 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 637
1da177e4
LT		 638 /*
639 * This clears any pending interrupts
640 */
641 writel(1, &regs->Mb0Lo);
642 readl(&regs->CpuCtrl); /* flush */
643
644 /*
645 * Make sure no other CPUs are processing interrupts
646 * on the card before the buffers are being released.
647 * Otherwise one might experience some `interesting'
648 * effects.
649 *
650 * Then release the RX buffers - jumbo buffers were
651 * already released in ace_close().
652 */
653 ace_sync_irq(dev->irq);
654
655 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
656 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
657
658 if (skb) {
659 struct ring_info *ringp;
660 dma_addr_t mapping;
661
662 ringp = &ap->skb->rx_std_skbuff[i];
663 mapping = pci_unmap_addr(ringp, mapping);
664 pci_unmap_page(ap->pdev, mapping,
665 ACE_STD_BUFSIZE,
666 PCI_DMA_FROMDEVICE);
667
668 ap->rx_std_ring[i].size = 0;
669 ap->skb->rx_std_skbuff[i].skb = NULL;
670 dev_kfree_skb(skb);
671 }
672 }
673
674 if (ap->version >= 2) {
675 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
676 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
677
678 if (skb) {
679 struct ring_info *ringp;
680 dma_addr_t mapping;
681
682 ringp = &ap->skb->rx_mini_skbuff[i];
683 mapping = pci_unmap_addr(ringp,mapping);
684 pci_unmap_page(ap->pdev, mapping,
685 ACE_MINI_BUFSIZE,
686 PCI_DMA_FROMDEVICE);
687
688 ap->rx_mini_ring[i].size = 0;
689 ap->skb->rx_mini_skbuff[i].skb = NULL;
690 dev_kfree_skb(skb);
691 }
692 }
693 }
694
695 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
696 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
697 if (skb) {
698 struct ring_info *ringp;
699 dma_addr_t mapping;
700
701 ringp = &ap->skb->rx_jumbo_skbuff[i];
702 mapping = pci_unmap_addr(ringp, mapping);
703 pci_unmap_page(ap->pdev, mapping,
704 ACE_JUMBO_BUFSIZE,
705 PCI_DMA_FROMDEVICE);
706
707 ap->rx_jumbo_ring[i].size = 0;
708 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
709 dev_kfree_skb(skb);
710 }
711 }
712
713 ace_init_cleanup(dev);
714 free_netdev(dev);
715}
716
717static struct pci_driver acenic_pci_driver = {
718 .name = "acenic",
719 .id_table = acenic_pci_tbl,
720 .probe = acenic_probe_one,
721 .remove = __devexit_p(acenic_remove_one),
722};
723
724static int __init acenic_init(void)
725{
29917620 726 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 727}
728
729static void __exit acenic_exit(void)
730{
731 pci_unregister_driver(&acenic_pci_driver);
732}
733
734module_init(acenic_init);
735module_exit(acenic_exit);
736
737static void ace_free_descriptors(struct net_device *dev)
738{
739 struct ace_private *ap = netdev_priv(dev);
740 int size;
741
742 if (ap->rx_std_ring != NULL) {
743 size = (sizeof(struct rx_desc) *
744 (RX_STD_RING_ENTRIES +
745 RX_JUMBO_RING_ENTRIES +
746 RX_MINI_RING_ENTRIES +
747 RX_RETURN_RING_ENTRIES));
748 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
749 ap->rx_ring_base_dma);
750 ap->rx_std_ring = NULL;
751 ap->rx_jumbo_ring = NULL;
752 ap->rx_mini_ring = NULL;
753 ap->rx_return_ring = NULL;
754 }
755 if (ap->evt_ring != NULL) {
756 size = (sizeof(struct event) * EVT_RING_ENTRIES);
757 pci_free_consistent(ap->pdev, size, ap->evt_ring,
758 ap->evt_ring_dma);
759 ap->evt_ring = NULL;
760 }
761 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
762 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
763 pci_free_consistent(ap->pdev, size, ap->tx_ring,
764 ap->tx_ring_dma);
765 }
766 ap->tx_ring = NULL;
767
768 if (ap->evt_prd != NULL) {
769 pci_free_consistent(ap->pdev, sizeof(u32),
770 (void *)ap->evt_prd, ap->evt_prd_dma);
771 ap->evt_prd = NULL;
772 }
773 if (ap->rx_ret_prd != NULL) {
774 pci_free_consistent(ap->pdev, sizeof(u32),
775 (void *)ap->rx_ret_prd,
776 ap->rx_ret_prd_dma);
777 ap->rx_ret_prd = NULL;
778 }
779 if (ap->tx_csm != NULL) {
780 pci_free_consistent(ap->pdev, sizeof(u32),
781 (void *)ap->tx_csm, ap->tx_csm_dma);
782 ap->tx_csm = NULL;
783 }
784}
785
786
787static int ace_allocate_descriptors(struct net_device *dev)
788{
789 struct ace_private *ap = netdev_priv(dev);
790 int size;
791
792 size = (sizeof(struct rx_desc) *
793 (RX_STD_RING_ENTRIES +
794 RX_JUMBO_RING_ENTRIES +
795 RX_MINI_RING_ENTRIES +
796 RX_RETURN_RING_ENTRIES));
797
798 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
799 &ap->rx_ring_base_dma);
800 if (ap->rx_std_ring == NULL)
801 goto fail;
802
803 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
804 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
805 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
806
807 size = (sizeof(struct event) * EVT_RING_ENTRIES);
808
809 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
810
811 if (ap->evt_ring == NULL)
812 goto fail;
813
814 /*
815 * Only allocate a host TX ring for the Tigon II, the Tigon I
816 * has to use PCI registers for this ;-(
817 */
818 if (!ACE_IS_TIGON_I(ap)) {
819 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
820
821 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
822 &ap->tx_ring_dma);
823
824 if (ap->tx_ring == NULL)
825 goto fail;
826 }
827
828 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
829 &ap->evt_prd_dma);
830 if (ap->evt_prd == NULL)
831 goto fail;
832
833 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
834 &ap->rx_ret_prd_dma);
835 if (ap->rx_ret_prd == NULL)
836 goto fail;
837
838 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
839 &ap->tx_csm_dma);
840 if (ap->tx_csm == NULL)
841 goto fail;
842
843 return 0;
844
845fail:
846 /* Clean up. */
847 ace_init_cleanup(dev);
848 return 1;
849}
850
851
852/*
853 * Generic cleanup handling data allocated during init. Used when the
854 * module is unloaded or if an error occurs during initialization
855 */
856static void ace_init_cleanup(struct net_device *dev)
857{
858 struct ace_private *ap;
859
860 ap = netdev_priv(dev);
861
862 ace_free_descriptors(dev);
863
864 if (ap->info)
865 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
866 ap->info, ap->info_dma);
b4558ea9
JJ		 867 kfree(ap->skb);
868 kfree(ap->trace_buf);
1da177e4
LT		 869
870 if (dev->irq)
871 free_irq(dev->irq, dev);
872
873 iounmap(ap->regs);
874}
875
876
877/*
878 * Commands are considered to be slow.
879 */
880static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
881{
882 u32 idx;
883
884 idx = readl(&regs->CmdPrd);
885
886 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
887 idx = (idx + 1) % CMD_RING_ENTRIES;
888
889 writel(idx, &regs->CmdPrd);
890}
891
892
893static int __devinit ace_init(struct net_device *dev)
894{
895 struct ace_private *ap;
896 struct ace_regs __iomem *regs;
897 struct ace_info *info = NULL;
898 struct pci_dev *pdev;
899 unsigned long myjif;
900 u64 tmp_ptr;
901 u32 tig_ver, mac1, mac2, tmp, pci_state;
902 int board_idx, ecode = 0;
903 short i;
904 unsigned char cache_size;
905
906 ap = netdev_priv(dev);
907 regs = ap->regs;
908
909 board_idx = ap->board_idx;
910
911 /*
912 * aman@sgi.com - its useful to do a NIC reset here to
913 * address the `Firmware not running' problem subsequent
914 * to any crashes involving the NIC
915 */
916 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
917 readl(&regs->HostCtrl); /* PCI write posting */
918 udelay(5);
919
920 /*
921 * Don't access any other registers before this point!
922 */
923#ifdef __BIG_ENDIAN
924 /*
925 * This will most likely need BYTE_SWAP once we switch
926 * to using __raw_writel()
927 */
928 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
929 &regs->HostCtrl);
930#else
931 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
932 &regs->HostCtrl);
933#endif
934 readl(&regs->HostCtrl); /* PCI write posting */
935
936 /*
937 * Stop the NIC CPU and clear pending interrupts
938 */
939 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
940 readl(&regs->CpuCtrl); /* PCI write posting */
941 writel(0, &regs->Mb0Lo);
942
943 tig_ver = readl(&regs->HostCtrl) >> 28;
944
945 switch(tig_ver){
946#ifndef CONFIG_ACENIC_OMIT_TIGON_I
947 case 4:
948 case 5:
949 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 950 tig_ver, ap->firmware_major, ap->firmware_minor,
951 ap->firmware_fix);
1da177e4
LT		 952 writel(0, &regs->LocalCtrl);
953 ap->version = 1;
954 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
955 break;
956#endif
957 case 6:
958 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 959 tig_ver, ap->firmware_major, ap->firmware_minor,
960 ap->firmware_fix);
1da177e4
LT		 961 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
962 readl(&regs->CpuBCtrl); /* PCI write posting */
963 /*
964 * The SRAM bank size does _not_ indicate the amount
965 * of memory on the card, it controls the _bank_ size!
966 * Ie. a 1MB AceNIC will have two banks of 512KB.
967 */
968 writel(SRAM_BANK_512K, &regs->LocalCtrl);
969 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
970 ap->version = 2;
971 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
972 break;
973 default:
974 printk(KERN_WARNING " Unsupported Tigon version detected "
975 "(%i)\n", tig_ver);
976 ecode = -ENODEV;
977 goto init_error;
978 }
979
980 /*
981 * ModeStat _must_ be set after the SRAM settings as this change
982 * seems to corrupt the ModeStat and possible other registers.
983 * The SRAM settings survive resets and setting it to the same
984 * value a second time works as well. This is what caused the
985 * `Firmware not running' problem on the Tigon II.
986 */
987#ifdef __BIG_ENDIAN
988 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
989 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
990#else
991 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
992 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
993#endif
994 readl(&regs->ModeStat); /* PCI write posting */
995
996 mac1 = 0;
997 for(i = 0; i < 4; i++) {
ddfce6bb 998 int t;
6f9d4722 999
1da177e4 1000 mac1 = mac1 << 8;
ddfce6bb
SH		 1001 t = read_eeprom_byte(dev, 0x8c+i);
1002 if (t < 0) {
1da177e4
LT		 1003 ecode = -EIO;
1004 goto init_error;
1005 } else
ddfce6bb 1006 mac1 |= (t & 0xff);
1da177e4
LT		 1007 }
1008 mac2 = 0;
1009 for(i = 4; i < 8; i++) {
ddfce6bb 1010 int t;
6f9d4722 1011
1da177e4 1012 mac2 = mac2 << 8;
ddfce6bb
SH		 1013 t = read_eeprom_byte(dev, 0x8c+i);
1014 if (t < 0) {
1da177e4
LT		 1015 ecode = -EIO;
1016 goto init_error;
1017 } else
ddfce6bb 1018 mac2 |= (t & 0xff);
1da177e4
LT		 1019 }
1020
1021 writel(mac1, &regs->MacAddrHi);
1022 writel(mac2, &regs->MacAddrLo);
1023
1da177e4
LT		 1024 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1025 dev->dev_addr[1] = mac1 & 0xff;
1026 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1027 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1028 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1029 dev->dev_addr[5] = mac2 & 0xff;
1030
e174961c 1031 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1032
1da177e4
LT		 1033 /*
1034 * Looks like this is necessary to deal with on all architectures,
1035 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1036 * Ie. having two NICs in the machine, one will have the cache
1037 * line set at boot time, the other will not.
1038 */
1039 pdev = ap->pdev;
1040 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1041 cache_size <<= 2;
1042 if (cache_size != SMP_CACHE_BYTES) {
1043 printk(KERN_INFO " PCI cache line size set incorrectly "
1044 "(%i bytes) by BIOS/FW, ", cache_size);
1045 if (cache_size > SMP_CACHE_BYTES)
1046 printk("expecting %i\n", SMP_CACHE_BYTES);
1047 else {
1048 printk("correcting to %i\n", SMP_CACHE_BYTES);
1049 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1050 SMP_CACHE_BYTES >> 2);
1051 }
1052 }
1053
1054 pci_state = readl(&regs->PciState);
1055 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1056 "latency: %i clks\n",
1057 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1058 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1059 ap->pci_latency);
1060
1061 /*
1062 * Set the max DMA transfer size. Seems that for most systems
1063 * the performance is better when no MAX parameter is
1064 * set. However for systems enabling PCI write and invalidate,
1065 * DMA writes must be set to the L1 cache line size to get
1066 * optimal performance.
1067 *
1068 * The default is now to turn the PCI write and invalidate off
1069 * - that is what Alteon does for NT.
1070 */
1071 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1072 if (ap->version >= 2) {
1073 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1074 /*
1075 * Tuning parameters only supported for 8 cards
1076 */
1077 if (board_idx == BOARD_IDX_OVERFLOW ||
1078 dis_pci_mem_inval[board_idx]) {
1079 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1080 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1081 pci_write_config_word(pdev, PCI_COMMAND,
1082 ap->pci_command);
1083 printk(KERN_INFO " Disabling PCI memory "
1084 "write and invalidate\n");
1085 }
1086 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1087 printk(KERN_INFO " PCI memory write & invalidate "
1088 "enabled by BIOS, enabling counter measures\n");
1089
1090 switch(SMP_CACHE_BYTES) {
1091 case 16:
1092 tmp |= DMA_WRITE_MAX_16;
1093 break;
1094 case 32:
1095 tmp |= DMA_WRITE_MAX_32;
1096 break;
1097 case 64:
1098 tmp |= DMA_WRITE_MAX_64;
1099 break;
1100 case 128:
1101 tmp |= DMA_WRITE_MAX_128;
1102 break;
1103 default:
1104 printk(KERN_INFO " Cache line size %i not "
1105 "supported, PCI write and invalidate "
1106 "disabled\n", SMP_CACHE_BYTES);
1107 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1108 pci_write_config_word(pdev, PCI_COMMAND,
1109 ap->pci_command);
1110 }
1111 }
1112 }
1113
1114#ifdef __sparc__
1115 /*
1116 * On this platform, we know what the best dma settings
1117 * are. We use 64-byte maximum bursts, because if we
1118 * burst larger than the cache line size (or even cross
1119 * a 64byte boundary in a single burst) the UltraSparc
1120 * PCI controller will disconnect at 64-byte multiples.
1121 *
1122 * Read-multiple will be properly enabled above, and when
1123 * set will give the PCI controller proper hints about
1124 * prefetching.
1125 */
1126 tmp &= ~DMA_READ_WRITE_MASK;
1127 tmp |= DMA_READ_MAX_64;
1128 tmp |= DMA_WRITE_MAX_64;
1129#endif
1130#ifdef __alpha__
1131 tmp &= ~DMA_READ_WRITE_MASK;
1132 tmp |= DMA_READ_MAX_128;
1133 /*
1134 * All the docs say MUST NOT. Well, I did.
1135 * Nothing terrible happens, if we load wrong size.
1136 * Bit w&i still works better!
1137 */
1138 tmp |= DMA_WRITE_MAX_128;
1139#endif
1140 writel(tmp, &regs->PciState);
1141
1142#if 0
1143 /*
1144 * The Host PCI bus controller driver has to set FBB.
1145 * If all devices on that PCI bus support FBB, then the controller
1146 * can enable FBB support in the Host PCI Bus controller (or on
1147 * the PCI-PCI bridge if that applies).
1148 * -ggg
1149 */
1150 /*
1151 * I have received reports from people having problems when this
1152 * bit is enabled.
1153 */
1154 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1155 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1156 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1157 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1158 }
1159#endif
6aa20a22 1160
1da177e4
LT		 1161 /*
1162 * Configure DMA attributes.
1163 */
6a35528a 1164 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1165 ap->pci_using_dac = 1;
284901a9 1166 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1167 ap->pci_using_dac = 0;
1168 } else {
1169 ecode = -ENODEV;
1170 goto init_error;
1171 }
1172
1173 /*
1174 * Initialize the generic info block and the command+event rings
1175 * and the control blocks for the transmit and receive rings
1176 * as they need to be setup once and for all.
1177 */
1178 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1179 &ap->info_dma))) {
1180 ecode = -EAGAIN;
1181 goto init_error;
1182 }
1183 ap->info = info;
1184
1185 /*
1186 * Get the memory for the skb rings.
1187 */
1188 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1189 ecode = -EAGAIN;
1190 goto init_error;
1191 }
1192
1fb9df5d 1193 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1194 DRV_NAME, dev);
1195 if (ecode) {
1196 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1197 DRV_NAME, pdev->irq);
1198 goto init_error;
1199 } else
1200 dev->irq = pdev->irq;
1201
1202#ifdef INDEX_DEBUG
1203 spin_lock_init(&ap->debug_lock);
1204 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1205 ap->last_std_rx = 0;
1206 ap->last_mini_rx = 0;
1207#endif
1208
1209 memset(ap->info, 0, sizeof(struct ace_info));
1210 memset(ap->skb, 0, sizeof(struct ace_skb));
1211
949b4254
JS		 1212 if (ace_load_firmware(dev))
1213 goto init_error;
1214
1da177e4
LT		 1215 ap->fw_running = 0;
1216
1217 tmp_ptr = ap->info_dma;
1218 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1219 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1220
1221 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1222
1223 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1224 info->evt_ctrl.flags = 0;
1225
1226 *(ap->evt_prd) = 0;
1227 wmb();
1228 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1229 writel(0, &regs->EvtCsm);
1230
1231 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1232 info->cmd_ctrl.flags = 0;
1233 info->cmd_ctrl.max_len = 0;
1234
1235 for (i = 0; i < CMD_RING_ENTRIES; i++)
1236 writel(0, &regs->CmdRng[i]);
1237
1238 writel(0, &regs->CmdPrd);
1239 writel(0, &regs->CmdCsm);
1240
1241 tmp_ptr = ap->info_dma;
1242 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1243 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1244
1245 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1246 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1247 info->rx_std_ctrl.flags =
1248 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1249
1250 memset(ap->rx_std_ring, 0,
1251 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1252
1253 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1254 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1255
1256 ap->rx_std_skbprd = 0;
1257 atomic_set(&ap->cur_rx_bufs, 0);
1258
1259 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1260 (ap->rx_ring_base_dma +
1261 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1262 info->rx_jumbo_ctrl.max_len = 0;
1263 info->rx_jumbo_ctrl.flags =
1264 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1265
1266 memset(ap->rx_jumbo_ring, 0,
1267 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1268
1269 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1270 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1271
1272 ap->rx_jumbo_skbprd = 0;
1273 atomic_set(&ap->cur_jumbo_bufs, 0);
1274
1275 memset(ap->rx_mini_ring, 0,
1276 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1277
1278 if (ap->version >= 2) {
1279 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1280 (ap->rx_ring_base_dma +
1281 (sizeof(struct rx_desc) *
1282 (RX_STD_RING_ENTRIES +
1283 RX_JUMBO_RING_ENTRIES))));
1284 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1285 info->rx_mini_ctrl.flags =
1da177e4
LT		 1286 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1287
1288 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1289 ap->rx_mini_ring[i].flags =
1290 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1291 } else {
1292 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1293 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1294 info->rx_mini_ctrl.max_len = 0;
1295 }
1296
1297 ap->rx_mini_skbprd = 0;
1298 atomic_set(&ap->cur_mini_bufs, 0);
1299
1300 set_aceaddr(&info->rx_return_ctrl.rngptr,
1301 (ap->rx_ring_base_dma +
1302 (sizeof(struct rx_desc) *
1303 (RX_STD_RING_ENTRIES +
1304 RX_JUMBO_RING_ENTRIES +
1305 RX_MINI_RING_ENTRIES))));
1306 info->rx_return_ctrl.flags = 0;
1307 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1308
1309 memset(ap->rx_return_ring, 0,
1310 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1311
1312 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1313 *(ap->rx_ret_prd) = 0;
1314
1315 writel(TX_RING_BASE, &regs->WinBase);
1316
1317 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1318 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1319 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1320 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1321 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1322
1323 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1324 } else {
1325 memset(ap->tx_ring, 0,
1326 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1327
1328 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1329 }
1330
1331 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1332 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1333
1334 /*
1335 * The Tigon I does not like having the TX ring in host memory ;-(
1336 */
1337 if (!ACE_IS_TIGON_I(ap))
1338 tmp |= RCB_FLG_TX_HOST_RING;
1339#if TX_COAL_INTS_ONLY
1340 tmp |= RCB_FLG_COAL_INT_ONLY;
1341#endif
1342 info->tx_ctrl.flags = tmp;
1343
1344 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1345
1346 /*
1347 * Potential item for tuning parameter
1348 */
1349#if 0 /* NO */
1350 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1351 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1352#else
1353 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1354 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1355#endif
1356
1357 writel(0, &regs->MaskInt);
1358 writel(1, &regs->IfIdx);
1359#if 0
1360 /*
1361 * McKinley boxes do not like us fiddling with AssistState
1362 * this early
1363 */
1364 writel(1, &regs->AssistState);
1365#endif
1366
1367 writel(DEF_STAT, &regs->TuneStatTicks);
1368 writel(DEF_TRACE, &regs->TuneTrace);
1369
1370 ace_set_rxtx_parms(dev, 0);
1371
1372 if (board_idx == BOARD_IDX_OVERFLOW) {
1373 printk(KERN_WARNING "%s: more than %i NICs detected, "
1374 "ignoring module parameters!\n",
1375 ap->name, ACE_MAX_MOD_PARMS);
1376 } else if (board_idx >= 0) {
1377 if (tx_coal_tick[board_idx])
1378 writel(tx_coal_tick[board_idx],
1379 &regs->TuneTxCoalTicks);
1380 if (max_tx_desc[board_idx])
1381 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1382
1383 if (rx_coal_tick[board_idx])
1384 writel(rx_coal_tick[board_idx],
1385 &regs->TuneRxCoalTicks);
1386 if (max_rx_desc[board_idx])
1387 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1388
1389 if (trace[board_idx])
1390 writel(trace[board_idx], &regs->TuneTrace);
1391
1392 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1393 writel(tx_ratio[board_idx], &regs->TxBufRat);
1394 }
1395
1396 /*
1397 * Default link parameters
1398 */
1399 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1400 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1401 if(ap->version >= 2)
1402 tmp |= LNK_TX_FLOW_CTL_Y;
1403
1404 /*
1405 * Override link default parameters
1406 */
ddfce6bb
SH		 1407 if ((board_idx >= 0) && link_state[board_idx]) {
1408 int option = link_state[board_idx];
1da177e4
LT		 1409
1410 tmp = LNK_ENABLE;
1411
1412 if (option & 0x01) {
1413 printk(KERN_INFO "%s: Setting half duplex link\n",
1414 ap->name);
1415 tmp &= ~LNK_FULL_DUPLEX;
1416 }
1417 if (option & 0x02)
1418 tmp &= ~LNK_NEGOTIATE;
1419 if (option & 0x10)
1420 tmp |= LNK_10MB;
1421 if (option & 0x20)
1422 tmp |= LNK_100MB;
1423 if (option & 0x40)
1424 tmp |= LNK_1000MB;
1425 if ((option & 0x70) == 0) {
1426 printk(KERN_WARNING "%s: No media speed specified, "
1427 "forcing auto negotiation\n", ap->name);
1428 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1429 LNK_100MB | LNK_10MB;
1430 }
1431 if ((option & 0x100) == 0)
1432 tmp |= LNK_NEG_FCTL;
1433 else
1434 printk(KERN_INFO "%s: Disabling flow control "
1435 "negotiation\n", ap->name);
1436 if (option & 0x200)
1437 tmp |= LNK_RX_FLOW_CTL_Y;
1438 if ((option & 0x400) && (ap->version >= 2)) {
1439 printk(KERN_INFO "%s: Enabling TX flow control\n",
1440 ap->name);
1441 tmp |= LNK_TX_FLOW_CTL_Y;
1442 }
1443 }
1444
1445 ap->link = tmp;
1446 writel(tmp, &regs->TuneLink);
1447 if (ap->version >= 2)
1448 writel(tmp, &regs->TuneFastLink);
1449
949b4254 1450 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1451
1452 writel(0, &regs->Mb0Lo);
1453
1454 /*
1455 * Set tx_csm before we start receiving interrupts, otherwise
1456 * the interrupt handler might think it is supposed to process
1457 * tx ints before we are up and running, which may cause a null
1458 * pointer access in the int handler.
1459 */
1460 ap->cur_rx = 0;
1461 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1462
1463 wmb();
1464 ace_set_txprd(regs, ap, 0);
1465 writel(0, &regs->RxRetCsm);
1466
1da177e4
LT		 1467 /*
1468 * Enable DMA engine now.
1469 * If we do this sooner, Mckinley box pukes.
1470 * I assume it's because Tigon II DMA engine wants to check
1471 * *something* even before the CPU is started.
1472 */
1473 writel(1, &regs->AssistState); /* enable DMA */
1474
1475 /*
1476 * Start the NIC CPU
1477 */
1478 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1479 readl(&regs->CpuCtrl);
1480
1481 /*
1482 * Wait for the firmware to spin up - max 3 seconds.
1483 */
1484 myjif = jiffies + 3 * HZ;
1485 while (time_before(jiffies, myjif) && !ap->fw_running)
1486 cpu_relax();
1487
1488 if (!ap->fw_running) {
1489 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1490
1491 ace_dump_trace(ap);
1492 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1493 readl(&regs->CpuCtrl);
1494
1495 /* aman@sgi.com - account for badly behaving firmware/NIC:
1496 * - have observed that the NIC may continue to generate
1497 * interrupts for some reason; attempt to stop it - halt
1498 * second CPU for Tigon II cards, and also clear Mb0
1499 * - if we're a module, we'll fail to load if this was
1500 * the only GbE card in the system => if the kernel does
1501 * see an interrupt from the NIC, code to handle it is
1502 * gone and OOps! - so free_irq also
1503 */
1504 if (ap->version >= 2)
1505 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1506 &regs->CpuBCtrl);
1507 writel(0, &regs->Mb0Lo);
1508 readl(&regs->Mb0Lo);
1509
1510 ecode = -EBUSY;
1511 goto init_error;
1512 }
1513
1514 /*
1515 * We load the ring here as there seem to be no way to tell the
1516 * firmware to wipe the ring without re-initializing it.
1517 */
1518 if (!test_and_set_bit(0, &ap->std_refill_busy))
1519 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1520 else
1521 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1522 ap->name);
1523 if (ap->version >= 2) {
1524 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1525 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1526 else
1527 printk(KERN_ERR "%s: Someone is busy refilling "
1528 "the RX mini ring\n", ap->name);
1529 }
1530 return 0;
1531
1532 init_error:
1533 ace_init_cleanup(dev);
1534 return ecode;
1535}
1536
1537
1538static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1539{
1540 struct ace_private *ap = netdev_priv(dev);
1541 struct ace_regs __iomem *regs = ap->regs;
1542 int board_idx = ap->board_idx;
1543
1544 if (board_idx >= 0) {
1545 if (!jumbo) {
1546 if (!tx_coal_tick[board_idx])
1547 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1548 if (!max_tx_desc[board_idx])
1549 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1550 if (!rx_coal_tick[board_idx])
1551 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1552 if (!max_rx_desc[board_idx])
1553 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1554 if (!tx_ratio[board_idx])
1555 writel(DEF_TX_RATIO, &regs->TxBufRat);
1556 } else {
1557 if (!tx_coal_tick[board_idx])
1558 writel(DEF_JUMBO_TX_COAL,
1559 &regs->TuneTxCoalTicks);
1560 if (!max_tx_desc[board_idx])
1561 writel(DEF_JUMBO_TX_MAX_DESC,
1562 &regs->TuneMaxTxDesc);
1563 if (!rx_coal_tick[board_idx])
1564 writel(DEF_JUMBO_RX_COAL,
1565 &regs->TuneRxCoalTicks);
1566 if (!max_rx_desc[board_idx])
1567 writel(DEF_JUMBO_RX_MAX_DESC,
1568 &regs->TuneMaxRxDesc);
1569 if (!tx_ratio[board_idx])
1570 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1571 }
1572 }
1573}
1574
1575
1576static void ace_watchdog(struct net_device *data)
1577{
1578 struct net_device *dev = data;
1579 struct ace_private *ap = netdev_priv(dev);
1580 struct ace_regs __iomem *regs = ap->regs;
1581
1582 /*
1583 * We haven't received a stats update event for more than 2.5
1584 * seconds and there is data in the transmit queue, thus we
1585 * asume the card is stuck.
1586 */
1587 if (*ap->tx_csm != ap->tx_ret_csm) {
1588 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1589 dev->name, (unsigned int)readl(&regs->HostCtrl));
1590 /* This can happen due to ieee flow control. */
1591 } else {
1592 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1593 dev->name);
1594#if 0
1595 netif_wake_queue(dev);
1596#endif
1597 }
1598}
1599
1600
1601static void ace_tasklet(unsigned long dev)
1602{
1603 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1604 int cur_size;
1605
1606 cur_size = atomic_read(&ap->cur_rx_bufs);
1607 if ((cur_size < RX_LOW_STD_THRES) &&
1608 !test_and_set_bit(0, &ap->std_refill_busy)) {
1609#ifdef DEBUG
1610 printk("refilling buffers (current %i)\n", cur_size);
1611#endif
1612 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1613 }
1614
1615 if (ap->version >= 2) {
1616 cur_size = atomic_read(&ap->cur_mini_bufs);
1617 if ((cur_size < RX_LOW_MINI_THRES) &&
1618 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1619#ifdef DEBUG
1620 printk("refilling mini buffers (current %i)\n",
1621 cur_size);
1622#endif
1623 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1624 }
1625 }
1626
1627 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1628 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1629 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1630#ifdef DEBUG
1631 printk("refilling jumbo buffers (current %i)\n", cur_size);
1632#endif
1633 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1634 }
1635 ap->tasklet_pending = 0;
1636}
1637
1638
1639/*
1640 * Copy the contents of the NIC's trace buffer to kernel memory.
1641 */
1642static void ace_dump_trace(struct ace_private *ap)
1643{
1644#if 0
1645 if (!ap->trace_buf)
1646 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1647 return;
1648#endif
1649}
1650
1651
1652/*
1653 * Load the standard rx ring.
1654 *
1655 * Loading rings is safe without holding the spin lock since this is
1656 * done only before the device is enabled, thus no interrupts are
1657 * generated and by the interrupt handler/tasklet handler.
1658 */
1659static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1660{
1661 struct ace_regs __iomem *regs = ap->regs;
1662 short i, idx;
6aa20a22 1663
1da177e4
LT		 1664
1665 prefetchw(&ap->cur_rx_bufs);
1666
1667 idx = ap->rx_std_skbprd;
1668
1669 for (i = 0; i < nr_bufs; i++) {
1670 struct sk_buff *skb;
1671 struct rx_desc *rd;
1672 dma_addr_t mapping;
1673
1674 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1675 if (!skb)
1676 break;
1677
1678 skb_reserve(skb, NET_IP_ALIGN);
1679 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1680 offset_in_page(skb->data),
1681 ACE_STD_BUFSIZE,
1682 PCI_DMA_FROMDEVICE);
1683 ap->skb->rx_std_skbuff[idx].skb = skb;
1684 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1685 mapping, mapping);
1686
1687 rd = &ap->rx_std_ring[idx];
1688 set_aceaddr(&rd->addr, mapping);
1689 rd->size = ACE_STD_BUFSIZE;
1690 rd->idx = idx;
1691 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1692 }
1693
1694 if (!i)
1695 goto error_out;
1696
1697 atomic_add(i, &ap->cur_rx_bufs);
1698 ap->rx_std_skbprd = idx;
1699
1700 if (ACE_IS_TIGON_I(ap)) {
1701 struct cmd cmd;
1702 cmd.evt = C_SET_RX_PRD_IDX;
1703 cmd.code = 0;
1704 cmd.idx = ap->rx_std_skbprd;
1705 ace_issue_cmd(regs, &cmd);
1706 } else {
1707 writel(idx, &regs->RxStdPrd);
1708 wmb();
1709 }
1710
1711 out:
1712 clear_bit(0, &ap->std_refill_busy);
1713 return;
1714
1715 error_out:
1716 printk(KERN_INFO "Out of memory when allocating "
1717 "standard receive buffers\n");
1718 goto out;
1719}
1720
1721
1722static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1723{
1724 struct ace_regs __iomem *regs = ap->regs;
1725 short i, idx;
1726
1727 prefetchw(&ap->cur_mini_bufs);
1728
1729 idx = ap->rx_mini_skbprd;
1730 for (i = 0; i < nr_bufs; i++) {
1731 struct sk_buff *skb;
1732 struct rx_desc *rd;
1733 dma_addr_t mapping;
1734
1735 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1736 if (!skb)
1737 break;
1738
1739 skb_reserve(skb, NET_IP_ALIGN);
1740 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1741 offset_in_page(skb->data),
1742 ACE_MINI_BUFSIZE,
1743 PCI_DMA_FROMDEVICE);
1744 ap->skb->rx_mini_skbuff[idx].skb = skb;
1745 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1746 mapping, mapping);
1747
1748 rd = &ap->rx_mini_ring[idx];
1749 set_aceaddr(&rd->addr, mapping);
1750 rd->size = ACE_MINI_BUFSIZE;
1751 rd->idx = idx;
1752 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1753 }
1754
1755 if (!i)
1756 goto error_out;
1757
1758 atomic_add(i, &ap->cur_mini_bufs);
1759
1760 ap->rx_mini_skbprd = idx;
1761
1762 writel(idx, &regs->RxMiniPrd);
1763 wmb();
1764
1765 out:
1766 clear_bit(0, &ap->mini_refill_busy);
1767 return;
1768 error_out:
1769 printk(KERN_INFO "Out of memory when allocating "
1770 "mini receive buffers\n");
1771 goto out;
1772}
1773
1774
1775/*
1776 * Load the jumbo rx ring, this may happen at any time if the MTU
1777 * is changed to a value > 1500.
1778 */
1779static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1780{
1781 struct ace_regs __iomem *regs = ap->regs;
1782 short i, idx;
1783
1784 idx = ap->rx_jumbo_skbprd;
1785
1786 for (i = 0; i < nr_bufs; i++) {
1787 struct sk_buff *skb;
1788 struct rx_desc *rd;
1789 dma_addr_t mapping;
1790
1791 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1792 if (!skb)
1793 break;
1794
1795 skb_reserve(skb, NET_IP_ALIGN);
1796 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1797 offset_in_page(skb->data),
1798 ACE_JUMBO_BUFSIZE,
1799 PCI_DMA_FROMDEVICE);
1800 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1801 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1802 mapping, mapping);
1803
1804 rd = &ap->rx_jumbo_ring[idx];
1805 set_aceaddr(&rd->addr, mapping);
1806 rd->size = ACE_JUMBO_BUFSIZE;
1807 rd->idx = idx;
1808 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1809 }
1810
1811 if (!i)
1812 goto error_out;
1813
1814 atomic_add(i, &ap->cur_jumbo_bufs);
1815 ap->rx_jumbo_skbprd = idx;
1816
1817 if (ACE_IS_TIGON_I(ap)) {
1818 struct cmd cmd;
1819 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1820 cmd.code = 0;
1821 cmd.idx = ap->rx_jumbo_skbprd;
1822 ace_issue_cmd(regs, &cmd);
1823 } else {
1824 writel(idx, &regs->RxJumboPrd);
1825 wmb();
1826 }
1827
1828 out:
1829 clear_bit(0, &ap->jumbo_refill_busy);
1830 return;
1831 error_out:
1832 if (net_ratelimit())
1833 printk(KERN_INFO "Out of memory when allocating "
1834 "jumbo receive buffers\n");
1835 goto out;
1836}
1837
1838
1839/*
1840 * All events are considered to be slow (RX/TX ints do not generate
1841 * events) and are handled here, outside the main interrupt handler,
1842 * to reduce the size of the handler.
1843 */
1844static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1845{
1846 struct ace_private *ap;
1847
1848 ap = netdev_priv(dev);
1849
1850 while (evtcsm != evtprd) {
1851 switch (ap->evt_ring[evtcsm].evt) {
1852 case E_FW_RUNNING:
1853 printk(KERN_INFO "%s: Firmware up and running\n",
1854 ap->name);
1855 ap->fw_running = 1;
1856 wmb();
1857 break;
1858 case E_STATS_UPDATED:
1859 break;
1860 case E_LNK_STATE:
1861 {
1862 u16 code = ap->evt_ring[evtcsm].code;
1863 switch (code) {
1864 case E_C_LINK_UP:
1865 {
1866 u32 state = readl(&ap->regs->GigLnkState);
1867 printk(KERN_WARNING "%s: Optical link UP "
1868 "(%s Duplex, Flow Control: %s%s)\n",
1869 ap->name,
1870 state & LNK_FULL_DUPLEX ? "Full":"Half",
1871 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1872 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1873 break;
1874 }
1875 case E_C_LINK_DOWN:
1876 printk(KERN_WARNING "%s: Optical link DOWN\n",
1877 ap->name);
1878 break;
1879 case E_C_LINK_10_100:
1880 printk(KERN_WARNING "%s: 10/100BaseT link "
1881 "UP\n", ap->name);
1882 break;
1883 default:
1884 printk(KERN_ERR "%s: Unknown optical link "
1885 "state %02x\n", ap->name, code);
1886 }
1887 break;
1888 }
1889 case E_ERROR:
1890 switch(ap->evt_ring[evtcsm].code) {
1891 case E_C_ERR_INVAL_CMD:
1892 printk(KERN_ERR "%s: invalid command error\n",
1893 ap->name);
1894 break;
1895 case E_C_ERR_UNIMP_CMD:
1896 printk(KERN_ERR "%s: unimplemented command "
1897 "error\n", ap->name);
1898 break;
1899 case E_C_ERR_BAD_CFG:
1900 printk(KERN_ERR "%s: bad config error\n",
1901 ap->name);
1902 break;
1903 default:
1904 printk(KERN_ERR "%s: unknown error %02x\n",
1905 ap->name, ap->evt_ring[evtcsm].code);
1906 }
1907 break;
1908 case E_RESET_JUMBO_RNG:
1909 {
1910 int i;
1911 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1912 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1913 ap->rx_jumbo_ring[i].size = 0;
1914 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1915 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1916 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1917 }
1918 }
1919
1920 if (ACE_IS_TIGON_I(ap)) {
1921 struct cmd cmd;
1922 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1923 cmd.code = 0;
1924 cmd.idx = 0;
1925 ace_issue_cmd(ap->regs, &cmd);
1926 } else {
1927 writel(0, &((ap->regs)->RxJumboPrd));
1928 wmb();
1929 }
1930
1931 ap->jumbo = 0;
1932 ap->rx_jumbo_skbprd = 0;
1933 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1934 ap->name);
1935 clear_bit(0, &ap->jumbo_refill_busy);
1936 break;
1937 }
1938 default:
1939 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1940 ap->name, ap->evt_ring[evtcsm].evt);
1941 }
1942 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1943 }
1944
1945 return evtcsm;
1946}
1947
1948
1949static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1950{
1951 struct ace_private *ap = netdev_priv(dev);
1952 u32 idx;
1953 int mini_count = 0, std_count = 0;
1954
1955 idx = rxretcsm;
1956
1957 prefetchw(&ap->cur_rx_bufs);
1958 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1959
1da177e4
LT		 1960 while (idx != rxretprd) {
1961 struct ring_info *rip;
1962 struct sk_buff *skb;
1963 struct rx_desc *rxdesc, *retdesc;
1964 u32 skbidx;
1965 int bd_flags, desc_type, mapsize;
1966 u16 csum;
1967
1968
1969 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1970 if (idx == rxretcsm)
1da177e4
LT		 1971 rmb();
1972
1973 retdesc = &ap->rx_return_ring[idx];
1974 skbidx = retdesc->idx;
1975 bd_flags = retdesc->flags;
1976 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1977
1978 switch(desc_type) {
1979 /*
1980 * Normal frames do not have any flags set
1981 *
1982 * Mini and normal frames arrive frequently,
1983 * so use a local counter to avoid doing
1984 * atomic operations for each packet arriving.
1985 */
1986 case 0:
1987 rip = &ap->skb->rx_std_skbuff[skbidx];
1988 mapsize = ACE_STD_BUFSIZE;
1989 rxdesc = &ap->rx_std_ring[skbidx];
1990 std_count++;
1991 break;
1992 case BD_FLG_JUMBO:
1993 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1994 mapsize = ACE_JUMBO_BUFSIZE;
1995 rxdesc = &ap->rx_jumbo_ring[skbidx];
1996 atomic_dec(&ap->cur_jumbo_bufs);
1997 break;
1998 case BD_FLG_MINI:
1999 rip = &ap->skb->rx_mini_skbuff[skbidx];
2000 mapsize = ACE_MINI_BUFSIZE;
2001 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 2002 mini_count++;
1da177e4
LT		 2003 break;
2004 default:
2005 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2006 "returned by NIC\n", dev->name,
2007 retdesc->flags);
2008 goto error;
2009 }
2010
2011 skb = rip->skb;
2012 rip->skb = NULL;
2013 pci_unmap_page(ap->pdev,
2014 pci_unmap_addr(rip, mapping),
2015 mapsize,
2016 PCI_DMA_FROMDEVICE);
2017 skb_put(skb, retdesc->size);
2018
2019 /*
2020 * Fly baby, fly!
2021 */
2022 csum = retdesc->tcp_udp_csum;
2023
1da177e4
LT		 2024 skb->protocol = eth_type_trans(skb, dev);
2025
2026 /*
2027 * Instead of forcing the poor tigon mips cpu to calculate
2028 * pseudo hdr checksum, we do this ourselves.
2029 */
2030 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2031 skb->csum = htons(csum);
84fa7933 2032 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2033 } else {
2034 skb->ip_summed = CHECKSUM_NONE;
2035 }
2036
2037 /* send it up */
2038#if ACENIC_DO_VLAN
2039 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2040 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2041 } else
2042#endif
2043 netif_rx(skb);
2044
966e37bc
PZ		 2045 dev->stats.rx_packets++;
2046 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2047
2048 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2049 }
2050
2051 atomic_sub(std_count, &ap->cur_rx_bufs);
2052 if (!ACE_IS_TIGON_I(ap))
2053 atomic_sub(mini_count, &ap->cur_mini_bufs);
2054
2055 out:
2056 /*
2057 * According to the documentation RxRetCsm is obsolete with
2058 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2059 */
2060 if (ACE_IS_TIGON_I(ap)) {
2061 writel(idx, &ap->regs->RxRetCsm);
2062 }
2063 ap->cur_rx = idx;
2064
2065 return;
2066 error:
2067 idx = rxretprd;
2068 goto out;
2069}
2070
2071
2072static inline void ace_tx_int(struct net_device *dev,
2073 u32 txcsm, u32 idx)
2074{
2075 struct ace_private *ap = netdev_priv(dev);
2076
2077 do {
2078 struct sk_buff *skb;
2079 dma_addr_t mapping;
2080 struct tx_ring_info *info;
2081
2082 info = ap->skb->tx_skbuff + idx;
2083 skb = info->skb;
2084 mapping = pci_unmap_addr(info, mapping);
2085
2086 if (mapping) {
2087 pci_unmap_page(ap->pdev, mapping,
2088 pci_unmap_len(info, maplen),
2089 PCI_DMA_TODEVICE);
2090 pci_unmap_addr_set(info, mapping, 0);
2091 }
2092
2093 if (skb) {
966e37bc
PZ		 2094 dev->stats.tx_packets++;
2095 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2096 dev_kfree_skb_irq(skb);
2097 info->skb = NULL;
2098 }
2099
2100 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2101 } while (idx != txcsm);
2102
2103 if (netif_queue_stopped(dev))
2104 netif_wake_queue(dev);
2105
2106 wmb();
2107 ap->tx_ret_csm = txcsm;
2108
2109 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2110 *
2111 * We could try to make it before. In this case we would get
2112 * the following race condition: hard_start_xmit on other cpu
2113 * enters after we advanced tx_ret_csm and fills space,
2114 * which we have just freed, so that we make illegal device wakeup.
2115 * There is no good way to workaround this (at entry
2116 * to ace_start_xmit detects this condition and prevents
2117 * ring corruption, but it is not a good workaround.)
2118 *
2119 * When tx_ret_csm is advanced after, we wake up device _only_
2120 * if we really have some space in ring (though the core doing
2121 * hard_start_xmit can see full ring for some period and has to
2122 * synchronize.) Superb.
2123 * BUT! We get another subtle race condition. hard_start_xmit
2124 * may think that ring is full between wakeup and advancing
2125 * tx_ret_csm and will stop device instantly! It is not so bad.
2126 * We are guaranteed that there is something in ring, so that
2127 * the next irq will resume transmission. To speedup this we could
2128 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2129 * (see ace_start_xmit).
2130 *
2131 * Well, this dilemma exists in all lock-free devices.
2132 * We, following scheme used in drivers by Donald Becker,
2133 * select the least dangerous.
2134 * --ANK
2135 */
2136}
2137
2138
7d12e780 2139static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2140{
2141 struct net_device *dev = (struct net_device *)dev_id;
2142 struct ace_private *ap = netdev_priv(dev);
2143 struct ace_regs __iomem *regs = ap->regs;
2144 u32 idx;
2145 u32 txcsm, rxretcsm, rxretprd;
2146 u32 evtcsm, evtprd;
2147
2148 /*
2149 * In case of PCI shared interrupts or spurious interrupts,
2150 * we want to make sure it is actually our interrupt before
2151 * spending any time in here.
2152 */
2153 if (!(readl(&regs->HostCtrl) & IN_INT))
2154 return IRQ_NONE;
2155
2156 /*
2157 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2158 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2159 * writel(0, &regs->Mb0Lo).
2160 *
2161 * "IRQ avoidance" recommended in docs applies to IRQs served
2162 * threads and it is wrong even for that case.
2163 */
2164 writel(0, &regs->Mb0Lo);
2165 readl(&regs->Mb0Lo);
2166
2167 /*
2168 * There is no conflict between transmit handling in
2169 * start_xmit and receive processing, thus there is no reason
2170 * to take a spin lock for RX handling. Wait until we start
2171 * working on the other stuff - hey we don't need a spin lock
2172 * anymore.
2173 */
2174 rxretprd = *ap->rx_ret_prd;
2175 rxretcsm = ap->cur_rx;
2176
2177 if (rxretprd != rxretcsm)
2178 ace_rx_int(dev, rxretprd, rxretcsm);
2179
2180 txcsm = *ap->tx_csm;
2181 idx = ap->tx_ret_csm;
2182
2183 if (txcsm != idx) {
2184 /*
2185 * If each skb takes only one descriptor this check degenerates
2186 * to identity, because new space has just been opened.
2187 * But if skbs are fragmented we must check that this index
2188 * update releases enough of space, otherwise we just
2189 * wait for device to make more work.
2190 */
2191 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2192 ace_tx_int(dev, txcsm, idx);
2193 }
2194
2195 evtcsm = readl(&regs->EvtCsm);
2196 evtprd = *ap->evt_prd;
2197
2198 if (evtcsm != evtprd) {
2199 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2200 writel(evtcsm, &regs->EvtCsm);
2201 }
2202
2203 /*
2204 * This has to go last in the interrupt handler and run with
2205 * the spin lock released ... what lock?
2206 */
2207 if (netif_running(dev)) {
2208 int cur_size;
2209 int run_tasklet = 0;
2210
2211 cur_size = atomic_read(&ap->cur_rx_bufs);
2212 if (cur_size < RX_LOW_STD_THRES) {
2213 if ((cur_size < RX_PANIC_STD_THRES) &&
2214 !test_and_set_bit(0, &ap->std_refill_busy)) {
2215#ifdef DEBUG
2216 printk("low on std buffers %i\n", cur_size);
2217#endif
2218 ace_load_std_rx_ring(ap,
2219 RX_RING_SIZE - cur_size);
2220 } else
2221 run_tasklet = 1;
2222 }
2223
2224 if (!ACE_IS_TIGON_I(ap)) {
2225 cur_size = atomic_read(&ap->cur_mini_bufs);
2226 if (cur_size < RX_LOW_MINI_THRES) {
2227 if ((cur_size < RX_PANIC_MINI_THRES) &&
2228 !test_and_set_bit(0,
2229 &ap->mini_refill_busy)) {
2230#ifdef DEBUG
2231 printk("low on mini buffers %i\n",
2232 cur_size);
2233#endif
2234 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2235 } else
2236 run_tasklet = 1;
2237 }
2238 }
2239
2240 if (ap->jumbo) {
2241 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2242 if (cur_size < RX_LOW_JUMBO_THRES) {
2243 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2244 !test_and_set_bit(0,
2245 &ap->jumbo_refill_busy)){
2246#ifdef DEBUG
2247 printk("low on jumbo buffers %i\n",
2248 cur_size);
2249#endif
2250 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2251 } else
2252 run_tasklet = 1;
2253 }
2254 }
2255 if (run_tasklet && !ap->tasklet_pending) {
2256 ap->tasklet_pending = 1;
2257 tasklet_schedule(&ap->ace_tasklet);
2258 }
2259 }
2260
2261 return IRQ_HANDLED;
2262}
2263
2264
2265#if ACENIC_DO_VLAN
2266static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2267{
2268 struct ace_private *ap = netdev_priv(dev);
2269 unsigned long flags;
2270
2271 local_irq_save(flags);
2272 ace_mask_irq(dev);
2273
2274 ap->vlgrp = grp;
2275
2276 ace_unmask_irq(dev);
2277 local_irq_restore(flags);
2278}
1da177e4
LT		 2279#endif /* ACENIC_DO_VLAN */
2280
2281
2282static int ace_open(struct net_device *dev)
2283{
2284 struct ace_private *ap = netdev_priv(dev);
2285 struct ace_regs __iomem *regs = ap->regs;
2286 struct cmd cmd;
2287
2288 if (!(ap->fw_running)) {
2289 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2290 return -EBUSY;
2291 }
2292
2293 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2294
2295 cmd.evt = C_CLEAR_STATS;
2296 cmd.code = 0;
2297 cmd.idx = 0;
2298 ace_issue_cmd(regs, &cmd);
2299
2300 cmd.evt = C_HOST_STATE;
2301 cmd.code = C_C_STACK_UP;
2302 cmd.idx = 0;
2303 ace_issue_cmd(regs, &cmd);
2304
2305 if (ap->jumbo &&
2306 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2307 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2308
2309 if (dev->flags & IFF_PROMISC) {
2310 cmd.evt = C_SET_PROMISC_MODE;
2311 cmd.code = C_C_PROMISC_ENABLE;
2312 cmd.idx = 0;
2313 ace_issue_cmd(regs, &cmd);
2314
2315 ap->promisc = 1;
2316 }else
2317 ap->promisc = 0;
2318 ap->mcast_all = 0;
2319
2320#if 0
2321 cmd.evt = C_LNK_NEGOTIATION;
2322 cmd.code = 0;
2323 cmd.idx = 0;
2324 ace_issue_cmd(regs, &cmd);
2325#endif
2326
2327 netif_start_queue(dev);
2328
2329 /*
2330 * Setup the bottom half rx ring refill handler
2331 */
2332 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2333 return 0;
2334}
2335
2336
2337static int ace_close(struct net_device *dev)
2338{
2339 struct ace_private *ap = netdev_priv(dev);
2340 struct ace_regs __iomem *regs = ap->regs;
2341 struct cmd cmd;
2342 unsigned long flags;
2343 short i;
2344
2345 /*
2346 * Without (or before) releasing irq and stopping hardware, this
2347 * is an absolute non-sense, by the way. It will be reset instantly
2348 * by the first irq.
2349 */
2350 netif_stop_queue(dev);
2351
6aa20a22 2352
1da177e4
LT		 2353 if (ap->promisc) {
2354 cmd.evt = C_SET_PROMISC_MODE;
2355 cmd.code = C_C_PROMISC_DISABLE;
2356 cmd.idx = 0;
2357 ace_issue_cmd(regs, &cmd);
2358 ap->promisc = 0;
2359 }
2360
2361 cmd.evt = C_HOST_STATE;
2362 cmd.code = C_C_STACK_DOWN;
2363 cmd.idx = 0;
2364 ace_issue_cmd(regs, &cmd);
2365
2366 tasklet_kill(&ap->ace_tasklet);
2367
2368 /*
2369 * Make sure one CPU is not processing packets while
2370 * buffers are being released by another.
2371 */
2372
2373 local_irq_save(flags);
2374 ace_mask_irq(dev);
2375
2376 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2377 struct sk_buff *skb;
2378 dma_addr_t mapping;
2379 struct tx_ring_info *info;
2380
2381 info = ap->skb->tx_skbuff + i;
2382 skb = info->skb;
2383 mapping = pci_unmap_addr(info, mapping);
2384
2385 if (mapping) {
2386 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2387 /* NB: TIGON_1 is special, tx_ring is in io space */
2388 struct tx_desc __iomem *tx;
2389 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2390 writel(0, &tx->addr.addrhi);
2391 writel(0, &tx->addr.addrlo);
2392 writel(0, &tx->flagsize);
2393 } else
2394 memset(ap->tx_ring + i, 0,
2395 sizeof(struct tx_desc));
2396 pci_unmap_page(ap->pdev, mapping,
2397 pci_unmap_len(info, maplen),
2398 PCI_DMA_TODEVICE);
2399 pci_unmap_addr_set(info, mapping, 0);
2400 }
2401 if (skb) {
2402 dev_kfree_skb(skb);
2403 info->skb = NULL;
2404 }
2405 }
2406
2407 if (ap->jumbo) {
2408 cmd.evt = C_RESET_JUMBO_RNG;
2409 cmd.code = 0;
2410 cmd.idx = 0;
2411 ace_issue_cmd(regs, &cmd);
2412 }
2413
2414 ace_unmask_irq(dev);
2415 local_irq_restore(flags);
2416
2417 return 0;
2418}
2419
2420
2421static inline dma_addr_t
2422ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2423 struct sk_buff *tail, u32 idx)
2424{
2425 dma_addr_t mapping;
2426 struct tx_ring_info *info;
2427
2428 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2429 offset_in_page(skb->data),
2430 skb->len, PCI_DMA_TODEVICE);
2431
2432 info = ap->skb->tx_skbuff + idx;
2433 info->skb = tail;
2434 pci_unmap_addr_set(info, mapping, mapping);
2435 pci_unmap_len_set(info, maplen, skb->len);
2436 return mapping;
2437}
2438
2439
2440static inline void
2441ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2442 u32 flagsize, u32 vlan_tag)
2443{
2444#if !USE_TX_COAL_NOW
2445 flagsize &= ~BD_FLG_COAL_NOW;
2446#endif
2447
2448 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2449 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2450 writel(addr >> 32, &io->addr.addrhi);
2451 writel(addr & 0xffffffff, &io->addr.addrlo);
2452 writel(flagsize, &io->flagsize);
2453#if ACENIC_DO_VLAN
2454 writel(vlan_tag, &io->vlanres);
2455#endif
2456 } else {
2457 desc->addr.addrhi = addr >> 32;
2458 desc->addr.addrlo = addr;
2459 desc->flagsize = flagsize;
2460#if ACENIC_DO_VLAN
2461 desc->vlanres = vlan_tag;
2462#endif
2463 }
2464}
2465
2466
2467static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
2468{
2469 struct ace_private *ap = netdev_priv(dev);
2470 struct ace_regs __iomem *regs = ap->regs;
2471 struct tx_desc *desc;
2472 u32 idx, flagsize;
2473 unsigned long maxjiff = jiffies + 3*HZ;
2474
2475restart:
2476 idx = ap->tx_prd;
2477
2478 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2479 goto overflow;
2480
2481 if (!skb_shinfo(skb)->nr_frags) {
2482 dma_addr_t mapping;
2483 u32 vlan_tag = 0;
2484
2485 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2486 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2487 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2488 flagsize |= BD_FLG_TCP_UDP_SUM;
2489#if ACENIC_DO_VLAN
2490 if (vlan_tx_tag_present(skb)) {
2491 flagsize |= BD_FLG_VLAN_TAG;
2492 vlan_tag = vlan_tx_tag_get(skb);
2493 }
2494#endif
2495 desc = ap->tx_ring + idx;
2496 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2497
2498 /* Look at ace_tx_int for explanations. */
2499 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2500 flagsize |= BD_FLG_COAL_NOW;
2501
2502 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2503 } else {
2504 dma_addr_t mapping;
2505 u32 vlan_tag = 0;
2506 int i, len = 0;
2507
2508 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2509 flagsize = (skb_headlen(skb) << 16);
84fa7933 2510 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2511 flagsize |= BD_FLG_TCP_UDP_SUM;
2512#if ACENIC_DO_VLAN
2513 if (vlan_tx_tag_present(skb)) {
2514 flagsize |= BD_FLG_VLAN_TAG;
2515 vlan_tag = vlan_tx_tag_get(skb);
2516 }
2517#endif
2518
2519 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2520
2521 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2522
2523 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2524 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2525 struct tx_ring_info *info;
2526
2527 len += frag->size;
2528 info = ap->skb->tx_skbuff + idx;
2529 desc = ap->tx_ring + idx;
2530
2531 mapping = pci_map_page(ap->pdev, frag->page,
2532 frag->page_offset, frag->size,
2533 PCI_DMA_TODEVICE);
2534
2535 flagsize = (frag->size << 16);
84fa7933 2536 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2537 flagsize |= BD_FLG_TCP_UDP_SUM;
2538 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2539
2540 if (i == skb_shinfo(skb)->nr_frags - 1) {
2541 flagsize |= BD_FLG_END;
2542 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2543 flagsize |= BD_FLG_COAL_NOW;
2544
2545 /*
2546 * Only the last fragment frees
2547 * the skb!
2548 */
2549 info->skb = skb;
2550 } else {
2551 info->skb = NULL;
2552 }
2553 pci_unmap_addr_set(info, mapping, mapping);
2554 pci_unmap_len_set(info, maplen, frag->size);
2555 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2556 }
2557 }
2558
2559 wmb();
2560 ap->tx_prd = idx;
2561 ace_set_txprd(regs, ap, idx);
2562
2563 if (flagsize & BD_FLG_COAL_NOW) {
2564 netif_stop_queue(dev);
2565
2566 /*
2567 * A TX-descriptor producer (an IRQ) might have gotten
2568 * inbetween, making the ring free again. Since xmit is
2569 * serialized, this is the only situation we have to
2570 * re-test.
2571 */
2572 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2573 netif_wake_queue(dev);
2574 }
2575
2576 dev->trans_start = jiffies;
2577 return NETDEV_TX_OK;
2578
2579overflow:
2580 /*
2581 * This race condition is unavoidable with lock-free drivers.
2582 * We wake up the queue _before_ tx_prd is advanced, so that we can
2583 * enter hard_start_xmit too early, while tx ring still looks closed.
2584 * This happens ~1-4 times per 100000 packets, so that we can allow
2585 * to loop syncing to other CPU. Probably, we need an additional
2586 * wmb() in ace_tx_intr as well.
2587 *
2588 * Note that this race is relieved by reserving one more entry
2589 * in tx ring than it is necessary (see original non-SG driver).
2590 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2591 * is already overkill.
2592 *
2593 * Alternative is to return with 1 not throttling queue. In this
2594 * case loop becomes longer, no more useful effects.
2595 */
2596 if (time_before(jiffies, maxjiff)) {
2597 barrier();
2598 cpu_relax();
2599 goto restart;
2600 }
6aa20a22 2601
1da177e4
LT		 2602 /* The ring is stuck full. */
2603 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2604 return NETDEV_TX_BUSY;
2605}
2606
2607
2608static int ace_change_mtu(struct net_device *dev, int new_mtu)
2609{
2610 struct ace_private *ap = netdev_priv(dev);
2611 struct ace_regs __iomem *regs = ap->regs;
2612
2613 if (new_mtu > ACE_JUMBO_MTU)
2614 return -EINVAL;
2615
2616 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2617 dev->mtu = new_mtu;
2618
2619 if (new_mtu > ACE_STD_MTU) {
2620 if (!(ap->jumbo)) {
2621 printk(KERN_INFO "%s: Enabling Jumbo frame "
2622 "support\n", dev->name);
2623 ap->jumbo = 1;
2624 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2625 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2626 ace_set_rxtx_parms(dev, 1);
2627 }
2628 } else {
2629 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2630 ace_sync_irq(dev->irq);
2631 ace_set_rxtx_parms(dev, 0);
2632 if (ap->jumbo) {
2633 struct cmd cmd;
2634
2635 cmd.evt = C_RESET_JUMBO_RNG;
2636 cmd.code = 0;
2637 cmd.idx = 0;
2638 ace_issue_cmd(regs, &cmd);
2639 }
2640 }
2641
2642 return 0;
2643}
2644
2645static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2646{
2647 struct ace_private *ap = netdev_priv(dev);
2648 struct ace_regs __iomem *regs = ap->regs;
2649 u32 link;
2650
2651 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2652 ecmd->supported =
2653 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2654 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2655 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2656 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2657
2658 ecmd->port = PORT_FIBRE;
2659 ecmd->transceiver = XCVR_INTERNAL;
2660
2661 link = readl(&regs->GigLnkState);
2662 if (link & LNK_1000MB)
2663 ecmd->speed = SPEED_1000;
2664 else {
2665 link = readl(&regs->FastLnkState);
2666 if (link & LNK_100MB)
2667 ecmd->speed = SPEED_100;
2668 else if (link & LNK_10MB)
2669 ecmd->speed = SPEED_10;
2670 else
2671 ecmd->speed = 0;
2672 }
2673 if (link & LNK_FULL_DUPLEX)
2674 ecmd->duplex = DUPLEX_FULL;
2675 else
2676 ecmd->duplex = DUPLEX_HALF;
2677
2678 if (link & LNK_NEGOTIATE)
2679 ecmd->autoneg = AUTONEG_ENABLE;
2680 else
2681 ecmd->autoneg = AUTONEG_DISABLE;
2682
2683#if 0
2684 /*
2685 * Current struct ethtool_cmd is insufficient
2686 */
2687 ecmd->trace = readl(&regs->TuneTrace);
2688
2689 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2690 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2691#endif
2692 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2693 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2694
2695 return 0;
2696}
2697
2698static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2699{
2700 struct ace_private *ap = netdev_priv(dev);
2701 struct ace_regs __iomem *regs = ap->regs;
2702 u32 link, speed;
2703
2704 link = readl(&regs->GigLnkState);
2705 if (link & LNK_1000MB)
2706 speed = SPEED_1000;
2707 else {
2708 link = readl(&regs->FastLnkState);
2709 if (link & LNK_100MB)
2710 speed = SPEED_100;
2711 else if (link & LNK_10MB)
2712 speed = SPEED_10;
2713 else
2714 speed = SPEED_100;
2715 }
2716
2717 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2718 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2719 if (!ACE_IS_TIGON_I(ap))
2720 link |= LNK_TX_FLOW_CTL_Y;
2721 if (ecmd->autoneg == AUTONEG_ENABLE)
2722 link |= LNK_NEGOTIATE;
2723 if (ecmd->speed != speed) {
2724 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2725 switch (speed) {
2726 case SPEED_1000:
2727 link |= LNK_1000MB;
2728 break;
2729 case SPEED_100:
2730 link |= LNK_100MB;
2731 break;
2732 case SPEED_10:
2733 link |= LNK_10MB;
2734 break;
2735 }
2736 }
2737
2738 if (ecmd->duplex == DUPLEX_FULL)
2739 link |= LNK_FULL_DUPLEX;
2740
2741 if (link != ap->link) {
2742 struct cmd cmd;
2743 printk(KERN_INFO "%s: Renegotiating link state\n",
2744 dev->name);
2745
2746 ap->link = link;
2747 writel(link, &regs->TuneLink);
2748 if (!ACE_IS_TIGON_I(ap))
2749 writel(link, &regs->TuneFastLink);
2750 wmb();
2751
2752 cmd.evt = C_LNK_NEGOTIATION;
2753 cmd.code = 0;
2754 cmd.idx = 0;
2755 ace_issue_cmd(regs, &cmd);
2756 }
2757 return 0;
2758}
2759
6aa20a22 2760static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2761 struct ethtool_drvinfo *info)
2762{
2763 struct ace_private *ap = netdev_priv(dev);
2764
2765 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2766 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2767 ap->firmware_major, ap->firmware_minor,
2768 ap->firmware_fix);
1da177e4
LT		 2769
2770 if (ap->pdev)
6aa20a22 2771 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2772 sizeof(info->bus_info));
2773
2774}
2775
2776/*
2777 * Set the hardware MAC address.
2778 */
2779static int ace_set_mac_addr(struct net_device *dev, void *p)
2780{
2781 struct ace_private *ap = netdev_priv(dev);
2782 struct ace_regs __iomem *regs = ap->regs;
2783 struct sockaddr *addr=p;
2784 u8 *da;
2785 struct cmd cmd;
2786
2787 if(netif_running(dev))
2788 return -EBUSY;
2789
2790 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2791
2792 da = (u8 *)dev->dev_addr;
2793
2794 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2795 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2796 &regs->MacAddrLo);
2797
2798 cmd.evt = C_SET_MAC_ADDR;
2799 cmd.code = 0;
2800 cmd.idx = 0;
2801 ace_issue_cmd(regs, &cmd);
2802
2803 return 0;
2804}
2805
2806
2807static void ace_set_multicast_list(struct net_device *dev)
2808{
2809 struct ace_private *ap = netdev_priv(dev);
2810 struct ace_regs __iomem *regs = ap->regs;
2811 struct cmd cmd;
2812
2813 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2814 cmd.evt = C_SET_MULTICAST_MODE;
2815 cmd.code = C_C_MCAST_ENABLE;
2816 cmd.idx = 0;
2817 ace_issue_cmd(regs, &cmd);
2818 ap->mcast_all = 1;
2819 } else if (ap->mcast_all) {
2820 cmd.evt = C_SET_MULTICAST_MODE;
2821 cmd.code = C_C_MCAST_DISABLE;
2822 cmd.idx = 0;
2823 ace_issue_cmd(regs, &cmd);
2824 ap->mcast_all = 0;
2825 }
2826
2827 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2828 cmd.evt = C_SET_PROMISC_MODE;
2829 cmd.code = C_C_PROMISC_ENABLE;
2830 cmd.idx = 0;
2831 ace_issue_cmd(regs, &cmd);
2832 ap->promisc = 1;
2833 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2834 cmd.evt = C_SET_PROMISC_MODE;
2835 cmd.code = C_C_PROMISC_DISABLE;
2836 cmd.idx = 0;
2837 ace_issue_cmd(regs, &cmd);
2838 ap->promisc = 0;
2839 }
2840
2841 /*
2842 * For the time being multicast relies on the upper layers
2843 * filtering it properly. The Firmware does not allow one to
2844 * set the entire multicast list at a time and keeping track of
2845 * it here is going to be messy.
2846 */
2847 if ((dev->mc_count) && !(ap->mcast_all)) {
2848 cmd.evt = C_SET_MULTICAST_MODE;
2849 cmd.code = C_C_MCAST_ENABLE;
2850 cmd.idx = 0;
2851 ace_issue_cmd(regs, &cmd);
2852 }else if (!ap->mcast_all) {
2853 cmd.evt = C_SET_MULTICAST_MODE;
2854 cmd.code = C_C_MCAST_DISABLE;
2855 cmd.idx = 0;
2856 ace_issue_cmd(regs, &cmd);
2857 }
2858}
2859
2860
2861static struct net_device_stats *ace_get_stats(struct net_device *dev)
2862{
2863 struct ace_private *ap = netdev_priv(dev);
2864 struct ace_mac_stats __iomem *mac_stats =
2865 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2866
966e37bc
PZ		 2867 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2868 dev->stats.multicast = readl(&mac_stats->kept_mc);
2869 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2870
966e37bc 2871 return &dev->stats;
1da177e4
LT		 2872}
2873
2874
949b4254
JS		 2875static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2876 u32 dest, int size)
1da177e4
LT		 2877{
2878 void __iomem *tdest;
1da177e4
LT		 2879 short tsize, i;
2880
2881 if (size <= 0)
2882 return;
2883
2884 while (size > 0) {
2885 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2886 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2887 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2888 (dest & (ACE_WINDOW_SIZE - 1));
2889 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2890 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2891 /* Firmware is big-endian */
2892 writel(be32_to_cpup(src), tdest);
2893 src++;
2894 tdest += 4;
2895 dest += 4;
2896 size -= 4;
1da177e4 2897 }
1da177e4 2898 }
1da177e4
LT		 2899}
2900
2901
2902static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2903{
2904 void __iomem *tdest;
2905 short tsize = 0, i;
2906
2907 if (size <= 0)
2908 return;
2909
2910 while (size > 0) {
2911 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2912 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2913 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2914 (dest & (ACE_WINDOW_SIZE - 1));
2915 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2916
2917 for (i = 0; i < (tsize / 4); i++) {
2918 writel(0, tdest + i*4);
2919 }
2920
2921 dest += tsize;
2922 size -= tsize;
2923 }
2924
2925 return;
2926}
2927
2928
2929/*
2930 * Download the firmware into the SRAM on the NIC
2931 *
2932 * This operation requires the NIC to be halted and is performed with
2933 * interrupts disabled and with the spinlock hold.
2934 */
ddfce6bb 2935static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4 2936{
949b4254
JS		 2937 const struct firmware *fw;
2938 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2939 struct ace_private *ap = netdev_priv(dev);
2940 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2941 const __be32 *fw_data;
2942 u32 load_addr;
2943 int ret;
1da177e4
LT		 2944
2945 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2946 printk(KERN_ERR "%s: trying to download firmware while the "
2947 "CPU is running!\n", ap->name);
2948 return -EFAULT;
2949 }
2950
949b4254
JS		 2951 if (ACE_IS_TIGON_I(ap))
2952 fw_name = "acenic/tg1.bin";
2953
2954 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2955 if (ret) {
2956 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2957 ap->name, fw_name);
2958 return ret;
2959 }
2960
2961 fw_data = (void *)fw->data;
2962
2963 /* Firmware blob starts with version numbers, followed by
2964 load and start address. Remainder is the blob to be loaded
2965 contiguously from load address. We don't bother to represent
2966 the BSS/SBSS sections any more, since we were clearing the
2967 whole thing anyway. */
2968 ap->firmware_major = fw->data[0];
2969 ap->firmware_minor = fw->data[1];
2970 ap->firmware_fix = fw->data[2];
2971
2972 ap->firmware_start = be32_to_cpu(fw_data[1]);
2973 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2974 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2975 ap->name, ap->firmware_start, fw_name);
2976 ret = -EINVAL;
2977 goto out;
2978 }
2979
2980 load_addr = be32_to_cpu(fw_data[2]);
2981 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2982 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2983 ap->name, load_addr, fw_name);
2984 ret = -EINVAL;
2985 goto out;
2986 }
2987
1da177e4 2988 /*
949b4254
JS		 2989 * Do not try to clear more than 512KiB or we end up seeing
2990 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2991 */
2992 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2993 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2994 out:
2995 release_firmware(fw);
2996 return ret;
1da177e4
LT		 2997}
2998
2999
3000/*
3001 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3002 *
3003 * Accessing the EEPROM is `interesting' to say the least - don't read
3004 * this code right after dinner.
3005 *
3006 * This is all about black magic and bit-banging the device .... I
3007 * wonder in what hospital they have put the guy who designed the i2c
3008 * specs.
3009 *
3010 * Oh yes, this is only the beginning!
3011 *
3012 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3013 * code i2c readout code by beta testing all my hacks.
3014 */
3015static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3016{
3017 u32 local;
3018
3019 readl(&regs->LocalCtrl);
3020 udelay(ACE_SHORT_DELAY);
3021 local = readl(&regs->LocalCtrl);
3022 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3023 writel(local, &regs->LocalCtrl);
3024 readl(&regs->LocalCtrl);
3025 mb();
3026 udelay(ACE_SHORT_DELAY);
3027 local |= EEPROM_CLK_OUT;
3028 writel(local, &regs->LocalCtrl);
3029 readl(&regs->LocalCtrl);
3030 mb();
3031 udelay(ACE_SHORT_DELAY);
3032 local &= ~EEPROM_DATA_OUT;
3033 writel(local, &regs->LocalCtrl);
3034 readl(&regs->LocalCtrl);
3035 mb();
3036 udelay(ACE_SHORT_DELAY);
3037 local &= ~EEPROM_CLK_OUT;
3038 writel(local, &regs->LocalCtrl);
3039 readl(&regs->LocalCtrl);
3040 mb();
3041}
3042
3043
3044static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3045{
3046 short i;
3047 u32 local;
3048
3049 udelay(ACE_SHORT_DELAY);
3050 local = readl(&regs->LocalCtrl);
3051 local &= ~EEPROM_DATA_OUT;
3052 local |= EEPROM_WRITE_ENABLE;
3053 writel(local, &regs->LocalCtrl);
3054 readl(&regs->LocalCtrl);
3055 mb();
3056
3057 for (i = 0; i < 8; i++, magic <<= 1) {
3058 udelay(ACE_SHORT_DELAY);
6aa20a22 3059 if (magic & 0x80)
1da177e4
LT		 3060 local |= EEPROM_DATA_OUT;
3061 else
3062 local &= ~EEPROM_DATA_OUT;
3063 writel(local, &regs->LocalCtrl);
3064 readl(&regs->LocalCtrl);
3065 mb();
3066
3067 udelay(ACE_SHORT_DELAY);
3068 local |= EEPROM_CLK_OUT;
3069 writel(local, &regs->LocalCtrl);
3070 readl(&regs->LocalCtrl);
3071 mb();
3072 udelay(ACE_SHORT_DELAY);
3073 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3074 writel(local, &regs->LocalCtrl);
3075 readl(&regs->LocalCtrl);
3076 mb();
3077 }
3078}
3079
3080
3081static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3082{
3083 int state;
3084 u32 local;
3085
3086 local = readl(&regs->LocalCtrl);
3087 local &= ~EEPROM_WRITE_ENABLE;
3088 writel(local, &regs->LocalCtrl);
3089 readl(&regs->LocalCtrl);
3090 mb();
3091 udelay(ACE_LONG_DELAY);
3092 local |= EEPROM_CLK_OUT;
3093 writel(local, &regs->LocalCtrl);
3094 readl(&regs->LocalCtrl);
3095 mb();
3096 udelay(ACE_SHORT_DELAY);
3097 /* sample data in middle of high clk */
3098 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3099 udelay(ACE_SHORT_DELAY);
3100 mb();
3101 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3102 readl(&regs->LocalCtrl);
3103 mb();
3104
3105 return state;
3106}
3107
3108
3109static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3110{
3111 u32 local;
3112
3113 udelay(ACE_SHORT_DELAY);
3114 local = readl(&regs->LocalCtrl);
3115 local |= EEPROM_WRITE_ENABLE;
3116 writel(local, &regs->LocalCtrl);
3117 readl(&regs->LocalCtrl);
3118 mb();
3119 udelay(ACE_SHORT_DELAY);
3120 local &= ~EEPROM_DATA_OUT;
3121 writel(local, &regs->LocalCtrl);
3122 readl(&regs->LocalCtrl);
3123 mb();
3124 udelay(ACE_SHORT_DELAY);
3125 local |= EEPROM_CLK_OUT;
3126 writel(local, &regs->LocalCtrl);
3127 readl(&regs->LocalCtrl);
3128 mb();
3129 udelay(ACE_SHORT_DELAY);
3130 local |= EEPROM_DATA_OUT;
3131 writel(local, &regs->LocalCtrl);
3132 readl(&regs->LocalCtrl);
3133 mb();
3134 udelay(ACE_LONG_DELAY);
3135 local &= ~EEPROM_CLK_OUT;
3136 writel(local, &regs->LocalCtrl);
3137 mb();
3138}
3139
3140
3141/*
3142 * Read a whole byte from the EEPROM.
3143 */
3144static int __devinit read_eeprom_byte(struct net_device *dev,
3145 unsigned long offset)
3146{
3147 struct ace_private *ap = netdev_priv(dev);
3148 struct ace_regs __iomem *regs = ap->regs;
3149 unsigned long flags;
3150 u32 local;
3151 int result = 0;
3152 short i;
3153
1da177e4
LT		 3154 /*
3155 * Don't take interrupts on this CPU will bit banging
3156 * the %#%#@$ I2C device
3157 */
3158 local_irq_save(flags);
3159
3160 eeprom_start(regs);
3161
3162 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3163 if (eeprom_check_ack(regs)) {
3164 local_irq_restore(flags);
3165 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3166 result = -EIO;
3167 goto eeprom_read_error;
3168 }
3169
3170 eeprom_prep(regs, (offset >> 8) & 0xff);
3171 if (eeprom_check_ack(regs)) {
3172 local_irq_restore(flags);
3173 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3174 ap->name);
3175 result = -EIO;
3176 goto eeprom_read_error;
3177 }
3178
3179 eeprom_prep(regs, offset & 0xff);
3180 if (eeprom_check_ack(regs)) {
3181 local_irq_restore(flags);
3182 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3183 ap->name);
3184 result = -EIO;
3185 goto eeprom_read_error;
3186 }
3187
3188 eeprom_start(regs);
3189 eeprom_prep(regs, EEPROM_READ_SELECT);
3190 if (eeprom_check_ack(regs)) {
3191 local_irq_restore(flags);
3192 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3193 ap->name);
3194 result = -EIO;
3195 goto eeprom_read_error;
3196 }
3197
3198 for (i = 0; i < 8; i++) {
3199 local = readl(&regs->LocalCtrl);
3200 local &= ~EEPROM_WRITE_ENABLE;
3201 writel(local, &regs->LocalCtrl);
3202 readl(&regs->LocalCtrl);
3203 udelay(ACE_LONG_DELAY);
3204 mb();
3205 local |= EEPROM_CLK_OUT;
3206 writel(local, &regs->LocalCtrl);
3207 readl(&regs->LocalCtrl);
3208 mb();
3209 udelay(ACE_SHORT_DELAY);
3210 /* sample data mid high clk */
3211 result = (result << 1) |
3212 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3213 udelay(ACE_SHORT_DELAY);
3214 mb();
3215 local = readl(&regs->LocalCtrl);
3216 local &= ~EEPROM_CLK_OUT;
3217 writel(local, &regs->LocalCtrl);
3218 readl(&regs->LocalCtrl);
3219 udelay(ACE_SHORT_DELAY);
3220 mb();
3221 if (i == 7) {
3222 local |= EEPROM_WRITE_ENABLE;
3223 writel(local, &regs->LocalCtrl);
3224 readl(&regs->LocalCtrl);
3225 mb();
3226 udelay(ACE_SHORT_DELAY);
3227 }
3228 }
3229
3230 local |= EEPROM_DATA_OUT;
3231 writel(local, &regs->LocalCtrl);
3232 readl(&regs->LocalCtrl);
3233 mb();
3234 udelay(ACE_SHORT_DELAY);
3235 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3236 readl(&regs->LocalCtrl);
3237 udelay(ACE_LONG_DELAY);
3238 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3239 readl(&regs->LocalCtrl);
3240 mb();
3241 udelay(ACE_SHORT_DELAY);
3242 eeprom_stop(regs);
3243
3244 local_irq_restore(flags);
3245 out:
3246 return result;
3247
3248 eeprom_read_error:
3249 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3250 ap->name, offset);
3251 goto out;
3252}
Clone of davem's net-next-2.6 tree