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Merge branches 'irq-core-for-linus' and 'core-locking-for-linus' of git://git.kernel...
[net-next-2.6.git] / drivers / mtd / onenand / onenand_base.c
CommitLineData
cd5f6346
KP		 1/*
2 * linux/drivers/mtd/onenand/onenand_base.c
3 *
3cf60253
AKS		 4 * Copyright © 2005-2009 Samsung Electronics
5 * Copyright © 2007 Nokia Corporation
6 *
cd5f6346
KP		 7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
81280d58
AH		 9 * Credits:
10 * Adrian Hunter <ext-adrian.hunter@nokia.com>:
11 * auto-placement support, read-while load support, various fixes
81280d58 12 *
5988af23
RH		 13 * Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
14 * Flex-OneNAND support
3cf60253
AKS		 15 * Amul Kumar Saha <amul.saha at samsung.com>
16 * OTP support
5988af23 17 *
cd5f6346
KP		 18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
c90173f0 25#include <linux/moduleparam.h>
5a0e3ad6 26#include <linux/slab.h>
cd5f6346 27#include <linux/init.h>
015953d7 28#include <linux/sched.h>
6c77fd64 29#include <linux/delay.h>
2c22120f 30#include <linux/interrupt.h>
015953d7 31#include <linux/jiffies.h>
cd5f6346
KP		 32#include <linux/mtd/mtd.h>
33#include <linux/mtd/onenand.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37
72073027
MK		 38/*
39 * Multiblock erase if number of blocks to erase is 2 or more.
40 * Maximum number of blocks for simultaneous erase is 64.
41 */
42#define MB_ERASE_MIN_BLK_COUNT 2
43#define MB_ERASE_MAX_BLK_COUNT 64
44
5988af23
RH		 45/* Default Flex-OneNAND boundary and lock respectively */
46static int flex_bdry[MAX_DIES * 2] = { -1, 0, -1, 0 };
47
c90173f0
AS		 48module_param_array(flex_bdry, int, NULL, 0400);
49MODULE_PARM_DESC(flex_bdry, "SLC Boundary information for Flex-OneNAND"
50 "Syntax:flex_bdry=DIE_BDRY,LOCK,..."
51 "DIE_BDRY: SLC boundary of the die"
52 "LOCK: Locking information for SLC boundary"
53 " : 0->Set boundary in unlocked status"
54 " : 1->Set boundary in locked status");
55
3cf60253
AKS		 56/* Default OneNAND/Flex-OneNAND OTP options*/
57static int otp;
58
59module_param(otp, int, 0400);
60MODULE_PARM_DESC(otp, "Corresponding behaviour of OneNAND in OTP"
61 "Syntax : otp=LOCK_TYPE"
62 "LOCK_TYPE : Keys issued, for specific OTP Lock type"
63 " : 0 -> Default (No Blocks Locked)"
64 " : 1 -> OTP Block lock"
65 " : 2 -> 1st Block lock"
66 " : 3 -> BOTH OTP Block and 1st Block lock");
67
5988af23
RH		 68/**
69 * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
70 * For now, we expose only 64 out of 80 ecc bytes
71 */
72static struct nand_ecclayout onenand_oob_128 = {
73 .eccbytes = 64,
74 .eccpos = {
75 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
76 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
77 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
78 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
79 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
81 102, 103, 104, 105
82 },
83 .oobfree = {
84 {2, 4}, {18, 4}, {34, 4}, {50, 4},
85 {66, 4}, {82, 4}, {98, 4}, {114, 4}
86 }
87};
88
cd5f6346
KP		 89/**
90 * onenand_oob_64 - oob info for large (2KB) page
91 */
5bd34c09 92static struct nand_ecclayout onenand_oob_64 = {
cd5f6346
KP		 93 .eccbytes = 20,
94 .eccpos = {
95 8, 9, 10, 11, 12,
96 24, 25, 26, 27, 28,
97 40, 41, 42, 43, 44,
98 56, 57, 58, 59, 60,
99 },
100 .oobfree = {
101 {2, 3}, {14, 2}, {18, 3}, {30, 2},
d9777f1c
JL		 102 {34, 3}, {46, 2}, {50, 3}, {62, 2}
103 }
cd5f6346
KP		 104};
105
106/**
107 * onenand_oob_32 - oob info for middle (1KB) page
108 */
5bd34c09 109static struct nand_ecclayout onenand_oob_32 = {
cd5f6346
KP		 110 .eccbytes = 10,
111 .eccpos = {
112 8, 9, 10, 11, 12,
113 24, 25, 26, 27, 28,
114 },
115 .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
116};
117
118static const unsigned char ffchars[] = {
119 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
5988af23
RH		 127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
cd5f6346
KP		 135};
136
137/**
138 * onenand_readw - [OneNAND Interface] Read OneNAND register
139 * @param addr address to read
140 *
141 * Read OneNAND register
142 */
143static unsigned short onenand_readw(void __iomem *addr)
144{
145 return readw(addr);
146}
147
148/**
149 * onenand_writew - [OneNAND Interface] Write OneNAND register with value
150 * @param value value to write
151 * @param addr address to write
152 *
153 * Write OneNAND register with value
154 */
155static void onenand_writew(unsigned short value, void __iomem *addr)
156{
157 writew(value, addr);
158}
159
160/**
161 * onenand_block_address - [DEFAULT] Get block address
83a36838 162 * @param this onenand chip data structure
cd5f6346
KP		 163 * @param block the block
164 * @return translated block address if DDP, otherwise same
165 *
166 * Setup Start Address 1 Register (F100h)
167 */
83a36838 168static int onenand_block_address(struct onenand_chip *this, int block)
cd5f6346 169{
738d61f5
KP		 170 /* Device Flash Core select, NAND Flash Block Address */
171 if (block & this->density_mask)
172 return ONENAND_DDP_CHIP1 | (block ^ this->density_mask);
cd5f6346
KP		 173
174 return block;
175}
176
177/**
178 * onenand_bufferram_address - [DEFAULT] Get bufferram address
83a36838 179 * @param this onenand chip data structure
cd5f6346
KP		 180 * @param block the block
181 * @return set DBS value if DDP, otherwise 0
182 *
183 * Setup Start Address 2 Register (F101h) for DDP
184 */
83a36838 185static int onenand_bufferram_address(struct onenand_chip *this, int block)
cd5f6346 186{
738d61f5
KP		 187 /* Device BufferRAM Select */
188 if (block & this->density_mask)
189 return ONENAND_DDP_CHIP1;
cd5f6346 190
738d61f5 191 return ONENAND_DDP_CHIP0;
cd5f6346
KP		 192}
193
194/**
195 * onenand_page_address - [DEFAULT] Get page address
196 * @param page the page address
197 * @param sector the sector address
198 * @return combined page and sector address
199 *
200 * Setup Start Address 8 Register (F107h)
201 */
202static int onenand_page_address(int page, int sector)
203{
204 /* Flash Page Address, Flash Sector Address */
205 int fpa, fsa;
206
207 fpa = page & ONENAND_FPA_MASK;
208 fsa = sector & ONENAND_FSA_MASK;
209
210 return ((fpa << ONENAND_FPA_SHIFT) | fsa);
211}
212
213/**
214 * onenand_buffer_address - [DEFAULT] Get buffer address
215 * @param dataram1 DataRAM index
216 * @param sectors the sector address
217 * @param count the number of sectors
218 * @return the start buffer value
219 *
220 * Setup Start Buffer Register (F200h)
221 */
222static int onenand_buffer_address(int dataram1, int sectors, int count)
223{
224 int bsa, bsc;
225
226 /* BufferRAM Sector Address */
227 bsa = sectors & ONENAND_BSA_MASK;
228
229 if (dataram1)
230 bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
231 else
232 bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
233
234 /* BufferRAM Sector Count */
235 bsc = count & ONENAND_BSC_MASK;
236
237 return ((bsa << ONENAND_BSA_SHIFT) | bsc);
238}
239
5988af23
RH		 240/**
241 * flexonenand_block- For given address return block number
242 * @param this - OneNAND device structure
243 * @param addr - Address for which block number is needed
244 */
245static unsigned flexonenand_block(struct onenand_chip *this, loff_t addr)
246{
247 unsigned boundary, blk, die = 0;
248
249 if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
250 die = 1;
251 addr -= this->diesize[0];
252 }
253
254 boundary = this->boundary[die];
255
256 blk = addr >> (this->erase_shift - 1);
257 if (blk > boundary)
258 blk = (blk + boundary + 1) >> 1;
259
260 blk += die ? this->density_mask : 0;
261 return blk;
262}
263
264inline unsigned onenand_block(struct onenand_chip *this, loff_t addr)
265{
266 if (!FLEXONENAND(this))
267 return addr >> this->erase_shift;
268 return flexonenand_block(this, addr);
269}
270
271/**
272 * flexonenand_addr - Return address of the block
273 * @this: OneNAND device structure
274 * @block: Block number on Flex-OneNAND
275 *
276 * Return address of the block
277 */
278static loff_t flexonenand_addr(struct onenand_chip *this, int block)
279{
280 loff_t ofs = 0;
281 int die = 0, boundary;
282
283 if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
284 block -= this->density_mask;
285 die = 1;
286 ofs = this->diesize[0];
287 }
288
289 boundary = this->boundary[die];
290 ofs += (loff_t)block << (this->erase_shift - 1);
291 if (block > (boundary + 1))
292 ofs += (loff_t)(block - boundary - 1) << (this->erase_shift - 1);
293 return ofs;
294}
295
296loff_t onenand_addr(struct onenand_chip *this, int block)
297{
298 if (!FLEXONENAND(this))
299 return (loff_t)block << this->erase_shift;
300 return flexonenand_addr(this, block);
301}
302EXPORT_SYMBOL(onenand_addr);
303
e71f04fc
KP		 304/**
305 * onenand_get_density - [DEFAULT] Get OneNAND density
306 * @param dev_id OneNAND device ID
307 *
308 * Get OneNAND density from device ID
309 */
310static inline int onenand_get_density(int dev_id)
311{
312 int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
313 return (density & ONENAND_DEVICE_DENSITY_MASK);
314}
315
5988af23
RH		 316/**
317 * flexonenand_region - [Flex-OneNAND] Return erase region of addr
318 * @param mtd MTD device structure
319 * @param addr address whose erase region needs to be identified
320 */
321int flexonenand_region(struct mtd_info *mtd, loff_t addr)
322{
323 int i;
324
325 for (i = 0; i < mtd->numeraseregions; i++)
326 if (addr < mtd->eraseregions[i].offset)
327 break;
328 return i - 1;
329}
330EXPORT_SYMBOL(flexonenand_region);
331
cd5f6346
KP		 332/**
333 * onenand_command - [DEFAULT] Send command to OneNAND device
334 * @param mtd MTD device structure
335 * @param cmd the command to be sent
336 * @param addr offset to read from or write to
337 * @param len number of bytes to read or write
338 *
339 * Send command to OneNAND device. This function is used for middle/large page
340 * devices (1KB/2KB Bytes per page)
341 */
342static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
343{
344 struct onenand_chip *this = mtd->priv;
b21b72cf 345 int value, block, page;
cd5f6346
KP		 346
347 /* Address translation */
348 switch (cmd) {
349 case ONENAND_CMD_UNLOCK:
350 case ONENAND_CMD_LOCK:
351 case ONENAND_CMD_LOCK_TIGHT:
28b79ff9 352 case ONENAND_CMD_UNLOCK_ALL:
cd5f6346
KP		 353 block = -1;
354 page = -1;
355 break;
356
5988af23
RH		 357 case FLEXONENAND_CMD_PI_ACCESS:
358 /* addr contains die index */
359 block = addr * this->density_mask;
360 page = -1;
361 break;
362
cd5f6346 363 case ONENAND_CMD_ERASE:
72073027
MK		 364 case ONENAND_CMD_MULTIBLOCK_ERASE:
365 case ONENAND_CMD_ERASE_VERIFY:
cd5f6346 366 case ONENAND_CMD_BUFFERRAM:
493c6460 367 case ONENAND_CMD_OTP_ACCESS:
5988af23 368 block = onenand_block(this, addr);
cd5f6346
KP		 369 page = -1;
370 break;
371
5988af23
RH		 372 case FLEXONENAND_CMD_READ_PI:
373 cmd = ONENAND_CMD_READ;
374 block = addr * this->density_mask;
375 page = 0;
376 break;
377
cd5f6346 378 default:
5988af23 379 block = onenand_block(this, addr);
42b0aab1
RHS		 380 if (FLEXONENAND(this))
381 page = (int) (addr - onenand_addr(this, block))>>\
382 this->page_shift;
383 else
384 page = (int) (addr >> this->page_shift);
ee9745fc
KP		 385 if (ONENAND_IS_2PLANE(this)) {
386 /* Make the even block number */
387 block &= ~1;
388 /* Is it the odd plane? */
389 if (addr & this->writesize)
390 block++;
391 page >>= 1;
392 }
cd5f6346
KP		 393 page &= this->page_mask;
394 break;
395 }
396
397 /* NOTE: The setting order of the registers is very important! */
398 if (cmd == ONENAND_CMD_BUFFERRAM) {
399 /* Select DataRAM for DDP */
83a36838 400 value = onenand_bufferram_address(this, block);
cd5f6346
KP		 401 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
402
6a88c47b
KP		 403 if (ONENAND_IS_MLC(this) || ONENAND_IS_2PLANE(this) ||
404 ONENAND_IS_4KB_PAGE(this))
ee9745fc
KP		 405 /* It is always BufferRAM0 */
406 ONENAND_SET_BUFFERRAM0(this);
407 else
408 /* Switch to the next data buffer */
409 ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 410
411 return 0;
412 }
413
414 if (block != -1) {
415 /* Write 'DFS, FBA' of Flash */
83a36838 416 value = onenand_block_address(this, block);
cd5f6346 417 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
3cecf69e 418
b21b72cf
KP		 419 /* Select DataRAM for DDP */
420 value = onenand_bufferram_address(this, block);
421 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 422 }
423
424 if (page != -1) {
60d84f97 425 /* Now we use page size operation */
5988af23 426 int sectors = 0, count = 0;
cd5f6346
KP		 427 int dataram;
428
429 switch (cmd) {
5988af23 430 case FLEXONENAND_CMD_RECOVER_LSB:
cd5f6346
KP		 431 case ONENAND_CMD_READ:
432 case ONENAND_CMD_READOOB:
6a88c47b 433 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 434 /* It is always BufferRAM0 */
435 dataram = ONENAND_SET_BUFFERRAM0(this);
436 else
437 dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 438 break;
439
440 default:
ee9745fc
KP		 441 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
442 cmd = ONENAND_CMD_2X_PROG;
cd5f6346
KP		 443 dataram = ONENAND_CURRENT_BUFFERRAM(this);
444 break;
445 }
446
447 /* Write 'FPA, FSA' of Flash */
448 value = onenand_page_address(page, sectors);
449 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
450
451 /* Write 'BSA, BSC' of DataRAM */
452 value = onenand_buffer_address(dataram, sectors, count);
453 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
cd5f6346
KP		 454 }
455
456 /* Interrupt clear */
457 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
458
459 /* Write command */
460 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
461
462 return 0;
463}
464
5988af23
RH		 465/**
466 * onenand_read_ecc - return ecc status
467 * @param this onenand chip structure
468 */
469static inline int onenand_read_ecc(struct onenand_chip *this)
470{
471 int ecc, i, result = 0;
472
6a88c47b 473 if (!FLEXONENAND(this) && !ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 474 return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
475
476 for (i = 0; i < 4; i++) {
6a88c47b 477 ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS + i*2);
5988af23
RH		 478 if (likely(!ecc))
479 continue;
480 if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
481 return ONENAND_ECC_2BIT_ALL;
482 else
483 result = ONENAND_ECC_1BIT_ALL;
484 }
485
486 return result;
487}
488
cd5f6346
KP		 489/**
490 * onenand_wait - [DEFAULT] wait until the command is done
491 * @param mtd MTD device structure
492 * @param state state to select the max. timeout value
493 *
494 * Wait for command done. This applies to all OneNAND command
495 * Read can take up to 30us, erase up to 2ms and program up to 350us
496 * according to general OneNAND specs
497 */
498static int onenand_wait(struct mtd_info *mtd, int state)
499{
500 struct onenand_chip * this = mtd->priv;
501 unsigned long timeout;
502 unsigned int flags = ONENAND_INT_MASTER;
503 unsigned int interrupt = 0;
2fd32d4a 504 unsigned int ctrl;
cd5f6346
KP		 505
506 /* The 20 msec is enough */
507 timeout = jiffies + msecs_to_jiffies(20);
508 while (time_before(jiffies, timeout)) {
509 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
510
511 if (interrupt & flags)
512 break;
513
72073027 514 if (state != FL_READING && state != FL_PREPARING_ERASE)
cd5f6346
KP		 515 cond_resched();
516 }
517 /* To get correct interrupt status in timeout case */
518 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
519
520 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
521
83973b87
KP		 522 /*
523 * In the Spec. it checks the controller status first
524 * However if you get the correct information in case of
525 * power off recovery (POR) test, it should read ECC status first
526 */
cd5f6346 527 if (interrupt & ONENAND_INT_READ) {
5988af23 528 int ecc = onenand_read_ecc(this);
f4f91ac3 529 if (ecc) {
b3c9f8bf 530 if (ecc & ONENAND_ECC_2BIT_ALL) {
297758f8
AKS		 531 printk(KERN_ERR "%s: ECC error = 0x%04x\n",
532 __func__, ecc);
f4f91ac3 533 mtd->ecc_stats.failed++;
30a7eb29 534 return -EBADMSG;
49dc08ee 535 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
297758f8
AKS		 536 printk(KERN_DEBUG "%s: correctable ECC error = 0x%04x\n",
537 __func__, ecc);
f4f91ac3 538 mtd->ecc_stats.corrected++;
49dc08ee 539 }
cd5f6346 540 }
9d032801 541 } else if (state == FL_READING) {
297758f8
AKS		 542 printk(KERN_ERR "%s: read timeout! ctrl=0x%04x intr=0x%04x\n",
543 __func__, ctrl, interrupt);
9d032801 544 return -EIO;
cd5f6346
KP		 545 }
546
72073027
MK		 547 if (state == FL_PREPARING_ERASE && !(interrupt & ONENAND_INT_ERASE)) {
548 printk(KERN_ERR "%s: mb erase timeout! ctrl=0x%04x intr=0x%04x\n",
549 __func__, ctrl, interrupt);
550 return -EIO;
551 }
552
553 if (!(interrupt & ONENAND_INT_MASTER)) {
554 printk(KERN_ERR "%s: timeout! ctrl=0x%04x intr=0x%04x\n",
555 __func__, ctrl, interrupt);
556 return -EIO;
557 }
558
83973b87
KP		 559 /* If there's controller error, it's a real error */
560 if (ctrl & ONENAND_CTRL_ERROR) {
297758f8
AKS		 561 printk(KERN_ERR "%s: controller error = 0x%04x\n",
562 __func__, ctrl);
83973b87 563 if (ctrl & ONENAND_CTRL_LOCK)
297758f8 564 printk(KERN_ERR "%s: it's locked error.\n", __func__);
83973b87
KP		 565 return -EIO;
566 }
567
cd5f6346
KP		 568 return 0;
569}
570
2c22120f
KP		 571/*
572 * onenand_interrupt - [DEFAULT] onenand interrupt handler
573 * @param irq onenand interrupt number
574 * @param dev_id interrupt data
575 *
576 * complete the work
577 */
578static irqreturn_t onenand_interrupt(int irq, void *data)
579{
06efcad0 580 struct onenand_chip *this = data;
2c22120f
KP		 581
582 /* To handle shared interrupt */
583 if (!this->complete.done)
584 complete(&this->complete);
585
586 return IRQ_HANDLED;
587}
588
589/*
590 * onenand_interrupt_wait - [DEFAULT] wait until the command is done
591 * @param mtd MTD device structure
592 * @param state state to select the max. timeout value
593 *
594 * Wait for command done.
595 */
596static int onenand_interrupt_wait(struct mtd_info *mtd, int state)
597{
598 struct onenand_chip *this = mtd->priv;
599
2c22120f
KP		 600 wait_for_completion(&this->complete);
601
602 return onenand_wait(mtd, state);
603}
604
605/*
606 * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait
607 * @param mtd MTD device structure
608 * @param state state to select the max. timeout value
609 *
610 * Try interrupt based wait (It is used one-time)
611 */
612static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state)
613{
614 struct onenand_chip *this = mtd->priv;
615 unsigned long remain, timeout;
616
617 /* We use interrupt wait first */
618 this->wait = onenand_interrupt_wait;
619
2c22120f
KP		 620 timeout = msecs_to_jiffies(100);
621 remain = wait_for_completion_timeout(&this->complete, timeout);
622 if (!remain) {
623 printk(KERN_INFO "OneNAND: There's no interrupt. "
624 "We use the normal wait\n");
625
626 /* Release the irq */
627 free_irq(this->irq, this);
c9ac5977 628
2c22120f
KP		 629 this->wait = onenand_wait;
630 }
631
632 return onenand_wait(mtd, state);
633}
634
635/*
636 * onenand_setup_wait - [OneNAND Interface] setup onenand wait method
637 * @param mtd MTD device structure
638 *
639 * There's two method to wait onenand work
640 * 1. polling - read interrupt status register
641 * 2. interrupt - use the kernel interrupt method
642 */
643static void onenand_setup_wait(struct mtd_info *mtd)
644{
645 struct onenand_chip *this = mtd->priv;
646 int syscfg;
647
648 init_completion(&this->complete);
649
650 if (this->irq <= 0) {
651 this->wait = onenand_wait;
652 return;
653 }
654
655 if (request_irq(this->irq, &onenand_interrupt,
656 IRQF_SHARED, "onenand", this)) {
657 /* If we can't get irq, use the normal wait */
658 this->wait = onenand_wait;
659 return;
660 }
661
662 /* Enable interrupt */
663 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
664 syscfg |= ONENAND_SYS_CFG1_IOBE;
665 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
666
667 this->wait = onenand_try_interrupt_wait;
668}
669
cd5f6346
KP		 670/**
671 * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
672 * @param mtd MTD data structure
673 * @param area BufferRAM area
674 * @return offset given area
675 *
676 * Return BufferRAM offset given area
677 */
678static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
679{
680 struct onenand_chip *this = mtd->priv;
681
682 if (ONENAND_CURRENT_BUFFERRAM(this)) {
ee9745fc 683 /* Note: the 'this->writesize' is a real page size */
cd5f6346 684 if (area == ONENAND_DATARAM)
ee9745fc 685 return this->writesize;
cd5f6346
KP		 686 if (area == ONENAND_SPARERAM)
687 return mtd->oobsize;
688 }
689
690 return 0;
691}
692
693/**
694 * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
695 * @param mtd MTD data structure
696 * @param area BufferRAM area
697 * @param buffer the databuffer to put/get data
698 * @param offset offset to read from or write to
699 * @param count number of bytes to read/write
700 *
701 * Read the BufferRAM area
702 */
703static int onenand_read_bufferram(struct mtd_info *mtd, int area,
704 unsigned char *buffer, int offset, size_t count)
705{
706 struct onenand_chip *this = mtd->priv;
707 void __iomem *bufferram;
708
709 bufferram = this->base + area;
710
711 bufferram += onenand_bufferram_offset(mtd, area);
712
9c01f87d
KP		 713 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
714 unsigned short word;
715
716 /* Align with word(16-bit) size */
717 count--;
718
719 /* Read word and save byte */
720 word = this->read_word(bufferram + offset + count);
721 buffer[count] = (word & 0xff);
722 }
723
cd5f6346
KP		 724 memcpy(buffer, bufferram + offset, count);
725
726 return 0;
727}
728
52b0eea7
KP		 729/**
730 * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
731 * @param mtd MTD data structure
732 * @param area BufferRAM area
733 * @param buffer the databuffer to put/get data
734 * @param offset offset to read from or write to
735 * @param count number of bytes to read/write
736 *
737 * Read the BufferRAM area with Sync. Burst Mode
738 */
739static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
740 unsigned char *buffer, int offset, size_t count)
741{
742 struct onenand_chip *this = mtd->priv;
743 void __iomem *bufferram;
744
745 bufferram = this->base + area;
746
747 bufferram += onenand_bufferram_offset(mtd, area);
748
749 this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
750
9c01f87d
KP		 751 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
752 unsigned short word;
753
754 /* Align with word(16-bit) size */
755 count--;
756
757 /* Read word and save byte */
758 word = this->read_word(bufferram + offset + count);
759 buffer[count] = (word & 0xff);
760 }
761
52b0eea7
KP		 762 memcpy(buffer, bufferram + offset, count);
763
764 this->mmcontrol(mtd, 0);
765
766 return 0;
767}
768
cd5f6346
KP		 769/**
770 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
771 * @param mtd MTD data structure
772 * @param area BufferRAM area
773 * @param buffer the databuffer to put/get data
774 * @param offset offset to read from or write to
775 * @param count number of bytes to read/write
776 *
777 * Write the BufferRAM area
778 */
779static int onenand_write_bufferram(struct mtd_info *mtd, int area,
780 const unsigned char *buffer, int offset, size_t count)
781{
782 struct onenand_chip *this = mtd->priv;
783 void __iomem *bufferram;
784
785 bufferram = this->base + area;
786
787 bufferram += onenand_bufferram_offset(mtd, area);
788
9c01f87d
KP		 789 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
790 unsigned short word;
791 int byte_offset;
792
793 /* Align with word(16-bit) size */
794 count--;
795
796 /* Calculate byte access offset */
797 byte_offset = offset + count;
798
799 /* Read word and save byte */
800 word = this->read_word(bufferram + byte_offset);
801 word = (word & ~0xff) | buffer[count];
802 this->write_word(word, bufferram + byte_offset);
803 }
804
cd5f6346
KP		 805 memcpy(bufferram + offset, buffer, count);
806
807 return 0;
808}
809
ee9745fc
KP		 810/**
811 * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
812 * @param mtd MTD data structure
813 * @param addr address to check
814 * @return blockpage address
815 *
816 * Get blockpage address at 2x program mode
817 */
818static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
819{
820 struct onenand_chip *this = mtd->priv;
821 int blockpage, block, page;
822
823 /* Calculate the even block number */
824 block = (int) (addr >> this->erase_shift) & ~1;
825 /* Is it the odd plane? */
826 if (addr & this->writesize)
827 block++;
828 page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
829 blockpage = (block << 7) | page;
830
831 return blockpage;
832}
833
cd5f6346
KP		 834/**
835 * onenand_check_bufferram - [GENERIC] Check BufferRAM information
836 * @param mtd MTD data structure
837 * @param addr address to check
d5c5e78a 838 * @return 1 if there are valid data, otherwise 0
cd5f6346
KP		 839 *
840 * Check bufferram if there is data we required
841 */
842static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
843{
844 struct onenand_chip *this = mtd->priv;
cde36b37 845 int blockpage, found = 0;
abf3c0f2 846 unsigned int i;
d5c5e78a 847
ee9745fc
KP		 848 if (ONENAND_IS_2PLANE(this))
849 blockpage = onenand_get_2x_blockpage(mtd, addr);
850 else
851 blockpage = (int) (addr >> this->page_shift);
cd5f6346 852
abf3c0f2 853 /* Is there valid data? */
cd5f6346 854 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2 855 if (this->bufferram[i].blockpage == blockpage)
cde36b37
AH		 856 found = 1;
857 else {
858 /* Check another BufferRAM */
859 i = ONENAND_NEXT_BUFFERRAM(this);
860 if (this->bufferram[i].blockpage == blockpage) {
861 ONENAND_SET_NEXT_BUFFERRAM(this);
862 found = 1;
863 }
864 }
cd5f6346 865
cde36b37
AH		 866 if (found && ONENAND_IS_DDP(this)) {
867 /* Select DataRAM for DDP */
5988af23 868 int block = onenand_block(this, addr);
cde36b37
AH		 869 int value = onenand_bufferram_address(this, block);
870 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
abf3c0f2 871 }
cd5f6346 872
cde36b37 873 return found;
cd5f6346
KP		 874}
875
876/**
877 * onenand_update_bufferram - [GENERIC] Update BufferRAM information
878 * @param mtd MTD data structure
879 * @param addr address to update
880 * @param valid valid flag
881 *
882 * Update BufferRAM information
883 */
abf3c0f2 884static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
cd5f6346
KP		 885 int valid)
886{
887 struct onenand_chip *this = mtd->priv;
abf3c0f2
KP		 888 int blockpage;
889 unsigned int i;
d5c5e78a 890
ee9745fc
KP		 891 if (ONENAND_IS_2PLANE(this))
892 blockpage = onenand_get_2x_blockpage(mtd, addr);
893 else
894 blockpage = (int) (addr >> this->page_shift);
cd5f6346 895
abf3c0f2
KP		 896 /* Invalidate another BufferRAM */
897 i = ONENAND_NEXT_BUFFERRAM(this);
5b4246f1 898 if (this->bufferram[i].blockpage == blockpage)
abf3c0f2 899 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 900
901 /* Update BufferRAM */
902 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2
KP		 903 if (valid)
904 this->bufferram[i].blockpage = blockpage;
905 else
906 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 907}
908
480b9dfb
AH		 909/**
910 * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information
911 * @param mtd MTD data structure
912 * @param addr start address to invalidate
913 * @param len length to invalidate
914 *
915 * Invalidate BufferRAM information
916 */
917static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr,
918 unsigned int len)
919{
920 struct onenand_chip *this = mtd->priv;
921 int i;
922 loff_t end_addr = addr + len;
923
924 /* Invalidate BufferRAM */
925 for (i = 0; i < MAX_BUFFERRAM; i++) {
926 loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift;
927 if (buf_addr >= addr && buf_addr < end_addr)
928 this->bufferram[i].blockpage = -1;
929 }
930}
931
cd5f6346
KP		 932/**
933 * onenand_get_device - [GENERIC] Get chip for selected access
934 * @param mtd MTD device structure
935 * @param new_state the state which is requested
936 *
937 * Get the device and lock it for exclusive access
938 */
a41371eb 939static int onenand_get_device(struct mtd_info *mtd, int new_state)
cd5f6346
KP		 940{
941 struct onenand_chip *this = mtd->priv;
942 DECLARE_WAITQUEUE(wait, current);
943
944 /*
945 * Grab the lock and see if the device is available
946 */
947 while (1) {
948 spin_lock(&this->chip_lock);
949 if (this->state == FL_READY) {
950 this->state = new_state;
951 spin_unlock(&this->chip_lock);
952 break;
953 }
a41371eb
KP		 954 if (new_state == FL_PM_SUSPENDED) {
955 spin_unlock(&this->chip_lock);
956 return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
957 }
cd5f6346
KP		 958 set_current_state(TASK_UNINTERRUPTIBLE);
959 add_wait_queue(&this->wq, &wait);
960 spin_unlock(&this->chip_lock);
961 schedule();
962 remove_wait_queue(&this->wq, &wait);
963 }
a41371eb
KP		 964
965 return 0;
cd5f6346
KP		 966}
967
968/**
969 * onenand_release_device - [GENERIC] release chip
970 * @param mtd MTD device structure
971 *
972 * Deselect, release chip lock and wake up anyone waiting on the device
973 */
974static void onenand_release_device(struct mtd_info *mtd)
975{
976 struct onenand_chip *this = mtd->priv;
977
978 /* Release the chip */
979 spin_lock(&this->chip_lock);
980 this->state = FL_READY;
981 wake_up(&this->wq);
982 spin_unlock(&this->chip_lock);
983}
984
985/**
d15057b7
KP		 986 * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
987 * @param mtd MTD device structure
988 * @param buf destination address
989 * @param column oob offset to read from
990 * @param thislen oob length to read
991 */
992static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,
993 int thislen)
994{
995 struct onenand_chip *this = mtd->priv;
996 struct nand_oobfree *free;
997 int readcol = column;
998 int readend = column + thislen;
999 int lastgap = 0;
1000 unsigned int i;
1001 uint8_t *oob_buf = this->oob_buf;
1002
1003 free = this->ecclayout->oobfree;
1004 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1005 if (readcol >= lastgap)
1006 readcol += free->offset - lastgap;
1007 if (readend >= lastgap)
1008 readend += free->offset - lastgap;
1009 lastgap = free->offset + free->length;
1010 }
1011 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
1012 free = this->ecclayout->oobfree;
1013 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1014 int free_end = free->offset + free->length;
1015 if (free->offset < readend && free_end > readcol) {
1016 int st = max_t(int,free->offset,readcol);
1017 int ed = min_t(int,free_end,readend);
1018 int n = ed - st;
1019 memcpy(buf, oob_buf + st, n);
1020 buf += n;
1021 } else if (column == 0)
1022 break;
1023 }
1024 return 0;
1025}
1026
5988af23
RH		 1027/**
1028 * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
1029 * @param mtd MTD device structure
1030 * @param addr address to recover
1031 * @param status return value from onenand_wait / onenand_bbt_wait
1032 *
1033 * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
1034 * lower page address and MSB page has higher page address in paired pages.
1035 * If power off occurs during MSB page program, the paired LSB page data can
1036 * become corrupt. LSB page recovery read is a way to read LSB page though page
1037 * data are corrupted. When uncorrectable error occurs as a result of LSB page
1038 * read after power up, issue LSB page recovery read.
1039 */
1040static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
1041{
1042 struct onenand_chip *this = mtd->priv;
1043 int i;
1044
1045 /* Recovery is only for Flex-OneNAND */
1046 if (!FLEXONENAND(this))
1047 return status;
1048
1049 /* check if we failed due to uncorrectable error */
1050 if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
1051 return status;
1052
1053 /* check if address lies in MLC region */
1054 i = flexonenand_region(mtd, addr);
1055 if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
1056 return status;
1057
1058 /* We are attempting to reread, so decrement stats.failed
1059 * which was incremented by onenand_wait due to read failure
1060 */
297758f8
AKS		 1061 printk(KERN_INFO "%s: Attempting to recover from uncorrectable read\n",
1062 __func__);
5988af23
RH		 1063 mtd->ecc_stats.failed--;
1064
1065 /* Issue the LSB page recovery command */
1066 this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
1067 return this->wait(mtd, FL_READING);
1068}
1069
1070/**
1071 * onenand_mlc_read_ops_nolock - MLC OneNAND read main and/or out-of-band
1072 * @param mtd MTD device structure
1073 * @param from offset to read from
1074 * @param ops: oob operation description structure
1075 *
1076 * MLC OneNAND / Flex-OneNAND has 4KB page size and 4KB dataram.
1077 * So, read-while-load is not present.
1078 */
1079static int onenand_mlc_read_ops_nolock(struct mtd_info *mtd, loff_t from,
1080 struct mtd_oob_ops *ops)
1081{
1082 struct onenand_chip *this = mtd->priv;
1083 struct mtd_ecc_stats stats;
1084 size_t len = ops->len;
1085 size_t ooblen = ops->ooblen;
1086 u_char *buf = ops->datbuf;
1087 u_char *oobbuf = ops->oobbuf;
1088 int read = 0, column, thislen;
1089 int oobread = 0, oobcolumn, thisooblen, oobsize;
1090 int ret = 0;
1091 int writesize = this->writesize;
1092
297758f8 1093 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
8032747e 1094 __func__, (unsigned int) from, (int) len);
5988af23
RH		 1095
1096 if (ops->mode == MTD_OOB_AUTO)
1097 oobsize = this->ecclayout->oobavail;
1098 else
1099 oobsize = mtd->oobsize;
1100
1101 oobcolumn = from & (mtd->oobsize - 1);
1102
1103 /* Do not allow reads past end of device */
1104 if (from + len > mtd->size) {
297758f8
AKS		 1105 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1106 __func__);
5988af23
RH		 1107 ops->retlen = 0;
1108 ops->oobretlen = 0;
1109 return -EINVAL;
1110 }
1111
1112 stats = mtd->ecc_stats;
1113
1114 while (read < len) {
1115 cond_resched();
1116
1117 thislen = min_t(int, writesize, len - read);
1118
1119 column = from & (writesize - 1);
1120 if (column + thislen > writesize)
1121 thislen = writesize - column;
1122
1123 if (!onenand_check_bufferram(mtd, from)) {
1124 this->command(mtd, ONENAND_CMD_READ, from, writesize);
1125
1126 ret = this->wait(mtd, FL_READING);
1127 if (unlikely(ret))
1128 ret = onenand_recover_lsb(mtd, from, ret);
1129 onenand_update_bufferram(mtd, from, !ret);
1130 if (ret == -EBADMSG)
1131 ret = 0;
1132 }
1133
1134 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
1135 if (oobbuf) {
1136 thisooblen = oobsize - oobcolumn;
1137 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1138
1139 if (ops->mode == MTD_OOB_AUTO)
1140 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1141 else
1142 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1143 oobread += thisooblen;
1144 oobbuf += thisooblen;
1145 oobcolumn = 0;
1146 }
1147
1148 read += thislen;
1149 if (read == len)
1150 break;
1151
1152 from += thislen;
1153 buf += thislen;
1154 }
1155
1156 /*
1157 * Return success, if no ECC failures, else -EBADMSG
1158 * fs driver will take care of that, because
1159 * retlen == desired len and result == -EBADMSG
1160 */
1161 ops->retlen = read;
1162 ops->oobretlen = oobread;
1163
1164 if (ret)
1165 return ret;
1166
1167 if (mtd->ecc_stats.failed - stats.failed)
1168 return -EBADMSG;
1169
1170 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1171}
1172
d15057b7 1173/**
49dc08ee 1174 * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
cd5f6346
KP		 1175 * @param mtd MTD device structure
1176 * @param from offset to read from
d15057b7 1177 * @param ops: oob operation description structure
cd5f6346 1178 *
d15057b7
KP		 1179 * OneNAND read main and/or out-of-band data
1180 */
49dc08ee 1181static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from,
d15057b7 1182 struct mtd_oob_ops *ops)
cd5f6346
KP		 1183{
1184 struct onenand_chip *this = mtd->priv;
f4f91ac3 1185 struct mtd_ecc_stats stats;
d15057b7
KP		 1186 size_t len = ops->len;
1187 size_t ooblen = ops->ooblen;
1188 u_char *buf = ops->datbuf;
1189 u_char *oobbuf = ops->oobbuf;
1190 int read = 0, column, thislen;
1191 int oobread = 0, oobcolumn, thisooblen, oobsize;
0fc2ccea 1192 int ret = 0, boundary = 0;
ee9745fc 1193 int writesize = this->writesize;
cd5f6346 1194
297758f8
AKS		 1195 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1196 __func__, (unsigned int) from, (int) len);
d15057b7
KP		 1197
1198 if (ops->mode == MTD_OOB_AUTO)
1199 oobsize = this->ecclayout->oobavail;
1200 else
1201 oobsize = mtd->oobsize;
1202
1203 oobcolumn = from & (mtd->oobsize - 1);
cd5f6346
KP		 1204
1205 /* Do not allow reads past end of device */
1206 if ((from + len) > mtd->size) {
297758f8
AKS		 1207 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1208 __func__);
d15057b7
KP		 1209 ops->retlen = 0;
1210 ops->oobretlen = 0;
cd5f6346
KP		 1211 return -EINVAL;
1212 }
1213
f4f91ac3 1214 stats = mtd->ecc_stats;
61a7e198 1215
a8de85d5
AH		 1216 /* Read-while-load method */
1217
1218 /* Do first load to bufferRAM */
1219 if (read < len) {
1220 if (!onenand_check_bufferram(mtd, from)) {
ee9745fc 1221 this->command(mtd, ONENAND_CMD_READ, from, writesize);
a8de85d5
AH		 1222 ret = this->wait(mtd, FL_READING);
1223 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1224 if (ret == -EBADMSG)
1225 ret = 0;
a8de85d5
AH		 1226 }
1227 }
1228
ee9745fc
KP		 1229 thislen = min_t(int, writesize, len - read);
1230 column = from & (writesize - 1);
1231 if (column + thislen > writesize)
1232 thislen = writesize - column;
a8de85d5
AH		 1233
1234 while (!ret) {
1235 /* If there is more to load then start next load */
1236 from += thislen;
1237 if (read + thislen < len) {
ee9745fc 1238 this->command(mtd, ONENAND_CMD_READ, from, writesize);
0fc2ccea
AH		 1239 /*
1240 * Chip boundary handling in DDP
1241 * Now we issued chip 1 read and pointed chip 1
492e1501 1242 * bufferram so we have to point chip 0 bufferram.
0fc2ccea 1243 */
738d61f5
KP		 1244 if (ONENAND_IS_DDP(this) &&
1245 unlikely(from == (this->chipsize >> 1))) {
1246 this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2);
0fc2ccea
AH		 1247 boundary = 1;
1248 } else
1249 boundary = 0;
a8de85d5
AH		 1250 ONENAND_SET_PREV_BUFFERRAM(this);
1251 }
1252 /* While load is going, read from last bufferRAM */
1253 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
d15057b7
KP		 1254
1255 /* Read oob area if needed */
1256 if (oobbuf) {
1257 thisooblen = oobsize - oobcolumn;
1258 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1259
1260 if (ops->mode == MTD_OOB_AUTO)
1261 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1262 else
1263 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1264 oobread += thisooblen;
1265 oobbuf += thisooblen;
1266 oobcolumn = 0;
1267 }
1268
a8de85d5
AH		 1269 /* See if we are done */
1270 read += thislen;
1271 if (read == len)
1272 break;
1273 /* Set up for next read from bufferRAM */
0fc2ccea 1274 if (unlikely(boundary))
738d61f5 1275 this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
a8de85d5
AH		 1276 ONENAND_SET_NEXT_BUFFERRAM(this);
1277 buf += thislen;
ee9745fc 1278 thislen = min_t(int, writesize, len - read);
a8de85d5
AH		 1279 column = 0;
1280 cond_resched();
1281 /* Now wait for load */
1282 ret = this->wait(mtd, FL_READING);
1283 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1284 if (ret == -EBADMSG)
1285 ret = 0;
a8de85d5 1286 }
cd5f6346 1287
cd5f6346
KP		 1288 /*
1289 * Return success, if no ECC failures, else -EBADMSG
1290 * fs driver will take care of that, because
1291 * retlen == desired len and result == -EBADMSG
1292 */
d15057b7
KP		 1293 ops->retlen = read;
1294 ops->oobretlen = oobread;
f4f91ac3 1295
a8de85d5
AH		 1296 if (ret)
1297 return ret;
1298
5f4d47d5
AH		 1299 if (mtd->ecc_stats.failed - stats.failed)
1300 return -EBADMSG;
1301
f4f91ac3 1302 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
cd5f6346
KP		 1303}
1304
cd5f6346 1305/**
49dc08ee 1306 * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
cd5f6346
KP		 1307 * @param mtd MTD device structure
1308 * @param from offset to read from
d15057b7 1309 * @param ops: oob operation description structure
cd5f6346
KP		 1310 *
1311 * OneNAND read out-of-band data from the spare area
1312 */
49dc08ee 1313static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from,
12f77c9e 1314 struct mtd_oob_ops *ops)
cd5f6346
KP		 1315{
1316 struct onenand_chip *this = mtd->priv;
5f4d47d5 1317 struct mtd_ecc_stats stats;
a5e7c7b4 1318 int read = 0, thislen, column, oobsize;
12f77c9e
KP		 1319 size_t len = ops->ooblen;
1320 mtd_oob_mode_t mode = ops->mode;
1321 u_char *buf = ops->oobbuf;
5988af23 1322 int ret = 0, readcmd;
cd5f6346 1323
12f77c9e
KP		 1324 from += ops->ooboffs;
1325
297758f8
AKS		 1326 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1327 __func__, (unsigned int) from, (int) len);
cd5f6346
KP		 1328
1329 /* Initialize return length value */
12f77c9e 1330 ops->oobretlen = 0;
cd5f6346 1331
a5e7c7b4
AH		 1332 if (mode == MTD_OOB_AUTO)
1333 oobsize = this->ecclayout->oobavail;
1334 else
1335 oobsize = mtd->oobsize;
1336
1337 column = from & (mtd->oobsize - 1);
1338
1339 if (unlikely(column >= oobsize)) {
297758f8
AKS		 1340 printk(KERN_ERR "%s: Attempted to start read outside oob\n",
1341 __func__);
a5e7c7b4
AH		 1342 return -EINVAL;
1343 }
1344
cd5f6346 1345 /* Do not allow reads past end of device */
a5e7c7b4
AH		 1346 if (unlikely(from >= mtd->size ||
1347 column + len > ((mtd->size >> this->page_shift) -
1348 (from >> this->page_shift)) * oobsize)) {
297758f8
AKS		 1349 printk(KERN_ERR "%s: Attempted to read beyond end of device\n",
1350 __func__);
cd5f6346
KP		 1351 return -EINVAL;
1352 }
1353
5f4d47d5
AH		 1354 stats = mtd->ecc_stats;
1355
5988af23
RH		 1356 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1357
cd5f6346 1358 while (read < len) {
61a7e198
AB		 1359 cond_resched();
1360
a5e7c7b4 1361 thislen = oobsize - column;
cd5f6346
KP		 1362 thislen = min_t(int, thislen, len);
1363
5988af23 1364 this->command(mtd, readcmd, from, mtd->oobsize);
cd5f6346
KP		 1365
1366 onenand_update_bufferram(mtd, from, 0);
1367
1368 ret = this->wait(mtd, FL_READING);
5988af23
RH		 1369 if (unlikely(ret))
1370 ret = onenand_recover_lsb(mtd, from, ret);
1371
5f4d47d5 1372 if (ret && ret != -EBADMSG) {
297758f8
AKS		 1373 printk(KERN_ERR "%s: read failed = 0x%x\n",
1374 __func__, ret);
5f4d47d5
AH		 1375 break;
1376 }
cd5f6346 1377
a5e7c7b4
AH		 1378 if (mode == MTD_OOB_AUTO)
1379 onenand_transfer_auto_oob(mtd, buf, column, thislen);
1380 else
1381 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
cd5f6346
KP		 1382
1383 read += thislen;
1384
1385 if (read == len)
1386 break;
1387
cd5f6346
KP		 1388 buf += thislen;
1389
1390 /* Read more? */
1391 if (read < len) {
1392 /* Page size */
28318776 1393 from += mtd->writesize;
cd5f6346
KP		 1394 column = 0;
1395 }
1396 }
1397
12f77c9e 1398 ops->oobretlen = read;
5f4d47d5
AH		 1399
1400 if (ret)
1401 return ret;
1402
1403 if (mtd->ecc_stats.failed - stats.failed)
1404 return -EBADMSG;
1405
1406 return 0;
cd5f6346
KP		 1407}
1408
8593fbc6 1409/**
d15057b7
KP		 1410 * onenand_read - [MTD Interface] Read data from flash
1411 * @param mtd MTD device structure
1412 * @param from offset to read from
1413 * @param len number of bytes to read
1414 * @param retlen pointer to variable to store the number of read bytes
1415 * @param buf the databuffer to put data
1416 *
1417 * Read with ecc
1418*/
1419static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
1420 size_t *retlen, u_char *buf)
1421{
5988af23 1422 struct onenand_chip *this = mtd->priv;
d15057b7
KP		 1423 struct mtd_oob_ops ops = {
1424 .len = len,
1425 .ooblen = 0,
1426 .datbuf = buf,
1427 .oobbuf = NULL,
1428 };
1429 int ret;
1430
49dc08ee 1431 onenand_get_device(mtd, FL_READING);
6a88c47b 1432 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1433 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
1434 onenand_read_ops_nolock(mtd, from, &ops);
49dc08ee 1435 onenand_release_device(mtd);
d15057b7 1436
49dc08ee 1437 *retlen = ops.retlen;
d15057b7
KP		 1438 return ret;
1439}
1440
1441/**
1442 * onenand_read_oob - [MTD Interface] Read main and/or out-of-band
e3da8067
KP		 1443 * @param mtd: MTD device structure
1444 * @param from: offset to read from
1445 * @param ops: oob operation description structure
d15057b7
KP		 1446
1447 * Read main and/or out-of-band
8593fbc6
TG		 1448 */
1449static int onenand_read_oob(struct mtd_info *mtd, loff_t from,
1450 struct mtd_oob_ops *ops)
1451{
5988af23 1452 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 1453 int ret;
1454
4f4fad27 1455 switch (ops->mode) {
a5e7c7b4
AH		 1456 case MTD_OOB_PLACE:
1457 case MTD_OOB_AUTO:
1458 break;
1459 case MTD_OOB_RAW:
4f4fad27 1460 /* Not implemented yet */
a5e7c7b4
AH		 1461 default:
1462 return -EINVAL;
1463 }
d15057b7 1464
49dc08ee 1465 onenand_get_device(mtd, FL_READING);
d15057b7 1466 if (ops->datbuf)
6a88c47b 1467 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1468 onenand_mlc_read_ops_nolock(mtd, from, ops) :
1469 onenand_read_ops_nolock(mtd, from, ops);
49dc08ee
AB		 1470 else
1471 ret = onenand_read_oob_nolock(mtd, from, ops);
1472 onenand_release_device(mtd);
d15057b7 1473
49dc08ee 1474 return ret;
8593fbc6
TG		 1475}
1476
211ac75f
KP		 1477/**
1478 * onenand_bbt_wait - [DEFAULT] wait until the command is done
1479 * @param mtd MTD device structure
1480 * @param state state to select the max. timeout value
1481 *
1482 * Wait for command done.
1483 */
1484static int onenand_bbt_wait(struct mtd_info *mtd, int state)
1485{
1486 struct onenand_chip *this = mtd->priv;
1487 unsigned long timeout;
1488 unsigned int interrupt;
1489 unsigned int ctrl;
1490
1491 /* The 20 msec is enough */
1492 timeout = jiffies + msecs_to_jiffies(20);
1493 while (time_before(jiffies, timeout)) {
1494 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1495 if (interrupt & ONENAND_INT_MASTER)
1496 break;
1497 }
1498 /* To get correct interrupt status in timeout case */
1499 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1500 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
1501
211ac75f 1502 if (interrupt & ONENAND_INT_READ) {
5988af23 1503 int ecc = onenand_read_ecc(this);
83973b87 1504 if (ecc & ONENAND_ECC_2BIT_ALL) {
297758f8
AKS		 1505 printk(KERN_WARNING "%s: ecc error = 0x%04x, "
1506 "controller error 0x%04x\n",
1507 __func__, ecc, ctrl);
5988af23 1508 return ONENAND_BBT_READ_ECC_ERROR;
83973b87 1509 }
211ac75f 1510 } else {
297758f8
AKS		 1511 printk(KERN_ERR "%s: read timeout! ctrl=0x%04x intr=0x%04x\n",
1512 __func__, ctrl, interrupt);
211ac75f
KP		 1513 return ONENAND_BBT_READ_FATAL_ERROR;
1514 }
1515
83973b87
KP		 1516 /* Initial bad block case: 0x2400 or 0x0400 */
1517 if (ctrl & ONENAND_CTRL_ERROR) {
297758f8
AKS		 1518 printk(KERN_DEBUG "%s: controller error = 0x%04x\n",
1519 __func__, ctrl);
83973b87
KP		 1520 return ONENAND_BBT_READ_ERROR;
1521 }
1522
211ac75f
KP		 1523 return 0;
1524}
1525
1526/**
1527 * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
1528 * @param mtd MTD device structure
1529 * @param from offset to read from
e3da8067 1530 * @param ops oob operation description structure
211ac75f
KP		 1531 *
1532 * OneNAND read out-of-band data from the spare area for bbt scan
1533 */
1534int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
1535 struct mtd_oob_ops *ops)
1536{
1537 struct onenand_chip *this = mtd->priv;
1538 int read = 0, thislen, column;
5988af23 1539 int ret = 0, readcmd;
211ac75f
KP		 1540 size_t len = ops->ooblen;
1541 u_char *buf = ops->oobbuf;
1542
297758f8
AKS		 1543 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %zi\n",
1544 __func__, (unsigned int) from, len);
211ac75f
KP		 1545
1546 /* Initialize return value */
1547 ops->oobretlen = 0;
1548
1549 /* Do not allow reads past end of device */
1550 if (unlikely((from + len) > mtd->size)) {
297758f8
AKS		 1551 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1552 __func__);
211ac75f
KP		 1553 return ONENAND_BBT_READ_FATAL_ERROR;
1554 }
1555
1556 /* Grab the lock and see if the device is available */
1557 onenand_get_device(mtd, FL_READING);
1558
1559 column = from & (mtd->oobsize - 1);
1560
5988af23
RH		 1561 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1562
211ac75f
KP		 1563 while (read < len) {
1564 cond_resched();
1565
1566 thislen = mtd->oobsize - column;
1567 thislen = min_t(int, thislen, len);
1568
5988af23 1569 this->command(mtd, readcmd, from, mtd->oobsize);
211ac75f
KP		 1570
1571 onenand_update_bufferram(mtd, from, 0);
1572
31bb999e 1573 ret = this->bbt_wait(mtd, FL_READING);
5988af23
RH		 1574 if (unlikely(ret))
1575 ret = onenand_recover_lsb(mtd, from, ret);
1576
211ac75f
KP		 1577 if (ret)
1578 break;
1579
1580 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
1581 read += thislen;
1582 if (read == len)
1583 break;
1584
1585 buf += thislen;
1586
1587 /* Read more? */
1588 if (read < len) {
1589 /* Update Page size */
ee9745fc 1590 from += this->writesize;
211ac75f
KP		 1591 column = 0;
1592 }
1593 }
1594
1595 /* Deselect and wake up anyone waiting on the device */
1596 onenand_release_device(mtd);
1597
1598 ops->oobretlen = read;
1599 return ret;
1600}
1601
cd5f6346 1602#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
8e6ec690
KP		 1603/**
1604 * onenand_verify_oob - [GENERIC] verify the oob contents after a write
1605 * @param mtd MTD device structure
1606 * @param buf the databuffer to verify
1607 * @param to offset to read from
8e6ec690 1608 */
a5e7c7b4 1609static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to)
8e6ec690
KP		 1610{
1611 struct onenand_chip *this = mtd->priv;
69d79186 1612 u_char *oob_buf = this->oob_buf;
5988af23
RH		 1613 int status, i, readcmd;
1614
1615 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
8e6ec690 1616
5988af23 1617 this->command(mtd, readcmd, to, mtd->oobsize);
8e6ec690
KP		 1618 onenand_update_bufferram(mtd, to, 0);
1619 status = this->wait(mtd, FL_READING);
1620 if (status)
1621 return status;
1622
69d79186 1623 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
91014e9b 1624 for (i = 0; i < mtd->oobsize; i++)
69d79186 1625 if (buf[i] != 0xFF && buf[i] != oob_buf[i])
8e6ec690
KP		 1626 return -EBADMSG;
1627
1628 return 0;
1629}
1630
cd5f6346 1631/**
8b29c0b6
AH		 1632 * onenand_verify - [GENERIC] verify the chip contents after a write
1633 * @param mtd MTD device structure
1634 * @param buf the databuffer to verify
1635 * @param addr offset to read from
1636 * @param len number of bytes to read and compare
cd5f6346 1637 */
8b29c0b6 1638static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len)
cd5f6346
KP		 1639{
1640 struct onenand_chip *this = mtd->priv;
cd5f6346 1641 int ret = 0;
8b29c0b6 1642 int thislen, column;
cd5f6346 1643
8b29c0b6 1644 while (len != 0) {
ee9745fc
KP		 1645 thislen = min_t(int, this->writesize, len);
1646 column = addr & (this->writesize - 1);
1647 if (column + thislen > this->writesize)
1648 thislen = this->writesize - column;
60d84f97 1649
ee9745fc 1650 this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
cd5f6346 1651
8b29c0b6
AH		 1652 onenand_update_bufferram(mtd, addr, 0);
1653
1654 ret = this->wait(mtd, FL_READING);
1655 if (ret)
1656 return ret;
cd5f6346 1657
8b29c0b6 1658 onenand_update_bufferram(mtd, addr, 1);
cd5f6346 1659
3328dc31 1660 this->read_bufferram(mtd, ONENAND_DATARAM, this->verify_buf, 0, mtd->writesize);
cd5f6346 1661
3328dc31 1662 if (memcmp(buf, this->verify_buf, thislen))
8b29c0b6
AH		 1663 return -EBADMSG;
1664
1665 len -= thislen;
1666 buf += thislen;
1667 addr += thislen;
1668 }
d5c5e78a 1669
cd5f6346
KP		 1670 return 0;
1671}
1672#else
8b29c0b6 1673#define onenand_verify(...) (0)
8e6ec690 1674#define onenand_verify_oob(...) (0)
cd5f6346
KP		 1675#endif
1676
60d84f97 1677#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0)
cd5f6346 1678
6c77fd64
RP		 1679static void onenand_panic_wait(struct mtd_info *mtd)
1680{
1681 struct onenand_chip *this = mtd->priv;
1682 unsigned int interrupt;
1683 int i;
1684
1685 for (i = 0; i < 2000; i++) {
1686 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1687 if (interrupt & ONENAND_INT_MASTER)
1688 break;
1689 udelay(10);
1690 }
1691}
1692
1693/**
1694 * onenand_panic_write - [MTD Interface] write buffer to FLASH in a panic context
1695 * @param mtd MTD device structure
1696 * @param to offset to write to
1697 * @param len number of bytes to write
1698 * @param retlen pointer to variable to store the number of written bytes
1699 * @param buf the data to write
1700 *
1701 * Write with ECC
1702 */
1703static int onenand_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
1704 size_t *retlen, const u_char *buf)
1705{
1706 struct onenand_chip *this = mtd->priv;
1707 int column, subpage;
1708 int written = 0;
1709 int ret = 0;
1710
1711 if (this->state == FL_PM_SUSPENDED)
1712 return -EBUSY;
1713
1714 /* Wait for any existing operation to clear */
1715 onenand_panic_wait(mtd);
1716
297758f8
AKS		 1717 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1718 __func__, (unsigned int) to, (int) len);
6c77fd64
RP		 1719
1720 /* Initialize retlen, in case of early exit */
1721 *retlen = 0;
1722
1723 /* Do not allow writes past end of device */
1724 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1725 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1726 __func__);
6c77fd64
RP		 1727 return -EINVAL;
1728 }
1729
1730 /* Reject writes, which are not page aligned */
b73d7e43 1731 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1732 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1733 __func__);
6c77fd64
RP		 1734 return -EINVAL;
1735 }
1736
1737 column = to & (mtd->writesize - 1);
1738
1739 /* Loop until all data write */
1740 while (written < len) {
1741 int thislen = min_t(int, mtd->writesize - column, len - written);
1742 u_char *wbuf = (u_char *) buf;
1743
1744 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
1745
1746 /* Partial page write */
1747 subpage = thislen < mtd->writesize;
1748 if (subpage) {
1749 memset(this->page_buf, 0xff, mtd->writesize);
1750 memcpy(this->page_buf + column, buf, thislen);
1751 wbuf = this->page_buf;
1752 }
1753
1754 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
1755 this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
1756
1757 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1758
1759 onenand_panic_wait(mtd);
1760
1761 /* In partial page write we don't update bufferram */
1762 onenand_update_bufferram(mtd, to, !ret && !subpage);
1763 if (ONENAND_IS_2PLANE(this)) {
1764 ONENAND_SET_BUFFERRAM1(this);
1765 onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
1766 }
1767
1768 if (ret) {
297758f8 1769 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
6c77fd64
RP		 1770 break;
1771 }
1772
1773 written += thislen;
1774
1775 if (written == len)
1776 break;
1777
1778 column = 0;
1779 to += thislen;
1780 buf += thislen;
1781 }
1782
1783 *retlen = written;
1784 return ret;
1785}
1786
cd5f6346 1787/**
d15057b7
KP		 1788 * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
1789 * @param mtd MTD device structure
1790 * @param oob_buf oob buffer
1791 * @param buf source address
1792 * @param column oob offset to write to
1793 * @param thislen oob length to write
1794 */
1795static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
1796 const u_char *buf, int column, int thislen)
1797{
1798 struct onenand_chip *this = mtd->priv;
1799 struct nand_oobfree *free;
1800 int writecol = column;
1801 int writeend = column + thislen;
1802 int lastgap = 0;
1803 unsigned int i;
1804
1805 free = this->ecclayout->oobfree;
1806 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1807 if (writecol >= lastgap)
1808 writecol += free->offset - lastgap;
1809 if (writeend >= lastgap)
1810 writeend += free->offset - lastgap;
1811 lastgap = free->offset + free->length;
1812 }
1813 free = this->ecclayout->oobfree;
1814 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1815 int free_end = free->offset + free->length;
1816 if (free->offset < writeend && free_end > writecol) {
1817 int st = max_t(int,free->offset,writecol);
1818 int ed = min_t(int,free_end,writeend);
1819 int n = ed - st;
1820 memcpy(oob_buf + st, buf, n);
1821 buf += n;
1822 } else if (column == 0)
1823 break;
1824 }
1825 return 0;
1826}
1827
1828/**
49dc08ee 1829 * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
cd5f6346
KP		 1830 * @param mtd MTD device structure
1831 * @param to offset to write to
d15057b7 1832 * @param ops oob operation description structure
cd5f6346 1833 *
d15057b7 1834 * Write main and/or oob with ECC
cd5f6346 1835 */
49dc08ee 1836static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to,
d15057b7 1837 struct mtd_oob_ops *ops)
cd5f6346
KP		 1838{
1839 struct onenand_chip *this = mtd->priv;
9ce96908
KP		 1840 int written = 0, column, thislen = 0, subpage = 0;
1841 int prev = 0, prevlen = 0, prev_subpage = 0, first = 1;
d15057b7
KP		 1842 int oobwritten = 0, oobcolumn, thisooblen, oobsize;
1843 size_t len = ops->len;
1844 size_t ooblen = ops->ooblen;
1845 const u_char *buf = ops->datbuf;
1846 const u_char *oob = ops->oobbuf;
1847 u_char *oobbuf;
cd5f6346
KP		 1848 int ret = 0;
1849
297758f8
AKS		 1850 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1851 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 1852
1853 /* Initialize retlen, in case of early exit */
d15057b7
KP		 1854 ops->retlen = 0;
1855 ops->oobretlen = 0;
cd5f6346
KP		 1856
1857 /* Do not allow writes past end of device */
1858 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1859 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1860 __func__);
cd5f6346
KP		 1861 return -EINVAL;
1862 }
1863
1864 /* Reject writes, which are not page aligned */
b73d7e43 1865 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1866 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1867 __func__);
cd5f6346
KP		 1868 return -EINVAL;
1869 }
1870
9ce96908
KP		 1871 /* Check zero length */
1872 if (!len)
1873 return 0;
1874
d15057b7
KP		 1875 if (ops->mode == MTD_OOB_AUTO)
1876 oobsize = this->ecclayout->oobavail;
1877 else
1878 oobsize = mtd->oobsize;
1879
1880 oobcolumn = to & (mtd->oobsize - 1);
1881
60d84f97 1882 column = to & (mtd->writesize - 1);
60d84f97 1883
cd5f6346 1884 /* Loop until all data write */
9ce96908
KP		 1885 while (1) {
1886 if (written < len) {
1887 u_char *wbuf = (u_char *) buf;
60d84f97 1888
9ce96908
KP		 1889 thislen = min_t(int, mtd->writesize - column, len - written);
1890 thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten);
d15057b7 1891
9ce96908 1892 cond_resched();
61a7e198 1893
9ce96908 1894 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
60d84f97 1895
9ce96908
KP		 1896 /* Partial page write */
1897 subpage = thislen < mtd->writesize;
1898 if (subpage) {
1899 memset(this->page_buf, 0xff, mtd->writesize);
1900 memcpy(this->page_buf + column, buf, thislen);
1901 wbuf = this->page_buf;
1902 }
cd5f6346 1903
9ce96908 1904 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
d15057b7 1905
9ce96908
KP		 1906 if (oob) {
1907 oobbuf = this->oob_buf;
d15057b7 1908
9ce96908
KP		 1909 /* We send data to spare ram with oobsize
1910 * to prevent byte access */
1911 memset(oobbuf, 0xff, mtd->oobsize);
1912 if (ops->mode == MTD_OOB_AUTO)
1913 onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
1914 else
1915 memcpy(oobbuf + oobcolumn, oob, thisooblen);
d15057b7 1916
9ce96908
KP		 1917 oobwritten += thisooblen;
1918 oob += thisooblen;
1919 oobcolumn = 0;
1920 } else
1921 oobbuf = (u_char *) ffchars;
1922
1923 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
d15057b7 1924 } else
9ce96908 1925 ONENAND_SET_NEXT_BUFFERRAM(this);
d15057b7 1926
9ce96908 1927 /*
492e1501
MK		 1928 * 2 PLANE, MLC, and Flex-OneNAND do not support
1929 * write-while-program feature.
9ce96908 1930 */
6a88c47b 1931 if (!ONENAND_IS_2PLANE(this) && !ONENAND_IS_4KB_PAGE(this) && !first) {
9ce96908
KP		 1932 ONENAND_SET_PREV_BUFFERRAM(this);
1933
1934 ret = this->wait(mtd, FL_WRITING);
1935
1936 /* In partial page write we don't update bufferram */
1937 onenand_update_bufferram(mtd, prev, !ret && !prev_subpage);
1938 if (ret) {
1939 written -= prevlen;
297758f8
AKS		 1940 printk(KERN_ERR "%s: write failed %d\n",
1941 __func__, ret);
9ce96908
KP		 1942 break;
1943 }
cd5f6346 1944
9ce96908
KP		 1945 if (written == len) {
1946 /* Only check verify write turn on */
1947 ret = onenand_verify(mtd, buf - len, to - len, len);
1948 if (ret)
297758f8
AKS		 1949 printk(KERN_ERR "%s: verify failed %d\n",
1950 __func__, ret);
9ce96908
KP		 1951 break;
1952 }
cd5f6346 1953
9ce96908
KP		 1954 ONENAND_SET_NEXT_BUFFERRAM(this);
1955 }
81f38e11 1956
9ce96908
KP		 1957 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1958
1959 /*
1960 * 2 PLANE, MLC, and Flex-OneNAND wait here
1961 */
6a88c47b 1962 if (ONENAND_IS_2PLANE(this) || ONENAND_IS_4KB_PAGE(this)) {
9ce96908 1963 ret = this->wait(mtd, FL_WRITING);
cd5f6346 1964
9ce96908
KP		 1965 /* In partial page write we don't update bufferram */
1966 onenand_update_bufferram(mtd, to, !ret && !subpage);
1967 if (ret) {
297758f8
AKS		 1968 printk(KERN_ERR "%s: write failed %d\n",
1969 __func__, ret);
9ce96908
KP		 1970 break;
1971 }
cd5f6346 1972
9ce96908
KP		 1973 /* Only check verify write turn on */
1974 ret = onenand_verify(mtd, buf, to, thislen);
1975 if (ret) {
297758f8
AKS		 1976 printk(KERN_ERR "%s: verify failed %d\n",
1977 __func__, ret);
9ce96908
KP		 1978 break;
1979 }
cd5f6346 1980
9ce96908 1981 written += thislen;
81f38e11 1982
9ce96908
KP		 1983 if (written == len)
1984 break;
1985
1986 } else
1987 written += thislen;
cd5f6346 1988
60d84f97 1989 column = 0;
9ce96908
KP		 1990 prev_subpage = subpage;
1991 prev = to;
1992 prevlen = thislen;
cd5f6346
KP		 1993 to += thislen;
1994 buf += thislen;
9ce96908 1995 first = 0;
cd5f6346
KP		 1996 }
1997
9ce96908
KP		 1998 /* In error case, clear all bufferrams */
1999 if (written != len)
2000 onenand_invalidate_bufferram(mtd, 0, -1);
2001
d15057b7 2002 ops->retlen = written;
9ce96908 2003 ops->oobretlen = oobwritten;
d5c5e78a 2004
cd5f6346
KP		 2005 return ret;
2006}
2007
a5e7c7b4 2008
cd5f6346 2009/**
49dc08ee 2010 * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
cd5f6346
KP		 2011 * @param mtd MTD device structure
2012 * @param to offset to write to
2013 * @param len number of bytes to write
2014 * @param retlen pointer to variable to store the number of written bytes
2015 * @param buf the data to write
a5e7c7b4 2016 * @param mode operation mode
cd5f6346
KP		 2017 *
2018 * OneNAND write out-of-band
2019 */
49dc08ee
AB		 2020static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2021 struct mtd_oob_ops *ops)
cd5f6346
KP		 2022{
2023 struct onenand_chip *this = mtd->priv;
a5e7c7b4 2024 int column, ret = 0, oobsize;
5988af23 2025 int written = 0, oobcmd;
91014e9b 2026 u_char *oobbuf;
12f77c9e
KP		 2027 size_t len = ops->ooblen;
2028 const u_char *buf = ops->oobbuf;
2029 mtd_oob_mode_t mode = ops->mode;
2030
2031 to += ops->ooboffs;
cd5f6346 2032
297758f8
AKS		 2033 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2034 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 2035
2036 /* Initialize retlen, in case of early exit */
12f77c9e 2037 ops->oobretlen = 0;
cd5f6346 2038
a5e7c7b4
AH		 2039 if (mode == MTD_OOB_AUTO)
2040 oobsize = this->ecclayout->oobavail;
2041 else
2042 oobsize = mtd->oobsize;
2043
2044 column = to & (mtd->oobsize - 1);
2045
2046 if (unlikely(column >= oobsize)) {
297758f8
AKS		 2047 printk(KERN_ERR "%s: Attempted to start write outside oob\n",
2048 __func__);
a5e7c7b4
AH		 2049 return -EINVAL;
2050 }
2051
52e4200a 2052 /* For compatibility with NAND: Do not allow write past end of page */
91014e9b 2053 if (unlikely(column + len > oobsize)) {
297758f8
AKS		 2054 printk(KERN_ERR "%s: Attempt to write past end of page\n",
2055 __func__);
52e4200a
AH		 2056 return -EINVAL;
2057 }
2058
a5e7c7b4
AH		 2059 /* Do not allow reads past end of device */
2060 if (unlikely(to >= mtd->size ||
2061 column + len > ((mtd->size >> this->page_shift) -
2062 (to >> this->page_shift)) * oobsize)) {
8032747e
DW		 2063 printk(KERN_ERR "%s: Attempted to write past end of device\n",
2064 __func__);
cd5f6346
KP		 2065 return -EINVAL;
2066 }
2067
470bc844 2068 oobbuf = this->oob_buf;
91014e9b 2069
5988af23
RH		 2070 oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
2071
cd5f6346
KP		 2072 /* Loop until all data write */
2073 while (written < len) {
a5e7c7b4 2074 int thislen = min_t(int, oobsize, len - written);
cd5f6346 2075
61a7e198
AB		 2076 cond_resched();
2077
cd5f6346
KP		 2078 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
2079
34c10609
KP		 2080 /* We send data to spare ram with oobsize
2081 * to prevent byte access */
91014e9b 2082 memset(oobbuf, 0xff, mtd->oobsize);
a5e7c7b4 2083 if (mode == MTD_OOB_AUTO)
91014e9b 2084 onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
a5e7c7b4 2085 else
91014e9b
KP		 2086 memcpy(oobbuf + column, buf, thislen);
2087 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
cd5f6346 2088
6a88c47b 2089 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this)) {
5988af23
RH		 2090 /* Set main area of DataRAM to 0xff*/
2091 memset(this->page_buf, 0xff, mtd->writesize);
2092 this->write_bufferram(mtd, ONENAND_DATARAM,
2093 this->page_buf, 0, mtd->writesize);
2094 }
2095
2096 this->command(mtd, oobcmd, to, mtd->oobsize);
cd5f6346
KP		 2097
2098 onenand_update_bufferram(mtd, to, 0);
ee9745fc
KP		 2099 if (ONENAND_IS_2PLANE(this)) {
2100 ONENAND_SET_BUFFERRAM1(this);
2101 onenand_update_bufferram(mtd, to + this->writesize, 0);
2102 }
cd5f6346 2103
8e6ec690
KP		 2104 ret = this->wait(mtd, FL_WRITING);
2105 if (ret) {
297758f8 2106 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
5b4246f1 2107 break;
8e6ec690
KP		 2108 }
2109
91014e9b 2110 ret = onenand_verify_oob(mtd, oobbuf, to);
8e6ec690 2111 if (ret) {
297758f8
AKS		 2112 printk(KERN_ERR "%s: verify failed %d\n",
2113 __func__, ret);
5b4246f1 2114 break;
8e6ec690 2115 }
cd5f6346
KP		 2116
2117 written += thislen;
cd5f6346
KP		 2118 if (written == len)
2119 break;
2120
a5e7c7b4 2121 to += mtd->writesize;
cd5f6346 2122 buf += thislen;
a5e7c7b4 2123 column = 0;
cd5f6346
KP		 2124 }
2125
12f77c9e 2126 ops->oobretlen = written;
d5c5e78a 2127
8e6ec690 2128 return ret;
cd5f6346
KP		 2129}
2130
d15057b7
KP		 2131/**
2132 * onenand_write - [MTD Interface] write buffer to FLASH
2133 * @param mtd MTD device structure
2134 * @param to offset to write to
2135 * @param len number of bytes to write
2136 * @param retlen pointer to variable to store the number of written bytes
2137 * @param buf the data to write
2138 *
2139 * Write with ECC
2140 */
2141static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
2142 size_t *retlen, const u_char *buf)
2143{
2144 struct mtd_oob_ops ops = {
2145 .len = len,
2146 .ooblen = 0,
2147 .datbuf = (u_char *) buf,
2148 .oobbuf = NULL,
2149 };
2150 int ret;
2151
49dc08ee
AB		 2152 onenand_get_device(mtd, FL_WRITING);
2153 ret = onenand_write_ops_nolock(mtd, to, &ops);
2154 onenand_release_device(mtd);
d15057b7 2155
49dc08ee 2156 *retlen = ops.retlen;
d15057b7
KP		 2157 return ret;
2158}
2159
8593fbc6
TG		 2160/**
2161 * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band
e3da8067
KP		 2162 * @param mtd: MTD device structure
2163 * @param to: offset to write
2164 * @param ops: oob operation description structure
8593fbc6
TG		 2165 */
2166static int onenand_write_oob(struct mtd_info *mtd, loff_t to,
2167 struct mtd_oob_ops *ops)
2168{
49dc08ee
AB		 2169 int ret;
2170
4f4fad27 2171 switch (ops->mode) {
a5e7c7b4
AH		 2172 case MTD_OOB_PLACE:
2173 case MTD_OOB_AUTO:
2174 break;
2175 case MTD_OOB_RAW:
4f4fad27 2176 /* Not implemented yet */
a5e7c7b4
AH		 2177 default:
2178 return -EINVAL;
2179 }
d15057b7 2180
49dc08ee 2181 onenand_get_device(mtd, FL_WRITING);
d15057b7 2182 if (ops->datbuf)
49dc08ee
AB		 2183 ret = onenand_write_ops_nolock(mtd, to, ops);
2184 else
2185 ret = onenand_write_oob_nolock(mtd, to, ops);
2186 onenand_release_device(mtd);
d15057b7 2187
49dc08ee 2188 return ret;
8593fbc6
TG		 2189}
2190
cdc00130 2191/**
49dc08ee 2192 * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
cdc00130
KP		 2193 * @param mtd MTD device structure
2194 * @param ofs offset from device start
cdc00130
KP		 2195 * @param allowbbt 1, if its allowed to access the bbt area
2196 *
2197 * Check, if the block is bad. Either by reading the bad block table or
2198 * calling of the scan function.
2199 */
49dc08ee 2200static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
cdc00130
KP		 2201{
2202 struct onenand_chip *this = mtd->priv;
2203 struct bbm_info *bbm = this->bbm;
2204
2205 /* Return info from the table */
2206 return bbm->isbad_bbt(mtd, ofs, allowbbt);
2207}
2208
72073027
MK		 2209
2210static int onenand_multiblock_erase_verify(struct mtd_info *mtd,
2211 struct erase_info *instr)
2212{
2213 struct onenand_chip *this = mtd->priv;
2214 loff_t addr = instr->addr;
2215 int len = instr->len;
2216 unsigned int block_size = (1 << this->erase_shift);
2217 int ret = 0;
2218
2219 while (len) {
2220 this->command(mtd, ONENAND_CMD_ERASE_VERIFY, addr, block_size);
2221 ret = this->wait(mtd, FL_VERIFYING_ERASE);
2222 if (ret) {
2223 printk(KERN_ERR "%s: Failed verify, block %d\n",
2224 __func__, onenand_block(this, addr));
2225 instr->state = MTD_ERASE_FAILED;
2226 instr->fail_addr = addr;
2227 return -1;
2228 }
2229 len -= block_size;
2230 addr += block_size;
2231 }
2232 return 0;
2233}
2234
2235/**
2236 * onenand_multiblock_erase - [Internal] erase block(s) using multiblock erase
2237 * @param mtd MTD device structure
2238 * @param instr erase instruction
2239 * @param region erase region
2240 *
2241 * Erase one or more blocks up to 64 block at a time
2242 */
2243static int onenand_multiblock_erase(struct mtd_info *mtd,
2244 struct erase_info *instr,
2245 unsigned int block_size)
2246{
2247 struct onenand_chip *this = mtd->priv;
2248 loff_t addr = instr->addr;
2249 int len = instr->len;
2250 int eb_count = 0;
2251 int ret = 0;
2252 int bdry_block = 0;
2253
2254 instr->state = MTD_ERASING;
2255
2256 if (ONENAND_IS_DDP(this)) {
2257 loff_t bdry_addr = this->chipsize >> 1;
2258 if (addr < bdry_addr && (addr + len) > bdry_addr)
2259 bdry_block = bdry_addr >> this->erase_shift;
2260 }
2261
2262 /* Pre-check bbs */
2263 while (len) {
2264 /* Check if we have a bad block, we do not erase bad blocks */
2265 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
2266 printk(KERN_WARNING "%s: attempt to erase a bad block "
2267 "at addr 0x%012llx\n",
2268 __func__, (unsigned long long) addr);
2269 instr->state = MTD_ERASE_FAILED;
2270 return -EIO;
2271 }
2272 len -= block_size;
2273 addr += block_size;
2274 }
2275
2276 len = instr->len;
2277 addr = instr->addr;
2278
2279 /* loop over 64 eb batches */
2280 while (len) {
2281 struct erase_info verify_instr = *instr;
2282 int max_eb_count = MB_ERASE_MAX_BLK_COUNT;
2283
2284 verify_instr.addr = addr;
2285 verify_instr.len = 0;
2286
2287 /* do not cross chip boundary */
2288 if (bdry_block) {
2289 int this_block = (addr >> this->erase_shift);
2290
2291 if (this_block < bdry_block) {
2292 max_eb_count = min(max_eb_count,
2293 (bdry_block - this_block));
2294 }
2295 }
2296
2297 eb_count = 0;
2298
2299 while (len > block_size && eb_count < (max_eb_count - 1)) {
2300 this->command(mtd, ONENAND_CMD_MULTIBLOCK_ERASE,
2301 addr, block_size);
2302 onenand_invalidate_bufferram(mtd, addr, block_size);
2303
2304 ret = this->wait(mtd, FL_PREPARING_ERASE);
2305 if (ret) {
2306 printk(KERN_ERR "%s: Failed multiblock erase, "
2307 "block %d\n", __func__,
2308 onenand_block(this, addr));
2309 instr->state = MTD_ERASE_FAILED;
2310 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2311 return -EIO;
2312 }
2313
2314 len -= block_size;
2315 addr += block_size;
2316 eb_count++;
2317 }
2318
2319 /* last block of 64-eb series */
2320 cond_resched();
2321 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2322 onenand_invalidate_bufferram(mtd, addr, block_size);
2323
2324 ret = this->wait(mtd, FL_ERASING);
2325 /* Check if it is write protected */
2326 if (ret) {
2327 printk(KERN_ERR "%s: Failed erase, block %d\n",
2328 __func__, onenand_block(this, addr));
2329 instr->state = MTD_ERASE_FAILED;
2330 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2331 return -EIO;
2332 }
2333
2334 len -= block_size;
2335 addr += block_size;
2336 eb_count++;
2337
2338 /* verify */
2339 verify_instr.len = eb_count * block_size;
2340 if (onenand_multiblock_erase_verify(mtd, &verify_instr)) {
2341 instr->state = verify_instr.state;
2342 instr->fail_addr = verify_instr.fail_addr;
2343 return -EIO;
2344 }
2345
2346 }
2347 return 0;
2348}
2349
2350
cd5f6346 2351/**
73885aea 2352 * onenand_block_by_block_erase - [Internal] erase block(s) using regular erase
cd5f6346
KP		 2353 * @param mtd MTD device structure
2354 * @param instr erase instruction
73885aea
MK		 2355 * @param region erase region
2356 * @param block_size erase block size
cd5f6346 2357 *
73885aea 2358 * Erase one or more blocks one block at a time
cd5f6346 2359 */
73885aea
MK		 2360static int onenand_block_by_block_erase(struct mtd_info *mtd,
2361 struct erase_info *instr,
2362 struct mtd_erase_region_info *region,
2363 unsigned int block_size)
cd5f6346
KP		 2364{
2365 struct onenand_chip *this = mtd->priv;
5988af23 2366 loff_t addr = instr->addr;
73885aea 2367 int len = instr->len;
5988af23 2368 loff_t region_end = 0;
73885aea 2369 int ret = 0;
cd5f6346 2370
73885aea
MK		 2371 if (region) {
2372 /* region is set for Flex-OneNAND */
5988af23 2373 region_end = region->offset + region->erasesize * region->numblocks;
cd5f6346
KP		 2374 }
2375
cd5f6346
KP		 2376 instr->state = MTD_ERASING;
2377
73885aea 2378 /* Loop through the blocks */
cd5f6346 2379 while (len) {
61a7e198 2380 cond_resched();
cd5f6346 2381
cdc00130 2382 /* Check if we have a bad block, we do not erase bad blocks */
49dc08ee 2383 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
297758f8
AKS		 2384 printk(KERN_WARNING "%s: attempt to erase a bad block "
2385 "at addr 0x%012llx\n",
2386 __func__, (unsigned long long) addr);
cdc00130 2387 instr->state = MTD_ERASE_FAILED;
73885aea 2388 return -EIO;
cdc00130 2389 }
cd5f6346
KP		 2390
2391 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2392
480b9dfb
AH		 2393 onenand_invalidate_bufferram(mtd, addr, block_size);
2394
cd5f6346
KP		 2395 ret = this->wait(mtd, FL_ERASING);
2396 /* Check, if it is write protected */
2397 if (ret) {
297758f8
AKS		 2398 printk(KERN_ERR "%s: Failed erase, block %d\n",
2399 __func__, onenand_block(this, addr));
cd5f6346
KP		 2400 instr->state = MTD_ERASE_FAILED;
2401 instr->fail_addr = addr;
73885aea 2402 return -EIO;
cd5f6346
KP		 2403 }
2404
2405 len -= block_size;
2406 addr += block_size;
5988af23
RH		 2407
2408 if (addr == region_end) {
2409 if (!len)
2410 break;
2411 region++;
2412
2413 block_size = region->erasesize;
2414 region_end = region->offset + region->erasesize * region->numblocks;
2415
2416 if (len & (block_size - 1)) {
2417 /* FIXME: This should be handled at MTD partitioning level. */
297758f8
AKS		 2418 printk(KERN_ERR "%s: Unaligned address\n",
2419 __func__);
73885aea 2420 return -EIO;
5988af23
RH		 2421 }
2422 }
73885aea
MK		 2423 }
2424 return 0;
2425}
5988af23 2426
73885aea
MK		 2427/**
2428 * onenand_erase - [MTD Interface] erase block(s)
2429 * @param mtd MTD device structure
2430 * @param instr erase instruction
2431 *
2432 * Erase one or more blocks
2433 */
2434static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
2435{
2436 struct onenand_chip *this = mtd->priv;
2437 unsigned int block_size;
2438 loff_t addr = instr->addr;
2439 loff_t len = instr->len;
2440 int ret = 0;
2441 struct mtd_erase_region_info *region = NULL;
2442 loff_t region_offset = 0;
2443
2444 DEBUG(MTD_DEBUG_LEVEL3, "%s: start=0x%012llx, len=%llu\n", __func__,
2445 (unsigned long long) instr->addr, (unsigned long long) instr->len);
2446
2447 /* Do not allow erase past end of device */
2448 if (unlikely((len + addr) > mtd->size)) {
2449 printk(KERN_ERR "%s: Erase past end of device\n", __func__);
2450 return -EINVAL;
cd5f6346
KP		 2451 }
2452
73885aea
MK		 2453 if (FLEXONENAND(this)) {
2454 /* Find the eraseregion of this address */
2455 int i = flexonenand_region(mtd, addr);
cd5f6346 2456
73885aea
MK		 2457 region = &mtd->eraseregions[i];
2458 block_size = region->erasesize;
cd5f6346 2459
73885aea
MK		 2460 /* Start address within region must align on block boundary.
2461 * Erase region's start offset is always block start address.
2462 */
2463 region_offset = region->offset;
2464 } else
2465 block_size = 1 << this->erase_shift;
2466
2467 /* Start address must align on block boundary */
2468 if (unlikely((addr - region_offset) & (block_size - 1))) {
2469 printk(KERN_ERR "%s: Unaligned address\n", __func__);
2470 return -EINVAL;
2471 }
2472
2473 /* Length must align on block boundary */
2474 if (unlikely(len & (block_size - 1))) {
2475 printk(KERN_ERR "%s: Length not block aligned\n", __func__);
2476 return -EINVAL;
2477 }
2478
2479 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2480
2481 /* Grab the lock and see if the device is available */
2482 onenand_get_device(mtd, FL_ERASING);
2483
72073027
MK		 2484 if (region || instr->len < MB_ERASE_MIN_BLK_COUNT * block_size) {
2485 /* region is set for Flex-OneNAND (no mb erase) */
2486 ret = onenand_block_by_block_erase(mtd, instr,
2487 region, block_size);
2488 } else {
2489 ret = onenand_multiblock_erase(mtd, instr, block_size);
2490 }
cd5f6346
KP		 2491
2492 /* Deselect and wake up anyone waiting on the device */
2493 onenand_release_device(mtd);
2494
3cd3a86b 2495 /* Do call back function */
73885aea
MK		 2496 if (!ret) {
2497 instr->state = MTD_ERASE_DONE;
3cd3a86b 2498 mtd_erase_callback(instr);
73885aea 2499 }
3cd3a86b 2500
cd5f6346
KP		 2501 return ret;
2502}
2503
2504/**
2505 * onenand_sync - [MTD Interface] sync
2506 * @param mtd MTD device structure
2507 *
2508 * Sync is actually a wait for chip ready function
2509 */
2510static void onenand_sync(struct mtd_info *mtd)
2511{
297758f8 2512 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
cd5f6346
KP		 2513
2514 /* Grab the lock and see if the device is available */
2515 onenand_get_device(mtd, FL_SYNCING);
2516
2517 /* Release it and go back */
2518 onenand_release_device(mtd);
2519}
2520
2521/**
2522 * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2523 * @param mtd MTD device structure
2524 * @param ofs offset relative to mtd start
cdc00130
KP		 2525 *
2526 * Check whether the block is bad
cd5f6346
KP		 2527 */
2528static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
2529{
49dc08ee
AB		 2530 int ret;
2531
cdc00130
KP		 2532 /* Check for invalid offset */
2533 if (ofs > mtd->size)
2534 return -EINVAL;
2535
49dc08ee
AB		 2536 onenand_get_device(mtd, FL_READING);
2537 ret = onenand_block_isbad_nolock(mtd, ofs, 0);
2538 onenand_release_device(mtd);
2539 return ret;
cdc00130
KP		 2540}
2541
2542/**
2543 * onenand_default_block_markbad - [DEFAULT] mark a block bad
2544 * @param mtd MTD device structure
2545 * @param ofs offset from device start
2546 *
2547 * This is the default implementation, which can be overridden by
2548 * a hardware specific driver.
2549 */
2550static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
2551{
2552 struct onenand_chip *this = mtd->priv;
2553 struct bbm_info *bbm = this->bbm;
2554 u_char buf[2] = {0, 0};
12f77c9e
KP		 2555 struct mtd_oob_ops ops = {
2556 .mode = MTD_OOB_PLACE,
2557 .ooblen = 2,
2558 .oobbuf = buf,
2559 .ooboffs = 0,
2560 };
cdc00130
KP		 2561 int block;
2562
2563 /* Get block number */
5988af23 2564 block = onenand_block(this, ofs);
cdc00130
KP		 2565 if (bbm->bbt)
2566 bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
2567
492e1501 2568 /* We write two bytes, so we don't have to mess with 16-bit access */
cdc00130 2569 ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
5988af23
RH		 2570 /* FIXME : What to do when marking SLC block in partition
2571 * with MLC erasesize? For now, it is not advisable to
2572 * create partitions containing both SLC and MLC regions.
2573 */
2574 return onenand_write_oob_nolock(mtd, ofs, &ops);
cd5f6346
KP		 2575}
2576
2577/**
2578 * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2579 * @param mtd MTD device structure
2580 * @param ofs offset relative to mtd start
cdc00130
KP		 2581 *
2582 * Mark the block as bad
cd5f6346
KP		 2583 */
2584static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2585{
cdc00130
KP		 2586 struct onenand_chip *this = mtd->priv;
2587 int ret;
2588
2589 ret = onenand_block_isbad(mtd, ofs);
2590 if (ret) {
2591 /* If it was bad already, return success and do nothing */
2592 if (ret > 0)
2593 return 0;
2594 return ret;
2595 }
2596
49dc08ee
AB		 2597 onenand_get_device(mtd, FL_WRITING);
2598 ret = this->block_markbad(mtd, ofs);
2599 onenand_release_device(mtd);
2600 return ret;
cd5f6346
KP		 2601}
2602
2603/**
08f782b6 2604 * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
cd5f6346
KP		 2605 * @param mtd MTD device structure
2606 * @param ofs offset relative to mtd start
08f782b6 2607 * @param len number of bytes to lock or unlock
e3da8067 2608 * @param cmd lock or unlock command
cd5f6346 2609 *
08f782b6 2610 * Lock or unlock one or more blocks
cd5f6346 2611 */
08f782b6 2612static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
cd5f6346
KP		 2613{
2614 struct onenand_chip *this = mtd->priv;
2615 int start, end, block, value, status;
08f782b6 2616 int wp_status_mask;
cd5f6346 2617
5988af23
RH		 2618 start = onenand_block(this, ofs);
2619 end = onenand_block(this, ofs + len) - 1;
cd5f6346 2620
08f782b6
KP		 2621 if (cmd == ONENAND_CMD_LOCK)
2622 wp_status_mask = ONENAND_WP_LS;
2623 else
2624 wp_status_mask = ONENAND_WP_US;
2625
cd5f6346 2626 /* Continuous lock scheme */
28b79ff9 2627 if (this->options & ONENAND_HAS_CONT_LOCK) {
cd5f6346
KP		 2628 /* Set start block address */
2629 this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2630 /* Set end block address */
5988af23 2631 this->write_word(end, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
08f782b6
KP		 2632 /* Write lock command */
2633 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2634
2635 /* There's no return value */
08f782b6 2636 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2637
2638 /* Sanity check */
2639 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2640 & ONENAND_CTRL_ONGO)
2641 continue;
2642
2643 /* Check lock status */
2644 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2645 if (!(status & wp_status_mask))
297758f8
AKS		 2646 printk(KERN_ERR "%s: wp status = 0x%x\n",
2647 __func__, status);
cd5f6346
KP		 2648
2649 return 0;
2650 }
2651
2652 /* Block lock scheme */
5988af23 2653 for (block = start; block < end + 1; block++) {
20ba89a3
KP		 2654 /* Set block address */
2655 value = onenand_block_address(this, block);
2656 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2657 /* Select DataRAM for DDP */
2658 value = onenand_bufferram_address(this, block);
2659 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 2660 /* Set start block address */
2661 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
08f782b6
KP		 2662 /* Write lock command */
2663 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2664
2665 /* There's no return value */
08f782b6 2666 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2667
2668 /* Sanity check */
2669 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2670 & ONENAND_CTRL_ONGO)
2671 continue;
2672
cd5f6346
KP		 2673 /* Check lock status */
2674 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2675 if (!(status & wp_status_mask))
297758f8
AKS		 2676 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2677 __func__, block, status);
cd5f6346 2678 }
d5c5e78a 2679
cd5f6346
KP		 2680 return 0;
2681}
2682
08f782b6
KP		 2683/**
2684 * onenand_lock - [MTD Interface] Lock block(s)
2685 * @param mtd MTD device structure
2686 * @param ofs offset relative to mtd start
2687 * @param len number of bytes to unlock
2688 *
2689 * Lock one or more blocks
2690 */
69423d99 2691static int onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2692{
34627f0e
AH		 2693 int ret;
2694
2695 onenand_get_device(mtd, FL_LOCKING);
2696 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
2697 onenand_release_device(mtd);
2698 return ret;
08f782b6
KP		 2699}
2700
08f782b6
KP		 2701/**
2702 * onenand_unlock - [MTD Interface] Unlock block(s)
2703 * @param mtd MTD device structure
2704 * @param ofs offset relative to mtd start
2705 * @param len number of bytes to unlock
2706 *
2707 * Unlock one or more blocks
2708 */
69423d99 2709static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2710{
34627f0e
AH		 2711 int ret;
2712
2713 onenand_get_device(mtd, FL_LOCKING);
2714 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2715 onenand_release_device(mtd);
2716 return ret;
08f782b6
KP		 2717}
2718
28b79ff9
KP		 2719/**
2720 * onenand_check_lock_status - [OneNAND Interface] Check lock status
2721 * @param this onenand chip data structure
2722 *
2723 * Check lock status
2724 */
66a10506 2725static int onenand_check_lock_status(struct onenand_chip *this)
28b79ff9
KP		 2726{
2727 unsigned int value, block, status;
2728 unsigned int end;
2729
2730 end = this->chipsize >> this->erase_shift;
2731 for (block = 0; block < end; block++) {
2732 /* Set block address */
2733 value = onenand_block_address(this, block);
2734 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2735 /* Select DataRAM for DDP */
2736 value = onenand_bufferram_address(this, block);
2737 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
2738 /* Set start block address */
2739 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2740
2741 /* Check lock status */
2742 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
66a10506 2743 if (!(status & ONENAND_WP_US)) {
297758f8
AKS		 2744 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2745 __func__, block, status);
66a10506
KP		 2746 return 0;
2747 }
28b79ff9 2748 }
66a10506
KP		 2749
2750 return 1;
28b79ff9
KP		 2751}
2752
2753/**
2754 * onenand_unlock_all - [OneNAND Interface] unlock all blocks
2755 * @param mtd MTD device structure
2756 *
2757 * Unlock all blocks
2758 */
66a10506 2759static void onenand_unlock_all(struct mtd_info *mtd)
28b79ff9
KP		 2760{
2761 struct onenand_chip *this = mtd->priv;
66a10506 2762 loff_t ofs = 0;
5988af23 2763 loff_t len = mtd->size;
28b79ff9
KP		 2764
2765 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
10b7a2bd
KP		 2766 /* Set start block address */
2767 this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
28b79ff9
KP		 2768 /* Write unlock command */
2769 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
2770
2771 /* There's no return value */
08f782b6 2772 this->wait(mtd, FL_LOCKING);
28b79ff9
KP		 2773
2774 /* Sanity check */
2775 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2776 & ONENAND_CTRL_ONGO)
2777 continue;
2778
31bb999e
KP		 2779 /* Don't check lock status */
2780 if (this->options & ONENAND_SKIP_UNLOCK_CHECK)
2781 return;
2782
66a10506
KP		 2783 /* Check lock status */
2784 if (onenand_check_lock_status(this))
2785 return;
2786
28b79ff9 2787 /* Workaround for all block unlock in DDP */
5988af23 2788 if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
66a10506
KP		 2789 /* All blocks on another chip */
2790 ofs = this->chipsize >> 1;
2791 len = this->chipsize >> 1;
28b79ff9 2792 }
28b79ff9
KP		 2793 }
2794
66a10506 2795 onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
28b79ff9
KP		 2796}
2797
493c6460
KP		 2798#ifdef CONFIG_MTD_ONENAND_OTP
2799
3cf60253
AKS		 2800/**
2801 * onenand_otp_command - Send OTP specific command to OneNAND device
2802 * @param mtd MTD device structure
2803 * @param cmd the command to be sent
2804 * @param addr offset to read from or write to
2805 * @param len number of bytes to read or write
2806 */
2807static int onenand_otp_command(struct mtd_info *mtd, int cmd, loff_t addr,
2808 size_t len)
2809{
2810 struct onenand_chip *this = mtd->priv;
2811 int value, block, page;
2812
2813 /* Address translation */
2814 switch (cmd) {
2815 case ONENAND_CMD_OTP_ACCESS:
2816 block = (int) (addr >> this->erase_shift);
2817 page = -1;
2818 break;
2819
2820 default:
2821 block = (int) (addr >> this->erase_shift);
2822 page = (int) (addr >> this->page_shift);
2823
2824 if (ONENAND_IS_2PLANE(this)) {
2825 /* Make the even block number */
2826 block &= ~1;
2827 /* Is it the odd plane? */
2828 if (addr & this->writesize)
2829 block++;
2830 page >>= 1;
2831 }
2832 page &= this->page_mask;
2833 break;
2834 }
2835
2836 if (block != -1) {
2837 /* Write 'DFS, FBA' of Flash */
2838 value = onenand_block_address(this, block);
2839 this->write_word(value, this->base +
2840 ONENAND_REG_START_ADDRESS1);
2841 }
2842
2843 if (page != -1) {
2844 /* Now we use page size operation */
2845 int sectors = 4, count = 4;
2846 int dataram;
2847
2848 switch (cmd) {
2849 default:
2850 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
2851 cmd = ONENAND_CMD_2X_PROG;
2852 dataram = ONENAND_CURRENT_BUFFERRAM(this);
2853 break;
2854 }
2855
2856 /* Write 'FPA, FSA' of Flash */
2857 value = onenand_page_address(page, sectors);
2858 this->write_word(value, this->base +
2859 ONENAND_REG_START_ADDRESS8);
2860
2861 /* Write 'BSA, BSC' of DataRAM */
2862 value = onenand_buffer_address(dataram, sectors, count);
2863 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
2864 }
2865
2866 /* Interrupt clear */
2867 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
2868
2869 /* Write command */
2870 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
2871
2872 return 0;
2873}
2874
2875/**
2876 * onenand_otp_write_oob_nolock - [Internal] OneNAND write out-of-band, specific to OTP
2877 * @param mtd MTD device structure
2878 * @param to offset to write to
2879 * @param len number of bytes to write
2880 * @param retlen pointer to variable to store the number of written bytes
2881 * @param buf the data to write
2882 *
2883 * OneNAND write out-of-band only for OTP
2884 */
2885static int onenand_otp_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2886 struct mtd_oob_ops *ops)
2887{
2888 struct onenand_chip *this = mtd->priv;
2889 int column, ret = 0, oobsize;
2890 int written = 0;
2891 u_char *oobbuf;
2892 size_t len = ops->ooblen;
2893 const u_char *buf = ops->oobbuf;
2894 int block, value, status;
2895
2896 to += ops->ooboffs;
2897
2898 /* Initialize retlen, in case of early exit */
2899 ops->oobretlen = 0;
2900
2901 oobsize = mtd->oobsize;
2902
2903 column = to & (mtd->oobsize - 1);
2904
2905 oobbuf = this->oob_buf;
2906
2907 /* Loop until all data write */
2908 while (written < len) {
2909 int thislen = min_t(int, oobsize, len - written);
2910
2911 cond_resched();
2912
2913 block = (int) (to >> this->erase_shift);
2914 /*
2915 * Write 'DFS, FBA' of Flash
2916 * Add: F100h DQ=DFS, FBA
2917 */
2918
2919 value = onenand_block_address(this, block);
2920 this->write_word(value, this->base +
2921 ONENAND_REG_START_ADDRESS1);
2922
2923 /*
2924 * Select DataRAM for DDP
2925 * Add: F101h DQ=DBS
2926 */
2927
2928 value = onenand_bufferram_address(this, block);
2929 this->write_word(value, this->base +
2930 ONENAND_REG_START_ADDRESS2);
2931 ONENAND_SET_NEXT_BUFFERRAM(this);
2932
2933 /*
2934 * Enter OTP access mode
2935 */
2936 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2937 this->wait(mtd, FL_OTPING);
2938
2939 /* We send data to spare ram with oobsize
2940 * to prevent byte access */
2941 memcpy(oobbuf + column, buf, thislen);
2942
2943 /*
2944 * Write Data into DataRAM
2945 * Add: 8th Word
2946 * in sector0/spare/page0
2947 * DQ=XXFCh
2948 */
2949 this->write_bufferram(mtd, ONENAND_SPARERAM,
2950 oobbuf, 0, mtd->oobsize);
2951
2952 onenand_otp_command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
2953 onenand_update_bufferram(mtd, to, 0);
2954 if (ONENAND_IS_2PLANE(this)) {
2955 ONENAND_SET_BUFFERRAM1(this);
2956 onenand_update_bufferram(mtd, to + this->writesize, 0);
2957 }
2958
2959 ret = this->wait(mtd, FL_WRITING);
2960 if (ret) {
2961 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
2962 break;
2963 }
2964
2965 /* Exit OTP access mode */
2966 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2967 this->wait(mtd, FL_RESETING);
2968
2969 status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
2970 status &= 0x60;
2971
2972 if (status == 0x60) {
2973 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2974 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2975 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
2976 } else if (status == 0x20) {
2977 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2978 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2979 printk(KERN_DEBUG "OTP Block\tUN-LOCKED\n");
2980 } else if (status == 0x40) {
2981 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2982 printk(KERN_DEBUG "1st Block\tUN-LOCKED\n");
2983 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
2984 } else {
2985 printk(KERN_DEBUG "Reboot to check\n");
2986 }
2987
2988 written += thislen;
2989 if (written == len)
2990 break;
2991
2992 to += mtd->writesize;
2993 buf += thislen;
2994 column = 0;
2995 }
2996
2997 ops->oobretlen = written;
2998
2999 return ret;
3000}
3001
492e1501 3002/* Internal OTP operation */
493c6460
KP		 3003typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len,
3004 size_t *retlen, u_char *buf);
3005
3006/**
3007 * do_otp_read - [DEFAULT] Read OTP block area
3008 * @param mtd MTD device structure
3009 * @param from The offset to read
3010 * @param len number of bytes to read
3011 * @param retlen pointer to variable to store the number of readbytes
3012 * @param buf the databuffer to put/get data
3013 *
3014 * Read OTP block area.
3015 */
3016static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
3017 size_t *retlen, u_char *buf)
3018{
3019 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 3020 struct mtd_oob_ops ops = {
3021 .len = len,
3022 .ooblen = 0,
3023 .datbuf = buf,
3024 .oobbuf = NULL,
3025 };
493c6460
KP		 3026 int ret;
3027
3028 /* Enter OTP access mode */
3029 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3030 this->wait(mtd, FL_OTPING);
3031
6a88c47b 3032 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 3033 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
3034 onenand_read_ops_nolock(mtd, from, &ops);
493c6460
KP		 3035
3036 /* Exit OTP access mode */
3037 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3038 this->wait(mtd, FL_RESETING);
3039
3040 return ret;
3041}
3042
3043/**
3044 * do_otp_write - [DEFAULT] Write OTP block area
3045 * @param mtd MTD device structure
49dc08ee 3046 * @param to The offset to write
493c6460
KP		 3047 * @param len number of bytes to write
3048 * @param retlen pointer to variable to store the number of write bytes
3049 * @param buf the databuffer to put/get data
3050 *
3051 * Write OTP block area.
3052 */
49dc08ee 3053static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
493c6460
KP		 3054 size_t *retlen, u_char *buf)
3055{
3056 struct onenand_chip *this = mtd->priv;
3057 unsigned char *pbuf = buf;
3058 int ret;
49dc08ee 3059 struct mtd_oob_ops ops;
493c6460
KP		 3060
3061 /* Force buffer page aligned */
28318776 3062 if (len < mtd->writesize) {
493c6460 3063 memcpy(this->page_buf, buf, len);
28318776 3064 memset(this->page_buf + len, 0xff, mtd->writesize - len);
493c6460 3065 pbuf = this->page_buf;
28318776 3066 len = mtd->writesize;
493c6460
KP		 3067 }
3068
3069 /* Enter OTP access mode */
3070 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3071 this->wait(mtd, FL_OTPING);
3072
49dc08ee
AB		 3073 ops.len = len;
3074 ops.ooblen = 0;
1437085c 3075 ops.datbuf = pbuf;
49dc08ee
AB		 3076 ops.oobbuf = NULL;
3077 ret = onenand_write_ops_nolock(mtd, to, &ops);
3078 *retlen = ops.retlen;
493c6460
KP		 3079
3080 /* Exit OTP access mode */
3081 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3082 this->wait(mtd, FL_RESETING);
3083
3084 return ret;
3085}
3086
3087/**
3088 * do_otp_lock - [DEFAULT] Lock OTP block area
3089 * @param mtd MTD device structure
3090 * @param from The offset to lock
3091 * @param len number of bytes to lock
3092 * @param retlen pointer to variable to store the number of lock bytes
3093 * @param buf the databuffer to put/get data
3094 *
3095 * Lock OTP block area.
3096 */
3097static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len,
3098 size_t *retlen, u_char *buf)
3099{
3100 struct onenand_chip *this = mtd->priv;
5988af23 3101 struct mtd_oob_ops ops;
493c6460
KP		 3102 int ret;
3103
5988af23 3104 if (FLEXONENAND(this)) {
3cf60253
AKS		 3105
3106 /* Enter OTP access mode */
3107 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3108 this->wait(mtd, FL_OTPING);
5988af23
RH		 3109 /*
3110 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3111 * main area of page 49.
3112 */
3113 ops.len = mtd->writesize;
3114 ops.ooblen = 0;
3115 ops.datbuf = buf;
3116 ops.oobbuf = NULL;
3117 ret = onenand_write_ops_nolock(mtd, mtd->writesize * 49, &ops);
3118 *retlen = ops.retlen;
3cf60253
AKS		 3119
3120 /* Exit OTP access mode */
3121 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3122 this->wait(mtd, FL_RESETING);
5988af23
RH		 3123 } else {
3124 ops.mode = MTD_OOB_PLACE;
3125 ops.ooblen = len;
3126 ops.oobbuf = buf;
3127 ops.ooboffs = 0;
3cf60253 3128 ret = onenand_otp_write_oob_nolock(mtd, from, &ops);
5988af23
RH		 3129 *retlen = ops.oobretlen;
3130 }
493c6460 3131
493c6460
KP		 3132 return ret;
3133}
3134
3135/**
3136 * onenand_otp_walk - [DEFAULT] Handle OTP operation
3137 * @param mtd MTD device structure
3138 * @param from The offset to read/write
3139 * @param len number of bytes to read/write
3140 * @param retlen pointer to variable to store the number of read bytes
3141 * @param buf the databuffer to put/get data
3142 * @param action do given action
3143 * @param mode specify user and factory
3144 *
3145 * Handle OTP operation.
3146 */
3147static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
3148 size_t *retlen, u_char *buf,
3149 otp_op_t action, int mode)
3150{
3151 struct onenand_chip *this = mtd->priv;
3152 int otp_pages;
3153 int density;
3154 int ret = 0;
3155
3156 *retlen = 0;
3157
e71f04fc 3158 density = onenand_get_density(this->device_id);
493c6460
KP		 3159 if (density < ONENAND_DEVICE_DENSITY_512Mb)
3160 otp_pages = 20;
3161 else
3cf60253 3162 otp_pages = 50;
493c6460
KP		 3163
3164 if (mode == MTD_OTP_FACTORY) {
28318776 3165 from += mtd->writesize * otp_pages;
3cf60253 3166 otp_pages = ONENAND_PAGES_PER_BLOCK - otp_pages;
493c6460
KP		 3167 }
3168
3169 /* Check User/Factory boundary */
3cf60253 3170 if (mode == MTD_OTP_USER) {
0a032a4d 3171 if (mtd->writesize * otp_pages < from + len)
3cf60253
AKS		 3172 return 0;
3173 } else {
0a032a4d 3174 if (mtd->writesize * otp_pages < len)
3cf60253
AKS		 3175 return 0;
3176 }
493c6460 3177
49dc08ee 3178 onenand_get_device(mtd, FL_OTPING);
493c6460
KP		 3179 while (len > 0 && otp_pages > 0) {
3180 if (!action) { /* OTP Info functions */
3181 struct otp_info *otpinfo;
3182
3183 len -= sizeof(struct otp_info);
49dc08ee
AB		 3184 if (len <= 0) {
3185 ret = -ENOSPC;
3186 break;
3187 }
493c6460
KP		 3188
3189 otpinfo = (struct otp_info *) buf;
3190 otpinfo->start = from;
28318776 3191 otpinfo->length = mtd->writesize;
493c6460
KP		 3192 otpinfo->locked = 0;
3193
28318776 3194 from += mtd->writesize;
493c6460
KP		 3195 buf += sizeof(struct otp_info);
3196 *retlen += sizeof(struct otp_info);
3197 } else {
3198 size_t tmp_retlen;
493c6460
KP		 3199
3200 ret = action(mtd, from, len, &tmp_retlen, buf);
3201
3cf60253
AKS		 3202 buf += tmp_retlen;
3203 len -= tmp_retlen;
3204 *retlen += tmp_retlen;
493c6460 3205
49dc08ee
AB		 3206 if (ret)
3207 break;
493c6460
KP		 3208 }
3209 otp_pages--;
3210 }
49dc08ee 3211 onenand_release_device(mtd);
493c6460 3212
49dc08ee 3213 return ret;
493c6460
KP		 3214}
3215
3216/**
3217 * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info
3218 * @param mtd MTD device structure
3219 * @param buf the databuffer to put/get data
3220 * @param len number of bytes to read
3221 *
3222 * Read factory OTP info.
3223 */
3224static int onenand_get_fact_prot_info(struct mtd_info *mtd,
3225 struct otp_info *buf, size_t len)
3226{
3227 size_t retlen;
3228 int ret;
3229
3230 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY);
3231
3232 return ret ? : retlen;
3233}
3234
3235/**
3236 * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area
3237 * @param mtd MTD device structure
3238 * @param from The offset to read
3239 * @param len number of bytes to read
3240 * @param retlen pointer to variable to store the number of read bytes
3241 * @param buf the databuffer to put/get data
3242 *
3243 * Read factory OTP area.
3244 */
3245static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
3246 size_t len, size_t *retlen, u_char *buf)
3247{
3248 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY);
3249}
3250
3251/**
3252 * onenand_get_user_prot_info - [MTD Interface] Read user OTP info
3253 * @param mtd MTD device structure
3254 * @param buf the databuffer to put/get data
3255 * @param len number of bytes to read
3256 *
3257 * Read user OTP info.
3258 */
3259static int onenand_get_user_prot_info(struct mtd_info *mtd,
3260 struct otp_info *buf, size_t len)
3261{
3262 size_t retlen;
3263 int ret;
3264
3265 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER);
3266
3267 return ret ? : retlen;
3268}
3269
3270/**
3271 * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area
3272 * @param mtd MTD device structure
3273 * @param from The offset to read
3274 * @param len number of bytes to read
3275 * @param retlen pointer to variable to store the number of read bytes
3276 * @param buf the databuffer to put/get data
3277 *
3278 * Read user OTP area.
3279 */
3280static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
3281 size_t len, size_t *retlen, u_char *buf)
3282{
3283 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER);
3284}
3285
3286/**
3287 * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area
3288 * @param mtd MTD device structure
3289 * @param from The offset to write
3290 * @param len number of bytes to write
3291 * @param retlen pointer to variable to store the number of write bytes
3292 * @param buf the databuffer to put/get data
3293 *
3294 * Write user OTP area.
3295 */
3296static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
3297 size_t len, size_t *retlen, u_char *buf)
3298{
3299 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER);
3300}
3301
3302/**
3303 * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area
3304 * @param mtd MTD device structure
3305 * @param from The offset to lock
3306 * @param len number of bytes to unlock
3307 *
3308 * Write lock mark on spare area in page 0 in OTP block
3309 */
3310static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
3311 size_t len)
3312{
69d79186 3313 struct onenand_chip *this = mtd->priv;
5988af23 3314 u_char *buf = FLEXONENAND(this) ? this->page_buf : this->oob_buf;
493c6460
KP		 3315 size_t retlen;
3316 int ret;
3cf60253 3317 unsigned int otp_lock_offset = ONENAND_OTP_LOCK_OFFSET;
493c6460 3318
5988af23
RH		 3319 memset(buf, 0xff, FLEXONENAND(this) ? this->writesize
3320 : mtd->oobsize);
493c6460
KP		 3321 /*
3322 * Write lock mark to 8th word of sector0 of page0 of the spare0.
3323 * We write 16 bytes spare area instead of 2 bytes.
5988af23
RH		 3324 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3325 * main area of page 49.
493c6460 3326 */
5988af23 3327
493c6460 3328 from = 0;
5988af23 3329 len = FLEXONENAND(this) ? mtd->writesize : 16;
493c6460 3330
3cf60253
AKS		 3331 /*
3332 * Note: OTP lock operation
3333 * OTP block : 0xXXFC XX 1111 1100
3334 * 1st block : 0xXXF3 (If chip support) XX 1111 0011
3335 * Both : 0xXXF0 (If chip support) XX 1111 0000
3336 */
3337 if (FLEXONENAND(this))
3338 otp_lock_offset = FLEXONENAND_OTP_LOCK_OFFSET;
3339
3340 /* ONENAND_OTP_AREA | ONENAND_OTP_BLOCK0 | ONENAND_OTP_AREA_BLOCK0 */
3341 if (otp == 1)
3342 buf[otp_lock_offset] = 0xFC;
3343 else if (otp == 2)
3344 buf[otp_lock_offset] = 0xF3;
3345 else if (otp == 3)
3346 buf[otp_lock_offset] = 0xF0;
3347 else if (otp != 0)
3348 printk(KERN_DEBUG "[OneNAND] Invalid option selected for OTP\n");
3349
5988af23 3350 ret = onenand_otp_walk(mtd, from, len, &retlen, buf, do_otp_lock, MTD_OTP_USER);
493c6460
KP		 3351
3352 return ret ? : retlen;
3353}
3cf60253 3354
493c6460
KP		 3355#endif /* CONFIG_MTD_ONENAND_OTP */
3356
28b79ff9 3357/**
75384b0d 3358 * onenand_check_features - Check and set OneNAND features
28b79ff9
KP		 3359 * @param mtd MTD data structure
3360 *
75384b0d
KP		 3361 * Check and set OneNAND features
3362 * - lock scheme
ee9745fc 3363 * - two plane
28b79ff9 3364 */
75384b0d 3365static void onenand_check_features(struct mtd_info *mtd)
28b79ff9
KP		 3366{
3367 struct onenand_chip *this = mtd->priv;
edb44b9b 3368 unsigned int density, process, numbufs;
28b79ff9
KP		 3369
3370 /* Lock scheme depends on density and process */
e71f04fc 3371 density = onenand_get_density(this->device_id);
28b79ff9 3372 process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
edb44b9b 3373 numbufs = this->read_word(this->base + ONENAND_REG_NUM_BUFFERS) >> 8;
28b79ff9
KP		 3374
3375 /* Lock scheme */
ee9745fc
KP		 3376 switch (density) {
3377 case ONENAND_DEVICE_DENSITY_4Gb:
6a88c47b
KP		 3378 if (ONENAND_IS_DDP(this))
3379 this->options |= ONENAND_HAS_2PLANE;
edb44b9b 3380 else if (numbufs == 1)
6a88c47b 3381 this->options |= ONENAND_HAS_4KB_PAGE;
ee9745fc
KP		 3382
3383 case ONENAND_DEVICE_DENSITY_2Gb:
492e1501 3384 /* 2Gb DDP does not have 2 plane */
ee9745fc
KP		 3385 if (!ONENAND_IS_DDP(this))
3386 this->options |= ONENAND_HAS_2PLANE;
3387 this->options |= ONENAND_HAS_UNLOCK_ALL;
3388
3389 case ONENAND_DEVICE_DENSITY_1Gb:
28b79ff9 3390 /* A-Die has all block unlock */
ee9745fc 3391 if (process)
28b79ff9 3392 this->options |= ONENAND_HAS_UNLOCK_ALL;
ee9745fc
KP		 3393 break;
3394
3395 default:
3396 /* Some OneNAND has continuous lock scheme */
3397 if (!process)
28b79ff9 3398 this->options |= ONENAND_HAS_CONT_LOCK;
ee9745fc 3399 break;
28b79ff9 3400 }
ee9745fc 3401
6a88c47b 3402 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3403 this->options &= ~ONENAND_HAS_2PLANE;
3404
3405 if (FLEXONENAND(this)) {
3406 this->options &= ~ONENAND_HAS_CONT_LOCK;
3407 this->options |= ONENAND_HAS_UNLOCK_ALL;
3408 }
3409
ee9745fc
KP		 3410 if (this->options & ONENAND_HAS_CONT_LOCK)
3411 printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
3412 if (this->options & ONENAND_HAS_UNLOCK_ALL)
3413 printk(KERN_DEBUG "Chip support all block unlock\n");
3414 if (this->options & ONENAND_HAS_2PLANE)
3415 printk(KERN_DEBUG "Chip has 2 plane\n");
6a88c47b
KP		 3416 if (this->options & ONENAND_HAS_4KB_PAGE)
3417 printk(KERN_DEBUG "Chip has 4KiB pagesize\n");
28b79ff9
KP		 3418}
3419
cd5f6346 3420/**
e3da8067 3421 * onenand_print_device_info - Print device & version ID
cd5f6346 3422 * @param device device ID
e3da8067 3423 * @param version version ID
cd5f6346 3424 *
e3da8067 3425 * Print device & version ID
cd5f6346 3426 */
28b79ff9 3427static void onenand_print_device_info(int device, int version)
cd5f6346 3428{
5988af23 3429 int vcc, demuxed, ddp, density, flexonenand;
cd5f6346
KP		 3430
3431 vcc = device & ONENAND_DEVICE_VCC_MASK;
3432 demuxed = device & ONENAND_DEVICE_IS_DEMUX;
3433 ddp = device & ONENAND_DEVICE_IS_DDP;
e71f04fc 3434 density = onenand_get_density(device);
5988af23
RH		 3435 flexonenand = device & DEVICE_IS_FLEXONENAND;
3436 printk(KERN_INFO "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
3437 demuxed ? "" : "Muxed ",
3438 flexonenand ? "Flex-" : "",
cd5f6346
KP		 3439 ddp ? "(DDP)" : "",
3440 (16 << density),
3441 vcc ? "2.65/3.3" : "1.8",
3442 device);
49dc08ee 3443 printk(KERN_INFO "OneNAND version = 0x%04x\n", version);
cd5f6346
KP		 3444}
3445
3446static const struct onenand_manufacturers onenand_manuf_ids[] = {
3447 {ONENAND_MFR_SAMSUNG, "Samsung"},
ee8f3768 3448 {ONENAND_MFR_NUMONYX, "Numonyx"},
cd5f6346
KP		 3449};
3450
3451/**
3452 * onenand_check_maf - Check manufacturer ID
3453 * @param manuf manufacturer ID
3454 *
3455 * Check manufacturer ID
3456 */
3457static int onenand_check_maf(int manuf)
3458{
37b1cc39
KP		 3459 int size = ARRAY_SIZE(onenand_manuf_ids);
3460 char *name;
cd5f6346
KP		 3461 int i;
3462
37b1cc39 3463 for (i = 0; i < size; i++)
cd5f6346
KP		 3464 if (manuf == onenand_manuf_ids[i].id)
3465 break;
cd5f6346 3466
37b1cc39
KP		 3467 if (i < size)
3468 name = onenand_manuf_ids[i].name;
3469 else
3470 name = "Unknown";
3471
3472 printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
cd5f6346 3473
37b1cc39 3474 return (i == size);
cd5f6346
KP		 3475}
3476
5988af23
RH		 3477/**
3478* flexonenand_get_boundary - Reads the SLC boundary
3479* @param onenand_info - onenand info structure
3480**/
3481static int flexonenand_get_boundary(struct mtd_info *mtd)
3482{
3483 struct onenand_chip *this = mtd->priv;
3484 unsigned die, bdry;
3485 int ret, syscfg, locked;
3486
3487 /* Disable ECC */
3488 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3489 this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
3490
3491 for (die = 0; die < this->dies; die++) {
3492 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3493 this->wait(mtd, FL_SYNCING);
3494
3495 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3496 ret = this->wait(mtd, FL_READING);
3497
3498 bdry = this->read_word(this->base + ONENAND_DATARAM);
3499 if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
3500 locked = 0;
3501 else
3502 locked = 1;
3503 this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
3504
3505 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3506 ret = this->wait(mtd, FL_RESETING);
3507
3508 printk(KERN_INFO "Die %d boundary: %d%s\n", die,
3509 this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
3510 }
3511
3512 /* Enable ECC */
3513 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3514 return 0;
3515}
3516
3517/**
3518 * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
3519 * boundary[], diesize[], mtd->size, mtd->erasesize
3520 * @param mtd - MTD device structure
3521 */
3522static void flexonenand_get_size(struct mtd_info *mtd)
3523{
3524 struct onenand_chip *this = mtd->priv;
3525 int die, i, eraseshift, density;
3526 int blksperdie, maxbdry;
3527 loff_t ofs;
3528
3529 density = onenand_get_density(this->device_id);
3530 blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
3531 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3532 maxbdry = blksperdie - 1;
3533 eraseshift = this->erase_shift - 1;
3534
3535 mtd->numeraseregions = this->dies << 1;
3536
3537 /* This fills up the device boundary */
3538 flexonenand_get_boundary(mtd);
3539 die = ofs = 0;
3540 i = -1;
3541 for (; die < this->dies; die++) {
3542 if (!die || this->boundary[die-1] != maxbdry) {
3543 i++;
3544 mtd->eraseregions[i].offset = ofs;
3545 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3546 mtd->eraseregions[i].numblocks =
3547 this->boundary[die] + 1;
3548 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3549 eraseshift++;
3550 } else {
3551 mtd->numeraseregions -= 1;
3552 mtd->eraseregions[i].numblocks +=
3553 this->boundary[die] + 1;
3554 ofs += (this->boundary[die] + 1) << (eraseshift - 1);
3555 }
3556 if (this->boundary[die] != maxbdry) {
3557 i++;
3558 mtd->eraseregions[i].offset = ofs;
3559 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3560 mtd->eraseregions[i].numblocks = maxbdry ^
3561 this->boundary[die];
3562 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3563 eraseshift--;
3564 } else
3565 mtd->numeraseregions -= 1;
3566 }
3567
3568 /* Expose MLC erase size except when all blocks are SLC */
3569 mtd->erasesize = 1 << this->erase_shift;
3570 if (mtd->numeraseregions == 1)
3571 mtd->erasesize >>= 1;
3572
3573 printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
3574 for (i = 0; i < mtd->numeraseregions; i++)
3575 printk(KERN_INFO "[offset: 0x%08x, erasesize: 0x%05x,"
3576 " numblocks: %04u]\n",
3577 (unsigned int) mtd->eraseregions[i].offset,
3578 mtd->eraseregions[i].erasesize,
3579 mtd->eraseregions[i].numblocks);
3580
3581 for (die = 0, mtd->size = 0; die < this->dies; die++) {
3582 this->diesize[die] = (loff_t)blksperdie << this->erase_shift;
3583 this->diesize[die] -= (loff_t)(this->boundary[die] + 1)
3584 << (this->erase_shift - 1);
3585 mtd->size += this->diesize[die];
3586 }
3587}
3588
3589/**
3590 * flexonenand_check_blocks_erased - Check if blocks are erased
3591 * @param mtd_info - mtd info structure
3592 * @param start - first erase block to check
3593 * @param end - last erase block to check
3594 *
3595 * Converting an unerased block from MLC to SLC
3596 * causes byte values to change. Since both data and its ECC
3597 * have changed, reads on the block give uncorrectable error.
3598 * This might lead to the block being detected as bad.
3599 *
3600 * Avoid this by ensuring that the block to be converted is
3601 * erased.
3602 */
3603static int flexonenand_check_blocks_erased(struct mtd_info *mtd, int start, int end)
3604{
3605 struct onenand_chip *this = mtd->priv;
3606 int i, ret;
3607 int block;
3608 struct mtd_oob_ops ops = {
3609 .mode = MTD_OOB_PLACE,
3610 .ooboffs = 0,
3611 .ooblen = mtd->oobsize,
3612 .datbuf = NULL,
3613 .oobbuf = this->oob_buf,
3614 };
3615 loff_t addr;
3616
3617 printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
3618
3619 for (block = start; block <= end; block++) {
3620 addr = flexonenand_addr(this, block);
3621 if (onenand_block_isbad_nolock(mtd, addr, 0))
3622 continue;
3623
3624 /*
3625 * Since main area write results in ECC write to spare,
3626 * it is sufficient to check only ECC bytes for change.
3627 */
3628 ret = onenand_read_oob_nolock(mtd, addr, &ops);
3629 if (ret)
3630 return ret;
3631
3632 for (i = 0; i < mtd->oobsize; i++)
3633 if (this->oob_buf[i] != 0xff)
3634 break;
3635
3636 if (i != mtd->oobsize) {
297758f8
AKS		 3637 printk(KERN_WARNING "%s: Block %d not erased.\n",
3638 __func__, block);
5988af23
RH		 3639 return 1;
3640 }
3641 }
3642
3643 return 0;
3644}
3645
3646/**
3647 * flexonenand_set_boundary - Writes the SLC boundary
3648 * @param mtd - mtd info structure
3649 */
3650int flexonenand_set_boundary(struct mtd_info *mtd, int die,
3651 int boundary, int lock)
3652{
3653 struct onenand_chip *this = mtd->priv;
3654 int ret, density, blksperdie, old, new, thisboundary;
3655 loff_t addr;
3656
3657 /* Change only once for SDP Flex-OneNAND */
3658 if (die && (!ONENAND_IS_DDP(this)))
3659 return 0;
3660
3661 /* boundary value of -1 indicates no required change */
3662 if (boundary < 0 || boundary == this->boundary[die])
3663 return 0;
3664
3665 density = onenand_get_density(this->device_id);
3666 blksperdie = ((16 << density) << 20) >> this->erase_shift;
3667 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3668
3669 if (boundary >= blksperdie) {
297758f8
AKS		 3670 printk(KERN_ERR "%s: Invalid boundary value. "
3671 "Boundary not changed.\n", __func__);
5988af23
RH		 3672 return -EINVAL;
3673 }
3674
3675 /* Check if converting blocks are erased */
3676 old = this->boundary[die] + (die * this->density_mask);
3677 new = boundary + (die * this->density_mask);
3678 ret = flexonenand_check_blocks_erased(mtd, min(old, new) + 1, max(old, new));
3679 if (ret) {
297758f8
AKS		 3680 printk(KERN_ERR "%s: Please erase blocks "
3681 "before boundary change\n", __func__);
5988af23
RH		 3682 return ret;
3683 }
3684
3685 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3686 this->wait(mtd, FL_SYNCING);
3687
3688 /* Check is boundary is locked */
3689 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3690 ret = this->wait(mtd, FL_READING);
3691
3692 thisboundary = this->read_word(this->base + ONENAND_DATARAM);
3693 if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
297758f8 3694 printk(KERN_ERR "%s: boundary locked\n", __func__);
5988af23
RH		 3695 ret = 1;
3696 goto out;
3697 }
3698
297758f8 3699 printk(KERN_INFO "Changing die %d boundary: %d%s\n",
5988af23
RH		 3700 die, boundary, lock ? "(Locked)" : "(Unlocked)");
3701
3702 addr = die ? this->diesize[0] : 0;
3703
3704 boundary &= FLEXONENAND_PI_MASK;
3705 boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
3706
3707 this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
3708 ret = this->wait(mtd, FL_ERASING);
3709 if (ret) {
f369c7ec
MK		 3710 printk(KERN_ERR "%s: Failed PI erase for Die %d\n",
3711 __func__, die);
5988af23
RH		 3712 goto out;
3713 }
3714
3715 this->write_word(boundary, this->base + ONENAND_DATARAM);
3716 this->command(mtd, ONENAND_CMD_PROG, addr, 0);
3717 ret = this->wait(mtd, FL_WRITING);
3718 if (ret) {
297758f8
AKS		 3719 printk(KERN_ERR "%s: Failed PI write for Die %d\n",
3720 __func__, die);
5988af23
RH		 3721 goto out;
3722 }
3723
3724 this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
3725 ret = this->wait(mtd, FL_WRITING);
3726out:
3727 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
3728 this->wait(mtd, FL_RESETING);
3729 if (!ret)
3730 /* Recalculate device size on boundary change*/
3731 flexonenand_get_size(mtd);
3732
3733 return ret;
3734}
3735
cd5f6346 3736/**
ad0d363b 3737 * onenand_chip_probe - [OneNAND Interface] The generic chip probe
cd5f6346
KP		 3738 * @param mtd MTD device structure
3739 *
3740 * OneNAND detection method:
59c51591 3741 * Compare the values from command with ones from register
cd5f6346 3742 */
ad0d363b 3743static int onenand_chip_probe(struct mtd_info *mtd)
cd5f6346
KP		 3744{
3745 struct onenand_chip *this = mtd->priv;
ad0d363b 3746 int bram_maf_id, bram_dev_id, maf_id, dev_id;
47e777e0
KP		 3747 int syscfg;
3748
3749 /* Save system configuration 1 */
3750 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3751 /* Clear Sync. Burst Read mode to read BootRAM */
ee8f3768 3752 this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE), this->base + ONENAND_REG_SYS_CFG1);
cd5f6346
KP		 3753
3754 /* Send the command for reading device ID from BootRAM */
3755 this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
3756
3757 /* Read manufacturer and device IDs from BootRAM */
3758 bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
3759 bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
3760
47e777e0
KP		 3761 /* Reset OneNAND to read default register values */
3762 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
3763 /* Wait reset */
3764 this->wait(mtd, FL_RESETING);
3765
3766 /* Restore system configuration 1 */
3767 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3768
cd5f6346
KP		 3769 /* Check manufacturer ID */
3770 if (onenand_check_maf(bram_maf_id))
3771 return -ENXIO;
3772
cd5f6346
KP		 3773 /* Read manufacturer and device IDs from Register */
3774 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3775 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
3776
3777 /* Check OneNAND device */
3778 if (maf_id != bram_maf_id || dev_id != bram_dev_id)
3779 return -ENXIO;
3780
ad0d363b
KP		 3781 return 0;
3782}
3783
3784/**
3785 * onenand_probe - [OneNAND Interface] Probe the OneNAND device
3786 * @param mtd MTD device structure
3787 */
3788static int onenand_probe(struct mtd_info *mtd)
3789{
3790 struct onenand_chip *this = mtd->priv;
3791 int maf_id, dev_id, ver_id;
3792 int density;
3793 int ret;
3794
3795 ret = this->chip_probe(mtd);
3796 if (ret)
3797 return ret;
3798
3799 /* Read manufacturer and device IDs from Register */
3800 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3801 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
3802 ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
3803 this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
3804
cd5f6346 3805 /* Flash device information */
28b79ff9 3806 onenand_print_device_info(dev_id, ver_id);
cd5f6346 3807 this->device_id = dev_id;
28b79ff9 3808 this->version_id = ver_id;
cd5f6346 3809
c37cb56f
KP		 3810 /* Check OneNAND features */
3811 onenand_check_features(mtd);
3812
e71f04fc 3813 density = onenand_get_density(dev_id);
5988af23
RH		 3814 if (FLEXONENAND(this)) {
3815 this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
3816 /* Maximum possible erase regions */
3817 mtd->numeraseregions = this->dies << 1;
3818 mtd->eraseregions = kzalloc(sizeof(struct mtd_erase_region_info)
3819 * (this->dies << 1), GFP_KERNEL);
3820 if (!mtd->eraseregions)
3821 return -ENOMEM;
3822 }
3823
3824 /*
3825 * For Flex-OneNAND, chipsize represents maximum possible device size.
3826 * mtd->size represents the actual device size.
3827 */
cd5f6346
KP		 3828 this->chipsize = (16 << density) << 20;
3829
3830 /* OneNAND page size & block size */
3831 /* The data buffer size is equal to page size */
28318776 3832 mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
5988af23 3833 /* We use the full BufferRAM */
6a88c47b 3834 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3835 mtd->writesize <<= 1;
3836
28318776 3837 mtd->oobsize = mtd->writesize >> 5;
9bfbc9b2 3838 /* Pages per a block are always 64 in OneNAND */
28318776 3839 mtd->erasesize = mtd->writesize << 6;
5988af23
RH		 3840 /*
3841 * Flex-OneNAND SLC area has 64 pages per block.
3842 * Flex-OneNAND MLC area has 128 pages per block.
3843 * Expose MLC erase size to find erase_shift and page_mask.
3844 */
3845 if (FLEXONENAND(this))
3846 mtd->erasesize <<= 1;
cd5f6346
KP		 3847
3848 this->erase_shift = ffs(mtd->erasesize) - 1;
28318776 3849 this->page_shift = ffs(mtd->writesize) - 1;
9bfbc9b2 3850 this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1;
5988af23
RH		 3851 /* Set density mask. it is used for DDP */
3852 if (ONENAND_IS_DDP(this))
3853 this->density_mask = this->chipsize >> (this->erase_shift + 1);
ee9745fc
KP		 3854 /* It's real page size */
3855 this->writesize = mtd->writesize;
cd5f6346 3856
492e1501 3857 /* REVISIT: Multichip handling */
cd5f6346 3858
5988af23
RH		 3859 if (FLEXONENAND(this))
3860 flexonenand_get_size(mtd);
3861 else
3862 mtd->size = this->chipsize;
cd5f6346 3863
ee9745fc
KP		 3864 /*
3865 * We emulate the 4KiB page and 256KiB erase block size
3866 * But oobsize is still 64 bytes.
3867 * It is only valid if you turn on 2X program support,
3868 * Otherwise it will be ignored by compiler.
3869 */
3870 if (ONENAND_IS_2PLANE(this)) {
3871 mtd->writesize <<= 1;
3872 mtd->erasesize <<= 1;
3873 }
3874
cd5f6346
KP		 3875 return 0;
3876}
3877
a41371eb
KP		 3878/**
3879 * onenand_suspend - [MTD Interface] Suspend the OneNAND flash
3880 * @param mtd MTD device structure
3881 */
3882static int onenand_suspend(struct mtd_info *mtd)
3883{
3884 return onenand_get_device(mtd, FL_PM_SUSPENDED);
3885}
3886
3887/**
3888 * onenand_resume - [MTD Interface] Resume the OneNAND flash
3889 * @param mtd MTD device structure
3890 */
3891static void onenand_resume(struct mtd_info *mtd)
3892{
3893 struct onenand_chip *this = mtd->priv;
3894
3895 if (this->state == FL_PM_SUSPENDED)
3896 onenand_release_device(mtd);
3897 else
297758f8
AKS		 3898 printk(KERN_ERR "%s: resume() called for the chip which is not "
3899 "in suspended state\n", __func__);
a41371eb
KP		 3900}
3901
cd5f6346
KP		 3902/**
3903 * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
3904 * @param mtd MTD device structure
3905 * @param maxchips Number of chips to scan for
3906 *
3907 * This fills out all the not initialized function pointers
3908 * with the defaults.
3909 * The flash ID is read and the mtd/chip structures are
3910 * filled with the appropriate values.
3911 */
3912int onenand_scan(struct mtd_info *mtd, int maxchips)
3913{
5988af23 3914 int i, ret;
cd5f6346
KP		 3915 struct onenand_chip *this = mtd->priv;
3916
3917 if (!this->read_word)
3918 this->read_word = onenand_readw;
3919 if (!this->write_word)
3920 this->write_word = onenand_writew;
3921
3922 if (!this->command)
3923 this->command = onenand_command;
3924 if (!this->wait)
2c22120f 3925 onenand_setup_wait(mtd);
31bb999e
KP		 3926 if (!this->bbt_wait)
3927 this->bbt_wait = onenand_bbt_wait;
3928 if (!this->unlock_all)
3929 this->unlock_all = onenand_unlock_all;
cd5f6346 3930
ad0d363b
KP		 3931 if (!this->chip_probe)
3932 this->chip_probe = onenand_chip_probe;
3933
cd5f6346
KP		 3934 if (!this->read_bufferram)
3935 this->read_bufferram = onenand_read_bufferram;
3936 if (!this->write_bufferram)
3937 this->write_bufferram = onenand_write_bufferram;
3938
cdc00130
KP		 3939 if (!this->block_markbad)
3940 this->block_markbad = onenand_default_block_markbad;
3941 if (!this->scan_bbt)
3942 this->scan_bbt = onenand_default_bbt;
3943
cd5f6346
KP		 3944 if (onenand_probe(mtd))
3945 return -ENXIO;
3946
52b0eea7
KP		 3947 /* Set Sync. Burst Read after probing */
3948 if (this->mmcontrol) {
3949 printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
3950 this->read_bufferram = onenand_sync_read_bufferram;
3951 }
3952
532a37cf
KP		 3953 /* Allocate buffers, if necessary */
3954 if (!this->page_buf) {
470bc844 3955 this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL);
532a37cf 3956 if (!this->page_buf) {
297758f8
AKS		 3957 printk(KERN_ERR "%s: Can't allocate page_buf\n",
3958 __func__);
532a37cf
KP		 3959 return -ENOMEM;
3960 }
4a8ce0b0
KP		 3961#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
3962 this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
3963 if (!this->verify_buf) {
3964 kfree(this->page_buf);
3965 return -ENOMEM;
3966 }
3967#endif
532a37cf
KP		 3968 this->options |= ONENAND_PAGEBUF_ALLOC;
3969 }
470bc844
KP		 3970 if (!this->oob_buf) {
3971 this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
3972 if (!this->oob_buf) {
297758f8
AKS		 3973 printk(KERN_ERR "%s: Can't allocate oob_buf\n",
3974 __func__);
470bc844
KP		 3975 if (this->options & ONENAND_PAGEBUF_ALLOC) {
3976 this->options &= ~ONENAND_PAGEBUF_ALLOC;
3977 kfree(this->page_buf);
3978 }
3979 return -ENOMEM;
3980 }
3981 this->options |= ONENAND_OOBBUF_ALLOC;
3982 }
532a37cf 3983
cd5f6346
KP		 3984 this->state = FL_READY;
3985 init_waitqueue_head(&this->wq);
3986 spin_lock_init(&this->chip_lock);
3987
60d84f97
KP		 3988 /*
3989 * Allow subpage writes up to oobsize.
3990 */
cd5f6346 3991 switch (mtd->oobsize) {
5988af23
RH		 3992 case 128:
3993 this->ecclayout = &onenand_oob_128;
3994 mtd->subpage_sft = 0;
3995 break;
cd5f6346 3996 case 64:
5bd34c09 3997 this->ecclayout = &onenand_oob_64;
60d84f97 3998 mtd->subpage_sft = 2;
cd5f6346
KP		 3999 break;
4000
4001 case 32:
5bd34c09 4002 this->ecclayout = &onenand_oob_32;
60d84f97 4003 mtd->subpage_sft = 1;
cd5f6346
KP		 4004 break;
4005
4006 default:
297758f8
AKS		 4007 printk(KERN_WARNING "%s: No OOB scheme defined for oobsize %d\n",
4008 __func__, mtd->oobsize);
60d84f97 4009 mtd->subpage_sft = 0;
cd5f6346 4010 /* To prevent kernel oops */
5bd34c09 4011 this->ecclayout = &onenand_oob_32;
cd5f6346
KP		 4012 break;
4013 }
4014
60d84f97 4015 this->subpagesize = mtd->writesize >> mtd->subpage_sft;
a5e7c7b4
AH		 4016
4017 /*
4018 * The number of bytes available for a client to place data into
4019 * the out of band area
4020 */
4021 this->ecclayout->oobavail = 0;
ad286343
KP		 4022 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
4023 this->ecclayout->oobfree[i].length; i++)
a5e7c7b4
AH		 4024 this->ecclayout->oobavail +=
4025 this->ecclayout->oobfree[i].length;
1f92267c 4026 mtd->oobavail = this->ecclayout->oobavail;
a5e7c7b4 4027
5bd34c09 4028 mtd->ecclayout = this->ecclayout;
d5c5e78a 4029
cd5f6346 4030 /* Fill in remaining MTD driver data */
c7626802 4031 mtd->type = ONENAND_IS_MLC(this) ? MTD_MLCNANDFLASH : MTD_NANDFLASH;
5fa43394 4032 mtd->flags = MTD_CAP_NANDFLASH;
cd5f6346
KP		 4033 mtd->erase = onenand_erase;
4034 mtd->point = NULL;
4035 mtd->unpoint = NULL;
4036 mtd->read = onenand_read;
4037 mtd->write = onenand_write;
cd5f6346
KP		 4038 mtd->read_oob = onenand_read_oob;
4039 mtd->write_oob = onenand_write_oob;
6c77fd64 4040 mtd->panic_write = onenand_panic_write;
493c6460
KP		 4041#ifdef CONFIG_MTD_ONENAND_OTP
4042 mtd->get_fact_prot_info = onenand_get_fact_prot_info;
4043 mtd->read_fact_prot_reg = onenand_read_fact_prot_reg;
4044 mtd->get_user_prot_info = onenand_get_user_prot_info;
4045 mtd->read_user_prot_reg = onenand_read_user_prot_reg;
4046 mtd->write_user_prot_reg = onenand_write_user_prot_reg;
4047 mtd->lock_user_prot_reg = onenand_lock_user_prot_reg;
4048#endif
cd5f6346 4049 mtd->sync = onenand_sync;
08f782b6 4050 mtd->lock = onenand_lock;
cd5f6346 4051 mtd->unlock = onenand_unlock;
a41371eb
KP		 4052 mtd->suspend = onenand_suspend;
4053 mtd->resume = onenand_resume;
cd5f6346
KP		 4054 mtd->block_isbad = onenand_block_isbad;
4055 mtd->block_markbad = onenand_block_markbad;
4056 mtd->owner = THIS_MODULE;
4057
4058 /* Unlock whole block */
31bb999e 4059 this->unlock_all(mtd);
cd5f6346 4060
5988af23
RH		 4061 ret = this->scan_bbt(mtd);
4062 if ((!FLEXONENAND(this)) || ret)
4063 return ret;
4064
4065 /* Change Flex-OneNAND boundaries if required */
4066 for (i = 0; i < MAX_DIES; i++)
4067 flexonenand_set_boundary(mtd, i, flex_bdry[2 * i],
4068 flex_bdry[(2 * i) + 1]);
4069
4070 return 0;
cd5f6346
KP		 4071}
4072
4073/**
4074 * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
4075 * @param mtd MTD device structure
4076 */
4077void onenand_release(struct mtd_info *mtd)
4078{
532a37cf
KP		 4079 struct onenand_chip *this = mtd->priv;
4080
cd5f6346
KP		 4081#ifdef CONFIG_MTD_PARTITIONS
4082 /* Deregister partitions */
4083 del_mtd_partitions (mtd);
4084#endif
4085 /* Deregister the device */
4086 del_mtd_device (mtd);
532a37cf
KP		 4087
4088 /* Free bad block table memory, if allocated */
f00b0046
AH		 4089 if (this->bbm) {
4090 struct bbm_info *bbm = this->bbm;
4091 kfree(bbm->bbt);
532a37cf 4092 kfree(this->bbm);
f00b0046 4093 }
470bc844 4094 /* Buffers allocated by onenand_scan */
4a8ce0b0 4095 if (this->options & ONENAND_PAGEBUF_ALLOC) {
532a37cf 4096 kfree(this->page_buf);
4a8ce0b0
KP		 4097#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
4098 kfree(this->verify_buf);
4099#endif
4100 }
470bc844
KP		 4101 if (this->options & ONENAND_OOBBUF_ALLOC)
4102 kfree(this->oob_buf);
5988af23 4103 kfree(mtd->eraseregions);
cd5f6346
KP		 4104}
4105
4106EXPORT_SYMBOL_GPL(onenand_scan);
4107EXPORT_SYMBOL_GPL(onenand_release);
4108
4109MODULE_LICENSE("GPL");
4110MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
4111MODULE_DESCRIPTION("Generic OneNAND flash driver code");
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