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mtd: onenand: add new callback for bufferram read
[net-next-2.6.git] / drivers / mtd / onenand / onenand_base.c
CommitLineData
cd5f6346
KP		 1/*
2 * linux/drivers/mtd/onenand/onenand_base.c
3 *
3cf60253
AKS		 4 * Copyright © 2005-2009 Samsung Electronics
5 * Copyright © 2007 Nokia Corporation
6 *
cd5f6346
KP		 7 * Kyungmin Park <kyungmin.park@samsung.com>
8 *
81280d58
AH		 9 * Credits:
10 * Adrian Hunter <ext-adrian.hunter@nokia.com>:
11 * auto-placement support, read-while load support, various fixes
81280d58 12 *
5988af23
RH		 13 * Vishak G <vishak.g at samsung.com>, Rohit Hagargundgi <h.rohit at samsung.com>
14 * Flex-OneNAND support
3cf60253
AKS		 15 * Amul Kumar Saha <amul.saha at samsung.com>
16 * OTP support
5988af23 17 *
cd5f6346
KP		 18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
c90173f0 25#include <linux/moduleparam.h>
5a0e3ad6 26#include <linux/slab.h>
cd5f6346 27#include <linux/init.h>
015953d7 28#include <linux/sched.h>
6c77fd64 29#include <linux/delay.h>
2c22120f 30#include <linux/interrupt.h>
015953d7 31#include <linux/jiffies.h>
cd5f6346
KP		 32#include <linux/mtd/mtd.h>
33#include <linux/mtd/onenand.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37
72073027
MK		 38/*
39 * Multiblock erase if number of blocks to erase is 2 or more.
40 * Maximum number of blocks for simultaneous erase is 64.
41 */
42#define MB_ERASE_MIN_BLK_COUNT 2
43#define MB_ERASE_MAX_BLK_COUNT 64
44
5988af23
RH		 45/* Default Flex-OneNAND boundary and lock respectively */
46static int flex_bdry[MAX_DIES * 2] = { -1, 0, -1, 0 };
47
c90173f0
AS		 48module_param_array(flex_bdry, int, NULL, 0400);
49MODULE_PARM_DESC(flex_bdry, "SLC Boundary information for Flex-OneNAND"
50 "Syntax:flex_bdry=DIE_BDRY,LOCK,..."
51 "DIE_BDRY: SLC boundary of the die"
52 "LOCK: Locking information for SLC boundary"
53 " : 0->Set boundary in unlocked status"
54 " : 1->Set boundary in locked status");
55
3cf60253
AKS		 56/* Default OneNAND/Flex-OneNAND OTP options*/
57static int otp;
58
59module_param(otp, int, 0400);
60MODULE_PARM_DESC(otp, "Corresponding behaviour of OneNAND in OTP"
61 "Syntax : otp=LOCK_TYPE"
62 "LOCK_TYPE : Keys issued, for specific OTP Lock type"
63 " : 0 -> Default (No Blocks Locked)"
64 " : 1 -> OTP Block lock"
65 " : 2 -> 1st Block lock"
66 " : 3 -> BOTH OTP Block and 1st Block lock");
67
5988af23
RH		 68/**
69 * onenand_oob_128 - oob info for Flex-Onenand with 4KB page
70 * For now, we expose only 64 out of 80 ecc bytes
71 */
72static struct nand_ecclayout onenand_oob_128 = {
73 .eccbytes = 64,
74 .eccpos = {
75 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
76 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
77 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
78 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
79 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
81 102, 103, 104, 105
82 },
83 .oobfree = {
84 {2, 4}, {18, 4}, {34, 4}, {50, 4},
85 {66, 4}, {82, 4}, {98, 4}, {114, 4}
86 }
87};
88
cd5f6346
KP		 89/**
90 * onenand_oob_64 - oob info for large (2KB) page
91 */
5bd34c09 92static struct nand_ecclayout onenand_oob_64 = {
cd5f6346
KP		 93 .eccbytes = 20,
94 .eccpos = {
95 8, 9, 10, 11, 12,
96 24, 25, 26, 27, 28,
97 40, 41, 42, 43, 44,
98 56, 57, 58, 59, 60,
99 },
100 .oobfree = {
101 {2, 3}, {14, 2}, {18, 3}, {30, 2},
d9777f1c
JL		 102 {34, 3}, {46, 2}, {50, 3}, {62, 2}
103 }
cd5f6346
KP		 104};
105
106/**
107 * onenand_oob_32 - oob info for middle (1KB) page
108 */
5bd34c09 109static struct nand_ecclayout onenand_oob_32 = {
cd5f6346
KP		 110 .eccbytes = 10,
111 .eccpos = {
112 8, 9, 10, 11, 12,
113 24, 25, 26, 27, 28,
114 },
115 .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
116};
117
118static const unsigned char ffchars[] = {
119 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
120 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */
121 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
122 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */
123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
124 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */
125 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
126 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */
5988af23
RH		 127 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
128 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */
129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */
131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */
133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */
cd5f6346
KP		 135};
136
137/**
138 * onenand_readw - [OneNAND Interface] Read OneNAND register
139 * @param addr address to read
140 *
141 * Read OneNAND register
142 */
143static unsigned short onenand_readw(void __iomem *addr)
144{
145 return readw(addr);
146}
147
148/**
149 * onenand_writew - [OneNAND Interface] Write OneNAND register with value
150 * @param value value to write
151 * @param addr address to write
152 *
153 * Write OneNAND register with value
154 */
155static void onenand_writew(unsigned short value, void __iomem *addr)
156{
157 writew(value, addr);
158}
159
160/**
161 * onenand_block_address - [DEFAULT] Get block address
83a36838 162 * @param this onenand chip data structure
cd5f6346
KP		 163 * @param block the block
164 * @return translated block address if DDP, otherwise same
165 *
166 * Setup Start Address 1 Register (F100h)
167 */
83a36838 168static int onenand_block_address(struct onenand_chip *this, int block)
cd5f6346 169{
738d61f5
KP		 170 /* Device Flash Core select, NAND Flash Block Address */
171 if (block & this->density_mask)
172 return ONENAND_DDP_CHIP1 | (block ^ this->density_mask);
cd5f6346
KP		 173
174 return block;
175}
176
177/**
178 * onenand_bufferram_address - [DEFAULT] Get bufferram address
83a36838 179 * @param this onenand chip data structure
cd5f6346
KP		 180 * @param block the block
181 * @return set DBS value if DDP, otherwise 0
182 *
183 * Setup Start Address 2 Register (F101h) for DDP
184 */
83a36838 185static int onenand_bufferram_address(struct onenand_chip *this, int block)
cd5f6346 186{
738d61f5
KP		 187 /* Device BufferRAM Select */
188 if (block & this->density_mask)
189 return ONENAND_DDP_CHIP1;
cd5f6346 190
738d61f5 191 return ONENAND_DDP_CHIP0;
cd5f6346
KP		 192}
193
194/**
195 * onenand_page_address - [DEFAULT] Get page address
196 * @param page the page address
197 * @param sector the sector address
198 * @return combined page and sector address
199 *
200 * Setup Start Address 8 Register (F107h)
201 */
202static int onenand_page_address(int page, int sector)
203{
204 /* Flash Page Address, Flash Sector Address */
205 int fpa, fsa;
206
207 fpa = page & ONENAND_FPA_MASK;
208 fsa = sector & ONENAND_FSA_MASK;
209
210 return ((fpa << ONENAND_FPA_SHIFT) | fsa);
211}
212
213/**
214 * onenand_buffer_address - [DEFAULT] Get buffer address
215 * @param dataram1 DataRAM index
216 * @param sectors the sector address
217 * @param count the number of sectors
218 * @return the start buffer value
219 *
220 * Setup Start Buffer Register (F200h)
221 */
222static int onenand_buffer_address(int dataram1, int sectors, int count)
223{
224 int bsa, bsc;
225
226 /* BufferRAM Sector Address */
227 bsa = sectors & ONENAND_BSA_MASK;
228
229 if (dataram1)
230 bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */
231 else
232 bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */
233
234 /* BufferRAM Sector Count */
235 bsc = count & ONENAND_BSC_MASK;
236
237 return ((bsa << ONENAND_BSA_SHIFT) | bsc);
238}
239
5988af23
RH		 240/**
241 * flexonenand_block- For given address return block number
242 * @param this - OneNAND device structure
243 * @param addr - Address for which block number is needed
244 */
245static unsigned flexonenand_block(struct onenand_chip *this, loff_t addr)
246{
247 unsigned boundary, blk, die = 0;
248
249 if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) {
250 die = 1;
251 addr -= this->diesize[0];
252 }
253
254 boundary = this->boundary[die];
255
256 blk = addr >> (this->erase_shift - 1);
257 if (blk > boundary)
258 blk = (blk + boundary + 1) >> 1;
259
260 blk += die ? this->density_mask : 0;
261 return blk;
262}
263
264inline unsigned onenand_block(struct onenand_chip *this, loff_t addr)
265{
266 if (!FLEXONENAND(this))
267 return addr >> this->erase_shift;
268 return flexonenand_block(this, addr);
269}
270
271/**
272 * flexonenand_addr - Return address of the block
273 * @this: OneNAND device structure
274 * @block: Block number on Flex-OneNAND
275 *
276 * Return address of the block
277 */
278static loff_t flexonenand_addr(struct onenand_chip *this, int block)
279{
280 loff_t ofs = 0;
281 int die = 0, boundary;
282
283 if (ONENAND_IS_DDP(this) && block >= this->density_mask) {
284 block -= this->density_mask;
285 die = 1;
286 ofs = this->diesize[0];
287 }
288
289 boundary = this->boundary[die];
290 ofs += (loff_t)block << (this->erase_shift - 1);
291 if (block > (boundary + 1))
292 ofs += (loff_t)(block - boundary - 1) << (this->erase_shift - 1);
293 return ofs;
294}
295
296loff_t onenand_addr(struct onenand_chip *this, int block)
297{
298 if (!FLEXONENAND(this))
299 return (loff_t)block << this->erase_shift;
300 return flexonenand_addr(this, block);
301}
302EXPORT_SYMBOL(onenand_addr);
303
e71f04fc
KP		 304/**
305 * onenand_get_density - [DEFAULT] Get OneNAND density
306 * @param dev_id OneNAND device ID
307 *
308 * Get OneNAND density from device ID
309 */
310static inline int onenand_get_density(int dev_id)
311{
312 int density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
313 return (density & ONENAND_DEVICE_DENSITY_MASK);
314}
315
5988af23
RH		 316/**
317 * flexonenand_region - [Flex-OneNAND] Return erase region of addr
318 * @param mtd MTD device structure
319 * @param addr address whose erase region needs to be identified
320 */
321int flexonenand_region(struct mtd_info *mtd, loff_t addr)
322{
323 int i;
324
325 for (i = 0; i < mtd->numeraseregions; i++)
326 if (addr < mtd->eraseregions[i].offset)
327 break;
328 return i - 1;
329}
330EXPORT_SYMBOL(flexonenand_region);
331
cd5f6346
KP		 332/**
333 * onenand_command - [DEFAULT] Send command to OneNAND device
334 * @param mtd MTD device structure
335 * @param cmd the command to be sent
336 * @param addr offset to read from or write to
337 * @param len number of bytes to read or write
338 *
339 * Send command to OneNAND device. This function is used for middle/large page
340 * devices (1KB/2KB Bytes per page)
341 */
342static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
343{
344 struct onenand_chip *this = mtd->priv;
b21b72cf 345 int value, block, page;
cd5f6346
KP		 346
347 /* Address translation */
348 switch (cmd) {
349 case ONENAND_CMD_UNLOCK:
350 case ONENAND_CMD_LOCK:
351 case ONENAND_CMD_LOCK_TIGHT:
28b79ff9 352 case ONENAND_CMD_UNLOCK_ALL:
cd5f6346
KP		 353 block = -1;
354 page = -1;
355 break;
356
5988af23
RH		 357 case FLEXONENAND_CMD_PI_ACCESS:
358 /* addr contains die index */
359 block = addr * this->density_mask;
360 page = -1;
361 break;
362
cd5f6346 363 case ONENAND_CMD_ERASE:
72073027
MK		 364 case ONENAND_CMD_MULTIBLOCK_ERASE:
365 case ONENAND_CMD_ERASE_VERIFY:
cd5f6346 366 case ONENAND_CMD_BUFFERRAM:
493c6460 367 case ONENAND_CMD_OTP_ACCESS:
5988af23 368 block = onenand_block(this, addr);
cd5f6346
KP		 369 page = -1;
370 break;
371
5988af23
RH		 372 case FLEXONENAND_CMD_READ_PI:
373 cmd = ONENAND_CMD_READ;
374 block = addr * this->density_mask;
375 page = 0;
376 break;
377
cd5f6346 378 default:
5988af23
RH		 379 block = onenand_block(this, addr);
380 page = (int) (addr - onenand_addr(this, block)) >> this->page_shift;
ee9745fc
KP		 381
382 if (ONENAND_IS_2PLANE(this)) {
383 /* Make the even block number */
384 block &= ~1;
385 /* Is it the odd plane? */
386 if (addr & this->writesize)
387 block++;
388 page >>= 1;
389 }
cd5f6346
KP		 390 page &= this->page_mask;
391 break;
392 }
393
394 /* NOTE: The setting order of the registers is very important! */
395 if (cmd == ONENAND_CMD_BUFFERRAM) {
396 /* Select DataRAM for DDP */
83a36838 397 value = onenand_bufferram_address(this, block);
cd5f6346
KP		 398 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
399
6a88c47b
KP		 400 if (ONENAND_IS_MLC(this) || ONENAND_IS_2PLANE(this) ||
401 ONENAND_IS_4KB_PAGE(this))
ee9745fc
KP		 402 /* It is always BufferRAM0 */
403 ONENAND_SET_BUFFERRAM0(this);
404 else
405 /* Switch to the next data buffer */
406 ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 407
408 return 0;
409 }
410
411 if (block != -1) {
412 /* Write 'DFS, FBA' of Flash */
83a36838 413 value = onenand_block_address(this, block);
cd5f6346 414 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
3cecf69e 415
b21b72cf
KP		 416 /* Select DataRAM for DDP */
417 value = onenand_bufferram_address(this, block);
418 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 419 }
420
421 if (page != -1) {
60d84f97 422 /* Now we use page size operation */
5988af23 423 int sectors = 0, count = 0;
cd5f6346
KP		 424 int dataram;
425
426 switch (cmd) {
5988af23 427 case FLEXONENAND_CMD_RECOVER_LSB:
cd5f6346
KP		 428 case ONENAND_CMD_READ:
429 case ONENAND_CMD_READOOB:
6a88c47b 430 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 431 /* It is always BufferRAM0 */
432 dataram = ONENAND_SET_BUFFERRAM0(this);
433 else
434 dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
cd5f6346
KP		 435 break;
436
437 default:
ee9745fc
KP		 438 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
439 cmd = ONENAND_CMD_2X_PROG;
cd5f6346
KP		 440 dataram = ONENAND_CURRENT_BUFFERRAM(this);
441 break;
442 }
443
444 /* Write 'FPA, FSA' of Flash */
445 value = onenand_page_address(page, sectors);
446 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
447
448 /* Write 'BSA, BSC' of DataRAM */
449 value = onenand_buffer_address(dataram, sectors, count);
450 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
cd5f6346
KP		 451 }
452
453 /* Interrupt clear */
454 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
455
456 /* Write command */
457 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
458
459 return 0;
460}
461
5988af23
RH		 462/**
463 * onenand_read_ecc - return ecc status
464 * @param this onenand chip structure
465 */
466static inline int onenand_read_ecc(struct onenand_chip *this)
467{
468 int ecc, i, result = 0;
469
6a88c47b 470 if (!FLEXONENAND(this) && !ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 471 return this->read_word(this->base + ONENAND_REG_ECC_STATUS);
472
473 for (i = 0; i < 4; i++) {
6a88c47b 474 ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS + i*2);
5988af23
RH		 475 if (likely(!ecc))
476 continue;
477 if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR)
478 return ONENAND_ECC_2BIT_ALL;
479 else
480 result = ONENAND_ECC_1BIT_ALL;
481 }
482
483 return result;
484}
485
cd5f6346
KP		 486/**
487 * onenand_wait - [DEFAULT] wait until the command is done
488 * @param mtd MTD device structure
489 * @param state state to select the max. timeout value
490 *
491 * Wait for command done. This applies to all OneNAND command
492 * Read can take up to 30us, erase up to 2ms and program up to 350us
493 * according to general OneNAND specs
494 */
495static int onenand_wait(struct mtd_info *mtd, int state)
496{
497 struct onenand_chip * this = mtd->priv;
498 unsigned long timeout;
499 unsigned int flags = ONENAND_INT_MASTER;
500 unsigned int interrupt = 0;
2fd32d4a 501 unsigned int ctrl;
cd5f6346
KP		 502
503 /* The 20 msec is enough */
504 timeout = jiffies + msecs_to_jiffies(20);
505 while (time_before(jiffies, timeout)) {
506 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
507
508 if (interrupt & flags)
509 break;
510
72073027 511 if (state != FL_READING && state != FL_PREPARING_ERASE)
cd5f6346
KP		 512 cond_resched();
513 }
514 /* To get correct interrupt status in timeout case */
515 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
516
517 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
518
83973b87
KP		 519 /*
520 * In the Spec. it checks the controller status first
521 * However if you get the correct information in case of
522 * power off recovery (POR) test, it should read ECC status first
523 */
cd5f6346 524 if (interrupt & ONENAND_INT_READ) {
5988af23 525 int ecc = onenand_read_ecc(this);
f4f91ac3 526 if (ecc) {
b3c9f8bf 527 if (ecc & ONENAND_ECC_2BIT_ALL) {
297758f8
AKS		 528 printk(KERN_ERR "%s: ECC error = 0x%04x\n",
529 __func__, ecc);
f4f91ac3 530 mtd->ecc_stats.failed++;
30a7eb29 531 return -EBADMSG;
49dc08ee 532 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
297758f8
AKS		 533 printk(KERN_DEBUG "%s: correctable ECC error = 0x%04x\n",
534 __func__, ecc);
f4f91ac3 535 mtd->ecc_stats.corrected++;
49dc08ee 536 }
cd5f6346 537 }
9d032801 538 } else if (state == FL_READING) {
297758f8
AKS		 539 printk(KERN_ERR "%s: read timeout! ctrl=0x%04x intr=0x%04x\n",
540 __func__, ctrl, interrupt);
9d032801 541 return -EIO;
cd5f6346
KP		 542 }
543
72073027
MK		 544 if (state == FL_PREPARING_ERASE && !(interrupt & ONENAND_INT_ERASE)) {
545 printk(KERN_ERR "%s: mb erase timeout! ctrl=0x%04x intr=0x%04x\n",
546 __func__, ctrl, interrupt);
547 return -EIO;
548 }
549
550 if (!(interrupt & ONENAND_INT_MASTER)) {
551 printk(KERN_ERR "%s: timeout! ctrl=0x%04x intr=0x%04x\n",
552 __func__, ctrl, interrupt);
553 return -EIO;
554 }
555
83973b87
KP		 556 /* If there's controller error, it's a real error */
557 if (ctrl & ONENAND_CTRL_ERROR) {
297758f8
AKS		 558 printk(KERN_ERR "%s: controller error = 0x%04x\n",
559 __func__, ctrl);
83973b87 560 if (ctrl & ONENAND_CTRL_LOCK)
297758f8 561 printk(KERN_ERR "%s: it's locked error.\n", __func__);
83973b87
KP		 562 return -EIO;
563 }
564
cd5f6346
KP		 565 return 0;
566}
567
2c22120f
KP		 568/*
569 * onenand_interrupt - [DEFAULT] onenand interrupt handler
570 * @param irq onenand interrupt number
571 * @param dev_id interrupt data
572 *
573 * complete the work
574 */
575static irqreturn_t onenand_interrupt(int irq, void *data)
576{
06efcad0 577 struct onenand_chip *this = data;
2c22120f
KP		 578
579 /* To handle shared interrupt */
580 if (!this->complete.done)
581 complete(&this->complete);
582
583 return IRQ_HANDLED;
584}
585
586/*
587 * onenand_interrupt_wait - [DEFAULT] wait until the command is done
588 * @param mtd MTD device structure
589 * @param state state to select the max. timeout value
590 *
591 * Wait for command done.
592 */
593static int onenand_interrupt_wait(struct mtd_info *mtd, int state)
594{
595 struct onenand_chip *this = mtd->priv;
596
2c22120f
KP		 597 wait_for_completion(&this->complete);
598
599 return onenand_wait(mtd, state);
600}
601
602/*
603 * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait
604 * @param mtd MTD device structure
605 * @param state state to select the max. timeout value
606 *
607 * Try interrupt based wait (It is used one-time)
608 */
609static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state)
610{
611 struct onenand_chip *this = mtd->priv;
612 unsigned long remain, timeout;
613
614 /* We use interrupt wait first */
615 this->wait = onenand_interrupt_wait;
616
2c22120f
KP		 617 timeout = msecs_to_jiffies(100);
618 remain = wait_for_completion_timeout(&this->complete, timeout);
619 if (!remain) {
620 printk(KERN_INFO "OneNAND: There's no interrupt. "
621 "We use the normal wait\n");
622
623 /* Release the irq */
624 free_irq(this->irq, this);
c9ac5977 625
2c22120f
KP		 626 this->wait = onenand_wait;
627 }
628
629 return onenand_wait(mtd, state);
630}
631
632/*
633 * onenand_setup_wait - [OneNAND Interface] setup onenand wait method
634 * @param mtd MTD device structure
635 *
636 * There's two method to wait onenand work
637 * 1. polling - read interrupt status register
638 * 2. interrupt - use the kernel interrupt method
639 */
640static void onenand_setup_wait(struct mtd_info *mtd)
641{
642 struct onenand_chip *this = mtd->priv;
643 int syscfg;
644
645 init_completion(&this->complete);
646
647 if (this->irq <= 0) {
648 this->wait = onenand_wait;
649 return;
650 }
651
652 if (request_irq(this->irq, &onenand_interrupt,
653 IRQF_SHARED, "onenand", this)) {
654 /* If we can't get irq, use the normal wait */
655 this->wait = onenand_wait;
656 return;
657 }
658
659 /* Enable interrupt */
660 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
661 syscfg |= ONENAND_SYS_CFG1_IOBE;
662 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
663
664 this->wait = onenand_try_interrupt_wait;
665}
666
cd5f6346
KP		 667/**
668 * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
669 * @param mtd MTD data structure
670 * @param area BufferRAM area
671 * @return offset given area
672 *
673 * Return BufferRAM offset given area
674 */
675static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
676{
677 struct onenand_chip *this = mtd->priv;
678
679 if (ONENAND_CURRENT_BUFFERRAM(this)) {
ee9745fc 680 /* Note: the 'this->writesize' is a real page size */
cd5f6346 681 if (area == ONENAND_DATARAM)
ee9745fc 682 return this->writesize;
cd5f6346
KP		 683 if (area == ONENAND_SPARERAM)
684 return mtd->oobsize;
685 }
686
687 return 0;
688}
689
690/**
691 * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
692 * @param mtd MTD data structure
693 * @param area BufferRAM area
694 * @param buffer the databuffer to put/get data
695 * @param offset offset to read from or write to
696 * @param count number of bytes to read/write
697 *
698 * Read the BufferRAM area
699 */
700static int onenand_read_bufferram(struct mtd_info *mtd, int area,
701 unsigned char *buffer, int offset, size_t count)
702{
703 struct onenand_chip *this = mtd->priv;
704 void __iomem *bufferram;
705
706 bufferram = this->base + area;
707
708 bufferram += onenand_bufferram_offset(mtd, area);
709
9c01f87d
KP		 710 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
711 unsigned short word;
712
713 /* Align with word(16-bit) size */
714 count--;
715
716 /* Read word and save byte */
717 word = this->read_word(bufferram + offset + count);
718 buffer[count] = (word & 0xff);
719 }
720
cd5f6346
KP		 721 memcpy(buffer, bufferram + offset, count);
722
723 return 0;
724}
725
52b0eea7
KP		 726/**
727 * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
728 * @param mtd MTD data structure
729 * @param area BufferRAM area
730 * @param buffer the databuffer to put/get data
731 * @param offset offset to read from or write to
732 * @param count number of bytes to read/write
733 *
734 * Read the BufferRAM area with Sync. Burst Mode
735 */
736static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
737 unsigned char *buffer, int offset, size_t count)
738{
739 struct onenand_chip *this = mtd->priv;
740 void __iomem *bufferram;
741
742 bufferram = this->base + area;
743
744 bufferram += onenand_bufferram_offset(mtd, area);
745
746 this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
747
9c01f87d
KP		 748 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
749 unsigned short word;
750
751 /* Align with word(16-bit) size */
752 count--;
753
754 /* Read word and save byte */
755 word = this->read_word(bufferram + offset + count);
756 buffer[count] = (word & 0xff);
757 }
758
52b0eea7
KP		 759 memcpy(buffer, bufferram + offset, count);
760
761 this->mmcontrol(mtd, 0);
762
763 return 0;
764}
765
cd5f6346
KP		 766/**
767 * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
768 * @param mtd MTD data structure
769 * @param area BufferRAM area
770 * @param buffer the databuffer to put/get data
771 * @param offset offset to read from or write to
772 * @param count number of bytes to read/write
773 *
774 * Write the BufferRAM area
775 */
776static int onenand_write_bufferram(struct mtd_info *mtd, int area,
777 const unsigned char *buffer, int offset, size_t count)
778{
779 struct onenand_chip *this = mtd->priv;
780 void __iomem *bufferram;
781
782 bufferram = this->base + area;
783
784 bufferram += onenand_bufferram_offset(mtd, area);
785
9c01f87d
KP		 786 if (ONENAND_CHECK_BYTE_ACCESS(count)) {
787 unsigned short word;
788 int byte_offset;
789
790 /* Align with word(16-bit) size */
791 count--;
792
793 /* Calculate byte access offset */
794 byte_offset = offset + count;
795
796 /* Read word and save byte */
797 word = this->read_word(bufferram + byte_offset);
798 word = (word & ~0xff) | buffer[count];
799 this->write_word(word, bufferram + byte_offset);
800 }
801
cd5f6346
KP		 802 memcpy(bufferram + offset, buffer, count);
803
804 return 0;
805}
806
ee9745fc
KP		 807/**
808 * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
809 * @param mtd MTD data structure
810 * @param addr address to check
811 * @return blockpage address
812 *
813 * Get blockpage address at 2x program mode
814 */
815static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
816{
817 struct onenand_chip *this = mtd->priv;
818 int blockpage, block, page;
819
820 /* Calculate the even block number */
821 block = (int) (addr >> this->erase_shift) & ~1;
822 /* Is it the odd plane? */
823 if (addr & this->writesize)
824 block++;
825 page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
826 blockpage = (block << 7) | page;
827
828 return blockpage;
829}
830
cd5f6346
KP		 831/**
832 * onenand_check_bufferram - [GENERIC] Check BufferRAM information
833 * @param mtd MTD data structure
834 * @param addr address to check
d5c5e78a 835 * @return 1 if there are valid data, otherwise 0
cd5f6346
KP		 836 *
837 * Check bufferram if there is data we required
838 */
839static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
840{
841 struct onenand_chip *this = mtd->priv;
cde36b37 842 int blockpage, found = 0;
abf3c0f2 843 unsigned int i;
d5c5e78a 844
ee9745fc
KP		 845 if (ONENAND_IS_2PLANE(this))
846 blockpage = onenand_get_2x_blockpage(mtd, addr);
847 else
848 blockpage = (int) (addr >> this->page_shift);
cd5f6346 849
abf3c0f2 850 /* Is there valid data? */
cd5f6346 851 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2 852 if (this->bufferram[i].blockpage == blockpage)
cde36b37
AH		 853 found = 1;
854 else {
855 /* Check another BufferRAM */
856 i = ONENAND_NEXT_BUFFERRAM(this);
857 if (this->bufferram[i].blockpage == blockpage) {
858 ONENAND_SET_NEXT_BUFFERRAM(this);
859 found = 1;
860 }
861 }
cd5f6346 862
cde36b37
AH		 863 if (found && ONENAND_IS_DDP(this)) {
864 /* Select DataRAM for DDP */
5988af23 865 int block = onenand_block(this, addr);
cde36b37
AH		 866 int value = onenand_bufferram_address(this, block);
867 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
abf3c0f2 868 }
cd5f6346 869
cde36b37 870 return found;
cd5f6346
KP		 871}
872
873/**
874 * onenand_update_bufferram - [GENERIC] Update BufferRAM information
875 * @param mtd MTD data structure
876 * @param addr address to update
877 * @param valid valid flag
878 *
879 * Update BufferRAM information
880 */
abf3c0f2 881static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
cd5f6346
KP		 882 int valid)
883{
884 struct onenand_chip *this = mtd->priv;
abf3c0f2
KP		 885 int blockpage;
886 unsigned int i;
d5c5e78a 887
ee9745fc
KP		 888 if (ONENAND_IS_2PLANE(this))
889 blockpage = onenand_get_2x_blockpage(mtd, addr);
890 else
891 blockpage = (int) (addr >> this->page_shift);
cd5f6346 892
abf3c0f2
KP		 893 /* Invalidate another BufferRAM */
894 i = ONENAND_NEXT_BUFFERRAM(this);
5b4246f1 895 if (this->bufferram[i].blockpage == blockpage)
abf3c0f2 896 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 897
898 /* Update BufferRAM */
899 i = ONENAND_CURRENT_BUFFERRAM(this);
abf3c0f2
KP		 900 if (valid)
901 this->bufferram[i].blockpage = blockpage;
902 else
903 this->bufferram[i].blockpage = -1;
cd5f6346
KP		 904}
905
480b9dfb
AH		 906/**
907 * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information
908 * @param mtd MTD data structure
909 * @param addr start address to invalidate
910 * @param len length to invalidate
911 *
912 * Invalidate BufferRAM information
913 */
914static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr,
915 unsigned int len)
916{
917 struct onenand_chip *this = mtd->priv;
918 int i;
919 loff_t end_addr = addr + len;
920
921 /* Invalidate BufferRAM */
922 for (i = 0; i < MAX_BUFFERRAM; i++) {
923 loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift;
924 if (buf_addr >= addr && buf_addr < end_addr)
925 this->bufferram[i].blockpage = -1;
926 }
927}
928
cd5f6346
KP		 929/**
930 * onenand_get_device - [GENERIC] Get chip for selected access
931 * @param mtd MTD device structure
932 * @param new_state the state which is requested
933 *
934 * Get the device and lock it for exclusive access
935 */
a41371eb 936static int onenand_get_device(struct mtd_info *mtd, int new_state)
cd5f6346
KP		 937{
938 struct onenand_chip *this = mtd->priv;
939 DECLARE_WAITQUEUE(wait, current);
940
941 /*
942 * Grab the lock and see if the device is available
943 */
944 while (1) {
945 spin_lock(&this->chip_lock);
946 if (this->state == FL_READY) {
947 this->state = new_state;
948 spin_unlock(&this->chip_lock);
949 break;
950 }
a41371eb
KP		 951 if (new_state == FL_PM_SUSPENDED) {
952 spin_unlock(&this->chip_lock);
953 return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
954 }
cd5f6346
KP		 955 set_current_state(TASK_UNINTERRUPTIBLE);
956 add_wait_queue(&this->wq, &wait);
957 spin_unlock(&this->chip_lock);
958 schedule();
959 remove_wait_queue(&this->wq, &wait);
960 }
a41371eb
KP		 961
962 return 0;
cd5f6346
KP		 963}
964
965/**
966 * onenand_release_device - [GENERIC] release chip
967 * @param mtd MTD device structure
968 *
969 * Deselect, release chip lock and wake up anyone waiting on the device
970 */
971static void onenand_release_device(struct mtd_info *mtd)
972{
973 struct onenand_chip *this = mtd->priv;
974
975 /* Release the chip */
976 spin_lock(&this->chip_lock);
977 this->state = FL_READY;
978 wake_up(&this->wq);
979 spin_unlock(&this->chip_lock);
980}
981
982/**
d15057b7
KP		 983 * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer
984 * @param mtd MTD device structure
985 * @param buf destination address
986 * @param column oob offset to read from
987 * @param thislen oob length to read
988 */
989static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column,
990 int thislen)
991{
992 struct onenand_chip *this = mtd->priv;
993 struct nand_oobfree *free;
994 int readcol = column;
995 int readend = column + thislen;
996 int lastgap = 0;
997 unsigned int i;
998 uint8_t *oob_buf = this->oob_buf;
999
1000 free = this->ecclayout->oobfree;
1001 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1002 if (readcol >= lastgap)
1003 readcol += free->offset - lastgap;
1004 if (readend >= lastgap)
1005 readend += free->offset - lastgap;
1006 lastgap = free->offset + free->length;
1007 }
1008 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
1009 free = this->ecclayout->oobfree;
1010 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1011 int free_end = free->offset + free->length;
1012 if (free->offset < readend && free_end > readcol) {
1013 int st = max_t(int,free->offset,readcol);
1014 int ed = min_t(int,free_end,readend);
1015 int n = ed - st;
1016 memcpy(buf, oob_buf + st, n);
1017 buf += n;
1018 } else if (column == 0)
1019 break;
1020 }
1021 return 0;
1022}
1023
5988af23
RH		 1024/**
1025 * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data
1026 * @param mtd MTD device structure
1027 * @param addr address to recover
1028 * @param status return value from onenand_wait / onenand_bbt_wait
1029 *
1030 * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has
1031 * lower page address and MSB page has higher page address in paired pages.
1032 * If power off occurs during MSB page program, the paired LSB page data can
1033 * become corrupt. LSB page recovery read is a way to read LSB page though page
1034 * data are corrupted. When uncorrectable error occurs as a result of LSB page
1035 * read after power up, issue LSB page recovery read.
1036 */
1037static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status)
1038{
1039 struct onenand_chip *this = mtd->priv;
1040 int i;
1041
1042 /* Recovery is only for Flex-OneNAND */
1043 if (!FLEXONENAND(this))
1044 return status;
1045
1046 /* check if we failed due to uncorrectable error */
1047 if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR)
1048 return status;
1049
1050 /* check if address lies in MLC region */
1051 i = flexonenand_region(mtd, addr);
1052 if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift))
1053 return status;
1054
1055 /* We are attempting to reread, so decrement stats.failed
1056 * which was incremented by onenand_wait due to read failure
1057 */
297758f8
AKS		 1058 printk(KERN_INFO "%s: Attempting to recover from uncorrectable read\n",
1059 __func__);
5988af23
RH		 1060 mtd->ecc_stats.failed--;
1061
1062 /* Issue the LSB page recovery command */
1063 this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize);
1064 return this->wait(mtd, FL_READING);
1065}
1066
1067/**
1068 * onenand_mlc_read_ops_nolock - MLC OneNAND read main and/or out-of-band
1069 * @param mtd MTD device structure
1070 * @param from offset to read from
1071 * @param ops: oob operation description structure
1072 *
1073 * MLC OneNAND / Flex-OneNAND has 4KB page size and 4KB dataram.
1074 * So, read-while-load is not present.
1075 */
1076static int onenand_mlc_read_ops_nolock(struct mtd_info *mtd, loff_t from,
1077 struct mtd_oob_ops *ops)
1078{
1079 struct onenand_chip *this = mtd->priv;
1080 struct mtd_ecc_stats stats;
1081 size_t len = ops->len;
1082 size_t ooblen = ops->ooblen;
1083 u_char *buf = ops->datbuf;
1084 u_char *oobbuf = ops->oobbuf;
1085 int read = 0, column, thislen;
1086 int oobread = 0, oobcolumn, thisooblen, oobsize;
1087 int ret = 0;
1088 int writesize = this->writesize;
1089
297758f8 1090 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
8032747e 1091 __func__, (unsigned int) from, (int) len);
5988af23
RH		 1092
1093 if (ops->mode == MTD_OOB_AUTO)
1094 oobsize = this->ecclayout->oobavail;
1095 else
1096 oobsize = mtd->oobsize;
1097
1098 oobcolumn = from & (mtd->oobsize - 1);
1099
1100 /* Do not allow reads past end of device */
1101 if (from + len > mtd->size) {
297758f8
AKS		 1102 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1103 __func__);
5988af23
RH		 1104 ops->retlen = 0;
1105 ops->oobretlen = 0;
1106 return -EINVAL;
1107 }
1108
1109 stats = mtd->ecc_stats;
1110
1111 while (read < len) {
1112 cond_resched();
1113
1114 thislen = min_t(int, writesize, len - read);
1115
1116 column = from & (writesize - 1);
1117 if (column + thislen > writesize)
1118 thislen = writesize - column;
1119
1120 if (!onenand_check_bufferram(mtd, from)) {
1121 this->command(mtd, ONENAND_CMD_READ, from, writesize);
1122
1123 ret = this->wait(mtd, FL_READING);
1124 if (unlikely(ret))
1125 ret = onenand_recover_lsb(mtd, from, ret);
1126 onenand_update_bufferram(mtd, from, !ret);
1127 if (ret == -EBADMSG)
1128 ret = 0;
1129 }
1130
1131 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
1132 if (oobbuf) {
1133 thisooblen = oobsize - oobcolumn;
1134 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1135
1136 if (ops->mode == MTD_OOB_AUTO)
1137 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1138 else
1139 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1140 oobread += thisooblen;
1141 oobbuf += thisooblen;
1142 oobcolumn = 0;
1143 }
1144
1145 read += thislen;
1146 if (read == len)
1147 break;
1148
1149 from += thislen;
1150 buf += thislen;
1151 }
1152
1153 /*
1154 * Return success, if no ECC failures, else -EBADMSG
1155 * fs driver will take care of that, because
1156 * retlen == desired len and result == -EBADMSG
1157 */
1158 ops->retlen = read;
1159 ops->oobretlen = oobread;
1160
1161 if (ret)
1162 return ret;
1163
1164 if (mtd->ecc_stats.failed - stats.failed)
1165 return -EBADMSG;
1166
1167 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1168}
1169
d15057b7 1170/**
49dc08ee 1171 * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band
cd5f6346
KP		 1172 * @param mtd MTD device structure
1173 * @param from offset to read from
d15057b7 1174 * @param ops: oob operation description structure
cd5f6346 1175 *
d15057b7
KP		 1176 * OneNAND read main and/or out-of-band data
1177 */
49dc08ee 1178static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from,
d15057b7 1179 struct mtd_oob_ops *ops)
cd5f6346
KP		 1180{
1181 struct onenand_chip *this = mtd->priv;
f4f91ac3 1182 struct mtd_ecc_stats stats;
d15057b7
KP		 1183 size_t len = ops->len;
1184 size_t ooblen = ops->ooblen;
1185 u_char *buf = ops->datbuf;
1186 u_char *oobbuf = ops->oobbuf;
1187 int read = 0, column, thislen;
1188 int oobread = 0, oobcolumn, thisooblen, oobsize;
0fc2ccea 1189 int ret = 0, boundary = 0;
ee9745fc 1190 int writesize = this->writesize;
cd5f6346 1191
297758f8
AKS		 1192 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1193 __func__, (unsigned int) from, (int) len);
d15057b7
KP		 1194
1195 if (ops->mode == MTD_OOB_AUTO)
1196 oobsize = this->ecclayout->oobavail;
1197 else
1198 oobsize = mtd->oobsize;
1199
1200 oobcolumn = from & (mtd->oobsize - 1);
cd5f6346
KP		 1201
1202 /* Do not allow reads past end of device */
1203 if ((from + len) > mtd->size) {
297758f8
AKS		 1204 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1205 __func__);
d15057b7
KP		 1206 ops->retlen = 0;
1207 ops->oobretlen = 0;
cd5f6346
KP		 1208 return -EINVAL;
1209 }
1210
f4f91ac3 1211 stats = mtd->ecc_stats;
61a7e198 1212
a8de85d5
AH		 1213 /* Read-while-load method */
1214
1215 /* Do first load to bufferRAM */
1216 if (read < len) {
1217 if (!onenand_check_bufferram(mtd, from)) {
ee9745fc 1218 this->command(mtd, ONENAND_CMD_READ, from, writesize);
a8de85d5
AH		 1219 ret = this->wait(mtd, FL_READING);
1220 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1221 if (ret == -EBADMSG)
1222 ret = 0;
a8de85d5
AH		 1223 }
1224 }
1225
ee9745fc
KP		 1226 thislen = min_t(int, writesize, len - read);
1227 column = from & (writesize - 1);
1228 if (column + thislen > writesize)
1229 thislen = writesize - column;
a8de85d5
AH		 1230
1231 while (!ret) {
1232 /* If there is more to load then start next load */
1233 from += thislen;
1234 if (read + thislen < len) {
ee9745fc 1235 this->command(mtd, ONENAND_CMD_READ, from, writesize);
0fc2ccea
AH		 1236 /*
1237 * Chip boundary handling in DDP
1238 * Now we issued chip 1 read and pointed chip 1
492e1501 1239 * bufferram so we have to point chip 0 bufferram.
0fc2ccea 1240 */
738d61f5
KP		 1241 if (ONENAND_IS_DDP(this) &&
1242 unlikely(from == (this->chipsize >> 1))) {
1243 this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2);
0fc2ccea
AH		 1244 boundary = 1;
1245 } else
1246 boundary = 0;
a8de85d5
AH		 1247 ONENAND_SET_PREV_BUFFERRAM(this);
1248 }
1249 /* While load is going, read from last bufferRAM */
1250 this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
d15057b7
KP		 1251
1252 /* Read oob area if needed */
1253 if (oobbuf) {
1254 thisooblen = oobsize - oobcolumn;
1255 thisooblen = min_t(int, thisooblen, ooblen - oobread);
1256
1257 if (ops->mode == MTD_OOB_AUTO)
1258 onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen);
1259 else
1260 this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen);
1261 oobread += thisooblen;
1262 oobbuf += thisooblen;
1263 oobcolumn = 0;
1264 }
1265
a8de85d5
AH		 1266 /* See if we are done */
1267 read += thislen;
1268 if (read == len)
1269 break;
1270 /* Set up for next read from bufferRAM */
0fc2ccea 1271 if (unlikely(boundary))
738d61f5 1272 this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
a8de85d5
AH		 1273 ONENAND_SET_NEXT_BUFFERRAM(this);
1274 buf += thislen;
ee9745fc 1275 thislen = min_t(int, writesize, len - read);
a8de85d5
AH		 1276 column = 0;
1277 cond_resched();
1278 /* Now wait for load */
1279 ret = this->wait(mtd, FL_READING);
1280 onenand_update_bufferram(mtd, from, !ret);
5f4d47d5
AH		 1281 if (ret == -EBADMSG)
1282 ret = 0;
a8de85d5 1283 }
cd5f6346 1284
cd5f6346
KP		 1285 /*
1286 * Return success, if no ECC failures, else -EBADMSG
1287 * fs driver will take care of that, because
1288 * retlen == desired len and result == -EBADMSG
1289 */
d15057b7
KP		 1290 ops->retlen = read;
1291 ops->oobretlen = oobread;
f4f91ac3 1292
a8de85d5
AH		 1293 if (ret)
1294 return ret;
1295
5f4d47d5
AH		 1296 if (mtd->ecc_stats.failed - stats.failed)
1297 return -EBADMSG;
1298
f4f91ac3 1299 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
cd5f6346
KP		 1300}
1301
cd5f6346 1302/**
49dc08ee 1303 * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band
cd5f6346
KP		 1304 * @param mtd MTD device structure
1305 * @param from offset to read from
d15057b7 1306 * @param ops: oob operation description structure
cd5f6346
KP		 1307 *
1308 * OneNAND read out-of-band data from the spare area
1309 */
49dc08ee 1310static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from,
12f77c9e 1311 struct mtd_oob_ops *ops)
cd5f6346
KP		 1312{
1313 struct onenand_chip *this = mtd->priv;
5f4d47d5 1314 struct mtd_ecc_stats stats;
a5e7c7b4 1315 int read = 0, thislen, column, oobsize;
12f77c9e
KP		 1316 size_t len = ops->ooblen;
1317 mtd_oob_mode_t mode = ops->mode;
1318 u_char *buf = ops->oobbuf;
5988af23 1319 int ret = 0, readcmd;
cd5f6346 1320
12f77c9e
KP		 1321 from += ops->ooboffs;
1322
297758f8
AKS		 1323 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %i\n",
1324 __func__, (unsigned int) from, (int) len);
cd5f6346
KP		 1325
1326 /* Initialize return length value */
12f77c9e 1327 ops->oobretlen = 0;
cd5f6346 1328
a5e7c7b4
AH		 1329 if (mode == MTD_OOB_AUTO)
1330 oobsize = this->ecclayout->oobavail;
1331 else
1332 oobsize = mtd->oobsize;
1333
1334 column = from & (mtd->oobsize - 1);
1335
1336 if (unlikely(column >= oobsize)) {
297758f8
AKS		 1337 printk(KERN_ERR "%s: Attempted to start read outside oob\n",
1338 __func__);
a5e7c7b4
AH		 1339 return -EINVAL;
1340 }
1341
cd5f6346 1342 /* Do not allow reads past end of device */
a5e7c7b4
AH		 1343 if (unlikely(from >= mtd->size ||
1344 column + len > ((mtd->size >> this->page_shift) -
1345 (from >> this->page_shift)) * oobsize)) {
297758f8
AKS		 1346 printk(KERN_ERR "%s: Attempted to read beyond end of device\n",
1347 __func__);
cd5f6346
KP		 1348 return -EINVAL;
1349 }
1350
5f4d47d5
AH		 1351 stats = mtd->ecc_stats;
1352
5988af23
RH		 1353 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1354
cd5f6346 1355 while (read < len) {
61a7e198
AB		 1356 cond_resched();
1357
a5e7c7b4 1358 thislen = oobsize - column;
cd5f6346
KP		 1359 thislen = min_t(int, thislen, len);
1360
5988af23 1361 this->command(mtd, readcmd, from, mtd->oobsize);
cd5f6346
KP		 1362
1363 onenand_update_bufferram(mtd, from, 0);
1364
1365 ret = this->wait(mtd, FL_READING);
5988af23
RH		 1366 if (unlikely(ret))
1367 ret = onenand_recover_lsb(mtd, from, ret);
1368
5f4d47d5 1369 if (ret && ret != -EBADMSG) {
297758f8
AKS		 1370 printk(KERN_ERR "%s: read failed = 0x%x\n",
1371 __func__, ret);
5f4d47d5
AH		 1372 break;
1373 }
cd5f6346 1374
a5e7c7b4
AH		 1375 if (mode == MTD_OOB_AUTO)
1376 onenand_transfer_auto_oob(mtd, buf, column, thislen);
1377 else
1378 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
cd5f6346
KP		 1379
1380 read += thislen;
1381
1382 if (read == len)
1383 break;
1384
cd5f6346
KP		 1385 buf += thislen;
1386
1387 /* Read more? */
1388 if (read < len) {
1389 /* Page size */
28318776 1390 from += mtd->writesize;
cd5f6346
KP		 1391 column = 0;
1392 }
1393 }
1394
12f77c9e 1395 ops->oobretlen = read;
5f4d47d5
AH		 1396
1397 if (ret)
1398 return ret;
1399
1400 if (mtd->ecc_stats.failed - stats.failed)
1401 return -EBADMSG;
1402
1403 return 0;
cd5f6346
KP		 1404}
1405
8593fbc6 1406/**
d15057b7
KP		 1407 * onenand_read - [MTD Interface] Read data from flash
1408 * @param mtd MTD device structure
1409 * @param from offset to read from
1410 * @param len number of bytes to read
1411 * @param retlen pointer to variable to store the number of read bytes
1412 * @param buf the databuffer to put data
1413 *
1414 * Read with ecc
1415*/
1416static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
1417 size_t *retlen, u_char *buf)
1418{
5988af23 1419 struct onenand_chip *this = mtd->priv;
d15057b7
KP		 1420 struct mtd_oob_ops ops = {
1421 .len = len,
1422 .ooblen = 0,
1423 .datbuf = buf,
1424 .oobbuf = NULL,
1425 };
1426 int ret;
1427
49dc08ee 1428 onenand_get_device(mtd, FL_READING);
6a88c47b 1429 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1430 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
1431 onenand_read_ops_nolock(mtd, from, &ops);
49dc08ee 1432 onenand_release_device(mtd);
d15057b7 1433
49dc08ee 1434 *retlen = ops.retlen;
d15057b7
KP		 1435 return ret;
1436}
1437
1438/**
1439 * onenand_read_oob - [MTD Interface] Read main and/or out-of-band
e3da8067
KP		 1440 * @param mtd: MTD device structure
1441 * @param from: offset to read from
1442 * @param ops: oob operation description structure
d15057b7
KP		 1443
1444 * Read main and/or out-of-band
8593fbc6
TG		 1445 */
1446static int onenand_read_oob(struct mtd_info *mtd, loff_t from,
1447 struct mtd_oob_ops *ops)
1448{
5988af23 1449 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 1450 int ret;
1451
4f4fad27 1452 switch (ops->mode) {
a5e7c7b4
AH		 1453 case MTD_OOB_PLACE:
1454 case MTD_OOB_AUTO:
1455 break;
1456 case MTD_OOB_RAW:
4f4fad27 1457 /* Not implemented yet */
a5e7c7b4
AH		 1458 default:
1459 return -EINVAL;
1460 }
d15057b7 1461
49dc08ee 1462 onenand_get_device(mtd, FL_READING);
d15057b7 1463 if (ops->datbuf)
6a88c47b 1464 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 1465 onenand_mlc_read_ops_nolock(mtd, from, ops) :
1466 onenand_read_ops_nolock(mtd, from, ops);
49dc08ee
AB		 1467 else
1468 ret = onenand_read_oob_nolock(mtd, from, ops);
1469 onenand_release_device(mtd);
d15057b7 1470
49dc08ee 1471 return ret;
8593fbc6
TG		 1472}
1473
211ac75f
KP		 1474/**
1475 * onenand_bbt_wait - [DEFAULT] wait until the command is done
1476 * @param mtd MTD device structure
1477 * @param state state to select the max. timeout value
1478 *
1479 * Wait for command done.
1480 */
1481static int onenand_bbt_wait(struct mtd_info *mtd, int state)
1482{
1483 struct onenand_chip *this = mtd->priv;
1484 unsigned long timeout;
1485 unsigned int interrupt;
1486 unsigned int ctrl;
1487
1488 /* The 20 msec is enough */
1489 timeout = jiffies + msecs_to_jiffies(20);
1490 while (time_before(jiffies, timeout)) {
1491 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1492 if (interrupt & ONENAND_INT_MASTER)
1493 break;
1494 }
1495 /* To get correct interrupt status in timeout case */
1496 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1497 ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
1498
211ac75f 1499 if (interrupt & ONENAND_INT_READ) {
5988af23 1500 int ecc = onenand_read_ecc(this);
83973b87 1501 if (ecc & ONENAND_ECC_2BIT_ALL) {
297758f8
AKS		 1502 printk(KERN_WARNING "%s: ecc error = 0x%04x, "
1503 "controller error 0x%04x\n",
1504 __func__, ecc, ctrl);
5988af23 1505 return ONENAND_BBT_READ_ECC_ERROR;
83973b87 1506 }
211ac75f 1507 } else {
297758f8
AKS		 1508 printk(KERN_ERR "%s: read timeout! ctrl=0x%04x intr=0x%04x\n",
1509 __func__, ctrl, interrupt);
211ac75f
KP		 1510 return ONENAND_BBT_READ_FATAL_ERROR;
1511 }
1512
83973b87
KP		 1513 /* Initial bad block case: 0x2400 or 0x0400 */
1514 if (ctrl & ONENAND_CTRL_ERROR) {
297758f8
AKS		 1515 printk(KERN_DEBUG "%s: controller error = 0x%04x\n",
1516 __func__, ctrl);
83973b87
KP		 1517 return ONENAND_BBT_READ_ERROR;
1518 }
1519
211ac75f
KP		 1520 return 0;
1521}
1522
1523/**
1524 * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan
1525 * @param mtd MTD device structure
1526 * @param from offset to read from
e3da8067 1527 * @param ops oob operation description structure
211ac75f
KP		 1528 *
1529 * OneNAND read out-of-band data from the spare area for bbt scan
1530 */
1531int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
1532 struct mtd_oob_ops *ops)
1533{
1534 struct onenand_chip *this = mtd->priv;
1535 int read = 0, thislen, column;
5988af23 1536 int ret = 0, readcmd;
211ac75f
KP		 1537 size_t len = ops->ooblen;
1538 u_char *buf = ops->oobbuf;
1539
297758f8
AKS		 1540 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08x, len = %zi\n",
1541 __func__, (unsigned int) from, len);
211ac75f
KP		 1542
1543 /* Initialize return value */
1544 ops->oobretlen = 0;
1545
1546 /* Do not allow reads past end of device */
1547 if (unlikely((from + len) > mtd->size)) {
297758f8
AKS		 1548 printk(KERN_ERR "%s: Attempt read beyond end of device\n",
1549 __func__);
211ac75f
KP		 1550 return ONENAND_BBT_READ_FATAL_ERROR;
1551 }
1552
1553 /* Grab the lock and see if the device is available */
1554 onenand_get_device(mtd, FL_READING);
1555
1556 column = from & (mtd->oobsize - 1);
1557
5988af23
RH		 1558 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
1559
211ac75f
KP		 1560 while (read < len) {
1561 cond_resched();
1562
1563 thislen = mtd->oobsize - column;
1564 thislen = min_t(int, thislen, len);
1565
5988af23 1566 this->command(mtd, readcmd, from, mtd->oobsize);
211ac75f
KP		 1567
1568 onenand_update_bufferram(mtd, from, 0);
1569
31bb999e 1570 ret = this->bbt_wait(mtd, FL_READING);
5988af23
RH		 1571 if (unlikely(ret))
1572 ret = onenand_recover_lsb(mtd, from, ret);
1573
211ac75f
KP		 1574 if (ret)
1575 break;
1576
1577 this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
1578 read += thislen;
1579 if (read == len)
1580 break;
1581
1582 buf += thislen;
1583
1584 /* Read more? */
1585 if (read < len) {
1586 /* Update Page size */
ee9745fc 1587 from += this->writesize;
211ac75f
KP		 1588 column = 0;
1589 }
1590 }
1591
1592 /* Deselect and wake up anyone waiting on the device */
1593 onenand_release_device(mtd);
1594
1595 ops->oobretlen = read;
1596 return ret;
1597}
1598
cd5f6346 1599#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
8e6ec690
KP		 1600/**
1601 * onenand_verify_oob - [GENERIC] verify the oob contents after a write
1602 * @param mtd MTD device structure
1603 * @param buf the databuffer to verify
1604 * @param to offset to read from
8e6ec690 1605 */
a5e7c7b4 1606static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to)
8e6ec690
KP		 1607{
1608 struct onenand_chip *this = mtd->priv;
69d79186 1609 u_char *oob_buf = this->oob_buf;
5988af23
RH		 1610 int status, i, readcmd;
1611
1612 readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB;
8e6ec690 1613
5988af23 1614 this->command(mtd, readcmd, to, mtd->oobsize);
8e6ec690
KP		 1615 onenand_update_bufferram(mtd, to, 0);
1616 status = this->wait(mtd, FL_READING);
1617 if (status)
1618 return status;
1619
69d79186 1620 this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize);
91014e9b 1621 for (i = 0; i < mtd->oobsize; i++)
69d79186 1622 if (buf[i] != 0xFF && buf[i] != oob_buf[i])
8e6ec690
KP		 1623 return -EBADMSG;
1624
1625 return 0;
1626}
1627
cd5f6346 1628/**
8b29c0b6
AH		 1629 * onenand_verify - [GENERIC] verify the chip contents after a write
1630 * @param mtd MTD device structure
1631 * @param buf the databuffer to verify
1632 * @param addr offset to read from
1633 * @param len number of bytes to read and compare
cd5f6346 1634 */
8b29c0b6 1635static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len)
cd5f6346
KP		 1636{
1637 struct onenand_chip *this = mtd->priv;
cd5f6346 1638 int ret = 0;
8b29c0b6 1639 int thislen, column;
cd5f6346 1640
8b29c0b6 1641 while (len != 0) {
ee9745fc
KP		 1642 thislen = min_t(int, this->writesize, len);
1643 column = addr & (this->writesize - 1);
1644 if (column + thislen > this->writesize)
1645 thislen = this->writesize - column;
60d84f97 1646
ee9745fc 1647 this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
cd5f6346 1648
8b29c0b6
AH		 1649 onenand_update_bufferram(mtd, addr, 0);
1650
1651 ret = this->wait(mtd, FL_READING);
1652 if (ret)
1653 return ret;
cd5f6346 1654
8b29c0b6 1655 onenand_update_bufferram(mtd, addr, 1);
cd5f6346 1656
3328dc31 1657 this->read_bufferram(mtd, ONENAND_DATARAM, this->verify_buf, 0, mtd->writesize);
cd5f6346 1658
3328dc31 1659 if (memcmp(buf, this->verify_buf, thislen))
8b29c0b6
AH		 1660 return -EBADMSG;
1661
1662 len -= thislen;
1663 buf += thislen;
1664 addr += thislen;
1665 }
d5c5e78a 1666
cd5f6346
KP		 1667 return 0;
1668}
1669#else
8b29c0b6 1670#define onenand_verify(...) (0)
8e6ec690 1671#define onenand_verify_oob(...) (0)
cd5f6346
KP		 1672#endif
1673
60d84f97 1674#define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0)
cd5f6346 1675
6c77fd64
RP		 1676static void onenand_panic_wait(struct mtd_info *mtd)
1677{
1678 struct onenand_chip *this = mtd->priv;
1679 unsigned int interrupt;
1680 int i;
1681
1682 for (i = 0; i < 2000; i++) {
1683 interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
1684 if (interrupt & ONENAND_INT_MASTER)
1685 break;
1686 udelay(10);
1687 }
1688}
1689
1690/**
1691 * onenand_panic_write - [MTD Interface] write buffer to FLASH in a panic context
1692 * @param mtd MTD device structure
1693 * @param to offset to write to
1694 * @param len number of bytes to write
1695 * @param retlen pointer to variable to store the number of written bytes
1696 * @param buf the data to write
1697 *
1698 * Write with ECC
1699 */
1700static int onenand_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
1701 size_t *retlen, const u_char *buf)
1702{
1703 struct onenand_chip *this = mtd->priv;
1704 int column, subpage;
1705 int written = 0;
1706 int ret = 0;
1707
1708 if (this->state == FL_PM_SUSPENDED)
1709 return -EBUSY;
1710
1711 /* Wait for any existing operation to clear */
1712 onenand_panic_wait(mtd);
1713
297758f8
AKS		 1714 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1715 __func__, (unsigned int) to, (int) len);
6c77fd64
RP		 1716
1717 /* Initialize retlen, in case of early exit */
1718 *retlen = 0;
1719
1720 /* Do not allow writes past end of device */
1721 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1722 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1723 __func__);
6c77fd64
RP		 1724 return -EINVAL;
1725 }
1726
1727 /* Reject writes, which are not page aligned */
b73d7e43 1728 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1729 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1730 __func__);
6c77fd64
RP		 1731 return -EINVAL;
1732 }
1733
1734 column = to & (mtd->writesize - 1);
1735
1736 /* Loop until all data write */
1737 while (written < len) {
1738 int thislen = min_t(int, mtd->writesize - column, len - written);
1739 u_char *wbuf = (u_char *) buf;
1740
1741 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
1742
1743 /* Partial page write */
1744 subpage = thislen < mtd->writesize;
1745 if (subpage) {
1746 memset(this->page_buf, 0xff, mtd->writesize);
1747 memcpy(this->page_buf + column, buf, thislen);
1748 wbuf = this->page_buf;
1749 }
1750
1751 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
1752 this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
1753
1754 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1755
1756 onenand_panic_wait(mtd);
1757
1758 /* In partial page write we don't update bufferram */
1759 onenand_update_bufferram(mtd, to, !ret && !subpage);
1760 if (ONENAND_IS_2PLANE(this)) {
1761 ONENAND_SET_BUFFERRAM1(this);
1762 onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
1763 }
1764
1765 if (ret) {
297758f8 1766 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
6c77fd64
RP		 1767 break;
1768 }
1769
1770 written += thislen;
1771
1772 if (written == len)
1773 break;
1774
1775 column = 0;
1776 to += thislen;
1777 buf += thislen;
1778 }
1779
1780 *retlen = written;
1781 return ret;
1782}
1783
cd5f6346 1784/**
d15057b7
KP		 1785 * onenand_fill_auto_oob - [Internal] oob auto-placement transfer
1786 * @param mtd MTD device structure
1787 * @param oob_buf oob buffer
1788 * @param buf source address
1789 * @param column oob offset to write to
1790 * @param thislen oob length to write
1791 */
1792static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf,
1793 const u_char *buf, int column, int thislen)
1794{
1795 struct onenand_chip *this = mtd->priv;
1796 struct nand_oobfree *free;
1797 int writecol = column;
1798 int writeend = column + thislen;
1799 int lastgap = 0;
1800 unsigned int i;
1801
1802 free = this->ecclayout->oobfree;
1803 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1804 if (writecol >= lastgap)
1805 writecol += free->offset - lastgap;
1806 if (writeend >= lastgap)
1807 writeend += free->offset - lastgap;
1808 lastgap = free->offset + free->length;
1809 }
1810 free = this->ecclayout->oobfree;
1811 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) {
1812 int free_end = free->offset + free->length;
1813 if (free->offset < writeend && free_end > writecol) {
1814 int st = max_t(int,free->offset,writecol);
1815 int ed = min_t(int,free_end,writeend);
1816 int n = ed - st;
1817 memcpy(oob_buf + st, buf, n);
1818 buf += n;
1819 } else if (column == 0)
1820 break;
1821 }
1822 return 0;
1823}
1824
1825/**
49dc08ee 1826 * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band
cd5f6346
KP		 1827 * @param mtd MTD device structure
1828 * @param to offset to write to
d15057b7 1829 * @param ops oob operation description structure
cd5f6346 1830 *
d15057b7 1831 * Write main and/or oob with ECC
cd5f6346 1832 */
49dc08ee 1833static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to,
d15057b7 1834 struct mtd_oob_ops *ops)
cd5f6346
KP		 1835{
1836 struct onenand_chip *this = mtd->priv;
9ce96908
KP		 1837 int written = 0, column, thislen = 0, subpage = 0;
1838 int prev = 0, prevlen = 0, prev_subpage = 0, first = 1;
d15057b7
KP		 1839 int oobwritten = 0, oobcolumn, thisooblen, oobsize;
1840 size_t len = ops->len;
1841 size_t ooblen = ops->ooblen;
1842 const u_char *buf = ops->datbuf;
1843 const u_char *oob = ops->oobbuf;
1844 u_char *oobbuf;
cd5f6346
KP		 1845 int ret = 0;
1846
297758f8
AKS		 1847 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1848 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 1849
1850 /* Initialize retlen, in case of early exit */
d15057b7
KP		 1851 ops->retlen = 0;
1852 ops->oobretlen = 0;
cd5f6346
KP		 1853
1854 /* Do not allow writes past end of device */
1855 if (unlikely((to + len) > mtd->size)) {
297758f8
AKS		 1856 printk(KERN_ERR "%s: Attempt write to past end of device\n",
1857 __func__);
cd5f6346
KP		 1858 return -EINVAL;
1859 }
1860
1861 /* Reject writes, which are not page aligned */
b73d7e43 1862 if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) {
297758f8
AKS		 1863 printk(KERN_ERR "%s: Attempt to write not page aligned data\n",
1864 __func__);
cd5f6346
KP		 1865 return -EINVAL;
1866 }
1867
9ce96908
KP		 1868 /* Check zero length */
1869 if (!len)
1870 return 0;
1871
d15057b7
KP		 1872 if (ops->mode == MTD_OOB_AUTO)
1873 oobsize = this->ecclayout->oobavail;
1874 else
1875 oobsize = mtd->oobsize;
1876
1877 oobcolumn = to & (mtd->oobsize - 1);
1878
60d84f97 1879 column = to & (mtd->writesize - 1);
60d84f97 1880
cd5f6346 1881 /* Loop until all data write */
9ce96908
KP		 1882 while (1) {
1883 if (written < len) {
1884 u_char *wbuf = (u_char *) buf;
60d84f97 1885
9ce96908
KP		 1886 thislen = min_t(int, mtd->writesize - column, len - written);
1887 thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten);
d15057b7 1888
9ce96908 1889 cond_resched();
61a7e198 1890
9ce96908 1891 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen);
60d84f97 1892
9ce96908
KP		 1893 /* Partial page write */
1894 subpage = thislen < mtd->writesize;
1895 if (subpage) {
1896 memset(this->page_buf, 0xff, mtd->writesize);
1897 memcpy(this->page_buf + column, buf, thislen);
1898 wbuf = this->page_buf;
1899 }
cd5f6346 1900
9ce96908 1901 this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize);
d15057b7 1902
9ce96908
KP		 1903 if (oob) {
1904 oobbuf = this->oob_buf;
d15057b7 1905
9ce96908
KP		 1906 /* We send data to spare ram with oobsize
1907 * to prevent byte access */
1908 memset(oobbuf, 0xff, mtd->oobsize);
1909 if (ops->mode == MTD_OOB_AUTO)
1910 onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen);
1911 else
1912 memcpy(oobbuf + oobcolumn, oob, thisooblen);
d15057b7 1913
9ce96908
KP		 1914 oobwritten += thisooblen;
1915 oob += thisooblen;
1916 oobcolumn = 0;
1917 } else
1918 oobbuf = (u_char *) ffchars;
1919
1920 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
d15057b7 1921 } else
9ce96908 1922 ONENAND_SET_NEXT_BUFFERRAM(this);
d15057b7 1923
9ce96908 1924 /*
492e1501
MK		 1925 * 2 PLANE, MLC, and Flex-OneNAND do not support
1926 * write-while-program feature.
9ce96908 1927 */
6a88c47b 1928 if (!ONENAND_IS_2PLANE(this) && !ONENAND_IS_4KB_PAGE(this) && !first) {
9ce96908
KP		 1929 ONENAND_SET_PREV_BUFFERRAM(this);
1930
1931 ret = this->wait(mtd, FL_WRITING);
1932
1933 /* In partial page write we don't update bufferram */
1934 onenand_update_bufferram(mtd, prev, !ret && !prev_subpage);
1935 if (ret) {
1936 written -= prevlen;
297758f8
AKS		 1937 printk(KERN_ERR "%s: write failed %d\n",
1938 __func__, ret);
9ce96908
KP		 1939 break;
1940 }
cd5f6346 1941
9ce96908
KP		 1942 if (written == len) {
1943 /* Only check verify write turn on */
1944 ret = onenand_verify(mtd, buf - len, to - len, len);
1945 if (ret)
297758f8
AKS		 1946 printk(KERN_ERR "%s: verify failed %d\n",
1947 __func__, ret);
9ce96908
KP		 1948 break;
1949 }
cd5f6346 1950
9ce96908
KP		 1951 ONENAND_SET_NEXT_BUFFERRAM(this);
1952 }
81f38e11 1953
9ce96908
KP		 1954 this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize);
1955
1956 /*
1957 * 2 PLANE, MLC, and Flex-OneNAND wait here
1958 */
6a88c47b 1959 if (ONENAND_IS_2PLANE(this) || ONENAND_IS_4KB_PAGE(this)) {
9ce96908 1960 ret = this->wait(mtd, FL_WRITING);
cd5f6346 1961
9ce96908
KP		 1962 /* In partial page write we don't update bufferram */
1963 onenand_update_bufferram(mtd, to, !ret && !subpage);
1964 if (ret) {
297758f8
AKS		 1965 printk(KERN_ERR "%s: write failed %d\n",
1966 __func__, ret);
9ce96908
KP		 1967 break;
1968 }
cd5f6346 1969
9ce96908
KP		 1970 /* Only check verify write turn on */
1971 ret = onenand_verify(mtd, buf, to, thislen);
1972 if (ret) {
297758f8
AKS		 1973 printk(KERN_ERR "%s: verify failed %d\n",
1974 __func__, ret);
9ce96908
KP		 1975 break;
1976 }
cd5f6346 1977
9ce96908 1978 written += thislen;
81f38e11 1979
9ce96908
KP		 1980 if (written == len)
1981 break;
1982
1983 } else
1984 written += thislen;
cd5f6346 1985
60d84f97 1986 column = 0;
9ce96908
KP		 1987 prev_subpage = subpage;
1988 prev = to;
1989 prevlen = thislen;
cd5f6346
KP		 1990 to += thislen;
1991 buf += thislen;
9ce96908 1992 first = 0;
cd5f6346
KP		 1993 }
1994
9ce96908
KP		 1995 /* In error case, clear all bufferrams */
1996 if (written != len)
1997 onenand_invalidate_bufferram(mtd, 0, -1);
1998
d15057b7 1999 ops->retlen = written;
9ce96908 2000 ops->oobretlen = oobwritten;
d5c5e78a 2001
cd5f6346
KP		 2002 return ret;
2003}
2004
a5e7c7b4 2005
cd5f6346 2006/**
49dc08ee 2007 * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band
cd5f6346
KP		 2008 * @param mtd MTD device structure
2009 * @param to offset to write to
2010 * @param len number of bytes to write
2011 * @param retlen pointer to variable to store the number of written bytes
2012 * @param buf the data to write
a5e7c7b4 2013 * @param mode operation mode
cd5f6346
KP		 2014 *
2015 * OneNAND write out-of-band
2016 */
49dc08ee
AB		 2017static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2018 struct mtd_oob_ops *ops)
cd5f6346
KP		 2019{
2020 struct onenand_chip *this = mtd->priv;
a5e7c7b4 2021 int column, ret = 0, oobsize;
5988af23 2022 int written = 0, oobcmd;
91014e9b 2023 u_char *oobbuf;
12f77c9e
KP		 2024 size_t len = ops->ooblen;
2025 const u_char *buf = ops->oobbuf;
2026 mtd_oob_mode_t mode = ops->mode;
2027
2028 to += ops->ooboffs;
cd5f6346 2029
297758f8
AKS		 2030 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2031 __func__, (unsigned int) to, (int) len);
cd5f6346
KP		 2032
2033 /* Initialize retlen, in case of early exit */
12f77c9e 2034 ops->oobretlen = 0;
cd5f6346 2035
a5e7c7b4
AH		 2036 if (mode == MTD_OOB_AUTO)
2037 oobsize = this->ecclayout->oobavail;
2038 else
2039 oobsize = mtd->oobsize;
2040
2041 column = to & (mtd->oobsize - 1);
2042
2043 if (unlikely(column >= oobsize)) {
297758f8
AKS		 2044 printk(KERN_ERR "%s: Attempted to start write outside oob\n",
2045 __func__);
a5e7c7b4
AH		 2046 return -EINVAL;
2047 }
2048
52e4200a 2049 /* For compatibility with NAND: Do not allow write past end of page */
91014e9b 2050 if (unlikely(column + len > oobsize)) {
297758f8
AKS		 2051 printk(KERN_ERR "%s: Attempt to write past end of page\n",
2052 __func__);
52e4200a
AH		 2053 return -EINVAL;
2054 }
2055
a5e7c7b4
AH		 2056 /* Do not allow reads past end of device */
2057 if (unlikely(to >= mtd->size ||
2058 column + len > ((mtd->size >> this->page_shift) -
2059 (to >> this->page_shift)) * oobsize)) {
8032747e
DW		 2060 printk(KERN_ERR "%s: Attempted to write past end of device\n",
2061 __func__);
cd5f6346
KP		 2062 return -EINVAL;
2063 }
2064
470bc844 2065 oobbuf = this->oob_buf;
91014e9b 2066
5988af23
RH		 2067 oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB;
2068
cd5f6346
KP		 2069 /* Loop until all data write */
2070 while (written < len) {
a5e7c7b4 2071 int thislen = min_t(int, oobsize, len - written);
cd5f6346 2072
61a7e198
AB		 2073 cond_resched();
2074
cd5f6346
KP		 2075 this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
2076
34c10609
KP		 2077 /* We send data to spare ram with oobsize
2078 * to prevent byte access */
91014e9b 2079 memset(oobbuf, 0xff, mtd->oobsize);
a5e7c7b4 2080 if (mode == MTD_OOB_AUTO)
91014e9b 2081 onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen);
a5e7c7b4 2082 else
91014e9b
KP		 2083 memcpy(oobbuf + column, buf, thislen);
2084 this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize);
cd5f6346 2085
6a88c47b 2086 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this)) {
5988af23
RH		 2087 /* Set main area of DataRAM to 0xff*/
2088 memset(this->page_buf, 0xff, mtd->writesize);
2089 this->write_bufferram(mtd, ONENAND_DATARAM,
2090 this->page_buf, 0, mtd->writesize);
2091 }
2092
2093 this->command(mtd, oobcmd, to, mtd->oobsize);
cd5f6346
KP		 2094
2095 onenand_update_bufferram(mtd, to, 0);
ee9745fc
KP		 2096 if (ONENAND_IS_2PLANE(this)) {
2097 ONENAND_SET_BUFFERRAM1(this);
2098 onenand_update_bufferram(mtd, to + this->writesize, 0);
2099 }
cd5f6346 2100
8e6ec690
KP		 2101 ret = this->wait(mtd, FL_WRITING);
2102 if (ret) {
297758f8 2103 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
5b4246f1 2104 break;
8e6ec690
KP		 2105 }
2106
91014e9b 2107 ret = onenand_verify_oob(mtd, oobbuf, to);
8e6ec690 2108 if (ret) {
297758f8
AKS		 2109 printk(KERN_ERR "%s: verify failed %d\n",
2110 __func__, ret);
5b4246f1 2111 break;
8e6ec690 2112 }
cd5f6346
KP		 2113
2114 written += thislen;
cd5f6346
KP		 2115 if (written == len)
2116 break;
2117
a5e7c7b4 2118 to += mtd->writesize;
cd5f6346 2119 buf += thislen;
a5e7c7b4 2120 column = 0;
cd5f6346
KP		 2121 }
2122
12f77c9e 2123 ops->oobretlen = written;
d5c5e78a 2124
8e6ec690 2125 return ret;
cd5f6346
KP		 2126}
2127
d15057b7
KP		 2128/**
2129 * onenand_write - [MTD Interface] write buffer to FLASH
2130 * @param mtd MTD device structure
2131 * @param to offset to write to
2132 * @param len number of bytes to write
2133 * @param retlen pointer to variable to store the number of written bytes
2134 * @param buf the data to write
2135 *
2136 * Write with ECC
2137 */
2138static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
2139 size_t *retlen, const u_char *buf)
2140{
2141 struct mtd_oob_ops ops = {
2142 .len = len,
2143 .ooblen = 0,
2144 .datbuf = (u_char *) buf,
2145 .oobbuf = NULL,
2146 };
2147 int ret;
2148
49dc08ee
AB		 2149 onenand_get_device(mtd, FL_WRITING);
2150 ret = onenand_write_ops_nolock(mtd, to, &ops);
2151 onenand_release_device(mtd);
d15057b7 2152
49dc08ee 2153 *retlen = ops.retlen;
d15057b7
KP		 2154 return ret;
2155}
2156
8593fbc6
TG		 2157/**
2158 * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band
e3da8067
KP		 2159 * @param mtd: MTD device structure
2160 * @param to: offset to write
2161 * @param ops: oob operation description structure
8593fbc6
TG		 2162 */
2163static int onenand_write_oob(struct mtd_info *mtd, loff_t to,
2164 struct mtd_oob_ops *ops)
2165{
49dc08ee
AB		 2166 int ret;
2167
4f4fad27 2168 switch (ops->mode) {
a5e7c7b4
AH		 2169 case MTD_OOB_PLACE:
2170 case MTD_OOB_AUTO:
2171 break;
2172 case MTD_OOB_RAW:
4f4fad27 2173 /* Not implemented yet */
a5e7c7b4
AH		 2174 default:
2175 return -EINVAL;
2176 }
d15057b7 2177
49dc08ee 2178 onenand_get_device(mtd, FL_WRITING);
d15057b7 2179 if (ops->datbuf)
49dc08ee
AB		 2180 ret = onenand_write_ops_nolock(mtd, to, ops);
2181 else
2182 ret = onenand_write_oob_nolock(mtd, to, ops);
2183 onenand_release_device(mtd);
d15057b7 2184
49dc08ee 2185 return ret;
8593fbc6
TG		 2186}
2187
cdc00130 2188/**
49dc08ee 2189 * onenand_block_isbad_nolock - [GENERIC] Check if a block is marked bad
cdc00130
KP		 2190 * @param mtd MTD device structure
2191 * @param ofs offset from device start
cdc00130
KP		 2192 * @param allowbbt 1, if its allowed to access the bbt area
2193 *
2194 * Check, if the block is bad. Either by reading the bad block table or
2195 * calling of the scan function.
2196 */
49dc08ee 2197static int onenand_block_isbad_nolock(struct mtd_info *mtd, loff_t ofs, int allowbbt)
cdc00130
KP		 2198{
2199 struct onenand_chip *this = mtd->priv;
2200 struct bbm_info *bbm = this->bbm;
2201
2202 /* Return info from the table */
2203 return bbm->isbad_bbt(mtd, ofs, allowbbt);
2204}
2205
72073027
MK		 2206
2207static int onenand_multiblock_erase_verify(struct mtd_info *mtd,
2208 struct erase_info *instr)
2209{
2210 struct onenand_chip *this = mtd->priv;
2211 loff_t addr = instr->addr;
2212 int len = instr->len;
2213 unsigned int block_size = (1 << this->erase_shift);
2214 int ret = 0;
2215
2216 while (len) {
2217 this->command(mtd, ONENAND_CMD_ERASE_VERIFY, addr, block_size);
2218 ret = this->wait(mtd, FL_VERIFYING_ERASE);
2219 if (ret) {
2220 printk(KERN_ERR "%s: Failed verify, block %d\n",
2221 __func__, onenand_block(this, addr));
2222 instr->state = MTD_ERASE_FAILED;
2223 instr->fail_addr = addr;
2224 return -1;
2225 }
2226 len -= block_size;
2227 addr += block_size;
2228 }
2229 return 0;
2230}
2231
2232/**
2233 * onenand_multiblock_erase - [Internal] erase block(s) using multiblock erase
2234 * @param mtd MTD device structure
2235 * @param instr erase instruction
2236 * @param region erase region
2237 *
2238 * Erase one or more blocks up to 64 block at a time
2239 */
2240static int onenand_multiblock_erase(struct mtd_info *mtd,
2241 struct erase_info *instr,
2242 unsigned int block_size)
2243{
2244 struct onenand_chip *this = mtd->priv;
2245 loff_t addr = instr->addr;
2246 int len = instr->len;
2247 int eb_count = 0;
2248 int ret = 0;
2249 int bdry_block = 0;
2250
2251 instr->state = MTD_ERASING;
2252
2253 if (ONENAND_IS_DDP(this)) {
2254 loff_t bdry_addr = this->chipsize >> 1;
2255 if (addr < bdry_addr && (addr + len) > bdry_addr)
2256 bdry_block = bdry_addr >> this->erase_shift;
2257 }
2258
2259 /* Pre-check bbs */
2260 while (len) {
2261 /* Check if we have a bad block, we do not erase bad blocks */
2262 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
2263 printk(KERN_WARNING "%s: attempt to erase a bad block "
2264 "at addr 0x%012llx\n",
2265 __func__, (unsigned long long) addr);
2266 instr->state = MTD_ERASE_FAILED;
2267 return -EIO;
2268 }
2269 len -= block_size;
2270 addr += block_size;
2271 }
2272
2273 len = instr->len;
2274 addr = instr->addr;
2275
2276 /* loop over 64 eb batches */
2277 while (len) {
2278 struct erase_info verify_instr = *instr;
2279 int max_eb_count = MB_ERASE_MAX_BLK_COUNT;
2280
2281 verify_instr.addr = addr;
2282 verify_instr.len = 0;
2283
2284 /* do not cross chip boundary */
2285 if (bdry_block) {
2286 int this_block = (addr >> this->erase_shift);
2287
2288 if (this_block < bdry_block) {
2289 max_eb_count = min(max_eb_count,
2290 (bdry_block - this_block));
2291 }
2292 }
2293
2294 eb_count = 0;
2295
2296 while (len > block_size && eb_count < (max_eb_count - 1)) {
2297 this->command(mtd, ONENAND_CMD_MULTIBLOCK_ERASE,
2298 addr, block_size);
2299 onenand_invalidate_bufferram(mtd, addr, block_size);
2300
2301 ret = this->wait(mtd, FL_PREPARING_ERASE);
2302 if (ret) {
2303 printk(KERN_ERR "%s: Failed multiblock erase, "
2304 "block %d\n", __func__,
2305 onenand_block(this, addr));
2306 instr->state = MTD_ERASE_FAILED;
2307 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2308 return -EIO;
2309 }
2310
2311 len -= block_size;
2312 addr += block_size;
2313 eb_count++;
2314 }
2315
2316 /* last block of 64-eb series */
2317 cond_resched();
2318 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2319 onenand_invalidate_bufferram(mtd, addr, block_size);
2320
2321 ret = this->wait(mtd, FL_ERASING);
2322 /* Check if it is write protected */
2323 if (ret) {
2324 printk(KERN_ERR "%s: Failed erase, block %d\n",
2325 __func__, onenand_block(this, addr));
2326 instr->state = MTD_ERASE_FAILED;
2327 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2328 return -EIO;
2329 }
2330
2331 len -= block_size;
2332 addr += block_size;
2333 eb_count++;
2334
2335 /* verify */
2336 verify_instr.len = eb_count * block_size;
2337 if (onenand_multiblock_erase_verify(mtd, &verify_instr)) {
2338 instr->state = verify_instr.state;
2339 instr->fail_addr = verify_instr.fail_addr;
2340 return -EIO;
2341 }
2342
2343 }
2344 return 0;
2345}
2346
2347
cd5f6346 2348/**
73885aea 2349 * onenand_block_by_block_erase - [Internal] erase block(s) using regular erase
cd5f6346
KP		 2350 * @param mtd MTD device structure
2351 * @param instr erase instruction
73885aea
MK		 2352 * @param region erase region
2353 * @param block_size erase block size
cd5f6346 2354 *
73885aea 2355 * Erase one or more blocks one block at a time
cd5f6346 2356 */
73885aea
MK		 2357static int onenand_block_by_block_erase(struct mtd_info *mtd,
2358 struct erase_info *instr,
2359 struct mtd_erase_region_info *region,
2360 unsigned int block_size)
cd5f6346
KP		 2361{
2362 struct onenand_chip *this = mtd->priv;
5988af23 2363 loff_t addr = instr->addr;
73885aea 2364 int len = instr->len;
5988af23 2365 loff_t region_end = 0;
73885aea 2366 int ret = 0;
cd5f6346 2367
73885aea
MK		 2368 if (region) {
2369 /* region is set for Flex-OneNAND */
5988af23 2370 region_end = region->offset + region->erasesize * region->numblocks;
cd5f6346
KP		 2371 }
2372
cd5f6346
KP		 2373 instr->state = MTD_ERASING;
2374
73885aea 2375 /* Loop through the blocks */
cd5f6346 2376 while (len) {
61a7e198 2377 cond_resched();
cd5f6346 2378
cdc00130 2379 /* Check if we have a bad block, we do not erase bad blocks */
49dc08ee 2380 if (onenand_block_isbad_nolock(mtd, addr, 0)) {
297758f8
AKS		 2381 printk(KERN_WARNING "%s: attempt to erase a bad block "
2382 "at addr 0x%012llx\n",
2383 __func__, (unsigned long long) addr);
cdc00130 2384 instr->state = MTD_ERASE_FAILED;
73885aea 2385 return -EIO;
cdc00130 2386 }
cd5f6346
KP		 2387
2388 this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
2389
480b9dfb
AH		 2390 onenand_invalidate_bufferram(mtd, addr, block_size);
2391
cd5f6346
KP		 2392 ret = this->wait(mtd, FL_ERASING);
2393 /* Check, if it is write protected */
2394 if (ret) {
297758f8
AKS		 2395 printk(KERN_ERR "%s: Failed erase, block %d\n",
2396 __func__, onenand_block(this, addr));
cd5f6346
KP		 2397 instr->state = MTD_ERASE_FAILED;
2398 instr->fail_addr = addr;
73885aea 2399 return -EIO;
cd5f6346
KP		 2400 }
2401
2402 len -= block_size;
2403 addr += block_size;
5988af23
RH		 2404
2405 if (addr == region_end) {
2406 if (!len)
2407 break;
2408 region++;
2409
2410 block_size = region->erasesize;
2411 region_end = region->offset + region->erasesize * region->numblocks;
2412
2413 if (len & (block_size - 1)) {
2414 /* FIXME: This should be handled at MTD partitioning level. */
297758f8
AKS		 2415 printk(KERN_ERR "%s: Unaligned address\n",
2416 __func__);
73885aea 2417 return -EIO;
5988af23
RH		 2418 }
2419 }
73885aea
MK		 2420 }
2421 return 0;
2422}
5988af23 2423
73885aea
MK		 2424/**
2425 * onenand_erase - [MTD Interface] erase block(s)
2426 * @param mtd MTD device structure
2427 * @param instr erase instruction
2428 *
2429 * Erase one or more blocks
2430 */
2431static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
2432{
2433 struct onenand_chip *this = mtd->priv;
2434 unsigned int block_size;
2435 loff_t addr = instr->addr;
2436 loff_t len = instr->len;
2437 int ret = 0;
2438 struct mtd_erase_region_info *region = NULL;
2439 loff_t region_offset = 0;
2440
2441 DEBUG(MTD_DEBUG_LEVEL3, "%s: start=0x%012llx, len=%llu\n", __func__,
2442 (unsigned long long) instr->addr, (unsigned long long) instr->len);
2443
2444 /* Do not allow erase past end of device */
2445 if (unlikely((len + addr) > mtd->size)) {
2446 printk(KERN_ERR "%s: Erase past end of device\n", __func__);
2447 return -EINVAL;
cd5f6346
KP		 2448 }
2449
73885aea
MK		 2450 if (FLEXONENAND(this)) {
2451 /* Find the eraseregion of this address */
2452 int i = flexonenand_region(mtd, addr);
cd5f6346 2453
73885aea
MK		 2454 region = &mtd->eraseregions[i];
2455 block_size = region->erasesize;
cd5f6346 2456
73885aea
MK		 2457 /* Start address within region must align on block boundary.
2458 * Erase region's start offset is always block start address.
2459 */
2460 region_offset = region->offset;
2461 } else
2462 block_size = 1 << this->erase_shift;
2463
2464 /* Start address must align on block boundary */
2465 if (unlikely((addr - region_offset) & (block_size - 1))) {
2466 printk(KERN_ERR "%s: Unaligned address\n", __func__);
2467 return -EINVAL;
2468 }
2469
2470 /* Length must align on block boundary */
2471 if (unlikely(len & (block_size - 1))) {
2472 printk(KERN_ERR "%s: Length not block aligned\n", __func__);
2473 return -EINVAL;
2474 }
2475
2476 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2477
2478 /* Grab the lock and see if the device is available */
2479 onenand_get_device(mtd, FL_ERASING);
2480
72073027
MK		 2481 if (region || instr->len < MB_ERASE_MIN_BLK_COUNT * block_size) {
2482 /* region is set for Flex-OneNAND (no mb erase) */
2483 ret = onenand_block_by_block_erase(mtd, instr,
2484 region, block_size);
2485 } else {
2486 ret = onenand_multiblock_erase(mtd, instr, block_size);
2487 }
cd5f6346
KP		 2488
2489 /* Deselect and wake up anyone waiting on the device */
2490 onenand_release_device(mtd);
2491
3cd3a86b 2492 /* Do call back function */
73885aea
MK		 2493 if (!ret) {
2494 instr->state = MTD_ERASE_DONE;
3cd3a86b 2495 mtd_erase_callback(instr);
73885aea 2496 }
3cd3a86b 2497
cd5f6346
KP		 2498 return ret;
2499}
2500
2501/**
2502 * onenand_sync - [MTD Interface] sync
2503 * @param mtd MTD device structure
2504 *
2505 * Sync is actually a wait for chip ready function
2506 */
2507static void onenand_sync(struct mtd_info *mtd)
2508{
297758f8 2509 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
cd5f6346
KP		 2510
2511 /* Grab the lock and see if the device is available */
2512 onenand_get_device(mtd, FL_SYNCING);
2513
2514 /* Release it and go back */
2515 onenand_release_device(mtd);
2516}
2517
2518/**
2519 * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2520 * @param mtd MTD device structure
2521 * @param ofs offset relative to mtd start
cdc00130
KP		 2522 *
2523 * Check whether the block is bad
cd5f6346
KP		 2524 */
2525static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
2526{
49dc08ee
AB		 2527 int ret;
2528
cdc00130
KP		 2529 /* Check for invalid offset */
2530 if (ofs > mtd->size)
2531 return -EINVAL;
2532
49dc08ee
AB		 2533 onenand_get_device(mtd, FL_READING);
2534 ret = onenand_block_isbad_nolock(mtd, ofs, 0);
2535 onenand_release_device(mtd);
2536 return ret;
cdc00130
KP		 2537}
2538
2539/**
2540 * onenand_default_block_markbad - [DEFAULT] mark a block bad
2541 * @param mtd MTD device structure
2542 * @param ofs offset from device start
2543 *
2544 * This is the default implementation, which can be overridden by
2545 * a hardware specific driver.
2546 */
2547static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
2548{
2549 struct onenand_chip *this = mtd->priv;
2550 struct bbm_info *bbm = this->bbm;
2551 u_char buf[2] = {0, 0};
12f77c9e
KP		 2552 struct mtd_oob_ops ops = {
2553 .mode = MTD_OOB_PLACE,
2554 .ooblen = 2,
2555 .oobbuf = buf,
2556 .ooboffs = 0,
2557 };
cdc00130
KP		 2558 int block;
2559
2560 /* Get block number */
5988af23 2561 block = onenand_block(this, ofs);
cdc00130
KP		 2562 if (bbm->bbt)
2563 bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
2564
492e1501 2565 /* We write two bytes, so we don't have to mess with 16-bit access */
cdc00130 2566 ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
5988af23
RH		 2567 /* FIXME : What to do when marking SLC block in partition
2568 * with MLC erasesize? For now, it is not advisable to
2569 * create partitions containing both SLC and MLC regions.
2570 */
2571 return onenand_write_oob_nolock(mtd, ofs, &ops);
cd5f6346
KP		 2572}
2573
2574/**
2575 * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2576 * @param mtd MTD device structure
2577 * @param ofs offset relative to mtd start
cdc00130
KP		 2578 *
2579 * Mark the block as bad
cd5f6346
KP		 2580 */
2581static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2582{
cdc00130
KP		 2583 struct onenand_chip *this = mtd->priv;
2584 int ret;
2585
2586 ret = onenand_block_isbad(mtd, ofs);
2587 if (ret) {
2588 /* If it was bad already, return success and do nothing */
2589 if (ret > 0)
2590 return 0;
2591 return ret;
2592 }
2593
49dc08ee
AB		 2594 onenand_get_device(mtd, FL_WRITING);
2595 ret = this->block_markbad(mtd, ofs);
2596 onenand_release_device(mtd);
2597 return ret;
cd5f6346
KP		 2598}
2599
2600/**
08f782b6 2601 * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s)
cd5f6346
KP		 2602 * @param mtd MTD device structure
2603 * @param ofs offset relative to mtd start
08f782b6 2604 * @param len number of bytes to lock or unlock
e3da8067 2605 * @param cmd lock or unlock command
cd5f6346 2606 *
08f782b6 2607 * Lock or unlock one or more blocks
cd5f6346 2608 */
08f782b6 2609static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd)
cd5f6346
KP		 2610{
2611 struct onenand_chip *this = mtd->priv;
2612 int start, end, block, value, status;
08f782b6 2613 int wp_status_mask;
cd5f6346 2614
5988af23
RH		 2615 start = onenand_block(this, ofs);
2616 end = onenand_block(this, ofs + len) - 1;
cd5f6346 2617
08f782b6
KP		 2618 if (cmd == ONENAND_CMD_LOCK)
2619 wp_status_mask = ONENAND_WP_LS;
2620 else
2621 wp_status_mask = ONENAND_WP_US;
2622
cd5f6346 2623 /* Continuous lock scheme */
28b79ff9 2624 if (this->options & ONENAND_HAS_CONT_LOCK) {
cd5f6346
KP		 2625 /* Set start block address */
2626 this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2627 /* Set end block address */
5988af23 2628 this->write_word(end, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
08f782b6
KP		 2629 /* Write lock command */
2630 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2631
2632 /* There's no return value */
08f782b6 2633 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2634
2635 /* Sanity check */
2636 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2637 & ONENAND_CTRL_ONGO)
2638 continue;
2639
2640 /* Check lock status */
2641 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2642 if (!(status & wp_status_mask))
297758f8
AKS		 2643 printk(KERN_ERR "%s: wp status = 0x%x\n",
2644 __func__, status);
cd5f6346
KP		 2645
2646 return 0;
2647 }
2648
2649 /* Block lock scheme */
5988af23 2650 for (block = start; block < end + 1; block++) {
20ba89a3
KP		 2651 /* Set block address */
2652 value = onenand_block_address(this, block);
2653 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2654 /* Select DataRAM for DDP */
2655 value = onenand_bufferram_address(this, block);
2656 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
cd5f6346
KP		 2657 /* Set start block address */
2658 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
08f782b6
KP		 2659 /* Write lock command */
2660 this->command(mtd, cmd, 0, 0);
cd5f6346
KP		 2661
2662 /* There's no return value */
08f782b6 2663 this->wait(mtd, FL_LOCKING);
cd5f6346
KP		 2664
2665 /* Sanity check */
2666 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2667 & ONENAND_CTRL_ONGO)
2668 continue;
2669
cd5f6346
KP		 2670 /* Check lock status */
2671 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
08f782b6 2672 if (!(status & wp_status_mask))
297758f8
AKS		 2673 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2674 __func__, block, status);
cd5f6346 2675 }
d5c5e78a 2676
cd5f6346
KP		 2677 return 0;
2678}
2679
08f782b6
KP		 2680/**
2681 * onenand_lock - [MTD Interface] Lock block(s)
2682 * @param mtd MTD device structure
2683 * @param ofs offset relative to mtd start
2684 * @param len number of bytes to unlock
2685 *
2686 * Lock one or more blocks
2687 */
69423d99 2688static int onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2689{
34627f0e
AH		 2690 int ret;
2691
2692 onenand_get_device(mtd, FL_LOCKING);
2693 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK);
2694 onenand_release_device(mtd);
2695 return ret;
08f782b6
KP		 2696}
2697
08f782b6
KP		 2698/**
2699 * onenand_unlock - [MTD Interface] Unlock block(s)
2700 * @param mtd MTD device structure
2701 * @param ofs offset relative to mtd start
2702 * @param len number of bytes to unlock
2703 *
2704 * Unlock one or more blocks
2705 */
69423d99 2706static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
08f782b6 2707{
34627f0e
AH		 2708 int ret;
2709
2710 onenand_get_device(mtd, FL_LOCKING);
2711 ret = onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
2712 onenand_release_device(mtd);
2713 return ret;
08f782b6
KP		 2714}
2715
28b79ff9
KP		 2716/**
2717 * onenand_check_lock_status - [OneNAND Interface] Check lock status
2718 * @param this onenand chip data structure
2719 *
2720 * Check lock status
2721 */
66a10506 2722static int onenand_check_lock_status(struct onenand_chip *this)
28b79ff9
KP		 2723{
2724 unsigned int value, block, status;
2725 unsigned int end;
2726
2727 end = this->chipsize >> this->erase_shift;
2728 for (block = 0; block < end; block++) {
2729 /* Set block address */
2730 value = onenand_block_address(this, block);
2731 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
2732 /* Select DataRAM for DDP */
2733 value = onenand_bufferram_address(this, block);
2734 this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
2735 /* Set start block address */
2736 this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
2737
2738 /* Check lock status */
2739 status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
66a10506 2740 if (!(status & ONENAND_WP_US)) {
297758f8
AKS		 2741 printk(KERN_ERR "%s: block = %d, wp status = 0x%x\n",
2742 __func__, block, status);
66a10506
KP		 2743 return 0;
2744 }
28b79ff9 2745 }
66a10506
KP		 2746
2747 return 1;
28b79ff9
KP		 2748}
2749
2750/**
2751 * onenand_unlock_all - [OneNAND Interface] unlock all blocks
2752 * @param mtd MTD device structure
2753 *
2754 * Unlock all blocks
2755 */
66a10506 2756static void onenand_unlock_all(struct mtd_info *mtd)
28b79ff9
KP		 2757{
2758 struct onenand_chip *this = mtd->priv;
66a10506 2759 loff_t ofs = 0;
5988af23 2760 loff_t len = mtd->size;
28b79ff9
KP		 2761
2762 if (this->options & ONENAND_HAS_UNLOCK_ALL) {
10b7a2bd
KP		 2763 /* Set start block address */
2764 this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
28b79ff9
KP		 2765 /* Write unlock command */
2766 this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
2767
2768 /* There's no return value */
08f782b6 2769 this->wait(mtd, FL_LOCKING);
28b79ff9
KP		 2770
2771 /* Sanity check */
2772 while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
2773 & ONENAND_CTRL_ONGO)
2774 continue;
2775
31bb999e
KP		 2776 /* Don't check lock status */
2777 if (this->options & ONENAND_SKIP_UNLOCK_CHECK)
2778 return;
2779
66a10506
KP		 2780 /* Check lock status */
2781 if (onenand_check_lock_status(this))
2782 return;
2783
28b79ff9 2784 /* Workaround for all block unlock in DDP */
5988af23 2785 if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) {
66a10506
KP		 2786 /* All blocks on another chip */
2787 ofs = this->chipsize >> 1;
2788 len = this->chipsize >> 1;
28b79ff9 2789 }
28b79ff9
KP		 2790 }
2791
66a10506 2792 onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
28b79ff9
KP		 2793}
2794
493c6460
KP		 2795#ifdef CONFIG_MTD_ONENAND_OTP
2796
3cf60253
AKS		 2797/**
2798 * onenand_otp_command - Send OTP specific command to OneNAND device
2799 * @param mtd MTD device structure
2800 * @param cmd the command to be sent
2801 * @param addr offset to read from or write to
2802 * @param len number of bytes to read or write
2803 */
2804static int onenand_otp_command(struct mtd_info *mtd, int cmd, loff_t addr,
2805 size_t len)
2806{
2807 struct onenand_chip *this = mtd->priv;
2808 int value, block, page;
2809
2810 /* Address translation */
2811 switch (cmd) {
2812 case ONENAND_CMD_OTP_ACCESS:
2813 block = (int) (addr >> this->erase_shift);
2814 page = -1;
2815 break;
2816
2817 default:
2818 block = (int) (addr >> this->erase_shift);
2819 page = (int) (addr >> this->page_shift);
2820
2821 if (ONENAND_IS_2PLANE(this)) {
2822 /* Make the even block number */
2823 block &= ~1;
2824 /* Is it the odd plane? */
2825 if (addr & this->writesize)
2826 block++;
2827 page >>= 1;
2828 }
2829 page &= this->page_mask;
2830 break;
2831 }
2832
2833 if (block != -1) {
2834 /* Write 'DFS, FBA' of Flash */
2835 value = onenand_block_address(this, block);
2836 this->write_word(value, this->base +
2837 ONENAND_REG_START_ADDRESS1);
2838 }
2839
2840 if (page != -1) {
2841 /* Now we use page size operation */
2842 int sectors = 4, count = 4;
2843 int dataram;
2844
2845 switch (cmd) {
2846 default:
2847 if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
2848 cmd = ONENAND_CMD_2X_PROG;
2849 dataram = ONENAND_CURRENT_BUFFERRAM(this);
2850 break;
2851 }
2852
2853 /* Write 'FPA, FSA' of Flash */
2854 value = onenand_page_address(page, sectors);
2855 this->write_word(value, this->base +
2856 ONENAND_REG_START_ADDRESS8);
2857
2858 /* Write 'BSA, BSC' of DataRAM */
2859 value = onenand_buffer_address(dataram, sectors, count);
2860 this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
2861 }
2862
2863 /* Interrupt clear */
2864 this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
2865
2866 /* Write command */
2867 this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
2868
2869 return 0;
2870}
2871
2872/**
2873 * onenand_otp_write_oob_nolock - [Internal] OneNAND write out-of-band, specific to OTP
2874 * @param mtd MTD device structure
2875 * @param to offset to write to
2876 * @param len number of bytes to write
2877 * @param retlen pointer to variable to store the number of written bytes
2878 * @param buf the data to write
2879 *
2880 * OneNAND write out-of-band only for OTP
2881 */
2882static int onenand_otp_write_oob_nolock(struct mtd_info *mtd, loff_t to,
2883 struct mtd_oob_ops *ops)
2884{
2885 struct onenand_chip *this = mtd->priv;
2886 int column, ret = 0, oobsize;
2887 int written = 0;
2888 u_char *oobbuf;
2889 size_t len = ops->ooblen;
2890 const u_char *buf = ops->oobbuf;
2891 int block, value, status;
2892
2893 to += ops->ooboffs;
2894
2895 /* Initialize retlen, in case of early exit */
2896 ops->oobretlen = 0;
2897
2898 oobsize = mtd->oobsize;
2899
2900 column = to & (mtd->oobsize - 1);
2901
2902 oobbuf = this->oob_buf;
2903
2904 /* Loop until all data write */
2905 while (written < len) {
2906 int thislen = min_t(int, oobsize, len - written);
2907
2908 cond_resched();
2909
2910 block = (int) (to >> this->erase_shift);
2911 /*
2912 * Write 'DFS, FBA' of Flash
2913 * Add: F100h DQ=DFS, FBA
2914 */
2915
2916 value = onenand_block_address(this, block);
2917 this->write_word(value, this->base +
2918 ONENAND_REG_START_ADDRESS1);
2919
2920 /*
2921 * Select DataRAM for DDP
2922 * Add: F101h DQ=DBS
2923 */
2924
2925 value = onenand_bufferram_address(this, block);
2926 this->write_word(value, this->base +
2927 ONENAND_REG_START_ADDRESS2);
2928 ONENAND_SET_NEXT_BUFFERRAM(this);
2929
2930 /*
2931 * Enter OTP access mode
2932 */
2933 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
2934 this->wait(mtd, FL_OTPING);
2935
2936 /* We send data to spare ram with oobsize
2937 * to prevent byte access */
2938 memcpy(oobbuf + column, buf, thislen);
2939
2940 /*
2941 * Write Data into DataRAM
2942 * Add: 8th Word
2943 * in sector0/spare/page0
2944 * DQ=XXFCh
2945 */
2946 this->write_bufferram(mtd, ONENAND_SPARERAM,
2947 oobbuf, 0, mtd->oobsize);
2948
2949 onenand_otp_command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
2950 onenand_update_bufferram(mtd, to, 0);
2951 if (ONENAND_IS_2PLANE(this)) {
2952 ONENAND_SET_BUFFERRAM1(this);
2953 onenand_update_bufferram(mtd, to + this->writesize, 0);
2954 }
2955
2956 ret = this->wait(mtd, FL_WRITING);
2957 if (ret) {
2958 printk(KERN_ERR "%s: write failed %d\n", __func__, ret);
2959 break;
2960 }
2961
2962 /* Exit OTP access mode */
2963 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
2964 this->wait(mtd, FL_RESETING);
2965
2966 status = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
2967 status &= 0x60;
2968
2969 if (status == 0x60) {
2970 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2971 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2972 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
2973 } else if (status == 0x20) {
2974 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2975 printk(KERN_DEBUG "1st Block\tLOCKED\n");
2976 printk(KERN_DEBUG "OTP Block\tUN-LOCKED\n");
2977 } else if (status == 0x40) {
2978 printk(KERN_DEBUG "\nBLOCK\tSTATUS\n");
2979 printk(KERN_DEBUG "1st Block\tUN-LOCKED\n");
2980 printk(KERN_DEBUG "OTP Block\tLOCKED\n");
2981 } else {
2982 printk(KERN_DEBUG "Reboot to check\n");
2983 }
2984
2985 written += thislen;
2986 if (written == len)
2987 break;
2988
2989 to += mtd->writesize;
2990 buf += thislen;
2991 column = 0;
2992 }
2993
2994 ops->oobretlen = written;
2995
2996 return ret;
2997}
2998
492e1501 2999/* Internal OTP operation */
493c6460
KP		 3000typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len,
3001 size_t *retlen, u_char *buf);
3002
3003/**
3004 * do_otp_read - [DEFAULT] Read OTP block area
3005 * @param mtd MTD device structure
3006 * @param from The offset to read
3007 * @param len number of bytes to read
3008 * @param retlen pointer to variable to store the number of readbytes
3009 * @param buf the databuffer to put/get data
3010 *
3011 * Read OTP block area.
3012 */
3013static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
3014 size_t *retlen, u_char *buf)
3015{
3016 struct onenand_chip *this = mtd->priv;
49dc08ee
AB		 3017 struct mtd_oob_ops ops = {
3018 .len = len,
3019 .ooblen = 0,
3020 .datbuf = buf,
3021 .oobbuf = NULL,
3022 };
493c6460
KP		 3023 int ret;
3024
3025 /* Enter OTP access mode */
3026 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3027 this->wait(mtd, FL_OTPING);
3028
6a88c47b 3029 ret = ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this) ?
5988af23
RH		 3030 onenand_mlc_read_ops_nolock(mtd, from, &ops) :
3031 onenand_read_ops_nolock(mtd, from, &ops);
493c6460
KP		 3032
3033 /* Exit OTP access mode */
3034 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3035 this->wait(mtd, FL_RESETING);
3036
3037 return ret;
3038}
3039
3040/**
3041 * do_otp_write - [DEFAULT] Write OTP block area
3042 * @param mtd MTD device structure
49dc08ee 3043 * @param to The offset to write
493c6460
KP		 3044 * @param len number of bytes to write
3045 * @param retlen pointer to variable to store the number of write bytes
3046 * @param buf the databuffer to put/get data
3047 *
3048 * Write OTP block area.
3049 */
49dc08ee 3050static int do_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
493c6460
KP		 3051 size_t *retlen, u_char *buf)
3052{
3053 struct onenand_chip *this = mtd->priv;
3054 unsigned char *pbuf = buf;
3055 int ret;
49dc08ee 3056 struct mtd_oob_ops ops;
493c6460
KP		 3057
3058 /* Force buffer page aligned */
28318776 3059 if (len < mtd->writesize) {
493c6460 3060 memcpy(this->page_buf, buf, len);
28318776 3061 memset(this->page_buf + len, 0xff, mtd->writesize - len);
493c6460 3062 pbuf = this->page_buf;
28318776 3063 len = mtd->writesize;
493c6460
KP		 3064 }
3065
3066 /* Enter OTP access mode */
3067 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3068 this->wait(mtd, FL_OTPING);
3069
49dc08ee
AB		 3070 ops.len = len;
3071 ops.ooblen = 0;
1437085c 3072 ops.datbuf = pbuf;
49dc08ee
AB		 3073 ops.oobbuf = NULL;
3074 ret = onenand_write_ops_nolock(mtd, to, &ops);
3075 *retlen = ops.retlen;
493c6460
KP		 3076
3077 /* Exit OTP access mode */
3078 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3079 this->wait(mtd, FL_RESETING);
3080
3081 return ret;
3082}
3083
3084/**
3085 * do_otp_lock - [DEFAULT] Lock OTP block area
3086 * @param mtd MTD device structure
3087 * @param from The offset to lock
3088 * @param len number of bytes to lock
3089 * @param retlen pointer to variable to store the number of lock bytes
3090 * @param buf the databuffer to put/get data
3091 *
3092 * Lock OTP block area.
3093 */
3094static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len,
3095 size_t *retlen, u_char *buf)
3096{
3097 struct onenand_chip *this = mtd->priv;
5988af23 3098 struct mtd_oob_ops ops;
493c6460
KP		 3099 int ret;
3100
5988af23 3101 if (FLEXONENAND(this)) {
3cf60253
AKS		 3102
3103 /* Enter OTP access mode */
3104 this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0);
3105 this->wait(mtd, FL_OTPING);
5988af23
RH		 3106 /*
3107 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3108 * main area of page 49.
3109 */
3110 ops.len = mtd->writesize;
3111 ops.ooblen = 0;
3112 ops.datbuf = buf;
3113 ops.oobbuf = NULL;
3114 ret = onenand_write_ops_nolock(mtd, mtd->writesize * 49, &ops);
3115 *retlen = ops.retlen;
3cf60253
AKS		 3116
3117 /* Exit OTP access mode */
3118 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3119 this->wait(mtd, FL_RESETING);
5988af23
RH		 3120 } else {
3121 ops.mode = MTD_OOB_PLACE;
3122 ops.ooblen = len;
3123 ops.oobbuf = buf;
3124 ops.ooboffs = 0;
3cf60253 3125 ret = onenand_otp_write_oob_nolock(mtd, from, &ops);
5988af23
RH		 3126 *retlen = ops.oobretlen;
3127 }
493c6460 3128
493c6460
KP		 3129 return ret;
3130}
3131
3132/**
3133 * onenand_otp_walk - [DEFAULT] Handle OTP operation
3134 * @param mtd MTD device structure
3135 * @param from The offset to read/write
3136 * @param len number of bytes to read/write
3137 * @param retlen pointer to variable to store the number of read bytes
3138 * @param buf the databuffer to put/get data
3139 * @param action do given action
3140 * @param mode specify user and factory
3141 *
3142 * Handle OTP operation.
3143 */
3144static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
3145 size_t *retlen, u_char *buf,
3146 otp_op_t action, int mode)
3147{
3148 struct onenand_chip *this = mtd->priv;
3149 int otp_pages;
3150 int density;
3151 int ret = 0;
3152
3153 *retlen = 0;
3154
e71f04fc 3155 density = onenand_get_density(this->device_id);
493c6460
KP		 3156 if (density < ONENAND_DEVICE_DENSITY_512Mb)
3157 otp_pages = 20;
3158 else
3cf60253 3159 otp_pages = 50;
493c6460
KP		 3160
3161 if (mode == MTD_OTP_FACTORY) {
28318776 3162 from += mtd->writesize * otp_pages;
3cf60253 3163 otp_pages = ONENAND_PAGES_PER_BLOCK - otp_pages;
493c6460
KP		 3164 }
3165
3166 /* Check User/Factory boundary */
3cf60253 3167 if (mode == MTD_OTP_USER) {
0a032a4d 3168 if (mtd->writesize * otp_pages < from + len)
3cf60253
AKS		 3169 return 0;
3170 } else {
0a032a4d 3171 if (mtd->writesize * otp_pages < len)
3cf60253
AKS		 3172 return 0;
3173 }
493c6460 3174
49dc08ee 3175 onenand_get_device(mtd, FL_OTPING);
493c6460
KP		 3176 while (len > 0 && otp_pages > 0) {
3177 if (!action) { /* OTP Info functions */
3178 struct otp_info *otpinfo;
3179
3180 len -= sizeof(struct otp_info);
49dc08ee
AB		 3181 if (len <= 0) {
3182 ret = -ENOSPC;
3183 break;
3184 }
493c6460
KP		 3185
3186 otpinfo = (struct otp_info *) buf;
3187 otpinfo->start = from;
28318776 3188 otpinfo->length = mtd->writesize;
493c6460
KP		 3189 otpinfo->locked = 0;
3190
28318776 3191 from += mtd->writesize;
493c6460
KP		 3192 buf += sizeof(struct otp_info);
3193 *retlen += sizeof(struct otp_info);
3194 } else {
3195 size_t tmp_retlen;
493c6460
KP		 3196
3197 ret = action(mtd, from, len, &tmp_retlen, buf);
3198
3cf60253
AKS		 3199 buf += tmp_retlen;
3200 len -= tmp_retlen;
3201 *retlen += tmp_retlen;
493c6460 3202
49dc08ee
AB		 3203 if (ret)
3204 break;
493c6460
KP		 3205 }
3206 otp_pages--;
3207 }
49dc08ee 3208 onenand_release_device(mtd);
493c6460 3209
49dc08ee 3210 return ret;
493c6460
KP		 3211}
3212
3213/**
3214 * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info
3215 * @param mtd MTD device structure
3216 * @param buf the databuffer to put/get data
3217 * @param len number of bytes to read
3218 *
3219 * Read factory OTP info.
3220 */
3221static int onenand_get_fact_prot_info(struct mtd_info *mtd,
3222 struct otp_info *buf, size_t len)
3223{
3224 size_t retlen;
3225 int ret;
3226
3227 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY);
3228
3229 return ret ? : retlen;
3230}
3231
3232/**
3233 * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area
3234 * @param mtd MTD device structure
3235 * @param from The offset to read
3236 * @param len number of bytes to read
3237 * @param retlen pointer to variable to store the number of read bytes
3238 * @param buf the databuffer to put/get data
3239 *
3240 * Read factory OTP area.
3241 */
3242static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
3243 size_t len, size_t *retlen, u_char *buf)
3244{
3245 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY);
3246}
3247
3248/**
3249 * onenand_get_user_prot_info - [MTD Interface] Read user OTP info
3250 * @param mtd MTD device structure
3251 * @param buf the databuffer to put/get data
3252 * @param len number of bytes to read
3253 *
3254 * Read user OTP info.
3255 */
3256static int onenand_get_user_prot_info(struct mtd_info *mtd,
3257 struct otp_info *buf, size_t len)
3258{
3259 size_t retlen;
3260 int ret;
3261
3262 ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER);
3263
3264 return ret ? : retlen;
3265}
3266
3267/**
3268 * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area
3269 * @param mtd MTD device structure
3270 * @param from The offset to read
3271 * @param len number of bytes to read
3272 * @param retlen pointer to variable to store the number of read bytes
3273 * @param buf the databuffer to put/get data
3274 *
3275 * Read user OTP area.
3276 */
3277static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
3278 size_t len, size_t *retlen, u_char *buf)
3279{
3280 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER);
3281}
3282
3283/**
3284 * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area
3285 * @param mtd MTD device structure
3286 * @param from The offset to write
3287 * @param len number of bytes to write
3288 * @param retlen pointer to variable to store the number of write bytes
3289 * @param buf the databuffer to put/get data
3290 *
3291 * Write user OTP area.
3292 */
3293static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
3294 size_t len, size_t *retlen, u_char *buf)
3295{
3296 return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER);
3297}
3298
3299/**
3300 * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area
3301 * @param mtd MTD device structure
3302 * @param from The offset to lock
3303 * @param len number of bytes to unlock
3304 *
3305 * Write lock mark on spare area in page 0 in OTP block
3306 */
3307static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
3308 size_t len)
3309{
69d79186 3310 struct onenand_chip *this = mtd->priv;
5988af23 3311 u_char *buf = FLEXONENAND(this) ? this->page_buf : this->oob_buf;
493c6460
KP		 3312 size_t retlen;
3313 int ret;
3cf60253 3314 unsigned int otp_lock_offset = ONENAND_OTP_LOCK_OFFSET;
493c6460 3315
5988af23
RH		 3316 memset(buf, 0xff, FLEXONENAND(this) ? this->writesize
3317 : mtd->oobsize);
493c6460
KP		 3318 /*
3319 * Write lock mark to 8th word of sector0 of page0 of the spare0.
3320 * We write 16 bytes spare area instead of 2 bytes.
5988af23
RH		 3321 * For Flex-OneNAND, we write lock mark to 1st word of sector 4 of
3322 * main area of page 49.
493c6460 3323 */
5988af23 3324
493c6460 3325 from = 0;
5988af23 3326 len = FLEXONENAND(this) ? mtd->writesize : 16;
493c6460 3327
3cf60253
AKS		 3328 /*
3329 * Note: OTP lock operation
3330 * OTP block : 0xXXFC XX 1111 1100
3331 * 1st block : 0xXXF3 (If chip support) XX 1111 0011
3332 * Both : 0xXXF0 (If chip support) XX 1111 0000
3333 */
3334 if (FLEXONENAND(this))
3335 otp_lock_offset = FLEXONENAND_OTP_LOCK_OFFSET;
3336
3337 /* ONENAND_OTP_AREA | ONENAND_OTP_BLOCK0 | ONENAND_OTP_AREA_BLOCK0 */
3338 if (otp == 1)
3339 buf[otp_lock_offset] = 0xFC;
3340 else if (otp == 2)
3341 buf[otp_lock_offset] = 0xF3;
3342 else if (otp == 3)
3343 buf[otp_lock_offset] = 0xF0;
3344 else if (otp != 0)
3345 printk(KERN_DEBUG "[OneNAND] Invalid option selected for OTP\n");
3346
5988af23 3347 ret = onenand_otp_walk(mtd, from, len, &retlen, buf, do_otp_lock, MTD_OTP_USER);
493c6460
KP		 3348
3349 return ret ? : retlen;
3350}
3cf60253 3351
493c6460
KP		 3352#endif /* CONFIG_MTD_ONENAND_OTP */
3353
28b79ff9 3354/**
75384b0d 3355 * onenand_check_features - Check and set OneNAND features
28b79ff9
KP		 3356 * @param mtd MTD data structure
3357 *
75384b0d
KP		 3358 * Check and set OneNAND features
3359 * - lock scheme
ee9745fc 3360 * - two plane
28b79ff9 3361 */
75384b0d 3362static void onenand_check_features(struct mtd_info *mtd)
28b79ff9
KP		 3363{
3364 struct onenand_chip *this = mtd->priv;
3365 unsigned int density, process;
3366
3367 /* Lock scheme depends on density and process */
e71f04fc 3368 density = onenand_get_density(this->device_id);
28b79ff9
KP		 3369 process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
3370
3371 /* Lock scheme */
ee9745fc
KP		 3372 switch (density) {
3373 case ONENAND_DEVICE_DENSITY_4Gb:
6a88c47b
KP		 3374 if (ONENAND_IS_DDP(this))
3375 this->options |= ONENAND_HAS_2PLANE;
3376 else
3377 this->options |= ONENAND_HAS_4KB_PAGE;
ee9745fc
KP		 3378
3379 case ONENAND_DEVICE_DENSITY_2Gb:
492e1501 3380 /* 2Gb DDP does not have 2 plane */
ee9745fc
KP		 3381 if (!ONENAND_IS_DDP(this))
3382 this->options |= ONENAND_HAS_2PLANE;
3383 this->options |= ONENAND_HAS_UNLOCK_ALL;
3384
3385 case ONENAND_DEVICE_DENSITY_1Gb:
28b79ff9 3386 /* A-Die has all block unlock */
ee9745fc 3387 if (process)
28b79ff9 3388 this->options |= ONENAND_HAS_UNLOCK_ALL;
ee9745fc
KP		 3389 break;
3390
3391 default:
3392 /* Some OneNAND has continuous lock scheme */
3393 if (!process)
28b79ff9 3394 this->options |= ONENAND_HAS_CONT_LOCK;
ee9745fc 3395 break;
28b79ff9 3396 }
ee9745fc 3397
6a88c47b 3398 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3399 this->options &= ~ONENAND_HAS_2PLANE;
3400
3401 if (FLEXONENAND(this)) {
3402 this->options &= ~ONENAND_HAS_CONT_LOCK;
3403 this->options |= ONENAND_HAS_UNLOCK_ALL;
3404 }
3405
ee9745fc
KP		 3406 if (this->options & ONENAND_HAS_CONT_LOCK)
3407 printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
3408 if (this->options & ONENAND_HAS_UNLOCK_ALL)
3409 printk(KERN_DEBUG "Chip support all block unlock\n");
3410 if (this->options & ONENAND_HAS_2PLANE)
3411 printk(KERN_DEBUG "Chip has 2 plane\n");
6a88c47b
KP		 3412 if (this->options & ONENAND_HAS_4KB_PAGE)
3413 printk(KERN_DEBUG "Chip has 4KiB pagesize\n");
28b79ff9
KP		 3414}
3415
cd5f6346 3416/**
e3da8067 3417 * onenand_print_device_info - Print device & version ID
cd5f6346 3418 * @param device device ID
e3da8067 3419 * @param version version ID
cd5f6346 3420 *
e3da8067 3421 * Print device & version ID
cd5f6346 3422 */
28b79ff9 3423static void onenand_print_device_info(int device, int version)
cd5f6346 3424{
5988af23 3425 int vcc, demuxed, ddp, density, flexonenand;
cd5f6346
KP		 3426
3427 vcc = device & ONENAND_DEVICE_VCC_MASK;
3428 demuxed = device & ONENAND_DEVICE_IS_DEMUX;
3429 ddp = device & ONENAND_DEVICE_IS_DDP;
e71f04fc 3430 density = onenand_get_density(device);
5988af23
RH		 3431 flexonenand = device & DEVICE_IS_FLEXONENAND;
3432 printk(KERN_INFO "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
3433 demuxed ? "" : "Muxed ",
3434 flexonenand ? "Flex-" : "",
cd5f6346
KP		 3435 ddp ? "(DDP)" : "",
3436 (16 << density),
3437 vcc ? "2.65/3.3" : "1.8",
3438 device);
49dc08ee 3439 printk(KERN_INFO "OneNAND version = 0x%04x\n", version);
cd5f6346
KP		 3440}
3441
3442static const struct onenand_manufacturers onenand_manuf_ids[] = {
3443 {ONENAND_MFR_SAMSUNG, "Samsung"},
ee8f3768 3444 {ONENAND_MFR_NUMONYX, "Numonyx"},
cd5f6346
KP		 3445};
3446
3447/**
3448 * onenand_check_maf - Check manufacturer ID
3449 * @param manuf manufacturer ID
3450 *
3451 * Check manufacturer ID
3452 */
3453static int onenand_check_maf(int manuf)
3454{
37b1cc39
KP		 3455 int size = ARRAY_SIZE(onenand_manuf_ids);
3456 char *name;
cd5f6346
KP		 3457 int i;
3458
37b1cc39 3459 for (i = 0; i < size; i++)
cd5f6346
KP		 3460 if (manuf == onenand_manuf_ids[i].id)
3461 break;
cd5f6346 3462
37b1cc39
KP		 3463 if (i < size)
3464 name = onenand_manuf_ids[i].name;
3465 else
3466 name = "Unknown";
3467
3468 printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf);
cd5f6346 3469
37b1cc39 3470 return (i == size);
cd5f6346
KP		 3471}
3472
5988af23
RH		 3473/**
3474* flexonenand_get_boundary - Reads the SLC boundary
3475* @param onenand_info - onenand info structure
3476**/
3477static int flexonenand_get_boundary(struct mtd_info *mtd)
3478{
3479 struct onenand_chip *this = mtd->priv;
3480 unsigned die, bdry;
3481 int ret, syscfg, locked;
3482
3483 /* Disable ECC */
3484 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3485 this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1);
3486
3487 for (die = 0; die < this->dies; die++) {
3488 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3489 this->wait(mtd, FL_SYNCING);
3490
3491 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3492 ret = this->wait(mtd, FL_READING);
3493
3494 bdry = this->read_word(this->base + ONENAND_DATARAM);
3495 if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3)
3496 locked = 0;
3497 else
3498 locked = 1;
3499 this->boundary[die] = bdry & FLEXONENAND_PI_MASK;
3500
3501 this->command(mtd, ONENAND_CMD_RESET, 0, 0);
3502 ret = this->wait(mtd, FL_RESETING);
3503
3504 printk(KERN_INFO "Die %d boundary: %d%s\n", die,
3505 this->boundary[die], locked ? "(Locked)" : "(Unlocked)");
3506 }
3507
3508 /* Enable ECC */
3509 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3510 return 0;
3511}
3512
3513/**
3514 * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info
3515 * boundary[], diesize[], mtd->size, mtd->erasesize
3516 * @param mtd - MTD device structure
3517 */
3518static void flexonenand_get_size(struct mtd_info *mtd)
3519{
3520 struct onenand_chip *this = mtd->priv;
3521 int die, i, eraseshift, density;
3522 int blksperdie, maxbdry;
3523 loff_t ofs;
3524
3525 density = onenand_get_density(this->device_id);
3526 blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift);
3527 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3528 maxbdry = blksperdie - 1;
3529 eraseshift = this->erase_shift - 1;
3530
3531 mtd->numeraseregions = this->dies << 1;
3532
3533 /* This fills up the device boundary */
3534 flexonenand_get_boundary(mtd);
3535 die = ofs = 0;
3536 i = -1;
3537 for (; die < this->dies; die++) {
3538 if (!die || this->boundary[die-1] != maxbdry) {
3539 i++;
3540 mtd->eraseregions[i].offset = ofs;
3541 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3542 mtd->eraseregions[i].numblocks =
3543 this->boundary[die] + 1;
3544 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3545 eraseshift++;
3546 } else {
3547 mtd->numeraseregions -= 1;
3548 mtd->eraseregions[i].numblocks +=
3549 this->boundary[die] + 1;
3550 ofs += (this->boundary[die] + 1) << (eraseshift - 1);
3551 }
3552 if (this->boundary[die] != maxbdry) {
3553 i++;
3554 mtd->eraseregions[i].offset = ofs;
3555 mtd->eraseregions[i].erasesize = 1 << eraseshift;
3556 mtd->eraseregions[i].numblocks = maxbdry ^
3557 this->boundary[die];
3558 ofs += mtd->eraseregions[i].numblocks << eraseshift;
3559 eraseshift--;
3560 } else
3561 mtd->numeraseregions -= 1;
3562 }
3563
3564 /* Expose MLC erase size except when all blocks are SLC */
3565 mtd->erasesize = 1 << this->erase_shift;
3566 if (mtd->numeraseregions == 1)
3567 mtd->erasesize >>= 1;
3568
3569 printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions);
3570 for (i = 0; i < mtd->numeraseregions; i++)
3571 printk(KERN_INFO "[offset: 0x%08x, erasesize: 0x%05x,"
3572 " numblocks: %04u]\n",
3573 (unsigned int) mtd->eraseregions[i].offset,
3574 mtd->eraseregions[i].erasesize,
3575 mtd->eraseregions[i].numblocks);
3576
3577 for (die = 0, mtd->size = 0; die < this->dies; die++) {
3578 this->diesize[die] = (loff_t)blksperdie << this->erase_shift;
3579 this->diesize[die] -= (loff_t)(this->boundary[die] + 1)
3580 << (this->erase_shift - 1);
3581 mtd->size += this->diesize[die];
3582 }
3583}
3584
3585/**
3586 * flexonenand_check_blocks_erased - Check if blocks are erased
3587 * @param mtd_info - mtd info structure
3588 * @param start - first erase block to check
3589 * @param end - last erase block to check
3590 *
3591 * Converting an unerased block from MLC to SLC
3592 * causes byte values to change. Since both data and its ECC
3593 * have changed, reads on the block give uncorrectable error.
3594 * This might lead to the block being detected as bad.
3595 *
3596 * Avoid this by ensuring that the block to be converted is
3597 * erased.
3598 */
3599static int flexonenand_check_blocks_erased(struct mtd_info *mtd, int start, int end)
3600{
3601 struct onenand_chip *this = mtd->priv;
3602 int i, ret;
3603 int block;
3604 struct mtd_oob_ops ops = {
3605 .mode = MTD_OOB_PLACE,
3606 .ooboffs = 0,
3607 .ooblen = mtd->oobsize,
3608 .datbuf = NULL,
3609 .oobbuf = this->oob_buf,
3610 };
3611 loff_t addr;
3612
3613 printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end);
3614
3615 for (block = start; block <= end; block++) {
3616 addr = flexonenand_addr(this, block);
3617 if (onenand_block_isbad_nolock(mtd, addr, 0))
3618 continue;
3619
3620 /*
3621 * Since main area write results in ECC write to spare,
3622 * it is sufficient to check only ECC bytes for change.
3623 */
3624 ret = onenand_read_oob_nolock(mtd, addr, &ops);
3625 if (ret)
3626 return ret;
3627
3628 for (i = 0; i < mtd->oobsize; i++)
3629 if (this->oob_buf[i] != 0xff)
3630 break;
3631
3632 if (i != mtd->oobsize) {
297758f8
AKS		 3633 printk(KERN_WARNING "%s: Block %d not erased.\n",
3634 __func__, block);
5988af23
RH		 3635 return 1;
3636 }
3637 }
3638
3639 return 0;
3640}
3641
3642/**
3643 * flexonenand_set_boundary - Writes the SLC boundary
3644 * @param mtd - mtd info structure
3645 */
3646int flexonenand_set_boundary(struct mtd_info *mtd, int die,
3647 int boundary, int lock)
3648{
3649 struct onenand_chip *this = mtd->priv;
3650 int ret, density, blksperdie, old, new, thisboundary;
3651 loff_t addr;
3652
3653 /* Change only once for SDP Flex-OneNAND */
3654 if (die && (!ONENAND_IS_DDP(this)))
3655 return 0;
3656
3657 /* boundary value of -1 indicates no required change */
3658 if (boundary < 0 || boundary == this->boundary[die])
3659 return 0;
3660
3661 density = onenand_get_density(this->device_id);
3662 blksperdie = ((16 << density) << 20) >> this->erase_shift;
3663 blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0;
3664
3665 if (boundary >= blksperdie) {
297758f8
AKS		 3666 printk(KERN_ERR "%s: Invalid boundary value. "
3667 "Boundary not changed.\n", __func__);
5988af23
RH		 3668 return -EINVAL;
3669 }
3670
3671 /* Check if converting blocks are erased */
3672 old = this->boundary[die] + (die * this->density_mask);
3673 new = boundary + (die * this->density_mask);
3674 ret = flexonenand_check_blocks_erased(mtd, min(old, new) + 1, max(old, new));
3675 if (ret) {
297758f8
AKS		 3676 printk(KERN_ERR "%s: Please erase blocks "
3677 "before boundary change\n", __func__);
5988af23
RH		 3678 return ret;
3679 }
3680
3681 this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0);
3682 this->wait(mtd, FL_SYNCING);
3683
3684 /* Check is boundary is locked */
3685 this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0);
3686 ret = this->wait(mtd, FL_READING);
3687
3688 thisboundary = this->read_word(this->base + ONENAND_DATARAM);
3689 if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) {
297758f8 3690 printk(KERN_ERR "%s: boundary locked\n", __func__);
5988af23
RH		 3691 ret = 1;
3692 goto out;
3693 }
3694
297758f8 3695 printk(KERN_INFO "Changing die %d boundary: %d%s\n",
5988af23
RH		 3696 die, boundary, lock ? "(Locked)" : "(Unlocked)");
3697
3698 addr = die ? this->diesize[0] : 0;
3699
3700 boundary &= FLEXONENAND_PI_MASK;
3701 boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT);
3702
3703 this->command(mtd, ONENAND_CMD_ERASE, addr, 0);
3704 ret = this->wait(mtd, FL_ERASING);
3705 if (ret) {
f369c7ec
MK		 3706 printk(KERN_ERR "%s: Failed PI erase for Die %d\n",
3707 __func__, die);
5988af23
RH		 3708 goto out;
3709 }
3710
3711 this->write_word(boundary, this->base + ONENAND_DATARAM);
3712 this->command(mtd, ONENAND_CMD_PROG, addr, 0);
3713 ret = this->wait(mtd, FL_WRITING);
3714 if (ret) {
297758f8
AKS		 3715 printk(KERN_ERR "%s: Failed PI write for Die %d\n",
3716 __func__, die);
5988af23
RH		 3717 goto out;
3718 }
3719
3720 this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0);
3721 ret = this->wait(mtd, FL_WRITING);
3722out:
3723 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND);
3724 this->wait(mtd, FL_RESETING);
3725 if (!ret)
3726 /* Recalculate device size on boundary change*/
3727 flexonenand_get_size(mtd);
3728
3729 return ret;
3730}
3731
cd5f6346
KP		 3732/**
3733 * onenand_probe - [OneNAND Interface] Probe the OneNAND device
3734 * @param mtd MTD device structure
3735 *
3736 * OneNAND detection method:
59c51591 3737 * Compare the values from command with ones from register
cd5f6346
KP		 3738 */
3739static int onenand_probe(struct mtd_info *mtd)
3740{
3741 struct onenand_chip *this = mtd->priv;
28b79ff9 3742 int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id;
cd5f6346 3743 int density;
47e777e0
KP		 3744 int syscfg;
3745
3746 /* Save system configuration 1 */
3747 syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1);
3748 /* Clear Sync. Burst Read mode to read BootRAM */
ee8f3768 3749 this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE), this->base + ONENAND_REG_SYS_CFG1);
cd5f6346
KP		 3750
3751 /* Send the command for reading device ID from BootRAM */
3752 this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
3753
3754 /* Read manufacturer and device IDs from BootRAM */
3755 bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
3756 bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
3757
47e777e0
KP		 3758 /* Reset OneNAND to read default register values */
3759 this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
3760 /* Wait reset */
3761 this->wait(mtd, FL_RESETING);
3762
3763 /* Restore system configuration 1 */
3764 this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1);
3765
cd5f6346
KP		 3766 /* Check manufacturer ID */
3767 if (onenand_check_maf(bram_maf_id))
3768 return -ENXIO;
3769
cd5f6346
KP		 3770 /* Read manufacturer and device IDs from Register */
3771 maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
3772 dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
f4f91ac3 3773 ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
5988af23 3774 this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY);
cd5f6346
KP		 3775
3776 /* Check OneNAND device */
3777 if (maf_id != bram_maf_id || dev_id != bram_dev_id)
3778 return -ENXIO;
3779
3780 /* Flash device information */
28b79ff9 3781 onenand_print_device_info(dev_id, ver_id);
cd5f6346 3782 this->device_id = dev_id;
28b79ff9 3783 this->version_id = ver_id;
cd5f6346 3784
e71f04fc 3785 density = onenand_get_density(dev_id);
5988af23
RH		 3786 if (FLEXONENAND(this)) {
3787 this->dies = ONENAND_IS_DDP(this) ? 2 : 1;
3788 /* Maximum possible erase regions */
3789 mtd->numeraseregions = this->dies << 1;
3790 mtd->eraseregions = kzalloc(sizeof(struct mtd_erase_region_info)
3791 * (this->dies << 1), GFP_KERNEL);
3792 if (!mtd->eraseregions)
3793 return -ENOMEM;
3794 }
3795
3796 /*
3797 * For Flex-OneNAND, chipsize represents maximum possible device size.
3798 * mtd->size represents the actual device size.
3799 */
cd5f6346
KP		 3800 this->chipsize = (16 << density) << 20;
3801
3802 /* OneNAND page size & block size */
3803 /* The data buffer size is equal to page size */
28318776 3804 mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
5988af23 3805 /* We use the full BufferRAM */
6a88c47b 3806 if (ONENAND_IS_MLC(this) || ONENAND_IS_4KB_PAGE(this))
5988af23
RH		 3807 mtd->writesize <<= 1;
3808
28318776 3809 mtd->oobsize = mtd->writesize >> 5;
9bfbc9b2 3810 /* Pages per a block are always 64 in OneNAND */
28318776 3811 mtd->erasesize = mtd->writesize << 6;
5988af23
RH		 3812 /*
3813 * Flex-OneNAND SLC area has 64 pages per block.
3814 * Flex-OneNAND MLC area has 128 pages per block.
3815 * Expose MLC erase size to find erase_shift and page_mask.
3816 */
3817 if (FLEXONENAND(this))
3818 mtd->erasesize <<= 1;
cd5f6346
KP		 3819
3820 this->erase_shift = ffs(mtd->erasesize) - 1;
28318776 3821 this->page_shift = ffs(mtd->writesize) - 1;
9bfbc9b2 3822 this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1;
5988af23
RH		 3823 /* Set density mask. it is used for DDP */
3824 if (ONENAND_IS_DDP(this))
3825 this->density_mask = this->chipsize >> (this->erase_shift + 1);
ee9745fc
KP		 3826 /* It's real page size */
3827 this->writesize = mtd->writesize;
cd5f6346 3828
492e1501 3829 /* REVISIT: Multichip handling */
cd5f6346 3830
5988af23
RH		 3831 if (FLEXONENAND(this))
3832 flexonenand_get_size(mtd);
3833 else
3834 mtd->size = this->chipsize;
cd5f6346 3835
75384b0d
KP		 3836 /* Check OneNAND features */
3837 onenand_check_features(mtd);
d5c5e78a 3838
ee9745fc
KP		 3839 /*
3840 * We emulate the 4KiB page and 256KiB erase block size
3841 * But oobsize is still 64 bytes.
3842 * It is only valid if you turn on 2X program support,
3843 * Otherwise it will be ignored by compiler.
3844 */
3845 if (ONENAND_IS_2PLANE(this)) {
3846 mtd->writesize <<= 1;
3847 mtd->erasesize <<= 1;
3848 }
3849
cd5f6346
KP		 3850 return 0;
3851}
3852
a41371eb
KP		 3853/**
3854 * onenand_suspend - [MTD Interface] Suspend the OneNAND flash
3855 * @param mtd MTD device structure
3856 */
3857static int onenand_suspend(struct mtd_info *mtd)
3858{
3859 return onenand_get_device(mtd, FL_PM_SUSPENDED);
3860}
3861
3862/**
3863 * onenand_resume - [MTD Interface] Resume the OneNAND flash
3864 * @param mtd MTD device structure
3865 */
3866static void onenand_resume(struct mtd_info *mtd)
3867{
3868 struct onenand_chip *this = mtd->priv;
3869
3870 if (this->state == FL_PM_SUSPENDED)
3871 onenand_release_device(mtd);
3872 else
297758f8
AKS		 3873 printk(KERN_ERR "%s: resume() called for the chip which is not "
3874 "in suspended state\n", __func__);
a41371eb
KP		 3875}
3876
cd5f6346
KP		 3877/**
3878 * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
3879 * @param mtd MTD device structure
3880 * @param maxchips Number of chips to scan for
3881 *
3882 * This fills out all the not initialized function pointers
3883 * with the defaults.
3884 * The flash ID is read and the mtd/chip structures are
3885 * filled with the appropriate values.
3886 */
3887int onenand_scan(struct mtd_info *mtd, int maxchips)
3888{
5988af23 3889 int i, ret;
cd5f6346
KP		 3890 struct onenand_chip *this = mtd->priv;
3891
3892 if (!this->read_word)
3893 this->read_word = onenand_readw;
3894 if (!this->write_word)
3895 this->write_word = onenand_writew;
3896
3897 if (!this->command)
3898 this->command = onenand_command;
3899 if (!this->wait)
2c22120f 3900 onenand_setup_wait(mtd);
31bb999e
KP		 3901 if (!this->bbt_wait)
3902 this->bbt_wait = onenand_bbt_wait;
3903 if (!this->unlock_all)
3904 this->unlock_all = onenand_unlock_all;
cd5f6346
KP		 3905
3906 if (!this->read_bufferram)
3907 this->read_bufferram = onenand_read_bufferram;
3908 if (!this->write_bufferram)
3909 this->write_bufferram = onenand_write_bufferram;
3910
cdc00130
KP		 3911 if (!this->block_markbad)
3912 this->block_markbad = onenand_default_block_markbad;
3913 if (!this->scan_bbt)
3914 this->scan_bbt = onenand_default_bbt;
3915
cd5f6346
KP		 3916 if (onenand_probe(mtd))
3917 return -ENXIO;
3918
52b0eea7
KP		 3919 /* Set Sync. Burst Read after probing */
3920 if (this->mmcontrol) {
3921 printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
3922 this->read_bufferram = onenand_sync_read_bufferram;
3923 }
3924
532a37cf
KP		 3925 /* Allocate buffers, if necessary */
3926 if (!this->page_buf) {
470bc844 3927 this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL);
532a37cf 3928 if (!this->page_buf) {
297758f8
AKS		 3929 printk(KERN_ERR "%s: Can't allocate page_buf\n",
3930 __func__);
532a37cf
KP		 3931 return -ENOMEM;
3932 }
4a8ce0b0
KP		 3933#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
3934 this->verify_buf = kzalloc(mtd->writesize, GFP_KERNEL);
3935 if (!this->verify_buf) {
3936 kfree(this->page_buf);
3937 return -ENOMEM;
3938 }
3939#endif
532a37cf
KP		 3940 this->options |= ONENAND_PAGEBUF_ALLOC;
3941 }
470bc844
KP		 3942 if (!this->oob_buf) {
3943 this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL);
3944 if (!this->oob_buf) {
297758f8
AKS		 3945 printk(KERN_ERR "%s: Can't allocate oob_buf\n",
3946 __func__);
470bc844
KP		 3947 if (this->options & ONENAND_PAGEBUF_ALLOC) {
3948 this->options &= ~ONENAND_PAGEBUF_ALLOC;
3949 kfree(this->page_buf);
3950 }
3951 return -ENOMEM;
3952 }
3953 this->options |= ONENAND_OOBBUF_ALLOC;
3954 }
532a37cf 3955
cd5f6346
KP		 3956 this->state = FL_READY;
3957 init_waitqueue_head(&this->wq);
3958 spin_lock_init(&this->chip_lock);
3959
60d84f97
KP		 3960 /*
3961 * Allow subpage writes up to oobsize.
3962 */
cd5f6346 3963 switch (mtd->oobsize) {
5988af23
RH		 3964 case 128:
3965 this->ecclayout = &onenand_oob_128;
3966 mtd->subpage_sft = 0;
3967 break;
cd5f6346 3968 case 64:
5bd34c09 3969 this->ecclayout = &onenand_oob_64;
60d84f97 3970 mtd->subpage_sft = 2;
cd5f6346
KP		 3971 break;
3972
3973 case 32:
5bd34c09 3974 this->ecclayout = &onenand_oob_32;
60d84f97 3975 mtd->subpage_sft = 1;
cd5f6346
KP		 3976 break;
3977
3978 default:
297758f8
AKS		 3979 printk(KERN_WARNING "%s: No OOB scheme defined for oobsize %d\n",
3980 __func__, mtd->oobsize);
60d84f97 3981 mtd->subpage_sft = 0;
cd5f6346 3982 /* To prevent kernel oops */
5bd34c09 3983 this->ecclayout = &onenand_oob_32;
cd5f6346
KP		 3984 break;
3985 }
3986
60d84f97 3987 this->subpagesize = mtd->writesize >> mtd->subpage_sft;
a5e7c7b4
AH		 3988
3989 /*
3990 * The number of bytes available for a client to place data into
3991 * the out of band area
3992 */
3993 this->ecclayout->oobavail = 0;
ad286343
KP		 3994 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES &&
3995 this->ecclayout->oobfree[i].length; i++)
a5e7c7b4
AH		 3996 this->ecclayout->oobavail +=
3997 this->ecclayout->oobfree[i].length;
1f92267c 3998 mtd->oobavail = this->ecclayout->oobavail;
a5e7c7b4 3999
5bd34c09 4000 mtd->ecclayout = this->ecclayout;
d5c5e78a 4001
cd5f6346
KP		 4002 /* Fill in remaining MTD driver data */
4003 mtd->type = MTD_NANDFLASH;
5fa43394 4004 mtd->flags = MTD_CAP_NANDFLASH;
cd5f6346
KP		 4005 mtd->erase = onenand_erase;
4006 mtd->point = NULL;
4007 mtd->unpoint = NULL;
4008 mtd->read = onenand_read;
4009 mtd->write = onenand_write;
cd5f6346
KP		 4010 mtd->read_oob = onenand_read_oob;
4011 mtd->write_oob = onenand_write_oob;
6c77fd64 4012 mtd->panic_write = onenand_panic_write;
493c6460
KP		 4013#ifdef CONFIG_MTD_ONENAND_OTP
4014 mtd->get_fact_prot_info = onenand_get_fact_prot_info;
4015 mtd->read_fact_prot_reg = onenand_read_fact_prot_reg;
4016 mtd->get_user_prot_info = onenand_get_user_prot_info;
4017 mtd->read_user_prot_reg = onenand_read_user_prot_reg;
4018 mtd->write_user_prot_reg = onenand_write_user_prot_reg;
4019 mtd->lock_user_prot_reg = onenand_lock_user_prot_reg;
4020#endif
cd5f6346 4021 mtd->sync = onenand_sync;
08f782b6 4022 mtd->lock = onenand_lock;
cd5f6346 4023 mtd->unlock = onenand_unlock;
a41371eb
KP		 4024 mtd->suspend = onenand_suspend;
4025 mtd->resume = onenand_resume;
cd5f6346
KP		 4026 mtd->block_isbad = onenand_block_isbad;
4027 mtd->block_markbad = onenand_block_markbad;
4028 mtd->owner = THIS_MODULE;
4029
4030 /* Unlock whole block */
31bb999e 4031 this->unlock_all(mtd);
cd5f6346 4032
5988af23
RH		 4033 ret = this->scan_bbt(mtd);
4034 if ((!FLEXONENAND(this)) || ret)
4035 return ret;
4036
4037 /* Change Flex-OneNAND boundaries if required */
4038 for (i = 0; i < MAX_DIES; i++)
4039 flexonenand_set_boundary(mtd, i, flex_bdry[2 * i],
4040 flex_bdry[(2 * i) + 1]);
4041
4042 return 0;
cd5f6346
KP		 4043}
4044
4045/**
4046 * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
4047 * @param mtd MTD device structure
4048 */
4049void onenand_release(struct mtd_info *mtd)
4050{
532a37cf
KP		 4051 struct onenand_chip *this = mtd->priv;
4052
cd5f6346
KP		 4053#ifdef CONFIG_MTD_PARTITIONS
4054 /* Deregister partitions */
4055 del_mtd_partitions (mtd);
4056#endif
4057 /* Deregister the device */
4058 del_mtd_device (mtd);
532a37cf
KP		 4059
4060 /* Free bad block table memory, if allocated */
f00b0046
AH		 4061 if (this->bbm) {
4062 struct bbm_info *bbm = this->bbm;
4063 kfree(bbm->bbt);
532a37cf 4064 kfree(this->bbm);
f00b0046 4065 }
470bc844 4066 /* Buffers allocated by onenand_scan */
4a8ce0b0 4067 if (this->options & ONENAND_PAGEBUF_ALLOC) {
532a37cf 4068 kfree(this->page_buf);
4a8ce0b0
KP		 4069#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
4070 kfree(this->verify_buf);
4071#endif
4072 }
470bc844
KP		 4073 if (this->options & ONENAND_OOBBUF_ALLOC)
4074 kfree(this->oob_buf);
5988af23 4075 kfree(mtd->eraseregions);
cd5f6346
KP		 4076}
4077
4078EXPORT_SYMBOL_GPL(onenand_scan);
4079EXPORT_SYMBOL_GPL(onenand_release);
4080
4081MODULE_LICENSE("GPL");
4082MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
4083MODULE_DESCRIPTION("Generic OneNAND flash driver code");
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