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cd5f6346 KP |
1 | /* |
2 | * linux/drivers/mtd/onenand/onenand_base.c | |
3 | * | |
28b79ff9 | 4 | * Copyright (C) 2005-2006 Samsung Electronics |
cd5f6346 KP |
5 | * Kyungmin Park <kyungmin.park@samsung.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
015953d7 | 15 | #include <linux/sched.h> |
2c22120f | 16 | #include <linux/interrupt.h> |
015953d7 | 17 | #include <linux/jiffies.h> |
cd5f6346 KP |
18 | #include <linux/mtd/mtd.h> |
19 | #include <linux/mtd/onenand.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | ||
24 | /** | |
25 | * onenand_oob_64 - oob info for large (2KB) page | |
26 | */ | |
5bd34c09 | 27 | static struct nand_ecclayout onenand_oob_64 = { |
cd5f6346 KP |
28 | .eccbytes = 20, |
29 | .eccpos = { | |
30 | 8, 9, 10, 11, 12, | |
31 | 24, 25, 26, 27, 28, | |
32 | 40, 41, 42, 43, 44, | |
33 | 56, 57, 58, 59, 60, | |
34 | }, | |
35 | .oobfree = { | |
36 | {2, 3}, {14, 2}, {18, 3}, {30, 2}, | |
d9777f1c JL |
37 | {34, 3}, {46, 2}, {50, 3}, {62, 2} |
38 | } | |
cd5f6346 KP |
39 | }; |
40 | ||
41 | /** | |
42 | * onenand_oob_32 - oob info for middle (1KB) page | |
43 | */ | |
5bd34c09 | 44 | static struct nand_ecclayout onenand_oob_32 = { |
cd5f6346 KP |
45 | .eccbytes = 10, |
46 | .eccpos = { | |
47 | 8, 9, 10, 11, 12, | |
48 | 24, 25, 26, 27, 28, | |
49 | }, | |
50 | .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } | |
51 | }; | |
52 | ||
53 | static const unsigned char ffchars[] = { | |
54 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
55 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ | |
56 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
57 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ | |
58 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
59 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ | |
60 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
61 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ | |
62 | }; | |
63 | ||
64 | /** | |
65 | * onenand_readw - [OneNAND Interface] Read OneNAND register | |
66 | * @param addr address to read | |
67 | * | |
68 | * Read OneNAND register | |
69 | */ | |
70 | static unsigned short onenand_readw(void __iomem *addr) | |
71 | { | |
72 | return readw(addr); | |
73 | } | |
74 | ||
75 | /** | |
76 | * onenand_writew - [OneNAND Interface] Write OneNAND register with value | |
77 | * @param value value to write | |
78 | * @param addr address to write | |
79 | * | |
80 | * Write OneNAND register with value | |
81 | */ | |
82 | static void onenand_writew(unsigned short value, void __iomem *addr) | |
83 | { | |
84 | writew(value, addr); | |
85 | } | |
86 | ||
87 | /** | |
88 | * onenand_block_address - [DEFAULT] Get block address | |
83a36838 | 89 | * @param this onenand chip data structure |
cd5f6346 KP |
90 | * @param block the block |
91 | * @return translated block address if DDP, otherwise same | |
92 | * | |
93 | * Setup Start Address 1 Register (F100h) | |
94 | */ | |
83a36838 | 95 | static int onenand_block_address(struct onenand_chip *this, int block) |
cd5f6346 | 96 | { |
83a36838 | 97 | if (this->device_id & ONENAND_DEVICE_IS_DDP) { |
cd5f6346 | 98 | /* Device Flash Core select, NAND Flash Block Address */ |
83a36838 | 99 | int dfs = 0; |
cd5f6346 | 100 | |
83a36838 | 101 | if (block & this->density_mask) |
cd5f6346 KP |
102 | dfs = 1; |
103 | ||
83a36838 KP |
104 | return (dfs << ONENAND_DDP_SHIFT) | |
105 | (block & (this->density_mask - 1)); | |
cd5f6346 KP |
106 | } |
107 | ||
108 | return block; | |
109 | } | |
110 | ||
111 | /** | |
112 | * onenand_bufferram_address - [DEFAULT] Get bufferram address | |
83a36838 | 113 | * @param this onenand chip data structure |
cd5f6346 KP |
114 | * @param block the block |
115 | * @return set DBS value if DDP, otherwise 0 | |
116 | * | |
117 | * Setup Start Address 2 Register (F101h) for DDP | |
118 | */ | |
83a36838 | 119 | static int onenand_bufferram_address(struct onenand_chip *this, int block) |
cd5f6346 | 120 | { |
83a36838 | 121 | if (this->device_id & ONENAND_DEVICE_IS_DDP) { |
cd5f6346 | 122 | /* Device BufferRAM Select */ |
83a36838 | 123 | int dbs = 0; |
cd5f6346 | 124 | |
83a36838 | 125 | if (block & this->density_mask) |
cd5f6346 KP |
126 | dbs = 1; |
127 | ||
128 | return (dbs << ONENAND_DDP_SHIFT); | |
129 | } | |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /** | |
135 | * onenand_page_address - [DEFAULT] Get page address | |
136 | * @param page the page address | |
137 | * @param sector the sector address | |
138 | * @return combined page and sector address | |
139 | * | |
140 | * Setup Start Address 8 Register (F107h) | |
141 | */ | |
142 | static int onenand_page_address(int page, int sector) | |
143 | { | |
144 | /* Flash Page Address, Flash Sector Address */ | |
145 | int fpa, fsa; | |
146 | ||
147 | fpa = page & ONENAND_FPA_MASK; | |
148 | fsa = sector & ONENAND_FSA_MASK; | |
149 | ||
150 | return ((fpa << ONENAND_FPA_SHIFT) | fsa); | |
151 | } | |
152 | ||
153 | /** | |
154 | * onenand_buffer_address - [DEFAULT] Get buffer address | |
155 | * @param dataram1 DataRAM index | |
156 | * @param sectors the sector address | |
157 | * @param count the number of sectors | |
158 | * @return the start buffer value | |
159 | * | |
160 | * Setup Start Buffer Register (F200h) | |
161 | */ | |
162 | static int onenand_buffer_address(int dataram1, int sectors, int count) | |
163 | { | |
164 | int bsa, bsc; | |
165 | ||
166 | /* BufferRAM Sector Address */ | |
167 | bsa = sectors & ONENAND_BSA_MASK; | |
168 | ||
169 | if (dataram1) | |
170 | bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ | |
171 | else | |
172 | bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ | |
173 | ||
174 | /* BufferRAM Sector Count */ | |
175 | bsc = count & ONENAND_BSC_MASK; | |
176 | ||
177 | return ((bsa << ONENAND_BSA_SHIFT) | bsc); | |
178 | } | |
179 | ||
180 | /** | |
181 | * onenand_command - [DEFAULT] Send command to OneNAND device | |
182 | * @param mtd MTD device structure | |
183 | * @param cmd the command to be sent | |
184 | * @param addr offset to read from or write to | |
185 | * @param len number of bytes to read or write | |
186 | * | |
187 | * Send command to OneNAND device. This function is used for middle/large page | |
188 | * devices (1KB/2KB Bytes per page) | |
189 | */ | |
190 | static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) | |
191 | { | |
192 | struct onenand_chip *this = mtd->priv; | |
493c6460 | 193 | int value, readcmd = 0, block_cmd = 0; |
cd5f6346 KP |
194 | int block, page; |
195 | /* Now we use page size operation */ | |
196 | int sectors = 4, count = 4; | |
197 | ||
198 | /* Address translation */ | |
199 | switch (cmd) { | |
200 | case ONENAND_CMD_UNLOCK: | |
201 | case ONENAND_CMD_LOCK: | |
202 | case ONENAND_CMD_LOCK_TIGHT: | |
28b79ff9 | 203 | case ONENAND_CMD_UNLOCK_ALL: |
cd5f6346 KP |
204 | block = -1; |
205 | page = -1; | |
206 | break; | |
207 | ||
208 | case ONENAND_CMD_ERASE: | |
209 | case ONENAND_CMD_BUFFERRAM: | |
493c6460 KP |
210 | case ONENAND_CMD_OTP_ACCESS: |
211 | block_cmd = 1; | |
cd5f6346 KP |
212 | block = (int) (addr >> this->erase_shift); |
213 | page = -1; | |
214 | break; | |
215 | ||
216 | default: | |
217 | block = (int) (addr >> this->erase_shift); | |
218 | page = (int) (addr >> this->page_shift); | |
219 | page &= this->page_mask; | |
220 | break; | |
221 | } | |
222 | ||
223 | /* NOTE: The setting order of the registers is very important! */ | |
224 | if (cmd == ONENAND_CMD_BUFFERRAM) { | |
225 | /* Select DataRAM for DDP */ | |
83a36838 | 226 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
227 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
228 | ||
229 | /* Switch to the next data buffer */ | |
230 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | if (block != -1) { | |
236 | /* Write 'DFS, FBA' of Flash */ | |
83a36838 | 237 | value = onenand_block_address(this, block); |
cd5f6346 | 238 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); |
3cecf69e | 239 | |
75287070 | 240 | if (block_cmd) { |
3cecf69e KP |
241 | /* Select DataRAM for DDP */ |
242 | value = onenand_bufferram_address(this, block); | |
243 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
244 | } | |
cd5f6346 KP |
245 | } |
246 | ||
247 | if (page != -1) { | |
248 | int dataram; | |
249 | ||
250 | switch (cmd) { | |
251 | case ONENAND_CMD_READ: | |
252 | case ONENAND_CMD_READOOB: | |
253 | dataram = ONENAND_SET_NEXT_BUFFERRAM(this); | |
254 | readcmd = 1; | |
255 | break; | |
256 | ||
257 | default: | |
258 | dataram = ONENAND_CURRENT_BUFFERRAM(this); | |
259 | break; | |
260 | } | |
261 | ||
262 | /* Write 'FPA, FSA' of Flash */ | |
263 | value = onenand_page_address(page, sectors); | |
264 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); | |
265 | ||
266 | /* Write 'BSA, BSC' of DataRAM */ | |
267 | value = onenand_buffer_address(dataram, sectors, count); | |
268 | this->write_word(value, this->base + ONENAND_REG_START_BUFFER); | |
d5c5e78a | 269 | |
cd5f6346 KP |
270 | if (readcmd) { |
271 | /* Select DataRAM for DDP */ | |
83a36838 | 272 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
273 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
274 | } | |
275 | } | |
276 | ||
277 | /* Interrupt clear */ | |
278 | this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); | |
279 | ||
280 | /* Write command */ | |
281 | this->write_word(cmd, this->base + ONENAND_REG_COMMAND); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
286 | /** | |
287 | * onenand_wait - [DEFAULT] wait until the command is done | |
288 | * @param mtd MTD device structure | |
289 | * @param state state to select the max. timeout value | |
290 | * | |
291 | * Wait for command done. This applies to all OneNAND command | |
292 | * Read can take up to 30us, erase up to 2ms and program up to 350us | |
293 | * according to general OneNAND specs | |
294 | */ | |
295 | static int onenand_wait(struct mtd_info *mtd, int state) | |
296 | { | |
297 | struct onenand_chip * this = mtd->priv; | |
298 | unsigned long timeout; | |
299 | unsigned int flags = ONENAND_INT_MASTER; | |
300 | unsigned int interrupt = 0; | |
301 | unsigned int ctrl, ecc; | |
302 | ||
303 | /* The 20 msec is enough */ | |
304 | timeout = jiffies + msecs_to_jiffies(20); | |
305 | while (time_before(jiffies, timeout)) { | |
306 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
307 | ||
308 | if (interrupt & flags) | |
309 | break; | |
310 | ||
311 | if (state != FL_READING) | |
312 | cond_resched(); | |
628bee65 | 313 | touch_softlockup_watchdog(); |
cd5f6346 KP |
314 | } |
315 | /* To get correct interrupt status in timeout case */ | |
316 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
317 | ||
318 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
319 | ||
320 | if (ctrl & ONENAND_CTRL_ERROR) { | |
cdc00130 KP |
321 | /* It maybe occur at initial bad block */ |
322 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x\n", ctrl); | |
323 | /* Clear other interrupt bits for preventing ECC error */ | |
324 | interrupt &= ONENAND_INT_MASTER; | |
cd5f6346 KP |
325 | } |
326 | ||
327 | if (ctrl & ONENAND_CTRL_LOCK) { | |
cdc00130 KP |
328 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x\n", ctrl); |
329 | return -EACCES; | |
cd5f6346 KP |
330 | } |
331 | ||
332 | if (interrupt & ONENAND_INT_READ) { | |
333 | ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); | |
334 | if (ecc & ONENAND_ECC_2BIT_ALL) { | |
cdc00130 | 335 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x\n", ecc); |
cd5f6346 KP |
336 | return -EBADMSG; |
337 | } | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
2c22120f KP |
343 | /* |
344 | * onenand_interrupt - [DEFAULT] onenand interrupt handler | |
345 | * @param irq onenand interrupt number | |
346 | * @param dev_id interrupt data | |
347 | * | |
348 | * complete the work | |
349 | */ | |
350 | static irqreturn_t onenand_interrupt(int irq, void *data) | |
351 | { | |
352 | struct onenand_chip *this = (struct onenand_chip *) data; | |
353 | ||
354 | /* To handle shared interrupt */ | |
355 | if (!this->complete.done) | |
356 | complete(&this->complete); | |
357 | ||
358 | return IRQ_HANDLED; | |
359 | } | |
360 | ||
361 | /* | |
362 | * onenand_interrupt_wait - [DEFAULT] wait until the command is done | |
363 | * @param mtd MTD device structure | |
364 | * @param state state to select the max. timeout value | |
365 | * | |
366 | * Wait for command done. | |
367 | */ | |
368 | static int onenand_interrupt_wait(struct mtd_info *mtd, int state) | |
369 | { | |
370 | struct onenand_chip *this = mtd->priv; | |
371 | ||
372 | /* To prevent soft lockup */ | |
373 | touch_softlockup_watchdog(); | |
374 | ||
375 | wait_for_completion(&this->complete); | |
376 | ||
377 | return onenand_wait(mtd, state); | |
378 | } | |
379 | ||
380 | /* | |
381 | * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait | |
382 | * @param mtd MTD device structure | |
383 | * @param state state to select the max. timeout value | |
384 | * | |
385 | * Try interrupt based wait (It is used one-time) | |
386 | */ | |
387 | static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state) | |
388 | { | |
389 | struct onenand_chip *this = mtd->priv; | |
390 | unsigned long remain, timeout; | |
391 | ||
392 | /* We use interrupt wait first */ | |
393 | this->wait = onenand_interrupt_wait; | |
394 | ||
395 | /* To prevent soft lockup */ | |
396 | touch_softlockup_watchdog(); | |
397 | ||
398 | timeout = msecs_to_jiffies(100); | |
399 | remain = wait_for_completion_timeout(&this->complete, timeout); | |
400 | if (!remain) { | |
401 | printk(KERN_INFO "OneNAND: There's no interrupt. " | |
402 | "We use the normal wait\n"); | |
403 | ||
404 | /* Release the irq */ | |
405 | free_irq(this->irq, this); | |
406 | ||
407 | this->wait = onenand_wait; | |
408 | } | |
409 | ||
410 | return onenand_wait(mtd, state); | |
411 | } | |
412 | ||
413 | /* | |
414 | * onenand_setup_wait - [OneNAND Interface] setup onenand wait method | |
415 | * @param mtd MTD device structure | |
416 | * | |
417 | * There's two method to wait onenand work | |
418 | * 1. polling - read interrupt status register | |
419 | * 2. interrupt - use the kernel interrupt method | |
420 | */ | |
421 | static void onenand_setup_wait(struct mtd_info *mtd) | |
422 | { | |
423 | struct onenand_chip *this = mtd->priv; | |
424 | int syscfg; | |
425 | ||
426 | init_completion(&this->complete); | |
427 | ||
428 | if (this->irq <= 0) { | |
429 | this->wait = onenand_wait; | |
430 | return; | |
431 | } | |
432 | ||
433 | if (request_irq(this->irq, &onenand_interrupt, | |
434 | IRQF_SHARED, "onenand", this)) { | |
435 | /* If we can't get irq, use the normal wait */ | |
436 | this->wait = onenand_wait; | |
437 | return; | |
438 | } | |
439 | ||
440 | /* Enable interrupt */ | |
441 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
442 | syscfg |= ONENAND_SYS_CFG1_IOBE; | |
443 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
444 | ||
445 | this->wait = onenand_try_interrupt_wait; | |
446 | } | |
447 | ||
cd5f6346 KP |
448 | /** |
449 | * onenand_bufferram_offset - [DEFAULT] BufferRAM offset | |
450 | * @param mtd MTD data structure | |
451 | * @param area BufferRAM area | |
452 | * @return offset given area | |
453 | * | |
454 | * Return BufferRAM offset given area | |
455 | */ | |
456 | static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) | |
457 | { | |
458 | struct onenand_chip *this = mtd->priv; | |
459 | ||
460 | if (ONENAND_CURRENT_BUFFERRAM(this)) { | |
461 | if (area == ONENAND_DATARAM) | |
28318776 | 462 | return mtd->writesize; |
cd5f6346 KP |
463 | if (area == ONENAND_SPARERAM) |
464 | return mtd->oobsize; | |
465 | } | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | /** | |
471 | * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area | |
472 | * @param mtd MTD data structure | |
473 | * @param area BufferRAM area | |
474 | * @param buffer the databuffer to put/get data | |
475 | * @param offset offset to read from or write to | |
476 | * @param count number of bytes to read/write | |
477 | * | |
478 | * Read the BufferRAM area | |
479 | */ | |
480 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
481 | unsigned char *buffer, int offset, size_t count) | |
482 | { | |
483 | struct onenand_chip *this = mtd->priv; | |
484 | void __iomem *bufferram; | |
485 | ||
486 | bufferram = this->base + area; | |
487 | ||
488 | bufferram += onenand_bufferram_offset(mtd, area); | |
489 | ||
9c01f87d KP |
490 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
491 | unsigned short word; | |
492 | ||
493 | /* Align with word(16-bit) size */ | |
494 | count--; | |
495 | ||
496 | /* Read word and save byte */ | |
497 | word = this->read_word(bufferram + offset + count); | |
498 | buffer[count] = (word & 0xff); | |
499 | } | |
500 | ||
cd5f6346 KP |
501 | memcpy(buffer, bufferram + offset, count); |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
52b0eea7 KP |
506 | /** |
507 | * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode | |
508 | * @param mtd MTD data structure | |
509 | * @param area BufferRAM area | |
510 | * @param buffer the databuffer to put/get data | |
511 | * @param offset offset to read from or write to | |
512 | * @param count number of bytes to read/write | |
513 | * | |
514 | * Read the BufferRAM area with Sync. Burst Mode | |
515 | */ | |
516 | static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, | |
517 | unsigned char *buffer, int offset, size_t count) | |
518 | { | |
519 | struct onenand_chip *this = mtd->priv; | |
520 | void __iomem *bufferram; | |
521 | ||
522 | bufferram = this->base + area; | |
523 | ||
524 | bufferram += onenand_bufferram_offset(mtd, area); | |
525 | ||
526 | this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); | |
527 | ||
9c01f87d KP |
528 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
529 | unsigned short word; | |
530 | ||
531 | /* Align with word(16-bit) size */ | |
532 | count--; | |
533 | ||
534 | /* Read word and save byte */ | |
535 | word = this->read_word(bufferram + offset + count); | |
536 | buffer[count] = (word & 0xff); | |
537 | } | |
538 | ||
52b0eea7 KP |
539 | memcpy(buffer, bufferram + offset, count); |
540 | ||
541 | this->mmcontrol(mtd, 0); | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
cd5f6346 KP |
546 | /** |
547 | * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area | |
548 | * @param mtd MTD data structure | |
549 | * @param area BufferRAM area | |
550 | * @param buffer the databuffer to put/get data | |
551 | * @param offset offset to read from or write to | |
552 | * @param count number of bytes to read/write | |
553 | * | |
554 | * Write the BufferRAM area | |
555 | */ | |
556 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
557 | const unsigned char *buffer, int offset, size_t count) | |
558 | { | |
559 | struct onenand_chip *this = mtd->priv; | |
560 | void __iomem *bufferram; | |
561 | ||
562 | bufferram = this->base + area; | |
563 | ||
564 | bufferram += onenand_bufferram_offset(mtd, area); | |
565 | ||
9c01f87d KP |
566 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
567 | unsigned short word; | |
568 | int byte_offset; | |
569 | ||
570 | /* Align with word(16-bit) size */ | |
571 | count--; | |
572 | ||
573 | /* Calculate byte access offset */ | |
574 | byte_offset = offset + count; | |
575 | ||
576 | /* Read word and save byte */ | |
577 | word = this->read_word(bufferram + byte_offset); | |
578 | word = (word & ~0xff) | buffer[count]; | |
579 | this->write_word(word, bufferram + byte_offset); | |
580 | } | |
581 | ||
cd5f6346 KP |
582 | memcpy(bufferram + offset, buffer, count); |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | /** | |
588 | * onenand_check_bufferram - [GENERIC] Check BufferRAM information | |
589 | * @param mtd MTD data structure | |
590 | * @param addr address to check | |
d5c5e78a | 591 | * @return 1 if there are valid data, otherwise 0 |
cd5f6346 KP |
592 | * |
593 | * Check bufferram if there is data we required | |
594 | */ | |
595 | static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) | |
596 | { | |
597 | struct onenand_chip *this = mtd->priv; | |
598 | int block, page; | |
599 | int i; | |
d5c5e78a | 600 | |
cd5f6346 KP |
601 | block = (int) (addr >> this->erase_shift); |
602 | page = (int) (addr >> this->page_shift); | |
603 | page &= this->page_mask; | |
604 | ||
605 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
606 | ||
607 | /* Is there valid data? */ | |
608 | if (this->bufferram[i].block == block && | |
609 | this->bufferram[i].page == page && | |
610 | this->bufferram[i].valid) | |
611 | return 1; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | /** | |
617 | * onenand_update_bufferram - [GENERIC] Update BufferRAM information | |
618 | * @param mtd MTD data structure | |
619 | * @param addr address to update | |
620 | * @param valid valid flag | |
621 | * | |
622 | * Update BufferRAM information | |
623 | */ | |
624 | static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, | |
625 | int valid) | |
626 | { | |
627 | struct onenand_chip *this = mtd->priv; | |
628 | int block, page; | |
629 | int i; | |
d5c5e78a | 630 | |
cd5f6346 KP |
631 | block = (int) (addr >> this->erase_shift); |
632 | page = (int) (addr >> this->page_shift); | |
633 | page &= this->page_mask; | |
634 | ||
635 | /* Invalidate BufferRAM */ | |
636 | for (i = 0; i < MAX_BUFFERRAM; i++) { | |
637 | if (this->bufferram[i].block == block && | |
638 | this->bufferram[i].page == page) | |
639 | this->bufferram[i].valid = 0; | |
640 | } | |
641 | ||
642 | /* Update BufferRAM */ | |
643 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
644 | this->bufferram[i].block = block; | |
645 | this->bufferram[i].page = page; | |
646 | this->bufferram[i].valid = valid; | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /** | |
652 | * onenand_get_device - [GENERIC] Get chip for selected access | |
653 | * @param mtd MTD device structure | |
654 | * @param new_state the state which is requested | |
655 | * | |
656 | * Get the device and lock it for exclusive access | |
657 | */ | |
a41371eb | 658 | static int onenand_get_device(struct mtd_info *mtd, int new_state) |
cd5f6346 KP |
659 | { |
660 | struct onenand_chip *this = mtd->priv; | |
661 | DECLARE_WAITQUEUE(wait, current); | |
662 | ||
663 | /* | |
664 | * Grab the lock and see if the device is available | |
665 | */ | |
666 | while (1) { | |
667 | spin_lock(&this->chip_lock); | |
668 | if (this->state == FL_READY) { | |
669 | this->state = new_state; | |
670 | spin_unlock(&this->chip_lock); | |
671 | break; | |
672 | } | |
a41371eb KP |
673 | if (new_state == FL_PM_SUSPENDED) { |
674 | spin_unlock(&this->chip_lock); | |
675 | return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; | |
676 | } | |
cd5f6346 KP |
677 | set_current_state(TASK_UNINTERRUPTIBLE); |
678 | add_wait_queue(&this->wq, &wait); | |
679 | spin_unlock(&this->chip_lock); | |
680 | schedule(); | |
681 | remove_wait_queue(&this->wq, &wait); | |
682 | } | |
a41371eb KP |
683 | |
684 | return 0; | |
cd5f6346 KP |
685 | } |
686 | ||
687 | /** | |
688 | * onenand_release_device - [GENERIC] release chip | |
689 | * @param mtd MTD device structure | |
690 | * | |
691 | * Deselect, release chip lock and wake up anyone waiting on the device | |
692 | */ | |
693 | static void onenand_release_device(struct mtd_info *mtd) | |
694 | { | |
695 | struct onenand_chip *this = mtd->priv; | |
696 | ||
697 | /* Release the chip */ | |
698 | spin_lock(&this->chip_lock); | |
699 | this->state = FL_READY; | |
700 | wake_up(&this->wq); | |
701 | spin_unlock(&this->chip_lock); | |
702 | } | |
703 | ||
704 | /** | |
9223a456 | 705 | * onenand_read - [MTD Interface] Read data from flash |
cd5f6346 KP |
706 | * @param mtd MTD device structure |
707 | * @param from offset to read from | |
708 | * @param len number of bytes to read | |
709 | * @param retlen pointer to variable to store the number of read bytes | |
710 | * @param buf the databuffer to put data | |
cd5f6346 | 711 | * |
9223a456 TG |
712 | * Read with ecc |
713 | */ | |
714 | static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
715 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
716 | { |
717 | struct onenand_chip *this = mtd->priv; | |
718 | int read = 0, column; | |
719 | int thislen; | |
720 | int ret = 0; | |
721 | ||
9223a456 | 722 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); |
cd5f6346 KP |
723 | |
724 | /* Do not allow reads past end of device */ | |
725 | if ((from + len) > mtd->size) { | |
9223a456 | 726 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read: Attempt read beyond end of device\n"); |
cd5f6346 KP |
727 | *retlen = 0; |
728 | return -EINVAL; | |
729 | } | |
730 | ||
731 | /* Grab the lock and see if the device is available */ | |
732 | onenand_get_device(mtd, FL_READING); | |
733 | ||
734 | /* TODO handling oob */ | |
735 | ||
736 | while (read < len) { | |
28318776 | 737 | thislen = min_t(int, mtd->writesize, len - read); |
cd5f6346 | 738 | |
28318776 JE |
739 | column = from & (mtd->writesize - 1); |
740 | if (column + thislen > mtd->writesize) | |
741 | thislen = mtd->writesize - column; | |
cd5f6346 KP |
742 | |
743 | if (!onenand_check_bufferram(mtd, from)) { | |
28318776 | 744 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); |
cd5f6346 KP |
745 | |
746 | ret = this->wait(mtd, FL_READING); | |
747 | /* First copy data and check return value for ECC handling */ | |
748 | onenand_update_bufferram(mtd, from, 1); | |
749 | } | |
750 | ||
751 | this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); | |
752 | ||
753 | read += thislen; | |
754 | ||
755 | if (read == len) | |
756 | break; | |
757 | ||
758 | if (ret) { | |
9223a456 | 759 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read: read failed = %d\n", ret); |
cd5f6346 KP |
760 | goto out; |
761 | } | |
762 | ||
763 | from += thislen; | |
764 | buf += thislen; | |
765 | } | |
766 | ||
767 | out: | |
768 | /* Deselect and wake up anyone waiting on the device */ | |
769 | onenand_release_device(mtd); | |
770 | ||
771 | /* | |
772 | * Return success, if no ECC failures, else -EBADMSG | |
773 | * fs driver will take care of that, because | |
774 | * retlen == desired len and result == -EBADMSG | |
775 | */ | |
776 | *retlen = read; | |
777 | return ret; | |
778 | } | |
779 | ||
cd5f6346 | 780 | /** |
8593fbc6 | 781 | * onenand_do_read_oob - [MTD Interface] OneNAND read out-of-band |
cd5f6346 KP |
782 | * @param mtd MTD device structure |
783 | * @param from offset to read from | |
784 | * @param len number of bytes to read | |
785 | * @param retlen pointer to variable to store the number of read bytes | |
786 | * @param buf the databuffer to put data | |
787 | * | |
788 | * OneNAND read out-of-band data from the spare area | |
789 | */ | |
8593fbc6 TG |
790 | int onenand_do_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
791 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
792 | { |
793 | struct onenand_chip *this = mtd->priv; | |
794 | int read = 0, thislen, column; | |
795 | int ret = 0; | |
796 | ||
797 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); | |
798 | ||
799 | /* Initialize return length value */ | |
800 | *retlen = 0; | |
801 | ||
802 | /* Do not allow reads past end of device */ | |
803 | if (unlikely((from + len) > mtd->size)) { | |
804 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | ||
808 | /* Grab the lock and see if the device is available */ | |
809 | onenand_get_device(mtd, FL_READING); | |
810 | ||
811 | column = from & (mtd->oobsize - 1); | |
812 | ||
813 | while (read < len) { | |
814 | thislen = mtd->oobsize - column; | |
815 | thislen = min_t(int, thislen, len); | |
816 | ||
817 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
818 | ||
819 | onenand_update_bufferram(mtd, from, 0); | |
820 | ||
821 | ret = this->wait(mtd, FL_READING); | |
822 | /* First copy data and check return value for ECC handling */ | |
823 | ||
824 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
825 | ||
826 | read += thislen; | |
827 | ||
828 | if (read == len) | |
829 | break; | |
830 | ||
831 | if (ret) { | |
832 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret); | |
833 | goto out; | |
834 | } | |
835 | ||
836 | buf += thislen; | |
837 | ||
838 | /* Read more? */ | |
839 | if (read < len) { | |
840 | /* Page size */ | |
28318776 | 841 | from += mtd->writesize; |
cd5f6346 KP |
842 | column = 0; |
843 | } | |
844 | } | |
845 | ||
846 | out: | |
847 | /* Deselect and wake up anyone waiting on the device */ | |
848 | onenand_release_device(mtd); | |
849 | ||
850 | *retlen = read; | |
851 | return ret; | |
852 | } | |
853 | ||
8593fbc6 TG |
854 | /** |
855 | * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band | |
856 | * @mtd: MTD device structure | |
857 | * @from: offset to read from | |
858 | * @ops: oob operation description structure | |
859 | */ | |
860 | static int onenand_read_oob(struct mtd_info *mtd, loff_t from, | |
861 | struct mtd_oob_ops *ops) | |
862 | { | |
863 | BUG_ON(ops->mode != MTD_OOB_PLACE); | |
864 | ||
865 | return onenand_do_read_oob(mtd, from + ops->ooboffs, ops->len, | |
866 | &ops->retlen, ops->oobbuf); | |
867 | } | |
868 | ||
cd5f6346 | 869 | #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE |
8e6ec690 KP |
870 | /** |
871 | * onenand_verify_oob - [GENERIC] verify the oob contents after a write | |
872 | * @param mtd MTD device structure | |
873 | * @param buf the databuffer to verify | |
874 | * @param to offset to read from | |
875 | * @param len number of bytes to read and compare | |
876 | * | |
877 | */ | |
878 | static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to, int len) | |
879 | { | |
880 | struct onenand_chip *this = mtd->priv; | |
881 | char *readp = this->page_buf; | |
882 | int column = to & (mtd->oobsize - 1); | |
883 | int status, i; | |
884 | ||
885 | this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); | |
886 | onenand_update_bufferram(mtd, to, 0); | |
887 | status = this->wait(mtd, FL_READING); | |
888 | if (status) | |
889 | return status; | |
890 | ||
891 | this->read_bufferram(mtd, ONENAND_SPARERAM, readp, column, len); | |
892 | ||
893 | for(i = 0; i < len; i++) | |
894 | if (buf[i] != 0xFF && buf[i] != readp[i]) | |
895 | return -EBADMSG; | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
cd5f6346 KP |
900 | /** |
901 | * onenand_verify_page - [GENERIC] verify the chip contents after a write | |
902 | * @param mtd MTD device structure | |
903 | * @param buf the databuffer to verify | |
cd5f6346 KP |
904 | * |
905 | * Check DataRAM area directly | |
906 | */ | |
d36d63d4 | 907 | static int onenand_verify_page(struct mtd_info *mtd, u_char *buf, loff_t addr) |
cd5f6346 KP |
908 | { |
909 | struct onenand_chip *this = mtd->priv; | |
910 | void __iomem *dataram0, *dataram1; | |
911 | int ret = 0; | |
912 | ||
28318776 | 913 | this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); |
cd5f6346 KP |
914 | |
915 | ret = this->wait(mtd, FL_READING); | |
916 | if (ret) | |
917 | return ret; | |
918 | ||
919 | onenand_update_bufferram(mtd, addr, 1); | |
920 | ||
921 | /* Check, if the two dataram areas are same */ | |
922 | dataram0 = this->base + ONENAND_DATARAM; | |
28318776 | 923 | dataram1 = dataram0 + mtd->writesize; |
cd5f6346 | 924 | |
28318776 | 925 | if (memcmp(dataram0, dataram1, mtd->writesize)) |
cd5f6346 | 926 | return -EBADMSG; |
d5c5e78a | 927 | |
cd5f6346 KP |
928 | return 0; |
929 | } | |
930 | #else | |
931 | #define onenand_verify_page(...) (0) | |
8e6ec690 | 932 | #define onenand_verify_oob(...) (0) |
cd5f6346 KP |
933 | #endif |
934 | ||
28318776 | 935 | #define NOTALIGNED(x) ((x & (mtd->writesize - 1)) != 0) |
cd5f6346 KP |
936 | |
937 | /** | |
9223a456 | 938 | * onenand_write - [MTD Interface] write buffer to FLASH |
cd5f6346 KP |
939 | * @param mtd MTD device structure |
940 | * @param to offset to write to | |
941 | * @param len number of bytes to write | |
942 | * @param retlen pointer to variable to store the number of written bytes | |
943 | * @param buf the data to write | |
cd5f6346 | 944 | * |
9223a456 | 945 | * Write with ECC |
cd5f6346 | 946 | */ |
9223a456 TG |
947 | static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, |
948 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
949 | { |
950 | struct onenand_chip *this = mtd->priv; | |
951 | int written = 0; | |
952 | int ret = 0; | |
953 | ||
9223a456 | 954 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); |
cd5f6346 KP |
955 | |
956 | /* Initialize retlen, in case of early exit */ | |
957 | *retlen = 0; | |
958 | ||
959 | /* Do not allow writes past end of device */ | |
960 | if (unlikely((to + len) > mtd->size)) { | |
9223a456 | 961 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt write to past end of device\n"); |
cd5f6346 KP |
962 | return -EINVAL; |
963 | } | |
964 | ||
965 | /* Reject writes, which are not page aligned */ | |
966 | if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { | |
9223a456 | 967 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: Attempt to write not page aligned data\n"); |
cd5f6346 KP |
968 | return -EINVAL; |
969 | } | |
970 | ||
971 | /* Grab the lock and see if the device is available */ | |
972 | onenand_get_device(mtd, FL_WRITING); | |
973 | ||
974 | /* Loop until all data write */ | |
975 | while (written < len) { | |
28318776 | 976 | int thislen = min_t(int, mtd->writesize, len - written); |
cd5f6346 | 977 | |
28318776 | 978 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->writesize); |
cd5f6346 KP |
979 | |
980 | this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen); | |
981 | this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); | |
982 | ||
28318776 | 983 | this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); |
cd5f6346 KP |
984 | |
985 | onenand_update_bufferram(mtd, to, 1); | |
986 | ||
987 | ret = this->wait(mtd, FL_WRITING); | |
988 | if (ret) { | |
9223a456 | 989 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: write filaed %d\n", ret); |
cd5f6346 KP |
990 | goto out; |
991 | } | |
992 | ||
993 | written += thislen; | |
994 | ||
995 | /* Only check verify write turn on */ | |
d36d63d4 | 996 | ret = onenand_verify_page(mtd, (u_char *) buf, to); |
cd5f6346 | 997 | if (ret) { |
9223a456 | 998 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write: verify failed %d\n", ret); |
cd5f6346 KP |
999 | goto out; |
1000 | } | |
1001 | ||
1002 | if (written == len) | |
1003 | break; | |
1004 | ||
1005 | to += thislen; | |
1006 | buf += thislen; | |
1007 | } | |
1008 | ||
1009 | out: | |
1010 | /* Deselect and wake up anyone waiting on the device */ | |
1011 | onenand_release_device(mtd); | |
1012 | ||
1013 | *retlen = written; | |
d5c5e78a | 1014 | |
cd5f6346 KP |
1015 | return ret; |
1016 | } | |
1017 | ||
cd5f6346 | 1018 | /** |
8593fbc6 | 1019 | * onenand_do_write_oob - [Internal] OneNAND write out-of-band |
cd5f6346 KP |
1020 | * @param mtd MTD device structure |
1021 | * @param to offset to write to | |
1022 | * @param len number of bytes to write | |
1023 | * @param retlen pointer to variable to store the number of written bytes | |
1024 | * @param buf the data to write | |
1025 | * | |
1026 | * OneNAND write out-of-band | |
1027 | */ | |
8593fbc6 TG |
1028 | static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
1029 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
1030 | { |
1031 | struct onenand_chip *this = mtd->priv; | |
8e6ec690 | 1032 | int column, ret = 0; |
cd5f6346 KP |
1033 | int written = 0; |
1034 | ||
1035 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); | |
1036 | ||
1037 | /* Initialize retlen, in case of early exit */ | |
1038 | *retlen = 0; | |
1039 | ||
1040 | /* Do not allow writes past end of device */ | |
1041 | if (unlikely((to + len) > mtd->size)) { | |
1042 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n"); | |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | /* Grab the lock and see if the device is available */ | |
1047 | onenand_get_device(mtd, FL_WRITING); | |
1048 | ||
1049 | /* Loop until all data write */ | |
1050 | while (written < len) { | |
1051 | int thislen = min_t(int, mtd->oobsize, len - written); | |
1052 | ||
1053 | column = to & (mtd->oobsize - 1); | |
1054 | ||
1055 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); | |
1056 | ||
34c10609 KP |
1057 | /* We send data to spare ram with oobsize |
1058 | * to prevent byte access */ | |
1059 | memset(this->page_buf, 0xff, mtd->oobsize); | |
1060 | memcpy(this->page_buf + column, buf, thislen); | |
1061 | this->write_bufferram(mtd, ONENAND_SPARERAM, this->page_buf, 0, mtd->oobsize); | |
cd5f6346 KP |
1062 | |
1063 | this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); | |
1064 | ||
1065 | onenand_update_bufferram(mtd, to, 0); | |
1066 | ||
8e6ec690 KP |
1067 | ret = this->wait(mtd, FL_WRITING); |
1068 | if (ret) { | |
1069 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: write filaed %d\n", ret); | |
1070 | goto out; | |
1071 | } | |
1072 | ||
1073 | ret = onenand_verify_oob(mtd, buf, to, thislen); | |
1074 | if (ret) { | |
1075 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: verify failed %d\n", ret); | |
cd5f6346 | 1076 | goto out; |
8e6ec690 | 1077 | } |
cd5f6346 KP |
1078 | |
1079 | written += thislen; | |
1080 | ||
1081 | if (written == len) | |
1082 | break; | |
1083 | ||
1084 | to += thislen; | |
1085 | buf += thislen; | |
1086 | } | |
1087 | ||
1088 | out: | |
1089 | /* Deselect and wake up anyone waiting on the device */ | |
1090 | onenand_release_device(mtd); | |
1091 | ||
1092 | *retlen = written; | |
d5c5e78a | 1093 | |
8e6ec690 | 1094 | return ret; |
cd5f6346 KP |
1095 | } |
1096 | ||
8593fbc6 TG |
1097 | /** |
1098 | * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1099 | * @mtd: MTD device structure | |
1100 | * @from: offset to read from | |
1101 | * @ops: oob operation description structure | |
1102 | */ | |
1103 | static int onenand_write_oob(struct mtd_info *mtd, loff_t to, | |
1104 | struct mtd_oob_ops *ops) | |
1105 | { | |
1106 | BUG_ON(ops->mode != MTD_OOB_PLACE); | |
1107 | ||
1108 | return onenand_do_write_oob(mtd, to + ops->ooboffs, ops->len, | |
1109 | &ops->retlen, ops->oobbuf); | |
1110 | } | |
1111 | ||
cdc00130 KP |
1112 | /** |
1113 | * onenand_block_checkbad - [GENERIC] Check if a block is marked bad | |
1114 | * @param mtd MTD device structure | |
1115 | * @param ofs offset from device start | |
1116 | * @param getchip 0, if the chip is already selected | |
1117 | * @param allowbbt 1, if its allowed to access the bbt area | |
1118 | * | |
1119 | * Check, if the block is bad. Either by reading the bad block table or | |
1120 | * calling of the scan function. | |
1121 | */ | |
1122 | static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) | |
1123 | { | |
1124 | struct onenand_chip *this = mtd->priv; | |
1125 | struct bbm_info *bbm = this->bbm; | |
1126 | ||
1127 | /* Return info from the table */ | |
1128 | return bbm->isbad_bbt(mtd, ofs, allowbbt); | |
1129 | } | |
1130 | ||
cd5f6346 KP |
1131 | /** |
1132 | * onenand_erase - [MTD Interface] erase block(s) | |
1133 | * @param mtd MTD device structure | |
1134 | * @param instr erase instruction | |
1135 | * | |
1136 | * Erase one ore more blocks | |
1137 | */ | |
1138 | static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) | |
1139 | { | |
1140 | struct onenand_chip *this = mtd->priv; | |
1141 | unsigned int block_size; | |
1142 | loff_t addr; | |
1143 | int len; | |
1144 | int ret = 0; | |
1145 | ||
1146 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); | |
1147 | ||
1148 | block_size = (1 << this->erase_shift); | |
1149 | ||
1150 | /* Start address must align on block boundary */ | |
1151 | if (unlikely(instr->addr & (block_size - 1))) { | |
1152 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); | |
1153 | return -EINVAL; | |
1154 | } | |
1155 | ||
1156 | /* Length must align on block boundary */ | |
1157 | if (unlikely(instr->len & (block_size - 1))) { | |
1158 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n"); | |
1159 | return -EINVAL; | |
1160 | } | |
1161 | ||
1162 | /* Do not allow erase past end of device */ | |
1163 | if (unlikely((instr->len + instr->addr) > mtd->size)) { | |
1164 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n"); | |
1165 | return -EINVAL; | |
1166 | } | |
1167 | ||
1168 | instr->fail_addr = 0xffffffff; | |
1169 | ||
1170 | /* Grab the lock and see if the device is available */ | |
1171 | onenand_get_device(mtd, FL_ERASING); | |
1172 | ||
1173 | /* Loop throught the pages */ | |
1174 | len = instr->len; | |
1175 | addr = instr->addr; | |
1176 | ||
1177 | instr->state = MTD_ERASING; | |
1178 | ||
1179 | while (len) { | |
1180 | ||
cdc00130 KP |
1181 | /* Check if we have a bad block, we do not erase bad blocks */ |
1182 | if (onenand_block_checkbad(mtd, addr, 0, 0)) { | |
1183 | printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); | |
1184 | instr->state = MTD_ERASE_FAILED; | |
1185 | goto erase_exit; | |
1186 | } | |
cd5f6346 KP |
1187 | |
1188 | this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); | |
1189 | ||
1190 | ret = this->wait(mtd, FL_ERASING); | |
1191 | /* Check, if it is write protected */ | |
1192 | if (ret) { | |
1193 | if (ret == -EPERM) | |
1194 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n"); | |
1195 | else | |
1196 | DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); | |
1197 | instr->state = MTD_ERASE_FAILED; | |
1198 | instr->fail_addr = addr; | |
1199 | goto erase_exit; | |
1200 | } | |
1201 | ||
1202 | len -= block_size; | |
1203 | addr += block_size; | |
1204 | } | |
1205 | ||
1206 | instr->state = MTD_ERASE_DONE; | |
1207 | ||
1208 | erase_exit: | |
1209 | ||
1210 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1211 | /* Do call back function */ | |
1212 | if (!ret) | |
1213 | mtd_erase_callback(instr); | |
1214 | ||
1215 | /* Deselect and wake up anyone waiting on the device */ | |
1216 | onenand_release_device(mtd); | |
1217 | ||
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * onenand_sync - [MTD Interface] sync | |
1223 | * @param mtd MTD device structure | |
1224 | * | |
1225 | * Sync is actually a wait for chip ready function | |
1226 | */ | |
1227 | static void onenand_sync(struct mtd_info *mtd) | |
1228 | { | |
1229 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); | |
1230 | ||
1231 | /* Grab the lock and see if the device is available */ | |
1232 | onenand_get_device(mtd, FL_SYNCING); | |
1233 | ||
1234 | /* Release it and go back */ | |
1235 | onenand_release_device(mtd); | |
1236 | } | |
1237 | ||
1238 | /** | |
1239 | * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad | |
1240 | * @param mtd MTD device structure | |
1241 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1242 | * |
1243 | * Check whether the block is bad | |
cd5f6346 KP |
1244 | */ |
1245 | static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) | |
1246 | { | |
cdc00130 KP |
1247 | /* Check for invalid offset */ |
1248 | if (ofs > mtd->size) | |
1249 | return -EINVAL; | |
1250 | ||
1251 | return onenand_block_checkbad(mtd, ofs, 1, 0); | |
1252 | } | |
1253 | ||
1254 | /** | |
1255 | * onenand_default_block_markbad - [DEFAULT] mark a block bad | |
1256 | * @param mtd MTD device structure | |
1257 | * @param ofs offset from device start | |
1258 | * | |
1259 | * This is the default implementation, which can be overridden by | |
1260 | * a hardware specific driver. | |
1261 | */ | |
1262 | static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1263 | { | |
1264 | struct onenand_chip *this = mtd->priv; | |
1265 | struct bbm_info *bbm = this->bbm; | |
1266 | u_char buf[2] = {0, 0}; | |
1267 | size_t retlen; | |
1268 | int block; | |
1269 | ||
1270 | /* Get block number */ | |
1271 | block = ((int) ofs) >> bbm->bbt_erase_shift; | |
1272 | if (bbm->bbt) | |
1273 | bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1274 | ||
1275 | /* We write two bytes, so we dont have to mess with 16 bit access */ | |
1276 | ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); | |
8593fbc6 | 1277 | return onenand_do_write_oob(mtd, ofs , 2, &retlen, buf); |
cd5f6346 KP |
1278 | } |
1279 | ||
1280 | /** | |
1281 | * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad | |
1282 | * @param mtd MTD device structure | |
1283 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1284 | * |
1285 | * Mark the block as bad | |
cd5f6346 KP |
1286 | */ |
1287 | static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1288 | { | |
cdc00130 KP |
1289 | struct onenand_chip *this = mtd->priv; |
1290 | int ret; | |
1291 | ||
1292 | ret = onenand_block_isbad(mtd, ofs); | |
1293 | if (ret) { | |
1294 | /* If it was bad already, return success and do nothing */ | |
1295 | if (ret > 0) | |
1296 | return 0; | |
1297 | return ret; | |
1298 | } | |
1299 | ||
1300 | return this->block_markbad(mtd, ofs); | |
cd5f6346 KP |
1301 | } |
1302 | ||
1303 | /** | |
1304 | * onenand_unlock - [MTD Interface] Unlock block(s) | |
1305 | * @param mtd MTD device structure | |
1306 | * @param ofs offset relative to mtd start | |
1307 | * @param len number of bytes to unlock | |
1308 | * | |
1309 | * Unlock one or more blocks | |
1310 | */ | |
1311 | static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1312 | { | |
1313 | struct onenand_chip *this = mtd->priv; | |
1314 | int start, end, block, value, status; | |
1315 | ||
1316 | start = ofs >> this->erase_shift; | |
1317 | end = len >> this->erase_shift; | |
1318 | ||
1319 | /* Continuous lock scheme */ | |
28b79ff9 | 1320 | if (this->options & ONENAND_HAS_CONT_LOCK) { |
cd5f6346 KP |
1321 | /* Set start block address */ |
1322 | this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1323 | /* Set end block address */ | |
28b79ff9 | 1324 | this->write_word(start + end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); |
cd5f6346 KP |
1325 | /* Write unlock command */ |
1326 | this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); | |
1327 | ||
1328 | /* There's no return value */ | |
1329 | this->wait(mtd, FL_UNLOCKING); | |
1330 | ||
1331 | /* Sanity check */ | |
1332 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1333 | & ONENAND_CTRL_ONGO) | |
1334 | continue; | |
1335 | ||
1336 | /* Check lock status */ | |
1337 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1338 | if (!(status & ONENAND_WP_US)) | |
1339 | printk(KERN_ERR "wp status = 0x%x\n", status); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | /* Block lock scheme */ | |
28b79ff9 | 1345 | for (block = start; block < start + end; block++) { |
20ba89a3 KP |
1346 | /* Set block address */ |
1347 | value = onenand_block_address(this, block); | |
1348 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1349 | /* Select DataRAM for DDP */ | |
1350 | value = onenand_bufferram_address(this, block); | |
1351 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
cd5f6346 KP |
1352 | /* Set start block address */ |
1353 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1354 | /* Write unlock command */ | |
1355 | this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); | |
1356 | ||
1357 | /* There's no return value */ | |
1358 | this->wait(mtd, FL_UNLOCKING); | |
1359 | ||
1360 | /* Sanity check */ | |
1361 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1362 | & ONENAND_CTRL_ONGO) | |
1363 | continue; | |
1364 | ||
cd5f6346 KP |
1365 | /* Check lock status */ |
1366 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1367 | if (!(status & ONENAND_WP_US)) | |
1368 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1369 | } | |
d5c5e78a | 1370 | |
cd5f6346 KP |
1371 | return 0; |
1372 | } | |
1373 | ||
28b79ff9 KP |
1374 | /** |
1375 | * onenand_check_lock_status - [OneNAND Interface] Check lock status | |
1376 | * @param this onenand chip data structure | |
1377 | * | |
1378 | * Check lock status | |
1379 | */ | |
1380 | static void onenand_check_lock_status(struct onenand_chip *this) | |
1381 | { | |
1382 | unsigned int value, block, status; | |
1383 | unsigned int end; | |
1384 | ||
1385 | end = this->chipsize >> this->erase_shift; | |
1386 | for (block = 0; block < end; block++) { | |
1387 | /* Set block address */ | |
1388 | value = onenand_block_address(this, block); | |
1389 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1390 | /* Select DataRAM for DDP */ | |
1391 | value = onenand_bufferram_address(this, block); | |
1392 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
1393 | /* Set start block address */ | |
1394 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1395 | ||
1396 | /* Check lock status */ | |
1397 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1398 | if (!(status & ONENAND_WP_US)) | |
1399 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1400 | } | |
1401 | } | |
1402 | ||
1403 | /** | |
1404 | * onenand_unlock_all - [OneNAND Interface] unlock all blocks | |
1405 | * @param mtd MTD device structure | |
1406 | * | |
1407 | * Unlock all blocks | |
1408 | */ | |
1409 | static int onenand_unlock_all(struct mtd_info *mtd) | |
1410 | { | |
1411 | struct onenand_chip *this = mtd->priv; | |
1412 | ||
1413 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
1414 | /* Write unlock command */ | |
1415 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
1416 | ||
1417 | /* There's no return value */ | |
1418 | this->wait(mtd, FL_UNLOCKING); | |
1419 | ||
1420 | /* Sanity check */ | |
1421 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1422 | & ONENAND_CTRL_ONGO) | |
1423 | continue; | |
1424 | ||
1425 | /* Workaround for all block unlock in DDP */ | |
1426 | if (this->device_id & ONENAND_DEVICE_IS_DDP) { | |
1427 | loff_t ofs; | |
1428 | size_t len; | |
1429 | ||
1430 | /* 1st block on another chip */ | |
1431 | ofs = this->chipsize >> 1; | |
1432 | len = 1 << this->erase_shift; | |
1433 | ||
1434 | onenand_unlock(mtd, ofs, len); | |
1435 | } | |
1436 | ||
1437 | onenand_check_lock_status(this); | |
1438 | ||
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | mtd->unlock(mtd, 0x0, this->chipsize); | |
1443 | ||
1444 | return 0; | |
1445 | } | |
1446 | ||
493c6460 KP |
1447 | #ifdef CONFIG_MTD_ONENAND_OTP |
1448 | ||
1449 | /* Interal OTP operation */ | |
1450 | typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, | |
1451 | size_t *retlen, u_char *buf); | |
1452 | ||
1453 | /** | |
1454 | * do_otp_read - [DEFAULT] Read OTP block area | |
1455 | * @param mtd MTD device structure | |
1456 | * @param from The offset to read | |
1457 | * @param len number of bytes to read | |
1458 | * @param retlen pointer to variable to store the number of readbytes | |
1459 | * @param buf the databuffer to put/get data | |
1460 | * | |
1461 | * Read OTP block area. | |
1462 | */ | |
1463 | static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1464 | size_t *retlen, u_char *buf) | |
1465 | { | |
1466 | struct onenand_chip *this = mtd->priv; | |
1467 | int ret; | |
1468 | ||
1469 | /* Enter OTP access mode */ | |
1470 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1471 | this->wait(mtd, FL_OTPING); | |
1472 | ||
1473 | ret = mtd->read(mtd, from, len, retlen, buf); | |
1474 | ||
1475 | /* Exit OTP access mode */ | |
1476 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1477 | this->wait(mtd, FL_RESETING); | |
1478 | ||
1479 | return ret; | |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * do_otp_write - [DEFAULT] Write OTP block area | |
1484 | * @param mtd MTD device structure | |
1485 | * @param from The offset to write | |
1486 | * @param len number of bytes to write | |
1487 | * @param retlen pointer to variable to store the number of write bytes | |
1488 | * @param buf the databuffer to put/get data | |
1489 | * | |
1490 | * Write OTP block area. | |
1491 | */ | |
1492 | static int do_otp_write(struct mtd_info *mtd, loff_t from, size_t len, | |
1493 | size_t *retlen, u_char *buf) | |
1494 | { | |
1495 | struct onenand_chip *this = mtd->priv; | |
1496 | unsigned char *pbuf = buf; | |
1497 | int ret; | |
1498 | ||
1499 | /* Force buffer page aligned */ | |
28318776 | 1500 | if (len < mtd->writesize) { |
493c6460 | 1501 | memcpy(this->page_buf, buf, len); |
28318776 | 1502 | memset(this->page_buf + len, 0xff, mtd->writesize - len); |
493c6460 | 1503 | pbuf = this->page_buf; |
28318776 | 1504 | len = mtd->writesize; |
493c6460 KP |
1505 | } |
1506 | ||
1507 | /* Enter OTP access mode */ | |
1508 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1509 | this->wait(mtd, FL_OTPING); | |
1510 | ||
1511 | ret = mtd->write(mtd, from, len, retlen, pbuf); | |
1512 | ||
1513 | /* Exit OTP access mode */ | |
1514 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1515 | this->wait(mtd, FL_RESETING); | |
1516 | ||
1517 | return ret; | |
1518 | } | |
1519 | ||
1520 | /** | |
1521 | * do_otp_lock - [DEFAULT] Lock OTP block area | |
1522 | * @param mtd MTD device structure | |
1523 | * @param from The offset to lock | |
1524 | * @param len number of bytes to lock | |
1525 | * @param retlen pointer to variable to store the number of lock bytes | |
1526 | * @param buf the databuffer to put/get data | |
1527 | * | |
1528 | * Lock OTP block area. | |
1529 | */ | |
1530 | static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, | |
1531 | size_t *retlen, u_char *buf) | |
1532 | { | |
1533 | struct onenand_chip *this = mtd->priv; | |
1534 | int ret; | |
1535 | ||
1536 | /* Enter OTP access mode */ | |
1537 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1538 | this->wait(mtd, FL_OTPING); | |
1539 | ||
8593fbc6 | 1540 | ret = onenand_do_write_oob(mtd, from, len, retlen, buf); |
493c6460 KP |
1541 | |
1542 | /* Exit OTP access mode */ | |
1543 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1544 | this->wait(mtd, FL_RESETING); | |
1545 | ||
1546 | return ret; | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * onenand_otp_walk - [DEFAULT] Handle OTP operation | |
1551 | * @param mtd MTD device structure | |
1552 | * @param from The offset to read/write | |
1553 | * @param len number of bytes to read/write | |
1554 | * @param retlen pointer to variable to store the number of read bytes | |
1555 | * @param buf the databuffer to put/get data | |
1556 | * @param action do given action | |
1557 | * @param mode specify user and factory | |
1558 | * | |
1559 | * Handle OTP operation. | |
1560 | */ | |
1561 | static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, | |
1562 | size_t *retlen, u_char *buf, | |
1563 | otp_op_t action, int mode) | |
1564 | { | |
1565 | struct onenand_chip *this = mtd->priv; | |
1566 | int otp_pages; | |
1567 | int density; | |
1568 | int ret = 0; | |
1569 | ||
1570 | *retlen = 0; | |
1571 | ||
1572 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1573 | if (density < ONENAND_DEVICE_DENSITY_512Mb) | |
1574 | otp_pages = 20; | |
1575 | else | |
1576 | otp_pages = 10; | |
1577 | ||
1578 | if (mode == MTD_OTP_FACTORY) { | |
28318776 | 1579 | from += mtd->writesize * otp_pages; |
493c6460 KP |
1580 | otp_pages = 64 - otp_pages; |
1581 | } | |
1582 | ||
1583 | /* Check User/Factory boundary */ | |
28318776 | 1584 | if (((mtd->writesize * otp_pages) - (from + len)) < 0) |
493c6460 KP |
1585 | return 0; |
1586 | ||
1587 | while (len > 0 && otp_pages > 0) { | |
1588 | if (!action) { /* OTP Info functions */ | |
1589 | struct otp_info *otpinfo; | |
1590 | ||
1591 | len -= sizeof(struct otp_info); | |
1592 | if (len <= 0) | |
1593 | return -ENOSPC; | |
1594 | ||
1595 | otpinfo = (struct otp_info *) buf; | |
1596 | otpinfo->start = from; | |
28318776 | 1597 | otpinfo->length = mtd->writesize; |
493c6460 KP |
1598 | otpinfo->locked = 0; |
1599 | ||
28318776 | 1600 | from += mtd->writesize; |
493c6460 KP |
1601 | buf += sizeof(struct otp_info); |
1602 | *retlen += sizeof(struct otp_info); | |
1603 | } else { | |
1604 | size_t tmp_retlen; | |
1605 | int size = len; | |
1606 | ||
1607 | ret = action(mtd, from, len, &tmp_retlen, buf); | |
1608 | ||
1609 | buf += size; | |
1610 | len -= size; | |
1611 | *retlen += size; | |
1612 | ||
1613 | if (ret < 0) | |
1614 | return ret; | |
1615 | } | |
1616 | otp_pages--; | |
1617 | } | |
1618 | ||
1619 | return 0; | |
1620 | } | |
1621 | ||
1622 | /** | |
1623 | * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info | |
1624 | * @param mtd MTD device structure | |
1625 | * @param buf the databuffer to put/get data | |
1626 | * @param len number of bytes to read | |
1627 | * | |
1628 | * Read factory OTP info. | |
1629 | */ | |
1630 | static int onenand_get_fact_prot_info(struct mtd_info *mtd, | |
1631 | struct otp_info *buf, size_t len) | |
1632 | { | |
1633 | size_t retlen; | |
1634 | int ret; | |
1635 | ||
1636 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY); | |
1637 | ||
1638 | return ret ? : retlen; | |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area | |
1643 | * @param mtd MTD device structure | |
1644 | * @param from The offset to read | |
1645 | * @param len number of bytes to read | |
1646 | * @param retlen pointer to variable to store the number of read bytes | |
1647 | * @param buf the databuffer to put/get data | |
1648 | * | |
1649 | * Read factory OTP area. | |
1650 | */ | |
1651 | static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | |
1652 | size_t len, size_t *retlen, u_char *buf) | |
1653 | { | |
1654 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY); | |
1655 | } | |
1656 | ||
1657 | /** | |
1658 | * onenand_get_user_prot_info - [MTD Interface] Read user OTP info | |
1659 | * @param mtd MTD device structure | |
1660 | * @param buf the databuffer to put/get data | |
1661 | * @param len number of bytes to read | |
1662 | * | |
1663 | * Read user OTP info. | |
1664 | */ | |
1665 | static int onenand_get_user_prot_info(struct mtd_info *mtd, | |
1666 | struct otp_info *buf, size_t len) | |
1667 | { | |
1668 | size_t retlen; | |
1669 | int ret; | |
1670 | ||
1671 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER); | |
1672 | ||
1673 | return ret ? : retlen; | |
1674 | } | |
1675 | ||
1676 | /** | |
1677 | * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area | |
1678 | * @param mtd MTD device structure | |
1679 | * @param from The offset to read | |
1680 | * @param len number of bytes to read | |
1681 | * @param retlen pointer to variable to store the number of read bytes | |
1682 | * @param buf the databuffer to put/get data | |
1683 | * | |
1684 | * Read user OTP area. | |
1685 | */ | |
1686 | static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1687 | size_t len, size_t *retlen, u_char *buf) | |
1688 | { | |
1689 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER); | |
1690 | } | |
1691 | ||
1692 | /** | |
1693 | * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area | |
1694 | * @param mtd MTD device structure | |
1695 | * @param from The offset to write | |
1696 | * @param len number of bytes to write | |
1697 | * @param retlen pointer to variable to store the number of write bytes | |
1698 | * @param buf the databuffer to put/get data | |
1699 | * | |
1700 | * Write user OTP area. | |
1701 | */ | |
1702 | static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1703 | size_t len, size_t *retlen, u_char *buf) | |
1704 | { | |
1705 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER); | |
1706 | } | |
1707 | ||
1708 | /** | |
1709 | * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area | |
1710 | * @param mtd MTD device structure | |
1711 | * @param from The offset to lock | |
1712 | * @param len number of bytes to unlock | |
1713 | * | |
1714 | * Write lock mark on spare area in page 0 in OTP block | |
1715 | */ | |
1716 | static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
1717 | size_t len) | |
1718 | { | |
1719 | unsigned char oob_buf[64]; | |
1720 | size_t retlen; | |
1721 | int ret; | |
1722 | ||
1723 | memset(oob_buf, 0xff, mtd->oobsize); | |
1724 | /* | |
1725 | * Note: OTP lock operation | |
1726 | * OTP block : 0xXXFC | |
1727 | * 1st block : 0xXXF3 (If chip support) | |
1728 | * Both : 0xXXF0 (If chip support) | |
1729 | */ | |
1730 | oob_buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC; | |
1731 | ||
1732 | /* | |
1733 | * Write lock mark to 8th word of sector0 of page0 of the spare0. | |
1734 | * We write 16 bytes spare area instead of 2 bytes. | |
1735 | */ | |
1736 | from = 0; | |
1737 | len = 16; | |
1738 | ||
1739 | ret = onenand_otp_walk(mtd, from, len, &retlen, oob_buf, do_otp_lock, MTD_OTP_USER); | |
1740 | ||
1741 | return ret ? : retlen; | |
1742 | } | |
1743 | #endif /* CONFIG_MTD_ONENAND_OTP */ | |
1744 | ||
28b79ff9 KP |
1745 | /** |
1746 | * onenand_lock_scheme - Check and set OneNAND lock scheme | |
1747 | * @param mtd MTD data structure | |
1748 | * | |
1749 | * Check and set OneNAND lock scheme | |
1750 | */ | |
1751 | static void onenand_lock_scheme(struct mtd_info *mtd) | |
1752 | { | |
1753 | struct onenand_chip *this = mtd->priv; | |
1754 | unsigned int density, process; | |
1755 | ||
1756 | /* Lock scheme depends on density and process */ | |
1757 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1758 | process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; | |
1759 | ||
1760 | /* Lock scheme */ | |
1761 | if (density >= ONENAND_DEVICE_DENSITY_1Gb) { | |
1762 | /* A-Die has all block unlock */ | |
1763 | if (process) { | |
1764 | printk(KERN_DEBUG "Chip support all block unlock\n"); | |
1765 | this->options |= ONENAND_HAS_UNLOCK_ALL; | |
1766 | } | |
1767 | } else { | |
1768 | /* Some OneNAND has continues lock scheme */ | |
1769 | if (!process) { | |
1770 | printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); | |
1771 | this->options |= ONENAND_HAS_CONT_LOCK; | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | ||
cd5f6346 KP |
1776 | /** |
1777 | * onenand_print_device_info - Print device ID | |
1778 | * @param device device ID | |
1779 | * | |
1780 | * Print device ID | |
1781 | */ | |
28b79ff9 | 1782 | static void onenand_print_device_info(int device, int version) |
cd5f6346 KP |
1783 | { |
1784 | int vcc, demuxed, ddp, density; | |
1785 | ||
1786 | vcc = device & ONENAND_DEVICE_VCC_MASK; | |
1787 | demuxed = device & ONENAND_DEVICE_IS_DEMUX; | |
1788 | ddp = device & ONENAND_DEVICE_IS_DDP; | |
1789 | density = device >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1790 | printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", | |
1791 | demuxed ? "" : "Muxed ", | |
1792 | ddp ? "(DDP)" : "", | |
1793 | (16 << density), | |
1794 | vcc ? "2.65/3.3" : "1.8", | |
1795 | device); | |
28b79ff9 | 1796 | printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); |
cd5f6346 KP |
1797 | } |
1798 | ||
1799 | static const struct onenand_manufacturers onenand_manuf_ids[] = { | |
1800 | {ONENAND_MFR_SAMSUNG, "Samsung"}, | |
cd5f6346 KP |
1801 | }; |
1802 | ||
1803 | /** | |
1804 | * onenand_check_maf - Check manufacturer ID | |
1805 | * @param manuf manufacturer ID | |
1806 | * | |
1807 | * Check manufacturer ID | |
1808 | */ | |
1809 | static int onenand_check_maf(int manuf) | |
1810 | { | |
37b1cc39 KP |
1811 | int size = ARRAY_SIZE(onenand_manuf_ids); |
1812 | char *name; | |
cd5f6346 KP |
1813 | int i; |
1814 | ||
37b1cc39 | 1815 | for (i = 0; i < size; i++) |
cd5f6346 KP |
1816 | if (manuf == onenand_manuf_ids[i].id) |
1817 | break; | |
cd5f6346 | 1818 | |
37b1cc39 KP |
1819 | if (i < size) |
1820 | name = onenand_manuf_ids[i].name; | |
1821 | else | |
1822 | name = "Unknown"; | |
1823 | ||
1824 | printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); | |
cd5f6346 | 1825 | |
37b1cc39 | 1826 | return (i == size); |
cd5f6346 KP |
1827 | } |
1828 | ||
1829 | /** | |
1830 | * onenand_probe - [OneNAND Interface] Probe the OneNAND device | |
1831 | * @param mtd MTD device structure | |
1832 | * | |
1833 | * OneNAND detection method: | |
1834 | * Compare the the values from command with ones from register | |
1835 | */ | |
1836 | static int onenand_probe(struct mtd_info *mtd) | |
1837 | { | |
1838 | struct onenand_chip *this = mtd->priv; | |
28b79ff9 | 1839 | int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; |
cd5f6346 | 1840 | int density; |
47e777e0 KP |
1841 | int syscfg; |
1842 | ||
1843 | /* Save system configuration 1 */ | |
1844 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
1845 | /* Clear Sync. Burst Read mode to read BootRAM */ | |
1846 | this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); | |
cd5f6346 KP |
1847 | |
1848 | /* Send the command for reading device ID from BootRAM */ | |
1849 | this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); | |
1850 | ||
1851 | /* Read manufacturer and device IDs from BootRAM */ | |
1852 | bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); | |
1853 | bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); | |
1854 | ||
47e777e0 KP |
1855 | /* Reset OneNAND to read default register values */ |
1856 | this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); | |
1857 | /* Wait reset */ | |
1858 | this->wait(mtd, FL_RESETING); | |
1859 | ||
1860 | /* Restore system configuration 1 */ | |
1861 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
1862 | ||
cd5f6346 KP |
1863 | /* Check manufacturer ID */ |
1864 | if (onenand_check_maf(bram_maf_id)) | |
1865 | return -ENXIO; | |
1866 | ||
cd5f6346 KP |
1867 | /* Read manufacturer and device IDs from Register */ |
1868 | maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); | |
1869 | dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); | |
28b79ff9 | 1870 | ver_id= this->read_word(this->base + ONENAND_REG_VERSION_ID); |
cd5f6346 KP |
1871 | |
1872 | /* Check OneNAND device */ | |
1873 | if (maf_id != bram_maf_id || dev_id != bram_dev_id) | |
1874 | return -ENXIO; | |
1875 | ||
1876 | /* Flash device information */ | |
28b79ff9 | 1877 | onenand_print_device_info(dev_id, ver_id); |
cd5f6346 | 1878 | this->device_id = dev_id; |
28b79ff9 | 1879 | this->version_id = ver_id; |
cd5f6346 KP |
1880 | |
1881 | density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1882 | this->chipsize = (16 << density) << 20; | |
83a36838 KP |
1883 | /* Set density mask. it is used for DDP */ |
1884 | this->density_mask = (1 << (density + 6)); | |
cd5f6346 KP |
1885 | |
1886 | /* OneNAND page size & block size */ | |
1887 | /* The data buffer size is equal to page size */ | |
28318776 JE |
1888 | mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); |
1889 | mtd->oobsize = mtd->writesize >> 5; | |
cd5f6346 | 1890 | /* Pagers per block is always 64 in OneNAND */ |
28318776 | 1891 | mtd->erasesize = mtd->writesize << 6; |
cd5f6346 KP |
1892 | |
1893 | this->erase_shift = ffs(mtd->erasesize) - 1; | |
28318776 | 1894 | this->page_shift = ffs(mtd->writesize) - 1; |
cd5f6346 | 1895 | this->ppb_shift = (this->erase_shift - this->page_shift); |
28318776 | 1896 | this->page_mask = (mtd->erasesize / mtd->writesize) - 1; |
cd5f6346 KP |
1897 | |
1898 | /* REVIST: Multichip handling */ | |
1899 | ||
1900 | mtd->size = this->chipsize; | |
1901 | ||
28b79ff9 KP |
1902 | /* Check OneNAND lock scheme */ |
1903 | onenand_lock_scheme(mtd); | |
d5c5e78a | 1904 | |
cd5f6346 KP |
1905 | return 0; |
1906 | } | |
1907 | ||
a41371eb KP |
1908 | /** |
1909 | * onenand_suspend - [MTD Interface] Suspend the OneNAND flash | |
1910 | * @param mtd MTD device structure | |
1911 | */ | |
1912 | static int onenand_suspend(struct mtd_info *mtd) | |
1913 | { | |
1914 | return onenand_get_device(mtd, FL_PM_SUSPENDED); | |
1915 | } | |
1916 | ||
1917 | /** | |
1918 | * onenand_resume - [MTD Interface] Resume the OneNAND flash | |
1919 | * @param mtd MTD device structure | |
1920 | */ | |
1921 | static void onenand_resume(struct mtd_info *mtd) | |
1922 | { | |
1923 | struct onenand_chip *this = mtd->priv; | |
1924 | ||
1925 | if (this->state == FL_PM_SUSPENDED) | |
1926 | onenand_release_device(mtd); | |
1927 | else | |
1928 | printk(KERN_ERR "resume() called for the chip which is not" | |
1929 | "in suspended state\n"); | |
1930 | } | |
1931 | ||
cd5f6346 KP |
1932 | /** |
1933 | * onenand_scan - [OneNAND Interface] Scan for the OneNAND device | |
1934 | * @param mtd MTD device structure | |
1935 | * @param maxchips Number of chips to scan for | |
1936 | * | |
1937 | * This fills out all the not initialized function pointers | |
1938 | * with the defaults. | |
1939 | * The flash ID is read and the mtd/chip structures are | |
1940 | * filled with the appropriate values. | |
1941 | */ | |
1942 | int onenand_scan(struct mtd_info *mtd, int maxchips) | |
1943 | { | |
1944 | struct onenand_chip *this = mtd->priv; | |
1945 | ||
1946 | if (!this->read_word) | |
1947 | this->read_word = onenand_readw; | |
1948 | if (!this->write_word) | |
1949 | this->write_word = onenand_writew; | |
1950 | ||
1951 | if (!this->command) | |
1952 | this->command = onenand_command; | |
1953 | if (!this->wait) | |
2c22120f | 1954 | onenand_setup_wait(mtd); |
cd5f6346 KP |
1955 | |
1956 | if (!this->read_bufferram) | |
1957 | this->read_bufferram = onenand_read_bufferram; | |
1958 | if (!this->write_bufferram) | |
1959 | this->write_bufferram = onenand_write_bufferram; | |
1960 | ||
cdc00130 KP |
1961 | if (!this->block_markbad) |
1962 | this->block_markbad = onenand_default_block_markbad; | |
1963 | if (!this->scan_bbt) | |
1964 | this->scan_bbt = onenand_default_bbt; | |
1965 | ||
cd5f6346 KP |
1966 | if (onenand_probe(mtd)) |
1967 | return -ENXIO; | |
1968 | ||
52b0eea7 KP |
1969 | /* Set Sync. Burst Read after probing */ |
1970 | if (this->mmcontrol) { | |
1971 | printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); | |
1972 | this->read_bufferram = onenand_sync_read_bufferram; | |
1973 | } | |
1974 | ||
532a37cf KP |
1975 | /* Allocate buffers, if necessary */ |
1976 | if (!this->page_buf) { | |
1977 | size_t len; | |
28318776 | 1978 | len = mtd->writesize + mtd->oobsize; |
532a37cf KP |
1979 | this->page_buf = kmalloc(len, GFP_KERNEL); |
1980 | if (!this->page_buf) { | |
1981 | printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); | |
1982 | return -ENOMEM; | |
1983 | } | |
1984 | this->options |= ONENAND_PAGEBUF_ALLOC; | |
1985 | } | |
1986 | ||
cd5f6346 KP |
1987 | this->state = FL_READY; |
1988 | init_waitqueue_head(&this->wq); | |
1989 | spin_lock_init(&this->chip_lock); | |
1990 | ||
1991 | switch (mtd->oobsize) { | |
1992 | case 64: | |
5bd34c09 | 1993 | this->ecclayout = &onenand_oob_64; |
cd5f6346 KP |
1994 | break; |
1995 | ||
1996 | case 32: | |
5bd34c09 | 1997 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
1998 | break; |
1999 | ||
2000 | default: | |
2001 | printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", | |
2002 | mtd->oobsize); | |
2003 | /* To prevent kernel oops */ | |
5bd34c09 | 2004 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
2005 | break; |
2006 | } | |
2007 | ||
5bd34c09 | 2008 | mtd->ecclayout = this->ecclayout; |
d5c5e78a | 2009 | |
cd5f6346 KP |
2010 | /* Fill in remaining MTD driver data */ |
2011 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2012 | mtd->flags = MTD_CAP_NANDFLASH; |
cd5f6346 KP |
2013 | mtd->ecctype = MTD_ECC_SW; |
2014 | mtd->erase = onenand_erase; | |
2015 | mtd->point = NULL; | |
2016 | mtd->unpoint = NULL; | |
2017 | mtd->read = onenand_read; | |
2018 | mtd->write = onenand_write; | |
cd5f6346 KP |
2019 | mtd->read_oob = onenand_read_oob; |
2020 | mtd->write_oob = onenand_write_oob; | |
493c6460 KP |
2021 | #ifdef CONFIG_MTD_ONENAND_OTP |
2022 | mtd->get_fact_prot_info = onenand_get_fact_prot_info; | |
2023 | mtd->read_fact_prot_reg = onenand_read_fact_prot_reg; | |
2024 | mtd->get_user_prot_info = onenand_get_user_prot_info; | |
2025 | mtd->read_user_prot_reg = onenand_read_user_prot_reg; | |
2026 | mtd->write_user_prot_reg = onenand_write_user_prot_reg; | |
2027 | mtd->lock_user_prot_reg = onenand_lock_user_prot_reg; | |
2028 | #endif | |
cd5f6346 KP |
2029 | mtd->sync = onenand_sync; |
2030 | mtd->lock = NULL; | |
2031 | mtd->unlock = onenand_unlock; | |
a41371eb KP |
2032 | mtd->suspend = onenand_suspend; |
2033 | mtd->resume = onenand_resume; | |
cd5f6346 KP |
2034 | mtd->block_isbad = onenand_block_isbad; |
2035 | mtd->block_markbad = onenand_block_markbad; | |
2036 | mtd->owner = THIS_MODULE; | |
2037 | ||
2038 | /* Unlock whole block */ | |
28b79ff9 | 2039 | onenand_unlock_all(mtd); |
cd5f6346 | 2040 | |
cdc00130 | 2041 | return this->scan_bbt(mtd); |
cd5f6346 KP |
2042 | } |
2043 | ||
2044 | /** | |
2045 | * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device | |
2046 | * @param mtd MTD device structure | |
2047 | */ | |
2048 | void onenand_release(struct mtd_info *mtd) | |
2049 | { | |
532a37cf KP |
2050 | struct onenand_chip *this = mtd->priv; |
2051 | ||
cd5f6346 KP |
2052 | #ifdef CONFIG_MTD_PARTITIONS |
2053 | /* Deregister partitions */ | |
2054 | del_mtd_partitions (mtd); | |
2055 | #endif | |
2056 | /* Deregister the device */ | |
2057 | del_mtd_device (mtd); | |
532a37cf KP |
2058 | |
2059 | /* Free bad block table memory, if allocated */ | |
2060 | if (this->bbm) | |
2061 | kfree(this->bbm); | |
2062 | /* Buffer allocated by onenand_scan */ | |
2063 | if (this->options & ONENAND_PAGEBUF_ALLOC) | |
2064 | kfree(this->page_buf); | |
cd5f6346 KP |
2065 | } |
2066 | ||
2067 | EXPORT_SYMBOL_GPL(onenand_scan); | |
2068 | EXPORT_SYMBOL_GPL(onenand_release); | |
2069 | ||
2070 | MODULE_LICENSE("GPL"); | |
2071 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
2072 | MODULE_DESCRIPTION("Generic OneNAND flash driver code"); |