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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 LT |
9 | * Additional technical information is available on |
10 | * http://www.linux-mtd.infradead.org/tech/nand.html | |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
27 | * | |
1da177e4 LT |
28 | * This program is free software; you can redistribute it and/or modify |
29 | * it under the terms of the GNU General Public License version 2 as | |
30 | * published by the Free Software Foundation. | |
31 | * | |
32 | */ | |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
44 | #include <linux/mtd/compatmac.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | ||
50 | #ifdef CONFIG_MTD_PARTITIONS | |
51 | #include <linux/mtd/partitions.h> | |
52 | #endif | |
53 | ||
54 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 55 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
56 | .eccbytes = 3, |
57 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
58 | .oobfree = { |
59 | {.offset = 3, | |
60 | .length = 2}, | |
61 | {.offset = 6, | |
62 | .length = 2}} | |
1da177e4 LT |
63 | }; |
64 | ||
5bd34c09 | 65 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
66 | .eccbytes = 6, |
67 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
68 | .oobfree = { |
69 | {.offset = 8, | |
70 | . length = 8}} | |
1da177e4 LT |
71 | }; |
72 | ||
5bd34c09 | 73 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
74 | .eccbytes = 24, |
75 | .eccpos = { | |
e0c7d767 DW |
76 | 40, 41, 42, 43, 44, 45, 46, 47, |
77 | 48, 49, 50, 51, 52, 53, 54, 55, | |
78 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
79 | .oobfree = { |
80 | {.offset = 2, | |
81 | .length = 38}} | |
1da177e4 LT |
82 | }; |
83 | ||
ace4dfee | 84 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 85 | int new_state); |
1da177e4 | 86 | |
8593fbc6 TG |
87 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
88 | struct mtd_oob_ops *ops); | |
89 | ||
d470a97c TG |
90 | /* |
91 | * For devices which display every fart in the system on a seperate LED. Is | |
92 | * compiled away when LED support is disabled. | |
93 | */ | |
94 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
95 | ||
1da177e4 LT |
96 | /** |
97 | * nand_release_device - [GENERIC] release chip | |
98 | * @mtd: MTD device structure | |
61b03bd7 TG |
99 | * |
100 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 101 | */ |
e0c7d767 | 102 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 103 | { |
ace4dfee | 104 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
105 | |
106 | /* De-select the NAND device */ | |
ace4dfee | 107 | chip->select_chip(mtd, -1); |
0dfc6246 | 108 | |
a36ed299 | 109 | /* Release the controller and the chip */ |
ace4dfee TG |
110 | spin_lock(&chip->controller->lock); |
111 | chip->controller->active = NULL; | |
112 | chip->state = FL_READY; | |
113 | wake_up(&chip->controller->wq); | |
114 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
115 | } |
116 | ||
117 | /** | |
118 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
119 | * @mtd: MTD device structure | |
120 | * | |
121 | * Default read function for 8bit buswith | |
122 | */ | |
58dd8f2b | 123 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 124 | { |
ace4dfee TG |
125 | struct nand_chip *chip = mtd->priv; |
126 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
127 | } |
128 | ||
1da177e4 LT |
129 | /** |
130 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
131 | * @mtd: MTD device structure | |
132 | * | |
61b03bd7 | 133 | * Default read function for 16bit buswith with |
1da177e4 LT |
134 | * endianess conversion |
135 | */ | |
58dd8f2b | 136 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 137 | { |
ace4dfee TG |
138 | struct nand_chip *chip = mtd->priv; |
139 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
140 | } |
141 | ||
1da177e4 LT |
142 | /** |
143 | * nand_read_word - [DEFAULT] read one word from the chip | |
144 | * @mtd: MTD device structure | |
145 | * | |
61b03bd7 | 146 | * Default read function for 16bit buswith without |
1da177e4 LT |
147 | * endianess conversion |
148 | */ | |
149 | static u16 nand_read_word(struct mtd_info *mtd) | |
150 | { | |
ace4dfee TG |
151 | struct nand_chip *chip = mtd->priv; |
152 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
153 | } |
154 | ||
1da177e4 LT |
155 | /** |
156 | * nand_select_chip - [DEFAULT] control CE line | |
157 | * @mtd: MTD device structure | |
158 | * @chip: chipnumber to select, -1 for deselect | |
159 | * | |
160 | * Default select function for 1 chip devices. | |
161 | */ | |
ace4dfee | 162 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 163 | { |
ace4dfee TG |
164 | struct nand_chip *chip = mtd->priv; |
165 | ||
166 | switch (chipnr) { | |
1da177e4 | 167 | case -1: |
ace4dfee | 168 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
169 | break; |
170 | case 0: | |
1da177e4 LT |
171 | break; |
172 | ||
173 | default: | |
174 | BUG(); | |
175 | } | |
176 | } | |
177 | ||
178 | /** | |
179 | * nand_write_buf - [DEFAULT] write buffer to chip | |
180 | * @mtd: MTD device structure | |
181 | * @buf: data buffer | |
182 | * @len: number of bytes to write | |
183 | * | |
184 | * Default write function for 8bit buswith | |
185 | */ | |
58dd8f2b | 186 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
187 | { |
188 | int i; | |
ace4dfee | 189 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 190 | |
e0c7d767 | 191 | for (i = 0; i < len; i++) |
ace4dfee | 192 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
193 | } |
194 | ||
195 | /** | |
61b03bd7 | 196 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
197 | * @mtd: MTD device structure |
198 | * @buf: buffer to store date | |
199 | * @len: number of bytes to read | |
200 | * | |
201 | * Default read function for 8bit buswith | |
202 | */ | |
58dd8f2b | 203 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
204 | { |
205 | int i; | |
ace4dfee | 206 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 207 | |
e0c7d767 | 208 | for (i = 0; i < len; i++) |
ace4dfee | 209 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
210 | } |
211 | ||
212 | /** | |
61b03bd7 | 213 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
214 | * @mtd: MTD device structure |
215 | * @buf: buffer containing the data to compare | |
216 | * @len: number of bytes to compare | |
217 | * | |
218 | * Default verify function for 8bit buswith | |
219 | */ | |
58dd8f2b | 220 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
221 | { |
222 | int i; | |
ace4dfee | 223 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 224 | |
e0c7d767 | 225 | for (i = 0; i < len; i++) |
ace4dfee | 226 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 227 | return -EFAULT; |
1da177e4 LT |
228 | return 0; |
229 | } | |
230 | ||
231 | /** | |
232 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
233 | * @mtd: MTD device structure | |
234 | * @buf: data buffer | |
235 | * @len: number of bytes to write | |
236 | * | |
237 | * Default write function for 16bit buswith | |
238 | */ | |
58dd8f2b | 239 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
240 | { |
241 | int i; | |
ace4dfee | 242 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
243 | u16 *p = (u16 *) buf; |
244 | len >>= 1; | |
61b03bd7 | 245 | |
e0c7d767 | 246 | for (i = 0; i < len; i++) |
ace4dfee | 247 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 248 | |
1da177e4 LT |
249 | } |
250 | ||
251 | /** | |
61b03bd7 | 252 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
253 | * @mtd: MTD device structure |
254 | * @buf: buffer to store date | |
255 | * @len: number of bytes to read | |
256 | * | |
257 | * Default read function for 16bit buswith | |
258 | */ | |
58dd8f2b | 259 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
260 | { |
261 | int i; | |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
263 | u16 *p = (u16 *) buf; |
264 | len >>= 1; | |
265 | ||
e0c7d767 | 266 | for (i = 0; i < len; i++) |
ace4dfee | 267 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
268 | } |
269 | ||
270 | /** | |
61b03bd7 | 271 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
272 | * @mtd: MTD device structure |
273 | * @buf: buffer containing the data to compare | |
274 | * @len: number of bytes to compare | |
275 | * | |
276 | * Default verify function for 16bit buswith | |
277 | */ | |
58dd8f2b | 278 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
279 | { |
280 | int i; | |
ace4dfee | 281 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
282 | u16 *p = (u16 *) buf; |
283 | len >>= 1; | |
284 | ||
e0c7d767 | 285 | for (i = 0; i < len; i++) |
ace4dfee | 286 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
287 | return -EFAULT; |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /** | |
293 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
294 | * @mtd: MTD device structure | |
295 | * @ofs: offset from device start | |
296 | * @getchip: 0, if the chip is already selected | |
297 | * | |
61b03bd7 | 298 | * Check, if the block is bad. |
1da177e4 LT |
299 | */ |
300 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
301 | { | |
302 | int page, chipnr, res = 0; | |
ace4dfee | 303 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
304 | u16 bad; |
305 | ||
306 | if (getchip) { | |
ace4dfee TG |
307 | page = (int)(ofs >> chip->page_shift); |
308 | chipnr = (int)(ofs >> chip->chip_shift); | |
1da177e4 | 309 | |
ace4dfee | 310 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
311 | |
312 | /* Select the NAND device */ | |
ace4dfee | 313 | chip->select_chip(mtd, chipnr); |
61b03bd7 | 314 | } else |
e0c7d767 | 315 | page = (int)ofs; |
1da177e4 | 316 | |
ace4dfee TG |
317 | if (chip->options & NAND_BUSWIDTH_16) { |
318 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
319 | page & chip->pagemask); | |
320 | bad = cpu_to_le16(chip->read_word(mtd)); | |
321 | if (chip->badblockpos & 0x1) | |
49196f33 | 322 | bad >>= 8; |
1da177e4 LT |
323 | if ((bad & 0xFF) != 0xff) |
324 | res = 1; | |
325 | } else { | |
ace4dfee TG |
326 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, |
327 | page & chip->pagemask); | |
328 | if (chip->read_byte(mtd) != 0xff) | |
1da177e4 LT |
329 | res = 1; |
330 | } | |
61b03bd7 | 331 | |
ace4dfee | 332 | if (getchip) |
1da177e4 | 333 | nand_release_device(mtd); |
61b03bd7 | 334 | |
1da177e4 LT |
335 | return res; |
336 | } | |
337 | ||
338 | /** | |
339 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
340 | * @mtd: MTD device structure | |
341 | * @ofs: offset from device start | |
342 | * | |
343 | * This is the default implementation, which can be overridden by | |
344 | * a hardware specific driver. | |
345 | */ | |
346 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
347 | { | |
ace4dfee | 348 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 349 | uint8_t buf[2] = { 0, 0 }; |
1da177e4 | 350 | int block; |
61b03bd7 | 351 | |
1da177e4 | 352 | /* Get block number */ |
ace4dfee TG |
353 | block = ((int)ofs) >> chip->bbt_erase_shift; |
354 | if (chip->bbt) | |
355 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
356 | |
357 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 358 | if (chip->options & NAND_USE_FLASH_BBT) |
e0c7d767 | 359 | return nand_update_bbt(mtd, ofs); |
61b03bd7 | 360 | |
1da177e4 | 361 | /* We write two bytes, so we dont have to mess with 16 bit access */ |
8593fbc6 TG |
362 | ofs += mtd->oobsize; |
363 | chip->ops.len = 2; | |
364 | chip->ops.datbuf = NULL; | |
365 | chip->ops.oobbuf = buf; | |
366 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
367 | ||
368 | return nand_do_write_oob(mtd, ofs, &chip->ops); | |
1da177e4 LT |
369 | } |
370 | ||
61b03bd7 | 371 | /** |
1da177e4 LT |
372 | * nand_check_wp - [GENERIC] check if the chip is write protected |
373 | * @mtd: MTD device structure | |
61b03bd7 | 374 | * Check, if the device is write protected |
1da177e4 | 375 | * |
61b03bd7 | 376 | * The function expects, that the device is already selected |
1da177e4 | 377 | */ |
e0c7d767 | 378 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 379 | { |
ace4dfee | 380 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 381 | /* Check the WP bit */ |
ace4dfee TG |
382 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
383 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
384 | } |
385 | ||
386 | /** | |
387 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
388 | * @mtd: MTD device structure | |
389 | * @ofs: offset from device start | |
390 | * @getchip: 0, if the chip is already selected | |
391 | * @allowbbt: 1, if its allowed to access the bbt area | |
392 | * | |
393 | * Check, if the block is bad. Either by reading the bad block table or | |
394 | * calling of the scan function. | |
395 | */ | |
2c0a2bed TG |
396 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
397 | int allowbbt) | |
1da177e4 | 398 | { |
ace4dfee | 399 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 400 | |
ace4dfee TG |
401 | if (!chip->bbt) |
402 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 403 | |
1da177e4 | 404 | /* Return info from the table */ |
e0c7d767 | 405 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
406 | } |
407 | ||
61b03bd7 | 408 | /* |
3b88775c TG |
409 | * Wait for the ready pin, after a command |
410 | * The timeout is catched later. | |
411 | */ | |
412 | static void nand_wait_ready(struct mtd_info *mtd) | |
413 | { | |
ace4dfee | 414 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 415 | unsigned long timeo = jiffies + 2; |
3b88775c | 416 | |
8fe833c1 | 417 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
418 | /* wait until command is processed or timeout occures */ |
419 | do { | |
ace4dfee | 420 | if (chip->dev_ready(mtd)) |
8fe833c1 | 421 | break; |
8446f1d3 | 422 | touch_softlockup_watchdog(); |
61b03bd7 | 423 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 424 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c TG |
425 | } |
426 | ||
1da177e4 LT |
427 | /** |
428 | * nand_command - [DEFAULT] Send command to NAND device | |
429 | * @mtd: MTD device structure | |
430 | * @command: the command to be sent | |
431 | * @column: the column address for this command, -1 if none | |
432 | * @page_addr: the page address for this command, -1 if none | |
433 | * | |
434 | * Send command to NAND device. This function is used for small page | |
435 | * devices (256/512 Bytes per page) | |
436 | */ | |
7abd3ef9 TG |
437 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
438 | int column, int page_addr) | |
1da177e4 | 439 | { |
ace4dfee | 440 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 441 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 442 | |
1da177e4 LT |
443 | /* |
444 | * Write out the command to the device. | |
445 | */ | |
446 | if (command == NAND_CMD_SEQIN) { | |
447 | int readcmd; | |
448 | ||
28318776 | 449 | if (column >= mtd->writesize) { |
1da177e4 | 450 | /* OOB area */ |
28318776 | 451 | column -= mtd->writesize; |
1da177e4 LT |
452 | readcmd = NAND_CMD_READOOB; |
453 | } else if (column < 256) { | |
454 | /* First 256 bytes --> READ0 */ | |
455 | readcmd = NAND_CMD_READ0; | |
456 | } else { | |
457 | column -= 256; | |
458 | readcmd = NAND_CMD_READ1; | |
459 | } | |
ace4dfee | 460 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 461 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 462 | } |
ace4dfee | 463 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 464 | |
7abd3ef9 TG |
465 | /* |
466 | * Address cycle, when necessary | |
467 | */ | |
468 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
469 | /* Serially input address */ | |
470 | if (column != -1) { | |
471 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 472 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 473 | column >>= 1; |
ace4dfee | 474 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
475 | ctrl &= ~NAND_CTRL_CHANGE; |
476 | } | |
477 | if (page_addr != -1) { | |
ace4dfee | 478 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 479 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 480 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 481 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
482 | if (chip->chipsize > (32 << 20)) |
483 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 484 | } |
ace4dfee | 485 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
486 | |
487 | /* | |
488 | * program and erase have their own busy handlers | |
1da177e4 | 489 | * status and sequential in needs no delay |
e0c7d767 | 490 | */ |
1da177e4 | 491 | switch (command) { |
61b03bd7 | 492 | |
1da177e4 LT |
493 | case NAND_CMD_PAGEPROG: |
494 | case NAND_CMD_ERASE1: | |
495 | case NAND_CMD_ERASE2: | |
496 | case NAND_CMD_SEQIN: | |
497 | case NAND_CMD_STATUS: | |
ace4dfee | 498 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE); |
1da177e4 LT |
499 | return; |
500 | ||
501 | case NAND_CMD_RESET: | |
ace4dfee | 502 | if (chip->dev_ready) |
1da177e4 | 503 | break; |
ace4dfee TG |
504 | udelay(chip->chip_delay); |
505 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 506 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
507 | chip->cmd_ctrl(mtd, |
508 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 509 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
510 | return; |
511 | ||
e0c7d767 | 512 | /* This applies to read commands */ |
1da177e4 | 513 | default: |
61b03bd7 | 514 | /* |
1da177e4 LT |
515 | * If we don't have access to the busy pin, we apply the given |
516 | * command delay | |
e0c7d767 | 517 | */ |
ace4dfee TG |
518 | if (!chip->dev_ready) { |
519 | udelay(chip->chip_delay); | |
1da177e4 | 520 | return; |
61b03bd7 | 521 | } |
1da177e4 | 522 | } |
1da177e4 LT |
523 | /* Apply this short delay always to ensure that we do wait tWB in |
524 | * any case on any machine. */ | |
e0c7d767 | 525 | ndelay(100); |
3b88775c TG |
526 | |
527 | nand_wait_ready(mtd); | |
1da177e4 LT |
528 | } |
529 | ||
530 | /** | |
531 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
532 | * @mtd: MTD device structure | |
533 | * @command: the command to be sent | |
534 | * @column: the column address for this command, -1 if none | |
535 | * @page_addr: the page address for this command, -1 if none | |
536 | * | |
7abd3ef9 TG |
537 | * Send command to NAND device. This is the version for the new large page |
538 | * devices We dont have the separate regions as we have in the small page | |
539 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 LT |
540 | * |
541 | */ | |
7abd3ef9 TG |
542 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
543 | int column, int page_addr) | |
1da177e4 | 544 | { |
ace4dfee | 545 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
546 | |
547 | /* Emulate NAND_CMD_READOOB */ | |
548 | if (command == NAND_CMD_READOOB) { | |
28318776 | 549 | column += mtd->writesize; |
1da177e4 LT |
550 | command = NAND_CMD_READ0; |
551 | } | |
61b03bd7 | 552 | |
7abd3ef9 | 553 | /* Command latch cycle */ |
ace4dfee | 554 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 555 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
556 | |
557 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 558 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
559 | |
560 | /* Serially input address */ | |
561 | if (column != -1) { | |
562 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 563 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 564 | column >>= 1; |
ace4dfee | 565 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 566 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 567 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 568 | } |
1da177e4 | 569 | if (page_addr != -1) { |
ace4dfee TG |
570 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
571 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 572 | NAND_NCE | NAND_ALE); |
1da177e4 | 573 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
574 | if (chip->chipsize > (128 << 20)) |
575 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 576 | NAND_NCE | NAND_ALE); |
1da177e4 | 577 | } |
1da177e4 | 578 | } |
ace4dfee | 579 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
580 | |
581 | /* | |
582 | * program and erase have their own busy handlers | |
30f464b7 DM |
583 | * status, sequential in, and deplete1 need no delay |
584 | */ | |
1da177e4 | 585 | switch (command) { |
61b03bd7 | 586 | |
1da177e4 LT |
587 | case NAND_CMD_CACHEDPROG: |
588 | case NAND_CMD_PAGEPROG: | |
589 | case NAND_CMD_ERASE1: | |
590 | case NAND_CMD_ERASE2: | |
591 | case NAND_CMD_SEQIN: | |
592 | case NAND_CMD_STATUS: | |
30f464b7 | 593 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
594 | return; |
595 | ||
e0c7d767 DW |
596 | /* |
597 | * read error status commands require only a short delay | |
598 | */ | |
30f464b7 DM |
599 | case NAND_CMD_STATUS_ERROR: |
600 | case NAND_CMD_STATUS_ERROR0: | |
601 | case NAND_CMD_STATUS_ERROR1: | |
602 | case NAND_CMD_STATUS_ERROR2: | |
603 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 604 | udelay(chip->chip_delay); |
30f464b7 | 605 | return; |
1da177e4 LT |
606 | |
607 | case NAND_CMD_RESET: | |
ace4dfee | 608 | if (chip->dev_ready) |
1da177e4 | 609 | break; |
ace4dfee | 610 | udelay(chip->chip_delay); |
12efdde3 TG |
611 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
612 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
613 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
614 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 615 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
616 | return; |
617 | ||
618 | case NAND_CMD_READ0: | |
12efdde3 TG |
619 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
620 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
621 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
622 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 623 | |
e0c7d767 | 624 | /* This applies to read commands */ |
1da177e4 | 625 | default: |
61b03bd7 | 626 | /* |
1da177e4 LT |
627 | * If we don't have access to the busy pin, we apply the given |
628 | * command delay | |
e0c7d767 | 629 | */ |
ace4dfee TG |
630 | if (!chip->dev_ready) { |
631 | udelay(chip->chip_delay); | |
1da177e4 | 632 | return; |
61b03bd7 | 633 | } |
1da177e4 | 634 | } |
3b88775c | 635 | |
1da177e4 LT |
636 | /* Apply this short delay always to ensure that we do wait tWB in |
637 | * any case on any machine. */ | |
e0c7d767 | 638 | ndelay(100); |
3b88775c TG |
639 | |
640 | nand_wait_ready(mtd); | |
1da177e4 LT |
641 | } |
642 | ||
643 | /** | |
644 | * nand_get_device - [GENERIC] Get chip for selected access | |
645 | * @this: the nand chip descriptor | |
646 | * @mtd: MTD device structure | |
61b03bd7 | 647 | * @new_state: the state which is requested |
1da177e4 LT |
648 | * |
649 | * Get the device and lock it for exclusive access | |
650 | */ | |
2c0a2bed | 651 | static int |
ace4dfee | 652 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 653 | { |
ace4dfee TG |
654 | spinlock_t *lock = &chip->controller->lock; |
655 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 656 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 657 | retry: |
0dfc6246 TG |
658 | spin_lock(lock); |
659 | ||
1da177e4 | 660 | /* Hardware controller shared among independend devices */ |
a36ed299 | 661 | /* Hardware controller shared among independend devices */ |
ace4dfee TG |
662 | if (!chip->controller->active) |
663 | chip->controller->active = chip; | |
a36ed299 | 664 | |
ace4dfee TG |
665 | if (chip->controller->active == chip && chip->state == FL_READY) { |
666 | chip->state = new_state; | |
0dfc6246 | 667 | spin_unlock(lock); |
962034f4 VW |
668 | return 0; |
669 | } | |
670 | if (new_state == FL_PM_SUSPENDED) { | |
671 | spin_unlock(lock); | |
ace4dfee | 672 | return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; |
0dfc6246 TG |
673 | } |
674 | set_current_state(TASK_UNINTERRUPTIBLE); | |
675 | add_wait_queue(wq, &wait); | |
676 | spin_unlock(lock); | |
677 | schedule(); | |
678 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
679 | goto retry; |
680 | } | |
681 | ||
682 | /** | |
683 | * nand_wait - [DEFAULT] wait until the command is done | |
684 | * @mtd: MTD device structure | |
685 | * @this: NAND chip structure | |
686 | * @state: state to select the max. timeout value | |
687 | * | |
688 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 689 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 LT |
690 | * general NAND and SmartMedia specs |
691 | * | |
692 | */ | |
ace4dfee | 693 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state) |
1da177e4 LT |
694 | { |
695 | ||
e0c7d767 DW |
696 | unsigned long timeo = jiffies; |
697 | int status; | |
61b03bd7 | 698 | |
1da177e4 | 699 | if (state == FL_ERASING) |
e0c7d767 | 700 | timeo += (HZ * 400) / 1000; |
1da177e4 | 701 | else |
e0c7d767 | 702 | timeo += (HZ * 20) / 1000; |
1da177e4 | 703 | |
8fe833c1 RP |
704 | led_trigger_event(nand_led_trigger, LED_FULL); |
705 | ||
1da177e4 LT |
706 | /* Apply this short delay always to ensure that we do wait tWB in |
707 | * any case on any machine. */ | |
e0c7d767 | 708 | ndelay(100); |
1da177e4 | 709 | |
ace4dfee TG |
710 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
711 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 712 | else |
ace4dfee | 713 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 714 | |
61b03bd7 | 715 | while (time_before(jiffies, timeo)) { |
1da177e4 | 716 | /* Check, if we were interrupted */ |
ace4dfee | 717 | if (chip->state != state) |
1da177e4 LT |
718 | return 0; |
719 | ||
ace4dfee TG |
720 | if (chip->dev_ready) { |
721 | if (chip->dev_ready(mtd)) | |
61b03bd7 | 722 | break; |
1da177e4 | 723 | } else { |
ace4dfee | 724 | if (chip->read_byte(mtd) & NAND_STATUS_READY) |
1da177e4 LT |
725 | break; |
726 | } | |
20a6c211 | 727 | cond_resched(); |
1da177e4 | 728 | } |
8fe833c1 RP |
729 | led_trigger_event(nand_led_trigger, LED_OFF); |
730 | ||
ace4dfee | 731 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
732 | return status; |
733 | } | |
734 | ||
8593fbc6 TG |
735 | /** |
736 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
737 | * @mtd: mtd info structure | |
738 | * @chip: nand chip info structure | |
739 | * @buf: buffer to store read data | |
740 | */ | |
741 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
742 | uint8_t *buf) | |
743 | { | |
744 | chip->read_buf(mtd, buf, mtd->writesize); | |
745 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
746 | return 0; | |
747 | } | |
748 | ||
1da177e4 | 749 | /** |
f5bbdacc TG |
750 | * nand_read_page_swecc - {REPLACABLE] software ecc based page read function |
751 | * @mtd: mtd info structure | |
752 | * @chip: nand chip info structure | |
753 | * @buf: buffer to store read data | |
068e3c0a | 754 | */ |
f5bbdacc TG |
755 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
756 | uint8_t *buf) | |
1da177e4 | 757 | { |
f5bbdacc TG |
758 | int i, eccsize = chip->ecc.size; |
759 | int eccbytes = chip->ecc.bytes; | |
760 | int eccsteps = chip->ecc.steps; | |
761 | uint8_t *p = buf; | |
f75e5097 TG |
762 | uint8_t *ecc_calc = chip->buffers.ecccalc; |
763 | uint8_t *ecc_code = chip->buffers.ecccode; | |
5bd34c09 | 764 | int *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 765 | |
8593fbc6 | 766 | nand_read_page_raw(mtd, chip, buf); |
f5bbdacc TG |
767 | |
768 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
769 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
770 | ||
771 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 772 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
773 | |
774 | eccsteps = chip->ecc.steps; | |
775 | p = buf; | |
776 | ||
777 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
778 | int stat; | |
779 | ||
780 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
781 | if (stat == -1) | |
782 | mtd->ecc_stats.failed++; | |
783 | else | |
784 | mtd->ecc_stats.corrected += stat; | |
785 | } | |
786 | return 0; | |
22c60f5f | 787 | } |
1da177e4 | 788 | |
068e3c0a | 789 | /** |
f5bbdacc TG |
790 | * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function |
791 | * @mtd: mtd info structure | |
792 | * @chip: nand chip info structure | |
793 | * @buf: buffer to store read data | |
068e3c0a | 794 | * |
f5bbdacc | 795 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 796 | */ |
f5bbdacc TG |
797 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
798 | uint8_t *buf) | |
1da177e4 | 799 | { |
f5bbdacc TG |
800 | int i, eccsize = chip->ecc.size; |
801 | int eccbytes = chip->ecc.bytes; | |
802 | int eccsteps = chip->ecc.steps; | |
803 | uint8_t *p = buf; | |
f75e5097 TG |
804 | uint8_t *ecc_calc = chip->buffers.ecccalc; |
805 | uint8_t *ecc_code = chip->buffers.ecccode; | |
5bd34c09 | 806 | int *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
807 | |
808 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
809 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
810 | chip->read_buf(mtd, p, eccsize); | |
811 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 812 | } |
f75e5097 | 813 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 814 | |
f5bbdacc | 815 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 816 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 817 | |
f5bbdacc TG |
818 | eccsteps = chip->ecc.steps; |
819 | p = buf; | |
61b03bd7 | 820 | |
f5bbdacc TG |
821 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
822 | int stat; | |
1da177e4 | 823 | |
f5bbdacc TG |
824 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
825 | if (stat == -1) | |
826 | mtd->ecc_stats.failed++; | |
827 | else | |
828 | mtd->ecc_stats.corrected += stat; | |
829 | } | |
830 | return 0; | |
831 | } | |
1da177e4 | 832 | |
f5bbdacc TG |
833 | /** |
834 | * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
835 | * @mtd: mtd info structure | |
836 | * @chip: nand chip info structure | |
837 | * @buf: buffer to store read data | |
838 | * | |
839 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 840 | * we need a special oob layout and handling. |
f5bbdacc TG |
841 | */ |
842 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
843 | uint8_t *buf) | |
844 | { | |
845 | int i, eccsize = chip->ecc.size; | |
846 | int eccbytes = chip->ecc.bytes; | |
847 | int eccsteps = chip->ecc.steps; | |
848 | uint8_t *p = buf; | |
f75e5097 | 849 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 850 | |
f5bbdacc TG |
851 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
852 | int stat; | |
61b03bd7 | 853 | |
f5bbdacc TG |
854 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
855 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 856 | |
f5bbdacc TG |
857 | if (chip->ecc.prepad) { |
858 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
859 | oob += chip->ecc.prepad; | |
860 | } | |
1da177e4 | 861 | |
f5bbdacc TG |
862 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
863 | chip->read_buf(mtd, oob, eccbytes); | |
864 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 865 | |
f5bbdacc TG |
866 | if (stat == -1) |
867 | mtd->ecc_stats.failed++; | |
61b03bd7 | 868 | else |
f5bbdacc | 869 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 870 | |
f5bbdacc | 871 | oob += eccbytes; |
1da177e4 | 872 | |
f5bbdacc TG |
873 | if (chip->ecc.postpad) { |
874 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
875 | oob += chip->ecc.postpad; | |
61b03bd7 | 876 | } |
f5bbdacc | 877 | } |
1da177e4 | 878 | |
f5bbdacc | 879 | /* Calculate remaining oob bytes */ |
f75e5097 | 880 | i = oob - chip->oob_poi; |
f5bbdacc TG |
881 | if (i) |
882 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 883 | |
f5bbdacc TG |
884 | return 0; |
885 | } | |
1da177e4 | 886 | |
f5bbdacc | 887 | /** |
8593fbc6 TG |
888 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
889 | * @chip: nand chip structure | |
890 | * @ops: oob ops structure | |
891 | */ | |
892 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
893 | struct mtd_oob_ops *ops) | |
894 | { | |
895 | size_t len = ops->ooblen; | |
896 | ||
897 | switch(ops->mode) { | |
898 | ||
899 | case MTD_OOB_PLACE: | |
900 | case MTD_OOB_RAW: | |
901 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
902 | return oob + len; | |
903 | ||
904 | case MTD_OOB_AUTO: { | |
905 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
906 | size_t bytes; | |
907 | ||
908 | for(; free->length && len; free++, len -= bytes) { | |
909 | bytes = min(len, free->length); | |
910 | ||
911 | memcpy(oob, chip->oob_poi + free->offset, bytes); | |
912 | oob += bytes; | |
913 | } | |
914 | return oob; | |
915 | } | |
916 | default: | |
917 | BUG(); | |
918 | } | |
919 | return NULL; | |
920 | } | |
921 | ||
922 | /** | |
923 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
924 | * |
925 | * @mtd: MTD device structure | |
926 | * @from: offset to read from | |
f5bbdacc TG |
927 | * |
928 | * Internal function. Called with chip held. | |
929 | */ | |
8593fbc6 TG |
930 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
931 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
932 | { |
933 | int chipnr, page, realpage, col, bytes, aligned; | |
934 | struct nand_chip *chip = mtd->priv; | |
935 | struct mtd_ecc_stats stats; | |
936 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
937 | int sndcmd = 1; | |
938 | int ret = 0; | |
8593fbc6 TG |
939 | uint32_t readlen = ops->len; |
940 | uint8_t *bufpoi, *oob, *buf; | |
1da177e4 | 941 | |
f5bbdacc | 942 | stats = mtd->ecc_stats; |
1da177e4 | 943 | |
f5bbdacc TG |
944 | chipnr = (int)(from >> chip->chip_shift); |
945 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 946 | |
f5bbdacc TG |
947 | realpage = (int)(from >> chip->page_shift); |
948 | page = realpage & chip->pagemask; | |
1da177e4 | 949 | |
f5bbdacc | 950 | col = (int)(from & (mtd->writesize - 1)); |
f75e5097 | 951 | chip->oob_poi = chip->buffers.oobrbuf; |
61b03bd7 | 952 | |
8593fbc6 TG |
953 | buf = ops->datbuf; |
954 | oob = ops->oobbuf; | |
955 | ||
f5bbdacc TG |
956 | while(1) { |
957 | bytes = min(mtd->writesize - col, readlen); | |
958 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 959 | |
f5bbdacc | 960 | /* Is the current page in the buffer ? */ |
8593fbc6 | 961 | if (realpage != chip->pagebuf || oob) { |
f75e5097 | 962 | bufpoi = aligned ? buf : chip->buffers.databuf; |
61b03bd7 | 963 | |
f5bbdacc TG |
964 | if (likely(sndcmd)) { |
965 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
966 | sndcmd = 0; | |
1da177e4 | 967 | } |
1da177e4 | 968 | |
f5bbdacc TG |
969 | /* Now read the page into the buffer */ |
970 | ret = chip->ecc.read_page(mtd, chip, bufpoi); | |
971 | if (ret < 0) | |
1da177e4 | 972 | break; |
f5bbdacc TG |
973 | |
974 | /* Transfer not aligned data */ | |
975 | if (!aligned) { | |
976 | chip->pagebuf = realpage; | |
f75e5097 | 977 | memcpy(buf, chip->buffers.databuf + col, bytes); |
f5bbdacc TG |
978 | } |
979 | ||
8593fbc6 TG |
980 | buf += bytes; |
981 | ||
982 | if (unlikely(oob)) { | |
983 | /* Raw mode does data:oob:data:oob */ | |
984 | if (ops->mode != MTD_OOB_RAW) | |
985 | oob = nand_transfer_oob(chip, oob, ops); | |
986 | else | |
987 | buf = nand_transfer_oob(chip, buf, ops); | |
988 | } | |
989 | ||
f5bbdacc TG |
990 | if (!(chip->options & NAND_NO_READRDY)) { |
991 | /* | |
992 | * Apply delay or wait for ready/busy pin. Do | |
993 | * this before the AUTOINCR check, so no | |
994 | * problems arise if a chip which does auto | |
995 | * increment is marked as NOAUTOINCR by the | |
996 | * board driver. | |
997 | */ | |
998 | if (!chip->dev_ready) | |
999 | udelay(chip->chip_delay); | |
1000 | else | |
1001 | nand_wait_ready(mtd); | |
1da177e4 | 1002 | } |
8593fbc6 | 1003 | } else { |
f75e5097 | 1004 | memcpy(buf, chip->buffers.databuf + col, bytes); |
8593fbc6 TG |
1005 | buf += bytes; |
1006 | } | |
1da177e4 | 1007 | |
f5bbdacc | 1008 | readlen -= bytes; |
61b03bd7 | 1009 | |
f5bbdacc | 1010 | if (!readlen) |
61b03bd7 | 1011 | break; |
1da177e4 LT |
1012 | |
1013 | /* For subsequent reads align to page boundary. */ | |
1014 | col = 0; | |
1015 | /* Increment page address */ | |
1016 | realpage++; | |
1017 | ||
ace4dfee | 1018 | page = realpage & chip->pagemask; |
1da177e4 LT |
1019 | /* Check, if we cross a chip boundary */ |
1020 | if (!page) { | |
1021 | chipnr++; | |
ace4dfee TG |
1022 | chip->select_chip(mtd, -1); |
1023 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1024 | } |
f5bbdacc | 1025 | |
61b03bd7 TG |
1026 | /* Check, if the chip supports auto page increment |
1027 | * or if we have hit a block boundary. | |
e0c7d767 | 1028 | */ |
f5bbdacc | 1029 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1030 | sndcmd = 1; |
1da177e4 LT |
1031 | } |
1032 | ||
8593fbc6 | 1033 | ops->retlen = ops->len - (size_t) readlen; |
1da177e4 | 1034 | |
f5bbdacc TG |
1035 | if (ret) |
1036 | return ret; | |
1037 | ||
9a1fcdfd TG |
1038 | if (mtd->ecc_stats.failed - stats.failed) |
1039 | return -EBADMSG; | |
1040 | ||
1041 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1042 | } |
1043 | ||
1044 | /** | |
1045 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1046 | * @mtd: MTD device structure | |
1047 | * @from: offset to read from | |
1048 | * @len: number of bytes to read | |
1049 | * @retlen: pointer to variable to store the number of read bytes | |
1050 | * @buf: the databuffer to put data | |
1051 | * | |
1052 | * Get hold of the chip and call nand_do_read | |
1053 | */ | |
1054 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1055 | size_t *retlen, uint8_t *buf) | |
1056 | { | |
8593fbc6 | 1057 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1058 | int ret; |
1059 | ||
f5bbdacc TG |
1060 | /* Do not allow reads past end of device */ |
1061 | if ((from + len) > mtd->size) | |
1062 | return -EINVAL; | |
1063 | if (!len) | |
1064 | return 0; | |
1065 | ||
8593fbc6 | 1066 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1067 | |
8593fbc6 TG |
1068 | chip->ops.len = len; |
1069 | chip->ops.datbuf = buf; | |
1070 | chip->ops.oobbuf = NULL; | |
1071 | ||
1072 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc TG |
1073 | |
1074 | nand_release_device(mtd); | |
1075 | ||
8593fbc6 | 1076 | *retlen = chip->ops.retlen; |
f5bbdacc | 1077 | return ret; |
1da177e4 LT |
1078 | } |
1079 | ||
1080 | /** | |
8593fbc6 | 1081 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1082 | * @mtd: MTD device structure |
1083 | * @from: offset to read from | |
8593fbc6 | 1084 | * @ops: oob operations description structure |
1da177e4 LT |
1085 | * |
1086 | * NAND read out-of-band data from the spare area | |
1087 | */ | |
8593fbc6 TG |
1088 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1089 | struct mtd_oob_ops *ops) | |
1da177e4 | 1090 | { |
7314e9e7 | 1091 | int col, page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1092 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1093 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
8593fbc6 TG |
1094 | int direct, bytes, readlen = ops->len; |
1095 | uint8_t *bufpoi, *buf = ops->oobbuf; | |
61b03bd7 | 1096 | |
7314e9e7 TG |
1097 | DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", |
1098 | (unsigned int)from, (int)len); | |
1da177e4 | 1099 | |
7314e9e7 | 1100 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1101 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1102 | |
7314e9e7 TG |
1103 | /* Shift to get page */ |
1104 | realpage = (int)(from >> chip->page_shift); | |
1105 | page = realpage & chip->pagemask; | |
1da177e4 | 1106 | |
8593fbc6 TG |
1107 | if (ops->mode != MTD_OOB_AUTO) { |
1108 | col = ops->ooboffs; | |
1109 | direct = 1; | |
1110 | } else { | |
1111 | col = 0; | |
1112 | direct = 0; | |
1113 | } | |
7314e9e7 TG |
1114 | |
1115 | while(1) { | |
8593fbc6 TG |
1116 | bytes = direct ? ops->ooblen : mtd->oobsize; |
1117 | bufpoi = direct ? buf : chip->buffers.oobrbuf; | |
7314e9e7 TG |
1118 | |
1119 | if (likely(sndcmd)) { | |
1120 | chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page); | |
1121 | sndcmd = 0; | |
1122 | } | |
1123 | ||
8593fbc6 | 1124 | chip->read_buf(mtd, bufpoi, bytes); |
61b03bd7 | 1125 | |
8593fbc6 TG |
1126 | if (unlikely(!direct)) |
1127 | buf = nand_transfer_oob(chip, buf, ops); | |
1128 | else | |
1129 | buf += ops->ooblen; | |
1130 | ||
1131 | readlen -= ops->ooblen; | |
7314e9e7 TG |
1132 | if (!readlen) |
1133 | break; | |
1134 | ||
1135 | if (!(chip->options & NAND_NO_READRDY)) { | |
1136 | /* | |
1137 | * Apply delay or wait for ready/busy pin. Do this | |
1138 | * before the AUTOINCR check, so no problems arise if a | |
1139 | * chip which does auto increment is marked as | |
1140 | * NOAUTOINCR by the board driver. | |
19870da7 | 1141 | */ |
ace4dfee TG |
1142 | if (!chip->dev_ready) |
1143 | udelay(chip->chip_delay); | |
19870da7 TG |
1144 | else |
1145 | nand_wait_ready(mtd); | |
7314e9e7 | 1146 | } |
19870da7 | 1147 | |
7314e9e7 TG |
1148 | /* Increment page address */ |
1149 | realpage++; | |
1150 | ||
1151 | page = realpage & chip->pagemask; | |
1152 | /* Check, if we cross a chip boundary */ | |
1153 | if (!page) { | |
1154 | chipnr++; | |
1155 | chip->select_chip(mtd, -1); | |
1156 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1157 | } |
7314e9e7 TG |
1158 | |
1159 | /* Check, if the chip supports auto page increment | |
1160 | * or if we have hit a block boundary. | |
1161 | */ | |
1162 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1163 | sndcmd = 1; | |
1da177e4 LT |
1164 | } |
1165 | ||
8593fbc6 | 1166 | ops->retlen = ops->len; |
1da177e4 LT |
1167 | return 0; |
1168 | } | |
1169 | ||
1170 | /** | |
8593fbc6 | 1171 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1172 | * @mtd: MTD device structure |
1da177e4 | 1173 | * @from: offset to read from |
8593fbc6 | 1174 | * @ops: oob operation description structure |
1da177e4 | 1175 | * |
8593fbc6 | 1176 | * NAND read data and/or out-of-band data |
1da177e4 | 1177 | */ |
8593fbc6 TG |
1178 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1179 | struct mtd_oob_ops *ops) | |
1da177e4 | 1180 | { |
8593fbc6 TG |
1181 | int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, |
1182 | uint8_t *buf) = NULL; | |
ace4dfee | 1183 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1184 | int ret = -ENOTSUPP; |
1185 | ||
1186 | ops->retlen = 0; | |
1da177e4 LT |
1187 | |
1188 | /* Do not allow reads past end of device */ | |
8593fbc6 TG |
1189 | if ((from + ops->len) > mtd->size) { |
1190 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
ace4dfee | 1191 | "Attempt read beyond end of device\n"); |
1da177e4 LT |
1192 | return -EINVAL; |
1193 | } | |
1194 | ||
ace4dfee | 1195 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1196 | |
8593fbc6 TG |
1197 | switch(ops->mode) { |
1198 | case MTD_OOB_PLACE: | |
1199 | case MTD_OOB_AUTO: | |
1200 | break; | |
61b03bd7 | 1201 | |
8593fbc6 TG |
1202 | case MTD_OOB_RAW: |
1203 | /* Replace the read_page algorithm temporary */ | |
1204 | read_page = chip->ecc.read_page; | |
1205 | chip->ecc.read_page = nand_read_page_raw; | |
1206 | break; | |
1da177e4 | 1207 | |
8593fbc6 TG |
1208 | default: |
1209 | goto out; | |
1210 | } | |
1da177e4 | 1211 | |
8593fbc6 TG |
1212 | if (!ops->datbuf) |
1213 | ret = nand_do_read_oob(mtd, from, ops); | |
1214 | else | |
1215 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1216 | |
8593fbc6 TG |
1217 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
1218 | chip->ecc.read_page = read_page; | |
1219 | out: | |
1220 | nand_release_device(mtd); | |
1221 | return ret; | |
1222 | } | |
61b03bd7 | 1223 | |
1da177e4 | 1224 | |
8593fbc6 TG |
1225 | /** |
1226 | * nand_write_page_raw - [Intern] raw page write function | |
1227 | * @mtd: mtd info structure | |
1228 | * @chip: nand chip info structure | |
1229 | * @buf: data buffer | |
1230 | */ | |
1231 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1232 | const uint8_t *buf) | |
1233 | { | |
1234 | chip->write_buf(mtd, buf, mtd->writesize); | |
1235 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1236 | } |
1237 | ||
9223a456 | 1238 | /** |
f75e5097 TG |
1239 | * nand_write_page_swecc - {REPLACABLE] software ecc based page write function |
1240 | * @mtd: mtd info structure | |
1241 | * @chip: nand chip info structure | |
1242 | * @buf: data buffer | |
9223a456 | 1243 | */ |
f75e5097 TG |
1244 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1245 | const uint8_t *buf) | |
9223a456 | 1246 | { |
f75e5097 TG |
1247 | int i, eccsize = chip->ecc.size; |
1248 | int eccbytes = chip->ecc.bytes; | |
1249 | int eccsteps = chip->ecc.steps; | |
1250 | uint8_t *ecc_calc = chip->buffers.ecccalc; | |
1251 | const uint8_t *p = buf; | |
5bd34c09 | 1252 | int *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1253 | |
8593fbc6 TG |
1254 | /* Software ecc calculation */ |
1255 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1256 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1257 | |
8593fbc6 TG |
1258 | for (i = 0; i < chip->ecc.total; i++) |
1259 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1260 | |
8593fbc6 | 1261 | nand_write_page_raw(mtd, chip, buf); |
f75e5097 | 1262 | } |
9223a456 | 1263 | |
f75e5097 TG |
1264 | /** |
1265 | * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function | |
1266 | * @mtd: mtd info structure | |
1267 | * @chip: nand chip info structure | |
1268 | * @buf: data buffer | |
1269 | */ | |
1270 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1271 | const uint8_t *buf) | |
1272 | { | |
1273 | int i, eccsize = chip->ecc.size; | |
1274 | int eccbytes = chip->ecc.bytes; | |
1275 | int eccsteps = chip->ecc.steps; | |
1276 | uint8_t *ecc_calc = chip->buffers.ecccalc; | |
1277 | const uint8_t *p = buf; | |
5bd34c09 | 1278 | int *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1279 | |
f75e5097 TG |
1280 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1281 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1282 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1283 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1284 | } |
1285 | ||
f75e5097 TG |
1286 | for (i = 0; i < chip->ecc.total; i++) |
1287 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1288 | ||
1289 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1290 | } |
1291 | ||
61b03bd7 | 1292 | /** |
f75e5097 TG |
1293 | * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write |
1294 | * @mtd: mtd info structure | |
1295 | * @chip: nand chip info structure | |
1296 | * @buf: data buffer | |
1da177e4 | 1297 | * |
f75e5097 TG |
1298 | * The hw generator calculates the error syndrome automatically. Therefor |
1299 | * we need a special oob layout and handling. | |
1300 | */ | |
1301 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1302 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1303 | { |
f75e5097 TG |
1304 | int i, eccsize = chip->ecc.size; |
1305 | int eccbytes = chip->ecc.bytes; | |
1306 | int eccsteps = chip->ecc.steps; | |
1307 | const uint8_t *p = buf; | |
1308 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1309 | |
f75e5097 | 1310 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1311 | |
f75e5097 TG |
1312 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1313 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1314 | |
f75e5097 TG |
1315 | if (chip->ecc.prepad) { |
1316 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1317 | oob += chip->ecc.prepad; | |
1318 | } | |
1319 | ||
1320 | chip->ecc.calculate(mtd, p, oob); | |
1321 | chip->write_buf(mtd, oob, eccbytes); | |
1322 | oob += eccbytes; | |
1323 | ||
1324 | if (chip->ecc.postpad) { | |
1325 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1326 | oob += chip->ecc.postpad; | |
1da177e4 | 1327 | } |
1da177e4 | 1328 | } |
f75e5097 TG |
1329 | |
1330 | /* Calculate remaining oob bytes */ | |
1331 | i = oob - chip->oob_poi; | |
1332 | if (i) | |
1333 | chip->write_buf(mtd, oob, i); | |
1334 | } | |
1335 | ||
1336 | /** | |
1337 | * nand_write_page - [INTERNAL] write one page | |
1338 | * @mtd: MTD device structure | |
1339 | * @chip: NAND chip descriptor | |
1340 | * @buf: the data to write | |
1341 | * @page: page number to write | |
1342 | * @cached: cached programming | |
1343 | */ | |
1344 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1345 | const uint8_t *buf, int page, int cached) | |
1346 | { | |
1347 | int status; | |
1348 | ||
1349 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
1350 | ||
1351 | chip->ecc.write_page(mtd, chip, buf); | |
1352 | ||
1353 | /* | |
1354 | * Cached progamming disabled for now, Not sure if its worth the | |
1355 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
1356 | */ | |
1357 | cached = 0; | |
1358 | ||
1359 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
1360 | ||
1361 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1362 | status = chip->waitfunc(mtd, chip, FL_WRITING); | |
1363 | /* | |
1364 | * See if operation failed and additional status checks are | |
1365 | * available | |
1366 | */ | |
1367 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1368 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
1369 | page); | |
1370 | ||
1371 | if (status & NAND_STATUS_FAIL) | |
1372 | return -EIO; | |
1373 | } else { | |
1374 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
1375 | status = chip->waitfunc(mtd, chip, FL_WRITING); | |
1376 | } | |
1377 | ||
1378 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1379 | /* Send command to read back the data */ | |
1380 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1381 | ||
1382 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
1383 | return -EIO; | |
1384 | #endif | |
1385 | return 0; | |
1da177e4 LT |
1386 | } |
1387 | ||
8593fbc6 TG |
1388 | /** |
1389 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
1390 | * @chip: nand chip structure | |
1391 | * @oob: oob data buffer | |
1392 | * @ops: oob ops structure | |
1393 | */ | |
1394 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, | |
1395 | struct mtd_oob_ops *ops) | |
1396 | { | |
1397 | size_t len = ops->ooblen; | |
1398 | ||
1399 | switch(ops->mode) { | |
1400 | ||
1401 | case MTD_OOB_PLACE: | |
1402 | case MTD_OOB_RAW: | |
1403 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
1404 | return oob + len; | |
1405 | ||
1406 | case MTD_OOB_AUTO: { | |
1407 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
1408 | size_t bytes; | |
1409 | ||
1410 | for(; free->length && len; free++, len -= bytes) { | |
1411 | bytes = min(len, free->length); | |
1412 | memcpy(chip->oob_poi + free->offset, oob, bytes); | |
1413 | oob += bytes; | |
1414 | } | |
1415 | return oob; | |
1416 | } | |
1417 | default: | |
1418 | BUG(); | |
1419 | } | |
1420 | return NULL; | |
1421 | } | |
1422 | ||
28318776 | 1423 | #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0 |
1da177e4 LT |
1424 | |
1425 | /** | |
8593fbc6 | 1426 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
1427 | * @mtd: MTD device structure |
1428 | * @to: offset to write to | |
8593fbc6 | 1429 | * @ops: oob operations description structure |
1da177e4 LT |
1430 | * |
1431 | * NAND write with ECC | |
1432 | */ | |
8593fbc6 TG |
1433 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
1434 | struct mtd_oob_ops *ops) | |
1da177e4 | 1435 | { |
f75e5097 | 1436 | int chipnr, realpage, page, blockmask; |
ace4dfee | 1437 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1438 | uint32_t writelen = ops->len; |
1439 | uint8_t *oob = ops->oobbuf; | |
1440 | uint8_t *buf = ops->datbuf; | |
f75e5097 | 1441 | int bytes = mtd->writesize; |
8593fbc6 | 1442 | int ret; |
1da177e4 | 1443 | |
8593fbc6 | 1444 | ops->retlen = 0; |
1da177e4 | 1445 | |
61b03bd7 | 1446 | /* reject writes, which are not page aligned */ |
8593fbc6 | 1447 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
f75e5097 TG |
1448 | printk(KERN_NOTICE "nand_write: " |
1449 | "Attempt to write not page aligned data\n"); | |
1da177e4 LT |
1450 | return -EINVAL; |
1451 | } | |
1452 | ||
8593fbc6 | 1453 | if (!writelen) |
f75e5097 | 1454 | return 0; |
1da177e4 | 1455 | |
1da177e4 LT |
1456 | /* Check, if it is write protected */ |
1457 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1458 | return -EIO; |
1da177e4 | 1459 | |
f75e5097 TG |
1460 | chipnr = (int)(to >> chip->chip_shift); |
1461 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1462 | |
f75e5097 TG |
1463 | realpage = (int)(to >> chip->page_shift); |
1464 | page = realpage & chip->pagemask; | |
1465 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1466 | ||
1467 | /* Invalidate the page cache, when we write to the cached page */ | |
1468 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 1469 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 1470 | chip->pagebuf = -1; |
61b03bd7 | 1471 | |
f75e5097 | 1472 | chip->oob_poi = chip->buffers.oobwbuf; |
61b03bd7 | 1473 | |
f75e5097 TG |
1474 | while(1) { |
1475 | int cached = writelen > bytes && page != blockmask; | |
1da177e4 | 1476 | |
8593fbc6 TG |
1477 | if (unlikely(oob)) |
1478 | oob = nand_fill_oob(chip, oob, ops); | |
1479 | ||
f75e5097 TG |
1480 | ret = nand_write_page(mtd, chip, buf, page, cached); |
1481 | if (ret) | |
1482 | break; | |
1483 | ||
1484 | writelen -= bytes; | |
1485 | if (!writelen) | |
1486 | break; | |
1487 | ||
1488 | buf += bytes; | |
1489 | realpage++; | |
1490 | ||
1491 | page = realpage & chip->pagemask; | |
1492 | /* Check, if we cross a chip boundary */ | |
1493 | if (!page) { | |
1494 | chipnr++; | |
1495 | chip->select_chip(mtd, -1); | |
1496 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1497 | } |
1498 | } | |
8593fbc6 TG |
1499 | |
1500 | if (unlikely(oob)) | |
1501 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1502 | ||
1503 | ops->retlen = ops->len - writelen; | |
1da177e4 LT |
1504 | return ret; |
1505 | } | |
1506 | ||
f75e5097 | 1507 | /** |
8593fbc6 | 1508 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 1509 | * @mtd: MTD device structure |
f75e5097 TG |
1510 | * @to: offset to write to |
1511 | * @len: number of bytes to write | |
8593fbc6 TG |
1512 | * @retlen: pointer to variable to store the number of written bytes |
1513 | * @buf: the data to write | |
f75e5097 | 1514 | * |
8593fbc6 | 1515 | * NAND write with ECC |
f75e5097 | 1516 | */ |
8593fbc6 TG |
1517 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1518 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
1519 | { |
1520 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
1521 | int ret; |
1522 | ||
8593fbc6 TG |
1523 | /* Do not allow reads past end of device */ |
1524 | if ((to + len) > mtd->size) | |
f75e5097 | 1525 | return -EINVAL; |
8593fbc6 TG |
1526 | if (!len) |
1527 | return 0; | |
f75e5097 | 1528 | |
8593fbc6 | 1529 | nand_get_device(chip, mtd, FL_READING); |
f75e5097 | 1530 | |
8593fbc6 TG |
1531 | chip->ops.len = len; |
1532 | chip->ops.datbuf = (uint8_t *)buf; | |
1533 | chip->ops.oobbuf = NULL; | |
f75e5097 | 1534 | |
8593fbc6 | 1535 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 1536 | |
f75e5097 | 1537 | nand_release_device(mtd); |
8593fbc6 TG |
1538 | |
1539 | *retlen = chip->ops.retlen; | |
1540 | return ret; | |
f75e5097 | 1541 | } |
7314e9e7 | 1542 | |
1da177e4 | 1543 | /** |
8593fbc6 | 1544 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
1545 | * @mtd: MTD device structure |
1546 | * @to: offset to write to | |
8593fbc6 | 1547 | * @ops: oob operation description structure |
1da177e4 LT |
1548 | * |
1549 | * NAND write out-of-band | |
1550 | */ | |
8593fbc6 TG |
1551 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
1552 | struct mtd_oob_ops *ops) | |
1da177e4 | 1553 | { |
8593fbc6 | 1554 | int chipnr, page, status; |
ace4dfee | 1555 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1556 | |
7314e9e7 | 1557 | DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", |
8593fbc6 | 1558 | (unsigned int)to, (int)ops->len); |
1da177e4 LT |
1559 | |
1560 | /* Do not allow write past end of page */ | |
8593fbc6 | 1561 | if ((ops->ooboffs + ops->len) > mtd->oobsize) { |
7314e9e7 TG |
1562 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1563 | "Attempt to write past end of page\n"); | |
1da177e4 LT |
1564 | return -EINVAL; |
1565 | } | |
1566 | ||
7314e9e7 | 1567 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 1568 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1569 | |
7314e9e7 TG |
1570 | /* Shift to get page */ |
1571 | page = (int)(to >> chip->page_shift); | |
1572 | ||
1573 | /* | |
1574 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
1575 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
1576 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
1577 | * it in the doc2000 driver in August 1999. dwmw2. | |
1578 | */ | |
ace4dfee | 1579 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
1580 | |
1581 | /* Check, if it is write protected */ | |
1582 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1583 | return -EROFS; |
61b03bd7 | 1584 | |
1da177e4 | 1585 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
1586 | if (page == chip->pagebuf) |
1587 | chip->pagebuf = -1; | |
1da177e4 | 1588 | |
8593fbc6 TG |
1589 | if (ops->mode == MTD_OOB_AUTO || NAND_MUST_PAD(chip)) { |
1590 | chip->oob_poi = chip->buffers.oobwbuf; | |
1591 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1592 | nand_fill_oob(chip, ops->oobbuf, ops); | |
7314e9e7 TG |
1593 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, |
1594 | page & chip->pagemask); | |
8593fbc6 TG |
1595 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
1596 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 1597 | } else { |
8593fbc6 TG |
1598 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, |
1599 | mtd->writesize + ops->ooboffs, | |
7314e9e7 | 1600 | page & chip->pagemask); |
8593fbc6 | 1601 | chip->write_buf(mtd, ops->oobbuf, ops->len); |
1da177e4 | 1602 | } |
8593fbc6 | 1603 | |
1da177e4 | 1604 | /* Send command to program the OOB data */ |
ace4dfee | 1605 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
1da177e4 | 1606 | |
ace4dfee | 1607 | status = chip->waitfunc(mtd, chip, FL_WRITING); |
1da177e4 LT |
1608 | |
1609 | /* See if device thinks it succeeded */ | |
a4ab4c5d | 1610 | if (status & NAND_STATUS_FAIL) { |
7314e9e7 TG |
1611 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1612 | "Failed write, page 0x%08x\n", page); | |
8593fbc6 | 1613 | return -EIO; |
1da177e4 | 1614 | } |
8593fbc6 | 1615 | ops->retlen = ops->len; |
1da177e4 LT |
1616 | |
1617 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
8593fbc6 TG |
1618 | if (ops->mode != MTD_OOB_AUTO) { |
1619 | /* Send command to read back the data */ | |
1620 | chip->cmdfunc(mtd, NAND_CMD_READOOB, ops->ooboffs, | |
1621 | page & chip->pagemask); | |
1da177e4 | 1622 | |
8593fbc6 TG |
1623 | if (chip->verify_buf(mtd, ops->oobbuf, ops->len)) { |
1624 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " | |
1625 | "Failed write verify, page 0x%08x\n", page); | |
1626 | return -EIO; | |
1627 | } | |
1da177e4 LT |
1628 | } |
1629 | #endif | |
8593fbc6 TG |
1630 | return 0; |
1631 | } | |
1632 | ||
1633 | /** | |
1634 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1635 | * @mtd: MTD device structure | |
1636 | * @from: offset to read from | |
1637 | * @ops: oob operation description structure | |
1638 | */ | |
1639 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
1640 | struct mtd_oob_ops *ops) | |
1641 | { | |
1642 | void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, | |
1643 | const uint8_t *buf) = NULL; | |
1644 | struct nand_chip *chip = mtd->priv; | |
1645 | int ret = -ENOTSUPP; | |
1646 | ||
1647 | ops->retlen = 0; | |
1648 | ||
1649 | /* Do not allow writes past end of device */ | |
1650 | if ((to + ops->len) > mtd->size) { | |
1651 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1652 | "Attempt read beyond end of device\n"); | |
1653 | return -EINVAL; | |
1654 | } | |
1655 | ||
1656 | nand_get_device(chip, mtd, FL_READING); | |
1657 | ||
1658 | switch(ops->mode) { | |
1659 | case MTD_OOB_PLACE: | |
1660 | case MTD_OOB_AUTO: | |
1661 | break; | |
1662 | ||
1663 | case MTD_OOB_RAW: | |
1664 | /* Replace the write_page algorithm temporary */ | |
1665 | write_page = chip->ecc.write_page; | |
1666 | chip->ecc.write_page = nand_write_page_raw; | |
1667 | break; | |
1668 | ||
1669 | default: | |
1670 | goto out; | |
1671 | } | |
1672 | ||
1673 | if (!ops->datbuf) | |
1674 | ret = nand_do_write_oob(mtd, to, ops); | |
1675 | else | |
1676 | ret = nand_do_write_ops(mtd, to, ops); | |
1677 | ||
1678 | if (unlikely(ops->mode == MTD_OOB_RAW)) | |
1679 | chip->ecc.write_page = write_page; | |
e0c7d767 | 1680 | out: |
1da177e4 | 1681 | nand_release_device(mtd); |
1da177e4 LT |
1682 | return ret; |
1683 | } | |
1684 | ||
1da177e4 LT |
1685 | /** |
1686 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
1687 | * @mtd: MTD device structure | |
1688 | * @page: the page address of the block which will be erased | |
1689 | * | |
1690 | * Standard erase command for NAND chips | |
1691 | */ | |
e0c7d767 | 1692 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1693 | { |
ace4dfee | 1694 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1695 | /* Send commands to erase a block */ |
ace4dfee TG |
1696 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
1697 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1698 | } |
1699 | ||
1700 | /** | |
1701 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
1702 | * @mtd: MTD device structure | |
1703 | * @page: the page address of the block which will be erased | |
1704 | * | |
1705 | * AND multi block erase command function | |
1706 | * Erase 4 consecutive blocks | |
1707 | */ | |
e0c7d767 | 1708 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1709 | { |
ace4dfee | 1710 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1711 | /* Send commands to erase a block */ |
ace4dfee TG |
1712 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
1713 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1714 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1715 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
1716 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1717 | } |
1718 | ||
1719 | /** | |
1720 | * nand_erase - [MTD Interface] erase block(s) | |
1721 | * @mtd: MTD device structure | |
1722 | * @instr: erase instruction | |
1723 | * | |
1724 | * Erase one ore more blocks | |
1725 | */ | |
e0c7d767 | 1726 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 1727 | { |
e0c7d767 | 1728 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 1729 | } |
61b03bd7 | 1730 | |
30f464b7 | 1731 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 1732 | /** |
ace4dfee | 1733 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
1734 | * @mtd: MTD device structure |
1735 | * @instr: erase instruction | |
1736 | * @allowbbt: allow erasing the bbt area | |
1737 | * | |
1738 | * Erase one ore more blocks | |
1739 | */ | |
ace4dfee TG |
1740 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
1741 | int allowbbt) | |
1da177e4 LT |
1742 | { |
1743 | int page, len, status, pages_per_block, ret, chipnr; | |
ace4dfee TG |
1744 | struct nand_chip *chip = mtd->priv; |
1745 | int rewrite_bbt[NAND_MAX_CHIPS]={0}; | |
1746 | unsigned int bbt_masked_page = 0xffffffff; | |
1da177e4 | 1747 | |
ace4dfee TG |
1748 | DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", |
1749 | (unsigned int)instr->addr, (unsigned int)instr->len); | |
1da177e4 LT |
1750 | |
1751 | /* Start address must align on block boundary */ | |
ace4dfee | 1752 | if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { |
e0c7d767 | 1753 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); |
1da177e4 LT |
1754 | return -EINVAL; |
1755 | } | |
1756 | ||
1757 | /* Length must align on block boundary */ | |
ace4dfee TG |
1758 | if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { |
1759 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " | |
1760 | "Length not block aligned\n"); | |
1da177e4 LT |
1761 | return -EINVAL; |
1762 | } | |
1763 | ||
1764 | /* Do not allow erase past end of device */ | |
1765 | if ((instr->len + instr->addr) > mtd->size) { | |
ace4dfee TG |
1766 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1767 | "Erase past end of device\n"); | |
1da177e4 LT |
1768 | return -EINVAL; |
1769 | } | |
1770 | ||
1771 | instr->fail_addr = 0xffffffff; | |
1772 | ||
1773 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1774 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
1775 | |
1776 | /* Shift to get first page */ | |
ace4dfee TG |
1777 | page = (int)(instr->addr >> chip->page_shift); |
1778 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
1779 | |
1780 | /* Calculate pages in each block */ | |
ace4dfee | 1781 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
1782 | |
1783 | /* Select the NAND device */ | |
ace4dfee | 1784 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1785 | |
1da177e4 LT |
1786 | /* Check, if it is write protected */ |
1787 | if (nand_check_wp(mtd)) { | |
ace4dfee TG |
1788 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1789 | "Device is write protected!!!\n"); | |
1da177e4 LT |
1790 | instr->state = MTD_ERASE_FAILED; |
1791 | goto erase_exit; | |
1792 | } | |
1793 | ||
ace4dfee TG |
1794 | /* |
1795 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
1796 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
1797 | * can not be matched. This is also done when the bbt is actually | |
1798 | * erased to avoid recusrsive updates | |
1799 | */ | |
1800 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
1801 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 1802 | |
1da177e4 LT |
1803 | /* Loop through the pages */ |
1804 | len = instr->len; | |
1805 | ||
1806 | instr->state = MTD_ERASING; | |
1807 | ||
1808 | while (len) { | |
ace4dfee TG |
1809 | /* |
1810 | * heck if we have a bad block, we do not erase bad blocks ! | |
1811 | */ | |
1812 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
1813 | chip->page_shift, 0, allowbbt)) { | |
1814 | printk(KERN_WARNING "nand_erase: attempt to erase a " | |
1815 | "bad block at page 0x%08x\n", page); | |
1da177e4 LT |
1816 | instr->state = MTD_ERASE_FAILED; |
1817 | goto erase_exit; | |
1818 | } | |
61b03bd7 | 1819 | |
ace4dfee TG |
1820 | /* |
1821 | * Invalidate the page cache, if we erase the block which | |
1822 | * contains the current cached page | |
1823 | */ | |
1824 | if (page <= chip->pagebuf && chip->pagebuf < | |
1825 | (page + pages_per_block)) | |
1826 | chip->pagebuf = -1; | |
1da177e4 | 1827 | |
ace4dfee | 1828 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 1829 | |
ace4dfee | 1830 | status = chip->waitfunc(mtd, chip, FL_ERASING); |
1da177e4 | 1831 | |
ace4dfee TG |
1832 | /* |
1833 | * See if operation failed and additional status checks are | |
1834 | * available | |
1835 | */ | |
1836 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1837 | status = chip->errstat(mtd, chip, FL_ERASING, | |
1838 | status, page); | |
068e3c0a | 1839 | |
1da177e4 | 1840 | /* See if block erase succeeded */ |
a4ab4c5d | 1841 | if (status & NAND_STATUS_FAIL) { |
ace4dfee TG |
1842 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1843 | "Failed erase, page 0x%08x\n", page); | |
1da177e4 | 1844 | instr->state = MTD_ERASE_FAILED; |
ace4dfee | 1845 | instr->fail_addr = (page << chip->page_shift); |
1da177e4 LT |
1846 | goto erase_exit; |
1847 | } | |
30f464b7 | 1848 | |
ace4dfee TG |
1849 | /* |
1850 | * If BBT requires refresh, set the BBT rewrite flag to the | |
1851 | * page being erased | |
1852 | */ | |
1853 | if (bbt_masked_page != 0xffffffff && | |
1854 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
1855 | rewrite_bbt[chipnr] = (page << chip->page_shift); | |
61b03bd7 | 1856 | |
1da177e4 | 1857 | /* Increment page address and decrement length */ |
ace4dfee | 1858 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
1859 | page += pages_per_block; |
1860 | ||
1861 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 1862 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 1863 | chipnr++; |
ace4dfee TG |
1864 | chip->select_chip(mtd, -1); |
1865 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 1866 | |
ace4dfee TG |
1867 | /* |
1868 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
1869 | * page mask to see if this BBT should be rewritten | |
1870 | */ | |
1871 | if (bbt_masked_page != 0xffffffff && | |
1872 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
1873 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
1874 | BBT_PAGE_MASK; | |
1da177e4 LT |
1875 | } |
1876 | } | |
1877 | instr->state = MTD_ERASE_DONE; | |
1878 | ||
e0c7d767 | 1879 | erase_exit: |
1da177e4 LT |
1880 | |
1881 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1882 | /* Do call back function */ | |
1883 | if (!ret) | |
1884 | mtd_erase_callback(instr); | |
1885 | ||
1886 | /* Deselect and wake up anyone waiting on the device */ | |
1887 | nand_release_device(mtd); | |
1888 | ||
ace4dfee TG |
1889 | /* |
1890 | * If BBT requires refresh and erase was successful, rewrite any | |
1891 | * selected bad block tables | |
1892 | */ | |
1893 | if (bbt_masked_page == 0xffffffff || ret) | |
1894 | return ret; | |
1895 | ||
1896 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
1897 | if (!rewrite_bbt[chipnr]) | |
1898 | continue; | |
1899 | /* update the BBT for chip */ | |
1900 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " | |
1901 | "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], | |
1902 | chip->bbt_td->pages[chipnr]); | |
1903 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); | |
30f464b7 DM |
1904 | } |
1905 | ||
1da177e4 LT |
1906 | /* Return more or less happy */ |
1907 | return ret; | |
1908 | } | |
1909 | ||
1910 | /** | |
1911 | * nand_sync - [MTD Interface] sync | |
1912 | * @mtd: MTD device structure | |
1913 | * | |
1914 | * Sync is actually a wait for chip ready function | |
1915 | */ | |
e0c7d767 | 1916 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 1917 | { |
ace4dfee | 1918 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1919 | |
e0c7d767 | 1920 | DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); |
1da177e4 LT |
1921 | |
1922 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1923 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 1924 | /* Release it and go back */ |
e0c7d767 | 1925 | nand_release_device(mtd); |
1da177e4 LT |
1926 | } |
1927 | ||
1da177e4 | 1928 | /** |
ace4dfee | 1929 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 LT |
1930 | * @mtd: MTD device structure |
1931 | * @ofs: offset relative to mtd start | |
1932 | */ | |
ace4dfee | 1933 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
1934 | { |
1935 | /* Check for invalid offset */ | |
ace4dfee | 1936 | if (offs > mtd->size) |
1da177e4 | 1937 | return -EINVAL; |
61b03bd7 | 1938 | |
ace4dfee | 1939 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
1940 | } |
1941 | ||
1942 | /** | |
ace4dfee | 1943 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
1944 | * @mtd: MTD device structure |
1945 | * @ofs: offset relative to mtd start | |
1946 | */ | |
e0c7d767 | 1947 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 1948 | { |
ace4dfee | 1949 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
1950 | int ret; |
1951 | ||
e0c7d767 DW |
1952 | if ((ret = nand_block_isbad(mtd, ofs))) { |
1953 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
1954 | if (ret > 0) |
1955 | return 0; | |
e0c7d767 DW |
1956 | return ret; |
1957 | } | |
1da177e4 | 1958 | |
ace4dfee | 1959 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
1960 | } |
1961 | ||
962034f4 VW |
1962 | /** |
1963 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
1964 | * @mtd: MTD device structure | |
1965 | */ | |
1966 | static int nand_suspend(struct mtd_info *mtd) | |
1967 | { | |
ace4dfee | 1968 | struct nand_chip *chip = mtd->priv; |
962034f4 | 1969 | |
ace4dfee | 1970 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
1971 | } |
1972 | ||
1973 | /** | |
1974 | * nand_resume - [MTD Interface] Resume the NAND flash | |
1975 | * @mtd: MTD device structure | |
1976 | */ | |
1977 | static void nand_resume(struct mtd_info *mtd) | |
1978 | { | |
ace4dfee | 1979 | struct nand_chip *chip = mtd->priv; |
962034f4 | 1980 | |
ace4dfee | 1981 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
1982 | nand_release_device(mtd); |
1983 | else | |
2c0a2bed TG |
1984 | printk(KERN_ERR "nand_resume() called for a chip which is not " |
1985 | "in suspended state\n"); | |
962034f4 VW |
1986 | } |
1987 | ||
7aa65bfd TG |
1988 | /* |
1989 | * Set default functions | |
1990 | */ | |
ace4dfee | 1991 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 1992 | { |
1da177e4 | 1993 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
1994 | if (!chip->chip_delay) |
1995 | chip->chip_delay = 20; | |
1da177e4 LT |
1996 | |
1997 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
1998 | if (chip->cmdfunc == NULL) |
1999 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2000 | |
2001 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2002 | if (chip->waitfunc == NULL) |
2003 | chip->waitfunc = nand_wait; | |
2004 | ||
2005 | if (!chip->select_chip) | |
2006 | chip->select_chip = nand_select_chip; | |
2007 | if (!chip->read_byte) | |
2008 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2009 | if (!chip->read_word) | |
2010 | chip->read_word = nand_read_word; | |
2011 | if (!chip->block_bad) | |
2012 | chip->block_bad = nand_block_bad; | |
2013 | if (!chip->block_markbad) | |
2014 | chip->block_markbad = nand_default_block_markbad; | |
2015 | if (!chip->write_buf) | |
2016 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2017 | if (!chip->read_buf) | |
2018 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2019 | if (!chip->verify_buf) | |
2020 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2021 | if (!chip->scan_bbt) | |
2022 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2023 | |
2024 | if (!chip->controller) { | |
2025 | chip->controller = &chip->hwcontrol; | |
2026 | spin_lock_init(&chip->controller->lock); | |
2027 | init_waitqueue_head(&chip->controller->wq); | |
2028 | } | |
2029 | ||
7aa65bfd TG |
2030 | } |
2031 | ||
2032 | /* | |
ace4dfee | 2033 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2034 | */ |
2035 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2036 | struct nand_chip *chip, |
7aa65bfd TG |
2037 | int busw, int *maf_id) |
2038 | { | |
2039 | struct nand_flash_dev *type = NULL; | |
2040 | int i, dev_id, maf_idx; | |
1da177e4 LT |
2041 | |
2042 | /* Select the device */ | |
ace4dfee | 2043 | chip->select_chip(mtd, 0); |
1da177e4 LT |
2044 | |
2045 | /* Send the command for reading device ID */ | |
ace4dfee | 2046 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2047 | |
2048 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2049 | *maf_id = chip->read_byte(mtd); |
2050 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2051 | |
7aa65bfd | 2052 | /* Lookup the flash id */ |
1da177e4 | 2053 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
7aa65bfd TG |
2054 | if (dev_id == nand_flash_ids[i].id) { |
2055 | type = &nand_flash_ids[i]; | |
2056 | break; | |
2057 | } | |
2058 | } | |
61b03bd7 | 2059 | |
7aa65bfd TG |
2060 | if (!type) |
2061 | return ERR_PTR(-ENODEV); | |
2062 | ||
ba0251fe TG |
2063 | if (!mtd->name) |
2064 | mtd->name = type->name; | |
2065 | ||
2066 | chip->chipsize = type->chipsize << 20; | |
7aa65bfd TG |
2067 | |
2068 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2069 | if (!type->pagesize) { |
7aa65bfd TG |
2070 | int extid; |
2071 | /* The 3rd id byte contains non relevant data ATM */ | |
ace4dfee | 2072 | extid = chip->read_byte(mtd); |
7aa65bfd | 2073 | /* The 4th id byte is the important one */ |
ace4dfee | 2074 | extid = chip->read_byte(mtd); |
7aa65bfd | 2075 | /* Calc pagesize */ |
4cbb9b80 | 2076 | mtd->writesize = 1024 << (extid & 0x3); |
7aa65bfd TG |
2077 | extid >>= 2; |
2078 | /* Calc oobsize */ | |
4cbb9b80 | 2079 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
7aa65bfd TG |
2080 | extid >>= 2; |
2081 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2082 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2083 | extid >>= 2; | |
2084 | /* Get buswidth information */ | |
2085 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
61b03bd7 | 2086 | |
7aa65bfd TG |
2087 | } else { |
2088 | /* | |
ace4dfee | 2089 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2090 | */ |
ba0251fe TG |
2091 | mtd->erasesize = type->erasesize; |
2092 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2093 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2094 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2095 | } |
1da177e4 | 2096 | |
7aa65bfd TG |
2097 | /* Try to identify manufacturer */ |
2098 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) { | |
2099 | if (nand_manuf_ids[maf_idx].id == *maf_id) | |
2100 | break; | |
2101 | } | |
0ea4a755 | 2102 | |
7aa65bfd TG |
2103 | /* |
2104 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2105 | * chip correct ! |
7aa65bfd | 2106 | */ |
ace4dfee | 2107 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2108 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2109 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2110 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2111 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2112 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2113 | busw ? 16 : 8); |
2114 | return ERR_PTR(-EINVAL); | |
2115 | } | |
61b03bd7 | 2116 | |
7aa65bfd | 2117 | /* Calculate the address shift from the page size */ |
ace4dfee | 2118 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2119 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2120 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2121 | |
ace4dfee | 2122 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2123 | ffs(mtd->erasesize) - 1; |
ace4dfee | 2124 | chip->chip_shift = ffs(chip->chipsize) - 1; |
1da177e4 | 2125 | |
7aa65bfd | 2126 | /* Set the bad block position */ |
ace4dfee | 2127 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2128 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
61b03bd7 | 2129 | |
7aa65bfd | 2130 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2131 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2132 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2133 | |
2134 | /* | |
ace4dfee | 2135 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2136 | */ |
ace4dfee | 2137 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2138 | |
ace4dfee | 2139 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2140 | * options for chips which are not having an extended id. |
2141 | */ | |
ba0251fe | 2142 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2143 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2144 | |
2145 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2146 | if (chip->options & NAND_4PAGE_ARRAY) |
2147 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2148 | else |
ace4dfee | 2149 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2150 | |
2151 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2152 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2153 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2154 | |
2155 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2156 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2157 | nand_manuf_ids[maf_idx].name, type->name); | |
2158 | ||
2159 | return type; | |
2160 | } | |
2161 | ||
2162 | /* module_text_address() isn't exported, and it's mostly a pointless | |
2163 | test if this is a module _anyway_ -- they'd have to try _really_ hard | |
2164 | to call us from in-kernel code if the core NAND support is modular. */ | |
2165 | #ifdef MODULE | |
2166 | #define caller_is_module() (1) | |
2167 | #else | |
2168 | #define caller_is_module() \ | |
2169 | module_text_address((unsigned long)__builtin_return_address(0)) | |
2170 | #endif | |
2171 | ||
2172 | /** | |
2173 | * nand_scan - [NAND Interface] Scan for the NAND device | |
2174 | * @mtd: MTD device structure | |
2175 | * @maxchips: Number of chips to scan for | |
2176 | * | |
2177 | * This fills out all the uninitialized function pointers | |
2178 | * with the defaults. | |
2179 | * The flash ID is read and the mtd/chip structures are | |
f75e5097 | 2180 | * filled with the appropriate values. |
7aa65bfd TG |
2181 | * The mtd->owner field must be set to the module of the caller |
2182 | * | |
2183 | */ | |
2184 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
2185 | { | |
2186 | int i, busw, nand_maf_id; | |
ace4dfee | 2187 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2188 | struct nand_flash_dev *type; |
2189 | ||
2190 | /* Many callers got this wrong, so check for it for a while... */ | |
2191 | if (!mtd->owner && caller_is_module()) { | |
2192 | printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); | |
2193 | BUG(); | |
1da177e4 LT |
2194 | } |
2195 | ||
7aa65bfd | 2196 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2197 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2198 | /* Set the default functions */ |
ace4dfee | 2199 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2200 | |
2201 | /* Read the flash type */ | |
ace4dfee | 2202 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
7aa65bfd TG |
2203 | |
2204 | if (IS_ERR(type)) { | |
e0c7d767 | 2205 | printk(KERN_WARNING "No NAND device found!!!\n"); |
ace4dfee | 2206 | chip->select_chip(mtd, -1); |
7aa65bfd | 2207 | return PTR_ERR(type); |
1da177e4 LT |
2208 | } |
2209 | ||
7aa65bfd | 2210 | /* Check for a chip array */ |
e0c7d767 | 2211 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2212 | chip->select_chip(mtd, i); |
1da177e4 | 2213 | /* Send the command for reading device ID */ |
ace4dfee | 2214 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2215 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2216 | if (nand_maf_id != chip->read_byte(mtd) || |
2217 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2218 | break; |
2219 | } | |
2220 | if (i > 1) | |
2221 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 2222 | |
1da177e4 | 2223 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
2224 | chip->numchips = i; |
2225 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 2226 | |
f75e5097 TG |
2227 | /* Preset the internal oob write buffer */ |
2228 | memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize); | |
1da177e4 | 2229 | |
7aa65bfd TG |
2230 | /* |
2231 | * If no default placement scheme is given, select an appropriate one | |
2232 | */ | |
5bd34c09 | 2233 | if (!chip->ecc.layout) { |
61b03bd7 | 2234 | switch (mtd->oobsize) { |
1da177e4 | 2235 | case 8: |
5bd34c09 | 2236 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
2237 | break; |
2238 | case 16: | |
5bd34c09 | 2239 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
2240 | break; |
2241 | case 64: | |
5bd34c09 | 2242 | chip->ecc.layout = &nand_oob_64; |
1da177e4 LT |
2243 | break; |
2244 | default: | |
7aa65bfd TG |
2245 | printk(KERN_WARNING "No oob scheme defined for " |
2246 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
2247 | BUG(); |
2248 | } | |
2249 | } | |
61b03bd7 | 2250 | |
61b03bd7 | 2251 | /* |
7aa65bfd TG |
2252 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
2253 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 2254 | */ |
ace4dfee | 2255 | switch (chip->ecc.mode) { |
6dfc6d25 | 2256 | case NAND_ECC_HW: |
f5bbdacc TG |
2257 | /* Use standard hwecc read page function ? */ |
2258 | if (!chip->ecc.read_page) | |
2259 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
2260 | if (!chip->ecc.write_page) |
2261 | chip->ecc.write_page = nand_write_page_hwecc; | |
f5bbdacc | 2262 | |
6dfc6d25 | 2263 | case NAND_ECC_HW_SYNDROME: |
ace4dfee TG |
2264 | if (!chip->ecc.calculate || !chip->ecc.correct || |
2265 | !chip->ecc.hwctl) { | |
6dfc6d25 TG |
2266 | printk(KERN_WARNING "No ECC functions supplied, " |
2267 | "Hardware ECC not possible\n"); | |
2268 | BUG(); | |
2269 | } | |
f75e5097 | 2270 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
2271 | if (!chip->ecc.read_page) |
2272 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
2273 | if (!chip->ecc.write_page) |
2274 | chip->ecc.write_page = nand_write_page_syndrome; | |
f5bbdacc | 2275 | |
ace4dfee | 2276 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
2277 | break; |
2278 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
2279 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
2280 | chip->ecc.size, mtd->writesize); |
2281 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 2282 | |
6dfc6d25 | 2283 | case NAND_ECC_SOFT: |
ace4dfee TG |
2284 | chip->ecc.calculate = nand_calculate_ecc; |
2285 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 2286 | chip->ecc.read_page = nand_read_page_swecc; |
f75e5097 | 2287 | chip->ecc.write_page = nand_write_page_swecc; |
ace4dfee TG |
2288 | chip->ecc.size = 256; |
2289 | chip->ecc.bytes = 3; | |
1da177e4 | 2290 | break; |
61b03bd7 TG |
2291 | |
2292 | case NAND_ECC_NONE: | |
7aa65bfd TG |
2293 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
2294 | "This is not recommended !!\n"); | |
8593fbc6 TG |
2295 | chip->ecc.read_page = nand_read_page_raw; |
2296 | chip->ecc.write_page = nand_write_page_raw; | |
ace4dfee TG |
2297 | chip->ecc.size = mtd->writesize; |
2298 | chip->ecc.bytes = 0; | |
1da177e4 | 2299 | break; |
1da177e4 | 2300 | default: |
7aa65bfd | 2301 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 2302 | chip->ecc.mode); |
61b03bd7 | 2303 | BUG(); |
1da177e4 | 2304 | } |
61b03bd7 | 2305 | |
5bd34c09 TG |
2306 | /* |
2307 | * The number of bytes available for a client to place data into | |
2308 | * the out of band area | |
2309 | */ | |
2310 | chip->ecc.layout->oobavail = 0; | |
2311 | for (i = 0; chip->ecc.layout->oobfree[i].length; i++) | |
2312 | chip->ecc.layout->oobavail += | |
2313 | chip->ecc.layout->oobfree[i].length; | |
2314 | ||
7aa65bfd TG |
2315 | /* |
2316 | * Set the number of read / write steps for one page depending on ECC | |
2317 | * mode | |
2318 | */ | |
ace4dfee TG |
2319 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
2320 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
2321 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
2322 | BUG(); | |
1da177e4 | 2323 | } |
f5bbdacc | 2324 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 2325 | |
04bbd0ea | 2326 | /* Initialize state */ |
ace4dfee | 2327 | chip->state = FL_READY; |
1da177e4 LT |
2328 | |
2329 | /* De-select the device */ | |
ace4dfee | 2330 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2331 | |
2332 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 2333 | chip->pagebuf = -1; |
1da177e4 LT |
2334 | |
2335 | /* Fill in remaining MTD driver data */ | |
2336 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2337 | mtd->flags = MTD_CAP_NANDFLASH; |
1da177e4 LT |
2338 | mtd->ecctype = MTD_ECC_SW; |
2339 | mtd->erase = nand_erase; | |
2340 | mtd->point = NULL; | |
2341 | mtd->unpoint = NULL; | |
2342 | mtd->read = nand_read; | |
2343 | mtd->write = nand_write; | |
1da177e4 LT |
2344 | mtd->read_oob = nand_read_oob; |
2345 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
2346 | mtd->sync = nand_sync; |
2347 | mtd->lock = NULL; | |
2348 | mtd->unlock = NULL; | |
962034f4 VW |
2349 | mtd->suspend = nand_suspend; |
2350 | mtd->resume = nand_resume; | |
1da177e4 LT |
2351 | mtd->block_isbad = nand_block_isbad; |
2352 | mtd->block_markbad = nand_block_markbad; | |
2353 | ||
5bd34c09 TG |
2354 | /* propagate ecc.layout to mtd_info */ |
2355 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 2356 | |
0040bf38 | 2357 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 2358 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 2359 | return 0; |
1da177e4 LT |
2360 | |
2361 | /* Build bad block table */ | |
ace4dfee | 2362 | return chip->scan_bbt(mtd); |
1da177e4 LT |
2363 | } |
2364 | ||
2365 | /** | |
61b03bd7 | 2366 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
2367 | * @mtd: MTD device structure |
2368 | */ | |
e0c7d767 | 2369 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 2370 | { |
ace4dfee | 2371 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2372 | |
2373 | #ifdef CONFIG_MTD_PARTITIONS | |
2374 | /* Deregister partitions */ | |
e0c7d767 | 2375 | del_mtd_partitions(mtd); |
1da177e4 LT |
2376 | #endif |
2377 | /* Deregister the device */ | |
e0c7d767 | 2378 | del_mtd_device(mtd); |
1da177e4 | 2379 | |
fa671646 | 2380 | /* Free bad block table memory */ |
ace4dfee | 2381 | kfree(chip->bbt); |
1da177e4 LT |
2382 | } |
2383 | ||
e0c7d767 DW |
2384 | EXPORT_SYMBOL_GPL(nand_scan); |
2385 | EXPORT_SYMBOL_GPL(nand_release); | |
8fe833c1 RP |
2386 | |
2387 | static int __init nand_base_init(void) | |
2388 | { | |
2389 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
2390 | return 0; | |
2391 | } | |
2392 | ||
2393 | static void __exit nand_base_exit(void) | |
2394 | { | |
2395 | led_trigger_unregister_simple(nand_led_trigger); | |
2396 | } | |
2397 | ||
2398 | module_init(nand_base_init); | |
2399 | module_exit(nand_base_exit); | |
2400 | ||
e0c7d767 DW |
2401 | MODULE_LICENSE("GPL"); |
2402 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
2403 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |