]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/mtd/nand/nand_base.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[MTD] [NAND] fix "raw" reads with ECC syndrome layouts
[net-next-2.6.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/compatmac.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
1da177e4
LT		 49#include <asm/io.h>
50
51#ifdef CONFIG_MTD_PARTITIONS
52#include <linux/mtd/partitions.h>
53#endif
54
55/* Define default oob placement schemes for large and small page devices */
5bd34c09 56static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
5bd34c09
TG		 59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
1da177e4
LT		 64};
65
5bd34c09 66static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
1da177e4
LT		 72};
73
5bd34c09 74static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 75 .eccbytes = 24,
76 .eccpos = {
e0c7d767
DW		 77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
1da177e4
LT		 83};
84
ace4dfee 85static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 86 int new_state);
1da177e4 87
8593fbc6
TG		 88static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
89 struct mtd_oob_ops *ops);
90
d470a97c 91/*
8e87d782 92 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 93 * compiled away when LED support is disabled.
94 */
95DEFINE_LED_TRIGGER(nand_led_trigger);
96
1da177e4
LT		 97/**
98 * nand_release_device - [GENERIC] release chip
99 * @mtd: MTD device structure
61b03bd7
TG		 100 *
101 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 102 */
e0c7d767 103static void nand_release_device(struct mtd_info *mtd)
1da177e4 104{
ace4dfee 105 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 106
107 /* De-select the NAND device */
ace4dfee 108 chip->select_chip(mtd, -1);
0dfc6246 109
a36ed299 110 /* Release the controller and the chip */
ace4dfee
TG		 111 spin_lock(&chip->controller->lock);
112 chip->controller->active = NULL;
113 chip->state = FL_READY;
114 wake_up(&chip->controller->wq);
115 spin_unlock(&chip->controller->lock);
1da177e4
LT		 116}
117
118/**
119 * nand_read_byte - [DEFAULT] read one byte from the chip
120 * @mtd: MTD device structure
121 *
122 * Default read function for 8bit buswith
123 */
58dd8f2b 124static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 125{
ace4dfee
TG		 126 struct nand_chip *chip = mtd->priv;
127 return readb(chip->IO_ADDR_R);
1da177e4
LT		 128}
129
1da177e4
LT		 130/**
131 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
132 * @mtd: MTD device structure
133 *
61b03bd7 134 * Default read function for 16bit buswith with
1da177e4
LT		 135 * endianess conversion
136 */
58dd8f2b 137static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 138{
ace4dfee
TG		 139 struct nand_chip *chip = mtd->priv;
140 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 141}
142
1da177e4
LT		 143/**
144 * nand_read_word - [DEFAULT] read one word from the chip
145 * @mtd: MTD device structure
146 *
61b03bd7 147 * Default read function for 16bit buswith without
1da177e4
LT		 148 * endianess conversion
149 */
150static u16 nand_read_word(struct mtd_info *mtd)
151{
ace4dfee
TG		 152 struct nand_chip *chip = mtd->priv;
153 return readw(chip->IO_ADDR_R);
1da177e4
LT		 154}
155
1da177e4
LT		 156/**
157 * nand_select_chip - [DEFAULT] control CE line
158 * @mtd: MTD device structure
844d3b42 159 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 160 *
161 * Default select function for 1 chip devices.
162 */
ace4dfee 163static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 164{
ace4dfee
TG		 165 struct nand_chip *chip = mtd->priv;
166
167 switch (chipnr) {
1da177e4 168 case -1:
ace4dfee 169 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 170 break;
171 case 0:
1da177e4
LT		 172 break;
173
174 default:
175 BUG();
176 }
177}
178
179/**
180 * nand_write_buf - [DEFAULT] write buffer to chip
181 * @mtd: MTD device structure
182 * @buf: data buffer
183 * @len: number of bytes to write
184 *
185 * Default write function for 8bit buswith
186 */
58dd8f2b 187static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 188{
189 int i;
ace4dfee 190 struct nand_chip *chip = mtd->priv;
1da177e4 191
e0c7d767 192 for (i = 0; i < len; i++)
ace4dfee 193 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 194}
195
196/**
61b03bd7 197 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 198 * @mtd: MTD device structure
199 * @buf: buffer to store date
200 * @len: number of bytes to read
201 *
202 * Default read function for 8bit buswith
203 */
58dd8f2b 204static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 205{
206 int i;
ace4dfee 207 struct nand_chip *chip = mtd->priv;
1da177e4 208
e0c7d767 209 for (i = 0; i < len; i++)
ace4dfee 210 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 211}
212
213/**
61b03bd7 214 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 215 * @mtd: MTD device structure
216 * @buf: buffer containing the data to compare
217 * @len: number of bytes to compare
218 *
219 * Default verify function for 8bit buswith
220 */
58dd8f2b 221static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 222{
223 int i;
ace4dfee 224 struct nand_chip *chip = mtd->priv;
1da177e4 225
e0c7d767 226 for (i = 0; i < len; i++)
ace4dfee 227 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 228 return -EFAULT;
1da177e4
LT		 229 return 0;
230}
231
232/**
233 * nand_write_buf16 - [DEFAULT] write buffer to chip
234 * @mtd: MTD device structure
235 * @buf: data buffer
236 * @len: number of bytes to write
237 *
238 * Default write function for 16bit buswith
239 */
58dd8f2b 240static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 241{
242 int i;
ace4dfee 243 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 244 u16 *p = (u16 *) buf;
245 len >>= 1;
61b03bd7 246
e0c7d767 247 for (i = 0; i < len; i++)
ace4dfee 248 writew(p[i], chip->IO_ADDR_W);
61b03bd7 249
1da177e4
LT		 250}
251
252/**
61b03bd7 253 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 254 * @mtd: MTD device structure
255 * @buf: buffer to store date
256 * @len: number of bytes to read
257 *
258 * Default read function for 16bit buswith
259 */
58dd8f2b 260static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 261{
262 int i;
ace4dfee 263 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 264 u16 *p = (u16 *) buf;
265 len >>= 1;
266
e0c7d767 267 for (i = 0; i < len; i++)
ace4dfee 268 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 269}
270
271/**
61b03bd7 272 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 273 * @mtd: MTD device structure
274 * @buf: buffer containing the data to compare
275 * @len: number of bytes to compare
276 *
277 * Default verify function for 16bit buswith
278 */
58dd8f2b 279static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 280{
281 int i;
ace4dfee 282 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 283 u16 *p = (u16 *) buf;
284 len >>= 1;
285
e0c7d767 286 for (i = 0; i < len; i++)
ace4dfee 287 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 288 return -EFAULT;
289
290 return 0;
291}
292
293/**
294 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
295 * @mtd: MTD device structure
296 * @ofs: offset from device start
297 * @getchip: 0, if the chip is already selected
298 *
61b03bd7 299 * Check, if the block is bad.
1da177e4
LT		 300 */
301static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
302{
303 int page, chipnr, res = 0;
ace4dfee 304 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 305 u16 bad;
306
1a12f46a
TK		 307 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
308
1da177e4 309 if (getchip) {
ace4dfee 310 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 311
ace4dfee 312 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 313
314 /* Select the NAND device */
ace4dfee 315 chip->select_chip(mtd, chipnr);
1a12f46a 316 }
1da177e4 317
ace4dfee
TG		 318 if (chip->options & NAND_BUSWIDTH_16) {
319 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 320 page);
ace4dfee
TG		 321 bad = cpu_to_le16(chip->read_word(mtd));
322 if (chip->badblockpos & 0x1)
49196f33 323 bad >>= 8;
1da177e4
LT		 324 if ((bad & 0xFF) != 0xff)
325 res = 1;
326 } else {
1a12f46a 327 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
ace4dfee 328 if (chip->read_byte(mtd) != 0xff)
1da177e4
LT		 329 res = 1;
330 }
61b03bd7 331
ace4dfee 332 if (getchip)
1da177e4 333 nand_release_device(mtd);
61b03bd7 334
1da177e4
LT		 335 return res;
336}
337
338/**
339 * nand_default_block_markbad - [DEFAULT] mark a block bad
340 * @mtd: MTD device structure
341 * @ofs: offset from device start
342 *
343 * This is the default implementation, which can be overridden by
344 * a hardware specific driver.
345*/
346static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
347{
ace4dfee 348 struct nand_chip *chip = mtd->priv;
58dd8f2b 349 uint8_t buf[2] = { 0, 0 };
f1a28c02 350 int block, ret;
61b03bd7 351
1da177e4 352 /* Get block number */
4226b510 353 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 354 if (chip->bbt)
355 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 356
357 /* Do we have a flash based bad block table ? */
ace4dfee 358 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 359 ret = nand_update_bbt(mtd, ofs);
360 else {
361 /* We write two bytes, so we dont have to mess with 16 bit
362 * access
363 */
c0b8ba7b 364 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 365 ofs += mtd->oobsize;
ff0dab64 366 chip->ops.len = chip->ops.ooblen = 2;
f1a28c02
TG		 367 chip->ops.datbuf = NULL;
368 chip->ops.oobbuf = buf;
369 chip->ops.ooboffs = chip->badblockpos & ~0x01;
370
371 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
c0b8ba7b 372 nand_release_device(mtd);
f1a28c02
TG		 373 }
374 if (!ret)
375 mtd->ecc_stats.badblocks++;
c0b8ba7b 376
f1a28c02 377 return ret;
1da177e4
LT		 378}
379
61b03bd7 380/**
1da177e4
LT		 381 * nand_check_wp - [GENERIC] check if the chip is write protected
382 * @mtd: MTD device structure
61b03bd7 383 * Check, if the device is write protected
1da177e4 384 *
61b03bd7 385 * The function expects, that the device is already selected
1da177e4 386 */
e0c7d767 387static int nand_check_wp(struct mtd_info *mtd)
1da177e4 388{
ace4dfee 389 struct nand_chip *chip = mtd->priv;
1da177e4 390 /* Check the WP bit */
ace4dfee
TG		 391 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
392 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 393}
394
395/**
396 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
397 * @mtd: MTD device structure
398 * @ofs: offset from device start
399 * @getchip: 0, if the chip is already selected
400 * @allowbbt: 1, if its allowed to access the bbt area
401 *
402 * Check, if the block is bad. Either by reading the bad block table or
403 * calling of the scan function.
404 */
2c0a2bed
TG		 405static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
406 int allowbbt)
1da177e4 407{
ace4dfee 408 struct nand_chip *chip = mtd->priv;
61b03bd7 409
ace4dfee
TG		 410 if (!chip->bbt)
411 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 412
1da177e4 413 /* Return info from the table */
e0c7d767 414 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 415}
416
61b03bd7 417/*
3b88775c
TG		 418 * Wait for the ready pin, after a command
419 * The timeout is catched later.
420 */
4b648b02 421void nand_wait_ready(struct mtd_info *mtd)
3b88775c 422{
ace4dfee 423 struct nand_chip *chip = mtd->priv;
e0c7d767 424 unsigned long timeo = jiffies + 2;
3b88775c 425
8fe833c1 426 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 427 /* wait until command is processed or timeout occures */
428 do {
ace4dfee 429 if (chip->dev_ready(mtd))
8fe833c1 430 break;
8446f1d3 431 touch_softlockup_watchdog();
61b03bd7 432 } while (time_before(jiffies, timeo));
8fe833c1 433 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 434}
4b648b02 435EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 436
1da177e4
LT		 437/**
438 * nand_command - [DEFAULT] Send command to NAND device
439 * @mtd: MTD device structure
440 * @command: the command to be sent
441 * @column: the column address for this command, -1 if none
442 * @page_addr: the page address for this command, -1 if none
443 *
444 * Send command to NAND device. This function is used for small page
445 * devices (256/512 Bytes per page)
446 */
7abd3ef9
TG		 447static void nand_command(struct mtd_info *mtd, unsigned int command,
448 int column, int page_addr)
1da177e4 449{
ace4dfee 450 register struct nand_chip *chip = mtd->priv;
7abd3ef9 451 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 452
1da177e4
LT		 453 /*
454 * Write out the command to the device.
455 */
456 if (command == NAND_CMD_SEQIN) {
457 int readcmd;
458
28318776 459 if (column >= mtd->writesize) {
1da177e4 460 /* OOB area */
28318776 461 column -= mtd->writesize;
1da177e4
LT		 462 readcmd = NAND_CMD_READOOB;
463 } else if (column < 256) {
464 /* First 256 bytes --> READ0 */
465 readcmd = NAND_CMD_READ0;
466 } else {
467 column -= 256;
468 readcmd = NAND_CMD_READ1;
469 }
ace4dfee 470 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 471 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 472 }
ace4dfee 473 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 474
7abd3ef9
TG		 475 /*
476 * Address cycle, when necessary
477 */
478 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
479 /* Serially input address */
480 if (column != -1) {
481 /* Adjust columns for 16 bit buswidth */
ace4dfee 482 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 483 column >>= 1;
ace4dfee 484 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 485 ctrl &= ~NAND_CTRL_CHANGE;
486 }
487 if (page_addr != -1) {
ace4dfee 488 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 489 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 490 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 491 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 492 if (chip->chipsize > (32 << 20))
493 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 494 }
ace4dfee 495 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 496
497 /*
498 * program and erase have their own busy handlers
1da177e4 499 * status and sequential in needs no delay
e0c7d767 500 */
1da177e4 501 switch (command) {
61b03bd7 502
1da177e4
LT		 503 case NAND_CMD_PAGEPROG:
504 case NAND_CMD_ERASE1:
505 case NAND_CMD_ERASE2:
506 case NAND_CMD_SEQIN:
507 case NAND_CMD_STATUS:
508 return;
509
510 case NAND_CMD_RESET:
ace4dfee 511 if (chip->dev_ready)
1da177e4 512 break;
ace4dfee
TG		 513 udelay(chip->chip_delay);
514 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 515 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 516 chip->cmd_ctrl(mtd,
517 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 518 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 519 return;
520
e0c7d767 521 /* This applies to read commands */
1da177e4 522 default:
61b03bd7 523 /*
1da177e4
LT		 524 * If we don't have access to the busy pin, we apply the given
525 * command delay
e0c7d767 526 */
ace4dfee
TG		 527 if (!chip->dev_ready) {
528 udelay(chip->chip_delay);
1da177e4 529 return;
61b03bd7 530 }
1da177e4 531 }
1da177e4
LT		 532 /* Apply this short delay always to ensure that we do wait tWB in
533 * any case on any machine. */
e0c7d767 534 ndelay(100);
3b88775c
TG		 535
536 nand_wait_ready(mtd);
1da177e4
LT		 537}
538
539/**
540 * nand_command_lp - [DEFAULT] Send command to NAND large page device
541 * @mtd: MTD device structure
542 * @command: the command to be sent
543 * @column: the column address for this command, -1 if none
544 * @page_addr: the page address for this command, -1 if none
545 *
7abd3ef9
TG		 546 * Send command to NAND device. This is the version for the new large page
547 * devices We dont have the separate regions as we have in the small page
548 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 549 */
7abd3ef9
TG		 550static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
551 int column, int page_addr)
1da177e4 552{
ace4dfee 553 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 554
555 /* Emulate NAND_CMD_READOOB */
556 if (command == NAND_CMD_READOOB) {
28318776 557 column += mtd->writesize;
1da177e4
LT		 558 command = NAND_CMD_READ0;
559 }
61b03bd7 560
7abd3ef9 561 /* Command latch cycle */
ace4dfee 562 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 563 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 564
565 if (column != -1 || page_addr != -1) {
7abd3ef9 566 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 567
568 /* Serially input address */
569 if (column != -1) {
570 /* Adjust columns for 16 bit buswidth */
ace4dfee 571 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 572 column >>= 1;
ace4dfee 573 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 574 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 575 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 576 }
1da177e4 577 if (page_addr != -1) {
ace4dfee
TG		 578 chip->cmd_ctrl(mtd, page_addr, ctrl);
579 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 580 NAND_NCE | NAND_ALE);
1da177e4 581 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 582 if (chip->chipsize > (128 << 20))
583 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 584 NAND_NCE | NAND_ALE);
1da177e4 585 }
1da177e4 586 }
ace4dfee 587 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 588
589 /*
590 * program and erase have their own busy handlers
30f464b7
DM		 591 * status, sequential in, and deplete1 need no delay
592 */
1da177e4 593 switch (command) {
61b03bd7 594
1da177e4
LT		 595 case NAND_CMD_CACHEDPROG:
596 case NAND_CMD_PAGEPROG:
597 case NAND_CMD_ERASE1:
598 case NAND_CMD_ERASE2:
599 case NAND_CMD_SEQIN:
7bc3312b 600 case NAND_CMD_RNDIN:
1da177e4 601 case NAND_CMD_STATUS:
30f464b7 602 case NAND_CMD_DEPLETE1:
1da177e4
LT		 603 return;
604
e0c7d767
DW		 605 /*
606 * read error status commands require only a short delay
607 */
30f464b7
DM		 608 case NAND_CMD_STATUS_ERROR:
609 case NAND_CMD_STATUS_ERROR0:
610 case NAND_CMD_STATUS_ERROR1:
611 case NAND_CMD_STATUS_ERROR2:
612 case NAND_CMD_STATUS_ERROR3:
ace4dfee 613 udelay(chip->chip_delay);
30f464b7 614 return;
1da177e4
LT		 615
616 case NAND_CMD_RESET:
ace4dfee 617 if (chip->dev_ready)
1da177e4 618 break;
ace4dfee 619 udelay(chip->chip_delay);
12efdde3
TG		 620 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
621 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
622 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
623 NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 624 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 625 return;
626
7bc3312b
TG		 627 case NAND_CMD_RNDOUT:
628 /* No ready / busy check necessary */
629 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
630 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
631 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
632 NAND_NCE | NAND_CTRL_CHANGE);
633 return;
634
1da177e4 635 case NAND_CMD_READ0:
12efdde3
TG		 636 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
637 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
638 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
639 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 640
e0c7d767 641 /* This applies to read commands */
1da177e4 642 default:
61b03bd7 643 /*
1da177e4
LT		 644 * If we don't have access to the busy pin, we apply the given
645 * command delay
e0c7d767 646 */
ace4dfee
TG		 647 if (!chip->dev_ready) {
648 udelay(chip->chip_delay);
1da177e4 649 return;
61b03bd7 650 }
1da177e4 651 }
3b88775c 652
1da177e4
LT		 653 /* Apply this short delay always to ensure that we do wait tWB in
654 * any case on any machine. */
e0c7d767 655 ndelay(100);
3b88775c
TG		 656
657 nand_wait_ready(mtd);
1da177e4
LT		 658}
659
660/**
661 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 662 * @chip: the nand chip descriptor
1da177e4 663 * @mtd: MTD device structure
61b03bd7 664 * @new_state: the state which is requested
1da177e4
LT		 665 *
666 * Get the device and lock it for exclusive access
667 */
2c0a2bed 668static int
ace4dfee 669nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 670{
ace4dfee
TG		 671 spinlock_t *lock = &chip->controller->lock;
672 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 673 DECLARE_WAITQUEUE(wait, current);
e0c7d767 674 retry:
0dfc6246
TG		 675 spin_lock(lock);
676
1da177e4 677 /* Hardware controller shared among independend devices */
a36ed299 678 /* Hardware controller shared among independend devices */
ace4dfee
TG		 679 if (!chip->controller->active)
680 chip->controller->active = chip;
a36ed299 681
ace4dfee
TG		 682 if (chip->controller->active == chip && chip->state == FL_READY) {
683 chip->state = new_state;
0dfc6246 684 spin_unlock(lock);
962034f4
VW		 685 return 0;
686 }
687 if (new_state == FL_PM_SUSPENDED) {
688 spin_unlock(lock);
ace4dfee 689 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
0dfc6246
TG		 690 }
691 set_current_state(TASK_UNINTERRUPTIBLE);
692 add_wait_queue(wq, &wait);
693 spin_unlock(lock);
694 schedule();
695 remove_wait_queue(wq, &wait);
1da177e4
LT		 696 goto retry;
697}
698
699/**
700 * nand_wait - [DEFAULT] wait until the command is done
701 * @mtd: MTD device structure
844d3b42 702 * @chip: NAND chip structure
1da177e4
LT		 703 *
704 * Wait for command done. This applies to erase and program only
61b03bd7 705 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 706 * general NAND and SmartMedia specs
844d3b42 707 */
7bc3312b 708static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 709{
710
e0c7d767 711 unsigned long timeo = jiffies;
7bc3312b 712 int status, state = chip->state;
61b03bd7 713
1da177e4 714 if (state == FL_ERASING)
e0c7d767 715 timeo += (HZ * 400) / 1000;
1da177e4 716 else
e0c7d767 717 timeo += (HZ * 20) / 1000;
1da177e4 718
8fe833c1
RP		 719 led_trigger_event(nand_led_trigger, LED_FULL);
720
1da177e4
LT		 721 /* Apply this short delay always to ensure that we do wait tWB in
722 * any case on any machine. */
e0c7d767 723 ndelay(100);
1da177e4 724
ace4dfee
TG		 725 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
726 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 727 else
ace4dfee 728 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 729
61b03bd7 730 while (time_before(jiffies, timeo)) {
ace4dfee
TG		 731 if (chip->dev_ready) {
732 if (chip->dev_ready(mtd))
61b03bd7 733 break;
1da177e4 734 } else {
ace4dfee 735 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1da177e4
LT		 736 break;
737 }
20a6c211 738 cond_resched();
1da177e4 739 }
8fe833c1
RP		 740 led_trigger_event(nand_led_trigger, LED_OFF);
741
ace4dfee 742 status = (int)chip->read_byte(mtd);
1da177e4
LT		 743 return status;
744}
745
8593fbc6
TG		 746/**
747 * nand_read_page_raw - [Intern] read raw page data without ecc
748 * @mtd: mtd info structure
749 * @chip: nand chip info structure
750 * @buf: buffer to store read data
52ff49df
DB		 751 *
752 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 753 */
754static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
755 uint8_t *buf)
756{
757 chip->read_buf(mtd, buf, mtd->writesize);
758 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
759 return 0;
760}
761
52ff49df
DB		 762/**
763 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
764 * @mtd: mtd info structure
765 * @chip: nand chip info structure
766 * @buf: buffer to store read data
767 *
768 * We need a special oob layout and handling even when OOB isn't used.
769 */
770static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
771 uint8_t *buf)
772{
773 int eccsize = chip->ecc.size;
774 int eccbytes = chip->ecc.bytes;
775 uint8_t *oob = chip->oob_poi;
776 int steps, size;
777
778 for (steps = chip->ecc.steps; steps > 0; steps--) {
779 chip->read_buf(mtd, buf, eccsize);
780 buf += eccsize;
781
782 if (chip->ecc.prepad) {
783 chip->read_buf(mtd, oob, chip->ecc.prepad);
784 oob += chip->ecc.prepad;
785 }
786
787 chip->read_buf(mtd, oob, eccbytes);
788 oob += eccbytes;
789
790 if (chip->ecc.postpad) {
791 chip->read_buf(mtd, oob, chip->ecc.postpad);
792 oob += chip->ecc.postpad;
793 }
794 }
795
796 size = mtd->oobsize - (oob - chip->oob_poi);
797 if (size)
798 chip->read_buf(mtd, oob, size);
799
800 return 0;
801}
802
1da177e4 803/**
d29ebdbe 804 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 805 * @mtd: mtd info structure
806 * @chip: nand chip info structure
807 * @buf: buffer to store read data
068e3c0a 808 */
f5bbdacc
TG		 809static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
810 uint8_t *buf)
1da177e4 811{
f5bbdacc
TG		 812 int i, eccsize = chip->ecc.size;
813 int eccbytes = chip->ecc.bytes;
814 int eccsteps = chip->ecc.steps;
815 uint8_t *p = buf;
4bf63fcb
DW		 816 uint8_t *ecc_calc = chip->buffers->ecccalc;
817 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 818 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 819
90424de8 820 chip->ecc.read_page_raw(mtd, chip, buf);
f5bbdacc
TG		 821
822 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
823 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
824
825 for (i = 0; i < chip->ecc.total; i++)
f75e5097 826 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 827
828 eccsteps = chip->ecc.steps;
829 p = buf;
830
831 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
832 int stat;
833
834 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 835 if (stat < 0)
f5bbdacc
TG		 836 mtd->ecc_stats.failed++;
837 else
838 mtd->ecc_stats.corrected += stat;
839 }
840 return 0;
22c60f5f 841}
1da177e4 842
3d459559
AK		 843/**
844 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
845 * @mtd: mtd info structure
846 * @chip: nand chip info structure
17c1d2be
AK		 847 * @data_offs: offset of requested data within the page
848 * @readlen: data length
849 * @bufpoi: buffer to store read data
3d459559
AK		 850 */
851static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
852{
853 int start_step, end_step, num_steps;
854 uint32_t *eccpos = chip->ecc.layout->eccpos;
855 uint8_t *p;
856 int data_col_addr, i, gaps = 0;
857 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
858 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
859
860 /* Column address wihin the page aligned to ECC size (256bytes). */
861 start_step = data_offs / chip->ecc.size;
862 end_step = (data_offs + readlen - 1) / chip->ecc.size;
863 num_steps = end_step - start_step + 1;
864
865 /* Data size aligned to ECC ecc.size*/
866 datafrag_len = num_steps * chip->ecc.size;
867 eccfrag_len = num_steps * chip->ecc.bytes;
868
869 data_col_addr = start_step * chip->ecc.size;
870 /* If we read not a page aligned data */
871 if (data_col_addr != 0)
872 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
873
874 p = bufpoi + data_col_addr;
875 chip->read_buf(mtd, p, datafrag_len);
876
877 /* Calculate ECC */
878 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
879 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
880
881 /* The performance is faster if to position offsets
882 according to ecc.pos. Let make sure here that
883 there are no gaps in ecc positions */
884 for (i = 0; i < eccfrag_len - 1; i++) {
885 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
886 eccpos[i + start_step * chip->ecc.bytes + 1]) {
887 gaps = 1;
888 break;
889 }
890 }
891 if (gaps) {
892 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
893 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
894 } else {
895 /* send the command to read the particular ecc bytes */
896 /* take care about buswidth alignment in read_buf */
897 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
898 aligned_len = eccfrag_len;
899 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
900 aligned_len++;
901 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
902 aligned_len++;
903
904 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
905 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
906 }
907
908 for (i = 0; i < eccfrag_len; i++)
909 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
910
911 p = bufpoi + data_col_addr;
912 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
913 int stat;
914
915 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
916 if (stat == -1)
917 mtd->ecc_stats.failed++;
918 else
919 mtd->ecc_stats.corrected += stat;
920 }
921 return 0;
922}
923
068e3c0a 924/**
d29ebdbe 925 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 926 * @mtd: mtd info structure
927 * @chip: nand chip info structure
928 * @buf: buffer to store read data
068e3c0a 929 *
f5bbdacc 930 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 931 */
f5bbdacc
TG		 932static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
933 uint8_t *buf)
1da177e4 934{
f5bbdacc
TG		 935 int i, eccsize = chip->ecc.size;
936 int eccbytes = chip->ecc.bytes;
937 int eccsteps = chip->ecc.steps;
938 uint8_t *p = buf;
4bf63fcb
DW		 939 uint8_t *ecc_calc = chip->buffers->ecccalc;
940 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 941 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 942
943 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
944 chip->ecc.hwctl(mtd, NAND_ECC_READ);
945 chip->read_buf(mtd, p, eccsize);
946 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 947 }
f75e5097 948 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 949
f5bbdacc 950 for (i = 0; i < chip->ecc.total; i++)
f75e5097 951 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 952
f5bbdacc
TG		 953 eccsteps = chip->ecc.steps;
954 p = buf;
61b03bd7 955
f5bbdacc
TG		 956 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
957 int stat;
1da177e4 958
f5bbdacc 959 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 960 if (stat < 0)
f5bbdacc
TG		 961 mtd->ecc_stats.failed++;
962 else
963 mtd->ecc_stats.corrected += stat;
964 }
965 return 0;
966}
1da177e4 967
f5bbdacc 968/**
d29ebdbe 969 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 970 * @mtd: mtd info structure
971 * @chip: nand chip info structure
972 * @buf: buffer to store read data
973 *
974 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 975 * we need a special oob layout and handling.
f5bbdacc
TG		 976 */
977static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
978 uint8_t *buf)
979{
980 int i, eccsize = chip->ecc.size;
981 int eccbytes = chip->ecc.bytes;
982 int eccsteps = chip->ecc.steps;
983 uint8_t *p = buf;
f75e5097 984 uint8_t *oob = chip->oob_poi;
1da177e4 985
f5bbdacc
TG		 986 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
987 int stat;
61b03bd7 988
f5bbdacc
TG		 989 chip->ecc.hwctl(mtd, NAND_ECC_READ);
990 chip->read_buf(mtd, p, eccsize);
1da177e4 991
f5bbdacc
TG		 992 if (chip->ecc.prepad) {
993 chip->read_buf(mtd, oob, chip->ecc.prepad);
994 oob += chip->ecc.prepad;
995 }
1da177e4 996
f5bbdacc
TG		 997 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
998 chip->read_buf(mtd, oob, eccbytes);
999 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1000
c32b8dcc 1001 if (stat < 0)
f5bbdacc 1002 mtd->ecc_stats.failed++;
61b03bd7 1003 else
f5bbdacc 1004 mtd->ecc_stats.corrected += stat;
61b03bd7 1005
f5bbdacc 1006 oob += eccbytes;
1da177e4 1007
f5bbdacc
TG		 1008 if (chip->ecc.postpad) {
1009 chip->read_buf(mtd, oob, chip->ecc.postpad);
1010 oob += chip->ecc.postpad;
61b03bd7 1011 }
f5bbdacc 1012 }
1da177e4 1013
f5bbdacc 1014 /* Calculate remaining oob bytes */
7e4178f9 1015 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1016 if (i)
1017 chip->read_buf(mtd, oob, i);
61b03bd7 1018
f5bbdacc
TG		 1019 return 0;
1020}
1da177e4 1021
f5bbdacc 1022/**
8593fbc6
TG		 1023 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1024 * @chip: nand chip structure
844d3b42 1025 * @oob: oob destination address
8593fbc6 1026 * @ops: oob ops structure
7014568b 1027 * @len: size of oob to transfer
8593fbc6
TG		 1028 */
1029static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1030 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1031{
8593fbc6
TG		 1032 switch(ops->mode) {
1033
1034 case MTD_OOB_PLACE:
1035 case MTD_OOB_RAW:
1036 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1037 return oob + len;
1038
1039 case MTD_OOB_AUTO: {
1040 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1041 uint32_t boffs = 0, roffs = ops->ooboffs;
1042 size_t bytes = 0;
8593fbc6
TG		 1043
1044 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1045 /* Read request not from offset 0 ? */
1046 if (unlikely(roffs)) {
1047 if (roffs >= free->length) {
1048 roffs -= free->length;
1049 continue;
1050 }
1051 boffs = free->offset + roffs;
1052 bytes = min_t(size_t, len,
1053 (free->length - roffs));
1054 roffs = 0;
1055 } else {
1056 bytes = min_t(size_t, len, free->length);
1057 boffs = free->offset;
1058 }
1059 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1060 oob += bytes;
1061 }
1062 return oob;
1063 }
1064 default:
1065 BUG();
1066 }
1067 return NULL;
1068}
1069
1070/**
1071 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1072 *
1073 * @mtd: MTD device structure
1074 * @from: offset to read from
844d3b42 1075 * @ops: oob ops structure
f5bbdacc
TG		 1076 *
1077 * Internal function. Called with chip held.
1078 */
8593fbc6
TG		 1079static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1080 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1081{
1082 int chipnr, page, realpage, col, bytes, aligned;
1083 struct nand_chip *chip = mtd->priv;
1084 struct mtd_ecc_stats stats;
1085 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1086 int sndcmd = 1;
1087 int ret = 0;
8593fbc6 1088 uint32_t readlen = ops->len;
7014568b 1089 uint32_t oobreadlen = ops->ooblen;
8593fbc6 1090 uint8_t *bufpoi, *oob, *buf;
1da177e4 1091
f5bbdacc 1092 stats = mtd->ecc_stats;
1da177e4 1093
f5bbdacc
TG		 1094 chipnr = (int)(from >> chip->chip_shift);
1095 chip->select_chip(mtd, chipnr);
61b03bd7 1096
f5bbdacc
TG		 1097 realpage = (int)(from >> chip->page_shift);
1098 page = realpage & chip->pagemask;
1da177e4 1099
f5bbdacc 1100 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1101
8593fbc6
TG		 1102 buf = ops->datbuf;
1103 oob = ops->oobbuf;
1104
f5bbdacc
TG		 1105 while(1) {
1106 bytes = min(mtd->writesize - col, readlen);
1107 aligned = (bytes == mtd->writesize);
61b03bd7 1108
f5bbdacc 1109 /* Is the current page in the buffer ? */
8593fbc6 1110 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1111 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1112
f5bbdacc
TG		 1113 if (likely(sndcmd)) {
1114 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1115 sndcmd = 0;
1da177e4 1116 }
1da177e4 1117
f5bbdacc 1118 /* Now read the page into the buffer */
956e944c
DW		 1119 if (unlikely(ops->mode == MTD_OOB_RAW))
1120 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
3d459559
AK		 1121 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1122 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
956e944c
DW		 1123 else
1124 ret = chip->ecc.read_page(mtd, chip, bufpoi);
f5bbdacc 1125 if (ret < 0)
1da177e4 1126 break;
f5bbdacc
TG		 1127
1128 /* Transfer not aligned data */
1129 if (!aligned) {
3d459559
AK		 1130 if (!NAND_SUBPAGE_READ(chip) && !oob)
1131 chip->pagebuf = realpage;
4bf63fcb 1132 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1133 }
1134
8593fbc6
TG		 1135 buf += bytes;
1136
1137 if (unlikely(oob)) {
1138 /* Raw mode does data:oob:data:oob */
7014568b
VW		 1139 if (ops->mode != MTD_OOB_RAW) {
1140 int toread = min(oobreadlen,
1141 chip->ecc.layout->oobavail);
1142 if (toread) {
1143 oob = nand_transfer_oob(chip,
1144 oob, ops, toread);
1145 oobreadlen -= toread;
1146 }
1147 } else
1148 buf = nand_transfer_oob(chip,
1149 buf, ops, mtd->oobsize);
8593fbc6
TG		 1150 }
1151
f5bbdacc
TG		 1152 if (!(chip->options & NAND_NO_READRDY)) {
1153 /*
1154 * Apply delay or wait for ready/busy pin. Do
1155 * this before the AUTOINCR check, so no
1156 * problems arise if a chip which does auto
1157 * increment is marked as NOAUTOINCR by the
1158 * board driver.
1159 */
1160 if (!chip->dev_ready)
1161 udelay(chip->chip_delay);
1162 else
1163 nand_wait_ready(mtd);
1da177e4 1164 }
8593fbc6 1165 } else {
4bf63fcb 1166 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1167 buf += bytes;
1168 }
1da177e4 1169
f5bbdacc 1170 readlen -= bytes;
61b03bd7 1171
f5bbdacc 1172 if (!readlen)
61b03bd7 1173 break;
1da177e4
LT		 1174
1175 /* For subsequent reads align to page boundary. */
1176 col = 0;
1177 /* Increment page address */
1178 realpage++;
1179
ace4dfee 1180 page = realpage & chip->pagemask;
1da177e4
LT		 1181 /* Check, if we cross a chip boundary */
1182 if (!page) {
1183 chipnr++;
ace4dfee
TG		 1184 chip->select_chip(mtd, -1);
1185 chip->select_chip(mtd, chipnr);
1da177e4 1186 }
f5bbdacc 1187
61b03bd7
TG		 1188 /* Check, if the chip supports auto page increment
1189 * or if we have hit a block boundary.
e0c7d767 1190 */
f5bbdacc 1191 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1192 sndcmd = 1;
1da177e4
LT		 1193 }
1194
8593fbc6 1195 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1196 if (oob)
1197 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1198
f5bbdacc
TG		 1199 if (ret)
1200 return ret;
1201
9a1fcdfd
TG		 1202 if (mtd->ecc_stats.failed - stats.failed)
1203 return -EBADMSG;
1204
1205 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1206}
1207
1208/**
1209 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1210 * @mtd: MTD device structure
1211 * @from: offset to read from
1212 * @len: number of bytes to read
1213 * @retlen: pointer to variable to store the number of read bytes
1214 * @buf: the databuffer to put data
1215 *
1216 * Get hold of the chip and call nand_do_read
1217 */
1218static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1219 size_t *retlen, uint8_t *buf)
1220{
8593fbc6 1221 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1222 int ret;
1223
f5bbdacc
TG		 1224 /* Do not allow reads past end of device */
1225 if ((from + len) > mtd->size)
1226 return -EINVAL;
1227 if (!len)
1228 return 0;
1229
8593fbc6 1230 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1231
8593fbc6
TG		 1232 chip->ops.len = len;
1233 chip->ops.datbuf = buf;
1234 chip->ops.oobbuf = NULL;
1235
1236 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1237
7fd5aecc
RP		 1238 *retlen = chip->ops.retlen;
1239
f5bbdacc
TG		 1240 nand_release_device(mtd);
1241
1242 return ret;
1da177e4
LT		 1243}
1244
7bc3312b
TG		 1245/**
1246 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1247 * @mtd: mtd info structure
1248 * @chip: nand chip info structure
1249 * @page: page number to read
1250 * @sndcmd: flag whether to issue read command or not
1251 */
1252static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1253 int page, int sndcmd)
1254{
1255 if (sndcmd) {
1256 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1257 sndcmd = 0;
1258 }
1259 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1260 return sndcmd;
1261}
1262
1263/**
1264 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1265 * with syndromes
1266 * @mtd: mtd info structure
1267 * @chip: nand chip info structure
1268 * @page: page number to read
1269 * @sndcmd: flag whether to issue read command or not
1270 */
1271static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1272 int page, int sndcmd)
1273{
1274 uint8_t *buf = chip->oob_poi;
1275 int length = mtd->oobsize;
1276 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1277 int eccsize = chip->ecc.size;
1278 uint8_t *bufpoi = buf;
1279 int i, toread, sndrnd = 0, pos;
1280
1281 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1282 for (i = 0; i < chip->ecc.steps; i++) {
1283 if (sndrnd) {
1284 pos = eccsize + i * (eccsize + chunk);
1285 if (mtd->writesize > 512)
1286 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1287 else
1288 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1289 } else
1290 sndrnd = 1;
1291 toread = min_t(int, length, chunk);
1292 chip->read_buf(mtd, bufpoi, toread);
1293 bufpoi += toread;
1294 length -= toread;
1295 }
1296 if (length > 0)
1297 chip->read_buf(mtd, bufpoi, length);
1298
1299 return 1;
1300}
1301
1302/**
1303 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1304 * @mtd: mtd info structure
1305 * @chip: nand chip info structure
1306 * @page: page number to write
1307 */
1308static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1309 int page)
1310{
1311 int status = 0;
1312 const uint8_t *buf = chip->oob_poi;
1313 int length = mtd->oobsize;
1314
1315 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1316 chip->write_buf(mtd, buf, length);
1317 /* Send command to program the OOB data */
1318 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1319
1320 status = chip->waitfunc(mtd, chip);
1321
0d420f9d 1322 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1323}
1324
1325/**
1326 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1327 * with syndrome - only for large page flash !
1328 * @mtd: mtd info structure
1329 * @chip: nand chip info structure
1330 * @page: page number to write
1331 */
1332static int nand_write_oob_syndrome(struct mtd_info *mtd,
1333 struct nand_chip *chip, int page)
1334{
1335 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1336 int eccsize = chip->ecc.size, length = mtd->oobsize;
1337 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1338 const uint8_t *bufpoi = chip->oob_poi;
1339
1340 /*
1341 * data-ecc-data-ecc ... ecc-oob
1342 * or
1343 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1344 */
1345 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1346 pos = steps * (eccsize + chunk);
1347 steps = 0;
1348 } else
8b0036ee 1349 pos = eccsize;
7bc3312b
TG		 1350
1351 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1352 for (i = 0; i < steps; i++) {
1353 if (sndcmd) {
1354 if (mtd->writesize <= 512) {
1355 uint32_t fill = 0xFFFFFFFF;
1356
1357 len = eccsize;
1358 while (len > 0) {
1359 int num = min_t(int, len, 4);
1360 chip->write_buf(mtd, (uint8_t *)&fill,
1361 num);
1362 len -= num;
1363 }
1364 } else {
1365 pos = eccsize + i * (eccsize + chunk);
1366 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1367 }
1368 } else
1369 sndcmd = 1;
1370 len = min_t(int, length, chunk);
1371 chip->write_buf(mtd, bufpoi, len);
1372 bufpoi += len;
1373 length -= len;
1374 }
1375 if (length > 0)
1376 chip->write_buf(mtd, bufpoi, length);
1377
1378 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1379 status = chip->waitfunc(mtd, chip);
1380
1381 return status & NAND_STATUS_FAIL ? -EIO : 0;
1382}
1383
1da177e4 1384/**
8593fbc6 1385 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1386 * @mtd: MTD device structure
1387 * @from: offset to read from
8593fbc6 1388 * @ops: oob operations description structure
1da177e4
LT		 1389 *
1390 * NAND read out-of-band data from the spare area
1391 */
8593fbc6
TG		 1392static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1393 struct mtd_oob_ops *ops)
1da177e4 1394{
7bc3312b 1395 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1396 struct nand_chip *chip = mtd->priv;
7314e9e7 1397 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1398 int readlen = ops->ooblen;
1399 int len;
7bc3312b 1400 uint8_t *buf = ops->oobbuf;
61b03bd7 1401
7e9a0bb0
AM		 1402 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1403 (unsigned long long)from, readlen);
1da177e4 1404
03736155 1405 if (ops->mode == MTD_OOB_AUTO)
7014568b 1406 len = chip->ecc.layout->oobavail;
03736155
AH		 1407 else
1408 len = mtd->oobsize;
1409
1410 if (unlikely(ops->ooboffs >= len)) {
1411 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1412 "Attempt to start read outside oob\n");
1413 return -EINVAL;
1414 }
1415
1416 /* Do not allow reads past end of device */
1417 if (unlikely(from >= mtd->size ||
1418 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1419 (from >> chip->page_shift)) * len)) {
1420 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1421 "Attempt read beyond end of device\n");
1422 return -EINVAL;
1423 }
7014568b 1424
7314e9e7 1425 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1426 chip->select_chip(mtd, chipnr);
1da177e4 1427
7314e9e7
TG		 1428 /* Shift to get page */
1429 realpage = (int)(from >> chip->page_shift);
1430 page = realpage & chip->pagemask;
1da177e4 1431
7314e9e7 1432 while(1) {
7bc3312b 1433 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1434
1435 len = min(len, readlen);
1436 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1437
7314e9e7
TG		 1438 if (!(chip->options & NAND_NO_READRDY)) {
1439 /*
1440 * Apply delay or wait for ready/busy pin. Do this
1441 * before the AUTOINCR check, so no problems arise if a
1442 * chip which does auto increment is marked as
1443 * NOAUTOINCR by the board driver.
19870da7 1444 */
ace4dfee
TG		 1445 if (!chip->dev_ready)
1446 udelay(chip->chip_delay);
19870da7
TG		 1447 else
1448 nand_wait_ready(mtd);
7314e9e7 1449 }
19870da7 1450
7014568b 1451 readlen -= len;
0d420f9d
SZ		 1452 if (!readlen)
1453 break;
1454
7314e9e7
TG		 1455 /* Increment page address */
1456 realpage++;
1457
1458 page = realpage & chip->pagemask;
1459 /* Check, if we cross a chip boundary */
1460 if (!page) {
1461 chipnr++;
1462 chip->select_chip(mtd, -1);
1463 chip->select_chip(mtd, chipnr);
1da177e4 1464 }
7314e9e7
TG		 1465
1466 /* Check, if the chip supports auto page increment
1467 * or if we have hit a block boundary.
1468 */
1469 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1470 sndcmd = 1;
1da177e4
LT		 1471 }
1472
7014568b 1473 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1474 return 0;
1475}
1476
1477/**
8593fbc6 1478 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1479 * @mtd: MTD device structure
1da177e4 1480 * @from: offset to read from
8593fbc6 1481 * @ops: oob operation description structure
1da177e4 1482 *
8593fbc6 1483 * NAND read data and/or out-of-band data
1da177e4 1484 */
8593fbc6
TG		 1485static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1486 struct mtd_oob_ops *ops)
1da177e4 1487{
ace4dfee 1488 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1489 int ret = -ENOTSUPP;
1490
1491 ops->retlen = 0;
1da177e4
LT		 1492
1493 /* Do not allow reads past end of device */
7014568b 1494 if (ops->datbuf && (from + ops->len) > mtd->size) {
8593fbc6 1495 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
ace4dfee 1496 "Attempt read beyond end of device\n");
1da177e4
LT		 1497 return -EINVAL;
1498 }
1499
ace4dfee 1500 nand_get_device(chip, mtd, FL_READING);
1da177e4 1501
8593fbc6
TG		 1502 switch(ops->mode) {
1503 case MTD_OOB_PLACE:
1504 case MTD_OOB_AUTO:
8593fbc6 1505 case MTD_OOB_RAW:
8593fbc6 1506 break;
1da177e4 1507
8593fbc6
TG		 1508 default:
1509 goto out;
1510 }
1da177e4 1511
8593fbc6
TG		 1512 if (!ops->datbuf)
1513 ret = nand_do_read_oob(mtd, from, ops);
1514 else
1515 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1516
8593fbc6
TG		 1517 out:
1518 nand_release_device(mtd);
1519 return ret;
1520}
61b03bd7 1521
1da177e4 1522
8593fbc6
TG		 1523/**
1524 * nand_write_page_raw - [Intern] raw page write function
1525 * @mtd: mtd info structure
1526 * @chip: nand chip info structure
1527 * @buf: data buffer
52ff49df
DB		 1528 *
1529 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1530 */
1531static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1532 const uint8_t *buf)
1533{
1534 chip->write_buf(mtd, buf, mtd->writesize);
1535 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1536}
1537
52ff49df
DB		 1538/**
1539 * nand_write_page_raw_syndrome - [Intern] raw page write function
1540 * @mtd: mtd info structure
1541 * @chip: nand chip info structure
1542 * @buf: data buffer
1543 *
1544 * We need a special oob layout and handling even when ECC isn't checked.
1545 */
1546static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1547 const uint8_t *buf)
1548{
1549 int eccsize = chip->ecc.size;
1550 int eccbytes = chip->ecc.bytes;
1551 uint8_t *oob = chip->oob_poi;
1552 int steps, size;
1553
1554 for (steps = chip->ecc.steps; steps > 0; steps--) {
1555 chip->write_buf(mtd, buf, eccsize);
1556 buf += eccsize;
1557
1558 if (chip->ecc.prepad) {
1559 chip->write_buf(mtd, oob, chip->ecc.prepad);
1560 oob += chip->ecc.prepad;
1561 }
1562
1563 chip->read_buf(mtd, oob, eccbytes);
1564 oob += eccbytes;
1565
1566 if (chip->ecc.postpad) {
1567 chip->write_buf(mtd, oob, chip->ecc.postpad);
1568 oob += chip->ecc.postpad;
1569 }
1570 }
1571
1572 size = mtd->oobsize - (oob - chip->oob_poi);
1573 if (size)
1574 chip->write_buf(mtd, oob, size);
1575}
9223a456 1576/**
d29ebdbe 1577 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1578 * @mtd: mtd info structure
1579 * @chip: nand chip info structure
1580 * @buf: data buffer
9223a456 1581 */
f75e5097
TG		 1582static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1583 const uint8_t *buf)
9223a456 1584{
f75e5097
TG		 1585 int i, eccsize = chip->ecc.size;
1586 int eccbytes = chip->ecc.bytes;
1587 int eccsteps = chip->ecc.steps;
4bf63fcb 1588 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1589 const uint8_t *p = buf;
8b099a39 1590 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1591
8593fbc6
TG		 1592 /* Software ecc calculation */
1593 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1594 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1595
8593fbc6
TG		 1596 for (i = 0; i < chip->ecc.total; i++)
1597 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1598
90424de8 1599 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1600}
9223a456 1601
f75e5097 1602/**
d29ebdbe 1603 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1604 * @mtd: mtd info structure
1605 * @chip: nand chip info structure
1606 * @buf: data buffer
1607 */
1608static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1609 const uint8_t *buf)
1610{
1611 int i, eccsize = chip->ecc.size;
1612 int eccbytes = chip->ecc.bytes;
1613 int eccsteps = chip->ecc.steps;
4bf63fcb 1614 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1615 const uint8_t *p = buf;
8b099a39 1616 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1617
f75e5097
TG		 1618 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1619 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1620 chip->write_buf(mtd, p, eccsize);
f75e5097 1621 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1622 }
1623
f75e5097
TG		 1624 for (i = 0; i < chip->ecc.total; i++)
1625 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1626
1627 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1628}
1629
61b03bd7 1630/**
d29ebdbe 1631 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1632 * @mtd: mtd info structure
1633 * @chip: nand chip info structure
1634 * @buf: data buffer
1da177e4 1635 *
f75e5097
TG		 1636 * The hw generator calculates the error syndrome automatically. Therefor
1637 * we need a special oob layout and handling.
1638 */
1639static void nand_write_page_syndrome(struct mtd_info *mtd,
1640 struct nand_chip *chip, const uint8_t *buf)
1da177e4 1641{
f75e5097
TG		 1642 int i, eccsize = chip->ecc.size;
1643 int eccbytes = chip->ecc.bytes;
1644 int eccsteps = chip->ecc.steps;
1645 const uint8_t *p = buf;
1646 uint8_t *oob = chip->oob_poi;
1da177e4 1647
f75e5097 1648 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 1649
f75e5097
TG		 1650 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1651 chip->write_buf(mtd, p, eccsize);
61b03bd7 1652
f75e5097
TG		 1653 if (chip->ecc.prepad) {
1654 chip->write_buf(mtd, oob, chip->ecc.prepad);
1655 oob += chip->ecc.prepad;
1656 }
1657
1658 chip->ecc.calculate(mtd, p, oob);
1659 chip->write_buf(mtd, oob, eccbytes);
1660 oob += eccbytes;
1661
1662 if (chip->ecc.postpad) {
1663 chip->write_buf(mtd, oob, chip->ecc.postpad);
1664 oob += chip->ecc.postpad;
1da177e4 1665 }
1da177e4 1666 }
f75e5097
TG		 1667
1668 /* Calculate remaining oob bytes */
7e4178f9 1669 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 1670 if (i)
1671 chip->write_buf(mtd, oob, i);
1672}
1673
1674/**
956e944c 1675 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 1676 * @mtd: MTD device structure
1677 * @chip: NAND chip descriptor
1678 * @buf: the data to write
1679 * @page: page number to write
1680 * @cached: cached programming
efbfe96c 1681 * @raw: use _raw version of write_page
f75e5097
TG		 1682 */
1683static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 1684 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 1685{
1686 int status;
1687
1688 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1689
956e944c
DW		 1690 if (unlikely(raw))
1691 chip->ecc.write_page_raw(mtd, chip, buf);
1692 else
1693 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 1694
1695 /*
1696 * Cached progamming disabled for now, Not sure if its worth the
1697 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1698 */
1699 cached = 0;
1700
1701 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1702
1703 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 1704 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1705 /*
1706 * See if operation failed and additional status checks are
1707 * available
1708 */
1709 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1710 status = chip->errstat(mtd, chip, FL_WRITING, status,
1711 page);
1712
1713 if (status & NAND_STATUS_FAIL)
1714 return -EIO;
1715 } else {
1716 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 1717 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1718 }
1719
1720#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1721 /* Send command to read back the data */
1722 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1723
1724 if (chip->verify_buf(mtd, buf, mtd->writesize))
1725 return -EIO;
1726#endif
1727 return 0;
1da177e4
LT		 1728}
1729
8593fbc6
TG		 1730/**
1731 * nand_fill_oob - [Internal] Transfer client buffer to oob
1732 * @chip: nand chip structure
1733 * @oob: oob data buffer
1734 * @ops: oob ops structure
1735 */
1736static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1737 struct mtd_oob_ops *ops)
1738{
1739 size_t len = ops->ooblen;
1740
1741 switch(ops->mode) {
1742
1743 case MTD_OOB_PLACE:
1744 case MTD_OOB_RAW:
1745 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1746 return oob + len;
1747
1748 case MTD_OOB_AUTO: {
1749 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1750 uint32_t boffs = 0, woffs = ops->ooboffs;
1751 size_t bytes = 0;
8593fbc6
TG		 1752
1753 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1754 /* Write request not from offset 0 ? */
1755 if (unlikely(woffs)) {
1756 if (woffs >= free->length) {
1757 woffs -= free->length;
1758 continue;
1759 }
1760 boffs = free->offset + woffs;
1761 bytes = min_t(size_t, len,
1762 (free->length - woffs));
1763 woffs = 0;
1764 } else {
1765 bytes = min_t(size_t, len, free->length);
1766 boffs = free->offset;
1767 }
8b0036ee 1768 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 1769 oob += bytes;
1770 }
1771 return oob;
1772 }
1773 default:
1774 BUG();
1775 }
1776 return NULL;
1777}
1778
29072b96 1779#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1da177e4
LT		 1780
1781/**
8593fbc6 1782 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 1783 * @mtd: MTD device structure
1784 * @to: offset to write to
8593fbc6 1785 * @ops: oob operations description structure
1da177e4
LT		 1786 *
1787 * NAND write with ECC
1788 */
8593fbc6
TG		 1789static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1790 struct mtd_oob_ops *ops)
1da177e4 1791{
29072b96 1792 int chipnr, realpage, page, blockmask, column;
ace4dfee 1793 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1794 uint32_t writelen = ops->len;
1795 uint8_t *oob = ops->oobbuf;
1796 uint8_t *buf = ops->datbuf;
29072b96 1797 int ret, subpage;
1da177e4 1798
8593fbc6 1799 ops->retlen = 0;
29072b96
TG		 1800 if (!writelen)
1801 return 0;
1da177e4 1802
61b03bd7 1803 /* reject writes, which are not page aligned */
8593fbc6 1804 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
f75e5097
TG		 1805 printk(KERN_NOTICE "nand_write: "
1806 "Attempt to write not page aligned data\n");
1da177e4
LT		 1807 return -EINVAL;
1808 }
1809
29072b96
TG		 1810 column = to & (mtd->writesize - 1);
1811 subpage = column || (writelen & (mtd->writesize - 1));
1812
1813 if (subpage && oob)
1814 return -EINVAL;
1da177e4 1815
6a930961
TG		 1816 chipnr = (int)(to >> chip->chip_shift);
1817 chip->select_chip(mtd, chipnr);
1818
1da177e4
LT		 1819 /* Check, if it is write protected */
1820 if (nand_check_wp(mtd))
8593fbc6 1821 return -EIO;
1da177e4 1822
f75e5097
TG		 1823 realpage = (int)(to >> chip->page_shift);
1824 page = realpage & chip->pagemask;
1825 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1826
1827 /* Invalidate the page cache, when we write to the cached page */
1828 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 1829 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 1830 chip->pagebuf = -1;
61b03bd7 1831
7dcdcbef
DW		 1832 /* If we're not given explicit OOB data, let it be 0xFF */
1833 if (likely(!oob))
1834 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 1835
f75e5097 1836 while(1) {
29072b96 1837 int bytes = mtd->writesize;
f75e5097 1838 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 1839 uint8_t *wbuf = buf;
1840
1841 /* Partial page write ? */
1842 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1843 cached = 0;
1844 bytes = min_t(int, bytes - column, (int) writelen);
1845 chip->pagebuf = -1;
1846 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1847 memcpy(&chip->buffers->databuf[column], buf, bytes);
1848 wbuf = chip->buffers->databuf;
1849 }
1da177e4 1850
8593fbc6
TG		 1851 if (unlikely(oob))
1852 oob = nand_fill_oob(chip, oob, ops);
1853
29072b96 1854 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 1855 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 1856 if (ret)
1857 break;
1858
1859 writelen -= bytes;
1860 if (!writelen)
1861 break;
1862
29072b96 1863 column = 0;
f75e5097
TG		 1864 buf += bytes;
1865 realpage++;
1866
1867 page = realpage & chip->pagemask;
1868 /* Check, if we cross a chip boundary */
1869 if (!page) {
1870 chipnr++;
1871 chip->select_chip(mtd, -1);
1872 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1873 }
1874 }
8593fbc6 1875
8593fbc6 1876 ops->retlen = ops->len - writelen;
7014568b
VW		 1877 if (unlikely(oob))
1878 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1879 return ret;
1880}
1881
f75e5097 1882/**
8593fbc6 1883 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 1884 * @mtd: MTD device structure
f75e5097
TG		 1885 * @to: offset to write to
1886 * @len: number of bytes to write
8593fbc6
TG		 1887 * @retlen: pointer to variable to store the number of written bytes
1888 * @buf: the data to write
f75e5097 1889 *
8593fbc6 1890 * NAND write with ECC
f75e5097 1891 */
8593fbc6
TG		 1892static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1893 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 1894{
1895 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 1896 int ret;
1897
8593fbc6
TG		 1898 /* Do not allow reads past end of device */
1899 if ((to + len) > mtd->size)
f75e5097 1900 return -EINVAL;
8593fbc6
TG		 1901 if (!len)
1902 return 0;
f75e5097 1903
7bc3312b 1904 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 1905
8593fbc6
TG		 1906 chip->ops.len = len;
1907 chip->ops.datbuf = (uint8_t *)buf;
1908 chip->ops.oobbuf = NULL;
f75e5097 1909
8593fbc6 1910 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 1911
7fd5aecc
RP		 1912 *retlen = chip->ops.retlen;
1913
f75e5097 1914 nand_release_device(mtd);
8593fbc6 1915
8593fbc6 1916 return ret;
f75e5097 1917}
7314e9e7 1918
1da177e4 1919/**
8593fbc6 1920 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 1921 * @mtd: MTD device structure
1922 * @to: offset to write to
8593fbc6 1923 * @ops: oob operation description structure
1da177e4
LT		 1924 *
1925 * NAND write out-of-band
1926 */
8593fbc6
TG		 1927static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1928 struct mtd_oob_ops *ops)
1da177e4 1929{
03736155 1930 int chipnr, page, status, len;
ace4dfee 1931 struct nand_chip *chip = mtd->priv;
1da177e4 1932
7314e9e7 1933 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
7014568b 1934 (unsigned int)to, (int)ops->ooblen);
1da177e4 1935
03736155
AH		 1936 if (ops->mode == MTD_OOB_AUTO)
1937 len = chip->ecc.layout->oobavail;
1938 else
1939 len = mtd->oobsize;
1940
1da177e4 1941 /* Do not allow write past end of page */
03736155 1942 if ((ops->ooboffs + ops->ooblen) > len) {
7314e9e7
TG		 1943 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1944 "Attempt to write past end of page\n");
1da177e4
LT		 1945 return -EINVAL;
1946 }
1947
03736155
AH		 1948 if (unlikely(ops->ooboffs >= len)) {
1949 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1950 "Attempt to start write outside oob\n");
1951 return -EINVAL;
1952 }
1953
1954 /* Do not allow reads past end of device */
1955 if (unlikely(to >= mtd->size ||
1956 ops->ooboffs + ops->ooblen >
1957 ((mtd->size >> chip->page_shift) -
1958 (to >> chip->page_shift)) * len)) {
1959 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1960 "Attempt write beyond end of device\n");
1961 return -EINVAL;
1962 }
1963
7314e9e7 1964 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 1965 chip->select_chip(mtd, chipnr);
1da177e4 1966
7314e9e7
TG		 1967 /* Shift to get page */
1968 page = (int)(to >> chip->page_shift);
1969
1970 /*
1971 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1972 * of my DiskOnChip 2000 test units) will clear the whole data page too
1973 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1974 * it in the doc2000 driver in August 1999. dwmw2.
1975 */
ace4dfee 1976 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 1977
1978 /* Check, if it is write protected */
1979 if (nand_check_wp(mtd))
8593fbc6 1980 return -EROFS;
61b03bd7 1981
1da177e4 1982 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 1983 if (page == chip->pagebuf)
1984 chip->pagebuf = -1;
1da177e4 1985
7bc3312b
TG		 1986 memset(chip->oob_poi, 0xff, mtd->oobsize);
1987 nand_fill_oob(chip, ops->oobbuf, ops);
1988 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1989 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 1990
7bc3312b
TG		 1991 if (status)
1992 return status;
1da177e4 1993
7014568b 1994 ops->oobretlen = ops->ooblen;
1da177e4 1995
7bc3312b 1996 return 0;
8593fbc6
TG		 1997}
1998
1999/**
2000 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2001 * @mtd: MTD device structure
844d3b42 2002 * @to: offset to write to
8593fbc6
TG		 2003 * @ops: oob operation description structure
2004 */
2005static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2006 struct mtd_oob_ops *ops)
2007{
8593fbc6
TG		 2008 struct nand_chip *chip = mtd->priv;
2009 int ret = -ENOTSUPP;
2010
2011 ops->retlen = 0;
2012
2013 /* Do not allow writes past end of device */
7014568b 2014 if (ops->datbuf && (to + ops->len) > mtd->size) {
8593fbc6
TG		 2015 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
2016 "Attempt read beyond end of device\n");
2017 return -EINVAL;
2018 }
2019
7bc3312b 2020 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6
TG		 2021
2022 switch(ops->mode) {
2023 case MTD_OOB_PLACE:
2024 case MTD_OOB_AUTO:
8593fbc6 2025 case MTD_OOB_RAW:
8593fbc6
TG		 2026 break;
2027
2028 default:
2029 goto out;
2030 }
2031
2032 if (!ops->datbuf)
2033 ret = nand_do_write_oob(mtd, to, ops);
2034 else
2035 ret = nand_do_write_ops(mtd, to, ops);
2036
e0c7d767 2037 out:
1da177e4 2038 nand_release_device(mtd);
1da177e4
LT		 2039 return ret;
2040}
2041
1da177e4
LT		 2042/**
2043 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2044 * @mtd: MTD device structure
2045 * @page: the page address of the block which will be erased
2046 *
2047 * Standard erase command for NAND chips
2048 */
e0c7d767 2049static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2050{
ace4dfee 2051 struct nand_chip *chip = mtd->priv;
1da177e4 2052 /* Send commands to erase a block */
ace4dfee
TG		 2053 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2054 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2055}
2056
2057/**
2058 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2059 * @mtd: MTD device structure
2060 * @page: the page address of the block which will be erased
2061 *
2062 * AND multi block erase command function
2063 * Erase 4 consecutive blocks
2064 */
e0c7d767 2065static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2066{
ace4dfee 2067 struct nand_chip *chip = mtd->priv;
1da177e4 2068 /* Send commands to erase a block */
ace4dfee
TG		 2069 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2070 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2071 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2072 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2073 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2074}
2075
2076/**
2077 * nand_erase - [MTD Interface] erase block(s)
2078 * @mtd: MTD device structure
2079 * @instr: erase instruction
2080 *
2081 * Erase one ore more blocks
2082 */
e0c7d767 2083static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2084{
e0c7d767 2085 return nand_erase_nand(mtd, instr, 0);
1da177e4 2086}
61b03bd7 2087
30f464b7 2088#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2089/**
ace4dfee 2090 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2091 * @mtd: MTD device structure
2092 * @instr: erase instruction
2093 * @allowbbt: allow erasing the bbt area
2094 *
2095 * Erase one ore more blocks
2096 */
ace4dfee
TG		 2097int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2098 int allowbbt)
1da177e4 2099{
69423d99 2100 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2101 struct nand_chip *chip = mtd->priv;
69423d99 2102 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
ace4dfee 2103 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2104 loff_t len;
1da177e4 2105
69423d99
AH		 2106 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n",
2107 (unsigned long long)instr->addr, (unsigned long long)instr->len);
1da177e4
LT		 2108
2109 /* Start address must align on block boundary */
ace4dfee 2110 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
e0c7d767 2111 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1da177e4
LT		 2112 return -EINVAL;
2113 }
2114
2115 /* Length must align on block boundary */
ace4dfee
TG		 2116 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2117 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2118 "Length not block aligned\n");
1da177e4
LT		 2119 return -EINVAL;
2120 }
2121
2122 /* Do not allow erase past end of device */
2123 if ((instr->len + instr->addr) > mtd->size) {
ace4dfee
TG		 2124 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2125 "Erase past end of device\n");
1da177e4
LT		 2126 return -EINVAL;
2127 }
2128
bb0eb217 2129 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2130
2131 /* Grab the lock and see if the device is available */
ace4dfee 2132 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2133
2134 /* Shift to get first page */
ace4dfee
TG		 2135 page = (int)(instr->addr >> chip->page_shift);
2136 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2137
2138 /* Calculate pages in each block */
ace4dfee 2139 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2140
2141 /* Select the NAND device */
ace4dfee 2142 chip->select_chip(mtd, chipnr);
1da177e4 2143
1da177e4
LT		 2144 /* Check, if it is write protected */
2145 if (nand_check_wp(mtd)) {
ace4dfee
TG		 2146 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2147 "Device is write protected!!!\n");
1da177e4
LT		 2148 instr->state = MTD_ERASE_FAILED;
2149 goto erase_exit;
2150 }
2151
ace4dfee
TG		 2152 /*
2153 * If BBT requires refresh, set the BBT page mask to see if the BBT
2154 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2155 * can not be matched. This is also done when the bbt is actually
2156 * erased to avoid recusrsive updates
2157 */
2158 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2159 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2160
1da177e4
LT		 2161 /* Loop through the pages */
2162 len = instr->len;
2163
2164 instr->state = MTD_ERASING;
2165
2166 while (len) {
ace4dfee
TG		 2167 /*
2168 * heck if we have a bad block, we do not erase bad blocks !
2169 */
2170 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2171 chip->page_shift, 0, allowbbt)) {
2172 printk(KERN_WARNING "nand_erase: attempt to erase a "
2173 "bad block at page 0x%08x\n", page);
1da177e4
LT		 2174 instr->state = MTD_ERASE_FAILED;
2175 goto erase_exit;
2176 }
61b03bd7 2177
ace4dfee
TG		 2178 /*
2179 * Invalidate the page cache, if we erase the block which
2180 * contains the current cached page
2181 */
2182 if (page <= chip->pagebuf && chip->pagebuf <
2183 (page + pages_per_block))
2184 chip->pagebuf = -1;
1da177e4 2185
ace4dfee 2186 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2187
7bc3312b 2188 status = chip->waitfunc(mtd, chip);
1da177e4 2189
ace4dfee
TG		 2190 /*
2191 * See if operation failed and additional status checks are
2192 * available
2193 */
2194 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2195 status = chip->errstat(mtd, chip, FL_ERASING,
2196 status, page);
068e3c0a 2197
1da177e4 2198 /* See if block erase succeeded */
a4ab4c5d 2199 if (status & NAND_STATUS_FAIL) {
ace4dfee
TG		 2200 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2201 "Failed erase, page 0x%08x\n", page);
1da177e4 2202 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2203 instr->fail_addr =
2204 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2205 goto erase_exit;
2206 }
30f464b7 2207
ace4dfee
TG		 2208 /*
2209 * If BBT requires refresh, set the BBT rewrite flag to the
2210 * page being erased
2211 */
2212 if (bbt_masked_page != 0xffffffff &&
2213 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2214 rewrite_bbt[chipnr] =
2215 ((loff_t)page << chip->page_shift);
61b03bd7 2216
1da177e4 2217 /* Increment page address and decrement length */
ace4dfee 2218 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2219 page += pages_per_block;
2220
2221 /* Check, if we cross a chip boundary */
ace4dfee 2222 if (len && !(page & chip->pagemask)) {
1da177e4 2223 chipnr++;
ace4dfee
TG		 2224 chip->select_chip(mtd, -1);
2225 chip->select_chip(mtd, chipnr);
30f464b7 2226
ace4dfee
TG		 2227 /*
2228 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2229 * page mask to see if this BBT should be rewritten
2230 */
2231 if (bbt_masked_page != 0xffffffff &&
2232 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2233 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2234 BBT_PAGE_MASK;
1da177e4
LT		 2235 }
2236 }
2237 instr->state = MTD_ERASE_DONE;
2238
e0c7d767 2239 erase_exit:
1da177e4
LT		 2240
2241 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2242
2243 /* Deselect and wake up anyone waiting on the device */
2244 nand_release_device(mtd);
2245
49defc01
DW		 2246 /* Do call back function */
2247 if (!ret)
2248 mtd_erase_callback(instr);
2249
ace4dfee
TG		 2250 /*
2251 * If BBT requires refresh and erase was successful, rewrite any
2252 * selected bad block tables
2253 */
2254 if (bbt_masked_page == 0xffffffff || ret)
2255 return ret;
2256
2257 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2258 if (!rewrite_bbt[chipnr])
2259 continue;
2260 /* update the BBT for chip */
2261 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
69423d99 2262 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
ace4dfee
TG		 2263 chip->bbt_td->pages[chipnr]);
2264 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2265 }
2266
1da177e4
LT		 2267 /* Return more or less happy */
2268 return ret;
2269}
2270
2271/**
2272 * nand_sync - [MTD Interface] sync
2273 * @mtd: MTD device structure
2274 *
2275 * Sync is actually a wait for chip ready function
2276 */
e0c7d767 2277static void nand_sync(struct mtd_info *mtd)
1da177e4 2278{
ace4dfee 2279 struct nand_chip *chip = mtd->priv;
1da177e4 2280
e0c7d767 2281 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1da177e4
LT		 2282
2283 /* Grab the lock and see if the device is available */
ace4dfee 2284 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2285 /* Release it and go back */
e0c7d767 2286 nand_release_device(mtd);
1da177e4
LT		 2287}
2288
1da177e4 2289/**
ace4dfee 2290 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2291 * @mtd: MTD device structure
844d3b42 2292 * @offs: offset relative to mtd start
1da177e4 2293 */
ace4dfee 2294static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2295{
2296 /* Check for invalid offset */
ace4dfee 2297 if (offs > mtd->size)
1da177e4 2298 return -EINVAL;
61b03bd7 2299
ace4dfee 2300 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2301}
2302
2303/**
ace4dfee 2304 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2305 * @mtd: MTD device structure
2306 * @ofs: offset relative to mtd start
2307 */
e0c7d767 2308static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2309{
ace4dfee 2310 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2311 int ret;
2312
e0c7d767
DW		 2313 if ((ret = nand_block_isbad(mtd, ofs))) {
2314 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2315 if (ret > 0)
2316 return 0;
e0c7d767
DW		 2317 return ret;
2318 }
1da177e4 2319
ace4dfee 2320 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2321}
2322
962034f4
VW		 2323/**
2324 * nand_suspend - [MTD Interface] Suspend the NAND flash
2325 * @mtd: MTD device structure
2326 */
2327static int nand_suspend(struct mtd_info *mtd)
2328{
ace4dfee 2329 struct nand_chip *chip = mtd->priv;
962034f4 2330
ace4dfee 2331 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2332}
2333
2334/**
2335 * nand_resume - [MTD Interface] Resume the NAND flash
2336 * @mtd: MTD device structure
2337 */
2338static void nand_resume(struct mtd_info *mtd)
2339{
ace4dfee 2340 struct nand_chip *chip = mtd->priv;
962034f4 2341
ace4dfee 2342 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2343 nand_release_device(mtd);
2344 else
2c0a2bed
TG		 2345 printk(KERN_ERR "nand_resume() called for a chip which is not "
2346 "in suspended state\n");
962034f4
VW		 2347}
2348
7aa65bfd
TG		 2349/*
2350 * Set default functions
2351 */
ace4dfee 2352static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2353{
1da177e4 2354 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2355 if (!chip->chip_delay)
2356 chip->chip_delay = 20;
1da177e4
LT		 2357
2358 /* check, if a user supplied command function given */
ace4dfee
TG		 2359 if (chip->cmdfunc == NULL)
2360 chip->cmdfunc = nand_command;
1da177e4
LT		 2361
2362 /* check, if a user supplied wait function given */
ace4dfee
TG		 2363 if (chip->waitfunc == NULL)
2364 chip->waitfunc = nand_wait;
2365
2366 if (!chip->select_chip)
2367 chip->select_chip = nand_select_chip;
2368 if (!chip->read_byte)
2369 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2370 if (!chip->read_word)
2371 chip->read_word = nand_read_word;
2372 if (!chip->block_bad)
2373 chip->block_bad = nand_block_bad;
2374 if (!chip->block_markbad)
2375 chip->block_markbad = nand_default_block_markbad;
2376 if (!chip->write_buf)
2377 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2378 if (!chip->read_buf)
2379 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2380 if (!chip->verify_buf)
2381 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2382 if (!chip->scan_bbt)
2383 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2384
2385 if (!chip->controller) {
2386 chip->controller = &chip->hwcontrol;
2387 spin_lock_init(&chip->controller->lock);
2388 init_waitqueue_head(&chip->controller->wq);
2389 }
2390
7aa65bfd
TG		 2391}
2392
2393/*
ace4dfee 2394 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2395 */
2396static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2397 struct nand_chip *chip,
7aa65bfd
TG		 2398 int busw, int *maf_id)
2399{
2400 struct nand_flash_dev *type = NULL;
2401 int i, dev_id, maf_idx;
ed8165c7 2402 int tmp_id, tmp_manf;
1da177e4
LT		 2403
2404 /* Select the device */
ace4dfee 2405 chip->select_chip(mtd, 0);
1da177e4 2406
ef89a880
KB		 2407 /*
2408 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2409 * after power-up
2410 */
2411 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2412
1da177e4 2413 /* Send the command for reading device ID */
ace4dfee 2414 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2415
2416 /* Read manufacturer and device IDs */
ace4dfee
TG		 2417 *maf_id = chip->read_byte(mtd);
2418 dev_id = chip->read_byte(mtd);
1da177e4 2419
ed8165c7
BD		 2420 /* Try again to make sure, as some systems the bus-hold or other
2421 * interface concerns can cause random data which looks like a
2422 * possibly credible NAND flash to appear. If the two results do
2423 * not match, ignore the device completely.
2424 */
2425
2426 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2427
2428 /* Read manufacturer and device IDs */
2429
2430 tmp_manf = chip->read_byte(mtd);
2431 tmp_id = chip->read_byte(mtd);
2432
2433 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2434 printk(KERN_INFO "%s: second ID read did not match "
2435 "%02x,%02x against %02x,%02x\n", __func__,
2436 *maf_id, dev_id, tmp_manf, tmp_id);
2437 return ERR_PTR(-ENODEV);
2438 }
2439
7aa65bfd 2440 /* Lookup the flash id */
1da177e4 2441 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
7aa65bfd
TG		 2442 if (dev_id == nand_flash_ids[i].id) {
2443 type = &nand_flash_ids[i];
2444 break;
2445 }
2446 }
61b03bd7 2447
7aa65bfd
TG		 2448 if (!type)
2449 return ERR_PTR(-ENODEV);
2450
ba0251fe
TG		 2451 if (!mtd->name)
2452 mtd->name = type->name;
2453
69423d99 2454 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd
TG		 2455
2456 /* Newer devices have all the information in additional id bytes */
ba0251fe 2457 if (!type->pagesize) {
7aa65bfd 2458 int extid;
29072b96
TG		 2459 /* The 3rd id byte holds MLC / multichip data */
2460 chip->cellinfo = chip->read_byte(mtd);
7aa65bfd 2461 /* The 4th id byte is the important one */
ace4dfee 2462 extid = chip->read_byte(mtd);
7aa65bfd 2463 /* Calc pagesize */
4cbb9b80 2464 mtd->writesize = 1024 << (extid & 0x3);
7aa65bfd
TG		 2465 extid >>= 2;
2466 /* Calc oobsize */
4cbb9b80 2467 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
7aa65bfd
TG		 2468 extid >>= 2;
2469 /* Calc blocksize. Blocksize is multiples of 64KiB */
2470 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2471 extid >>= 2;
2472 /* Get buswidth information */
2473 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
61b03bd7 2474
7aa65bfd
TG		 2475 } else {
2476 /*
ace4dfee 2477 * Old devices have chip data hardcoded in the device id table
7aa65bfd 2478 */
ba0251fe
TG		 2479 mtd->erasesize = type->erasesize;
2480 mtd->writesize = type->pagesize;
4cbb9b80 2481 mtd->oobsize = mtd->writesize / 32;
ba0251fe 2482 busw = type->options & NAND_BUSWIDTH_16;
7aa65bfd 2483 }
1da177e4 2484
7aa65bfd 2485 /* Try to identify manufacturer */
9a909867 2486 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 2487 if (nand_manuf_ids[maf_idx].id == *maf_id)
2488 break;
2489 }
0ea4a755 2490
7aa65bfd
TG		 2491 /*
2492 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 2493 * chip correct !
7aa65bfd 2494 */
ace4dfee 2495 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 2496 printk(KERN_INFO "NAND device: Manufacturer ID:"
2497 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2498 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2499 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 2500 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 2501 busw ? 16 : 8);
2502 return ERR_PTR(-EINVAL);
2503 }
61b03bd7 2504
7aa65bfd 2505 /* Calculate the address shift from the page size */
ace4dfee 2506 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 2507 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 2508 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 2509
ace4dfee 2510 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 2511 ffs(mtd->erasesize) - 1;
69423d99
AH		 2512 if (chip->chipsize & 0xffffffff)
2513 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2514 else
2515 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
1da177e4 2516
7aa65bfd 2517 /* Set the bad block position */
ace4dfee 2518 chip->badblockpos = mtd->writesize > 512 ?
7aa65bfd 2519 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
61b03bd7 2520
7aa65bfd 2521 /* Get chip options, preserve non chip based options */
ace4dfee 2522 chip->options &= ~NAND_CHIPOPTIONS_MSK;
ba0251fe 2523 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
7aa65bfd
TG		 2524
2525 /*
ace4dfee 2526 * Set chip as a default. Board drivers can override it, if necessary
7aa65bfd 2527 */
ace4dfee 2528 chip->options |= NAND_NO_AUTOINCR;
7aa65bfd 2529
ace4dfee 2530 /* Check if chip is a not a samsung device. Do not clear the
7aa65bfd
TG		 2531 * options for chips which are not having an extended id.
2532 */
ba0251fe 2533 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
ace4dfee 2534 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
7aa65bfd
TG		 2535
2536 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 2537 if (chip->options & NAND_4PAGE_ARRAY)
2538 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 2539 else
ace4dfee 2540 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 2541
2542 /* Do not replace user supplied command function ! */
ace4dfee
TG		 2543 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2544 chip->cmdfunc = nand_command_lp;
7aa65bfd
TG		 2545
2546 printk(KERN_INFO "NAND device: Manufacturer ID:"
2547 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2548 nand_manuf_ids[maf_idx].name, type->name);
2549
2550 return type;
2551}
2552
7aa65bfd 2553/**
3b85c321
DW		 2554 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2555 * @mtd: MTD device structure
2556 * @maxchips: Number of chips to scan for
7aa65bfd 2557 *
3b85c321
DW		 2558 * This is the first phase of the normal nand_scan() function. It
2559 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 2560 *
3b85c321 2561 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 2562 */
3b85c321 2563int nand_scan_ident(struct mtd_info *mtd, int maxchips)
7aa65bfd
TG		 2564{
2565 int i, busw, nand_maf_id;
ace4dfee 2566 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 2567 struct nand_flash_dev *type;
2568
7aa65bfd 2569 /* Get buswidth to select the correct functions */
ace4dfee 2570 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 2571 /* Set the default functions */
ace4dfee 2572 nand_set_defaults(chip, busw);
7aa65bfd
TG		 2573
2574 /* Read the flash type */
ace4dfee 2575 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
7aa65bfd
TG		 2576
2577 if (IS_ERR(type)) {
e0c7d767 2578 printk(KERN_WARNING "No NAND device found!!!\n");
ace4dfee 2579 chip->select_chip(mtd, -1);
7aa65bfd 2580 return PTR_ERR(type);
1da177e4
LT		 2581 }
2582
7aa65bfd 2583 /* Check for a chip array */
e0c7d767 2584 for (i = 1; i < maxchips; i++) {
ace4dfee 2585 chip->select_chip(mtd, i);
ef89a880
KB		 2586 /* See comment in nand_get_flash_type for reset */
2587 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 2588 /* Send the command for reading device ID */
ace4dfee 2589 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 2590 /* Read manufacturer and device IDs */
ace4dfee
TG		 2591 if (nand_maf_id != chip->read_byte(mtd) ||
2592 type->id != chip->read_byte(mtd))
1da177e4
LT		 2593 break;
2594 }
2595 if (i > 1)
2596 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 2597
1da177e4 2598 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 2599 chip->numchips = i;
2600 mtd->size = i * chip->chipsize;
7aa65bfd 2601
3b85c321
DW		 2602 return 0;
2603}
2604
2605
2606/**
2607 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2608 * @mtd: MTD device structure
3b85c321
DW		 2609 *
2610 * This is the second phase of the normal nand_scan() function. It
2611 * fills out all the uninitialized function pointers with the defaults
2612 * and scans for a bad block table if appropriate.
2613 */
2614int nand_scan_tail(struct mtd_info *mtd)
2615{
2616 int i;
2617 struct nand_chip *chip = mtd->priv;
2618
4bf63fcb
DW		 2619 if (!(chip->options & NAND_OWN_BUFFERS))
2620 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2621 if (!chip->buffers)
2622 return -ENOMEM;
2623
7dcdcbef 2624 /* Set the internal oob buffer location, just after the page data */
784f4d5e 2625 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 2626
7aa65bfd
TG		 2627 /*
2628 * If no default placement scheme is given, select an appropriate one
2629 */
5bd34c09 2630 if (!chip->ecc.layout) {
61b03bd7 2631 switch (mtd->oobsize) {
1da177e4 2632 case 8:
5bd34c09 2633 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 2634 break;
2635 case 16:
5bd34c09 2636 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 2637 break;
2638 case 64:
5bd34c09 2639 chip->ecc.layout = &nand_oob_64;
1da177e4
LT		 2640 break;
2641 default:
7aa65bfd
TG		 2642 printk(KERN_WARNING "No oob scheme defined for "
2643 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 2644 BUG();
2645 }
2646 }
61b03bd7 2647
956e944c
DW		 2648 if (!chip->write_page)
2649 chip->write_page = nand_write_page;
2650
61b03bd7 2651 /*
7aa65bfd
TG		 2652 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2653 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 2654 */
956e944c 2655
ace4dfee 2656 switch (chip->ecc.mode) {
6dfc6d25 2657 case NAND_ECC_HW:
f5bbdacc
TG		 2658 /* Use standard hwecc read page function ? */
2659 if (!chip->ecc.read_page)
2660 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 2661 if (!chip->ecc.write_page)
2662 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 2663 if (!chip->ecc.read_page_raw)
2664 chip->ecc.read_page_raw = nand_read_page_raw;
2665 if (!chip->ecc.write_page_raw)
2666 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2667 if (!chip->ecc.read_oob)
2668 chip->ecc.read_oob = nand_read_oob_std;
2669 if (!chip->ecc.write_oob)
2670 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 2671
6dfc6d25 2672 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 2673 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2674 !chip->ecc.hwctl) &&
2675 (!chip->ecc.read_page ||
1c45f604 2676 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 2677 !chip->ecc.write_page ||
1c45f604 2678 chip->ecc.write_page == nand_write_page_hwecc)) {
6dfc6d25
TG		 2679 printk(KERN_WARNING "No ECC functions supplied, "
2680 "Hardware ECC not possible\n");
2681 BUG();
2682 }
f75e5097 2683 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 2684 if (!chip->ecc.read_page)
2685 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 2686 if (!chip->ecc.write_page)
2687 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 2688 if (!chip->ecc.read_page_raw)
2689 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2690 if (!chip->ecc.write_page_raw)
2691 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 2692 if (!chip->ecc.read_oob)
2693 chip->ecc.read_oob = nand_read_oob_syndrome;
2694 if (!chip->ecc.write_oob)
2695 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 2696
ace4dfee 2697 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 2698 break;
2699 printk(KERN_WARNING "%d byte HW ECC not possible on "
2700 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 2701 chip->ecc.size, mtd->writesize);
2702 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 2703
6dfc6d25 2704 case NAND_ECC_SOFT:
ace4dfee
TG		 2705 chip->ecc.calculate = nand_calculate_ecc;
2706 chip->ecc.correct = nand_correct_data;
f5bbdacc 2707 chip->ecc.read_page = nand_read_page_swecc;
3d459559 2708 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 2709 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 2710 chip->ecc.read_page_raw = nand_read_page_raw;
2711 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2712 chip->ecc.read_oob = nand_read_oob_std;
2713 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 2714 chip->ecc.size = 256;
2715 chip->ecc.bytes = 3;
1da177e4 2716 break;
61b03bd7
TG		 2717
2718 case NAND_ECC_NONE:
7aa65bfd
TG		 2719 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2720 "This is not recommended !!\n");
8593fbc6
TG		 2721 chip->ecc.read_page = nand_read_page_raw;
2722 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 2723 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 2724 chip->ecc.read_page_raw = nand_read_page_raw;
2725 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 2726 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 2727 chip->ecc.size = mtd->writesize;
2728 chip->ecc.bytes = 0;
1da177e4 2729 break;
956e944c 2730
1da177e4 2731 default:
7aa65bfd 2732 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 2733 chip->ecc.mode);
61b03bd7 2734 BUG();
1da177e4 2735 }
61b03bd7 2736
5bd34c09
TG		 2737 /*
2738 * The number of bytes available for a client to place data into
2739 * the out of band area
2740 */
2741 chip->ecc.layout->oobavail = 0;
2742 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2743 chip->ecc.layout->oobavail +=
2744 chip->ecc.layout->oobfree[i].length;
1f92267c 2745 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 2746
7aa65bfd
TG		 2747 /*
2748 * Set the number of read / write steps for one page depending on ECC
2749 * mode
2750 */
ace4dfee
TG		 2751 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2752 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 2753 printk(KERN_WARNING "Invalid ecc parameters\n");
2754 BUG();
1da177e4 2755 }
f5bbdacc 2756 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 2757
29072b96
TG		 2758 /*
2759 * Allow subpage writes up to ecc.steps. Not possible for MLC
2760 * FLASH.
2761 */
2762 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2763 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2764 switch(chip->ecc.steps) {
2765 case 2:
2766 mtd->subpage_sft = 1;
2767 break;
2768 case 4:
2769 case 8:
2770 mtd->subpage_sft = 2;
2771 break;
2772 }
2773 }
2774 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2775
04bbd0ea 2776 /* Initialize state */
ace4dfee 2777 chip->state = FL_READY;
1da177e4
LT		 2778
2779 /* De-select the device */
ace4dfee 2780 chip->select_chip(mtd, -1);
1da177e4
LT		 2781
2782 /* Invalidate the pagebuffer reference */
ace4dfee 2783 chip->pagebuf = -1;
1da177e4
LT		 2784
2785 /* Fill in remaining MTD driver data */
2786 mtd->type = MTD_NANDFLASH;
5fa43394 2787 mtd->flags = MTD_CAP_NANDFLASH;
1da177e4
LT		 2788 mtd->erase = nand_erase;
2789 mtd->point = NULL;
2790 mtd->unpoint = NULL;
2791 mtd->read = nand_read;
2792 mtd->write = nand_write;
1da177e4
LT		 2793 mtd->read_oob = nand_read_oob;
2794 mtd->write_oob = nand_write_oob;
1da177e4
LT		 2795 mtd->sync = nand_sync;
2796 mtd->lock = NULL;
2797 mtd->unlock = NULL;
962034f4
VW		 2798 mtd->suspend = nand_suspend;
2799 mtd->resume = nand_resume;
1da177e4
LT		 2800 mtd->block_isbad = nand_block_isbad;
2801 mtd->block_markbad = nand_block_markbad;
2802
5bd34c09
TG		 2803 /* propagate ecc.layout to mtd_info */
2804 mtd->ecclayout = chip->ecc.layout;
1da177e4 2805
0040bf38 2806 /* Check, if we should skip the bad block table scan */
ace4dfee 2807 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 2808 return 0;
1da177e4
LT		 2809
2810 /* Build bad block table */
ace4dfee 2811 return chip->scan_bbt(mtd);
1da177e4
LT		 2812}
2813
3b85c321
DW		 2814/* module_text_address() isn't exported, and it's mostly a pointless
2815 test if this is a module _anyway_ -- they'd have to try _really_ hard
2816 to call us from in-kernel code if the core NAND support is modular. */
2817#ifdef MODULE
2818#define caller_is_module() (1)
2819#else
2820#define caller_is_module() \
2821 module_text_address((unsigned long)__builtin_return_address(0))
2822#endif
2823
2824/**
2825 * nand_scan - [NAND Interface] Scan for the NAND device
2826 * @mtd: MTD device structure
2827 * @maxchips: Number of chips to scan for
2828 *
2829 * This fills out all the uninitialized function pointers
2830 * with the defaults.
2831 * The flash ID is read and the mtd/chip structures are
2832 * filled with the appropriate values.
2833 * The mtd->owner field must be set to the module of the caller
2834 *
2835 */
2836int nand_scan(struct mtd_info *mtd, int maxchips)
2837{
2838 int ret;
2839
2840 /* Many callers got this wrong, so check for it for a while... */
2841 if (!mtd->owner && caller_is_module()) {
2842 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2843 BUG();
2844 }
2845
2846 ret = nand_scan_ident(mtd, maxchips);
2847 if (!ret)
2848 ret = nand_scan_tail(mtd);
2849 return ret;
2850}
2851
1da177e4 2852/**
61b03bd7 2853 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 2854 * @mtd: MTD device structure
2855*/
e0c7d767 2856void nand_release(struct mtd_info *mtd)
1da177e4 2857{
ace4dfee 2858 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2859
2860#ifdef CONFIG_MTD_PARTITIONS
2861 /* Deregister partitions */
e0c7d767 2862 del_mtd_partitions(mtd);
1da177e4
LT		 2863#endif
2864 /* Deregister the device */
e0c7d767 2865 del_mtd_device(mtd);
1da177e4 2866
fa671646 2867 /* Free bad block table memory */
ace4dfee 2868 kfree(chip->bbt);
4bf63fcb
DW		 2869 if (!(chip->options & NAND_OWN_BUFFERS))
2870 kfree(chip->buffers);
1da177e4
LT		 2871}
2872
e0c7d767 2873EXPORT_SYMBOL_GPL(nand_scan);
3b85c321
DW		 2874EXPORT_SYMBOL_GPL(nand_scan_ident);
2875EXPORT_SYMBOL_GPL(nand_scan_tail);
e0c7d767 2876EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 2877
2878static int __init nand_base_init(void)
2879{
2880 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2881 return 0;
2882}
2883
2884static void __exit nand_base_exit(void)
2885{
2886 led_trigger_unregister_simple(nand_led_trigger);
2887}
2888
2889module_init(nand_base_init);
2890module_exit(nand_base_exit);
2891
e0c7d767
DW		 2892MODULE_LICENSE("GPL");
2893MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2894MODULE_DESCRIPTION("Generic NAND flash driver code");
Clone of davem's net-next-2.6 tree