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[net-next-2.6.git] / drivers / mtd / nand / nand_base.c
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1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
45#include <linux/mtd/compatmac.h>
46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
1da177e4
LT		 49#include <asm/io.h>
50
51#ifdef CONFIG_MTD_PARTITIONS
52#include <linux/mtd/partitions.h>
53#endif
54
55/* Define default oob placement schemes for large and small page devices */
5bd34c09 56static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
5bd34c09
TG		 59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
1da177e4
LT		 64};
65
5bd34c09 66static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
1da177e4
LT		 72};
73
5bd34c09 74static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 75 .eccbytes = 24,
76 .eccpos = {
e0c7d767
DW		 77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
1da177e4
LT		 83};
84
81ec5364
TG		 85static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
96 .length = 78}}
97};
98
ace4dfee 99static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 100 int new_state);
1da177e4 101
8593fbc6
TG		 102static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
d470a97c 105/*
8e87d782 106 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 107 * compiled away when LED support is disabled.
108 */
109DEFINE_LED_TRIGGER(nand_led_trigger);
110
1da177e4
LT		 111/**
112 * nand_release_device - [GENERIC] release chip
113 * @mtd: MTD device structure
61b03bd7
TG		 114 *
115 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 116 */
e0c7d767 117static void nand_release_device(struct mtd_info *mtd)
1da177e4 118{
ace4dfee 119 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 120
121 /* De-select the NAND device */
ace4dfee 122 chip->select_chip(mtd, -1);
0dfc6246 123
a36ed299 124 /* Release the controller and the chip */
ace4dfee
TG		 125 spin_lock(&chip->controller->lock);
126 chip->controller->active = NULL;
127 chip->state = FL_READY;
128 wake_up(&chip->controller->wq);
129 spin_unlock(&chip->controller->lock);
1da177e4
LT		 130}
131
132/**
133 * nand_read_byte - [DEFAULT] read one byte from the chip
134 * @mtd: MTD device structure
135 *
136 * Default read function for 8bit buswith
137 */
58dd8f2b 138static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 139{
ace4dfee
TG		 140 struct nand_chip *chip = mtd->priv;
141 return readb(chip->IO_ADDR_R);
1da177e4
LT		 142}
143
1da177e4
LT		 144/**
145 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
146 * @mtd: MTD device structure
147 *
61b03bd7 148 * Default read function for 16bit buswith with
1da177e4
LT		 149 * endianess conversion
150 */
58dd8f2b 151static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 152{
ace4dfee
TG		 153 struct nand_chip *chip = mtd->priv;
154 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 155}
156
1da177e4
LT		 157/**
158 * nand_read_word - [DEFAULT] read one word from the chip
159 * @mtd: MTD device structure
160 *
61b03bd7 161 * Default read function for 16bit buswith without
1da177e4
LT		 162 * endianess conversion
163 */
164static u16 nand_read_word(struct mtd_info *mtd)
165{
ace4dfee
TG		 166 struct nand_chip *chip = mtd->priv;
167 return readw(chip->IO_ADDR_R);
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_select_chip - [DEFAULT] control CE line
172 * @mtd: MTD device structure
844d3b42 173 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 174 *
175 * Default select function for 1 chip devices.
176 */
ace4dfee 177static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180
181 switch (chipnr) {
1da177e4 182 case -1:
ace4dfee 183 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 184 break;
185 case 0:
1da177e4
LT		 186 break;
187
188 default:
189 BUG();
190 }
191}
192
193/**
194 * nand_write_buf - [DEFAULT] write buffer to chip
195 * @mtd: MTD device structure
196 * @buf: data buffer
197 * @len: number of bytes to write
198 *
199 * Default write function for 8bit buswith
200 */
58dd8f2b 201static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 202{
203 int i;
ace4dfee 204 struct nand_chip *chip = mtd->priv;
1da177e4 205
e0c7d767 206 for (i = 0; i < len; i++)
ace4dfee 207 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 208}
209
210/**
61b03bd7 211 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 212 * @mtd: MTD device structure
213 * @buf: buffer to store date
214 * @len: number of bytes to read
215 *
216 * Default read function for 8bit buswith
217 */
58dd8f2b 218static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 219{
220 int i;
ace4dfee 221 struct nand_chip *chip = mtd->priv;
1da177e4 222
e0c7d767 223 for (i = 0; i < len; i++)
ace4dfee 224 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 225}
226
227/**
61b03bd7 228 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 229 * @mtd: MTD device structure
230 * @buf: buffer containing the data to compare
231 * @len: number of bytes to compare
232 *
233 * Default verify function for 8bit buswith
234 */
58dd8f2b 235static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 236{
237 int i;
ace4dfee 238 struct nand_chip *chip = mtd->priv;
1da177e4 239
e0c7d767 240 for (i = 0; i < len; i++)
ace4dfee 241 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 242 return -EFAULT;
1da177e4
LT		 243 return 0;
244}
245
246/**
247 * nand_write_buf16 - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
249 * @buf: data buffer
250 * @len: number of bytes to write
251 *
252 * Default write function for 16bit buswith
253 */
58dd8f2b 254static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 255{
256 int i;
ace4dfee 257 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 258 u16 *p = (u16 *) buf;
259 len >>= 1;
61b03bd7 260
e0c7d767 261 for (i = 0; i < len; i++)
ace4dfee 262 writew(p[i], chip->IO_ADDR_W);
61b03bd7 263
1da177e4
LT		 264}
265
266/**
61b03bd7 267 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
271 *
272 * Default read function for 16bit buswith
273 */
58dd8f2b 274static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 275{
276 int i;
ace4dfee 277 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 278 u16 *p = (u16 *) buf;
279 len >>= 1;
280
e0c7d767 281 for (i = 0; i < len; i++)
ace4dfee 282 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 283}
284
285/**
61b03bd7 286 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 287 * @mtd: MTD device structure
288 * @buf: buffer containing the data to compare
289 * @len: number of bytes to compare
290 *
291 * Default verify function for 16bit buswith
292 */
58dd8f2b 293static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 294{
295 int i;
ace4dfee 296 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 297 u16 *p = (u16 *) buf;
298 len >>= 1;
299
e0c7d767 300 for (i = 0; i < len; i++)
ace4dfee 301 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 302 return -EFAULT;
303
304 return 0;
305}
306
307/**
308 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
309 * @mtd: MTD device structure
310 * @ofs: offset from device start
311 * @getchip: 0, if the chip is already selected
312 *
61b03bd7 313 * Check, if the block is bad.
1da177e4
LT		 314 */
315static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
316{
317 int page, chipnr, res = 0;
ace4dfee 318 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 319 u16 bad;
320
1a12f46a
TK		 321 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322
1da177e4 323 if (getchip) {
ace4dfee 324 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 325
ace4dfee 326 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 327
328 /* Select the NAND device */
ace4dfee 329 chip->select_chip(mtd, chipnr);
1a12f46a 330 }
1da177e4 331
ace4dfee
TG		 332 if (chip->options & NAND_BUSWIDTH_16) {
333 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 334 page);
ace4dfee
TG		 335 bad = cpu_to_le16(chip->read_word(mtd));
336 if (chip->badblockpos & 0x1)
49196f33 337 bad >>= 8;
1da177e4
LT		 338 if ((bad & 0xFF) != 0xff)
339 res = 1;
340 } else {
1a12f46a 341 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
ace4dfee 342 if (chip->read_byte(mtd) != 0xff)
1da177e4
LT		 343 res = 1;
344 }
61b03bd7 345
ace4dfee 346 if (getchip)
1da177e4 347 nand_release_device(mtd);
61b03bd7 348
1da177e4
LT		 349 return res;
350}
351
352/**
353 * nand_default_block_markbad - [DEFAULT] mark a block bad
354 * @mtd: MTD device structure
355 * @ofs: offset from device start
356 *
357 * This is the default implementation, which can be overridden by
358 * a hardware specific driver.
359*/
360static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
361{
ace4dfee 362 struct nand_chip *chip = mtd->priv;
58dd8f2b 363 uint8_t buf[2] = { 0, 0 };
f1a28c02 364 int block, ret;
61b03bd7 365
1da177e4 366 /* Get block number */
4226b510 367 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 368 if (chip->bbt)
369 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 370
371 /* Do we have a flash based bad block table ? */
ace4dfee 372 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 373 ret = nand_update_bbt(mtd, ofs);
374 else {
375 /* We write two bytes, so we dont have to mess with 16 bit
376 * access
377 */
c0b8ba7b 378 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 379 ofs += mtd->oobsize;
ff0dab64 380 chip->ops.len = chip->ops.ooblen = 2;
f1a28c02
TG		 381 chip->ops.datbuf = NULL;
382 chip->ops.oobbuf = buf;
383 chip->ops.ooboffs = chip->badblockpos & ~0x01;
384
385 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
c0b8ba7b 386 nand_release_device(mtd);
f1a28c02
TG		 387 }
388 if (!ret)
389 mtd->ecc_stats.badblocks++;
c0b8ba7b 390
f1a28c02 391 return ret;
1da177e4
LT		 392}
393
61b03bd7 394/**
1da177e4
LT		 395 * nand_check_wp - [GENERIC] check if the chip is write protected
396 * @mtd: MTD device structure
61b03bd7 397 * Check, if the device is write protected
1da177e4 398 *
61b03bd7 399 * The function expects, that the device is already selected
1da177e4 400 */
e0c7d767 401static int nand_check_wp(struct mtd_info *mtd)
1da177e4 402{
ace4dfee 403 struct nand_chip *chip = mtd->priv;
1da177e4 404 /* Check the WP bit */
ace4dfee
TG		 405 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
406 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 407}
408
409/**
410 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
411 * @mtd: MTD device structure
412 * @ofs: offset from device start
413 * @getchip: 0, if the chip is already selected
414 * @allowbbt: 1, if its allowed to access the bbt area
415 *
416 * Check, if the block is bad. Either by reading the bad block table or
417 * calling of the scan function.
418 */
2c0a2bed
TG		 419static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 int allowbbt)
1da177e4 421{
ace4dfee 422 struct nand_chip *chip = mtd->priv;
61b03bd7 423
ace4dfee
TG		 424 if (!chip->bbt)
425 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 426
1da177e4 427 /* Return info from the table */
e0c7d767 428 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 429}
430
61b03bd7 431/*
3b88775c
TG		 432 * Wait for the ready pin, after a command
433 * The timeout is catched later.
434 */
4b648b02 435void nand_wait_ready(struct mtd_info *mtd)
3b88775c 436{
ace4dfee 437 struct nand_chip *chip = mtd->priv;
e0c7d767 438 unsigned long timeo = jiffies + 2;
3b88775c 439
8fe833c1 440 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 441 /* wait until command is processed or timeout occures */
442 do {
ace4dfee 443 if (chip->dev_ready(mtd))
8fe833c1 444 break;
8446f1d3 445 touch_softlockup_watchdog();
61b03bd7 446 } while (time_before(jiffies, timeo));
8fe833c1 447 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 448}
4b648b02 449EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 450
1da177e4
LT		 451/**
452 * nand_command - [DEFAULT] Send command to NAND device
453 * @mtd: MTD device structure
454 * @command: the command to be sent
455 * @column: the column address for this command, -1 if none
456 * @page_addr: the page address for this command, -1 if none
457 *
458 * Send command to NAND device. This function is used for small page
459 * devices (256/512 Bytes per page)
460 */
7abd3ef9
TG		 461static void nand_command(struct mtd_info *mtd, unsigned int command,
462 int column, int page_addr)
1da177e4 463{
ace4dfee 464 register struct nand_chip *chip = mtd->priv;
7abd3ef9 465 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 466
1da177e4
LT		 467 /*
468 * Write out the command to the device.
469 */
470 if (command == NAND_CMD_SEQIN) {
471 int readcmd;
472
28318776 473 if (column >= mtd->writesize) {
1da177e4 474 /* OOB area */
28318776 475 column -= mtd->writesize;
1da177e4
LT		 476 readcmd = NAND_CMD_READOOB;
477 } else if (column < 256) {
478 /* First 256 bytes --> READ0 */
479 readcmd = NAND_CMD_READ0;
480 } else {
481 column -= 256;
482 readcmd = NAND_CMD_READ1;
483 }
ace4dfee 484 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 485 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 486 }
ace4dfee 487 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 488
7abd3ef9
TG		 489 /*
490 * Address cycle, when necessary
491 */
492 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
493 /* Serially input address */
494 if (column != -1) {
495 /* Adjust columns for 16 bit buswidth */
ace4dfee 496 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 497 column >>= 1;
ace4dfee 498 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 499 ctrl &= ~NAND_CTRL_CHANGE;
500 }
501 if (page_addr != -1) {
ace4dfee 502 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 503 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 504 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 505 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 506 if (chip->chipsize > (32 << 20))
507 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 508 }
ace4dfee 509 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 510
511 /*
512 * program and erase have their own busy handlers
1da177e4 513 * status and sequential in needs no delay
e0c7d767 514 */
1da177e4 515 switch (command) {
61b03bd7 516
1da177e4
LT		 517 case NAND_CMD_PAGEPROG:
518 case NAND_CMD_ERASE1:
519 case NAND_CMD_ERASE2:
520 case NAND_CMD_SEQIN:
521 case NAND_CMD_STATUS:
522 return;
523
524 case NAND_CMD_RESET:
ace4dfee 525 if (chip->dev_ready)
1da177e4 526 break;
ace4dfee
TG		 527 udelay(chip->chip_delay);
528 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 529 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 530 chip->cmd_ctrl(mtd,
531 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 532 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 533 return;
534
e0c7d767 535 /* This applies to read commands */
1da177e4 536 default:
61b03bd7 537 /*
1da177e4
LT		 538 * If we don't have access to the busy pin, we apply the given
539 * command delay
e0c7d767 540 */
ace4dfee
TG		 541 if (!chip->dev_ready) {
542 udelay(chip->chip_delay);
1da177e4 543 return;
61b03bd7 544 }
1da177e4 545 }
1da177e4
LT		 546 /* Apply this short delay always to ensure that we do wait tWB in
547 * any case on any machine. */
e0c7d767 548 ndelay(100);
3b88775c
TG		 549
550 nand_wait_ready(mtd);
1da177e4
LT		 551}
552
553/**
554 * nand_command_lp - [DEFAULT] Send command to NAND large page device
555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
559 *
7abd3ef9
TG		 560 * Send command to NAND device. This is the version for the new large page
561 * devices We dont have the separate regions as we have in the small page
562 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 563 */
7abd3ef9
TG		 564static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
565 int column, int page_addr)
1da177e4 566{
ace4dfee 567 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 568
569 /* Emulate NAND_CMD_READOOB */
570 if (command == NAND_CMD_READOOB) {
28318776 571 column += mtd->writesize;
1da177e4
LT		 572 command = NAND_CMD_READ0;
573 }
61b03bd7 574
7abd3ef9 575 /* Command latch cycle */
ace4dfee 576 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 577 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 578
579 if (column != -1 || page_addr != -1) {
7abd3ef9 580 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 581
582 /* Serially input address */
583 if (column != -1) {
584 /* Adjust columns for 16 bit buswidth */
ace4dfee 585 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 586 column >>= 1;
ace4dfee 587 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 588 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 589 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 590 }
1da177e4 591 if (page_addr != -1) {
ace4dfee
TG		 592 chip->cmd_ctrl(mtd, page_addr, ctrl);
593 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 594 NAND_NCE | NAND_ALE);
1da177e4 595 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 596 if (chip->chipsize > (128 << 20))
597 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 598 NAND_NCE | NAND_ALE);
1da177e4 599 }
1da177e4 600 }
ace4dfee 601 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 602
603 /*
604 * program and erase have their own busy handlers
30f464b7
DM		 605 * status, sequential in, and deplete1 need no delay
606 */
1da177e4 607 switch (command) {
61b03bd7 608
1da177e4
LT		 609 case NAND_CMD_CACHEDPROG:
610 case NAND_CMD_PAGEPROG:
611 case NAND_CMD_ERASE1:
612 case NAND_CMD_ERASE2:
613 case NAND_CMD_SEQIN:
7bc3312b 614 case NAND_CMD_RNDIN:
1da177e4 615 case NAND_CMD_STATUS:
30f464b7 616 case NAND_CMD_DEPLETE1:
1da177e4
LT		 617 return;
618
e0c7d767
DW		 619 /*
620 * read error status commands require only a short delay
621 */
30f464b7
DM		 622 case NAND_CMD_STATUS_ERROR:
623 case NAND_CMD_STATUS_ERROR0:
624 case NAND_CMD_STATUS_ERROR1:
625 case NAND_CMD_STATUS_ERROR2:
626 case NAND_CMD_STATUS_ERROR3:
ace4dfee 627 udelay(chip->chip_delay);
30f464b7 628 return;
1da177e4
LT		 629
630 case NAND_CMD_RESET:
ace4dfee 631 if (chip->dev_ready)
1da177e4 632 break;
ace4dfee 633 udelay(chip->chip_delay);
12efdde3
TG		 634 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
635 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
636 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
637 NAND_NCE | NAND_CTRL_CHANGE);
ace4dfee 638 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
1da177e4
LT		 639 return;
640
7bc3312b
TG		 641 case NAND_CMD_RNDOUT:
642 /* No ready / busy check necessary */
643 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
644 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
645 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
646 NAND_NCE | NAND_CTRL_CHANGE);
647 return;
648
1da177e4 649 case NAND_CMD_READ0:
12efdde3
TG		 650 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
651 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 654
e0c7d767 655 /* This applies to read commands */
1da177e4 656 default:
61b03bd7 657 /*
1da177e4
LT		 658 * If we don't have access to the busy pin, we apply the given
659 * command delay
e0c7d767 660 */
ace4dfee
TG		 661 if (!chip->dev_ready) {
662 udelay(chip->chip_delay);
1da177e4 663 return;
61b03bd7 664 }
1da177e4 665 }
3b88775c 666
1da177e4
LT		 667 /* Apply this short delay always to ensure that we do wait tWB in
668 * any case on any machine. */
e0c7d767 669 ndelay(100);
3b88775c
TG		 670
671 nand_wait_ready(mtd);
1da177e4
LT		 672}
673
674/**
675 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 676 * @chip: the nand chip descriptor
1da177e4 677 * @mtd: MTD device structure
61b03bd7 678 * @new_state: the state which is requested
1da177e4
LT		 679 *
680 * Get the device and lock it for exclusive access
681 */
2c0a2bed 682static int
ace4dfee 683nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 684{
ace4dfee
TG		 685 spinlock_t *lock = &chip->controller->lock;
686 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 687 DECLARE_WAITQUEUE(wait, current);
e0c7d767 688 retry:
0dfc6246
TG		 689 spin_lock(lock);
690
1da177e4 691 /* Hardware controller shared among independend devices */
a36ed299 692 /* Hardware controller shared among independend devices */
ace4dfee
TG		 693 if (!chip->controller->active)
694 chip->controller->active = chip;
a36ed299 695
ace4dfee
TG		 696 if (chip->controller->active == chip && chip->state == FL_READY) {
697 chip->state = new_state;
0dfc6246 698 spin_unlock(lock);
962034f4
VW		 699 return 0;
700 }
701 if (new_state == FL_PM_SUSPENDED) {
702 spin_unlock(lock);
ace4dfee 703 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
0dfc6246
TG		 704 }
705 set_current_state(TASK_UNINTERRUPTIBLE);
706 add_wait_queue(wq, &wait);
707 spin_unlock(lock);
708 schedule();
709 remove_wait_queue(wq, &wait);
1da177e4
LT		 710 goto retry;
711}
712
713/**
714 * nand_wait - [DEFAULT] wait until the command is done
715 * @mtd: MTD device structure
844d3b42 716 * @chip: NAND chip structure
1da177e4
LT		 717 *
718 * Wait for command done. This applies to erase and program only
61b03bd7 719 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 720 * general NAND and SmartMedia specs
844d3b42 721 */
7bc3312b 722static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 723{
724
e0c7d767 725 unsigned long timeo = jiffies;
7bc3312b 726 int status, state = chip->state;
61b03bd7 727
1da177e4 728 if (state == FL_ERASING)
e0c7d767 729 timeo += (HZ * 400) / 1000;
1da177e4 730 else
e0c7d767 731 timeo += (HZ * 20) / 1000;
1da177e4 732
8fe833c1
RP		 733 led_trigger_event(nand_led_trigger, LED_FULL);
734
1da177e4
LT		 735 /* Apply this short delay always to ensure that we do wait tWB in
736 * any case on any machine. */
e0c7d767 737 ndelay(100);
1da177e4 738
ace4dfee
TG		 739 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
740 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 741 else
ace4dfee 742 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 743
61b03bd7 744 while (time_before(jiffies, timeo)) {
ace4dfee
TG		 745 if (chip->dev_ready) {
746 if (chip->dev_ready(mtd))
61b03bd7 747 break;
1da177e4 748 } else {
ace4dfee 749 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1da177e4
LT		 750 break;
751 }
20a6c211 752 cond_resched();
1da177e4 753 }
8fe833c1
RP		 754 led_trigger_event(nand_led_trigger, LED_OFF);
755
ace4dfee 756 status = (int)chip->read_byte(mtd);
1da177e4
LT		 757 return status;
758}
759
8593fbc6
TG		 760/**
761 * nand_read_page_raw - [Intern] read raw page data without ecc
762 * @mtd: mtd info structure
763 * @chip: nand chip info structure
764 * @buf: buffer to store read data
52ff49df
DB		 765 *
766 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 767 */
768static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
769 uint8_t *buf)
770{
771 chip->read_buf(mtd, buf, mtd->writesize);
772 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
773 return 0;
774}
775
52ff49df
DB		 776/**
777 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
778 * @mtd: mtd info structure
779 * @chip: nand chip info structure
780 * @buf: buffer to store read data
781 *
782 * We need a special oob layout and handling even when OOB isn't used.
783 */
784static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
785 uint8_t *buf)
786{
787 int eccsize = chip->ecc.size;
788 int eccbytes = chip->ecc.bytes;
789 uint8_t *oob = chip->oob_poi;
790 int steps, size;
791
792 for (steps = chip->ecc.steps; steps > 0; steps--) {
793 chip->read_buf(mtd, buf, eccsize);
794 buf += eccsize;
795
796 if (chip->ecc.prepad) {
797 chip->read_buf(mtd, oob, chip->ecc.prepad);
798 oob += chip->ecc.prepad;
799 }
800
801 chip->read_buf(mtd, oob, eccbytes);
802 oob += eccbytes;
803
804 if (chip->ecc.postpad) {
805 chip->read_buf(mtd, oob, chip->ecc.postpad);
806 oob += chip->ecc.postpad;
807 }
808 }
809
810 size = mtd->oobsize - (oob - chip->oob_poi);
811 if (size)
812 chip->read_buf(mtd, oob, size);
813
814 return 0;
815}
816
1da177e4 817/**
d29ebdbe 818 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 819 * @mtd: mtd info structure
820 * @chip: nand chip info structure
821 * @buf: buffer to store read data
068e3c0a 822 */
f5bbdacc
TG		 823static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
824 uint8_t *buf)
1da177e4 825{
f5bbdacc
TG		 826 int i, eccsize = chip->ecc.size;
827 int eccbytes = chip->ecc.bytes;
828 int eccsteps = chip->ecc.steps;
829 uint8_t *p = buf;
4bf63fcb
DW		 830 uint8_t *ecc_calc = chip->buffers->ecccalc;
831 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 832 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 833
90424de8 834 chip->ecc.read_page_raw(mtd, chip, buf);
f5bbdacc
TG		 835
836 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
837 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
838
839 for (i = 0; i < chip->ecc.total; i++)
f75e5097 840 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 841
842 eccsteps = chip->ecc.steps;
843 p = buf;
844
845 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
846 int stat;
847
848 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 849 if (stat < 0)
f5bbdacc
TG		 850 mtd->ecc_stats.failed++;
851 else
852 mtd->ecc_stats.corrected += stat;
853 }
854 return 0;
22c60f5f 855}
1da177e4 856
3d459559
AK		 857/**
858 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
859 * @mtd: mtd info structure
860 * @chip: nand chip info structure
17c1d2be
AK		 861 * @data_offs: offset of requested data within the page
862 * @readlen: data length
863 * @bufpoi: buffer to store read data
3d459559
AK		 864 */
865static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
866{
867 int start_step, end_step, num_steps;
868 uint32_t *eccpos = chip->ecc.layout->eccpos;
869 uint8_t *p;
870 int data_col_addr, i, gaps = 0;
871 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
872 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
873
874 /* Column address wihin the page aligned to ECC size (256bytes). */
875 start_step = data_offs / chip->ecc.size;
876 end_step = (data_offs + readlen - 1) / chip->ecc.size;
877 num_steps = end_step - start_step + 1;
878
879 /* Data size aligned to ECC ecc.size*/
880 datafrag_len = num_steps * chip->ecc.size;
881 eccfrag_len = num_steps * chip->ecc.bytes;
882
883 data_col_addr = start_step * chip->ecc.size;
884 /* If we read not a page aligned data */
885 if (data_col_addr != 0)
886 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
887
888 p = bufpoi + data_col_addr;
889 chip->read_buf(mtd, p, datafrag_len);
890
891 /* Calculate ECC */
892 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
893 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
894
895 /* The performance is faster if to position offsets
896 according to ecc.pos. Let make sure here that
897 there are no gaps in ecc positions */
898 for (i = 0; i < eccfrag_len - 1; i++) {
899 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
900 eccpos[i + start_step * chip->ecc.bytes + 1]) {
901 gaps = 1;
902 break;
903 }
904 }
905 if (gaps) {
906 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
907 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
908 } else {
909 /* send the command to read the particular ecc bytes */
910 /* take care about buswidth alignment in read_buf */
911 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
912 aligned_len = eccfrag_len;
913 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
914 aligned_len++;
915 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
916 aligned_len++;
917
918 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
919 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
920 }
921
922 for (i = 0; i < eccfrag_len; i++)
923 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
924
925 p = bufpoi + data_col_addr;
926 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
927 int stat;
928
929 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
930 if (stat == -1)
931 mtd->ecc_stats.failed++;
932 else
933 mtd->ecc_stats.corrected += stat;
934 }
935 return 0;
936}
937
068e3c0a 938/**
d29ebdbe 939 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 940 * @mtd: mtd info structure
941 * @chip: nand chip info structure
942 * @buf: buffer to store read data
068e3c0a 943 *
f5bbdacc 944 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 945 */
f5bbdacc
TG		 946static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
947 uint8_t *buf)
1da177e4 948{
f5bbdacc
TG		 949 int i, eccsize = chip->ecc.size;
950 int eccbytes = chip->ecc.bytes;
951 int eccsteps = chip->ecc.steps;
952 uint8_t *p = buf;
4bf63fcb
DW		 953 uint8_t *ecc_calc = chip->buffers->ecccalc;
954 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 955 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 956
957 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
958 chip->ecc.hwctl(mtd, NAND_ECC_READ);
959 chip->read_buf(mtd, p, eccsize);
960 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 961 }
f75e5097 962 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 963
f5bbdacc 964 for (i = 0; i < chip->ecc.total; i++)
f75e5097 965 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 966
f5bbdacc
TG		 967 eccsteps = chip->ecc.steps;
968 p = buf;
61b03bd7 969
f5bbdacc
TG		 970 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
971 int stat;
1da177e4 972
f5bbdacc 973 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 974 if (stat < 0)
f5bbdacc
TG		 975 mtd->ecc_stats.failed++;
976 else
977 mtd->ecc_stats.corrected += stat;
978 }
979 return 0;
980}
1da177e4 981
f5bbdacc 982/**
d29ebdbe 983 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 984 * @mtd: mtd info structure
985 * @chip: nand chip info structure
986 * @buf: buffer to store read data
987 *
988 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 989 * we need a special oob layout and handling.
f5bbdacc
TG		 990 */
991static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
992 uint8_t *buf)
993{
994 int i, eccsize = chip->ecc.size;
995 int eccbytes = chip->ecc.bytes;
996 int eccsteps = chip->ecc.steps;
997 uint8_t *p = buf;
f75e5097 998 uint8_t *oob = chip->oob_poi;
1da177e4 999
f5bbdacc
TG		 1000 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1001 int stat;
61b03bd7 1002
f5bbdacc
TG		 1003 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1004 chip->read_buf(mtd, p, eccsize);
1da177e4 1005
f5bbdacc
TG		 1006 if (chip->ecc.prepad) {
1007 chip->read_buf(mtd, oob, chip->ecc.prepad);
1008 oob += chip->ecc.prepad;
1009 }
1da177e4 1010
f5bbdacc
TG		 1011 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1012 chip->read_buf(mtd, oob, eccbytes);
1013 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1014
c32b8dcc 1015 if (stat < 0)
f5bbdacc 1016 mtd->ecc_stats.failed++;
61b03bd7 1017 else
f5bbdacc 1018 mtd->ecc_stats.corrected += stat;
61b03bd7 1019
f5bbdacc 1020 oob += eccbytes;
1da177e4 1021
f5bbdacc
TG		 1022 if (chip->ecc.postpad) {
1023 chip->read_buf(mtd, oob, chip->ecc.postpad);
1024 oob += chip->ecc.postpad;
61b03bd7 1025 }
f5bbdacc 1026 }
1da177e4 1027
f5bbdacc 1028 /* Calculate remaining oob bytes */
7e4178f9 1029 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1030 if (i)
1031 chip->read_buf(mtd, oob, i);
61b03bd7 1032
f5bbdacc
TG		 1033 return 0;
1034}
1da177e4 1035
f5bbdacc 1036/**
8593fbc6
TG		 1037 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1038 * @chip: nand chip structure
844d3b42 1039 * @oob: oob destination address
8593fbc6 1040 * @ops: oob ops structure
7014568b 1041 * @len: size of oob to transfer
8593fbc6
TG		 1042 */
1043static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1044 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1045{
8593fbc6
TG		 1046 switch(ops->mode) {
1047
1048 case MTD_OOB_PLACE:
1049 case MTD_OOB_RAW:
1050 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1051 return oob + len;
1052
1053 case MTD_OOB_AUTO: {
1054 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1055 uint32_t boffs = 0, roffs = ops->ooboffs;
1056 size_t bytes = 0;
8593fbc6
TG		 1057
1058 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1059 /* Read request not from offset 0 ? */
1060 if (unlikely(roffs)) {
1061 if (roffs >= free->length) {
1062 roffs -= free->length;
1063 continue;
1064 }
1065 boffs = free->offset + roffs;
1066 bytes = min_t(size_t, len,
1067 (free->length - roffs));
1068 roffs = 0;
1069 } else {
1070 bytes = min_t(size_t, len, free->length);
1071 boffs = free->offset;
1072 }
1073 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1074 oob += bytes;
1075 }
1076 return oob;
1077 }
1078 default:
1079 BUG();
1080 }
1081 return NULL;
1082}
1083
1084/**
1085 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1086 *
1087 * @mtd: MTD device structure
1088 * @from: offset to read from
844d3b42 1089 * @ops: oob ops structure
f5bbdacc
TG		 1090 *
1091 * Internal function. Called with chip held.
1092 */
8593fbc6
TG		 1093static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1094 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1095{
1096 int chipnr, page, realpage, col, bytes, aligned;
1097 struct nand_chip *chip = mtd->priv;
1098 struct mtd_ecc_stats stats;
1099 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1100 int sndcmd = 1;
1101 int ret = 0;
8593fbc6 1102 uint32_t readlen = ops->len;
7014568b 1103 uint32_t oobreadlen = ops->ooblen;
8593fbc6 1104 uint8_t *bufpoi, *oob, *buf;
1da177e4 1105
f5bbdacc 1106 stats = mtd->ecc_stats;
1da177e4 1107
f5bbdacc
TG		 1108 chipnr = (int)(from >> chip->chip_shift);
1109 chip->select_chip(mtd, chipnr);
61b03bd7 1110
f5bbdacc
TG		 1111 realpage = (int)(from >> chip->page_shift);
1112 page = realpage & chip->pagemask;
1da177e4 1113
f5bbdacc 1114 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1115
8593fbc6
TG		 1116 buf = ops->datbuf;
1117 oob = ops->oobbuf;
1118
f5bbdacc
TG		 1119 while(1) {
1120 bytes = min(mtd->writesize - col, readlen);
1121 aligned = (bytes == mtd->writesize);
61b03bd7 1122
f5bbdacc 1123 /* Is the current page in the buffer ? */
8593fbc6 1124 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1125 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1126
f5bbdacc
TG		 1127 if (likely(sndcmd)) {
1128 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1129 sndcmd = 0;
1da177e4 1130 }
1da177e4 1131
f5bbdacc 1132 /* Now read the page into the buffer */
956e944c
DW		 1133 if (unlikely(ops->mode == MTD_OOB_RAW))
1134 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
3d459559
AK		 1135 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1136 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
956e944c
DW		 1137 else
1138 ret = chip->ecc.read_page(mtd, chip, bufpoi);
f5bbdacc 1139 if (ret < 0)
1da177e4 1140 break;
f5bbdacc
TG		 1141
1142 /* Transfer not aligned data */
1143 if (!aligned) {
3d459559
AK		 1144 if (!NAND_SUBPAGE_READ(chip) && !oob)
1145 chip->pagebuf = realpage;
4bf63fcb 1146 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1147 }
1148
8593fbc6
TG		 1149 buf += bytes;
1150
1151 if (unlikely(oob)) {
1152 /* Raw mode does data:oob:data:oob */
7014568b
VW		 1153 if (ops->mode != MTD_OOB_RAW) {
1154 int toread = min(oobreadlen,
1155 chip->ecc.layout->oobavail);
1156 if (toread) {
1157 oob = nand_transfer_oob(chip,
1158 oob, ops, toread);
1159 oobreadlen -= toread;
1160 }
1161 } else
1162 buf = nand_transfer_oob(chip,
1163 buf, ops, mtd->oobsize);
8593fbc6
TG		 1164 }
1165
f5bbdacc
TG		 1166 if (!(chip->options & NAND_NO_READRDY)) {
1167 /*
1168 * Apply delay or wait for ready/busy pin. Do
1169 * this before the AUTOINCR check, so no
1170 * problems arise if a chip which does auto
1171 * increment is marked as NOAUTOINCR by the
1172 * board driver.
1173 */
1174 if (!chip->dev_ready)
1175 udelay(chip->chip_delay);
1176 else
1177 nand_wait_ready(mtd);
1da177e4 1178 }
8593fbc6 1179 } else {
4bf63fcb 1180 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1181 buf += bytes;
1182 }
1da177e4 1183
f5bbdacc 1184 readlen -= bytes;
61b03bd7 1185
f5bbdacc 1186 if (!readlen)
61b03bd7 1187 break;
1da177e4
LT		 1188
1189 /* For subsequent reads align to page boundary. */
1190 col = 0;
1191 /* Increment page address */
1192 realpage++;
1193
ace4dfee 1194 page = realpage & chip->pagemask;
1da177e4
LT		 1195 /* Check, if we cross a chip boundary */
1196 if (!page) {
1197 chipnr++;
ace4dfee
TG		 1198 chip->select_chip(mtd, -1);
1199 chip->select_chip(mtd, chipnr);
1da177e4 1200 }
f5bbdacc 1201
61b03bd7
TG		 1202 /* Check, if the chip supports auto page increment
1203 * or if we have hit a block boundary.
e0c7d767 1204 */
f5bbdacc 1205 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1206 sndcmd = 1;
1da177e4
LT		 1207 }
1208
8593fbc6 1209 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1210 if (oob)
1211 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1212
f5bbdacc
TG		 1213 if (ret)
1214 return ret;
1215
9a1fcdfd
TG		 1216 if (mtd->ecc_stats.failed - stats.failed)
1217 return -EBADMSG;
1218
1219 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1220}
1221
1222/**
1223 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1224 * @mtd: MTD device structure
1225 * @from: offset to read from
1226 * @len: number of bytes to read
1227 * @retlen: pointer to variable to store the number of read bytes
1228 * @buf: the databuffer to put data
1229 *
1230 * Get hold of the chip and call nand_do_read
1231 */
1232static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1233 size_t *retlen, uint8_t *buf)
1234{
8593fbc6 1235 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1236 int ret;
1237
f5bbdacc
TG		 1238 /* Do not allow reads past end of device */
1239 if ((from + len) > mtd->size)
1240 return -EINVAL;
1241 if (!len)
1242 return 0;
1243
8593fbc6 1244 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1245
8593fbc6
TG		 1246 chip->ops.len = len;
1247 chip->ops.datbuf = buf;
1248 chip->ops.oobbuf = NULL;
1249
1250 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1251
7fd5aecc
RP		 1252 *retlen = chip->ops.retlen;
1253
f5bbdacc
TG		 1254 nand_release_device(mtd);
1255
1256 return ret;
1da177e4
LT		 1257}
1258
7bc3312b
TG		 1259/**
1260 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1261 * @mtd: mtd info structure
1262 * @chip: nand chip info structure
1263 * @page: page number to read
1264 * @sndcmd: flag whether to issue read command or not
1265 */
1266static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1267 int page, int sndcmd)
1268{
1269 if (sndcmd) {
1270 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1271 sndcmd = 0;
1272 }
1273 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1274 return sndcmd;
1275}
1276
1277/**
1278 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1279 * with syndromes
1280 * @mtd: mtd info structure
1281 * @chip: nand chip info structure
1282 * @page: page number to read
1283 * @sndcmd: flag whether to issue read command or not
1284 */
1285static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1286 int page, int sndcmd)
1287{
1288 uint8_t *buf = chip->oob_poi;
1289 int length = mtd->oobsize;
1290 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1291 int eccsize = chip->ecc.size;
1292 uint8_t *bufpoi = buf;
1293 int i, toread, sndrnd = 0, pos;
1294
1295 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1296 for (i = 0; i < chip->ecc.steps; i++) {
1297 if (sndrnd) {
1298 pos = eccsize + i * (eccsize + chunk);
1299 if (mtd->writesize > 512)
1300 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1301 else
1302 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1303 } else
1304 sndrnd = 1;
1305 toread = min_t(int, length, chunk);
1306 chip->read_buf(mtd, bufpoi, toread);
1307 bufpoi += toread;
1308 length -= toread;
1309 }
1310 if (length > 0)
1311 chip->read_buf(mtd, bufpoi, length);
1312
1313 return 1;
1314}
1315
1316/**
1317 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1318 * @mtd: mtd info structure
1319 * @chip: nand chip info structure
1320 * @page: page number to write
1321 */
1322static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1323 int page)
1324{
1325 int status = 0;
1326 const uint8_t *buf = chip->oob_poi;
1327 int length = mtd->oobsize;
1328
1329 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1330 chip->write_buf(mtd, buf, length);
1331 /* Send command to program the OOB data */
1332 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1333
1334 status = chip->waitfunc(mtd, chip);
1335
0d420f9d 1336 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1337}
1338
1339/**
1340 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1341 * with syndrome - only for large page flash !
1342 * @mtd: mtd info structure
1343 * @chip: nand chip info structure
1344 * @page: page number to write
1345 */
1346static int nand_write_oob_syndrome(struct mtd_info *mtd,
1347 struct nand_chip *chip, int page)
1348{
1349 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1350 int eccsize = chip->ecc.size, length = mtd->oobsize;
1351 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1352 const uint8_t *bufpoi = chip->oob_poi;
1353
1354 /*
1355 * data-ecc-data-ecc ... ecc-oob
1356 * or
1357 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1358 */
1359 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1360 pos = steps * (eccsize + chunk);
1361 steps = 0;
1362 } else
8b0036ee 1363 pos = eccsize;
7bc3312b
TG		 1364
1365 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1366 for (i = 0; i < steps; i++) {
1367 if (sndcmd) {
1368 if (mtd->writesize <= 512) {
1369 uint32_t fill = 0xFFFFFFFF;
1370
1371 len = eccsize;
1372 while (len > 0) {
1373 int num = min_t(int, len, 4);
1374 chip->write_buf(mtd, (uint8_t *)&fill,
1375 num);
1376 len -= num;
1377 }
1378 } else {
1379 pos = eccsize + i * (eccsize + chunk);
1380 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1381 }
1382 } else
1383 sndcmd = 1;
1384 len = min_t(int, length, chunk);
1385 chip->write_buf(mtd, bufpoi, len);
1386 bufpoi += len;
1387 length -= len;
1388 }
1389 if (length > 0)
1390 chip->write_buf(mtd, bufpoi, length);
1391
1392 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1393 status = chip->waitfunc(mtd, chip);
1394
1395 return status & NAND_STATUS_FAIL ? -EIO : 0;
1396}
1397
1da177e4 1398/**
8593fbc6 1399 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1400 * @mtd: MTD device structure
1401 * @from: offset to read from
8593fbc6 1402 * @ops: oob operations description structure
1da177e4
LT		 1403 *
1404 * NAND read out-of-band data from the spare area
1405 */
8593fbc6
TG		 1406static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1407 struct mtd_oob_ops *ops)
1da177e4 1408{
7bc3312b 1409 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1410 struct nand_chip *chip = mtd->priv;
7314e9e7 1411 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1412 int readlen = ops->ooblen;
1413 int len;
7bc3312b 1414 uint8_t *buf = ops->oobbuf;
61b03bd7 1415
7e9a0bb0
AM		 1416 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1417 (unsigned long long)from, readlen);
1da177e4 1418
03736155 1419 if (ops->mode == MTD_OOB_AUTO)
7014568b 1420 len = chip->ecc.layout->oobavail;
03736155
AH		 1421 else
1422 len = mtd->oobsize;
1423
1424 if (unlikely(ops->ooboffs >= len)) {
1425 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1426 "Attempt to start read outside oob\n");
1427 return -EINVAL;
1428 }
1429
1430 /* Do not allow reads past end of device */
1431 if (unlikely(from >= mtd->size ||
1432 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1433 (from >> chip->page_shift)) * len)) {
1434 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1435 "Attempt read beyond end of device\n");
1436 return -EINVAL;
1437 }
7014568b 1438
7314e9e7 1439 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1440 chip->select_chip(mtd, chipnr);
1da177e4 1441
7314e9e7
TG		 1442 /* Shift to get page */
1443 realpage = (int)(from >> chip->page_shift);
1444 page = realpage & chip->pagemask;
1da177e4 1445
7314e9e7 1446 while(1) {
7bc3312b 1447 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1448
1449 len = min(len, readlen);
1450 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1451
7314e9e7
TG		 1452 if (!(chip->options & NAND_NO_READRDY)) {
1453 /*
1454 * Apply delay or wait for ready/busy pin. Do this
1455 * before the AUTOINCR check, so no problems arise if a
1456 * chip which does auto increment is marked as
1457 * NOAUTOINCR by the board driver.
19870da7 1458 */
ace4dfee
TG		 1459 if (!chip->dev_ready)
1460 udelay(chip->chip_delay);
19870da7
TG		 1461 else
1462 nand_wait_ready(mtd);
7314e9e7 1463 }
19870da7 1464
7014568b 1465 readlen -= len;
0d420f9d
SZ		 1466 if (!readlen)
1467 break;
1468
7314e9e7
TG		 1469 /* Increment page address */
1470 realpage++;
1471
1472 page = realpage & chip->pagemask;
1473 /* Check, if we cross a chip boundary */
1474 if (!page) {
1475 chipnr++;
1476 chip->select_chip(mtd, -1);
1477 chip->select_chip(mtd, chipnr);
1da177e4 1478 }
7314e9e7
TG		 1479
1480 /* Check, if the chip supports auto page increment
1481 * or if we have hit a block boundary.
1482 */
1483 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1484 sndcmd = 1;
1da177e4
LT		 1485 }
1486
7014568b 1487 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1488 return 0;
1489}
1490
1491/**
8593fbc6 1492 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1493 * @mtd: MTD device structure
1da177e4 1494 * @from: offset to read from
8593fbc6 1495 * @ops: oob operation description structure
1da177e4 1496 *
8593fbc6 1497 * NAND read data and/or out-of-band data
1da177e4 1498 */
8593fbc6
TG		 1499static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1500 struct mtd_oob_ops *ops)
1da177e4 1501{
ace4dfee 1502 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1503 int ret = -ENOTSUPP;
1504
1505 ops->retlen = 0;
1da177e4
LT		 1506
1507 /* Do not allow reads past end of device */
7014568b 1508 if (ops->datbuf && (from + ops->len) > mtd->size) {
8593fbc6 1509 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
ace4dfee 1510 "Attempt read beyond end of device\n");
1da177e4
LT		 1511 return -EINVAL;
1512 }
1513
ace4dfee 1514 nand_get_device(chip, mtd, FL_READING);
1da177e4 1515
8593fbc6
TG		 1516 switch(ops->mode) {
1517 case MTD_OOB_PLACE:
1518 case MTD_OOB_AUTO:
8593fbc6 1519 case MTD_OOB_RAW:
8593fbc6 1520 break;
1da177e4 1521
8593fbc6
TG		 1522 default:
1523 goto out;
1524 }
1da177e4 1525
8593fbc6
TG		 1526 if (!ops->datbuf)
1527 ret = nand_do_read_oob(mtd, from, ops);
1528 else
1529 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1530
8593fbc6
TG		 1531 out:
1532 nand_release_device(mtd);
1533 return ret;
1534}
61b03bd7 1535
1da177e4 1536
8593fbc6
TG		 1537/**
1538 * nand_write_page_raw - [Intern] raw page write function
1539 * @mtd: mtd info structure
1540 * @chip: nand chip info structure
1541 * @buf: data buffer
52ff49df
DB		 1542 *
1543 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1544 */
1545static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1546 const uint8_t *buf)
1547{
1548 chip->write_buf(mtd, buf, mtd->writesize);
1549 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1550}
1551
52ff49df
DB		 1552/**
1553 * nand_write_page_raw_syndrome - [Intern] raw page write function
1554 * @mtd: mtd info structure
1555 * @chip: nand chip info structure
1556 * @buf: data buffer
1557 *
1558 * We need a special oob layout and handling even when ECC isn't checked.
1559 */
1560static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1561 const uint8_t *buf)
1562{
1563 int eccsize = chip->ecc.size;
1564 int eccbytes = chip->ecc.bytes;
1565 uint8_t *oob = chip->oob_poi;
1566 int steps, size;
1567
1568 for (steps = chip->ecc.steps; steps > 0; steps--) {
1569 chip->write_buf(mtd, buf, eccsize);
1570 buf += eccsize;
1571
1572 if (chip->ecc.prepad) {
1573 chip->write_buf(mtd, oob, chip->ecc.prepad);
1574 oob += chip->ecc.prepad;
1575 }
1576
1577 chip->read_buf(mtd, oob, eccbytes);
1578 oob += eccbytes;
1579
1580 if (chip->ecc.postpad) {
1581 chip->write_buf(mtd, oob, chip->ecc.postpad);
1582 oob += chip->ecc.postpad;
1583 }
1584 }
1585
1586 size = mtd->oobsize - (oob - chip->oob_poi);
1587 if (size)
1588 chip->write_buf(mtd, oob, size);
1589}
9223a456 1590/**
d29ebdbe 1591 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1592 * @mtd: mtd info structure
1593 * @chip: nand chip info structure
1594 * @buf: data buffer
9223a456 1595 */
f75e5097
TG		 1596static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1597 const uint8_t *buf)
9223a456 1598{
f75e5097
TG		 1599 int i, eccsize = chip->ecc.size;
1600 int eccbytes = chip->ecc.bytes;
1601 int eccsteps = chip->ecc.steps;
4bf63fcb 1602 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1603 const uint8_t *p = buf;
8b099a39 1604 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1605
8593fbc6
TG		 1606 /* Software ecc calculation */
1607 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1608 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1609
8593fbc6
TG		 1610 for (i = 0; i < chip->ecc.total; i++)
1611 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1612
90424de8 1613 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1614}
9223a456 1615
f75e5097 1616/**
d29ebdbe 1617 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1618 * @mtd: mtd info structure
1619 * @chip: nand chip info structure
1620 * @buf: data buffer
1621 */
1622static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1623 const uint8_t *buf)
1624{
1625 int i, eccsize = chip->ecc.size;
1626 int eccbytes = chip->ecc.bytes;
1627 int eccsteps = chip->ecc.steps;
4bf63fcb 1628 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1629 const uint8_t *p = buf;
8b099a39 1630 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1631
f75e5097
TG		 1632 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1633 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1634 chip->write_buf(mtd, p, eccsize);
f75e5097 1635 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1636 }
1637
f75e5097
TG		 1638 for (i = 0; i < chip->ecc.total; i++)
1639 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1640
1641 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1642}
1643
61b03bd7 1644/**
d29ebdbe 1645 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1646 * @mtd: mtd info structure
1647 * @chip: nand chip info structure
1648 * @buf: data buffer
1da177e4 1649 *
f75e5097
TG		 1650 * The hw generator calculates the error syndrome automatically. Therefor
1651 * we need a special oob layout and handling.
1652 */
1653static void nand_write_page_syndrome(struct mtd_info *mtd,
1654 struct nand_chip *chip, const uint8_t *buf)
1da177e4 1655{
f75e5097
TG		 1656 int i, eccsize = chip->ecc.size;
1657 int eccbytes = chip->ecc.bytes;
1658 int eccsteps = chip->ecc.steps;
1659 const uint8_t *p = buf;
1660 uint8_t *oob = chip->oob_poi;
1da177e4 1661
f75e5097 1662 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 1663
f75e5097
TG		 1664 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1665 chip->write_buf(mtd, p, eccsize);
61b03bd7 1666
f75e5097
TG		 1667 if (chip->ecc.prepad) {
1668 chip->write_buf(mtd, oob, chip->ecc.prepad);
1669 oob += chip->ecc.prepad;
1670 }
1671
1672 chip->ecc.calculate(mtd, p, oob);
1673 chip->write_buf(mtd, oob, eccbytes);
1674 oob += eccbytes;
1675
1676 if (chip->ecc.postpad) {
1677 chip->write_buf(mtd, oob, chip->ecc.postpad);
1678 oob += chip->ecc.postpad;
1da177e4 1679 }
1da177e4 1680 }
f75e5097
TG		 1681
1682 /* Calculate remaining oob bytes */
7e4178f9 1683 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 1684 if (i)
1685 chip->write_buf(mtd, oob, i);
1686}
1687
1688/**
956e944c 1689 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 1690 * @mtd: MTD device structure
1691 * @chip: NAND chip descriptor
1692 * @buf: the data to write
1693 * @page: page number to write
1694 * @cached: cached programming
efbfe96c 1695 * @raw: use _raw version of write_page
f75e5097
TG		 1696 */
1697static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 1698 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 1699{
1700 int status;
1701
1702 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1703
956e944c
DW		 1704 if (unlikely(raw))
1705 chip->ecc.write_page_raw(mtd, chip, buf);
1706 else
1707 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 1708
1709 /*
1710 * Cached progamming disabled for now, Not sure if its worth the
1711 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1712 */
1713 cached = 0;
1714
1715 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1716
1717 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 1718 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1719 /*
1720 * See if operation failed and additional status checks are
1721 * available
1722 */
1723 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1724 status = chip->errstat(mtd, chip, FL_WRITING, status,
1725 page);
1726
1727 if (status & NAND_STATUS_FAIL)
1728 return -EIO;
1729 } else {
1730 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 1731 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 1732 }
1733
1734#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1735 /* Send command to read back the data */
1736 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1737
1738 if (chip->verify_buf(mtd, buf, mtd->writesize))
1739 return -EIO;
1740#endif
1741 return 0;
1da177e4
LT		 1742}
1743
8593fbc6
TG		 1744/**
1745 * nand_fill_oob - [Internal] Transfer client buffer to oob
1746 * @chip: nand chip structure
1747 * @oob: oob data buffer
1748 * @ops: oob ops structure
1749 */
1750static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1751 struct mtd_oob_ops *ops)
1752{
1753 size_t len = ops->ooblen;
1754
1755 switch(ops->mode) {
1756
1757 case MTD_OOB_PLACE:
1758 case MTD_OOB_RAW:
1759 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1760 return oob + len;
1761
1762 case MTD_OOB_AUTO: {
1763 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1764 uint32_t boffs = 0, woffs = ops->ooboffs;
1765 size_t bytes = 0;
8593fbc6
TG		 1766
1767 for(; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1768 /* Write request not from offset 0 ? */
1769 if (unlikely(woffs)) {
1770 if (woffs >= free->length) {
1771 woffs -= free->length;
1772 continue;
1773 }
1774 boffs = free->offset + woffs;
1775 bytes = min_t(size_t, len,
1776 (free->length - woffs));
1777 woffs = 0;
1778 } else {
1779 bytes = min_t(size_t, len, free->length);
1780 boffs = free->offset;
1781 }
8b0036ee 1782 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 1783 oob += bytes;
1784 }
1785 return oob;
1786 }
1787 default:
1788 BUG();
1789 }
1790 return NULL;
1791}
1792
29072b96 1793#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1da177e4
LT		 1794
1795/**
8593fbc6 1796 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 1797 * @mtd: MTD device structure
1798 * @to: offset to write to
8593fbc6 1799 * @ops: oob operations description structure
1da177e4
LT		 1800 *
1801 * NAND write with ECC
1802 */
8593fbc6
TG		 1803static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1804 struct mtd_oob_ops *ops)
1da177e4 1805{
29072b96 1806 int chipnr, realpage, page, blockmask, column;
ace4dfee 1807 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1808 uint32_t writelen = ops->len;
1809 uint8_t *oob = ops->oobbuf;
1810 uint8_t *buf = ops->datbuf;
29072b96 1811 int ret, subpage;
1da177e4 1812
8593fbc6 1813 ops->retlen = 0;
29072b96
TG		 1814 if (!writelen)
1815 return 0;
1da177e4 1816
61b03bd7 1817 /* reject writes, which are not page aligned */
8593fbc6 1818 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
f75e5097
TG		 1819 printk(KERN_NOTICE "nand_write: "
1820 "Attempt to write not page aligned data\n");
1da177e4
LT		 1821 return -EINVAL;
1822 }
1823
29072b96
TG		 1824 column = to & (mtd->writesize - 1);
1825 subpage = column || (writelen & (mtd->writesize - 1));
1826
1827 if (subpage && oob)
1828 return -EINVAL;
1da177e4 1829
6a930961
TG		 1830 chipnr = (int)(to >> chip->chip_shift);
1831 chip->select_chip(mtd, chipnr);
1832
1da177e4
LT		 1833 /* Check, if it is write protected */
1834 if (nand_check_wp(mtd))
8593fbc6 1835 return -EIO;
1da177e4 1836
f75e5097
TG		 1837 realpage = (int)(to >> chip->page_shift);
1838 page = realpage & chip->pagemask;
1839 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1840
1841 /* Invalidate the page cache, when we write to the cached page */
1842 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 1843 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 1844 chip->pagebuf = -1;
61b03bd7 1845
7dcdcbef
DW		 1846 /* If we're not given explicit OOB data, let it be 0xFF */
1847 if (likely(!oob))
1848 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 1849
f75e5097 1850 while(1) {
29072b96 1851 int bytes = mtd->writesize;
f75e5097 1852 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 1853 uint8_t *wbuf = buf;
1854
1855 /* Partial page write ? */
1856 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1857 cached = 0;
1858 bytes = min_t(int, bytes - column, (int) writelen);
1859 chip->pagebuf = -1;
1860 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1861 memcpy(&chip->buffers->databuf[column], buf, bytes);
1862 wbuf = chip->buffers->databuf;
1863 }
1da177e4 1864
8593fbc6
TG		 1865 if (unlikely(oob))
1866 oob = nand_fill_oob(chip, oob, ops);
1867
29072b96 1868 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 1869 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 1870 if (ret)
1871 break;
1872
1873 writelen -= bytes;
1874 if (!writelen)
1875 break;
1876
29072b96 1877 column = 0;
f75e5097
TG		 1878 buf += bytes;
1879 realpage++;
1880
1881 page = realpage & chip->pagemask;
1882 /* Check, if we cross a chip boundary */
1883 if (!page) {
1884 chipnr++;
1885 chip->select_chip(mtd, -1);
1886 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1887 }
1888 }
8593fbc6 1889
8593fbc6 1890 ops->retlen = ops->len - writelen;
7014568b
VW		 1891 if (unlikely(oob))
1892 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1893 return ret;
1894}
1895
f75e5097 1896/**
8593fbc6 1897 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 1898 * @mtd: MTD device structure
f75e5097
TG		 1899 * @to: offset to write to
1900 * @len: number of bytes to write
8593fbc6
TG		 1901 * @retlen: pointer to variable to store the number of written bytes
1902 * @buf: the data to write
f75e5097 1903 *
8593fbc6 1904 * NAND write with ECC
f75e5097 1905 */
8593fbc6
TG		 1906static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1907 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 1908{
1909 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 1910 int ret;
1911
8593fbc6
TG		 1912 /* Do not allow reads past end of device */
1913 if ((to + len) > mtd->size)
f75e5097 1914 return -EINVAL;
8593fbc6
TG		 1915 if (!len)
1916 return 0;
f75e5097 1917
7bc3312b 1918 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 1919
8593fbc6
TG		 1920 chip->ops.len = len;
1921 chip->ops.datbuf = (uint8_t *)buf;
1922 chip->ops.oobbuf = NULL;
f75e5097 1923
8593fbc6 1924 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 1925
7fd5aecc
RP		 1926 *retlen = chip->ops.retlen;
1927
f75e5097 1928 nand_release_device(mtd);
8593fbc6 1929
8593fbc6 1930 return ret;
f75e5097 1931}
7314e9e7 1932
1da177e4 1933/**
8593fbc6 1934 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 1935 * @mtd: MTD device structure
1936 * @to: offset to write to
8593fbc6 1937 * @ops: oob operation description structure
1da177e4
LT		 1938 *
1939 * NAND write out-of-band
1940 */
8593fbc6
TG		 1941static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1942 struct mtd_oob_ops *ops)
1da177e4 1943{
03736155 1944 int chipnr, page, status, len;
ace4dfee 1945 struct nand_chip *chip = mtd->priv;
1da177e4 1946
7314e9e7 1947 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
7014568b 1948 (unsigned int)to, (int)ops->ooblen);
1da177e4 1949
03736155
AH		 1950 if (ops->mode == MTD_OOB_AUTO)
1951 len = chip->ecc.layout->oobavail;
1952 else
1953 len = mtd->oobsize;
1954
1da177e4 1955 /* Do not allow write past end of page */
03736155 1956 if ((ops->ooboffs + ops->ooblen) > len) {
7314e9e7
TG		 1957 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1958 "Attempt to write past end of page\n");
1da177e4
LT		 1959 return -EINVAL;
1960 }
1961
03736155 1962 if (unlikely(ops->ooboffs >= len)) {
374555ae 1963 DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: "
03736155
AH		 1964 "Attempt to start write outside oob\n");
1965 return -EINVAL;
1966 }
1967
1968 /* Do not allow reads past end of device */
1969 if (unlikely(to >= mtd->size ||
1970 ops->ooboffs + ops->ooblen >
1971 ((mtd->size >> chip->page_shift) -
1972 (to >> chip->page_shift)) * len)) {
374555ae 1973 DEBUG(MTD_DEBUG_LEVEL0, "nand_do_write_oob: "
03736155
AH		 1974 "Attempt write beyond end of device\n");
1975 return -EINVAL;
1976 }
1977
7314e9e7 1978 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 1979 chip->select_chip(mtd, chipnr);
1da177e4 1980
7314e9e7
TG		 1981 /* Shift to get page */
1982 page = (int)(to >> chip->page_shift);
1983
1984 /*
1985 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1986 * of my DiskOnChip 2000 test units) will clear the whole data page too
1987 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1988 * it in the doc2000 driver in August 1999. dwmw2.
1989 */
ace4dfee 1990 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 1991
1992 /* Check, if it is write protected */
1993 if (nand_check_wp(mtd))
8593fbc6 1994 return -EROFS;
61b03bd7 1995
1da177e4 1996 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 1997 if (page == chip->pagebuf)
1998 chip->pagebuf = -1;
1da177e4 1999
7bc3312b
TG		 2000 memset(chip->oob_poi, 0xff, mtd->oobsize);
2001 nand_fill_oob(chip, ops->oobbuf, ops);
2002 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2003 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2004
7bc3312b
TG		 2005 if (status)
2006 return status;
1da177e4 2007
7014568b 2008 ops->oobretlen = ops->ooblen;
1da177e4 2009
7bc3312b 2010 return 0;
8593fbc6
TG		 2011}
2012
2013/**
2014 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2015 * @mtd: MTD device structure
844d3b42 2016 * @to: offset to write to
8593fbc6
TG		 2017 * @ops: oob operation description structure
2018 */
2019static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2020 struct mtd_oob_ops *ops)
2021{
8593fbc6
TG		 2022 struct nand_chip *chip = mtd->priv;
2023 int ret = -ENOTSUPP;
2024
2025 ops->retlen = 0;
2026
2027 /* Do not allow writes past end of device */
7014568b 2028 if (ops->datbuf && (to + ops->len) > mtd->size) {
374555ae
DB		 2029 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
2030 "Attempt write beyond end of device\n");
8593fbc6
TG		 2031 return -EINVAL;
2032 }
2033
7bc3312b 2034 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6
TG		 2035
2036 switch(ops->mode) {
2037 case MTD_OOB_PLACE:
2038 case MTD_OOB_AUTO:
8593fbc6 2039 case MTD_OOB_RAW:
8593fbc6
TG		 2040 break;
2041
2042 default:
2043 goto out;
2044 }
2045
2046 if (!ops->datbuf)
2047 ret = nand_do_write_oob(mtd, to, ops);
2048 else
2049 ret = nand_do_write_ops(mtd, to, ops);
2050
e0c7d767 2051 out:
1da177e4 2052 nand_release_device(mtd);
1da177e4
LT		 2053 return ret;
2054}
2055
1da177e4
LT		 2056/**
2057 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2058 * @mtd: MTD device structure
2059 * @page: the page address of the block which will be erased
2060 *
2061 * Standard erase command for NAND chips
2062 */
e0c7d767 2063static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2064{
ace4dfee 2065 struct nand_chip *chip = mtd->priv;
1da177e4 2066 /* Send commands to erase a block */
ace4dfee
TG		 2067 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2068 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2069}
2070
2071/**
2072 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2073 * @mtd: MTD device structure
2074 * @page: the page address of the block which will be erased
2075 *
2076 * AND multi block erase command function
2077 * Erase 4 consecutive blocks
2078 */
e0c7d767 2079static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2080{
ace4dfee 2081 struct nand_chip *chip = mtd->priv;
1da177e4 2082 /* Send commands to erase a block */
ace4dfee
TG		 2083 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2084 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2085 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2086 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2087 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2088}
2089
2090/**
2091 * nand_erase - [MTD Interface] erase block(s)
2092 * @mtd: MTD device structure
2093 * @instr: erase instruction
2094 *
2095 * Erase one ore more blocks
2096 */
e0c7d767 2097static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2098{
e0c7d767 2099 return nand_erase_nand(mtd, instr, 0);
1da177e4 2100}
61b03bd7 2101
30f464b7 2102#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2103/**
ace4dfee 2104 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2105 * @mtd: MTD device structure
2106 * @instr: erase instruction
2107 * @allowbbt: allow erasing the bbt area
2108 *
2109 * Erase one ore more blocks
2110 */
ace4dfee
TG		 2111int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2112 int allowbbt)
1da177e4 2113{
69423d99 2114 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2115 struct nand_chip *chip = mtd->priv;
69423d99 2116 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
ace4dfee 2117 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2118 loff_t len;
1da177e4 2119
69423d99
AH		 2120 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, len = %llu\n",
2121 (unsigned long long)instr->addr, (unsigned long long)instr->len);
1da177e4
LT		 2122
2123 /* Start address must align on block boundary */
ace4dfee 2124 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
e0c7d767 2125 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1da177e4
LT		 2126 return -EINVAL;
2127 }
2128
2129 /* Length must align on block boundary */
ace4dfee
TG		 2130 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2131 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2132 "Length not block aligned\n");
1da177e4
LT		 2133 return -EINVAL;
2134 }
2135
2136 /* Do not allow erase past end of device */
2137 if ((instr->len + instr->addr) > mtd->size) {
ace4dfee
TG		 2138 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2139 "Erase past end of device\n");
1da177e4
LT		 2140 return -EINVAL;
2141 }
2142
bb0eb217 2143 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2144
2145 /* Grab the lock and see if the device is available */
ace4dfee 2146 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2147
2148 /* Shift to get first page */
ace4dfee
TG		 2149 page = (int)(instr->addr >> chip->page_shift);
2150 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2151
2152 /* Calculate pages in each block */
ace4dfee 2153 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2154
2155 /* Select the NAND device */
ace4dfee 2156 chip->select_chip(mtd, chipnr);
1da177e4 2157
1da177e4
LT		 2158 /* Check, if it is write protected */
2159 if (nand_check_wp(mtd)) {
ace4dfee
TG		 2160 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2161 "Device is write protected!!!\n");
1da177e4
LT		 2162 instr->state = MTD_ERASE_FAILED;
2163 goto erase_exit;
2164 }
2165
ace4dfee
TG		 2166 /*
2167 * If BBT requires refresh, set the BBT page mask to see if the BBT
2168 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2169 * can not be matched. This is also done when the bbt is actually
2170 * erased to avoid recusrsive updates
2171 */
2172 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2173 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2174
1da177e4
LT		 2175 /* Loop through the pages */
2176 len = instr->len;
2177
2178 instr->state = MTD_ERASING;
2179
2180 while (len) {
ace4dfee
TG		 2181 /*
2182 * heck if we have a bad block, we do not erase bad blocks !
2183 */
2184 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2185 chip->page_shift, 0, allowbbt)) {
2186 printk(KERN_WARNING "nand_erase: attempt to erase a "
2187 "bad block at page 0x%08x\n", page);
1da177e4
LT		 2188 instr->state = MTD_ERASE_FAILED;
2189 goto erase_exit;
2190 }
61b03bd7 2191
ace4dfee
TG		 2192 /*
2193 * Invalidate the page cache, if we erase the block which
2194 * contains the current cached page
2195 */
2196 if (page <= chip->pagebuf && chip->pagebuf <
2197 (page + pages_per_block))
2198 chip->pagebuf = -1;
1da177e4 2199
ace4dfee 2200 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2201
7bc3312b 2202 status = chip->waitfunc(mtd, chip);
1da177e4 2203
ace4dfee
TG		 2204 /*
2205 * See if operation failed and additional status checks are
2206 * available
2207 */
2208 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2209 status = chip->errstat(mtd, chip, FL_ERASING,
2210 status, page);
068e3c0a 2211
1da177e4 2212 /* See if block erase succeeded */
a4ab4c5d 2213 if (status & NAND_STATUS_FAIL) {
ace4dfee
TG		 2214 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2215 "Failed erase, page 0x%08x\n", page);
1da177e4 2216 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2217 instr->fail_addr =
2218 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2219 goto erase_exit;
2220 }
30f464b7 2221
ace4dfee
TG		 2222 /*
2223 * If BBT requires refresh, set the BBT rewrite flag to the
2224 * page being erased
2225 */
2226 if (bbt_masked_page != 0xffffffff &&
2227 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2228 rewrite_bbt[chipnr] =
2229 ((loff_t)page << chip->page_shift);
61b03bd7 2230
1da177e4 2231 /* Increment page address and decrement length */
ace4dfee 2232 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2233 page += pages_per_block;
2234
2235 /* Check, if we cross a chip boundary */
ace4dfee 2236 if (len && !(page & chip->pagemask)) {
1da177e4 2237 chipnr++;
ace4dfee
TG		 2238 chip->select_chip(mtd, -1);
2239 chip->select_chip(mtd, chipnr);
30f464b7 2240
ace4dfee
TG		 2241 /*
2242 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2243 * page mask to see if this BBT should be rewritten
2244 */
2245 if (bbt_masked_page != 0xffffffff &&
2246 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2247 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2248 BBT_PAGE_MASK;
1da177e4
LT		 2249 }
2250 }
2251 instr->state = MTD_ERASE_DONE;
2252
e0c7d767 2253 erase_exit:
1da177e4
LT		 2254
2255 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2256
2257 /* Deselect and wake up anyone waiting on the device */
2258 nand_release_device(mtd);
2259
49defc01
DW		 2260 /* Do call back function */
2261 if (!ret)
2262 mtd_erase_callback(instr);
2263
ace4dfee
TG		 2264 /*
2265 * If BBT requires refresh and erase was successful, rewrite any
2266 * selected bad block tables
2267 */
2268 if (bbt_masked_page == 0xffffffff || ret)
2269 return ret;
2270
2271 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2272 if (!rewrite_bbt[chipnr])
2273 continue;
2274 /* update the BBT for chip */
2275 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
69423d99 2276 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
ace4dfee
TG		 2277 chip->bbt_td->pages[chipnr]);
2278 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2279 }
2280
1da177e4
LT		 2281 /* Return more or less happy */
2282 return ret;
2283}
2284
2285/**
2286 * nand_sync - [MTD Interface] sync
2287 * @mtd: MTD device structure
2288 *
2289 * Sync is actually a wait for chip ready function
2290 */
e0c7d767 2291static void nand_sync(struct mtd_info *mtd)
1da177e4 2292{
ace4dfee 2293 struct nand_chip *chip = mtd->priv;
1da177e4 2294
e0c7d767 2295 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1da177e4
LT		 2296
2297 /* Grab the lock and see if the device is available */
ace4dfee 2298 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2299 /* Release it and go back */
e0c7d767 2300 nand_release_device(mtd);
1da177e4
LT		 2301}
2302
1da177e4 2303/**
ace4dfee 2304 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2305 * @mtd: MTD device structure
844d3b42 2306 * @offs: offset relative to mtd start
1da177e4 2307 */
ace4dfee 2308static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2309{
2310 /* Check for invalid offset */
ace4dfee 2311 if (offs > mtd->size)
1da177e4 2312 return -EINVAL;
61b03bd7 2313
ace4dfee 2314 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2315}
2316
2317/**
ace4dfee 2318 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2319 * @mtd: MTD device structure
2320 * @ofs: offset relative to mtd start
2321 */
e0c7d767 2322static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2323{
ace4dfee 2324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2325 int ret;
2326
e0c7d767
DW		 2327 if ((ret = nand_block_isbad(mtd, ofs))) {
2328 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2329 if (ret > 0)
2330 return 0;
e0c7d767
DW		 2331 return ret;
2332 }
1da177e4 2333
ace4dfee 2334 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2335}
2336
962034f4
VW		 2337/**
2338 * nand_suspend - [MTD Interface] Suspend the NAND flash
2339 * @mtd: MTD device structure
2340 */
2341static int nand_suspend(struct mtd_info *mtd)
2342{
ace4dfee 2343 struct nand_chip *chip = mtd->priv;
962034f4 2344
ace4dfee 2345 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2346}
2347
2348/**
2349 * nand_resume - [MTD Interface] Resume the NAND flash
2350 * @mtd: MTD device structure
2351 */
2352static void nand_resume(struct mtd_info *mtd)
2353{
ace4dfee 2354 struct nand_chip *chip = mtd->priv;
962034f4 2355
ace4dfee 2356 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2357 nand_release_device(mtd);
2358 else
2c0a2bed
TG		 2359 printk(KERN_ERR "nand_resume() called for a chip which is not "
2360 "in suspended state\n");
962034f4
VW		 2361}
2362
7aa65bfd
TG		 2363/*
2364 * Set default functions
2365 */
ace4dfee 2366static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2367{
1da177e4 2368 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2369 if (!chip->chip_delay)
2370 chip->chip_delay = 20;
1da177e4
LT		 2371
2372 /* check, if a user supplied command function given */
ace4dfee
TG		 2373 if (chip->cmdfunc == NULL)
2374 chip->cmdfunc = nand_command;
1da177e4
LT		 2375
2376 /* check, if a user supplied wait function given */
ace4dfee
TG		 2377 if (chip->waitfunc == NULL)
2378 chip->waitfunc = nand_wait;
2379
2380 if (!chip->select_chip)
2381 chip->select_chip = nand_select_chip;
2382 if (!chip->read_byte)
2383 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2384 if (!chip->read_word)
2385 chip->read_word = nand_read_word;
2386 if (!chip->block_bad)
2387 chip->block_bad = nand_block_bad;
2388 if (!chip->block_markbad)
2389 chip->block_markbad = nand_default_block_markbad;
2390 if (!chip->write_buf)
2391 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2392 if (!chip->read_buf)
2393 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2394 if (!chip->verify_buf)
2395 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2396 if (!chip->scan_bbt)
2397 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2398
2399 if (!chip->controller) {
2400 chip->controller = &chip->hwcontrol;
2401 spin_lock_init(&chip->controller->lock);
2402 init_waitqueue_head(&chip->controller->wq);
2403 }
2404
7aa65bfd
TG		 2405}
2406
2407/*
ace4dfee 2408 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2409 */
2410static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2411 struct nand_chip *chip,
7aa65bfd
TG		 2412 int busw, int *maf_id)
2413{
2414 struct nand_flash_dev *type = NULL;
2415 int i, dev_id, maf_idx;
ed8165c7 2416 int tmp_id, tmp_manf;
1da177e4
LT		 2417
2418 /* Select the device */
ace4dfee 2419 chip->select_chip(mtd, 0);
1da177e4 2420
ef89a880
KB		 2421 /*
2422 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2423 * after power-up
2424 */
2425 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2426
1da177e4 2427 /* Send the command for reading device ID */
ace4dfee 2428 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2429
2430 /* Read manufacturer and device IDs */
ace4dfee
TG		 2431 *maf_id = chip->read_byte(mtd);
2432 dev_id = chip->read_byte(mtd);
1da177e4 2433
ed8165c7
BD		 2434 /* Try again to make sure, as some systems the bus-hold or other
2435 * interface concerns can cause random data which looks like a
2436 * possibly credible NAND flash to appear. If the two results do
2437 * not match, ignore the device completely.
2438 */
2439
2440 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2441
2442 /* Read manufacturer and device IDs */
2443
2444 tmp_manf = chip->read_byte(mtd);
2445 tmp_id = chip->read_byte(mtd);
2446
2447 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2448 printk(KERN_INFO "%s: second ID read did not match "
2449 "%02x,%02x against %02x,%02x\n", __func__,
2450 *maf_id, dev_id, tmp_manf, tmp_id);
2451 return ERR_PTR(-ENODEV);
2452 }
2453
7aa65bfd 2454 /* Lookup the flash id */
1da177e4 2455 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
7aa65bfd
TG		 2456 if (dev_id == nand_flash_ids[i].id) {
2457 type = &nand_flash_ids[i];
2458 break;
2459 }
2460 }
61b03bd7 2461
7aa65bfd
TG		 2462 if (!type)
2463 return ERR_PTR(-ENODEV);
2464
ba0251fe
TG		 2465 if (!mtd->name)
2466 mtd->name = type->name;
2467
69423d99 2468 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd
TG		 2469
2470 /* Newer devices have all the information in additional id bytes */
ba0251fe 2471 if (!type->pagesize) {
7aa65bfd 2472 int extid;
29072b96
TG		 2473 /* The 3rd id byte holds MLC / multichip data */
2474 chip->cellinfo = chip->read_byte(mtd);
7aa65bfd 2475 /* The 4th id byte is the important one */
ace4dfee 2476 extid = chip->read_byte(mtd);
7aa65bfd 2477 /* Calc pagesize */
4cbb9b80 2478 mtd->writesize = 1024 << (extid & 0x3);
7aa65bfd
TG		 2479 extid >>= 2;
2480 /* Calc oobsize */
4cbb9b80 2481 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
7aa65bfd
TG		 2482 extid >>= 2;
2483 /* Calc blocksize. Blocksize is multiples of 64KiB */
2484 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2485 extid >>= 2;
2486 /* Get buswidth information */
2487 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
61b03bd7 2488
7aa65bfd
TG		 2489 } else {
2490 /*
ace4dfee 2491 * Old devices have chip data hardcoded in the device id table
7aa65bfd 2492 */
ba0251fe
TG		 2493 mtd->erasesize = type->erasesize;
2494 mtd->writesize = type->pagesize;
4cbb9b80 2495 mtd->oobsize = mtd->writesize / 32;
ba0251fe 2496 busw = type->options & NAND_BUSWIDTH_16;
7aa65bfd 2497 }
1da177e4 2498
7aa65bfd 2499 /* Try to identify manufacturer */
9a909867 2500 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 2501 if (nand_manuf_ids[maf_idx].id == *maf_id)
2502 break;
2503 }
0ea4a755 2504
7aa65bfd
TG		 2505 /*
2506 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 2507 * chip correct !
7aa65bfd 2508 */
ace4dfee 2509 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 2510 printk(KERN_INFO "NAND device: Manufacturer ID:"
2511 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2512 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2513 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 2514 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 2515 busw ? 16 : 8);
2516 return ERR_PTR(-EINVAL);
2517 }
61b03bd7 2518
7aa65bfd 2519 /* Calculate the address shift from the page size */
ace4dfee 2520 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 2521 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 2522 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 2523
ace4dfee 2524 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 2525 ffs(mtd->erasesize) - 1;
69423d99
AH		 2526 if (chip->chipsize & 0xffffffff)
2527 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2528 else
2529 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
1da177e4 2530
7aa65bfd 2531 /* Set the bad block position */
ace4dfee 2532 chip->badblockpos = mtd->writesize > 512 ?
7aa65bfd 2533 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
61b03bd7 2534
7aa65bfd 2535 /* Get chip options, preserve non chip based options */
ace4dfee 2536 chip->options &= ~NAND_CHIPOPTIONS_MSK;
ba0251fe 2537 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
7aa65bfd
TG		 2538
2539 /*
ace4dfee 2540 * Set chip as a default. Board drivers can override it, if necessary
7aa65bfd 2541 */
ace4dfee 2542 chip->options |= NAND_NO_AUTOINCR;
7aa65bfd 2543
ace4dfee 2544 /* Check if chip is a not a samsung device. Do not clear the
7aa65bfd
TG		 2545 * options for chips which are not having an extended id.
2546 */
ba0251fe 2547 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
ace4dfee 2548 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
7aa65bfd
TG		 2549
2550 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 2551 if (chip->options & NAND_4PAGE_ARRAY)
2552 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 2553 else
ace4dfee 2554 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 2555
2556 /* Do not replace user supplied command function ! */
ace4dfee
TG		 2557 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2558 chip->cmdfunc = nand_command_lp;
7aa65bfd
TG		 2559
2560 printk(KERN_INFO "NAND device: Manufacturer ID:"
2561 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2562 nand_manuf_ids[maf_idx].name, type->name);
2563
2564 return type;
2565}
2566
7aa65bfd 2567/**
3b85c321
DW		 2568 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2569 * @mtd: MTD device structure
2570 * @maxchips: Number of chips to scan for
7aa65bfd 2571 *
3b85c321
DW		 2572 * This is the first phase of the normal nand_scan() function. It
2573 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 2574 *
3b85c321 2575 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 2576 */
3b85c321 2577int nand_scan_ident(struct mtd_info *mtd, int maxchips)
7aa65bfd
TG		 2578{
2579 int i, busw, nand_maf_id;
ace4dfee 2580 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 2581 struct nand_flash_dev *type;
2582
7aa65bfd 2583 /* Get buswidth to select the correct functions */
ace4dfee 2584 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 2585 /* Set the default functions */
ace4dfee 2586 nand_set_defaults(chip, busw);
7aa65bfd
TG		 2587
2588 /* Read the flash type */
ace4dfee 2589 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
7aa65bfd
TG		 2590
2591 if (IS_ERR(type)) {
e0c7d767 2592 printk(KERN_WARNING "No NAND device found!!!\n");
ace4dfee 2593 chip->select_chip(mtd, -1);
7aa65bfd 2594 return PTR_ERR(type);
1da177e4
LT		 2595 }
2596
7aa65bfd 2597 /* Check for a chip array */
e0c7d767 2598 for (i = 1; i < maxchips; i++) {
ace4dfee 2599 chip->select_chip(mtd, i);
ef89a880
KB		 2600 /* See comment in nand_get_flash_type for reset */
2601 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 2602 /* Send the command for reading device ID */
ace4dfee 2603 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 2604 /* Read manufacturer and device IDs */
ace4dfee
TG		 2605 if (nand_maf_id != chip->read_byte(mtd) ||
2606 type->id != chip->read_byte(mtd))
1da177e4
LT		 2607 break;
2608 }
2609 if (i > 1)
2610 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 2611
1da177e4 2612 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 2613 chip->numchips = i;
2614 mtd->size = i * chip->chipsize;
7aa65bfd 2615
3b85c321
DW		 2616 return 0;
2617}
2618
2619
2620/**
2621 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2622 * @mtd: MTD device structure
3b85c321
DW		 2623 *
2624 * This is the second phase of the normal nand_scan() function. It
2625 * fills out all the uninitialized function pointers with the defaults
2626 * and scans for a bad block table if appropriate.
2627 */
2628int nand_scan_tail(struct mtd_info *mtd)
2629{
2630 int i;
2631 struct nand_chip *chip = mtd->priv;
2632
4bf63fcb
DW		 2633 if (!(chip->options & NAND_OWN_BUFFERS))
2634 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2635 if (!chip->buffers)
2636 return -ENOMEM;
2637
7dcdcbef 2638 /* Set the internal oob buffer location, just after the page data */
784f4d5e 2639 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 2640
7aa65bfd
TG		 2641 /*
2642 * If no default placement scheme is given, select an appropriate one
2643 */
5bd34c09 2644 if (!chip->ecc.layout) {
61b03bd7 2645 switch (mtd->oobsize) {
1da177e4 2646 case 8:
5bd34c09 2647 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 2648 break;
2649 case 16:
5bd34c09 2650 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 2651 break;
2652 case 64:
5bd34c09 2653 chip->ecc.layout = &nand_oob_64;
1da177e4 2654 break;
81ec5364
TG		 2655 case 128:
2656 chip->ecc.layout = &nand_oob_128;
2657 break;
1da177e4 2658 default:
7aa65bfd
TG		 2659 printk(KERN_WARNING "No oob scheme defined for "
2660 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 2661 BUG();
2662 }
2663 }
61b03bd7 2664
956e944c
DW		 2665 if (!chip->write_page)
2666 chip->write_page = nand_write_page;
2667
61b03bd7 2668 /*
7aa65bfd
TG		 2669 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2670 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 2671 */
956e944c 2672
ace4dfee 2673 switch (chip->ecc.mode) {
6dfc6d25 2674 case NAND_ECC_HW:
f5bbdacc
TG		 2675 /* Use standard hwecc read page function ? */
2676 if (!chip->ecc.read_page)
2677 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 2678 if (!chip->ecc.write_page)
2679 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 2680 if (!chip->ecc.read_page_raw)
2681 chip->ecc.read_page_raw = nand_read_page_raw;
2682 if (!chip->ecc.write_page_raw)
2683 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2684 if (!chip->ecc.read_oob)
2685 chip->ecc.read_oob = nand_read_oob_std;
2686 if (!chip->ecc.write_oob)
2687 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 2688
6dfc6d25 2689 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 2690 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2691 !chip->ecc.hwctl) &&
2692 (!chip->ecc.read_page ||
1c45f604 2693 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 2694 !chip->ecc.write_page ||
1c45f604 2695 chip->ecc.write_page == nand_write_page_hwecc)) {
6dfc6d25
TG		 2696 printk(KERN_WARNING "No ECC functions supplied, "
2697 "Hardware ECC not possible\n");
2698 BUG();
2699 }
f75e5097 2700 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 2701 if (!chip->ecc.read_page)
2702 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 2703 if (!chip->ecc.write_page)
2704 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 2705 if (!chip->ecc.read_page_raw)
2706 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2707 if (!chip->ecc.write_page_raw)
2708 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 2709 if (!chip->ecc.read_oob)
2710 chip->ecc.read_oob = nand_read_oob_syndrome;
2711 if (!chip->ecc.write_oob)
2712 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 2713
ace4dfee 2714 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 2715 break;
2716 printk(KERN_WARNING "%d byte HW ECC not possible on "
2717 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 2718 chip->ecc.size, mtd->writesize);
2719 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 2720
6dfc6d25 2721 case NAND_ECC_SOFT:
ace4dfee
TG		 2722 chip->ecc.calculate = nand_calculate_ecc;
2723 chip->ecc.correct = nand_correct_data;
f5bbdacc 2724 chip->ecc.read_page = nand_read_page_swecc;
3d459559 2725 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 2726 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 2727 chip->ecc.read_page_raw = nand_read_page_raw;
2728 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 2729 chip->ecc.read_oob = nand_read_oob_std;
2730 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 2731 chip->ecc.size = 256;
2732 chip->ecc.bytes = 3;
1da177e4 2733 break;
61b03bd7
TG		 2734
2735 case NAND_ECC_NONE:
7aa65bfd
TG		 2736 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2737 "This is not recommended !!\n");
8593fbc6
TG		 2738 chip->ecc.read_page = nand_read_page_raw;
2739 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 2740 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 2741 chip->ecc.read_page_raw = nand_read_page_raw;
2742 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 2743 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 2744 chip->ecc.size = mtd->writesize;
2745 chip->ecc.bytes = 0;
1da177e4 2746 break;
956e944c 2747
1da177e4 2748 default:
7aa65bfd 2749 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 2750 chip->ecc.mode);
61b03bd7 2751 BUG();
1da177e4 2752 }
61b03bd7 2753
5bd34c09
TG		 2754 /*
2755 * The number of bytes available for a client to place data into
2756 * the out of band area
2757 */
2758 chip->ecc.layout->oobavail = 0;
2759 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2760 chip->ecc.layout->oobavail +=
2761 chip->ecc.layout->oobfree[i].length;
1f92267c 2762 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 2763
7aa65bfd
TG		 2764 /*
2765 * Set the number of read / write steps for one page depending on ECC
2766 * mode
2767 */
ace4dfee
TG		 2768 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2769 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 2770 printk(KERN_WARNING "Invalid ecc parameters\n");
2771 BUG();
1da177e4 2772 }
f5bbdacc 2773 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 2774
29072b96
TG		 2775 /*
2776 * Allow subpage writes up to ecc.steps. Not possible for MLC
2777 * FLASH.
2778 */
2779 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2780 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2781 switch(chip->ecc.steps) {
2782 case 2:
2783 mtd->subpage_sft = 1;
2784 break;
2785 case 4:
2786 case 8:
81ec5364 2787 case 16:
29072b96
TG		 2788 mtd->subpage_sft = 2;
2789 break;
2790 }
2791 }
2792 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2793
04bbd0ea 2794 /* Initialize state */
ace4dfee 2795 chip->state = FL_READY;
1da177e4
LT		 2796
2797 /* De-select the device */
ace4dfee 2798 chip->select_chip(mtd, -1);
1da177e4
LT		 2799
2800 /* Invalidate the pagebuffer reference */
ace4dfee 2801 chip->pagebuf = -1;
1da177e4
LT		 2802
2803 /* Fill in remaining MTD driver data */
2804 mtd->type = MTD_NANDFLASH;
5fa43394 2805 mtd->flags = MTD_CAP_NANDFLASH;
1da177e4
LT		 2806 mtd->erase = nand_erase;
2807 mtd->point = NULL;
2808 mtd->unpoint = NULL;
2809 mtd->read = nand_read;
2810 mtd->write = nand_write;
1da177e4
LT		 2811 mtd->read_oob = nand_read_oob;
2812 mtd->write_oob = nand_write_oob;
1da177e4
LT		 2813 mtd->sync = nand_sync;
2814 mtd->lock = NULL;
2815 mtd->unlock = NULL;
962034f4
VW		 2816 mtd->suspend = nand_suspend;
2817 mtd->resume = nand_resume;
1da177e4
LT		 2818 mtd->block_isbad = nand_block_isbad;
2819 mtd->block_markbad = nand_block_markbad;
2820
5bd34c09
TG		 2821 /* propagate ecc.layout to mtd_info */
2822 mtd->ecclayout = chip->ecc.layout;
1da177e4 2823
0040bf38 2824 /* Check, if we should skip the bad block table scan */
ace4dfee 2825 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 2826 return 0;
1da177e4
LT		 2827
2828 /* Build bad block table */
ace4dfee 2829 return chip->scan_bbt(mtd);
1da177e4
LT		 2830}
2831
a6e6abd5 2832/* is_module_text_address() isn't exported, and it's mostly a pointless
3b85c321
DW		 2833 test if this is a module _anyway_ -- they'd have to try _really_ hard
2834 to call us from in-kernel code if the core NAND support is modular. */
2835#ifdef MODULE
2836#define caller_is_module() (1)
2837#else
2838#define caller_is_module() \
a6e6abd5 2839 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 2840#endif
2841
2842/**
2843 * nand_scan - [NAND Interface] Scan for the NAND device
2844 * @mtd: MTD device structure
2845 * @maxchips: Number of chips to scan for
2846 *
2847 * This fills out all the uninitialized function pointers
2848 * with the defaults.
2849 * The flash ID is read and the mtd/chip structures are
2850 * filled with the appropriate values.
2851 * The mtd->owner field must be set to the module of the caller
2852 *
2853 */
2854int nand_scan(struct mtd_info *mtd, int maxchips)
2855{
2856 int ret;
2857
2858 /* Many callers got this wrong, so check for it for a while... */
2859 if (!mtd->owner && caller_is_module()) {
2860 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2861 BUG();
2862 }
2863
2864 ret = nand_scan_ident(mtd, maxchips);
2865 if (!ret)
2866 ret = nand_scan_tail(mtd);
2867 return ret;
2868}
2869
1da177e4 2870/**
61b03bd7 2871 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 2872 * @mtd: MTD device structure
2873*/
e0c7d767 2874void nand_release(struct mtd_info *mtd)
1da177e4 2875{
ace4dfee 2876 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2877
2878#ifdef CONFIG_MTD_PARTITIONS
2879 /* Deregister partitions */
e0c7d767 2880 del_mtd_partitions(mtd);
1da177e4
LT		 2881#endif
2882 /* Deregister the device */
e0c7d767 2883 del_mtd_device(mtd);
1da177e4 2884
fa671646 2885 /* Free bad block table memory */
ace4dfee 2886 kfree(chip->bbt);
4bf63fcb
DW		 2887 if (!(chip->options & NAND_OWN_BUFFERS))
2888 kfree(chip->buffers);
1da177e4
LT		 2889}
2890
e0c7d767 2891EXPORT_SYMBOL_GPL(nand_scan);
3b85c321
DW		 2892EXPORT_SYMBOL_GPL(nand_scan_ident);
2893EXPORT_SYMBOL_GPL(nand_scan_tail);
e0c7d767 2894EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 2895
2896static int __init nand_base_init(void)
2897{
2898 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2899 return 0;
2900}
2901
2902static void __exit nand_base_exit(void)
2903{
2904 led_trigger_unregister_simple(nand_led_trigger);
2905}
2906
2907module_init(nand_base_init);
2908module_exit(nand_base_exit);
2909
e0c7d767
DW		 2910MODULE_LICENSE("GPL");
2911MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2912MODULE_DESCRIPTION("Generic NAND flash driver code");
Clone of davem's net-next-2.6 tree