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34f6e157 SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
17 | * MA 02110-1301, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/mtd/mtd.h> | |
25 | #include <linux/mtd/nand.h> | |
26 | #include <linux/mtd/partitions.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/err.h> | |
32 | #include <linux/io.h> | |
33 | ||
34 | #include <asm/mach/flash.h> | |
35 | #include <mach/mxc_nand.h> | |
9467114e | 36 | #include <mach/hardware.h> |
34f6e157 SH |
37 | |
38 | #define DRIVER_NAME "mxc_nand" | |
39 | ||
9467114e | 40 | #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) |
a47bfd2e | 41 | #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) |
71ec5155 SH |
42 | #define nfc_is_v3_2() cpu_is_mx51() |
43 | #define nfc_is_v3() nfc_is_v3_2() | |
9467114e | 44 | |
34f6e157 | 45 | /* Addresses for NFC registers */ |
1bc99180 SH |
46 | #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) |
47 | #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) | |
48 | #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) | |
49 | #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) | |
50 | #define NFC_V1_V2_CONFIG (host->regs + 0x0a) | |
51 | #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) | |
52 | #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) | |
53 | #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) | |
54 | #define NFC_V1_V2_WRPROT (host->regs + 0x12) | |
55 | #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) | |
56 | #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) | |
57 | #define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20) | |
58 | #define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22) | |
59 | #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) | |
60 | #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) | |
61 | #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) | |
62 | ||
6e85dfdc | 63 | #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) |
1bc99180 SH |
64 | #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) |
65 | #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) | |
66 | #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) | |
67 | #define NFC_V1_V2_CONFIG1_BIG (1 << 5) | |
68 | #define NFC_V1_V2_CONFIG1_RST (1 << 6) | |
69 | #define NFC_V1_V2_CONFIG1_CE (1 << 7) | |
b8db2f51 SH |
70 | #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) |
71 | #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) | |
72 | #define NFC_V2_CONFIG1_FP_INT (1 << 11) | |
1bc99180 SH |
73 | |
74 | #define NFC_V1_V2_CONFIG2_INT (1 << 15) | |
75 | ||
76 | /* | |
77 | * Operation modes for the NFC. Valid for v1, v2 and v3 | |
78 | * type controllers. | |
79 | */ | |
80 | #define NFC_CMD (1 << 0) | |
81 | #define NFC_ADDR (1 << 1) | |
82 | #define NFC_INPUT (1 << 2) | |
83 | #define NFC_OUTPUT (1 << 3) | |
84 | #define NFC_ID (1 << 4) | |
85 | #define NFC_STATUS (1 << 5) | |
34f6e157 | 86 | |
71ec5155 SH |
87 | #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) |
88 | #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) | |
89 | ||
90 | #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) | |
91 | #define NFC_V3_CONFIG1_SP_EN (1 << 0) | |
92 | #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) | |
93 | ||
94 | #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) | |
95 | ||
96 | #define NFC_V3_LAUNCH (host->regs_axi + 0x40) | |
97 | ||
98 | #define NFC_V3_WRPROT (host->regs_ip + 0x0) | |
99 | #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) | |
100 | #define NFC_V3_WRPROT_LOCK (1 << 1) | |
101 | #define NFC_V3_WRPROT_UNLOCK (1 << 2) | |
102 | #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) | |
103 | ||
104 | #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) | |
105 | ||
106 | #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) | |
107 | #define NFC_V3_CONFIG2_PS_512 (0 << 0) | |
108 | #define NFC_V3_CONFIG2_PS_2048 (1 << 0) | |
109 | #define NFC_V3_CONFIG2_PS_4096 (2 << 0) | |
110 | #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) | |
111 | #define NFC_V3_CONFIG2_ECC_EN (1 << 3) | |
112 | #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) | |
113 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) | |
114 | #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) | |
115 | #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) | |
116 | #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) | |
117 | #define NFC_V3_CONFIG2_INT_MSK (1 << 15) | |
118 | #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) | |
119 | #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) | |
120 | ||
121 | #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) | |
122 | #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) | |
123 | #define NFC_V3_CONFIG3_FW8 (1 << 3) | |
124 | #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) | |
125 | #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) | |
126 | #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) | |
127 | #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) | |
128 | ||
129 | #define NFC_V3_IPC (host->regs_ip + 0x2C) | |
130 | #define NFC_V3_IPC_CREQ (1 << 0) | |
131 | #define NFC_V3_IPC_INT (1 << 31) | |
132 | ||
133 | #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) | |
34f6e157 SH |
134 | |
135 | struct mxc_nand_host { | |
136 | struct mtd_info mtd; | |
137 | struct nand_chip nand; | |
138 | struct mtd_partition *parts; | |
139 | struct device *dev; | |
140 | ||
c6de7e1b SH |
141 | void *spare0; |
142 | void *main_area0; | |
c6de7e1b SH |
143 | |
144 | void __iomem *base; | |
34f6e157 | 145 | void __iomem *regs; |
71ec5155 SH |
146 | void __iomem *regs_axi; |
147 | void __iomem *regs_ip; | |
34f6e157 | 148 | int status_request; |
34f6e157 SH |
149 | struct clk *clk; |
150 | int clk_act; | |
151 | int irq; | |
94f77e50 | 152 | int eccsize; |
34f6e157 SH |
153 | |
154 | wait_queue_head_t irq_waitq; | |
34f6e157 | 155 | |
f8f9608d SH |
156 | uint8_t *data_buf; |
157 | unsigned int buf_start; | |
158 | int spare_len; | |
5f97304e SH |
159 | |
160 | void (*preset)(struct mtd_info *); | |
161 | void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); | |
162 | void (*send_addr)(struct mxc_nand_host *, uint16_t, int); | |
163 | void (*send_page)(struct mtd_info *, unsigned int); | |
164 | void (*send_read_id)(struct mxc_nand_host *); | |
165 | uint16_t (*get_dev_status)(struct mxc_nand_host *); | |
7aaf28ac | 166 | int (*check_int)(struct mxc_nand_host *); |
34f6e157 SH |
167 | }; |
168 | ||
34f6e157 | 169 | /* OOB placement block for use with hardware ecc generation */ |
9467114e | 170 | static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { |
34f6e157 SH |
171 | .eccbytes = 5, |
172 | .eccpos = {6, 7, 8, 9, 10}, | |
8c1fd89a | 173 | .oobfree = {{0, 5}, {12, 4}, } |
bd3fd62e VB |
174 | }; |
175 | ||
9467114e | 176 | static struct nand_ecclayout nandv1_hw_eccoob_largepage = { |
bd3fd62e VB |
177 | .eccbytes = 20, |
178 | .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, | |
179 | 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, | |
180 | .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } | |
34f6e157 SH |
181 | }; |
182 | ||
9467114e SH |
183 | /* OOB description for 512 byte pages with 16 byte OOB */ |
184 | static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { | |
185 | .eccbytes = 1 * 9, | |
186 | .eccpos = { | |
187 | 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
188 | }, | |
189 | .oobfree = { | |
190 | {.offset = 0, .length = 5} | |
191 | } | |
192 | }; | |
193 | ||
194 | /* OOB description for 2048 byte pages with 64 byte OOB */ | |
195 | static struct nand_ecclayout nandv2_hw_eccoob_largepage = { | |
196 | .eccbytes = 4 * 9, | |
197 | .eccpos = { | |
198 | 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
199 | 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
200 | 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
201 | 55, 56, 57, 58, 59, 60, 61, 62, 63 | |
202 | }, | |
203 | .oobfree = { | |
204 | {.offset = 2, .length = 4}, | |
205 | {.offset = 16, .length = 7}, | |
206 | {.offset = 32, .length = 7}, | |
207 | {.offset = 48, .length = 7} | |
208 | } | |
209 | }; | |
210 | ||
34f6e157 SH |
211 | #ifdef CONFIG_MTD_PARTITIONS |
212 | static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL }; | |
213 | #endif | |
214 | ||
215 | static irqreturn_t mxc_nfc_irq(int irq, void *dev_id) | |
216 | { | |
217 | struct mxc_nand_host *host = dev_id; | |
218 | ||
a47bfd2e | 219 | disable_irq_nosync(irq); |
34f6e157 SH |
220 | |
221 | wake_up(&host->irq_waitq); | |
222 | ||
223 | return IRQ_HANDLED; | |
224 | } | |
225 | ||
71ec5155 SH |
226 | static int check_int_v3(struct mxc_nand_host *host) |
227 | { | |
228 | uint32_t tmp; | |
229 | ||
230 | tmp = readl(NFC_V3_IPC); | |
231 | if (!(tmp & NFC_V3_IPC_INT)) | |
232 | return 0; | |
233 | ||
234 | tmp &= ~NFC_V3_IPC_INT; | |
235 | writel(tmp, NFC_V3_IPC); | |
236 | ||
237 | return 1; | |
238 | } | |
239 | ||
7aaf28ac SH |
240 | static int check_int_v1_v2(struct mxc_nand_host *host) |
241 | { | |
242 | uint32_t tmp; | |
243 | ||
1bc99180 SH |
244 | tmp = readw(NFC_V1_V2_CONFIG2); |
245 | if (!(tmp & NFC_V1_V2_CONFIG2_INT)) | |
7aaf28ac SH |
246 | return 0; |
247 | ||
1bc99180 | 248 | writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2); |
7aaf28ac SH |
249 | |
250 | return 1; | |
251 | } | |
252 | ||
34f6e157 SH |
253 | /* This function polls the NANDFC to wait for the basic operation to |
254 | * complete by checking the INT bit of config2 register. | |
255 | */ | |
c110eaf4 | 256 | static void wait_op_done(struct mxc_nand_host *host, int useirq) |
34f6e157 | 257 | { |
a47bfd2e | 258 | int max_retries = 8000; |
34f6e157 SH |
259 | |
260 | if (useirq) { | |
7aaf28ac | 261 | if (!host->check_int(host)) { |
34f6e157 | 262 | |
a47bfd2e | 263 | enable_irq(host->irq); |
34f6e157 | 264 | |
7aaf28ac | 265 | wait_event(host->irq_waitq, host->check_int(host)); |
34f6e157 SH |
266 | } |
267 | } else { | |
268 | while (max_retries-- > 0) { | |
7aaf28ac | 269 | if (host->check_int(host)) |
34f6e157 | 270 | break; |
7aaf28ac | 271 | |
34f6e157 SH |
272 | udelay(1); |
273 | } | |
43950a60 | 274 | if (max_retries < 0) |
62465491 SH |
275 | DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n", |
276 | __func__); | |
34f6e157 SH |
277 | } |
278 | } | |
279 | ||
71ec5155 SH |
280 | static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
281 | { | |
282 | /* fill command */ | |
283 | writel(cmd, NFC_V3_FLASH_CMD); | |
284 | ||
285 | /* send out command */ | |
286 | writel(NFC_CMD, NFC_V3_LAUNCH); | |
287 | ||
288 | /* Wait for operation to complete */ | |
289 | wait_op_done(host, useirq); | |
290 | } | |
291 | ||
34f6e157 SH |
292 | /* This function issues the specified command to the NAND device and |
293 | * waits for completion. */ | |
5f97304e | 294 | static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq) |
34f6e157 SH |
295 | { |
296 | DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq); | |
297 | ||
1bc99180 SH |
298 | writew(cmd, NFC_V1_V2_FLASH_CMD); |
299 | writew(NFC_CMD, NFC_V1_V2_CONFIG2); | |
34f6e157 | 300 | |
a47bfd2e IC |
301 | if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) { |
302 | int max_retries = 100; | |
303 | /* Reset completion is indicated by NFC_CONFIG2 */ | |
304 | /* being set to 0 */ | |
305 | while (max_retries-- > 0) { | |
1bc99180 | 306 | if (readw(NFC_V1_V2_CONFIG2) == 0) { |
a47bfd2e IC |
307 | break; |
308 | } | |
309 | udelay(1); | |
310 | } | |
311 | if (max_retries < 0) | |
312 | DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n", | |
313 | __func__); | |
314 | } else { | |
315 | /* Wait for operation to complete */ | |
316 | wait_op_done(host, useirq); | |
317 | } | |
34f6e157 SH |
318 | } |
319 | ||
71ec5155 SH |
320 | static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast) |
321 | { | |
322 | /* fill address */ | |
323 | writel(addr, NFC_V3_FLASH_ADDR0); | |
324 | ||
325 | /* send out address */ | |
326 | writel(NFC_ADDR, NFC_V3_LAUNCH); | |
327 | ||
328 | wait_op_done(host, 0); | |
329 | } | |
330 | ||
34f6e157 SH |
331 | /* This function sends an address (or partial address) to the |
332 | * NAND device. The address is used to select the source/destination for | |
333 | * a NAND command. */ | |
5f97304e | 334 | static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast) |
34f6e157 SH |
335 | { |
336 | DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast); | |
337 | ||
1bc99180 SH |
338 | writew(addr, NFC_V1_V2_FLASH_ADDR); |
339 | writew(NFC_ADDR, NFC_V1_V2_CONFIG2); | |
34f6e157 SH |
340 | |
341 | /* Wait for operation to complete */ | |
c110eaf4 | 342 | wait_op_done(host, islast); |
34f6e157 SH |
343 | } |
344 | ||
71ec5155 SH |
345 | static void send_page_v3(struct mtd_info *mtd, unsigned int ops) |
346 | { | |
347 | struct nand_chip *nand_chip = mtd->priv; | |
348 | struct mxc_nand_host *host = nand_chip->priv; | |
349 | uint32_t tmp; | |
350 | ||
351 | tmp = readl(NFC_V3_CONFIG1); | |
352 | tmp &= ~(7 << 4); | |
353 | writel(tmp, NFC_V3_CONFIG1); | |
354 | ||
355 | /* transfer data from NFC ram to nand */ | |
356 | writel(ops, NFC_V3_LAUNCH); | |
357 | ||
358 | wait_op_done(host, false); | |
359 | } | |
360 | ||
5f97304e | 361 | static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops) |
34f6e157 | 362 | { |
2d69c7fa SH |
363 | struct nand_chip *nand_chip = mtd->priv; |
364 | struct mxc_nand_host *host = nand_chip->priv; | |
c5d23f1b | 365 | int bufs, i; |
34f6e157 | 366 | |
9467114e | 367 | if (nfc_is_v1() && mtd->writesize > 512) |
c5d23f1b SH |
368 | bufs = 4; |
369 | else | |
370 | bufs = 1; | |
34f6e157 | 371 | |
c5d23f1b | 372 | for (i = 0; i < bufs; i++) { |
34f6e157 | 373 | |
c5d23f1b | 374 | /* NANDFC buffer 0 is used for page read/write */ |
1bc99180 | 375 | writew(i, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 376 | |
1bc99180 | 377 | writew(ops, NFC_V1_V2_CONFIG2); |
34f6e157 | 378 | |
c5d23f1b | 379 | /* Wait for operation to complete */ |
c110eaf4 | 380 | wait_op_done(host, true); |
34f6e157 | 381 | } |
34f6e157 SH |
382 | } |
383 | ||
71ec5155 SH |
384 | static void send_read_id_v3(struct mxc_nand_host *host) |
385 | { | |
386 | /* Read ID into main buffer */ | |
387 | writel(NFC_ID, NFC_V3_LAUNCH); | |
388 | ||
389 | wait_op_done(host, true); | |
390 | ||
391 | memcpy(host->data_buf, host->main_area0, 16); | |
392 | } | |
393 | ||
34f6e157 | 394 | /* Request the NANDFC to perform a read of the NAND device ID. */ |
5f97304e | 395 | static void send_read_id_v1_v2(struct mxc_nand_host *host) |
34f6e157 SH |
396 | { |
397 | struct nand_chip *this = &host->nand; | |
34f6e157 SH |
398 | |
399 | /* NANDFC buffer 0 is used for device ID output */ | |
1bc99180 | 400 | writew(0x0, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 401 | |
1bc99180 | 402 | writew(NFC_ID, NFC_V1_V2_CONFIG2); |
34f6e157 SH |
403 | |
404 | /* Wait for operation to complete */ | |
c110eaf4 | 405 | wait_op_done(host, true); |
34f6e157 | 406 | |
f7b66e5e JO |
407 | memcpy(host->data_buf, host->main_area0, 16); |
408 | ||
34f6e157 | 409 | if (this->options & NAND_BUSWIDTH_16) { |
34f6e157 | 410 | /* compress the ID info */ |
f7b66e5e JO |
411 | host->data_buf[1] = host->data_buf[2]; |
412 | host->data_buf[2] = host->data_buf[4]; | |
413 | host->data_buf[3] = host->data_buf[6]; | |
414 | host->data_buf[4] = host->data_buf[8]; | |
415 | host->data_buf[5] = host->data_buf[10]; | |
34f6e157 SH |
416 | } |
417 | } | |
418 | ||
71ec5155 SH |
419 | static uint16_t get_dev_status_v3(struct mxc_nand_host *host) |
420 | { | |
421 | writew(NFC_STATUS, NFC_V3_LAUNCH); | |
422 | wait_op_done(host, true); | |
423 | ||
424 | return readl(NFC_V3_CONFIG1) >> 16; | |
425 | } | |
426 | ||
34f6e157 SH |
427 | /* This function requests the NANDFC to perform a read of the |
428 | * NAND device status and returns the current status. */ | |
5f97304e | 429 | static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host) |
34f6e157 | 430 | { |
c29c607a | 431 | void __iomem *main_buf = host->main_area0; |
34f6e157 | 432 | uint32_t store; |
f06368f7 | 433 | uint16_t ret; |
34f6e157 | 434 | |
c29c607a | 435 | writew(0x0, NFC_V1_V2_BUF_ADDR); |
34f6e157 | 436 | |
c29c607a SH |
437 | /* |
438 | * The device status is stored in main_area0. To | |
439 | * prevent corruption of the buffer save the value | |
440 | * and restore it afterwards. | |
441 | */ | |
34f6e157 | 442 | store = readl(main_buf); |
34f6e157 | 443 | |
1bc99180 | 444 | writew(NFC_STATUS, NFC_V1_V2_CONFIG2); |
c110eaf4 | 445 | wait_op_done(host, true); |
34f6e157 | 446 | |
34f6e157 | 447 | ret = readw(main_buf); |
c29c607a | 448 | |
34f6e157 SH |
449 | writel(store, main_buf); |
450 | ||
451 | return ret; | |
452 | } | |
453 | ||
454 | /* This functions is used by upper layer to checks if device is ready */ | |
455 | static int mxc_nand_dev_ready(struct mtd_info *mtd) | |
456 | { | |
457 | /* | |
458 | * NFC handles R/B internally. Therefore, this function | |
459 | * always returns status as ready. | |
460 | */ | |
461 | return 1; | |
462 | } | |
463 | ||
464 | static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
465 | { | |
466 | /* | |
467 | * If HW ECC is enabled, we turn it on during init. There is | |
468 | * no need to enable again here. | |
469 | */ | |
470 | } | |
471 | ||
94f77e50 | 472 | static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat, |
34f6e157 SH |
473 | u_char *read_ecc, u_char *calc_ecc) |
474 | { | |
475 | struct nand_chip *nand_chip = mtd->priv; | |
476 | struct mxc_nand_host *host = nand_chip->priv; | |
477 | ||
478 | /* | |
479 | * 1-Bit errors are automatically corrected in HW. No need for | |
480 | * additional correction. 2-Bit errors cannot be corrected by | |
481 | * HW ECC, so we need to return failure | |
482 | */ | |
1bc99180 | 483 | uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT); |
34f6e157 SH |
484 | |
485 | if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { | |
486 | DEBUG(MTD_DEBUG_LEVEL0, | |
487 | "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n"); | |
488 | return -1; | |
489 | } | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
94f77e50 SH |
494 | static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, |
495 | u_char *read_ecc, u_char *calc_ecc) | |
496 | { | |
497 | struct nand_chip *nand_chip = mtd->priv; | |
498 | struct mxc_nand_host *host = nand_chip->priv; | |
499 | u32 ecc_stat, err; | |
500 | int no_subpages = 1; | |
501 | int ret = 0; | |
502 | u8 ecc_bit_mask, err_limit; | |
503 | ||
504 | ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; | |
505 | err_limit = (host->eccsize == 4) ? 0x4 : 0x8; | |
506 | ||
507 | no_subpages = mtd->writesize >> 9; | |
508 | ||
71ec5155 SH |
509 | if (nfc_is_v21()) |
510 | ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT); | |
511 | else | |
512 | ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT); | |
94f77e50 SH |
513 | |
514 | do { | |
515 | err = ecc_stat & ecc_bit_mask; | |
516 | if (err > err_limit) { | |
517 | printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); | |
518 | return -1; | |
519 | } else { | |
520 | ret += err; | |
521 | } | |
522 | ecc_stat >>= 4; | |
523 | } while (--no_subpages); | |
524 | ||
525 | mtd->ecc_stats.corrected += ret; | |
526 | pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); | |
527 | ||
528 | return ret; | |
529 | } | |
530 | ||
34f6e157 SH |
531 | static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
532 | u_char *ecc_code) | |
533 | { | |
534 | return 0; | |
535 | } | |
536 | ||
537 | static u_char mxc_nand_read_byte(struct mtd_info *mtd) | |
538 | { | |
539 | struct nand_chip *nand_chip = mtd->priv; | |
540 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 541 | uint8_t ret; |
34f6e157 SH |
542 | |
543 | /* Check for status request */ | |
544 | if (host->status_request) | |
5f97304e | 545 | return host->get_dev_status(host) & 0xFF; |
34f6e157 | 546 | |
f8f9608d SH |
547 | ret = *(uint8_t *)(host->data_buf + host->buf_start); |
548 | host->buf_start++; | |
34f6e157 SH |
549 | |
550 | return ret; | |
551 | } | |
552 | ||
553 | static uint16_t mxc_nand_read_word(struct mtd_info *mtd) | |
554 | { | |
555 | struct nand_chip *nand_chip = mtd->priv; | |
556 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d | 557 | uint16_t ret; |
34f6e157 | 558 | |
f8f9608d SH |
559 | ret = *(uint16_t *)(host->data_buf + host->buf_start); |
560 | host->buf_start += 2; | |
34f6e157 SH |
561 | |
562 | return ret; | |
563 | } | |
564 | ||
565 | /* Write data of length len to buffer buf. The data to be | |
566 | * written on NAND Flash is first copied to RAMbuffer. After the Data Input | |
567 | * Operation by the NFC, the data is written to NAND Flash */ | |
568 | static void mxc_nand_write_buf(struct mtd_info *mtd, | |
569 | const u_char *buf, int len) | |
570 | { | |
571 | struct nand_chip *nand_chip = mtd->priv; | |
572 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
573 | u16 col = host->buf_start; |
574 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 575 | |
f8f9608d | 576 | n = min(n, len); |
34f6e157 | 577 | |
f8f9608d | 578 | memcpy(host->data_buf + col, buf, n); |
34f6e157 | 579 | |
f8f9608d | 580 | host->buf_start += n; |
34f6e157 SH |
581 | } |
582 | ||
583 | /* Read the data buffer from the NAND Flash. To read the data from NAND | |
584 | * Flash first the data output cycle is initiated by the NFC, which copies | |
585 | * the data to RAMbuffer. This data of length len is then copied to buffer buf. | |
586 | */ | |
587 | static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
588 | { | |
589 | struct nand_chip *nand_chip = mtd->priv; | |
590 | struct mxc_nand_host *host = nand_chip->priv; | |
f8f9608d SH |
591 | u16 col = host->buf_start; |
592 | int n = mtd->oobsize + mtd->writesize - col; | |
34f6e157 | 593 | |
f8f9608d | 594 | n = min(n, len); |
34f6e157 | 595 | |
f8f9608d | 596 | memcpy(buf, host->data_buf + col, len); |
34f6e157 | 597 | |
f8f9608d | 598 | host->buf_start += len; |
34f6e157 SH |
599 | } |
600 | ||
601 | /* Used by the upper layer to verify the data in NAND Flash | |
602 | * with the data in the buf. */ | |
603 | static int mxc_nand_verify_buf(struct mtd_info *mtd, | |
604 | const u_char *buf, int len) | |
605 | { | |
606 | return -EFAULT; | |
607 | } | |
608 | ||
609 | /* This function is used by upper layer for select and | |
610 | * deselect of the NAND chip */ | |
611 | static void mxc_nand_select_chip(struct mtd_info *mtd, int chip) | |
612 | { | |
613 | struct nand_chip *nand_chip = mtd->priv; | |
614 | struct mxc_nand_host *host = nand_chip->priv; | |
615 | ||
34f6e157 SH |
616 | switch (chip) { |
617 | case -1: | |
618 | /* Disable the NFC clock */ | |
619 | if (host->clk_act) { | |
620 | clk_disable(host->clk); | |
621 | host->clk_act = 0; | |
622 | } | |
623 | break; | |
624 | case 0: | |
625 | /* Enable the NFC clock */ | |
626 | if (!host->clk_act) { | |
627 | clk_enable(host->clk); | |
628 | host->clk_act = 1; | |
629 | } | |
630 | break; | |
631 | ||
632 | default: | |
633 | break; | |
634 | } | |
635 | } | |
636 | ||
f8f9608d SH |
637 | /* |
638 | * Function to transfer data to/from spare area. | |
639 | */ | |
640 | static void copy_spare(struct mtd_info *mtd, bool bfrom) | |
34f6e157 | 641 | { |
f8f9608d SH |
642 | struct nand_chip *this = mtd->priv; |
643 | struct mxc_nand_host *host = this->priv; | |
644 | u16 i, j; | |
645 | u16 n = mtd->writesize >> 9; | |
646 | u8 *d = host->data_buf + mtd->writesize; | |
c6de7e1b | 647 | u8 *s = host->spare0; |
f8f9608d SH |
648 | u16 t = host->spare_len; |
649 | ||
650 | j = (mtd->oobsize / n >> 1) << 1; | |
651 | ||
652 | if (bfrom) { | |
653 | for (i = 0; i < n - 1; i++) | |
654 | memcpy(d + i * j, s + i * t, j); | |
655 | ||
656 | /* the last section */ | |
657 | memcpy(d + i * j, s + i * t, mtd->oobsize - i * j); | |
658 | } else { | |
659 | for (i = 0; i < n - 1; i++) | |
660 | memcpy(&s[i * t], &d[i * j], j); | |
34f6e157 | 661 | |
f8f9608d SH |
662 | /* the last section */ |
663 | memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j); | |
34f6e157 | 664 | } |
f8f9608d | 665 | } |
34f6e157 | 666 | |
a3e65b64 SH |
667 | static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) |
668 | { | |
669 | struct nand_chip *nand_chip = mtd->priv; | |
670 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
671 | |
672 | /* Write out column address, if necessary */ | |
673 | if (column != -1) { | |
674 | /* | |
675 | * MXC NANDFC can only perform full page+spare or | |
676 | * spare-only read/write. When the upper layers | |
677 | * layers perform a read/write buf operation, | |
3ad2f3fb | 678 | * we will used the saved column address to index into |
34f6e157 SH |
679 | * the full page. |
680 | */ | |
5f97304e | 681 | host->send_addr(host, 0, page_addr == -1); |
2d69c7fa | 682 | if (mtd->writesize > 512) |
34f6e157 | 683 | /* another col addr cycle for 2k page */ |
5f97304e | 684 | host->send_addr(host, 0, false); |
34f6e157 SH |
685 | } |
686 | ||
687 | /* Write out page address, if necessary */ | |
688 | if (page_addr != -1) { | |
689 | /* paddr_0 - p_addr_7 */ | |
5f97304e | 690 | host->send_addr(host, (page_addr & 0xff), false); |
34f6e157 | 691 | |
2d69c7fa | 692 | if (mtd->writesize > 512) { |
bd3fd62e VB |
693 | if (mtd->size >= 0x10000000) { |
694 | /* paddr_8 - paddr_15 */ | |
5f97304e SH |
695 | host->send_addr(host, (page_addr >> 8) & 0xff, false); |
696 | host->send_addr(host, (page_addr >> 16) & 0xff, true); | |
bd3fd62e VB |
697 | } else |
698 | /* paddr_8 - paddr_15 */ | |
5f97304e | 699 | host->send_addr(host, (page_addr >> 8) & 0xff, true); |
34f6e157 SH |
700 | } else { |
701 | /* One more address cycle for higher density devices */ | |
702 | if (mtd->size >= 0x4000000) { | |
703 | /* paddr_8 - paddr_15 */ | |
5f97304e SH |
704 | host->send_addr(host, (page_addr >> 8) & 0xff, false); |
705 | host->send_addr(host, (page_addr >> 16) & 0xff, true); | |
34f6e157 SH |
706 | } else |
707 | /* paddr_8 - paddr_15 */ | |
5f97304e | 708 | host->send_addr(host, (page_addr >> 8) & 0xff, true); |
34f6e157 SH |
709 | } |
710 | } | |
a3e65b64 SH |
711 | } |
712 | ||
6e85dfdc SH |
713 | /* |
714 | * v2 and v3 type controllers can do 4bit or 8bit ecc depending | |
715 | * on how much oob the nand chip has. For 8bit ecc we need at least | |
716 | * 26 bytes of oob data per 512 byte block. | |
717 | */ | |
718 | static int get_eccsize(struct mtd_info *mtd) | |
719 | { | |
720 | int oobbytes_per_512 = 0; | |
721 | ||
722 | oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; | |
723 | ||
724 | if (oobbytes_per_512 < 26) | |
725 | return 4; | |
726 | else | |
727 | return 8; | |
728 | } | |
729 | ||
5f97304e | 730 | static void preset_v1_v2(struct mtd_info *mtd) |
d4840180 IC |
731 | { |
732 | struct nand_chip *nand_chip = mtd->priv; | |
733 | struct mxc_nand_host *host = nand_chip->priv; | |
b8db2f51 SH |
734 | uint16_t config1 = 0; |
735 | ||
736 | if (nand_chip->ecc.mode == NAND_ECC_HW) | |
737 | config1 |= NFC_V1_V2_CONFIG1_ECC_EN; | |
738 | ||
739 | if (nfc_is_v21()) | |
740 | config1 |= NFC_V2_CONFIG1_FP_INT; | |
741 | ||
742 | if (!cpu_is_mx21()) | |
743 | config1 |= NFC_V1_V2_CONFIG1_INT_MSK; | |
6e85dfdc SH |
744 | |
745 | if (nfc_is_v21() && mtd->writesize) { | |
b8db2f51 SH |
746 | uint16_t pages_per_block = mtd->erasesize / mtd->writesize; |
747 | ||
6e85dfdc SH |
748 | host->eccsize = get_eccsize(mtd); |
749 | if (host->eccsize == 4) | |
b8db2f51 SH |
750 | config1 |= NFC_V2_CONFIG1_ECC_MODE_4; |
751 | ||
752 | config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); | |
d4840180 | 753 | } else { |
6e85dfdc | 754 | host->eccsize = 1; |
d4840180 | 755 | } |
6e85dfdc | 756 | |
b8db2f51 | 757 | writew(config1, NFC_V1_V2_CONFIG1); |
d4840180 IC |
758 | /* preset operation */ |
759 | ||
760 | /* Unlock the internal RAM Buffer */ | |
1bc99180 | 761 | writew(0x2, NFC_V1_V2_CONFIG); |
d4840180 IC |
762 | |
763 | /* Blocks to be unlocked */ | |
764 | if (nfc_is_v21()) { | |
1bc99180 SH |
765 | writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR); |
766 | writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR); | |
d4840180 | 767 | } else if (nfc_is_v1()) { |
1bc99180 SH |
768 | writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR); |
769 | writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR); | |
d4840180 IC |
770 | } else |
771 | BUG(); | |
772 | ||
773 | /* Unlock Block Command for given address range */ | |
1bc99180 | 774 | writew(0x4, NFC_V1_V2_WRPROT); |
d4840180 IC |
775 | } |
776 | ||
71ec5155 SH |
777 | static void preset_v3(struct mtd_info *mtd) |
778 | { | |
779 | struct nand_chip *chip = mtd->priv; | |
780 | struct mxc_nand_host *host = chip->priv; | |
781 | uint32_t config2, config3; | |
782 | int i, addr_phases; | |
783 | ||
784 | writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); | |
785 | writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); | |
786 | ||
787 | /* Unlock the internal RAM Buffer */ | |
788 | writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, | |
789 | NFC_V3_WRPROT); | |
790 | ||
791 | /* Blocks to be unlocked */ | |
792 | for (i = 0; i < NAND_MAX_CHIPS; i++) | |
793 | writel(0x0 | (0xffff << 16), | |
794 | NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); | |
795 | ||
796 | writel(0, NFC_V3_IPC); | |
797 | ||
798 | config2 = NFC_V3_CONFIG2_ONE_CYCLE | | |
799 | NFC_V3_CONFIG2_2CMD_PHASES | | |
800 | NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | | |
801 | NFC_V3_CONFIG2_ST_CMD(0x70) | | |
802 | NFC_V3_CONFIG2_NUM_ADDR_PHASE0; | |
803 | ||
804 | if (chip->ecc.mode == NAND_ECC_HW) | |
805 | config2 |= NFC_V3_CONFIG2_ECC_EN; | |
806 | ||
807 | addr_phases = fls(chip->pagemask) >> 3; | |
808 | ||
809 | if (mtd->writesize == 2048) { | |
810 | config2 |= NFC_V3_CONFIG2_PS_2048; | |
811 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
812 | } else if (mtd->writesize == 4096) { | |
813 | config2 |= NFC_V3_CONFIG2_PS_4096; | |
814 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); | |
815 | } else { | |
816 | config2 |= NFC_V3_CONFIG2_PS_512; | |
817 | config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); | |
818 | } | |
819 | ||
820 | if (mtd->writesize) { | |
821 | config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); | |
822 | host->eccsize = get_eccsize(mtd); | |
823 | if (host->eccsize == 8) | |
824 | config2 |= NFC_V3_CONFIG2_ECC_MODE_8; | |
825 | } | |
826 | ||
827 | writel(config2, NFC_V3_CONFIG2); | |
828 | ||
829 | config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | | |
830 | NFC_V3_CONFIG3_NO_SDMA | | |
831 | NFC_V3_CONFIG3_RBB_MODE | | |
832 | NFC_V3_CONFIG3_SBB(6) | /* Reset default */ | |
833 | NFC_V3_CONFIG3_ADD_OP(0); | |
834 | ||
835 | if (!(chip->options & NAND_BUSWIDTH_16)) | |
836 | config3 |= NFC_V3_CONFIG3_FW8; | |
837 | ||
838 | writel(config3, NFC_V3_CONFIG3); | |
839 | ||
840 | writel(0, NFC_V3_DELAY_LINE); | |
d4840180 IC |
841 | } |
842 | ||
34f6e157 SH |
843 | /* Used by the upper layer to write command to NAND Flash for |
844 | * different operations to be carried out on NAND Flash */ | |
845 | static void mxc_nand_command(struct mtd_info *mtd, unsigned command, | |
846 | int column, int page_addr) | |
847 | { | |
848 | struct nand_chip *nand_chip = mtd->priv; | |
849 | struct mxc_nand_host *host = nand_chip->priv; | |
34f6e157 SH |
850 | |
851 | DEBUG(MTD_DEBUG_LEVEL3, | |
852 | "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n", | |
853 | command, column, page_addr); | |
854 | ||
855 | /* Reset command state information */ | |
856 | host->status_request = false; | |
34f6e157 | 857 | |
34f6e157 | 858 | /* Command pre-processing step */ |
34f6e157 | 859 | switch (command) { |
d4840180 | 860 | case NAND_CMD_RESET: |
5f97304e SH |
861 | host->preset(mtd); |
862 | host->send_cmd(host, command, false); | |
d4840180 | 863 | break; |
34f6e157 | 864 | |
34f6e157 | 865 | case NAND_CMD_STATUS: |
f8f9608d | 866 | host->buf_start = 0; |
34f6e157 | 867 | host->status_request = true; |
34f6e157 | 868 | |
5f97304e | 869 | host->send_cmd(host, command, true); |
89121a6b | 870 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
871 | break; |
872 | ||
34f6e157 | 873 | case NAND_CMD_READ0: |
34f6e157 | 874 | case NAND_CMD_READOOB: |
89121a6b SH |
875 | if (command == NAND_CMD_READ0) |
876 | host->buf_start = column; | |
877 | else | |
878 | host->buf_start = column + mtd->writesize; | |
f8f9608d | 879 | |
5ea32021 | 880 | command = NAND_CMD_READ0; /* only READ0 is valid */ |
89121a6b | 881 | |
5f97304e | 882 | host->send_cmd(host, command, false); |
89121a6b SH |
883 | mxc_do_addr_cycle(mtd, column, page_addr); |
884 | ||
2d69c7fa | 885 | if (mtd->writesize > 512) |
5f97304e | 886 | host->send_cmd(host, NAND_CMD_READSTART, true); |
c5d23f1b | 887 | |
5f97304e | 888 | host->send_page(mtd, NFC_OUTPUT); |
89121a6b | 889 | |
c6de7e1b | 890 | memcpy(host->data_buf, host->main_area0, mtd->writesize); |
89121a6b | 891 | copy_spare(mtd, true); |
34f6e157 SH |
892 | break; |
893 | ||
34f6e157 | 894 | case NAND_CMD_SEQIN: |
5ea32021 SH |
895 | if (column >= mtd->writesize) |
896 | /* call ourself to read a page */ | |
897 | mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr); | |
34f6e157 | 898 | |
5ea32021 | 899 | host->buf_start = column; |
89121a6b | 900 | |
5f97304e | 901 | host->send_cmd(host, command, false); |
89121a6b | 902 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
903 | break; |
904 | ||
905 | case NAND_CMD_PAGEPROG: | |
c6de7e1b | 906 | memcpy(host->main_area0, host->data_buf, mtd->writesize); |
f8f9608d | 907 | copy_spare(mtd, false); |
5f97304e SH |
908 | host->send_page(mtd, NFC_INPUT); |
909 | host->send_cmd(host, command, true); | |
89121a6b | 910 | mxc_do_addr_cycle(mtd, column, page_addr); |
34f6e157 SH |
911 | break; |
912 | ||
34f6e157 | 913 | case NAND_CMD_READID: |
5f97304e | 914 | host->send_cmd(host, command, true); |
89121a6b | 915 | mxc_do_addr_cycle(mtd, column, page_addr); |
5f97304e | 916 | host->send_read_id(host); |
9467114e | 917 | host->buf_start = column; |
34f6e157 SH |
918 | break; |
919 | ||
89121a6b | 920 | case NAND_CMD_ERASE1: |
34f6e157 | 921 | case NAND_CMD_ERASE2: |
5f97304e | 922 | host->send_cmd(host, command, false); |
89121a6b SH |
923 | mxc_do_addr_cycle(mtd, column, page_addr); |
924 | ||
34f6e157 SH |
925 | break; |
926 | } | |
927 | } | |
928 | ||
f1372055 SH |
929 | /* |
930 | * The generic flash bbt decriptors overlap with our ecc | |
931 | * hardware, so define some i.MX specific ones. | |
932 | */ | |
933 | static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; | |
934 | static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; | |
935 | ||
936 | static struct nand_bbt_descr bbt_main_descr = { | |
937 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
938 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
939 | .offs = 0, | |
940 | .len = 4, | |
941 | .veroffs = 4, | |
942 | .maxblocks = 4, | |
943 | .pattern = bbt_pattern, | |
944 | }; | |
945 | ||
946 | static struct nand_bbt_descr bbt_mirror_descr = { | |
947 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
948 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
949 | .offs = 0, | |
950 | .len = 4, | |
951 | .veroffs = 4, | |
952 | .maxblocks = 4, | |
953 | .pattern = mirror_pattern, | |
954 | }; | |
955 | ||
34f6e157 SH |
956 | static int __init mxcnd_probe(struct platform_device *pdev) |
957 | { | |
958 | struct nand_chip *this; | |
959 | struct mtd_info *mtd; | |
960 | struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; | |
961 | struct mxc_nand_host *host; | |
962 | struct resource *res; | |
34f6e157 | 963 | int err = 0, nr_parts = 0; |
9467114e | 964 | struct nand_ecclayout *oob_smallpage, *oob_largepage; |
34f6e157 SH |
965 | |
966 | /* Allocate memory for MTD device structure and private data */ | |
f8f9608d SH |
967 | host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE + |
968 | NAND_MAX_OOBSIZE, GFP_KERNEL); | |
34f6e157 SH |
969 | if (!host) |
970 | return -ENOMEM; | |
971 | ||
f8f9608d | 972 | host->data_buf = (uint8_t *)(host + 1); |
f8f9608d | 973 | |
34f6e157 SH |
974 | host->dev = &pdev->dev; |
975 | /* structures must be linked */ | |
976 | this = &host->nand; | |
977 | mtd = &host->mtd; | |
978 | mtd->priv = this; | |
979 | mtd->owner = THIS_MODULE; | |
87f39f04 | 980 | mtd->dev.parent = &pdev->dev; |
1fbff0a6 | 981 | mtd->name = DRIVER_NAME; |
34f6e157 SH |
982 | |
983 | /* 50 us command delay time */ | |
984 | this->chip_delay = 5; | |
985 | ||
986 | this->priv = host; | |
987 | this->dev_ready = mxc_nand_dev_ready; | |
988 | this->cmdfunc = mxc_nand_command; | |
989 | this->select_chip = mxc_nand_select_chip; | |
990 | this->read_byte = mxc_nand_read_byte; | |
991 | this->read_word = mxc_nand_read_word; | |
992 | this->write_buf = mxc_nand_write_buf; | |
993 | this->read_buf = mxc_nand_read_buf; | |
994 | this->verify_buf = mxc_nand_verify_buf; | |
995 | ||
e65fb009 | 996 | host->clk = clk_get(&pdev->dev, "nfc"); |
8541c118 VB |
997 | if (IS_ERR(host->clk)) { |
998 | err = PTR_ERR(host->clk); | |
34f6e157 | 999 | goto eclk; |
8541c118 | 1000 | } |
34f6e157 SH |
1001 | |
1002 | clk_enable(host->clk); | |
1003 | host->clk_act = 1; | |
1004 | ||
1005 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1006 | if (!res) { | |
1007 | err = -ENODEV; | |
1008 | goto eres; | |
1009 | } | |
1010 | ||
c6de7e1b SH |
1011 | host->base = ioremap(res->start, resource_size(res)); |
1012 | if (!host->base) { | |
8541c118 | 1013 | err = -ENOMEM; |
34f6e157 SH |
1014 | goto eres; |
1015 | } | |
1016 | ||
c6de7e1b | 1017 | host->main_area0 = host->base; |
9467114e | 1018 | |
5f97304e SH |
1019 | if (nfc_is_v1() || nfc_is_v21()) { |
1020 | host->preset = preset_v1_v2; | |
1021 | host->send_cmd = send_cmd_v1_v2; | |
1022 | host->send_addr = send_addr_v1_v2; | |
1023 | host->send_page = send_page_v1_v2; | |
1024 | host->send_read_id = send_read_id_v1_v2; | |
1025 | host->get_dev_status = get_dev_status_v1_v2; | |
7aaf28ac | 1026 | host->check_int = check_int_v1_v2; |
5f97304e | 1027 | } |
9467114e SH |
1028 | |
1029 | if (nfc_is_v21()) { | |
938cf997 | 1030 | host->regs = host->base + 0x1e00; |
9467114e SH |
1031 | host->spare0 = host->base + 0x1000; |
1032 | host->spare_len = 64; | |
1033 | oob_smallpage = &nandv2_hw_eccoob_smallpage; | |
1034 | oob_largepage = &nandv2_hw_eccoob_largepage; | |
d4840180 | 1035 | this->ecc.bytes = 9; |
9467114e | 1036 | } else if (nfc_is_v1()) { |
938cf997 | 1037 | host->regs = host->base + 0xe00; |
9467114e SH |
1038 | host->spare0 = host->base + 0x800; |
1039 | host->spare_len = 16; | |
1040 | oob_smallpage = &nandv1_hw_eccoob_smallpage; | |
1041 | oob_largepage = &nandv1_hw_eccoob_largepage; | |
9467114e | 1042 | this->ecc.bytes = 3; |
71ec5155 SH |
1043 | host->eccsize = 1; |
1044 | } else if (nfc_is_v3_2()) { | |
1045 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1046 | if (!res) { | |
1047 | err = -ENODEV; | |
1048 | goto eirq; | |
1049 | } | |
1050 | host->regs_ip = ioremap(res->start, resource_size(res)); | |
1051 | if (!host->regs_ip) { | |
1052 | err = -ENOMEM; | |
1053 | goto eirq; | |
1054 | } | |
1055 | host->regs_axi = host->base + 0x1e00; | |
1056 | host->spare0 = host->base + 0x1000; | |
1057 | host->spare_len = 64; | |
1058 | host->preset = preset_v3; | |
1059 | host->send_cmd = send_cmd_v3; | |
1060 | host->send_addr = send_addr_v3; | |
1061 | host->send_page = send_page_v3; | |
1062 | host->send_read_id = send_read_id_v3; | |
1063 | host->check_int = check_int_v3; | |
1064 | host->get_dev_status = get_dev_status_v3; | |
1065 | oob_smallpage = &nandv2_hw_eccoob_smallpage; | |
1066 | oob_largepage = &nandv2_hw_eccoob_largepage; | |
9467114e SH |
1067 | } else |
1068 | BUG(); | |
13e1add1 | 1069 | |
13e1add1 | 1070 | this->ecc.size = 512; |
9467114e | 1071 | this->ecc.layout = oob_smallpage; |
13e1add1 | 1072 | |
34f6e157 SH |
1073 | if (pdata->hw_ecc) { |
1074 | this->ecc.calculate = mxc_nand_calculate_ecc; | |
1075 | this->ecc.hwctl = mxc_nand_enable_hwecc; | |
94f77e50 SH |
1076 | if (nfc_is_v1()) |
1077 | this->ecc.correct = mxc_nand_correct_data_v1; | |
1078 | else | |
1079 | this->ecc.correct = mxc_nand_correct_data_v2_v3; | |
34f6e157 | 1080 | this->ecc.mode = NAND_ECC_HW; |
34f6e157 | 1081 | } else { |
34f6e157 | 1082 | this->ecc.mode = NAND_ECC_SOFT; |
34f6e157 SH |
1083 | } |
1084 | ||
34f6e157 | 1085 | /* NAND bus width determines access funtions used by upper layer */ |
13e1add1 | 1086 | if (pdata->width == 2) |
34f6e157 | 1087 | this->options |= NAND_BUSWIDTH_16; |
34f6e157 | 1088 | |
f1372055 SH |
1089 | if (pdata->flash_bbt) { |
1090 | this->bbt_td = &bbt_main_descr; | |
1091 | this->bbt_md = &bbt_mirror_descr; | |
1092 | /* update flash based bbt */ | |
1093 | this->options |= NAND_USE_FLASH_BBT; | |
34f6e157 SH |
1094 | } |
1095 | ||
d4840180 IC |
1096 | init_waitqueue_head(&host->irq_waitq); |
1097 | ||
1098 | host->irq = platform_get_irq(pdev, 0); | |
1099 | ||
a47bfd2e | 1100 | err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host); |
d4840180 IC |
1101 | if (err) |
1102 | goto eirq; | |
1103 | ||
bd3fd62e | 1104 | /* first scan to find the device and get the page size */ |
5e81e88a | 1105 | if (nand_scan_ident(mtd, 1, NULL)) { |
bd3fd62e VB |
1106 | err = -ENXIO; |
1107 | goto escan; | |
1108 | } | |
34f6e157 | 1109 | |
6e85dfdc SH |
1110 | /* Call preset again, with correct writesize this time */ |
1111 | host->preset(mtd); | |
1112 | ||
2d69c7fa | 1113 | if (mtd->writesize == 2048) |
9467114e | 1114 | this->ecc.layout = oob_largepage; |
bd3fd62e VB |
1115 | |
1116 | /* second phase scan */ | |
1117 | if (nand_scan_tail(mtd)) { | |
34f6e157 SH |
1118 | err = -ENXIO; |
1119 | goto escan; | |
1120 | } | |
1121 | ||
1122 | /* Register the partitions */ | |
1123 | #ifdef CONFIG_MTD_PARTITIONS | |
1124 | nr_parts = | |
1125 | parse_mtd_partitions(mtd, part_probes, &host->parts, 0); | |
1126 | if (nr_parts > 0) | |
1127 | add_mtd_partitions(mtd, host->parts, nr_parts); | |
cce02464 BS |
1128 | else if (pdata->parts) |
1129 | add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); | |
34f6e157 SH |
1130 | else |
1131 | #endif | |
1132 | { | |
1133 | pr_info("Registering %s as whole device\n", mtd->name); | |
1134 | add_mtd_device(mtd); | |
1135 | } | |
1136 | ||
1137 | platform_set_drvdata(pdev, host); | |
1138 | ||
1139 | return 0; | |
1140 | ||
1141 | escan: | |
b258fd8d | 1142 | free_irq(host->irq, host); |
34f6e157 | 1143 | eirq: |
71ec5155 SH |
1144 | if (host->regs_ip) |
1145 | iounmap(host->regs_ip); | |
c6de7e1b | 1146 | iounmap(host->base); |
34f6e157 SH |
1147 | eres: |
1148 | clk_put(host->clk); | |
1149 | eclk: | |
1150 | kfree(host); | |
1151 | ||
1152 | return err; | |
1153 | } | |
1154 | ||
51eeb878 | 1155 | static int __devexit mxcnd_remove(struct platform_device *pdev) |
34f6e157 SH |
1156 | { |
1157 | struct mxc_nand_host *host = platform_get_drvdata(pdev); | |
1158 | ||
1159 | clk_put(host->clk); | |
1160 | ||
1161 | platform_set_drvdata(pdev, NULL); | |
1162 | ||
1163 | nand_release(&host->mtd); | |
b258fd8d | 1164 | free_irq(host->irq, host); |
71ec5155 SH |
1165 | if (host->regs_ip) |
1166 | iounmap(host->regs_ip); | |
c6de7e1b | 1167 | iounmap(host->base); |
34f6e157 SH |
1168 | kfree(host); |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
34f6e157 SH |
1173 | static struct platform_driver mxcnd_driver = { |
1174 | .driver = { | |
1175 | .name = DRIVER_NAME, | |
04dd0d3a | 1176 | }, |
daa0f15a | 1177 | .remove = __devexit_p(mxcnd_remove), |
34f6e157 SH |
1178 | }; |
1179 | ||
1180 | static int __init mxc_nd_init(void) | |
1181 | { | |
8541c118 | 1182 | return platform_driver_probe(&mxcnd_driver, mxcnd_probe); |
34f6e157 SH |
1183 | } |
1184 | ||
1185 | static void __exit mxc_nd_cleanup(void) | |
1186 | { | |
1187 | /* Unregister the device structure */ | |
1188 | platform_driver_unregister(&mxcnd_driver); | |
1189 | } | |
1190 | ||
1191 | module_init(mxc_nd_init); | |
1192 | module_exit(mxc_nd_cleanup); | |
1193 | ||
1194 | MODULE_AUTHOR("Freescale Semiconductor, Inc."); | |
1195 | MODULE_DESCRIPTION("MXC NAND MTD driver"); | |
1196 | MODULE_LICENSE("GPL"); |