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76b10467 SW |
1 | /* Freescale Enhanced Local Bus Controller NAND driver |
2 | * | |
3ab8f2a2 | 3 | * Copyright © 2006-2007, 2010 Freescale Semiconductor |
76b10467 SW |
4 | * |
5 | * Authors: Nick Spence <nick.spence@freescale.com>, | |
6 | * Scott Wood <scottwood@freescale.com> | |
3ab8f2a2 RZ |
7 | * Jack Lan <jack.lan@freescale.com> |
8 | * Roy Zang <tie-fei.zang@freescale.com> | |
76b10467 SW |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/of_platform.h> | |
3ab8f2a2 | 32 | #include <linux/platform_device.h> |
76b10467 SW |
33 | #include <linux/slab.h> |
34 | #include <linux/interrupt.h> | |
35 | ||
36 | #include <linux/mtd/mtd.h> | |
37 | #include <linux/mtd/nand.h> | |
38 | #include <linux/mtd/nand_ecc.h> | |
39 | #include <linux/mtd/partitions.h> | |
40 | ||
41 | #include <asm/io.h> | |
d4a32fe4 | 42 | #include <asm/fsl_lbc.h> |
76b10467 SW |
43 | |
44 | #define MAX_BANKS 8 | |
45 | #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ | |
46 | #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ | |
47 | ||
76b10467 SW |
48 | /* mtd information per set */ |
49 | ||
50 | struct fsl_elbc_mtd { | |
51 | struct mtd_info mtd; | |
52 | struct nand_chip chip; | |
3ab8f2a2 | 53 | struct fsl_lbc_ctrl *ctrl; |
76b10467 SW |
54 | |
55 | struct device *dev; | |
56 | int bank; /* Chip select bank number */ | |
57 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
58 | int page_size; /* NAND page size (0=512, 1=2048) */ | |
59 | unsigned int fmr; /* FCM Flash Mode Register value */ | |
60 | }; | |
61 | ||
3ab8f2a2 | 62 | /* Freescale eLBC FCM controller infomation */ |
76b10467 | 63 | |
3ab8f2a2 | 64 | struct fsl_elbc_fcm_ctrl { |
76b10467 SW |
65 | struct nand_hw_control controller; |
66 | struct fsl_elbc_mtd *chips[MAX_BANKS]; | |
67 | ||
76b10467 SW |
68 | u8 __iomem *addr; /* Address of assigned FCM buffer */ |
69 | unsigned int page; /* Last page written to / read from */ | |
70 | unsigned int read_bytes; /* Number of bytes read during command */ | |
71 | unsigned int column; /* Saved column from SEQIN */ | |
72 | unsigned int index; /* Pointer to next byte to 'read' */ | |
73 | unsigned int status; /* status read from LTESR after last op */ | |
74 | unsigned int mdr; /* UPM/FCM Data Register value */ | |
75 | unsigned int use_mdr; /* Non zero if the MDR is to be set */ | |
76 | unsigned int oob; /* Non zero if operating on OOB data */ | |
3ab8f2a2 | 77 | unsigned int counter; /* counter for the initializations */ |
76b10467 SW |
78 | char *oob_poi; /* Place to write ECC after read back */ |
79 | }; | |
80 | ||
81 | /* These map to the positions used by the FCM hardware ECC generator */ | |
82 | ||
83 | /* Small Page FLASH with FMR[ECCM] = 0 */ | |
84 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { | |
85 | .eccbytes = 3, | |
86 | .eccpos = {6, 7, 8}, | |
87 | .oobfree = { {0, 5}, {9, 7} }, | |
76b10467 SW |
88 | }; |
89 | ||
90 | /* Small Page FLASH with FMR[ECCM] = 1 */ | |
91 | static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { | |
92 | .eccbytes = 3, | |
93 | .eccpos = {8, 9, 10}, | |
94 | .oobfree = { {0, 5}, {6, 2}, {11, 5} }, | |
76b10467 SW |
95 | }; |
96 | ||
97 | /* Large Page FLASH with FMR[ECCM] = 0 */ | |
98 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { | |
99 | .eccbytes = 12, | |
100 | .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, | |
101 | .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, | |
76b10467 SW |
102 | }; |
103 | ||
104 | /* Large Page FLASH with FMR[ECCM] = 1 */ | |
105 | static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |
106 | .eccbytes = 12, | |
107 | .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, | |
108 | .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, | |
76b10467 SW |
109 | }; |
110 | ||
452db272 AV |
111 | /* |
112 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | |
113 | * 1, so we have to adjust bad block pattern. This pattern should be used for | |
114 | * x8 chips only. So far hardware does not support x16 chips anyway. | |
115 | */ | |
116 | static u8 scan_ff_pattern[] = { 0xff, }; | |
117 | ||
118 | static struct nand_bbt_descr largepage_memorybased = { | |
119 | .options = 0, | |
120 | .offs = 0, | |
121 | .len = 1, | |
122 | .pattern = scan_ff_pattern, | |
123 | }; | |
124 | ||
ec6e0ea3 AV |
125 | /* |
126 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | |
127 | * interfere with ECC positions, that's why we implement our own descriptors. | |
128 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | |
129 | */ | |
130 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
131 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
132 | ||
133 | static struct nand_bbt_descr bbt_main_descr = { | |
134 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
135 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
136 | .offs = 11, | |
137 | .len = 4, | |
138 | .veroffs = 15, | |
139 | .maxblocks = 4, | |
140 | .pattern = bbt_pattern, | |
141 | }; | |
142 | ||
143 | static struct nand_bbt_descr bbt_mirror_descr = { | |
144 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
145 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
146 | .offs = 11, | |
147 | .len = 4, | |
148 | .veroffs = 15, | |
149 | .maxblocks = 4, | |
150 | .pattern = mirror_pattern, | |
151 | }; | |
152 | ||
76b10467 SW |
153 | /*=================================*/ |
154 | ||
155 | /* | |
156 | * Set up the FCM hardware block and page address fields, and the fcm | |
157 | * structure addr field to point to the correct FCM buffer in memory | |
158 | */ | |
159 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
160 | { | |
161 | struct nand_chip *chip = mtd->priv; | |
162 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 163 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 164 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 165 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
166 | int buf_num; |
167 | ||
3ab8f2a2 | 168 | elbc_fcm_ctrl->page = page_addr; |
76b10467 SW |
169 | |
170 | out_be32(&lbc->fbar, | |
171 | page_addr >> (chip->phys_erase_shift - chip->page_shift)); | |
172 | ||
173 | if (priv->page_size) { | |
174 | out_be32(&lbc->fpar, | |
175 | ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | | |
176 | (oob ? FPAR_LP_MS : 0) | column); | |
177 | buf_num = (page_addr & 1) << 2; | |
178 | } else { | |
179 | out_be32(&lbc->fpar, | |
180 | ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | | |
181 | (oob ? FPAR_SP_MS : 0) | column); | |
182 | buf_num = page_addr & 7; | |
183 | } | |
184 | ||
3ab8f2a2 RZ |
185 | elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; |
186 | elbc_fcm_ctrl->index = column; | |
76b10467 SW |
187 | |
188 | /* for OOB data point to the second half of the buffer */ | |
189 | if (oob) | |
3ab8f2a2 | 190 | elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; |
76b10467 | 191 | |
3ab8f2a2 RZ |
192 | dev_vdbg(priv->dev, "set_addr: bank=%d, " |
193 | "elbc_fcm_ctrl->addr=0x%p (0x%p), " | |
76b10467 | 194 | "index %x, pes %d ps %d\n", |
3ab8f2a2 RZ |
195 | buf_num, elbc_fcm_ctrl->addr, priv->vbase, |
196 | elbc_fcm_ctrl->index, | |
76b10467 SW |
197 | chip->phys_erase_shift, chip->page_shift); |
198 | } | |
199 | ||
200 | /* | |
201 | * execute FCM command and wait for it to complete | |
202 | */ | |
203 | static int fsl_elbc_run_command(struct mtd_info *mtd) | |
204 | { | |
205 | struct nand_chip *chip = mtd->priv; | |
206 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
207 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
208 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 209 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
210 | |
211 | /* Setup the FMR[OP] to execute without write protection */ | |
212 | out_be32(&lbc->fmr, priv->fmr | 3); | |
3ab8f2a2 RZ |
213 | if (elbc_fcm_ctrl->use_mdr) |
214 | out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); | |
76b10467 | 215 | |
3ab8f2a2 | 216 | dev_vdbg(priv->dev, |
76b10467 SW |
217 | "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", |
218 | in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); | |
3ab8f2a2 | 219 | dev_vdbg(priv->dev, |
76b10467 SW |
220 | "fsl_elbc_run_command: fbar=%08x fpar=%08x " |
221 | "fbcr=%08x bank=%d\n", | |
222 | in_be32(&lbc->fbar), in_be32(&lbc->fpar), | |
223 | in_be32(&lbc->fbcr), priv->bank); | |
224 | ||
1938de46 | 225 | ctrl->irq_status = 0; |
76b10467 SW |
226 | /* execute special operation */ |
227 | out_be32(&lbc->lsor, priv->bank); | |
228 | ||
229 | /* wait for FCM complete flag or timeout */ | |
76b10467 SW |
230 | wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
231 | FCM_TIMEOUT_MSECS * HZ/1000); | |
3ab8f2a2 | 232 | elbc_fcm_ctrl->status = ctrl->irq_status; |
76b10467 | 233 | /* store mdr value in case it was needed */ |
3ab8f2a2 RZ |
234 | if (elbc_fcm_ctrl->use_mdr) |
235 | elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); | |
76b10467 | 236 | |
3ab8f2a2 | 237 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 | 238 | |
3ab8f2a2 RZ |
239 | if (elbc_fcm_ctrl->status != LTESR_CC) { |
240 | dev_info(priv->dev, | |
c1317f71 SW |
241 | "command failed: fir %x fcr %x status %x mdr %x\n", |
242 | in_be32(&lbc->fir), in_be32(&lbc->fcr), | |
3ab8f2a2 | 243 | elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); |
c1317f71 SW |
244 | return -EIO; |
245 | } | |
76b10467 | 246 | |
c1317f71 | 247 | return 0; |
76b10467 SW |
248 | } |
249 | ||
250 | static void fsl_elbc_do_read(struct nand_chip *chip, int oob) | |
251 | { | |
252 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 253 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 254 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
255 | |
256 | if (priv->page_size) { | |
257 | out_be32(&lbc->fir, | |
476459a6 | 258 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
259 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
260 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
476459a6 | 261 | (FIR_OP_CM1 << FIR_OP3_SHIFT) | |
76b10467 SW |
262 | (FIR_OP_RBW << FIR_OP4_SHIFT)); |
263 | ||
264 | out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
265 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
266 | } else { | |
267 | out_be32(&lbc->fir, | |
476459a6 | 268 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
269 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
270 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
271 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
272 | ||
273 | if (oob) | |
274 | out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); | |
275 | else | |
276 | out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
277 | } | |
278 | } | |
279 | ||
280 | /* cmdfunc send commands to the FCM */ | |
281 | static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
282 | int column, int page_addr) | |
283 | { | |
284 | struct nand_chip *chip = mtd->priv; | |
285 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 RZ |
286 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
287 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; | |
d4a32fe4 | 288 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 | 289 | |
3ab8f2a2 | 290 | elbc_fcm_ctrl->use_mdr = 0; |
76b10467 SW |
291 | |
292 | /* clear the read buffer */ | |
3ab8f2a2 | 293 | elbc_fcm_ctrl->read_bytes = 0; |
76b10467 | 294 | if (command != NAND_CMD_PAGEPROG) |
3ab8f2a2 | 295 | elbc_fcm_ctrl->index = 0; |
76b10467 SW |
296 | |
297 | switch (command) { | |
298 | /* READ0 and READ1 read the entire buffer to use hardware ECC. */ | |
299 | case NAND_CMD_READ1: | |
300 | column += 256; | |
301 | ||
302 | /* fall-through */ | |
303 | case NAND_CMD_READ0: | |
3ab8f2a2 | 304 | dev_dbg(priv->dev, |
76b10467 SW |
305 | "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" |
306 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
307 | ||
308 | ||
309 | out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ | |
310 | set_addr(mtd, 0, page_addr, 0); | |
311 | ||
3ab8f2a2 RZ |
312 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
313 | elbc_fcm_ctrl->index += column; | |
76b10467 SW |
314 | |
315 | fsl_elbc_do_read(chip, 0); | |
316 | fsl_elbc_run_command(mtd); | |
317 | return; | |
318 | ||
319 | /* READOOB reads only the OOB because no ECC is performed. */ | |
320 | case NAND_CMD_READOOB: | |
3ab8f2a2 | 321 | dev_vdbg(priv->dev, |
76b10467 SW |
322 | "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" |
323 | " 0x%x, column: 0x%x.\n", page_addr, column); | |
324 | ||
325 | out_be32(&lbc->fbcr, mtd->oobsize - column); | |
326 | set_addr(mtd, column, page_addr, 1); | |
327 | ||
3ab8f2a2 | 328 | elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
76b10467 SW |
329 | |
330 | fsl_elbc_do_read(chip, 1); | |
331 | fsl_elbc_run_command(mtd); | |
332 | return; | |
333 | ||
334 | /* READID must read all 5 possible bytes while CEB is active */ | |
335 | case NAND_CMD_READID: | |
3ab8f2a2 | 336 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); |
76b10467 | 337 | |
476459a6 | 338 | out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
339 | (FIR_OP_UA << FIR_OP1_SHIFT) | |
340 | (FIR_OP_RBW << FIR_OP2_SHIFT)); | |
341 | out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); | |
342 | /* 5 bytes for manuf, device and exts */ | |
343 | out_be32(&lbc->fbcr, 5); | |
3ab8f2a2 RZ |
344 | elbc_fcm_ctrl->read_bytes = 5; |
345 | elbc_fcm_ctrl->use_mdr = 1; | |
346 | elbc_fcm_ctrl->mdr = 0; | |
76b10467 SW |
347 | |
348 | set_addr(mtd, 0, 0, 0); | |
349 | fsl_elbc_run_command(mtd); | |
350 | return; | |
351 | ||
352 | /* ERASE1 stores the block and page address */ | |
353 | case NAND_CMD_ERASE1: | |
3ab8f2a2 | 354 | dev_vdbg(priv->dev, |
76b10467 SW |
355 | "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " |
356 | "page_addr: 0x%x.\n", page_addr); | |
357 | set_addr(mtd, 0, page_addr, 0); | |
358 | return; | |
359 | ||
360 | /* ERASE2 uses the block and page address from ERASE1 */ | |
361 | case NAND_CMD_ERASE2: | |
3ab8f2a2 | 362 | dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); |
76b10467 SW |
363 | |
364 | out_be32(&lbc->fir, | |
476459a6 | 365 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 | 366 | (FIR_OP_PA << FIR_OP1_SHIFT) | |
476459a6 SW |
367 | (FIR_OP_CM2 << FIR_OP2_SHIFT) | |
368 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
369 | (FIR_OP_RS << FIR_OP4_SHIFT)); | |
76b10467 SW |
370 | |
371 | out_be32(&lbc->fcr, | |
372 | (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | | |
476459a6 SW |
373 | (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
374 | (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); | |
76b10467 SW |
375 | |
376 | out_be32(&lbc->fbcr, 0); | |
3ab8f2a2 RZ |
377 | elbc_fcm_ctrl->read_bytes = 0; |
378 | elbc_fcm_ctrl->use_mdr = 1; | |
76b10467 SW |
379 | |
380 | fsl_elbc_run_command(mtd); | |
381 | return; | |
382 | ||
383 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
384 | case NAND_CMD_SEQIN: { | |
385 | __be32 fcr; | |
3ab8f2a2 RZ |
386 | dev_vdbg(priv->dev, |
387 | "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " | |
76b10467 SW |
388 | "page_addr: 0x%x, column: 0x%x.\n", |
389 | page_addr, column); | |
390 | ||
3ab8f2a2 | 391 | elbc_fcm_ctrl->use_mdr = 1; |
76b10467 | 392 | |
476459a6 SW |
393 | fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
394 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | | |
395 | (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); | |
57650664 | 396 | |
476459a6 | 397 | if (priv->page_size) { |
76b10467 | 398 | out_be32(&lbc->fir, |
476459a6 | 399 | (FIR_OP_CM2 << FIR_OP0_SHIFT) | |
76b10467 SW |
400 | (FIR_OP_CA << FIR_OP1_SHIFT) | |
401 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
402 | (FIR_OP_WB << FIR_OP3_SHIFT) | | |
476459a6 SW |
403 | (FIR_OP_CM3 << FIR_OP4_SHIFT) | |
404 | (FIR_OP_CW1 << FIR_OP5_SHIFT) | | |
405 | (FIR_OP_RS << FIR_OP6_SHIFT)); | |
76b10467 SW |
406 | } else { |
407 | out_be32(&lbc->fir, | |
476459a6 | 408 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
76b10467 SW |
409 | (FIR_OP_CM2 << FIR_OP1_SHIFT) | |
410 | (FIR_OP_CA << FIR_OP2_SHIFT) | | |
411 | (FIR_OP_PA << FIR_OP3_SHIFT) | | |
412 | (FIR_OP_WB << FIR_OP4_SHIFT) | | |
476459a6 SW |
413 | (FIR_OP_CM3 << FIR_OP5_SHIFT) | |
414 | (FIR_OP_CW1 << FIR_OP6_SHIFT) | | |
415 | (FIR_OP_RS << FIR_OP7_SHIFT)); | |
76b10467 SW |
416 | |
417 | if (column >= mtd->writesize) { | |
418 | /* OOB area --> READOOB */ | |
419 | column -= mtd->writesize; | |
420 | fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; | |
3ab8f2a2 | 421 | elbc_fcm_ctrl->oob = 1; |
476459a6 SW |
422 | } else { |
423 | WARN_ON(column != 0); | |
76b10467 SW |
424 | /* First 256 bytes --> READ0 */ |
425 | fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; | |
76b10467 SW |
426 | } |
427 | } | |
428 | ||
429 | out_be32(&lbc->fcr, fcr); | |
3ab8f2a2 | 430 | set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); |
76b10467 SW |
431 | return; |
432 | } | |
433 | ||
434 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
435 | case NAND_CMD_PAGEPROG: { | |
436 | int full_page; | |
3ab8f2a2 | 437 | dev_vdbg(priv->dev, |
76b10467 | 438 | "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " |
3ab8f2a2 | 439 | "writing %d bytes.\n", elbc_fcm_ctrl->index); |
76b10467 SW |
440 | |
441 | /* if the write did not start at 0 or is not a full page | |
442 | * then set the exact length, otherwise use a full page | |
443 | * write so the HW generates the ECC. | |
444 | */ | |
3ab8f2a2 RZ |
445 | if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || |
446 | elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) { | |
447 | out_be32(&lbc->fbcr, elbc_fcm_ctrl->index); | |
76b10467 SW |
448 | full_page = 0; |
449 | } else { | |
450 | out_be32(&lbc->fbcr, 0); | |
451 | full_page = 1; | |
452 | } | |
453 | ||
454 | fsl_elbc_run_command(mtd); | |
455 | ||
456 | /* Read back the page in order to fill in the ECC for the | |
457 | * caller. Is this really needed? | |
458 | */ | |
3ab8f2a2 | 459 | if (full_page && elbc_fcm_ctrl->oob_poi) { |
76b10467 SW |
460 | out_be32(&lbc->fbcr, 3); |
461 | set_addr(mtd, 6, page_addr, 1); | |
462 | ||
3ab8f2a2 | 463 | elbc_fcm_ctrl->read_bytes = mtd->writesize + 9; |
76b10467 SW |
464 | |
465 | fsl_elbc_do_read(chip, 1); | |
466 | fsl_elbc_run_command(mtd); | |
467 | ||
3ab8f2a2 RZ |
468 | memcpy_fromio(elbc_fcm_ctrl->oob_poi + 6, |
469 | &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], 3); | |
470 | elbc_fcm_ctrl->index += 3; | |
76b10467 SW |
471 | } |
472 | ||
3ab8f2a2 | 473 | elbc_fcm_ctrl->oob_poi = NULL; |
76b10467 SW |
474 | return; |
475 | } | |
476 | ||
477 | /* CMD_STATUS must read the status byte while CEB is active */ | |
478 | /* Note - it does not wait for the ready line */ | |
479 | case NAND_CMD_STATUS: | |
480 | out_be32(&lbc->fir, | |
481 | (FIR_OP_CM0 << FIR_OP0_SHIFT) | | |
482 | (FIR_OP_RBW << FIR_OP1_SHIFT)); | |
483 | out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); | |
484 | out_be32(&lbc->fbcr, 1); | |
485 | set_addr(mtd, 0, 0, 0); | |
3ab8f2a2 | 486 | elbc_fcm_ctrl->read_bytes = 1; |
76b10467 SW |
487 | |
488 | fsl_elbc_run_command(mtd); | |
489 | ||
490 | /* The chip always seems to report that it is | |
491 | * write-protected, even when it is not. | |
492 | */ | |
3ab8f2a2 | 493 | setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); |
76b10467 SW |
494 | return; |
495 | ||
496 | /* RESET without waiting for the ready line */ | |
497 | case NAND_CMD_RESET: | |
3ab8f2a2 | 498 | dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); |
76b10467 SW |
499 | out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); |
500 | out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); | |
501 | fsl_elbc_run_command(mtd); | |
502 | return; | |
503 | ||
504 | default: | |
3ab8f2a2 | 505 | dev_err(priv->dev, |
76b10467 SW |
506 | "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", |
507 | command); | |
508 | } | |
509 | } | |
510 | ||
511 | static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) | |
512 | { | |
513 | /* The hardware does not seem to support multiple | |
514 | * chips per bank. | |
515 | */ | |
516 | } | |
517 | ||
518 | /* | |
519 | * Write buf to the FCM Controller Data Buffer | |
520 | */ | |
521 | static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
522 | { | |
523 | struct nand_chip *chip = mtd->priv; | |
524 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 525 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
526 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
527 | ||
0ff6631b | 528 | if (len <= 0) { |
3ab8f2a2 RZ |
529 | dev_err(priv->dev, "write_buf of %d bytes", len); |
530 | elbc_fcm_ctrl->status = 0; | |
76b10467 SW |
531 | return; |
532 | } | |
533 | ||
3ab8f2a2 RZ |
534 | if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { |
535 | dev_err(priv->dev, | |
76b10467 SW |
536 | "write_buf beyond end of buffer " |
537 | "(%d requested, %u available)\n", | |
3ab8f2a2 RZ |
538 | len, bufsize - elbc_fcm_ctrl->index); |
539 | len = bufsize - elbc_fcm_ctrl->index; | |
76b10467 SW |
540 | } |
541 | ||
3ab8f2a2 | 542 | memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); |
0ff6631b AV |
543 | /* |
544 | * This is workaround for the weird elbc hangs during nand write, | |
545 | * Scott Wood says: "...perhaps difference in how long it takes a | |
546 | * write to make it through the localbus compared to a write to IMMR | |
547 | * is causing problems, and sync isn't helping for some reason." | |
548 | * Reading back the last byte helps though. | |
549 | */ | |
3ab8f2a2 | 550 | in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); |
0ff6631b | 551 | |
3ab8f2a2 | 552 | elbc_fcm_ctrl->index += len; |
76b10467 SW |
553 | } |
554 | ||
555 | /* | |
556 | * read a byte from either the FCM hardware buffer if it has any data left | |
557 | * otherwise issue a command to read a single byte. | |
558 | */ | |
559 | static u8 fsl_elbc_read_byte(struct mtd_info *mtd) | |
560 | { | |
561 | struct nand_chip *chip = mtd->priv; | |
562 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 563 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
564 | |
565 | /* If there are still bytes in the FCM, then use the next byte. */ | |
3ab8f2a2 RZ |
566 | if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) |
567 | return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); | |
76b10467 | 568 | |
3ab8f2a2 | 569 | dev_err(priv->dev, "read_byte beyond end of buffer\n"); |
76b10467 SW |
570 | return ERR_BYTE; |
571 | } | |
572 | ||
573 | /* | |
574 | * Read from the FCM Controller Data Buffer | |
575 | */ | |
576 | static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
577 | { | |
578 | struct nand_chip *chip = mtd->priv; | |
579 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 580 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
581 | int avail; |
582 | ||
583 | if (len < 0) | |
584 | return; | |
585 | ||
3ab8f2a2 RZ |
586 | avail = min((unsigned int)len, |
587 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
588 | memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); | |
589 | elbc_fcm_ctrl->index += avail; | |
76b10467 SW |
590 | |
591 | if (len > avail) | |
3ab8f2a2 | 592 | dev_err(priv->dev, |
76b10467 SW |
593 | "read_buf beyond end of buffer " |
594 | "(%d requested, %d available)\n", | |
595 | len, avail); | |
596 | } | |
597 | ||
598 | /* | |
599 | * Verify buffer against the FCM Controller Data Buffer | |
600 | */ | |
601 | static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
602 | { | |
603 | struct nand_chip *chip = mtd->priv; | |
604 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 605 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
606 | int i; |
607 | ||
608 | if (len < 0) { | |
3ab8f2a2 | 609 | dev_err(priv->dev, "write_buf of %d bytes", len); |
76b10467 SW |
610 | return -EINVAL; |
611 | } | |
612 | ||
3ab8f2a2 RZ |
613 | if ((unsigned int)len > |
614 | elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) { | |
615 | dev_err(priv->dev, | |
616 | "verify_buf beyond end of buffer " | |
617 | "(%d requested, %u available)\n", | |
618 | len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); | |
76b10467 | 619 | |
3ab8f2a2 | 620 | elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes; |
76b10467 SW |
621 | return -EINVAL; |
622 | } | |
623 | ||
624 | for (i = 0; i < len; i++) | |
3ab8f2a2 RZ |
625 | if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i]) |
626 | != buf[i]) | |
76b10467 SW |
627 | break; |
628 | ||
3ab8f2a2 RZ |
629 | elbc_fcm_ctrl->index += len; |
630 | return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO; | |
76b10467 SW |
631 | } |
632 | ||
633 | /* This function is called after Program and Erase Operations to | |
634 | * check for success or failure. | |
635 | */ | |
636 | static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
637 | { | |
638 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 639 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 | 640 | |
3ab8f2a2 | 641 | if (elbc_fcm_ctrl->status != LTESR_CC) |
76b10467 SW |
642 | return NAND_STATUS_FAIL; |
643 | ||
644 | /* The chip always seems to report that it is | |
645 | * write-protected, even when it is not. | |
646 | */ | |
3ab8f2a2 | 647 | return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; |
76b10467 SW |
648 | } |
649 | ||
650 | static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |
651 | { | |
652 | struct nand_chip *chip = mtd->priv; | |
653 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 654 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 655 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
76b10467 SW |
656 | unsigned int al; |
657 | ||
658 | /* calculate FMR Address Length field */ | |
659 | al = 0; | |
660 | if (chip->pagemask & 0xffff0000) | |
661 | al++; | |
662 | if (chip->pagemask & 0xff000000) | |
663 | al++; | |
664 | ||
665 | /* add to ECCM mode set in fsl_elbc_init */ | |
666 | priv->fmr |= (12 << FMR_CWTO_SHIFT) | /* Timeout > 12 ms */ | |
667 | (al << FMR_AL_SHIFT); | |
668 | ||
3ab8f2a2 | 669 | dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", |
76b10467 | 670 | chip->numchips); |
3ab8f2a2 | 671 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", |
76b10467 | 672 | chip->chipsize); |
3ab8f2a2 | 673 | dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", |
76b10467 | 674 | chip->pagemask); |
3ab8f2a2 | 675 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", |
76b10467 | 676 | chip->chip_delay); |
3ab8f2a2 | 677 | dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", |
76b10467 | 678 | chip->badblockpos); |
3ab8f2a2 | 679 | dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", |
76b10467 | 680 | chip->chip_shift); |
3ab8f2a2 | 681 | dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", |
76b10467 | 682 | chip->page_shift); |
3ab8f2a2 | 683 | dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", |
76b10467 | 684 | chip->phys_erase_shift); |
3ab8f2a2 | 685 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n", |
76b10467 | 686 | chip->ecclayout); |
3ab8f2a2 | 687 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", |
76b10467 | 688 | chip->ecc.mode); |
3ab8f2a2 | 689 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", |
76b10467 | 690 | chip->ecc.steps); |
3ab8f2a2 | 691 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", |
76b10467 | 692 | chip->ecc.bytes); |
3ab8f2a2 | 693 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", |
76b10467 | 694 | chip->ecc.total); |
3ab8f2a2 | 695 | dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n", |
76b10467 | 696 | chip->ecc.layout); |
3ab8f2a2 RZ |
697 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); |
698 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); | |
699 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", | |
76b10467 | 700 | mtd->erasesize); |
3ab8f2a2 | 701 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", |
76b10467 | 702 | mtd->writesize); |
3ab8f2a2 | 703 | dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", |
76b10467 SW |
704 | mtd->oobsize); |
705 | ||
706 | /* adjust Option Register and ECC to match Flash page size */ | |
707 | if (mtd->writesize == 512) { | |
708 | priv->page_size = 0; | |
1938de46 | 709 | clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
76b10467 SW |
710 | } else if (mtd->writesize == 2048) { |
711 | priv->page_size = 1; | |
712 | setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); | |
713 | /* adjust ecc setup if needed */ | |
714 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
715 | BR_DECC_CHK_GEN) { | |
716 | chip->ecc.size = 512; | |
717 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
718 | &fsl_elbc_oob_lp_eccm1 : | |
719 | &fsl_elbc_oob_lp_eccm0; | |
452db272 | 720 | chip->badblock_pattern = &largepage_memorybased; |
76b10467 SW |
721 | } |
722 | } else { | |
3ab8f2a2 | 723 | dev_err(priv->dev, |
76b10467 SW |
724 | "fsl_elbc_init: page size %d is not supported\n", |
725 | mtd->writesize); | |
726 | return -1; | |
727 | } | |
728 | ||
76b10467 SW |
729 | return 0; |
730 | } | |
731 | ||
732 | static int fsl_elbc_read_page(struct mtd_info *mtd, | |
733 | struct nand_chip *chip, | |
46a8cf2d SN |
734 | uint8_t *buf, |
735 | int page) | |
76b10467 SW |
736 | { |
737 | fsl_elbc_read_buf(mtd, buf, mtd->writesize); | |
738 | fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
739 | ||
740 | if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) | |
741 | mtd->ecc_stats.failed++; | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
746 | /* ECC will be calculated automatically, and errors will be detected in | |
747 | * waitfunc. | |
748 | */ | |
749 | static void fsl_elbc_write_page(struct mtd_info *mtd, | |
750 | struct nand_chip *chip, | |
751 | const uint8_t *buf) | |
752 | { | |
753 | struct fsl_elbc_mtd *priv = chip->priv; | |
3ab8f2a2 | 754 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
755 | |
756 | fsl_elbc_write_buf(mtd, buf, mtd->writesize); | |
757 | fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
758 | ||
3ab8f2a2 | 759 | elbc_fcm_ctrl->oob_poi = chip->oob_poi; |
76b10467 SW |
760 | } |
761 | ||
762 | static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) | |
763 | { | |
3ab8f2a2 | 764 | struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
d4a32fe4 | 765 | struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
3ab8f2a2 | 766 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
76b10467 SW |
767 | struct nand_chip *chip = &priv->chip; |
768 | ||
769 | dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); | |
770 | ||
771 | /* Fill in fsl_elbc_mtd structure */ | |
772 | priv->mtd.priv = chip; | |
773 | priv->mtd.owner = THIS_MODULE; | |
03ed1078 JJ |
774 | |
775 | /* Set the ECCM according to the settings in bootloader.*/ | |
776 | priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM; | |
76b10467 SW |
777 | |
778 | /* fill in nand_chip structure */ | |
779 | /* set up function call table */ | |
780 | chip->read_byte = fsl_elbc_read_byte; | |
781 | chip->write_buf = fsl_elbc_write_buf; | |
782 | chip->read_buf = fsl_elbc_read_buf; | |
783 | chip->verify_buf = fsl_elbc_verify_buf; | |
784 | chip->select_chip = fsl_elbc_select_chip; | |
785 | chip->cmdfunc = fsl_elbc_cmdfunc; | |
786 | chip->waitfunc = fsl_elbc_wait; | |
787 | ||
ec6e0ea3 AV |
788 | chip->bbt_td = &bbt_main_descr; |
789 | chip->bbt_md = &bbt_mirror_descr; | |
790 | ||
76b10467 | 791 | /* set up nand options */ |
ec6e0ea3 AV |
792 | chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR | |
793 | NAND_USE_FLASH_BBT; | |
76b10467 | 794 | |
3ab8f2a2 | 795 | chip->controller = &elbc_fcm_ctrl->controller; |
76b10467 SW |
796 | chip->priv = priv; |
797 | ||
798 | chip->ecc.read_page = fsl_elbc_read_page; | |
799 | chip->ecc.write_page = fsl_elbc_write_page; | |
800 | ||
801 | /* If CS Base Register selects full hardware ECC then use it */ | |
802 | if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == | |
803 | BR_DECC_CHK_GEN) { | |
804 | chip->ecc.mode = NAND_ECC_HW; | |
805 | /* put in small page settings and adjust later if needed */ | |
806 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | |
807 | &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0; | |
808 | chip->ecc.size = 512; | |
809 | chip->ecc.bytes = 3; | |
810 | } else { | |
811 | /* otherwise fall back to default software ECC */ | |
812 | chip->ecc.mode = NAND_ECC_SOFT; | |
813 | } | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) | |
819 | { | |
3ab8f2a2 | 820 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
76b10467 SW |
821 | nand_release(&priv->mtd); |
822 | ||
9ebed3e6 AV |
823 | kfree(priv->mtd.name); |
824 | ||
76b10467 SW |
825 | if (priv->vbase) |
826 | iounmap(priv->vbase); | |
827 | ||
3ab8f2a2 | 828 | elbc_fcm_ctrl->chips[priv->bank] = NULL; |
76b10467 | 829 | kfree(priv); |
3ab8f2a2 | 830 | kfree(elbc_fcm_ctrl); |
76b10467 SW |
831 | return 0; |
832 | } | |
833 | ||
3ab8f2a2 RZ |
834 | static DEFINE_MUTEX(fsl_elbc_nand_mutex); |
835 | ||
836 | static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev) | |
76b10467 | 837 | { |
3ab8f2a2 | 838 | struct fsl_lbc_regs __iomem *lbc; |
76b10467 SW |
839 | struct fsl_elbc_mtd *priv; |
840 | struct resource res; | |
3ab8f2a2 RZ |
841 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; |
842 | ||
76b10467 SW |
843 | #ifdef CONFIG_MTD_PARTITIONS |
844 | static const char *part_probe_types[] | |
845 | = { "cmdlinepart", "RedBoot", NULL }; | |
846 | struct mtd_partition *parts; | |
847 | #endif | |
848 | int ret; | |
849 | int bank; | |
3ab8f2a2 RZ |
850 | struct device *dev; |
851 | struct device_node *node = pdev->dev.of_node; | |
852 | ||
853 | if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) | |
854 | return -ENODEV; | |
855 | lbc = fsl_lbc_ctrl_dev->regs; | |
856 | dev = fsl_lbc_ctrl_dev->dev; | |
76b10467 SW |
857 | |
858 | /* get, allocate and map the memory resource */ | |
859 | ret = of_address_to_resource(node, 0, &res); | |
860 | if (ret) { | |
3ab8f2a2 | 861 | dev_err(dev, "failed to get resource\n"); |
76b10467 SW |
862 | return ret; |
863 | } | |
864 | ||
865 | /* find which chip select it is connected to */ | |
866 | for (bank = 0; bank < MAX_BANKS; bank++) | |
867 | if ((in_be32(&lbc->bank[bank].br) & BR_V) && | |
868 | (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && | |
869 | (in_be32(&lbc->bank[bank].br) & | |
870 | in_be32(&lbc->bank[bank].or) & BR_BA) | |
0b824d2b | 871 | == fsl_lbc_addr(res.start)) |
76b10467 SW |
872 | break; |
873 | ||
874 | if (bank >= MAX_BANKS) { | |
3ab8f2a2 | 875 | dev_err(dev, "address did not match any chip selects\n"); |
76b10467 SW |
876 | return -ENODEV; |
877 | } | |
878 | ||
879 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
880 | if (!priv) | |
881 | return -ENOMEM; | |
882 | ||
3ab8f2a2 RZ |
883 | mutex_lock(&fsl_elbc_nand_mutex); |
884 | if (!fsl_lbc_ctrl_dev->nand) { | |
885 | elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); | |
886 | if (!elbc_fcm_ctrl) { | |
887 | dev_err(dev, "failed to allocate memory\n"); | |
888 | mutex_unlock(&fsl_elbc_nand_mutex); | |
889 | ret = -ENOMEM; | |
890 | goto err; | |
891 | } | |
892 | elbc_fcm_ctrl->counter++; | |
893 | ||
894 | spin_lock_init(&elbc_fcm_ctrl->controller.lock); | |
895 | init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); | |
896 | fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; | |
897 | } else { | |
898 | elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; | |
899 | } | |
900 | mutex_unlock(&fsl_elbc_nand_mutex); | |
901 | ||
902 | elbc_fcm_ctrl->chips[bank] = priv; | |
76b10467 | 903 | priv->bank = bank; |
3ab8f2a2 RZ |
904 | priv->ctrl = fsl_lbc_ctrl_dev; |
905 | priv->dev = dev; | |
76b10467 | 906 | |
8a19b558 | 907 | priv->vbase = ioremap(res.start, resource_size(&res)); |
76b10467 | 908 | if (!priv->vbase) { |
3ab8f2a2 | 909 | dev_err(dev, "failed to map chip region\n"); |
76b10467 SW |
910 | ret = -ENOMEM; |
911 | goto err; | |
912 | } | |
913 | ||
650da9d0 | 914 | priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start); |
9ebed3e6 AV |
915 | if (!priv->mtd.name) { |
916 | ret = -ENOMEM; | |
917 | goto err; | |
918 | } | |
919 | ||
76b10467 SW |
920 | ret = fsl_elbc_chip_init(priv); |
921 | if (ret) | |
922 | goto err; | |
923 | ||
5e81e88a | 924 | ret = nand_scan_ident(&priv->mtd, 1, NULL); |
76b10467 SW |
925 | if (ret) |
926 | goto err; | |
927 | ||
928 | ret = fsl_elbc_chip_init_tail(&priv->mtd); | |
929 | if (ret) | |
930 | goto err; | |
931 | ||
932 | ret = nand_scan_tail(&priv->mtd); | |
933 | if (ret) | |
934 | goto err; | |
935 | ||
936 | #ifdef CONFIG_MTD_PARTITIONS | |
937 | /* First look for RedBoot table or partitions on the command | |
938 | * line, these take precedence over device tree information */ | |
939 | ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0); | |
940 | if (ret < 0) | |
941 | goto err; | |
942 | ||
943 | #ifdef CONFIG_MTD_OF_PARTS | |
944 | if (ret == 0) { | |
69fd3a8d | 945 | ret = of_mtd_parse_partitions(priv->dev, node, &parts); |
76b10467 SW |
946 | if (ret < 0) |
947 | goto err; | |
948 | } | |
949 | #endif | |
950 | ||
951 | if (ret > 0) | |
952 | add_mtd_partitions(&priv->mtd, parts, ret); | |
953 | else | |
954 | #endif | |
955 | add_mtd_device(&priv->mtd); | |
956 | ||
4712fff9 SR |
957 | printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n", |
958 | (unsigned long long)res.start, priv->bank); | |
76b10467 SW |
959 | return 0; |
960 | ||
961 | err: | |
962 | fsl_elbc_chip_remove(priv); | |
963 | return ret; | |
964 | } | |
965 | ||
3ab8f2a2 | 966 | static int fsl_elbc_nand_remove(struct platform_device *pdev) |
76b10467 | 967 | { |
76b10467 | 968 | int i; |
3ab8f2a2 | 969 | struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
76b10467 | 970 | for (i = 0; i < MAX_BANKS; i++) |
3ab8f2a2 RZ |
971 | if (elbc_fcm_ctrl->chips[i]) |
972 | fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]); | |
973 | ||
974 | mutex_lock(&fsl_elbc_nand_mutex); | |
975 | elbc_fcm_ctrl->counter--; | |
976 | if (!elbc_fcm_ctrl->counter) { | |
977 | fsl_lbc_ctrl_dev->nand = NULL; | |
978 | kfree(elbc_fcm_ctrl); | |
76b10467 | 979 | } |
3ab8f2a2 | 980 | mutex_unlock(&fsl_elbc_nand_mutex); |
76b10467 SW |
981 | |
982 | return 0; | |
983 | ||
76b10467 SW |
984 | } |
985 | ||
3ab8f2a2 RZ |
986 | static const struct of_device_id fsl_elbc_nand_match[] = { |
987 | { .compatible = "fsl,elbc-fcm-nand", }, | |
76b10467 SW |
988 | {} |
989 | }; | |
990 | ||
3ab8f2a2 | 991 | static struct platform_driver fsl_elbc_nand_driver = { |
76b10467 | 992 | .driver = { |
3ab8f2a2 | 993 | .name = "fsl,elbc-fcm-nand", |
4018294b | 994 | .owner = THIS_MODULE, |
3ab8f2a2 | 995 | .of_match_table = fsl_elbc_nand_match, |
76b10467 | 996 | }, |
3ab8f2a2 RZ |
997 | .probe = fsl_elbc_nand_probe, |
998 | .remove = fsl_elbc_nand_remove, | |
76b10467 SW |
999 | }; |
1000 | ||
3ab8f2a2 | 1001 | static int __init fsl_elbc_nand_init(void) |
76b10467 | 1002 | { |
3ab8f2a2 | 1003 | return platform_driver_register(&fsl_elbc_nand_driver); |
76b10467 SW |
1004 | } |
1005 | ||
3ab8f2a2 | 1006 | static void __exit fsl_elbc_nand_exit(void) |
76b10467 | 1007 | { |
3ab8f2a2 | 1008 | platform_driver_unregister(&fsl_elbc_nand_driver); |
76b10467 SW |
1009 | } |
1010 | ||
3ab8f2a2 RZ |
1011 | module_init(fsl_elbc_nand_init); |
1012 | module_exit(fsl_elbc_nand_exit); | |
76b10467 SW |
1013 | |
1014 | MODULE_LICENSE("GPL"); | |
1015 | MODULE_AUTHOR("Freescale"); | |
1016 | MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver"); |