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mtd: denali: rename functions which is named by using capitals
[net-next-2.6.git] / drivers / mtd / nand / denali.c
CommitLineData
ce082596
JR		 1/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/wait.h>
23#include <linux/mutex.h>
24#include <linux/pci.h>
25#include <linux/mtd/mtd.h>
26#include <linux/module.h>
27
28#include "denali.h"
29
30MODULE_LICENSE("GPL");
31
5bac3acf 32/* We define a module parameter that allows the user to override
ce082596
JR		 33 * the hardware and decide what timing mode should be used.
34 */
35#define NAND_DEFAULT_TIMINGS -1
36
37static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
38module_param(onfi_timing_mode, int, S_IRUGO);
bdca6dae
CD		 39MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
40 " -1 indicates use default timings");
ce082596
JR		 41
42#define DENALI_NAND_NAME "denali-nand"
43
44/* We define a macro here that combines all interrupts this driver uses into
45 * a single constant value, for convenience. */
46#define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
47 INTR_STATUS0__ECC_TRANSACTION_DONE | \
48 INTR_STATUS0__ECC_ERR | \
49 INTR_STATUS0__PROGRAM_FAIL | \
50 INTR_STATUS0__LOAD_COMP | \
51 INTR_STATUS0__PROGRAM_COMP | \
52 INTR_STATUS0__TIME_OUT | \
53 INTR_STATUS0__ERASE_FAIL | \
54 INTR_STATUS0__RST_COMP | \
55 INTR_STATUS0__ERASE_COMP)
56
5bac3acf 57/* indicates whether or not the internal value for the flash bank is
ce082596 58 valid or not */
5bac3acf 59#define CHIP_SELECT_INVALID -1
ce082596
JR		 60
61#define SUPPORT_8BITECC 1
62
5bac3acf 63/* This macro divides two integers and rounds fractional values up
ce082596
JR		 64 * to the nearest integer value. */
65#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
66
67/* this macro allows us to convert from an MTD structure to our own
68 * device context (denali) structure.
69 */
70#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
71
72/* These constants are defined by the driver to enable common driver
73 configuration options. */
74#define SPARE_ACCESS 0x41
75#define MAIN_ACCESS 0x42
76#define MAIN_SPARE_ACCESS 0x43
77
78#define DENALI_READ 0
79#define DENALI_WRITE 0x100
80
81/* types of device accesses. We can issue commands and get status */
82#define COMMAND_CYCLE 0
83#define ADDR_CYCLE 1
84#define STATUS_CYCLE 2
85
5bac3acf 86/* this is a helper macro that allows us to
ce082596
JR		 87 * format the bank into the proper bits for the controller */
88#define BANK(x) ((x) << 24)
89
90/* List of platforms this NAND controller has be integrated into */
91static const struct pci_device_id denali_pci_ids[] = {
92 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
93 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
94 { /* end: all zeroes */ }
95};
96
97
5bac3acf
C		 98/* these are static lookup tables that give us easy access to
99 registers in the NAND controller.
ce082596 100 */
5bac3acf
C		 101static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
102 INTR_STATUS1,
103 INTR_STATUS2,
ce082596
JR		 104 INTR_STATUS3};
105
106static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
5bac3acf
C		 107 DEVICE_RESET__BANK1,
108 DEVICE_RESET__BANK2,
109 DEVICE_RESET__BANK3};
ce082596
JR		 110
111static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
5bac3acf
C		 112 INTR_STATUS1__TIME_OUT,
113 INTR_STATUS2__TIME_OUT,
114 INTR_STATUS3__TIME_OUT};
ce082596
JR		 115
116static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
5bac3acf
C		 117 INTR_STATUS1__RST_COMP,
118 INTR_STATUS2__RST_COMP,
119 INTR_STATUS3__RST_COMP};
ce082596
JR		 120
121/* specifies the debug level of the driver */
a99d1796 122static int nand_debug_level;
ce082596
JR		 123
124/* forward declarations */
125static void clear_interrupts(struct denali_nand_info *denali);
bdca6dae
CD		 126static uint32_t wait_for_irq(struct denali_nand_info *denali,
127 uint32_t irq_mask);
128static void denali_irq_enable(struct denali_nand_info *denali,
129 uint32_t int_mask);
ce082596
JR		 130static uint32_t read_interrupt_status(struct denali_nand_info *denali);
131
132#define DEBUG_DENALI 0
133
134/* This is a wrapper for writing to the denali registers.
135 * this allows us to create debug information so we can
5bac3acf 136 * observe how the driver is programming the device.
ce082596
JR		 137 * it uses standard linux convention for (val, addr) */
138static void denali_write32(uint32_t value, void *addr)
139{
5bac3acf 140 iowrite32(value, addr);
ce082596
JR		 141
142#if DEBUG_DENALI
bdca6dae
CD		 143 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
144 (uint32_t)((uint32_t)addr & 0x1fff));
ce082596 145#endif
5bac3acf 146}
ce082596 147
bdca6dae
CD		 148/* Certain operations for the denali NAND controller use
149 * an indexed mode to read/write data. The operation is
150 * performed by writing the address value of the command
151 * to the device memory followed by the data. This function
152 * abstracts this common operation.
ce082596 153*/
bdca6dae
CD		 154static void index_addr(struct denali_nand_info *denali,
155 uint32_t address, uint32_t data)
ce082596
JR		 156{
157 denali_write32(address, denali->flash_mem);
158 denali_write32(data, denali->flash_mem + 0x10);
159}
160
161/* Perform an indexed read of the device */
162static void index_addr_read_data(struct denali_nand_info *denali,
163 uint32_t address, uint32_t *pdata)
164{
165 denali_write32(address, denali->flash_mem);
166 *pdata = ioread32(denali->flash_mem + 0x10);
167}
168
5bac3acf 169/* We need to buffer some data for some of the NAND core routines.
ce082596
JR		 170 * The operations manage buffering that data. */
171static void reset_buf(struct denali_nand_info *denali)
172{
173 denali->buf.head = denali->buf.tail = 0;
174}
175
176static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
177{
178 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
179 denali->buf.buf[denali->buf.tail++] = byte;
180}
181
182/* reads the status of the device */
183static void read_status(struct denali_nand_info *denali)
184{
185 uint32_t cmd = 0x0;
186
187 /* initialize the data buffer to store status */
188 reset_buf(denali);
189
190 /* initiate a device status read */
5bac3acf 191 cmd = MODE_11 | BANK(denali->flash_bank);
ce082596
JR		 192 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
193 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
194
195 /* update buffer with status value */
196 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
197
198#if DEBUG_DENALI
bdca6dae
CD		 199 printk(KERN_INFO "device reporting status value of 0x%2x\n",
200 denali->buf.buf[0]);
ce082596
JR		 201#endif
202}
203
204/* resets a specific device connected to the core */
205static void reset_bank(struct denali_nand_info *denali)
206{
207 uint32_t irq_status = 0;
5bac3acf 208 uint32_t irq_mask = reset_complete[denali->flash_bank] |
ce082596
JR		 209 operation_timeout[denali->flash_bank];
210 int bank = 0;
211
212 clear_interrupts(denali);
213
214 bank = device_reset_banks[denali->flash_bank];
215 denali_write32(bank, denali->flash_reg + DEVICE_RESET);
216
217 irq_status = wait_for_irq(denali, irq_mask);
5bac3acf 218
ce082596 219 if (irq_status & operation_timeout[denali->flash_bank])
ce082596 220 printk(KERN_ERR "reset bank failed.\n");
ce082596
JR		 221}
222
223/* Reset the flash controller */
eda936ef 224static uint16_t denali_nand_reset(struct denali_nand_info *denali)
ce082596
JR		 225{
226 uint32_t i;
227
228 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
229 __FILE__, __LINE__, __func__);
230
231 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
232 denali_write32(reset_complete[i] | operation_timeout[i],
233 denali->flash_reg + intr_status_addresses[i]);
234
235 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
bdca6dae
CD		 236 denali_write32(device_reset_banks[i],
237 denali->flash_reg + DEVICE_RESET);
238 while (!(ioread32(denali->flash_reg +
239 intr_status_addresses[i]) &
ce082596
JR		 240 (reset_complete[i] | operation_timeout[i])))
241 ;
242 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
243 operation_timeout[i])
244 nand_dbg_print(NAND_DBG_WARN,
245 "NAND Reset operation timed out on bank %d\n", i);
246 }
247
248 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
249 denali_write32(reset_complete[i] | operation_timeout[i],
250 denali->flash_reg + intr_status_addresses[i]);
251
252 return PASS;
253}
254
bdca6dae
CD		 255/* this routine calculates the ONFI timing values for a given mode and
256 * programs the clocking register accordingly. The mode is determined by
257 * the get_onfi_nand_para routine.
ce082596 258 */
eda936ef 259static void nand_onfi_timing_set(struct denali_nand_info *denali,
bdca6dae 260 uint16_t mode)
ce082596
JR		 261{
262 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
263 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
264 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
265 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
266 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
267 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
268 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
269 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
270 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
271 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
272 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
273 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
274
275 uint16_t TclsRising = 1;
276 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
277 uint16_t dv_window = 0;
278 uint16_t en_lo, en_hi;
279 uint16_t acc_clks;
280 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
281
282 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
283 __FILE__, __LINE__, __func__);
284
285 en_lo = CEIL_DIV(Trp[mode], CLK_X);
286 en_hi = CEIL_DIV(Treh[mode], CLK_X);
287#if ONFI_BLOOM_TIME
288 if ((en_hi * CLK_X) < (Treh[mode] + 2))
289 en_hi++;
290#endif
291
292 if ((en_lo + en_hi) * CLK_X < Trc[mode])
293 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
294
295 if ((en_lo + en_hi) < CLK_MULTI)
296 en_lo += CLK_MULTI - en_lo - en_hi;
297
298 while (dv_window < 8) {
299 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
300
301 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
302
303 data_invalid =
304 data_invalid_rhoh <
305 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
306
307 dv_window = data_invalid - Trea[mode];
308
309 if (dv_window < 8)
310 en_lo++;
311 }
312
313 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
314
315 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
316 acc_clks++;
317
318 if ((data_invalid - acc_clks * CLK_X) < 2)
319 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
320 __FILE__, __LINE__);
321
322 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
323 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
324 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
325 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
326 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
327 if (!TclsRising)
328 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
329 if (cs_cnt == 0)
330 cs_cnt = 1;
331
332 if (Tcea[mode]) {
333 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
334 cs_cnt++;
335 }
336
337#if MODE5_WORKAROUND
338 if (mode == 5)
339 acc_clks = 5;
340#endif
341
342 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
343 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
344 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
345 acc_clks = 6;
346
347 denali_write32(acc_clks, denali->flash_reg + ACC_CLKS);
348 denali_write32(re_2_we, denali->flash_reg + RE_2_WE);
349 denali_write32(re_2_re, denali->flash_reg + RE_2_RE);
350 denali_write32(we_2_re, denali->flash_reg + WE_2_RE);
351 denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
352 denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
353 denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
354 denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
355}
356
357/* configures the initial ECC settings for the controller */
358static void set_ecc_config(struct denali_nand_info *denali)
359{
360#if SUPPORT_8BITECC
361 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
362 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
363 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
364#endif
365
bdca6dae
CD		 366 if ((ioread32(denali->flash_reg + ECC_CORRECTION) &
367 ECC_CORRECTION__VALUE) == 1) {
ce082596 368 denali->dev_info.wECCBytesPerSector = 4;
bdca6dae
CD		 369 denali->dev_info.wECCBytesPerSector *=
370 denali->dev_info.wDevicesConnected;
ce082596
JR		 371 denali->dev_info.wNumPageSpareFlag =
372 denali->dev_info.wPageSpareSize -
373 denali->dev_info.wPageDataSize /
374 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
375 denali->dev_info.wECCBytesPerSector
376 - denali->dev_info.wSpareSkipBytes;
377 } else {
378 denali->dev_info.wECCBytesPerSector =
379 (ioread32(denali->flash_reg + ECC_CORRECTION) &
380 ECC_CORRECTION__VALUE) * 13 / 8;
381 if ((denali->dev_info.wECCBytesPerSector) % 2 == 0)
382 denali->dev_info.wECCBytesPerSector += 2;
383 else
384 denali->dev_info.wECCBytesPerSector += 1;
385
bdca6dae
CD		 386 denali->dev_info.wECCBytesPerSector *=
387 denali->dev_info.wDevicesConnected;
388 denali->dev_info.wNumPageSpareFlag =
389 denali->dev_info.wPageSpareSize -
ce082596
JR		 390 denali->dev_info.wPageDataSize /
391 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
392 denali->dev_info.wECCBytesPerSector
393 - denali->dev_info.wSpareSkipBytes;
394 }
395}
396
397/* queries the NAND device to see what ONFI modes it supports. */
398static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
399{
400 int i;
401 uint16_t blks_lun_l, blks_lun_h, n_of_luns;
402 uint32_t blockperlun, id;
403
404 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
405
406 while (!((ioread32(denali->flash_reg + INTR_STATUS0) &
bdca6dae
CD		 407 INTR_STATUS0__RST_COMP) |
408 (ioread32(denali->flash_reg + INTR_STATUS0) &
409 INTR_STATUS0__TIME_OUT)))
ce082596
JR		 410 ;
411
bdca6dae
CD		 412 if (ioread32(denali->flash_reg + INTR_STATUS0) &
413 INTR_STATUS0__RST_COMP) {
414 denali_write32(DEVICE_RESET__BANK1,
415 denali->flash_reg + DEVICE_RESET);
ce082596
JR		 416 while (!((ioread32(denali->flash_reg + INTR_STATUS1) &
417 INTR_STATUS1__RST_COMP) |
418 (ioread32(denali->flash_reg + INTR_STATUS1) &
419 INTR_STATUS1__TIME_OUT)))
420 ;
421
422 if (ioread32(denali->flash_reg + INTR_STATUS1) &
423 INTR_STATUS1__RST_COMP) {
424 denali_write32(DEVICE_RESET__BANK2,
425 denali->flash_reg + DEVICE_RESET);
426 while (!((ioread32(denali->flash_reg + INTR_STATUS2) &
427 INTR_STATUS2__RST_COMP) |
428 (ioread32(denali->flash_reg + INTR_STATUS2) &
429 INTR_STATUS2__TIME_OUT)))
430 ;
431
432 if (ioread32(denali->flash_reg + INTR_STATUS2) &
433 INTR_STATUS2__RST_COMP) {
434 denali_write32(DEVICE_RESET__BANK3,
435 denali->flash_reg + DEVICE_RESET);
bdca6dae
CD		 436 while (!((ioread32(denali->flash_reg +
437 INTR_STATUS3) &
438 INTR_STATUS3__RST_COMP) |
439 (ioread32(denali->flash_reg +
440 INTR_STATUS3) &
441 INTR_STATUS3__TIME_OUT)))
ce082596
JR		 442 ;
443 } else {
444 printk(KERN_ERR "Getting a time out for bank 2!\n");
445 }
446 } else {
447 printk(KERN_ERR "Getting a time out for bank 1!\n");
448 }
449 }
450
bdca6dae
CD		 451 denali_write32(INTR_STATUS0__TIME_OUT,
452 denali->flash_reg + INTR_STATUS0);
453 denali_write32(INTR_STATUS1__TIME_OUT,
454 denali->flash_reg + INTR_STATUS1);
455 denali_write32(INTR_STATUS2__TIME_OUT,
456 denali->flash_reg + INTR_STATUS2);
457 denali_write32(INTR_STATUS3__TIME_OUT,
458 denali->flash_reg + INTR_STATUS3);
ce082596
JR		 459
460 denali->dev_info.wONFIDevFeatures =
461 ioread32(denali->flash_reg + ONFI_DEVICE_FEATURES);
462 denali->dev_info.wONFIOptCommands =
463 ioread32(denali->flash_reg + ONFI_OPTIONAL_COMMANDS);
464 denali->dev_info.wONFITimingMode =
465 ioread32(denali->flash_reg + ONFI_TIMING_MODE);
466 denali->dev_info.wONFIPgmCacheTimingMode =
467 ioread32(denali->flash_reg + ONFI_PGM_CACHE_TIMING_MODE);
468
469 n_of_luns = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
470 ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS;
bdca6dae
CD		 471 blks_lun_l = ioread32(denali->flash_reg +
472 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L);
473 blks_lun_h = ioread32(denali->flash_reg +
474 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U);
ce082596
JR		 475
476 blockperlun = (blks_lun_h << 16) | blks_lun_l;
477
478 denali->dev_info.wTotalBlocks = n_of_luns * blockperlun;
479
480 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
481 ONFI_TIMING_MODE__VALUE))
482 return FAIL;
483
484 for (i = 5; i > 0; i--) {
bdca6dae
CD		 485 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
486 (0x01 << i))
ce082596
JR		 487 break;
488 }
489
eda936ef 490 nand_onfi_timing_set(denali, i);
ce082596
JR		 491
492 index_addr(denali, MODE_11 | 0, 0x90);
493 index_addr(denali, MODE_11 | 1, 0);
494
495 for (i = 0; i < 3; i++)
496 index_addr_read_data(denali, MODE_11 | 2, &id);
497
498 nand_dbg_print(NAND_DBG_DEBUG, "3rd ID: 0x%x\n", id);
499
500 denali->dev_info.MLCDevice = id & 0x0C;
501
502 /* By now, all the ONFI devices we know support the page cache */
503 /* rw feature. So here we enable the pipeline_rw_ahead feature */
504 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
505 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
506
507 return PASS;
508}
509
510static void get_samsung_nand_para(struct denali_nand_info *denali)
511{
512 uint8_t no_of_planes;
513 uint32_t blk_size;
514 uint64_t plane_size, capacity;
515 uint32_t id_bytes[5];
516 int i;
517
518 index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90);
519 index_addr(denali, (uint32_t)(MODE_11 | 1), 0);
520 for (i = 0; i < 5; i++)
bdca6dae
CD		 521 index_addr_read_data(denali, (uint32_t)(MODE_11 | 2),
522 &id_bytes[i]);
ce082596
JR		 523
524 nand_dbg_print(NAND_DBG_DEBUG,
525 "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
526 id_bytes[0], id_bytes[1], id_bytes[2],
527 id_bytes[3], id_bytes[4]);
528
529 if ((id_bytes[1] & 0xff) == 0xd3) { /* Samsung K9WAG08U1A */
530 /* Set timing register values according to datasheet */
531 denali_write32(5, denali->flash_reg + ACC_CLKS);
532 denali_write32(20, denali->flash_reg + RE_2_WE);
533 denali_write32(12, denali->flash_reg + WE_2_RE);
534 denali_write32(14, denali->flash_reg + ADDR_2_DATA);
535 denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT);
536 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
537 denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
538 }
539
540 no_of_planes = 1 << ((id_bytes[4] & 0x0c) >> 2);
541 plane_size = (uint64_t)64 << ((id_bytes[4] & 0x70) >> 4);
bdca6dae
CD		 542 blk_size = 64 << ((ioread32(denali->flash_reg + DEVICE_PARAM_1) &
543 0x30) >> 4);
ce082596
JR		 544 capacity = (uint64_t)128 * plane_size * no_of_planes;
545
546 do_div(capacity, blk_size);
547 denali->dev_info.wTotalBlocks = capacity;
548}
549
550static void get_toshiba_nand_para(struct denali_nand_info *denali)
551{
552 void __iomem *scratch_reg;
553 uint32_t tmp;
554
555 /* Workaround to fix a controller bug which reports a wrong */
556 /* spare area size for some kind of Toshiba NAND device */
557 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
558 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
559 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
560 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
561 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
bdca6dae
CD		 562 denali_write32(tmp,
563 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
ce082596
JR		 564#if SUPPORT_15BITECC
565 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
566#elif SUPPORT_8BITECC
567 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
568#endif
569 }
570
571 /* As Toshiba NAND can not provide it's block number, */
572 /* so here we need user to provide the correct block */
573 /* number in a scratch register before the Linux NAND */
574 /* driver is loaded. If no valid value found in the scratch */
575 /* register, then we use default block number value */
576 scratch_reg = ioremap_nocache(SCRATCH_REG_ADDR, SCRATCH_REG_SIZE);
577 if (!scratch_reg) {
578 printk(KERN_ERR "Spectra: ioremap failed in %s, Line %d",
579 __FILE__, __LINE__);
580 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
581 } else {
582 nand_dbg_print(NAND_DBG_WARN,
583 "Spectra: ioremap reg address: 0x%p\n", scratch_reg);
584 denali->dev_info.wTotalBlocks = 1 << ioread8(scratch_reg);
585 if (denali->dev_info.wTotalBlocks < 512)
586 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
587 iounmap(scratch_reg);
588 }
589}
590
591static void get_hynix_nand_para(struct denali_nand_info *denali)
592{
593 void __iomem *scratch_reg;
594 uint32_t main_size, spare_size;
595
596 switch (denali->dev_info.wDeviceID) {
597 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
598 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
599 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
600 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
601 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
bdca6dae
CD		 602 main_size = 4096 *
603 ioread32(denali->flash_reg + DEVICES_CONNECTED);
604 spare_size = 224 *
605 ioread32(denali->flash_reg + DEVICES_CONNECTED);
606 denali_write32(main_size,
607 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
608 denali_write32(spare_size,
609 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
ce082596
JR		 610 denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
611#if SUPPORT_15BITECC
612 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
613#elif SUPPORT_8BITECC
614 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
615#endif
616 denali->dev_info.MLCDevice = 1;
617 break;
618 default:
619 nand_dbg_print(NAND_DBG_WARN,
620 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
621 "Will use default parameter values instead.\n",
622 denali->dev_info.wDeviceID);
623 }
624
625 scratch_reg = ioremap_nocache(SCRATCH_REG_ADDR, SCRATCH_REG_SIZE);
626 if (!scratch_reg) {
627 printk(KERN_ERR "Spectra: ioremap failed in %s, Line %d",
628 __FILE__, __LINE__);
629 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
630 } else {
631 nand_dbg_print(NAND_DBG_WARN,
632 "Spectra: ioremap reg address: 0x%p\n", scratch_reg);
633 denali->dev_info.wTotalBlocks = 1 << ioread8(scratch_reg);
634 if (denali->dev_info.wTotalBlocks < 512)
635 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
636 iounmap(scratch_reg);
637 }
638}
639
640/* determines how many NAND chips are connected to the controller. Note for
5bac3acf 641 Intel CE4100 devices we don't support more than one device.
ce082596
JR		 642 */
643static void find_valid_banks(struct denali_nand_info *denali)
644{
645 uint32_t id[LLD_MAX_FLASH_BANKS];
646 int i;
647
648 denali->total_used_banks = 1;
649 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
650 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
651 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
bdca6dae
CD		 652 index_addr_read_data(denali,
653 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
ce082596
JR		 654
655 nand_dbg_print(NAND_DBG_DEBUG,
656 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
657
658 if (i == 0) {
659 if (!(id[i] & 0x0ff))
660 break; /* WTF? */
661 } else {
662 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
663 denali->total_used_banks++;
664 else
665 break;
666 }
667 }
668
345b1d3b 669 if (denali->platform == INTEL_CE4100) {
ce082596
JR		 670 /* Platform limitations of the CE4100 device limit
671 * users to a single chip solution for NAND.
5bac3acf
C		 672 * Multichip support is not enabled.
673 */
345b1d3b 674 if (denali->total_used_banks != 1) {
ce082596
JR		 675 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
676 "a single NAND device.\n");
677 BUG();
678 }
679 }
680 nand_dbg_print(NAND_DBG_DEBUG,
681 "denali->total_used_banks: %d\n", denali->total_used_banks);
682}
683
684static void detect_partition_feature(struct denali_nand_info *denali)
685{
686 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
687 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
688 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
689 denali->dev_info.wSpectraStartBlock =
690 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
691 MIN_MAX_BANK_1__MIN_VALUE) *
692 denali->dev_info.wTotalBlocks)
693 +
694 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
695 MIN_BLK_ADDR_1__VALUE);
696
697 denali->dev_info.wSpectraEndBlock =
698 (((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
699 MIN_MAX_BANK_1__MAX_VALUE) >> 2) *
700 denali->dev_info.wTotalBlocks)
701 +
702 (ioread32(denali->flash_reg + MAX_BLK_ADDR_1) &
703 MAX_BLK_ADDR_1__VALUE);
704
bdca6dae
CD		 705 denali->dev_info.wTotalBlocks *=
706 denali->total_used_banks;
ce082596
JR		 707
708 if (denali->dev_info.wSpectraEndBlock >=
709 denali->dev_info.wTotalBlocks) {
710 denali->dev_info.wSpectraEndBlock =
711 denali->dev_info.wTotalBlocks - 1;
712 }
713
714 denali->dev_info.wDataBlockNum =
715 denali->dev_info.wSpectraEndBlock -
716 denali->dev_info.wSpectraStartBlock + 1;
717 } else {
bdca6dae
CD		 718 denali->dev_info.wTotalBlocks *=
719 denali->total_used_banks;
720 denali->dev_info.wSpectraStartBlock =
721 SPECTRA_START_BLOCK;
ce082596
JR		 722 denali->dev_info.wSpectraEndBlock =
723 denali->dev_info.wTotalBlocks - 1;
724 denali->dev_info.wDataBlockNum =
725 denali->dev_info.wSpectraEndBlock -
726 denali->dev_info.wSpectraStartBlock + 1;
727 }
728 } else {
729 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
730 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK;
bdca6dae
CD		 731 denali->dev_info.wSpectraEndBlock =
732 denali->dev_info.wTotalBlocks - 1;
ce082596
JR		 733 denali->dev_info.wDataBlockNum =
734 denali->dev_info.wSpectraEndBlock -
735 denali->dev_info.wSpectraStartBlock + 1;
736 }
737}
738
739static void dump_device_info(struct denali_nand_info *denali)
740{
741 nand_dbg_print(NAND_DBG_DEBUG, "denali->dev_info:\n");
742 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMaker: 0x%x\n",
743 denali->dev_info.wDeviceMaker);
744 nand_dbg_print(NAND_DBG_DEBUG, "DeviceID: 0x%x\n",
745 denali->dev_info.wDeviceID);
746 nand_dbg_print(NAND_DBG_DEBUG, "DeviceType: 0x%x\n",
747 denali->dev_info.wDeviceType);
748 nand_dbg_print(NAND_DBG_DEBUG, "SpectraStartBlock: %d\n",
749 denali->dev_info.wSpectraStartBlock);
750 nand_dbg_print(NAND_DBG_DEBUG, "SpectraEndBlock: %d\n",
751 denali->dev_info.wSpectraEndBlock);
752 nand_dbg_print(NAND_DBG_DEBUG, "TotalBlocks: %d\n",
753 denali->dev_info.wTotalBlocks);
754 nand_dbg_print(NAND_DBG_DEBUG, "PagesPerBlock: %d\n",
755 denali->dev_info.wPagesPerBlock);
756 nand_dbg_print(NAND_DBG_DEBUG, "PageSize: %d\n",
757 denali->dev_info.wPageSize);
758 nand_dbg_print(NAND_DBG_DEBUG, "PageDataSize: %d\n",
759 denali->dev_info.wPageDataSize);
760 nand_dbg_print(NAND_DBG_DEBUG, "PageSpareSize: %d\n",
761 denali->dev_info.wPageSpareSize);
762 nand_dbg_print(NAND_DBG_DEBUG, "NumPageSpareFlag: %d\n",
763 denali->dev_info.wNumPageSpareFlag);
764 nand_dbg_print(NAND_DBG_DEBUG, "ECCBytesPerSector: %d\n",
765 denali->dev_info.wECCBytesPerSector);
766 nand_dbg_print(NAND_DBG_DEBUG, "BlockSize: %d\n",
767 denali->dev_info.wBlockSize);
768 nand_dbg_print(NAND_DBG_DEBUG, "BlockDataSize: %d\n",
769 denali->dev_info.wBlockDataSize);
770 nand_dbg_print(NAND_DBG_DEBUG, "DataBlockNum: %d\n",
771 denali->dev_info.wDataBlockNum);
772 nand_dbg_print(NAND_DBG_DEBUG, "PlaneNum: %d\n",
773 denali->dev_info.bPlaneNum);
774 nand_dbg_print(NAND_DBG_DEBUG, "DeviceMainAreaSize: %d\n",
775 denali->dev_info.wDeviceMainAreaSize);
776 nand_dbg_print(NAND_DBG_DEBUG, "DeviceSpareAreaSize: %d\n",
777 denali->dev_info.wDeviceSpareAreaSize);
778 nand_dbg_print(NAND_DBG_DEBUG, "DevicesConnected: %d\n",
779 denali->dev_info.wDevicesConnected);
780 nand_dbg_print(NAND_DBG_DEBUG, "DeviceWidth: %d\n",
781 denali->dev_info.wDeviceWidth);
782 nand_dbg_print(NAND_DBG_DEBUG, "HWRevision: 0x%x\n",
783 denali->dev_info.wHWRevision);
784 nand_dbg_print(NAND_DBG_DEBUG, "HWFeatures: 0x%x\n",
785 denali->dev_info.wHWFeatures);
786 nand_dbg_print(NAND_DBG_DEBUG, "ONFIDevFeatures: 0x%x\n",
787 denali->dev_info.wONFIDevFeatures);
788 nand_dbg_print(NAND_DBG_DEBUG, "ONFIOptCommands: 0x%x\n",
789 denali->dev_info.wONFIOptCommands);
790 nand_dbg_print(NAND_DBG_DEBUG, "ONFITimingMode: 0x%x\n",
791 denali->dev_info.wONFITimingMode);
792 nand_dbg_print(NAND_DBG_DEBUG, "ONFIPgmCacheTimingMode: 0x%x\n",
793 denali->dev_info.wONFIPgmCacheTimingMode);
794 nand_dbg_print(NAND_DBG_DEBUG, "MLCDevice: %s\n",
795 denali->dev_info.MLCDevice ? "Yes" : "No");
796 nand_dbg_print(NAND_DBG_DEBUG, "SpareSkipBytes: %d\n",
797 denali->dev_info.wSpareSkipBytes);
798 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageNumber: %d\n",
799 denali->dev_info.nBitsInPageNumber);
800 nand_dbg_print(NAND_DBG_DEBUG, "BitsInPageDataSize: %d\n",
801 denali->dev_info.nBitsInPageDataSize);
802 nand_dbg_print(NAND_DBG_DEBUG, "BitsInBlockDataSize: %d\n",
803 denali->dev_info.nBitsInBlockDataSize);
804}
805
eda936ef 806static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
ce082596
JR		 807{
808 uint16_t status = PASS;
809 uint8_t no_of_planes;
810
811 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
812 __FILE__, __LINE__, __func__);
813
bdca6dae
CD		 814 denali->dev_info.wDeviceMaker =
815 ioread32(denali->flash_reg + MANUFACTURER_ID);
816 denali->dev_info.wDeviceID =
817 ioread32(denali->flash_reg + DEVICE_ID);
818 denali->dev_info.bDeviceParam0 =
819 ioread32(denali->flash_reg + DEVICE_PARAM_0);
820 denali->dev_info.bDeviceParam1 =
821 ioread32(denali->flash_reg + DEVICE_PARAM_1);
822 denali->dev_info.bDeviceParam2 =
823 ioread32(denali->flash_reg + DEVICE_PARAM_2);
ce082596 824
bdca6dae
CD		 825 denali->dev_info.MLCDevice =
826 ioread32(denali->flash_reg + DEVICE_PARAM_0) & 0x0c;
ce082596
JR		 827
828 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
829 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
830 if (FAIL == get_onfi_nand_para(denali))
831 return FAIL;
832 } else if (denali->dev_info.wDeviceMaker == 0xEC) { /* Samsung NAND */
833 get_samsung_nand_para(denali);
834 } else if (denali->dev_info.wDeviceMaker == 0x98) { /* Toshiba NAND */
835 get_toshiba_nand_para(denali);
836 } else if (denali->dev_info.wDeviceMaker == 0xAD) { /* Hynix NAND */
837 get_hynix_nand_para(denali);
838 } else {
839 denali->dev_info.wTotalBlocks = GLOB_HWCTL_DEFAULT_BLKS;
840 }
841
842 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
843 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
844 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
845 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
846 ioread32(denali->flash_reg + ACC_CLKS),
847 ioread32(denali->flash_reg + RE_2_WE),
848 ioread32(denali->flash_reg + WE_2_RE),
849 ioread32(denali->flash_reg + ADDR_2_DATA),
850 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
851 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
852 ioread32(denali->flash_reg + CS_SETUP_CNT));
853
854 denali->dev_info.wHWRevision = ioread32(denali->flash_reg + REVISION);
855 denali->dev_info.wHWFeatures = ioread32(denali->flash_reg + FEATURES);
856
857 denali->dev_info.wDeviceMainAreaSize =
858 ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
859 denali->dev_info.wDeviceSpareAreaSize =
860 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
861
862 denali->dev_info.wPageDataSize =
863 ioread32(denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
864
865 /* Note: When using the Micon 4K NAND device, the controller will report
866 * Page Spare Size as 216 bytes. But Micron's Spec say it's 218 bytes.
867 * And if force set it to 218 bytes, the controller can not work
868 * correctly. So just let it be. But keep in mind that this bug may
869 * cause
870 * other problems in future. - Yunpeng 2008-10-10
871 */
872 denali->dev_info.wPageSpareSize =
873 ioread32(denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
874
bdca6dae
CD		 875 denali->dev_info.wPagesPerBlock =
876 ioread32(denali->flash_reg + PAGES_PER_BLOCK);
ce082596
JR		 877
878 denali->dev_info.wPageSize =
879 denali->dev_info.wPageDataSize + denali->dev_info.wPageSpareSize;
880 denali->dev_info.wBlockSize =
881 denali->dev_info.wPageSize * denali->dev_info.wPagesPerBlock;
882 denali->dev_info.wBlockDataSize =
883 denali->dev_info.wPagesPerBlock * denali->dev_info.wPageDataSize;
884
bdca6dae
CD		 885 denali->dev_info.wDeviceWidth =
886 ioread32(denali->flash_reg + DEVICE_WIDTH);
ce082596
JR		 887 denali->dev_info.wDeviceType =
888 ((ioread32(denali->flash_reg + DEVICE_WIDTH) > 0) ? 16 : 8);
889
bdca6dae
CD		 890 denali->dev_info.wDevicesConnected =
891 ioread32(denali->flash_reg + DEVICES_CONNECTED);
ce082596
JR		 892
893 denali->dev_info.wSpareSkipBytes =
894 ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES) *
895 denali->dev_info.wDevicesConnected;
896
897 denali->dev_info.nBitsInPageNumber =
898 ilog2(denali->dev_info.wPagesPerBlock);
899 denali->dev_info.nBitsInPageDataSize =
900 ilog2(denali->dev_info.wPageDataSize);
901 denali->dev_info.nBitsInBlockDataSize =
902 ilog2(denali->dev_info.wBlockDataSize);
903
904 set_ecc_config(denali);
905
906 no_of_planes = ioread32(denali->flash_reg + NUMBER_OF_PLANES) &
907 NUMBER_OF_PLANES__VALUE;
908
909 switch (no_of_planes) {
910 case 0:
911 case 1:
912 case 3:
913 case 7:
914 denali->dev_info.bPlaneNum = no_of_planes + 1;
915 break;
916 default:
917 status = FAIL;
918 break;
919 }
920
921 find_valid_banks(denali);
922
923 detect_partition_feature(denali);
924
925 dump_device_info(denali);
926
927 /* If the user specified to override the default timings
5bac3acf 928 * with a specific ONFI mode, we apply those changes here.
ce082596
JR		 929 */
930 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
eda936ef 931 nand_onfi_timing_set(denali, onfi_timing_mode);
ce082596
JR		 932
933 return status;
934}
935
eda936ef 936static void denali_set_intr_modes(struct denali_nand_info *denali,
ce082596
JR		 937 uint16_t INT_ENABLE)
938{
939 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
940 __FILE__, __LINE__, __func__);
941
942 if (INT_ENABLE)
943 denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
944 else
945 denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
946}
947
948/* validation function to verify that the controlling software is making
949 a valid request
950 */
951static inline bool is_flash_bank_valid(int flash_bank)
952{
5bac3acf 953 return (flash_bank >= 0 && flash_bank < 4);
ce082596
JR		 954}
955
956static void denali_irq_init(struct denali_nand_info *denali)
957{
958 uint32_t int_mask = 0;
959
960 /* Disable global interrupts */
eda936ef 961 denali_set_intr_modes(denali, false);
ce082596
JR		 962
963 int_mask = DENALI_IRQ_ALL;
964
965 /* Clear all status bits */
966 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0);
967 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1);
968 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2);
969 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3);
970
971 denali_irq_enable(denali, int_mask);
972}
973
974static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
975{
eda936ef 976 denali_set_intr_modes(denali, false);
ce082596
JR		 977 free_irq(irqnum, denali);
978}
979
bdca6dae
CD		 980static void denali_irq_enable(struct denali_nand_info *denali,
981 uint32_t int_mask)
ce082596
JR		 982{
983 denali_write32(int_mask, denali->flash_reg + INTR_EN0);
984 denali_write32(int_mask, denali->flash_reg + INTR_EN1);
985 denali_write32(int_mask, denali->flash_reg + INTR_EN2);
986 denali_write32(int_mask, denali->flash_reg + INTR_EN3);
987}
988
989/* This function only returns when an interrupt that this driver cares about
5bac3acf 990 * occurs. This is to reduce the overhead of servicing interrupts
ce082596
JR		 991 */
992static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
993{
a99d1796 994 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
ce082596
JR		 995}
996
997/* Interrupts are cleared by writing a 1 to the appropriate status bit */
bdca6dae
CD		 998static inline void clear_interrupt(struct denali_nand_info *denali,
999 uint32_t irq_mask)
ce082596
JR		 1000{
1001 uint32_t intr_status_reg = 0;
1002
1003 intr_status_reg = intr_status_addresses[denali->flash_bank];
1004
1005 denali_write32(irq_mask, denali->flash_reg + intr_status_reg);
1006}
1007
1008static void clear_interrupts(struct denali_nand_info *denali)
1009{
1010 uint32_t status = 0x0;
1011 spin_lock_irq(&denali->irq_lock);
1012
1013 status = read_interrupt_status(denali);
1014
1015#if DEBUG_DENALI
1016 denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
1017 denali->idx %= 32;
1018#endif
1019
1020 denali->irq_status = 0x0;
1021 spin_unlock_irq(&denali->irq_lock);
1022}
1023
1024static uint32_t read_interrupt_status(struct denali_nand_info *denali)
1025{
1026 uint32_t intr_status_reg = 0;
1027
1028 intr_status_reg = intr_status_addresses[denali->flash_bank];
1029
1030 return ioread32(denali->flash_reg + intr_status_reg);
1031}
1032
1033#if DEBUG_DENALI
1034static void print_irq_log(struct denali_nand_info *denali)
1035{
1036 int i = 0;
1037
bf1806dd 1038 printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
ce082596 1039 for (i = 0; i < 32; i++)
bf1806dd 1040 printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
ce082596
JR		 1041}
1042#endif
1043
5bac3acf
C		 1044/* This is the interrupt service routine. It handles all interrupts
1045 * sent to this device. Note that on CE4100, this is a shared
1046 * interrupt.
ce082596
JR		 1047 */
1048static irqreturn_t denali_isr(int irq, void *dev_id)
1049{
1050 struct denali_nand_info *denali = dev_id;
1051 uint32_t irq_status = 0x0;
1052 irqreturn_t result = IRQ_NONE;
1053
1054 spin_lock(&denali->irq_lock);
1055
5bac3acf
C		 1056 /* check to see if a valid NAND chip has
1057 * been selected.
ce082596 1058 */
345b1d3b 1059 if (is_flash_bank_valid(denali->flash_bank)) {
5bac3acf 1060 /* check to see if controller generated
ce082596 1061 * the interrupt, since this is a shared interrupt */
bdca6dae
CD		 1062 irq_status = denali_irq_detected(denali);
1063 if (irq_status != 0) {
ce082596 1064#if DEBUG_DENALI
bdca6dae
CD		 1065 denali->irq_debug_array[denali->idx++] =
1066 0x10000000 | irq_status;
ce082596
JR		 1067 denali->idx %= 32;
1068
bf1806dd 1069 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
ce082596
JR		 1070#endif
1071 /* handle interrupt */
1072 /* first acknowledge it */
1073 clear_interrupt(denali, irq_status);
1074 /* store the status in the device context for someone
1075 to read */
1076 denali->irq_status |= irq_status;
1077 /* notify anyone who cares that it happened */
1078 complete(&denali->complete);
1079 /* tell the OS that we've handled this */
1080 result = IRQ_HANDLED;
1081 }
1082 }
1083 spin_unlock(&denali->irq_lock);
1084 return result;
1085}
1086#define BANK(x) ((x) << 24)
1087
1088static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1089{
1090 unsigned long comp_res = 0;
1091 uint32_t intr_status = 0;
1092 bool retry = false;
1093 unsigned long timeout = msecs_to_jiffies(1000);
1094
345b1d3b 1095 do {
ce082596 1096#if DEBUG_DENALI
bf1806dd 1097 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
ce082596 1098#endif
bdca6dae
CD		 1099 comp_res =
1100 wait_for_completion_timeout(&denali->complete, timeout);
ce082596
JR		 1101 spin_lock_irq(&denali->irq_lock);
1102 intr_status = denali->irq_status;
1103
1104#if DEBUG_DENALI
bdca6dae
CD		 1105 denali->irq_debug_array[denali->idx++] =
1106 0x20000000 | (irq_mask << 16) | intr_status;
ce082596
JR		 1107 denali->idx %= 32;
1108#endif
1109
345b1d3b 1110 if (intr_status & irq_mask) {
ce082596
JR		 1111 denali->irq_status &= ~irq_mask;
1112 spin_unlock_irq(&denali->irq_lock);
1113#if DEBUG_DENALI
bdca6dae
CD		 1114 if (retry)
1115 printk(KERN_INFO "status on retry = 0x%x\n",
1116 intr_status);
ce082596
JR		 1117#endif
1118 /* our interrupt was detected */
1119 break;
345b1d3b 1120 } else {
5bac3acf
C		 1121 /* these are not the interrupts you are looking for -
1122 * need to wait again */
ce082596
JR		 1123 spin_unlock_irq(&denali->irq_lock);
1124#if DEBUG_DENALI
1125 print_irq_log(denali);
bdca6dae
CD		 1126 printk(KERN_INFO "received irq nobody cared:"
1127 " irq_status = 0x%x, irq_mask = 0x%x,"
1128 " timeout = %ld\n", intr_status,
1129 irq_mask, comp_res);
ce082596
JR		 1130#endif
1131 retry = true;
1132 }
1133 } while (comp_res != 0);
1134
345b1d3b 1135 if (comp_res == 0) {
ce082596 1136 /* timeout */
5bac3acf
C		 1137 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
1138 intr_status, irq_mask);
ce082596
JR		 1139
1140 intr_status = 0;
1141 }
1142 return intr_status;
1143}
1144
5bac3acf 1145/* This helper function setups the registers for ECC and whether or not
ce082596 1146 the spare area will be transfered. */
5bac3acf 1147static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
ce082596
JR		 1148 bool transfer_spare)
1149{
5bac3acf 1150 int ecc_en_flag = 0, transfer_spare_flag = 0;
ce082596
JR		 1151
1152 /* set ECC, transfer spare bits if needed */
1153 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
1154 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
1155
1156 /* Enable spare area/ECC per user's request. */
1157 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
bdca6dae
CD		 1158 denali_write32(transfer_spare_flag,
1159 denali->flash_reg + TRANSFER_SPARE_REG);
ce082596
JR		 1160}
1161
5bac3acf
C		 1162/* sends a pipeline command operation to the controller. See the Denali NAND
1163 controller's user guide for more information (section 4.2.3.6).
ce082596 1164 */
bdca6dae
CD		 1165static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
1166 bool ecc_en,
1167 bool transfer_spare,
1168 int access_type,
1169 int op)
ce082596
JR		 1170{
1171 int status = PASS;
5bac3acf 1172 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
ce082596
JR		 1173 irq_mask = 0;
1174
a99d1796
CD		 1175 if (op == DENALI_READ)
1176 irq_mask = INTR_STATUS0__LOAD_COMP;
1177 else if (op == DENALI_WRITE)
1178 irq_mask = 0;
1179 else
1180 BUG();
ce082596
JR		 1181
1182 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
1183
1184#if DEBUG_DENALI
1185 spin_lock_irq(&denali->irq_lock);
bdca6dae
CD		 1186 denali->irq_debug_array[denali->idx++] =
1187 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
1188 (access_type << 4);
ce082596
JR		 1189 denali->idx %= 32;
1190 spin_unlock_irq(&denali->irq_lock);
1191#endif
1192
1193
1194 /* clear interrupts */
5bac3acf 1195 clear_interrupts(denali);
ce082596
JR		 1196
1197 addr = BANK(denali->flash_bank) | denali->page;
1198
345b1d3b 1199 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
5bac3acf 1200 cmd = MODE_01 | addr;
ce082596 1201 denali_write32(cmd, denali->flash_mem);
345b1d3b 1202 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
ce082596 1203 /* read spare area */
5bac3acf 1204 cmd = MODE_10 | addr;
ce082596
JR		 1205 index_addr(denali, (uint32_t)cmd, access_type);
1206
5bac3acf 1207 cmd = MODE_01 | addr;
ce082596 1208 denali_write32(cmd, denali->flash_mem);
345b1d3b 1209 } else if (op == DENALI_READ) {
ce082596 1210 /* setup page read request for access type */
5bac3acf 1211 cmd = MODE_10 | addr;
ce082596
JR		 1212 index_addr(denali, (uint32_t)cmd, access_type);
1213
1214 /* page 33 of the NAND controller spec indicates we should not
5bac3acf 1215 use the pipeline commands in Spare area only mode. So we
ce082596
JR		 1216 don't.
1217 */
345b1d3b 1218 if (access_type == SPARE_ACCESS) {
ce082596
JR		 1219 cmd = MODE_01 | addr;
1220 denali_write32(cmd, denali->flash_mem);
345b1d3b 1221 } else {
bdca6dae
CD		 1222 index_addr(denali, (uint32_t)cmd,
1223 0x2000 | op | page_count);
5bac3acf
C		 1224
1225 /* wait for command to be accepted
bdca6dae
CD		 1226 * can always use status0 bit as the
1227 * mask is identical for each
ce082596
JR		 1228 * bank. */
1229 irq_status = wait_for_irq(denali, irq_mask);
1230
345b1d3b 1231 if (irq_status == 0) {
ce082596 1232 printk(KERN_ERR "cmd, page, addr on timeout "
bdca6dae
CD		 1233 "(0x%x, 0x%x, 0x%x)\n", cmd,
1234 denali->page, addr);
ce082596 1235 status = FAIL;
345b1d3b 1236 } else {
ce082596
JR		 1237 cmd = MODE_01 | addr;
1238 denali_write32(cmd, denali->flash_mem);
1239 }
1240 }
1241 }
1242 return status;
1243}
1244
1245/* helper function that simply writes a buffer to the flash */
bdca6dae
CD		 1246static int write_data_to_flash_mem(struct denali_nand_info *denali,
1247 const uint8_t *buf,
1248 int len)
ce082596
JR		 1249{
1250 uint32_t i = 0, *buf32;
1251
5bac3acf
C		 1252 /* verify that the len is a multiple of 4. see comment in
1253 * read_data_from_flash_mem() */
ce082596
JR		 1254 BUG_ON((len % 4) != 0);
1255
1256 /* write the data to the flash memory */
1257 buf32 = (uint32_t *)buf;
1258 for (i = 0; i < len / 4; i++)
ce082596 1259 denali_write32(*buf32++, denali->flash_mem + 0x10);
5bac3acf 1260 return i*4; /* intent is to return the number of bytes read */
ce082596
JR		 1261}
1262
1263/* helper function that simply reads a buffer from the flash */
bdca6dae
CD		 1264static int read_data_from_flash_mem(struct denali_nand_info *denali,
1265 uint8_t *buf,
1266 int len)
ce082596
JR		 1267{
1268 uint32_t i = 0, *buf32;
1269
1270 /* we assume that len will be a multiple of 4, if not
1271 * it would be nice to know about it ASAP rather than
5bac3acf
C		 1272 * have random failures...
1273 * This assumption is based on the fact that this
1274 * function is designed to be used to read flash pages,
ce082596
JR		 1275 * which are typically multiples of 4...
1276 */
1277
1278 BUG_ON((len % 4) != 0);
1279
1280 /* transfer the data from the flash */
1281 buf32 = (uint32_t *)buf;
1282 for (i = 0; i < len / 4; i++)
ce082596 1283 *buf32++ = ioread32(denali->flash_mem + 0x10);
5bac3acf 1284 return i*4; /* intent is to return the number of bytes read */
ce082596
JR		 1285}
1286
1287/* writes OOB data to the device */
1288static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1289{
1290 struct denali_nand_info *denali = mtd_to_denali(mtd);
1291 uint32_t irq_status = 0;
5bac3acf 1292 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
ce082596
JR		 1293 INTR_STATUS0__PROGRAM_FAIL;
1294 int status = 0;
1295
1296 denali->page = page;
1297
5bac3acf 1298 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
345b1d3b 1299 DENALI_WRITE) == PASS) {
ce082596
JR		 1300 write_data_to_flash_mem(denali, buf, mtd->oobsize);
1301
1302#if DEBUG_DENALI
1303 spin_lock_irq(&denali->irq_lock);
bdca6dae
CD		 1304 denali->irq_debug_array[denali->idx++] =
1305 0x80000000 | mtd->oobsize;
ce082596
JR		 1306 denali->idx %= 32;
1307 spin_unlock_irq(&denali->irq_lock);
1308#endif
1309
5bac3acf 1310
ce082596
JR		 1311 /* wait for operation to complete */
1312 irq_status = wait_for_irq(denali, irq_mask);
1313
345b1d3b 1314 if (irq_status == 0) {
ce082596
JR		 1315 printk(KERN_ERR "OOB write failed\n");
1316 status = -EIO;
1317 }
345b1d3b 1318 } else {
ce082596 1319 printk(KERN_ERR "unable to send pipeline command\n");
5bac3acf 1320 status = -EIO;
ce082596
JR		 1321 }
1322 return status;
1323}
1324
1325/* reads OOB data from the device */
1326static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1327{
1328 struct denali_nand_info *denali = mtd_to_denali(mtd);
bdca6dae
CD		 1329 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
1330 irq_status = 0, addr = 0x0, cmd = 0x0;
ce082596
JR		 1331
1332 denali->page = page;
1333
1334#if DEBUG_DENALI
bf1806dd 1335 printk(KERN_INFO "read_oob %d\n", page);
ce082596 1336#endif
5bac3acf 1337 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
345b1d3b 1338 DENALI_READ) == PASS) {
5bac3acf 1339 read_data_from_flash_mem(denali, buf, mtd->oobsize);
ce082596 1340
5bac3acf 1341 /* wait for command to be accepted
ce082596
JR		 1342 * can always use status0 bit as the mask is identical for each
1343 * bank. */
1344 irq_status = wait_for_irq(denali, irq_mask);
1345
1346 if (irq_status == 0)
bdca6dae
CD		 1347 printk(KERN_ERR "page on OOB timeout %d\n",
1348 denali->page);
ce082596
JR		 1349
1350 /* We set the device back to MAIN_ACCESS here as I observed
1351 * instability with the controller if you do a block erase
1352 * and the last transaction was a SPARE_ACCESS. Block erase
1353 * is reliable (according to the MTD test infrastructure)
5bac3acf 1354 * if you are in MAIN_ACCESS.
ce082596
JR		 1355 */
1356 addr = BANK(denali->flash_bank) | denali->page;
5bac3acf 1357 cmd = MODE_10 | addr;
ce082596
JR		 1358 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
1359
1360#if DEBUG_DENALI
1361 spin_lock_irq(&denali->irq_lock);
bdca6dae
CD		 1362 denali->irq_debug_array[denali->idx++] =
1363 0x60000000 | mtd->oobsize;
ce082596
JR		 1364 denali->idx %= 32;
1365 spin_unlock_irq(&denali->irq_lock);
1366#endif
1367 }
1368}
1369
5bac3acf 1370/* this function examines buffers to see if they contain data that
ce082596
JR		 1371 * indicate that the buffer is part of an erased region of flash.
1372 */
1373bool is_erased(uint8_t *buf, int len)
1374{
1375 int i = 0;
1376 for (i = 0; i < len; i++)
ce082596 1377 if (buf[i] != 0xFF)
ce082596 1378 return false;
ce082596
JR		 1379 return true;
1380}
1381#define ECC_SECTOR_SIZE 512
1382
1383#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
1384#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
1385#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
1386#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO))
1387#define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1388#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1389
5bac3acf 1390static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
ce082596
JR		 1391 uint8_t *oobbuf, uint32_t irq_status)
1392{
1393 bool check_erased_page = false;
1394
345b1d3b 1395 if (irq_status & INTR_STATUS0__ECC_ERR) {
ce082596
JR		 1396 /* read the ECC errors. we'll ignore them for now */
1397 uint32_t err_address = 0, err_correction_info = 0;
1398 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1399 uint32_t err_correction_value = 0;
1400
345b1d3b 1401 do {
5bac3acf 1402 err_address = ioread32(denali->flash_reg +
ce082596
JR		 1403 ECC_ERROR_ADDRESS);
1404 err_sector = ECC_SECTOR(err_address);
1405 err_byte = ECC_BYTE(err_address);
1406
1407
5bac3acf 1408 err_correction_info = ioread32(denali->flash_reg +
ce082596 1409 ERR_CORRECTION_INFO);
5bac3acf 1410 err_correction_value =
ce082596
JR		 1411 ECC_CORRECTION_VALUE(err_correction_info);
1412 err_device = ECC_ERR_DEVICE(err_correction_info);
1413
345b1d3b 1414 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
ce082596 1415 /* offset in our buffer is computed as:
5bac3acf 1416 sector number * sector size + offset in
ce082596
JR		 1417 sector
1418 */
5bac3acf 1419 int offset = err_sector * ECC_SECTOR_SIZE +
ce082596 1420 err_byte;
345b1d3b 1421 if (offset < denali->mtd.writesize) {
ce082596
JR		 1422 /* correct the ECC error */
1423 buf[offset] ^= err_correction_value;
1424 denali->mtd.ecc_stats.corrected++;
345b1d3b 1425 } else {
ce082596
JR		 1426 /* bummer, couldn't correct the error */
1427 printk(KERN_ERR "ECC offset invalid\n");
1428 denali->mtd.ecc_stats.failed++;
1429 }
345b1d3b 1430 } else {
5bac3acf 1431 /* if the error is not correctable, need to
bdca6dae
CD		 1432 * look at the page to see if it is an erased
1433 * page. if so, then it's not a real ECC error
1434 * */
ce082596
JR		 1435 check_erased_page = true;
1436 }
1437
5bac3acf 1438#if DEBUG_DENALI
bdca6dae
CD		 1439 printk(KERN_INFO "Detected ECC error in page %d:"
1440 " err_addr = 0x%08x, info to fix is"
1441 " 0x%08x\n", denali->page, err_address,
1442 err_correction_info);
ce082596
JR		 1443#endif
1444 } while (!ECC_LAST_ERR(err_correction_info));
1445 }
1446 return check_erased_page;
1447}
1448
1449/* programs the controller to either enable/disable DMA transfers */
aadff49c 1450static void denali_enable_dma(struct denali_nand_info *denali, bool en)
ce082596
JR		 1451{
1452 uint32_t reg_val = 0x0;
1453
a99d1796
CD		 1454 if (en)
1455 reg_val = DMA_ENABLE__FLAG;
ce082596
JR		 1456
1457 denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
1458 ioread32(denali->flash_reg + DMA_ENABLE);
1459}
1460
1461/* setups the HW to perform the data DMA */
aadff49c 1462static void denali_setup_dma(struct denali_nand_info *denali, int op)
ce082596
JR		 1463{
1464 uint32_t mode = 0x0;
1465 const int page_count = 1;
1466 dma_addr_t addr = denali->buf.dma_buf;
1467
1468 mode = MODE_10 | BANK(denali->flash_bank);
1469
1470 /* DMA is a four step process */
1471
1472 /* 1. setup transfer type and # of pages */
1473 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1474
1475 /* 2. set memory high address bits 23:8 */
1476 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1477
1478 /* 3. set memory low address bits 23:8 */
1479 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1480
1481 /* 4. interrupt when complete, burst len = 64 bytes*/
1482 index_addr(denali, mode | 0x14000, 0x2400);
1483}
1484
5bac3acf 1485/* writes a page. user specifies type, and this function handles the
ce082596 1486 configuration details. */
5bac3acf 1487static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
ce082596
JR		 1488 const uint8_t *buf, bool raw_xfer)
1489{
1490 struct denali_nand_info *denali = mtd_to_denali(mtd);
1491 struct pci_dev *pci_dev = denali->dev;
1492
1493 dma_addr_t addr = denali->buf.dma_buf;
1494 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1495
1496 uint32_t irq_status = 0;
5bac3acf 1497 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
ce082596
JR		 1498 INTR_STATUS0__PROGRAM_FAIL;
1499
1500 /* if it is a raw xfer, we want to disable ecc, and send
1501 * the spare area.
1502 * !raw_xfer - enable ecc
1503 * raw_xfer - transfer spare
1504 */
1505 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1506
1507 /* copy buffer into DMA buffer */
1508 memcpy(denali->buf.buf, buf, mtd->writesize);
1509
345b1d3b 1510 if (raw_xfer) {
ce082596 1511 /* transfer the data to the spare area */
5bac3acf
C		 1512 memcpy(denali->buf.buf + mtd->writesize,
1513 chip->oob_poi,
1514 mtd->oobsize);
ce082596
JR		 1515 }
1516
1517 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1518
1519 clear_interrupts(denali);
5bac3acf 1520 denali_enable_dma(denali, true);
ce082596 1521
aadff49c 1522 denali_setup_dma(denali, DENALI_WRITE);
ce082596
JR		 1523
1524 /* wait for operation to complete */
1525 irq_status = wait_for_irq(denali, irq_mask);
1526
345b1d3b 1527 if (irq_status == 0) {
bdca6dae
CD		 1528 printk(KERN_ERR "timeout on write_page"
1529 " (type = %d)\n", raw_xfer);
5bac3acf 1530 denali->status =
bdca6dae
CD		 1531 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1532 NAND_STATUS_FAIL : PASS;
ce082596
JR		 1533 }
1534
5bac3acf 1535 denali_enable_dma(denali, false);
ce082596
JR		 1536 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1537}
1538
1539/* NAND core entry points */
1540
5bac3acf
C		 1541/* this is the callback that the NAND core calls to write a page. Since
1542 writing a page with ECC or without is similar, all the work is done
ce082596 1543 by write_page above. */
5bac3acf 1544static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
ce082596
JR		 1545 const uint8_t *buf)
1546{
1547 /* for regular page writes, we let HW handle all the ECC
5bac3acf 1548 * data written to the device. */
ce082596
JR		 1549 write_page(mtd, chip, buf, false);
1550}
1551
5bac3acf 1552/* This is the callback that the NAND core calls to write a page without ECC.
ce082596 1553 raw access is similiar to ECC page writes, so all the work is done in the
5bac3acf 1554 write_page() function above.
ce082596 1555 */
5bac3acf 1556static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
ce082596
JR		 1557 const uint8_t *buf)
1558{
5bac3acf 1559 /* for raw page writes, we want to disable ECC and simply write
ce082596
JR		 1560 whatever data is in the buffer. */
1561 write_page(mtd, chip, buf, true);
1562}
1563
5bac3acf 1564static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
ce082596
JR		 1565 int page)
1566{
5bac3acf 1567 return write_oob_data(mtd, chip->oob_poi, page);
ce082596
JR		 1568}
1569
5bac3acf 1570static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
ce082596
JR		 1571 int page, int sndcmd)
1572{
1573 read_oob_data(mtd, chip->oob_poi, page);
1574
5bac3acf
C		 1575 return 0; /* notify NAND core to send command to
1576 NAND device. */
ce082596
JR		 1577}
1578
1579static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1580 uint8_t *buf, int page)
1581{
1582 struct denali_nand_info *denali = mtd_to_denali(mtd);
1583 struct pci_dev *pci_dev = denali->dev;
1584
1585 dma_addr_t addr = denali->buf.dma_buf;
1586 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1587
1588 uint32_t irq_status = 0;
5bac3acf 1589 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
ce082596
JR		 1590 INTR_STATUS0__ECC_ERR;
1591 bool check_erased_page = false;
1592
1593 setup_ecc_for_xfer(denali, true, false);
1594
aadff49c 1595 denali_enable_dma(denali, true);
ce082596
JR		 1596 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1597
1598 clear_interrupts(denali);
aadff49c 1599 denali_setup_dma(denali, DENALI_READ);
ce082596
JR		 1600
1601 /* wait for operation to complete */
1602 irq_status = wait_for_irq(denali, irq_mask);
1603
1604 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1605
1606 memcpy(buf, denali->buf.buf, mtd->writesize);
5bac3acf 1607
ce082596 1608 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
aadff49c 1609 denali_enable_dma(denali, false);
ce082596 1610
345b1d3b 1611 if (check_erased_page) {
ce082596
JR		 1612 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1613
1614 /* check ECC failures that may have occurred on erased pages */
345b1d3b 1615 if (check_erased_page) {
ce082596 1616 if (!is_erased(buf, denali->mtd.writesize))
ce082596 1617 denali->mtd.ecc_stats.failed++;
ce082596 1618 if (!is_erased(buf, denali->mtd.oobsize))
ce082596 1619 denali->mtd.ecc_stats.failed++;
5bac3acf 1620 }
ce082596
JR		 1621 }
1622 return 0;
1623}
1624
1625static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1626 uint8_t *buf, int page)
1627{
1628 struct denali_nand_info *denali = mtd_to_denali(mtd);
1629 struct pci_dev *pci_dev = denali->dev;
1630
1631 dma_addr_t addr = denali->buf.dma_buf;
1632 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1633
1634 uint32_t irq_status = 0;
1635 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
5bac3acf 1636
ce082596 1637 setup_ecc_for_xfer(denali, false, true);
aadff49c 1638 denali_enable_dma(denali, true);
ce082596
JR		 1639
1640 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1641
1642 clear_interrupts(denali);
aadff49c 1643 denali_setup_dma(denali, DENALI_READ);
ce082596
JR		 1644
1645 /* wait for operation to complete */
1646 irq_status = wait_for_irq(denali, irq_mask);
1647
1648 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1649
aadff49c 1650 denali_enable_dma(denali, false);
ce082596
JR		 1651
1652 memcpy(buf, denali->buf.buf, mtd->writesize);
1653 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1654
1655 return 0;
1656}
1657
1658static uint8_t denali_read_byte(struct mtd_info *mtd)
1659{
1660 struct denali_nand_info *denali = mtd_to_denali(mtd);
1661 uint8_t result = 0xff;
1662
1663 if (denali->buf.head < denali->buf.tail)
ce082596 1664 result = denali->buf.buf[denali->buf.head++];
ce082596
JR		 1665
1666#if DEBUG_DENALI
bf1806dd 1667 printk(KERN_INFO "read byte -> 0x%02x\n", result);
ce082596
JR		 1668#endif
1669 return result;
1670}
1671
1672static void denali_select_chip(struct mtd_info *mtd, int chip)
1673{
1674 struct denali_nand_info *denali = mtd_to_denali(mtd);
1675#if DEBUG_DENALI
bf1806dd 1676 printk(KERN_INFO "denali select chip %d\n", chip);
ce082596
JR		 1677#endif
1678 spin_lock_irq(&denali->irq_lock);
1679 denali->flash_bank = chip;
1680 spin_unlock_irq(&denali->irq_lock);
1681}
1682
1683static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1684{
1685 struct denali_nand_info *denali = mtd_to_denali(mtd);
1686 int status = denali->status;
1687 denali->status = 0;
1688
1689#if DEBUG_DENALI
bf1806dd 1690 printk(KERN_INFO "waitfunc %d\n", status);
ce082596
JR		 1691#endif
1692 return status;
1693}
1694
1695static void denali_erase(struct mtd_info *mtd, int page)
1696{
1697 struct denali_nand_info *denali = mtd_to_denali(mtd);
1698
1699 uint32_t cmd = 0x0, irq_status = 0;
1700
1701#if DEBUG_DENALI
bf1806dd 1702 printk(KERN_INFO "erase page: %d\n", page);
ce082596
JR		 1703#endif
1704 /* clear interrupts */
5bac3acf 1705 clear_interrupts(denali);
ce082596
JR		 1706
1707 /* setup page read request for access type */
1708 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1709 index_addr(denali, (uint32_t)cmd, 0x1);
1710
1711 /* wait for erase to complete or failure to occur */
5bac3acf 1712 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
ce082596
JR		 1713 INTR_STATUS0__ERASE_FAIL);
1714
bdca6dae
CD		 1715 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1716 NAND_STATUS_FAIL : PASS;
ce082596
JR		 1717}
1718
5bac3acf 1719static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
ce082596
JR		 1720 int page)
1721{
1722 struct denali_nand_info *denali = mtd_to_denali(mtd);
1723
1724#if DEBUG_DENALI
bf1806dd 1725 printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
ce082596 1726#endif
345b1d3b 1727 switch (cmd) {
a99d1796
CD		 1728 case NAND_CMD_PAGEPROG:
1729 break;
1730 case NAND_CMD_STATUS:
1731 read_status(denali);
1732 break;
1733 case NAND_CMD_READID:
1734 reset_buf(denali);
1735 if (denali->flash_bank < denali->total_used_banks) {
1736 /* write manufacturer information into nand
1737 buffer for NAND subsystem to fetch.
1738 */
1739 write_byte_to_buf(denali,
1740 denali->dev_info.wDeviceMaker);
1741 write_byte_to_buf(denali,
1742 denali->dev_info.wDeviceID);
1743 write_byte_to_buf(denali,
1744 denali->dev_info.bDeviceParam0);
1745 write_byte_to_buf(denali,
1746 denali->dev_info.bDeviceParam1);
1747 write_byte_to_buf(denali,
1748 denali->dev_info.bDeviceParam2);
1749 } else {
1750 int i;
1751 for (i = 0; i < 5; i++)
1752 write_byte_to_buf(denali, 0xff);
1753 }
1754 break;
1755 case NAND_CMD_READ0:
1756 case NAND_CMD_SEQIN:
1757 denali->page = page;
1758 break;
1759 case NAND_CMD_RESET:
1760 reset_bank(denali);
1761 break;
1762 case NAND_CMD_READOOB:
1763 /* TODO: Read OOB data */
1764 break;
1765 default:
1766 printk(KERN_ERR ": unsupported command"
1767 " received 0x%x\n", cmd);
1768 break;
ce082596
JR		 1769 }
1770}
1771
1772/* stubs for ECC functions not used by the NAND core */
5bac3acf 1773static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
ce082596
JR		 1774 uint8_t *ecc_code)
1775{
1776 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
1777 BUG();
1778 return -EIO;
1779}
1780
5bac3acf 1781static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
ce082596
JR		 1782 uint8_t *read_ecc, uint8_t *calc_ecc)
1783{
1784 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
1785 BUG();
1786 return -EIO;
1787}
1788
1789static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1790{
1791 printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
1792 BUG();
1793}
1794/* end NAND core entry points */
1795
1796/* Initialization code to bring the device up to a known good state */
1797static void denali_hw_init(struct denali_nand_info *denali)
1798{
1799 denali_irq_init(denali);
eda936ef 1800 denali_nand_reset(denali);
ce082596 1801 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
bdca6dae
CD		 1802 denali_write32(CHIP_EN_DONT_CARE__FLAG,
1803 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
ce082596
JR		 1804
1805 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1806 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1807
1808 /* Should set value for these registers when init */
1809 denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1810 denali_write32(1, denali->flash_reg + ECC_ENABLE);
1811}
1812
1813/* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */
a99d1796 1814#define ECC_BYTES_SLC (4 * (2048 / ECC_SECTOR_SIZE))
ce082596
JR		 1815static struct nand_ecclayout nand_oob_slc = {
1816 .eccbytes = 4,
1817 .eccpos = { 0, 1, 2, 3 }, /* not used */
345b1d3b
CD		 1818 .oobfree = {
1819 {
5bac3acf
C		 1820 .offset = ECC_BYTES_SLC,
1821 .length = 64 - ECC_BYTES_SLC
345b1d3b
CD		 1822 }
1823 }
ce082596
JR		 1824};
1825
a99d1796 1826#define ECC_BYTES_MLC (14 * (2048 / ECC_SECTOR_SIZE))
ce082596
JR		 1827static struct nand_ecclayout nand_oob_mlc_14bit = {
1828 .eccbytes = 14,
1829 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
345b1d3b
CD		 1830 .oobfree = {
1831 {
5bac3acf
C		 1832 .offset = ECC_BYTES_MLC,
1833 .length = 64 - ECC_BYTES_MLC
345b1d3b
CD		 1834 }
1835 }
ce082596
JR		 1836};
1837
1838static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1839static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1840
1841static struct nand_bbt_descr bbt_main_descr = {
1842 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1843 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1844 .offs = 8,
1845 .len = 4,
1846 .veroffs = 12,
1847 .maxblocks = 4,
1848 .pattern = bbt_pattern,
1849};
1850
1851static struct nand_bbt_descr bbt_mirror_descr = {
1852 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1853 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1854 .offs = 8,
1855 .len = 4,
1856 .veroffs = 12,
1857 .maxblocks = 4,
1858 .pattern = mirror_pattern,
1859};
1860
1861/* initalize driver data structures */
1862void denali_drv_init(struct denali_nand_info *denali)
1863{
1864 denali->idx = 0;
1865
1866 /* setup interrupt handler */
5bac3acf 1867 /* the completion object will be used to notify
ce082596
JR		 1868 * the callee that the interrupt is done */
1869 init_completion(&denali->complete);
1870
1871 /* the spinlock will be used to synchronize the ISR
5bac3acf 1872 * with any element that might be access shared
ce082596
JR		 1873 * data (interrupt status) */
1874 spin_lock_init(&denali->irq_lock);
1875
1876 /* indicate that MTD has not selected a valid bank yet */
1877 denali->flash_bank = CHIP_SELECT_INVALID;
1878
1879 /* initialize our irq_status variable to indicate no interrupts */
1880 denali->irq_status = 0;
1881}
1882
1883/* driver entry point */
1884static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1885{
1886 int ret = -ENODEV;
1887 resource_size_t csr_base, mem_base;
1888 unsigned long csr_len, mem_len;
1889 struct denali_nand_info *denali;
1890
1891 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
1892 __FILE__, __LINE__, __func__);
1893
1894 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1895 if (!denali)
1896 return -ENOMEM;
1897
1898 ret = pci_enable_device(dev);
1899 if (ret) {
1900 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1901 goto failed_enable;
1902 }
1903
1904 if (id->driver_data == INTEL_CE4100) {
5bac3acf
C		 1905 /* Due to a silicon limitation, we can only support
1906 * ONFI timing mode 1 and below.
1907 */
345b1d3b 1908 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
bdca6dae
CD		 1909 printk(KERN_ERR "Intel CE4100 only supports"
1910 " ONFI timing mode 1 or below\n");
ce082596
JR		 1911 ret = -EINVAL;
1912 goto failed_enable;
1913 }
1914 denali->platform = INTEL_CE4100;
1915 mem_base = pci_resource_start(dev, 0);
1916 mem_len = pci_resource_len(dev, 1);
1917 csr_base = pci_resource_start(dev, 1);
1918 csr_len = pci_resource_len(dev, 1);
1919 } else {
1920 denali->platform = INTEL_MRST;
1921 csr_base = pci_resource_start(dev, 0);
1922 csr_len = pci_resource_start(dev, 0);
1923 mem_base = pci_resource_start(dev, 1);
1924 mem_len = pci_resource_len(dev, 1);
1925 if (!mem_len) {
1926 mem_base = csr_base + csr_len;
1927 mem_len = csr_len;
1928 nand_dbg_print(NAND_DBG_WARN,
bdca6dae
CD		 1929 "Spectra: No second"
1930 " BAR for PCI device;"
1931 " assuming %08Lx\n",
ce082596
JR		 1932 (uint64_t)csr_base);
1933 }
1934 }
1935
1936 /* Is 32-bit DMA supported? */
1937 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1938
345b1d3b 1939 if (ret) {
ce082596
JR		 1940 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1941 goto failed_enable;
1942 }
bdca6dae
CD		 1943 denali->buf.dma_buf =
1944 pci_map_single(dev, denali->buf.buf,
1945 DENALI_BUF_SIZE,
1946 PCI_DMA_BIDIRECTIONAL);
ce082596 1947
345b1d3b 1948 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
ce082596
JR		 1949 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1950 goto failed_enable;
1951 }
1952
1953 pci_set_master(dev);
1954 denali->dev = dev;
1955
1956 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1957 if (ret) {
1958 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1959 goto failed_req_csr;
1960 }
1961
1962 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1963 if (!denali->flash_reg) {
1964 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1965 ret = -ENOMEM;
1966 goto failed_remap_csr;
1967 }
1968 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
1969 (uint64_t)csr_base, denali->flash_reg, csr_len);
1970
1971 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1972 if (!denali->flash_mem) {
1973 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1974 iounmap(denali->flash_reg);
1975 ret = -ENOMEM;
1976 goto failed_remap_csr;
1977 }
1978
1979 nand_dbg_print(NAND_DBG_WARN,
1980 "Spectra: Remapped flash base address: "
1981 "0x%p, len: %ld\n",
1982 denali->flash_mem, csr_len);
1983
1984 denali_hw_init(denali);
1985 denali_drv_init(denali);
1986
1987 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
1988 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1989 DENALI_NAND_NAME, denali)) {
1990 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1991 ret = -ENODEV;
1992 goto failed_request_irq;
1993 }
1994
1995 /* now that our ISR is registered, we can enable interrupts */
eda936ef 1996 denali_set_intr_modes(denali, true);
ce082596
JR		 1997
1998 pci_set_drvdata(dev, denali);
1999
eda936ef 2000 denali_nand_timing_set(denali);
ce082596 2001
5bac3acf
C		 2002 /* MTD supported page sizes vary by kernel. We validate our
2003 * kernel supports the device here.
ce082596 2004 */
345b1d3b 2005 if (denali->dev_info.wPageSize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
ce082596
JR		 2006 ret = -ENODEV;
2007 printk(KERN_ERR "Spectra: device size not supported by this "
2008 "version of MTD.");
2009 goto failed_nand;
2010 }
2011
2012 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
2013 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
2014 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
2015 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
2016 ioread32(denali->flash_reg + ACC_CLKS),
2017 ioread32(denali->flash_reg + RE_2_WE),
2018 ioread32(denali->flash_reg + WE_2_RE),
2019 ioread32(denali->flash_reg + ADDR_2_DATA),
2020 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
2021 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
2022 ioread32(denali->flash_reg + CS_SETUP_CNT));
2023
2024 denali->mtd.name = "Denali NAND";
2025 denali->mtd.owner = THIS_MODULE;
2026 denali->mtd.priv = &denali->nand;
2027
2028 /* register the driver with the NAND core subsystem */
2029 denali->nand.select_chip = denali_select_chip;
2030 denali->nand.cmdfunc = denali_cmdfunc;
2031 denali->nand.read_byte = denali_read_byte;
2032 denali->nand.waitfunc = denali_waitfunc;
2033
5bac3acf 2034 /* scan for NAND devices attached to the controller
ce082596 2035 * this is the first stage in a two step process to register
5bac3acf 2036 * with the nand subsystem */
345b1d3b 2037 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
ce082596
JR		 2038 ret = -ENXIO;
2039 goto failed_nand;
2040 }
5bac3acf
C		 2041
2042 /* second stage of the NAND scan
2043 * this stage requires information regarding ECC and
2044 * bad block management. */
ce082596
JR		 2045
2046 /* Bad block management */
2047 denali->nand.bbt_td = &bbt_main_descr;
2048 denali->nand.bbt_md = &bbt_mirror_descr;
2049
2050 /* skip the scan for now until we have OOB read and write support */
2051 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
2052 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
2053
345b1d3b 2054 if (denali->dev_info.MLCDevice) {
ce082596
JR		 2055 denali->nand.ecc.layout = &nand_oob_mlc_14bit;
2056 denali->nand.ecc.bytes = ECC_BYTES_MLC;
345b1d3b 2057 } else {/* SLC */
ce082596
JR		 2058 denali->nand.ecc.layout = &nand_oob_slc;
2059 denali->nand.ecc.bytes = ECC_BYTES_SLC;
2060 }
2061
5bac3acf
C		 2062 /* These functions are required by the NAND core framework, otherwise,
2063 * the NAND core will assert. However, we don't need them, so we'll stub
2064 * them out. */
ce082596
JR		 2065 denali->nand.ecc.calculate = denali_ecc_calculate;
2066 denali->nand.ecc.correct = denali_ecc_correct;
2067 denali->nand.ecc.hwctl = denali_ecc_hwctl;
2068
2069 /* override the default read operations */
2070 denali->nand.ecc.size = denali->mtd.writesize;
2071 denali->nand.ecc.read_page = denali_read_page;
2072 denali->nand.ecc.read_page_raw = denali_read_page_raw;
2073 denali->nand.ecc.write_page = denali_write_page;
2074 denali->nand.ecc.write_page_raw = denali_write_page_raw;
2075 denali->nand.ecc.read_oob = denali_read_oob;
2076 denali->nand.ecc.write_oob = denali_write_oob;
2077 denali->nand.erase_cmd = denali_erase;
2078
345b1d3b 2079 if (nand_scan_tail(&denali->mtd)) {
ce082596
JR		 2080 ret = -ENXIO;
2081 goto failed_nand;
2082 }
2083
2084 ret = add_mtd_device(&denali->mtd);
2085 if (ret) {
bdca6dae
CD		 2086 printk(KERN_ERR "Spectra: Failed to register"
2087 " MTD device: %d\n", ret);
ce082596
JR		 2088 goto failed_nand;
2089 }
2090 return 0;
2091
2092 failed_nand:
2093 denali_irq_cleanup(dev->irq, denali);
2094 failed_request_irq:
2095 iounmap(denali->flash_reg);
2096 iounmap(denali->flash_mem);
2097 failed_remap_csr:
2098 pci_release_regions(dev);
2099 failed_req_csr:
5bac3acf 2100 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
ce082596
JR		 2101 PCI_DMA_BIDIRECTIONAL);
2102 failed_enable:
2103 kfree(denali);
2104 return ret;
2105}
2106
2107/* driver exit point */
2108static void denali_pci_remove(struct pci_dev *dev)
2109{
2110 struct denali_nand_info *denali = pci_get_drvdata(dev);
2111
2112 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
2113 __FILE__, __LINE__, __func__);
2114
2115 nand_release(&denali->mtd);
2116 del_mtd_device(&denali->mtd);
2117
2118 denali_irq_cleanup(dev->irq, denali);
2119
2120 iounmap(denali->flash_reg);
2121 iounmap(denali->flash_mem);
2122 pci_release_regions(dev);
2123 pci_disable_device(dev);
5bac3acf 2124 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
ce082596
JR		 2125 PCI_DMA_BIDIRECTIONAL);
2126 pci_set_drvdata(dev, NULL);
2127 kfree(denali);
2128}
2129
2130MODULE_DEVICE_TABLE(pci, denali_pci_ids);
2131
2132static struct pci_driver denali_pci_driver = {
2133 .name = DENALI_NAND_NAME,
2134 .id_table = denali_pci_ids,
2135 .probe = denali_pci_probe,
2136 .remove = denali_pci_remove,
2137};
2138
2139static int __devinit denali_init(void)
2140{
bdca6dae
CD		 2141 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
2142 __DATE__, __TIME__);
ce082596
JR		 2143 return pci_register_driver(&denali_pci_driver);
2144}
2145
2146/* Free memory */
2147static void __devexit denali_exit(void)
2148{
2149 pci_unregister_driver(&denali_pci_driver);
2150}
2151
2152module_init(denali_init);
2153module_exit(denali_exit);
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