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ff4569c7 DB |
1 | /* |
2 | * davinci_nand.c - NAND Flash Driver for DaVinci family chips | |
3 | * | |
4 | * Copyright © 2006 Texas Instruments. | |
5 | * | |
6 | * Port to 2.6.23 Copyright © 2008 by: | |
7 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> | |
8 | * Troy Kisky <troy.kisky@boundarydevices.com> | |
9 | * Dirk Behme <Dirk.Behme@gmail.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/err.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/mtd/nand.h> | |
34 | #include <linux/mtd/partitions.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
ff4569c7 | 36 | |
ff4569c7 | 37 | #include <mach/nand.h> |
8060ef4d | 38 | #include <mach/aemif.h> |
ff4569c7 DB |
39 | |
40 | #include <asm/mach-types.h> | |
41 | ||
42 | ||
ff4569c7 DB |
43 | /* |
44 | * This is a device driver for the NAND flash controller found on the | |
45 | * various DaVinci family chips. It handles up to four SoC chipselects, | |
46 | * and some flavors of secondary chipselect (e.g. based on A12) as used | |
47 | * with multichip packages. | |
48 | * | |
6a4123e5 | 49 | * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC |
ff4569c7 DB |
50 | * available on chips like the DM355 and OMAP-L137 and needed with the |
51 | * more error-prone MLC NAND chips. | |
52 | * | |
53 | * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY | |
54 | * outputs in a "wire-AND" configuration, with no per-chip signals. | |
55 | */ | |
56 | struct davinci_nand_info { | |
57 | struct mtd_info mtd; | |
58 | struct nand_chip chip; | |
6a4123e5 | 59 | struct nand_ecclayout ecclayout; |
ff4569c7 DB |
60 | |
61 | struct device *dev; | |
62 | struct clk *clk; | |
63 | bool partitioned; | |
64 | ||
6a4123e5 DB |
65 | bool is_readmode; |
66 | ||
ff4569c7 DB |
67 | void __iomem *base; |
68 | void __iomem *vaddr; | |
69 | ||
70 | uint32_t ioaddr; | |
71 | uint32_t current_cs; | |
72 | ||
73 | uint32_t mask_chipsel; | |
74 | uint32_t mask_ale; | |
75 | uint32_t mask_cle; | |
76 | ||
77 | uint32_t core_chipsel; | |
a88dbc5b SN |
78 | |
79 | struct davinci_aemif_timing *timing; | |
ff4569c7 DB |
80 | }; |
81 | ||
82 | static DEFINE_SPINLOCK(davinci_nand_lock); | |
6a4123e5 | 83 | static bool ecc4_busy; |
ff4569c7 DB |
84 | |
85 | #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd) | |
86 | ||
87 | ||
88 | static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info, | |
89 | int offset) | |
90 | { | |
91 | return __raw_readl(info->base + offset); | |
92 | } | |
93 | ||
94 | static inline void davinci_nand_writel(struct davinci_nand_info *info, | |
95 | int offset, unsigned long value) | |
96 | { | |
97 | __raw_writel(value, info->base + offset); | |
98 | } | |
99 | ||
100 | /*----------------------------------------------------------------------*/ | |
101 | ||
102 | /* | |
103 | * Access to hardware control lines: ALE, CLE, secondary chipselect. | |
104 | */ | |
105 | ||
106 | static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, | |
107 | unsigned int ctrl) | |
108 | { | |
109 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
110 | uint32_t addr = info->current_cs; | |
111 | struct nand_chip *nand = mtd->priv; | |
112 | ||
113 | /* Did the control lines change? */ | |
114 | if (ctrl & NAND_CTRL_CHANGE) { | |
115 | if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE) | |
116 | addr |= info->mask_cle; | |
117 | else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE) | |
118 | addr |= info->mask_ale; | |
119 | ||
120 | nand->IO_ADDR_W = (void __iomem __force *)addr; | |
121 | } | |
122 | ||
123 | if (cmd != NAND_CMD_NONE) | |
124 | iowrite8(cmd, nand->IO_ADDR_W); | |
125 | } | |
126 | ||
127 | static void nand_davinci_select_chip(struct mtd_info *mtd, int chip) | |
128 | { | |
129 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
130 | uint32_t addr = info->ioaddr; | |
131 | ||
132 | /* maybe kick in a second chipselect */ | |
133 | if (chip > 0) | |
134 | addr |= info->mask_chipsel; | |
135 | info->current_cs = addr; | |
136 | ||
137 | info->chip.IO_ADDR_W = (void __iomem __force *)addr; | |
138 | info->chip.IO_ADDR_R = info->chip.IO_ADDR_W; | |
139 | } | |
140 | ||
141 | /*----------------------------------------------------------------------*/ | |
142 | ||
143 | /* | |
144 | * 1-bit hardware ECC ... context maintained for each core chipselect | |
145 | */ | |
146 | ||
147 | static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd) | |
148 | { | |
149 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
150 | ||
151 | return davinci_nand_readl(info, NANDF1ECC_OFFSET | |
152 | + 4 * info->core_chipsel); | |
153 | } | |
154 | ||
155 | static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode) | |
156 | { | |
157 | struct davinci_nand_info *info; | |
158 | uint32_t nandcfr; | |
159 | unsigned long flags; | |
160 | ||
161 | info = to_davinci_nand(mtd); | |
162 | ||
163 | /* Reset ECC hardware */ | |
164 | nand_davinci_readecc_1bit(mtd); | |
165 | ||
166 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
167 | ||
168 | /* Restart ECC hardware */ | |
169 | nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET); | |
170 | nandcfr |= BIT(8 + info->core_chipsel); | |
171 | davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr); | |
172 | ||
173 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
174 | } | |
175 | ||
176 | /* | |
177 | * Read hardware ECC value and pack into three bytes | |
178 | */ | |
179 | static int nand_davinci_calculate_1bit(struct mtd_info *mtd, | |
180 | const u_char *dat, u_char *ecc_code) | |
181 | { | |
182 | unsigned int ecc_val = nand_davinci_readecc_1bit(mtd); | |
183 | unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4); | |
184 | ||
185 | /* invert so that erased block ecc is correct */ | |
186 | ecc24 = ~ecc24; | |
187 | ecc_code[0] = (u_char)(ecc24); | |
188 | ecc_code[1] = (u_char)(ecc24 >> 8); | |
189 | ecc_code[2] = (u_char)(ecc24 >> 16); | |
190 | ||
191 | return 0; | |
192 | } | |
193 | ||
194 | static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat, | |
195 | u_char *read_ecc, u_char *calc_ecc) | |
196 | { | |
197 | struct nand_chip *chip = mtd->priv; | |
198 | uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) | | |
199 | (read_ecc[2] << 16); | |
200 | uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) | | |
201 | (calc_ecc[2] << 16); | |
202 | uint32_t diff = eccCalc ^ eccNand; | |
203 | ||
204 | if (diff) { | |
205 | if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { | |
206 | /* Correctable error */ | |
207 | if ((diff >> (12 + 3)) < chip->ecc.size) { | |
208 | dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7); | |
209 | return 1; | |
210 | } else { | |
211 | return -1; | |
212 | } | |
213 | } else if (!(diff & (diff - 1))) { | |
214 | /* Single bit ECC error in the ECC itself, | |
215 | * nothing to fix */ | |
216 | return 1; | |
217 | } else { | |
218 | /* Uncorrectable error */ | |
219 | return -1; | |
220 | } | |
221 | ||
222 | } | |
223 | return 0; | |
224 | } | |
225 | ||
226 | /*----------------------------------------------------------------------*/ | |
227 | ||
6a4123e5 DB |
228 | /* |
229 | * 4-bit hardware ECC ... context maintained over entire AEMIF | |
230 | * | |
231 | * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME | |
232 | * since that forces use of a problematic "infix OOB" layout. | |
233 | * Among other things, it trashes manufacturer bad block markers. | |
234 | * Also, and specific to this hardware, it ECC-protects the "prepad" | |
235 | * in the OOB ... while having ECC protection for parts of OOB would | |
236 | * seem useful, the current MTD stack sometimes wants to update the | |
237 | * OOB without recomputing ECC. | |
238 | */ | |
239 | ||
240 | static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode) | |
241 | { | |
242 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
243 | unsigned long flags; | |
244 | u32 val; | |
245 | ||
246 | spin_lock_irqsave(&davinci_nand_lock, flags); | |
247 | ||
248 | /* Start 4-bit ECC calculation for read/write */ | |
249 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
250 | val &= ~(0x03 << 4); | |
251 | val |= (info->core_chipsel << 4) | BIT(12); | |
252 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
253 | ||
254 | info->is_readmode = (mode == NAND_ECC_READ); | |
255 | ||
256 | spin_unlock_irqrestore(&davinci_nand_lock, flags); | |
257 | } | |
258 | ||
259 | /* Read raw ECC code after writing to NAND. */ | |
260 | static void | |
261 | nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4]) | |
262 | { | |
263 | const u32 mask = 0x03ff03ff; | |
264 | ||
265 | code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask; | |
266 | code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask; | |
267 | code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask; | |
268 | code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask; | |
269 | } | |
270 | ||
271 | /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */ | |
272 | static int nand_davinci_calculate_4bit(struct mtd_info *mtd, | |
273 | const u_char *dat, u_char *ecc_code) | |
274 | { | |
275 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
276 | u32 raw_ecc[4], *p; | |
277 | unsigned i; | |
278 | ||
279 | /* After a read, terminate ECC calculation by a dummy read | |
280 | * of some 4-bit ECC register. ECC covers everything that | |
281 | * was read; correct() just uses the hardware state, so | |
282 | * ecc_code is not needed. | |
283 | */ | |
284 | if (info->is_readmode) { | |
285 | davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET); | |
286 | return 0; | |
287 | } | |
288 | ||
289 | /* Pack eight raw 10-bit ecc values into ten bytes, making | |
290 | * two passes which each convert four values (in upper and | |
291 | * lower halves of two 32-bit words) into five bytes. The | |
292 | * ROM boot loader uses this same packing scheme. | |
293 | */ | |
294 | nand_davinci_readecc_4bit(info, raw_ecc); | |
295 | for (i = 0, p = raw_ecc; i < 2; i++, p += 2) { | |
296 | *ecc_code++ = p[0] & 0xff; | |
297 | *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc); | |
298 | *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0); | |
299 | *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0); | |
300 | *ecc_code++ = (p[1] >> 18) & 0xff; | |
301 | } | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | /* Correct up to 4 bits in data we just read, using state left in the | |
307 | * hardware plus the ecc_code computed when it was first written. | |
308 | */ | |
309 | static int nand_davinci_correct_4bit(struct mtd_info *mtd, | |
310 | u_char *data, u_char *ecc_code, u_char *null) | |
311 | { | |
312 | int i; | |
313 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
314 | unsigned short ecc10[8]; | |
315 | unsigned short *ecc16; | |
316 | u32 syndrome[4]; | |
1c3275b6 | 317 | u32 ecc_state; |
6a4123e5 | 318 | unsigned num_errors, corrected; |
2bdb053a | 319 | unsigned long timeo; |
6a4123e5 DB |
320 | |
321 | /* All bytes 0xff? It's an erased page; ignore its ECC. */ | |
322 | for (i = 0; i < 10; i++) { | |
323 | if (ecc_code[i] != 0xff) | |
324 | goto compare; | |
325 | } | |
326 | return 0; | |
327 | ||
328 | compare: | |
329 | /* Unpack ten bytes into eight 10 bit values. We know we're | |
330 | * little-endian, and use type punning for less shifting/masking. | |
331 | */ | |
332 | if (WARN_ON(0x01 & (unsigned) ecc_code)) | |
333 | return -EINVAL; | |
334 | ecc16 = (unsigned short *)ecc_code; | |
335 | ||
336 | ecc10[0] = (ecc16[0] >> 0) & 0x3ff; | |
337 | ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0); | |
338 | ecc10[2] = (ecc16[1] >> 4) & 0x3ff; | |
339 | ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc); | |
340 | ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300); | |
341 | ecc10[5] = (ecc16[3] >> 2) & 0x3ff; | |
342 | ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0); | |
343 | ecc10[7] = (ecc16[4] >> 6) & 0x3ff; | |
344 | ||
345 | /* Tell ECC controller about the expected ECC codes. */ | |
346 | for (i = 7; i >= 0; i--) | |
347 | davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]); | |
348 | ||
349 | /* Allow time for syndrome calculation ... then read it. | |
350 | * A syndrome of all zeroes 0 means no detected errors. | |
351 | */ | |
352 | davinci_nand_readl(info, NANDFSR_OFFSET); | |
353 | nand_davinci_readecc_4bit(info, syndrome); | |
354 | if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3])) | |
355 | return 0; | |
356 | ||
f12a9473 SN |
357 | /* |
358 | * Clear any previous address calculation by doing a dummy read of an | |
359 | * error address register. | |
360 | */ | |
361 | davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET); | |
362 | ||
6a4123e5 DB |
363 | /* Start address calculation, and wait for it to complete. |
364 | * We _could_ start reading more data while this is working, | |
365 | * to speed up the overall page read. | |
366 | */ | |
367 | davinci_nand_writel(info, NANDFCR_OFFSET, | |
368 | davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13)); | |
1c3275b6 SR |
369 | |
370 | /* | |
371 | * ECC_STATE field reads 0x3 (Error correction complete) immediately | |
372 | * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately | |
373 | * begin trying to poll for the state, you may fall right out of your | |
374 | * loop without any of the correction calculations having taken place. | |
eea116ed WS |
375 | * The recommendation from the hardware team is to initially delay as |
376 | * long as ECC_STATE reads less than 4. After that, ECC HW has entered | |
377 | * correction state. | |
1c3275b6 | 378 | */ |
2bdb053a | 379 | timeo = jiffies + usecs_to_jiffies(100); |
1c3275b6 SR |
380 | do { |
381 | ecc_state = (davinci_nand_readl(info, | |
382 | NANDFSR_OFFSET) >> 8) & 0x0f; | |
383 | cpu_relax(); | |
384 | } while ((ecc_state < 4) && time_before(jiffies, timeo)); | |
385 | ||
6a4123e5 DB |
386 | for (;;) { |
387 | u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET); | |
388 | ||
389 | switch ((fsr >> 8) & 0x0f) { | |
390 | case 0: /* no error, should not happen */ | |
f12a9473 | 391 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
392 | return 0; |
393 | case 1: /* five or more errors detected */ | |
f12a9473 | 394 | davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET); |
6a4123e5 DB |
395 | return -EIO; |
396 | case 2: /* error addresses computed */ | |
397 | case 3: | |
398 | num_errors = 1 + ((fsr >> 16) & 0x03); | |
399 | goto correct; | |
400 | default: /* still working on it */ | |
401 | cpu_relax(); | |
402 | continue; | |
403 | } | |
404 | } | |
405 | ||
406 | correct: | |
407 | /* correct each error */ | |
408 | for (i = 0, corrected = 0; i < num_errors; i++) { | |
409 | int error_address, error_value; | |
410 | ||
411 | if (i > 1) { | |
412 | error_address = davinci_nand_readl(info, | |
413 | NAND_ERR_ADD2_OFFSET); | |
414 | error_value = davinci_nand_readl(info, | |
415 | NAND_ERR_ERRVAL2_OFFSET); | |
416 | } else { | |
417 | error_address = davinci_nand_readl(info, | |
418 | NAND_ERR_ADD1_OFFSET); | |
419 | error_value = davinci_nand_readl(info, | |
420 | NAND_ERR_ERRVAL1_OFFSET); | |
421 | } | |
422 | ||
423 | if (i & 1) { | |
424 | error_address >>= 16; | |
425 | error_value >>= 16; | |
426 | } | |
427 | error_address &= 0x3ff; | |
428 | error_address = (512 + 7) - error_address; | |
429 | ||
430 | if (error_address < 512) { | |
431 | data[error_address] ^= error_value; | |
432 | corrected++; | |
433 | } | |
434 | } | |
435 | ||
436 | return corrected; | |
437 | } | |
438 | ||
439 | /*----------------------------------------------------------------------*/ | |
440 | ||
ff4569c7 DB |
441 | /* |
442 | * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's | |
443 | * how these chips are normally wired. This translates to both 8 and 16 | |
444 | * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4). | |
445 | * | |
446 | * For now we assume that configuration, or any other one which ignores | |
447 | * the two LSBs for NAND access ... so we can issue 32-bit reads/writes | |
448 | * and have that transparently morphed into multiple NAND operations. | |
449 | */ | |
450 | static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
451 | { | |
452 | struct nand_chip *chip = mtd->priv; | |
453 | ||
454 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
455 | ioread32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
456 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
457 | ioread16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
458 | else | |
459 | ioread8_rep(chip->IO_ADDR_R, buf, len); | |
460 | } | |
461 | ||
462 | static void nand_davinci_write_buf(struct mtd_info *mtd, | |
463 | const uint8_t *buf, int len) | |
464 | { | |
465 | struct nand_chip *chip = mtd->priv; | |
466 | ||
467 | if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0) | |
468 | iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2); | |
469 | else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0) | |
470 | iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1); | |
471 | else | |
472 | iowrite8_rep(chip->IO_ADDR_R, buf, len); | |
473 | } | |
474 | ||
475 | /* | |
476 | * Check hardware register for wait status. Returns 1 if device is ready, | |
477 | * 0 if it is still busy. | |
478 | */ | |
479 | static int nand_davinci_dev_ready(struct mtd_info *mtd) | |
480 | { | |
481 | struct davinci_nand_info *info = to_davinci_nand(mtd); | |
482 | ||
483 | return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0); | |
484 | } | |
485 | ||
ff4569c7 DB |
486 | /*----------------------------------------------------------------------*/ |
487 | ||
6a4123e5 DB |
488 | /* An ECC layout for using 4-bit ECC with small-page flash, storing |
489 | * ten ECC bytes plus the manufacturer's bad block marker byte, and | |
490 | * and not overlapping the default BBT markers. | |
491 | */ | |
492 | static struct nand_ecclayout hwecc4_small __initconst = { | |
493 | .eccbytes = 10, | |
494 | .eccpos = { 0, 1, 2, 3, 4, | |
495 | /* offset 5 holds the badblock marker */ | |
496 | 6, 7, | |
497 | 13, 14, 15, }, | |
498 | .oobfree = { | |
499 | {.offset = 8, .length = 5, }, | |
500 | {.offset = 16, }, | |
501 | }, | |
502 | }; | |
503 | ||
f12a9473 SN |
504 | /* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash, |
505 | * storing ten ECC bytes plus the manufacturer's bad block marker byte, | |
506 | * and not overlapping the default BBT markers. | |
507 | */ | |
508 | static struct nand_ecclayout hwecc4_2048 __initconst = { | |
509 | .eccbytes = 40, | |
510 | .eccpos = { | |
511 | /* at the end of spare sector */ | |
512 | 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, | |
513 | 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, | |
514 | 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, | |
515 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, | |
516 | }, | |
517 | .oobfree = { | |
518 | /* 2 bytes at offset 0 hold manufacturer badblock markers */ | |
519 | {.offset = 2, .length = 22, }, | |
520 | /* 5 bytes at offset 8 hold BBT markers */ | |
521 | /* 8 bytes at offset 16 hold JFFS2 clean markers */ | |
522 | }, | |
523 | }; | |
6a4123e5 | 524 | |
ff4569c7 DB |
525 | static int __init nand_davinci_probe(struct platform_device *pdev) |
526 | { | |
527 | struct davinci_nand_pdata *pdata = pdev->dev.platform_data; | |
528 | struct davinci_nand_info *info; | |
529 | struct resource *res1; | |
530 | struct resource *res2; | |
531 | void __iomem *vaddr; | |
532 | void __iomem *base; | |
533 | int ret; | |
534 | uint32_t val; | |
535 | nand_ecc_modes_t ecc_mode; | |
536 | ||
533a0149 DB |
537 | /* insist on board-specific configuration */ |
538 | if (!pdata) | |
539 | return -ENODEV; | |
540 | ||
ff4569c7 DB |
541 | /* which external chipselect will we be managing? */ |
542 | if (pdev->id < 0 || pdev->id > 3) | |
543 | return -ENODEV; | |
544 | ||
545 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
546 | if (!info) { | |
547 | dev_err(&pdev->dev, "unable to allocate memory\n"); | |
548 | ret = -ENOMEM; | |
549 | goto err_nomem; | |
550 | } | |
551 | ||
552 | platform_set_drvdata(pdev, info); | |
553 | ||
554 | res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
555 | res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
556 | if (!res1 || !res2) { | |
557 | dev_err(&pdev->dev, "resource missing\n"); | |
558 | ret = -EINVAL; | |
559 | goto err_nomem; | |
560 | } | |
561 | ||
d8bc5555 HS |
562 | vaddr = ioremap(res1->start, resource_size(res1)); |
563 | base = ioremap(res2->start, resource_size(res2)); | |
ff4569c7 DB |
564 | if (!vaddr || !base) { |
565 | dev_err(&pdev->dev, "ioremap failed\n"); | |
566 | ret = -EINVAL; | |
567 | goto err_ioremap; | |
568 | } | |
569 | ||
570 | info->dev = &pdev->dev; | |
571 | info->base = base; | |
572 | info->vaddr = vaddr; | |
573 | ||
574 | info->mtd.priv = &info->chip; | |
575 | info->mtd.name = dev_name(&pdev->dev); | |
576 | info->mtd.owner = THIS_MODULE; | |
577 | ||
87f39f04 DB |
578 | info->mtd.dev.parent = &pdev->dev; |
579 | ||
ff4569c7 DB |
580 | info->chip.IO_ADDR_R = vaddr; |
581 | info->chip.IO_ADDR_W = vaddr; | |
582 | info->chip.chip_delay = 0; | |
583 | info->chip.select_chip = nand_davinci_select_chip; | |
584 | ||
585 | /* options such as NAND_USE_FLASH_BBT or 16-bit widths */ | |
533a0149 | 586 | info->chip.options = pdata->options; |
f611a79f MG |
587 | info->chip.bbt_td = pdata->bbt_td; |
588 | info->chip.bbt_md = pdata->bbt_md; | |
a88dbc5b | 589 | info->timing = pdata->timing; |
ff4569c7 DB |
590 | |
591 | info->ioaddr = (uint32_t __force) vaddr; | |
592 | ||
593 | info->current_cs = info->ioaddr; | |
594 | info->core_chipsel = pdev->id; | |
595 | info->mask_chipsel = pdata->mask_chipsel; | |
596 | ||
597 | /* use nandboot-capable ALE/CLE masks by default */ | |
5cd0be8e | 598 | info->mask_ale = pdata->mask_ale ? : MASK_ALE; |
533a0149 | 599 | info->mask_cle = pdata->mask_cle ? : MASK_CLE; |
ff4569c7 DB |
600 | |
601 | /* Set address of hardware control function */ | |
602 | info->chip.cmd_ctrl = nand_davinci_hwcontrol; | |
603 | info->chip.dev_ready = nand_davinci_dev_ready; | |
604 | ||
605 | /* Speed up buffer I/O */ | |
606 | info->chip.read_buf = nand_davinci_read_buf; | |
607 | info->chip.write_buf = nand_davinci_write_buf; | |
608 | ||
533a0149 DB |
609 | /* Use board-specific ECC config */ |
610 | ecc_mode = pdata->ecc_mode; | |
ff4569c7 | 611 | |
6a4123e5 | 612 | ret = -EINVAL; |
ff4569c7 DB |
613 | switch (ecc_mode) { |
614 | case NAND_ECC_NONE: | |
615 | case NAND_ECC_SOFT: | |
6a4123e5 | 616 | pdata->ecc_bits = 0; |
ff4569c7 DB |
617 | break; |
618 | case NAND_ECC_HW: | |
6a4123e5 DB |
619 | if (pdata->ecc_bits == 4) { |
620 | /* No sanity checks: CPUs must support this, | |
621 | * and the chips may not use NAND_BUSWIDTH_16. | |
622 | */ | |
623 | ||
624 | /* No sharing 4-bit hardware between chipselects yet */ | |
625 | spin_lock_irq(&davinci_nand_lock); | |
626 | if (ecc4_busy) | |
627 | ret = -EBUSY; | |
628 | else | |
629 | ecc4_busy = true; | |
630 | spin_unlock_irq(&davinci_nand_lock); | |
631 | ||
632 | if (ret == -EBUSY) | |
633 | goto err_ecc; | |
634 | ||
635 | info->chip.ecc.calculate = nand_davinci_calculate_4bit; | |
636 | info->chip.ecc.correct = nand_davinci_correct_4bit; | |
637 | info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; | |
638 | info->chip.ecc.bytes = 10; | |
639 | } else { | |
640 | info->chip.ecc.calculate = nand_davinci_calculate_1bit; | |
641 | info->chip.ecc.correct = nand_davinci_correct_1bit; | |
642 | info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; | |
643 | info->chip.ecc.bytes = 3; | |
644 | } | |
ff4569c7 | 645 | info->chip.ecc.size = 512; |
ff4569c7 | 646 | break; |
ff4569c7 DB |
647 | default: |
648 | ret = -EINVAL; | |
649 | goto err_ecc; | |
650 | } | |
651 | info->chip.ecc.mode = ecc_mode; | |
652 | ||
cd24f8c1 | 653 | info->clk = clk_get(&pdev->dev, "aemif"); |
ff4569c7 DB |
654 | if (IS_ERR(info->clk)) { |
655 | ret = PTR_ERR(info->clk); | |
cd24f8c1 | 656 | dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret); |
ff4569c7 DB |
657 | goto err_clk; |
658 | } | |
659 | ||
660 | ret = clk_enable(info->clk); | |
661 | if (ret < 0) { | |
cd24f8c1 KH |
662 | dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n", |
663 | ret); | |
ff4569c7 DB |
664 | goto err_clk_enable; |
665 | } | |
666 | ||
a88dbc5b SN |
667 | /* |
668 | * Setup Async configuration register in case we did not boot from | |
669 | * NAND and so bootloader did not bother to set it up. | |
ff4569c7 | 670 | */ |
a88dbc5b SN |
671 | val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4); |
672 | ||
673 | /* Extended Wait is not valid and Select Strobe mode is not used */ | |
674 | val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK); | |
675 | if (info->chip.options & NAND_BUSWIDTH_16) | |
676 | val |= 0x1; | |
677 | ||
678 | davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val); | |
679 | ||
680 | ret = davinci_aemif_setup_timing(info->timing, info->base, | |
681 | info->core_chipsel); | |
682 | if (ret < 0) { | |
683 | dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); | |
684 | goto err_timing; | |
685 | } | |
ff4569c7 DB |
686 | |
687 | spin_lock_irq(&davinci_nand_lock); | |
688 | ||
689 | /* put CSxNAND into NAND mode */ | |
690 | val = davinci_nand_readl(info, NANDFCR_OFFSET); | |
691 | val |= BIT(info->core_chipsel); | |
692 | davinci_nand_writel(info, NANDFCR_OFFSET, val); | |
693 | ||
694 | spin_unlock_irq(&davinci_nand_lock); | |
695 | ||
696 | /* Scan to find existence of the device(s) */ | |
5e81e88a | 697 | ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL); |
ff4569c7 DB |
698 | if (ret < 0) { |
699 | dev_dbg(&pdev->dev, "no NAND chip(s) found\n"); | |
700 | goto err_scan; | |
701 | } | |
702 | ||
6a4123e5 DB |
703 | /* Update ECC layout if needed ... for 1-bit HW ECC, the default |
704 | * is OK, but it allocates 6 bytes when only 3 are needed (for | |
705 | * each 512 bytes). For the 4-bit HW ECC, that default is not | |
706 | * usable: 10 bytes are needed, not 6. | |
707 | */ | |
708 | if (pdata->ecc_bits == 4) { | |
709 | int chunks = info->mtd.writesize / 512; | |
710 | ||
711 | if (!chunks || info->mtd.oobsize < 16) { | |
712 | dev_dbg(&pdev->dev, "too small\n"); | |
713 | ret = -EINVAL; | |
714 | goto err_scan; | |
715 | } | |
716 | ||
717 | /* For small page chips, preserve the manufacturer's | |
718 | * badblock marking data ... and make sure a flash BBT | |
719 | * table marker fits in the free bytes. | |
720 | */ | |
721 | if (chunks == 1) { | |
722 | info->ecclayout = hwecc4_small; | |
723 | info->ecclayout.oobfree[1].length = | |
724 | info->mtd.oobsize - 16; | |
725 | goto syndrome_done; | |
726 | } | |
f12a9473 SN |
727 | if (chunks == 4) { |
728 | info->ecclayout = hwecc4_2048; | |
729 | info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST; | |
730 | goto syndrome_done; | |
731 | } | |
6a4123e5 | 732 | |
f12a9473 SN |
733 | /* 4KiB page chips are not yet supported. The eccpos from |
734 | * nand_ecclayout cannot hold 80 bytes and change to eccpos[] | |
735 | * breaks userspace ioctl interface with mtd-utils. Once we | |
736 | * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used | |
737 | * for the 4KiB page chips. | |
cc26c3cd BN |
738 | * |
739 | * TODO: Note that nand_ecclayout has now been expanded and can | |
740 | * hold plenty of OOB entries. | |
6a4123e5 DB |
741 | */ |
742 | dev_warn(&pdev->dev, "no 4-bit ECC support yet " | |
f12a9473 | 743 | "for 4KiB-page NAND\n"); |
6a4123e5 DB |
744 | ret = -EIO; |
745 | goto err_scan; | |
746 | ||
747 | syndrome_done: | |
748 | info->chip.ecc.layout = &info->ecclayout; | |
749 | } | |
750 | ||
751 | ret = nand_scan_tail(&info->mtd); | |
752 | if (ret < 0) | |
753 | goto err_scan; | |
754 | ||
ff4569c7 DB |
755 | if (mtd_has_partitions()) { |
756 | struct mtd_partition *mtd_parts = NULL; | |
757 | int mtd_parts_nb = 0; | |
758 | ||
759 | if (mtd_has_cmdlinepart()) { | |
760 | static const char *probes[] __initconst = | |
761 | { "cmdlinepart", NULL }; | |
762 | ||
ff4569c7 DB |
763 | mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes, |
764 | &mtd_parts, 0); | |
ff4569c7 DB |
765 | } |
766 | ||
533a0149 | 767 | if (mtd_parts_nb <= 0) { |
ff4569c7 DB |
768 | mtd_parts = pdata->parts; |
769 | mtd_parts_nb = pdata->nr_parts; | |
770 | } | |
771 | ||
772 | /* Register any partitions */ | |
773 | if (mtd_parts_nb > 0) { | |
774 | ret = add_mtd_partitions(&info->mtd, | |
775 | mtd_parts, mtd_parts_nb); | |
776 | if (ret == 0) | |
777 | info->partitioned = true; | |
778 | } | |
779 | ||
533a0149 | 780 | } else if (pdata->nr_parts) { |
ff4569c7 DB |
781 | dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n", |
782 | pdata->nr_parts, info->mtd.name); | |
783 | } | |
784 | ||
785 | /* If there's no partition info, just package the whole chip | |
786 | * as a single MTD device. | |
787 | */ | |
788 | if (!info->partitioned) | |
789 | ret = add_mtd_device(&info->mtd) ? -ENODEV : 0; | |
790 | ||
791 | if (ret < 0) | |
792 | goto err_scan; | |
793 | ||
794 | val = davinci_nand_readl(info, NRCSR_OFFSET); | |
795 | dev_info(&pdev->dev, "controller rev. %d.%d\n", | |
796 | (val >> 8) & 0xff, val & 0xff); | |
797 | ||
798 | return 0; | |
799 | ||
800 | err_scan: | |
a88dbc5b | 801 | err_timing: |
ff4569c7 DB |
802 | clk_disable(info->clk); |
803 | ||
804 | err_clk_enable: | |
805 | clk_put(info->clk); | |
806 | ||
6a4123e5 DB |
807 | spin_lock_irq(&davinci_nand_lock); |
808 | if (ecc_mode == NAND_ECC_HW_SYNDROME) | |
809 | ecc4_busy = false; | |
810 | spin_unlock_irq(&davinci_nand_lock); | |
811 | ||
ff4569c7 DB |
812 | err_ecc: |
813 | err_clk: | |
814 | err_ioremap: | |
815 | if (base) | |
816 | iounmap(base); | |
817 | if (vaddr) | |
818 | iounmap(vaddr); | |
819 | ||
820 | err_nomem: | |
821 | kfree(info); | |
822 | return ret; | |
823 | } | |
824 | ||
825 | static int __exit nand_davinci_remove(struct platform_device *pdev) | |
826 | { | |
827 | struct davinci_nand_info *info = platform_get_drvdata(pdev); | |
828 | int status; | |
829 | ||
830 | if (mtd_has_partitions() && info->partitioned) | |
831 | status = del_mtd_partitions(&info->mtd); | |
832 | else | |
833 | status = del_mtd_device(&info->mtd); | |
834 | ||
6a4123e5 DB |
835 | spin_lock_irq(&davinci_nand_lock); |
836 | if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) | |
837 | ecc4_busy = false; | |
838 | spin_unlock_irq(&davinci_nand_lock); | |
839 | ||
ff4569c7 DB |
840 | iounmap(info->base); |
841 | iounmap(info->vaddr); | |
842 | ||
843 | nand_release(&info->mtd); | |
844 | ||
845 | clk_disable(info->clk); | |
846 | clk_put(info->clk); | |
847 | ||
848 | kfree(info); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | static struct platform_driver nand_davinci_driver = { | |
854 | .remove = __exit_p(nand_davinci_remove), | |
855 | .driver = { | |
856 | .name = "davinci_nand", | |
857 | }, | |
858 | }; | |
859 | MODULE_ALIAS("platform:davinci_nand"); | |
860 | ||
861 | static int __init nand_davinci_init(void) | |
862 | { | |
863 | return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe); | |
864 | } | |
865 | module_init(nand_davinci_init); | |
866 | ||
867 | static void __exit nand_davinci_exit(void) | |
868 | { | |
869 | platform_driver_unregister(&nand_davinci_driver); | |
870 | } | |
871 | module_exit(nand_davinci_exit); | |
872 | ||
873 | MODULE_LICENSE("GPL"); | |
874 | MODULE_AUTHOR("Texas Instruments"); | |
875 | MODULE_DESCRIPTION("Davinci NAND flash driver"); | |
876 |