]>
Commit | Line | Data |
---|---|---|
5467fb02 | 1 | /* |
fbad5696 | 2 | * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 |
5467fb02 DW |
3 | * |
4 | * Copyright © 2006 Red Hat, Inc. | |
5 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
6 | */ | |
7 | ||
8dd851de | 8 | #define DEBUG |
5467fb02 DW |
9 | |
10 | #include <linux/device.h> | |
11 | #undef DEBUG | |
12 | #include <linux/mtd/mtd.h> | |
13 | #include <linux/mtd/nand.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <asm/io.h> | |
18 | ||
19 | #define CAFE_NAND_CTRL1 0x00 | |
20 | #define CAFE_NAND_CTRL2 0x04 | |
21 | #define CAFE_NAND_CTRL3 0x08 | |
22 | #define CAFE_NAND_STATUS 0x0c | |
23 | #define CAFE_NAND_IRQ 0x10 | |
24 | #define CAFE_NAND_IRQ_MASK 0x14 | |
25 | #define CAFE_NAND_DATA_LEN 0x18 | |
26 | #define CAFE_NAND_ADDR1 0x1c | |
27 | #define CAFE_NAND_ADDR2 0x20 | |
28 | #define CAFE_NAND_TIMING1 0x24 | |
29 | #define CAFE_NAND_TIMING2 0x28 | |
30 | #define CAFE_NAND_TIMING3 0x2c | |
31 | #define CAFE_NAND_NONMEM 0x30 | |
04459d7c | 32 | #define CAFE_NAND_ECC_RESULT 0x3C |
fbad5696 DW |
33 | #define CAFE_NAND_DMA_CTRL 0x40 |
34 | #define CAFE_NAND_DMA_ADDR0 0x44 | |
35 | #define CAFE_NAND_DMA_ADDR1 0x48 | |
04459d7c DW |
36 | #define CAFE_NAND_ECC_SYN01 0x50 |
37 | #define CAFE_NAND_ECC_SYN23 0x54 | |
38 | #define CAFE_NAND_ECC_SYN45 0x58 | |
39 | #define CAFE_NAND_ECC_SYN67 0x5c | |
5467fb02 DW |
40 | #define CAFE_NAND_READ_DATA 0x1000 |
41 | #define CAFE_NAND_WRITE_DATA 0x2000 | |
42 | ||
195a253b DW |
43 | #define CAFE_GLOBAL_CTRL 0x3004 |
44 | #define CAFE_GLOBAL_IRQ 0x3008 | |
45 | #define CAFE_GLOBAL_IRQ_MASK 0x300c | |
46 | #define CAFE_NAND_RESET 0x3034 | |
47 | ||
04459d7c DW |
48 | int cafe_correct_ecc(unsigned char *buf, |
49 | unsigned short *chk_syndrome_list); | |
50 | ||
5467fb02 DW |
51 | struct cafe_priv { |
52 | struct nand_chip nand; | |
53 | struct pci_dev *pdev; | |
54 | void __iomem *mmio; | |
55 | uint32_t ctl1; | |
56 | uint32_t ctl2; | |
57 | int datalen; | |
58 | int nr_data; | |
59 | int data_pos; | |
60 | int page_addr; | |
61 | dma_addr_t dmaaddr; | |
62 | unsigned char *dmabuf; | |
63 | ||
64 | }; | |
65 | ||
b478c775 | 66 | static int usedma = 1; |
5467fb02 DW |
67 | module_param(usedma, int, 0644); |
68 | ||
8dd851de DW |
69 | static int skipbbt = 0; |
70 | module_param(skipbbt, int, 0644); | |
71 | ||
72 | static int debug = 0; | |
73 | module_param(debug, int, 0644); | |
74 | ||
be8444bd DW |
75 | static int regdebug = 0; |
76 | module_param(regdebug, int, 0644); | |
77 | ||
b478c775 | 78 | static int checkecc = 1; |
470b0a90 DW |
79 | module_param(checkecc, int, 0644); |
80 | ||
b478c775 DW |
81 | static int slowtiming = 0; |
82 | module_param(slowtiming, int, 0644); | |
83 | ||
04459d7c | 84 | /* Hrm. Why isn't this already conditional on something in the struct device? */ |
8dd851de DW |
85 | #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) |
86 | ||
195a253b DW |
87 | /* Make it easier to switch to PIO if we need to */ |
88 | #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) | |
89 | #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) | |
8dd851de | 90 | |
5467fb02 DW |
91 | static int cafe_device_ready(struct mtd_info *mtd) |
92 | { | |
93 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
94 | int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000); |
95 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); | |
fbad5696 | 96 | |
195a253b | 97 | cafe_writel(cafe, irqs, NAND_IRQ); |
fbad5696 | 98 | |
8dd851de | 99 | cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", |
195a253b DW |
100 | result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), |
101 | cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
fbad5696 | 102 | |
5467fb02 DW |
103 | return result; |
104 | } | |
105 | ||
106 | ||
107 | static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
108 | { | |
109 | struct cafe_priv *cafe = mtd->priv; | |
110 | ||
111 | if (usedma) | |
112 | memcpy(cafe->dmabuf + cafe->datalen, buf, len); | |
113 | else | |
114 | memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); | |
fbad5696 | 115 | |
5467fb02 DW |
116 | cafe->datalen += len; |
117 | ||
8dd851de | 118 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", |
5467fb02 DW |
119 | len, cafe->datalen); |
120 | } | |
121 | ||
122 | static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
123 | { | |
124 | struct cafe_priv *cafe = mtd->priv; | |
125 | ||
126 | if (usedma) | |
127 | memcpy(buf, cafe->dmabuf + cafe->datalen, len); | |
128 | else | |
129 | memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); | |
130 | ||
8dd851de | 131 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", |
5467fb02 DW |
132 | len, cafe->datalen); |
133 | cafe->datalen += len; | |
134 | } | |
135 | ||
136 | static uint8_t cafe_read_byte(struct mtd_info *mtd) | |
137 | { | |
138 | struct cafe_priv *cafe = mtd->priv; | |
139 | uint8_t d; | |
140 | ||
141 | cafe_read_buf(mtd, &d, 1); | |
8dd851de | 142 | cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); |
5467fb02 DW |
143 | |
144 | return d; | |
145 | } | |
146 | ||
147 | static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
148 | int column, int page_addr) | |
149 | { | |
150 | struct cafe_priv *cafe = mtd->priv; | |
151 | int adrbytes = 0; | |
152 | uint32_t ctl1; | |
153 | uint32_t doneint = 0x80000000; | |
5467fb02 | 154 | |
8dd851de | 155 | cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", |
5467fb02 DW |
156 | command, column, page_addr); |
157 | ||
158 | if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { | |
159 | /* Second half of a command we already calculated */ | |
195a253b | 160 | cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); |
5467fb02 | 161 | ctl1 = cafe->ctl1; |
8dd851de | 162 | cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", |
5467fb02 DW |
163 | cafe->ctl1, cafe->nr_data); |
164 | goto do_command; | |
165 | } | |
166 | /* Reset ECC engine */ | |
195a253b | 167 | cafe_writel(cafe, 0, NAND_CTRL2); |
5467fb02 DW |
168 | |
169 | /* Emulate NAND_CMD_READOOB on large-page chips */ | |
170 | if (mtd->writesize > 512 && | |
171 | command == NAND_CMD_READOOB) { | |
172 | column += mtd->writesize; | |
173 | command = NAND_CMD_READ0; | |
174 | } | |
175 | ||
176 | /* FIXME: Do we need to send read command before sending data | |
177 | for small-page chips, to position the buffer correctly? */ | |
178 | ||
179 | if (column != -1) { | |
195a253b | 180 | cafe_writel(cafe, column, NAND_ADDR1); |
5467fb02 DW |
181 | adrbytes = 2; |
182 | if (page_addr != -1) | |
183 | goto write_adr2; | |
184 | } else if (page_addr != -1) { | |
195a253b | 185 | cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); |
5467fb02 DW |
186 | page_addr >>= 16; |
187 | write_adr2: | |
195a253b | 188 | cafe_writel(cafe, page_addr, NAND_ADDR2); |
5467fb02 DW |
189 | adrbytes += 2; |
190 | if (mtd->size > mtd->writesize << 16) | |
191 | adrbytes++; | |
192 | } | |
193 | ||
194 | cafe->data_pos = cafe->datalen = 0; | |
195 | ||
196 | /* Set command valid bit */ | |
197 | ctl1 = 0x80000000 | command; | |
198 | ||
199 | /* Set RD or WR bits as appropriate */ | |
200 | if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { | |
201 | ctl1 |= (1<<26); /* rd */ | |
202 | /* Always 5 bytes, for now */ | |
8dd851de | 203 | cafe->datalen = 4; |
5467fb02 DW |
204 | /* And one address cycle -- even for STATUS, since the controller doesn't work without */ |
205 | adrbytes = 1; | |
206 | } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || | |
207 | command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { | |
208 | ctl1 |= 1<<26; /* rd */ | |
209 | /* For now, assume just read to end of page */ | |
210 | cafe->datalen = mtd->writesize + mtd->oobsize - column; | |
211 | } else if (command == NAND_CMD_SEQIN) | |
212 | ctl1 |= 1<<25; /* wr */ | |
213 | ||
214 | /* Set number of address bytes */ | |
215 | if (adrbytes) | |
216 | ctl1 |= ((adrbytes-1)|8) << 27; | |
217 | ||
218 | if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { | |
219 | /* Ignore the first command of a pair; the hardware | |
220 | deals with them both at once, later */ | |
221 | cafe->ctl1 = ctl1; | |
222 | cafe->ctl2 = 0; | |
8dd851de | 223 | cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", |
5467fb02 DW |
224 | cafe->ctl1, cafe->datalen); |
225 | return; | |
226 | } | |
227 | /* RNDOUT and READ0 commands need a following byte */ | |
228 | if (command == NAND_CMD_RNDOUT) | |
195a253b | 229 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); |
5467fb02 | 230 | else if (command == NAND_CMD_READ0 && mtd->writesize > 512) |
195a253b | 231 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); |
5467fb02 DW |
232 | |
233 | do_command: | |
8dd851de | 234 | cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", |
195a253b | 235 | cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); |
fbad5696 | 236 | |
5467fb02 | 237 | /* NB: The datasheet lies -- we really should be subtracting 1 here */ |
195a253b DW |
238 | cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); |
239 | cafe_writel(cafe, 0x90000000, NAND_IRQ); | |
5467fb02 DW |
240 | if (usedma && (ctl1 & (3<<25))) { |
241 | uint32_t dmactl = 0xc0000000 + cafe->datalen; | |
242 | /* If WR or RD bits set, set up DMA */ | |
243 | if (ctl1 & (1<<26)) { | |
244 | /* It's a read */ | |
245 | dmactl |= (1<<29); | |
246 | /* ... so it's done when the DMA is done, not just | |
247 | the command. */ | |
248 | doneint = 0x10000000; | |
249 | } | |
195a253b | 250 | cafe_writel(cafe, dmactl, NAND_DMA_CTRL); |
5467fb02 | 251 | } |
5467fb02 DW |
252 | cafe->datalen = 0; |
253 | ||
be8444bd DW |
254 | if (unlikely(regdebug)) { |
255 | int i; | |
256 | printk("About to write command %08x to register 0\n", ctl1); | |
257 | for (i=4; i< 0x5c; i+=4) | |
258 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
fbad5696 | 259 | } |
be8444bd | 260 | |
195a253b | 261 | cafe_writel(cafe, ctl1, NAND_CTRL1); |
5467fb02 DW |
262 | /* Apply this short delay always to ensure that we do wait tWB in |
263 | * any case on any machine. */ | |
264 | ndelay(100); | |
265 | ||
266 | if (1) { | |
8dd851de | 267 | int c = 500000; |
5467fb02 DW |
268 | uint32_t irqs; |
269 | ||
270 | while (c--) { | |
195a253b | 271 | irqs = cafe_readl(cafe, NAND_IRQ); |
5467fb02 DW |
272 | if (irqs & doneint) |
273 | break; | |
274 | udelay(1); | |
8dd851de DW |
275 | if (!(c % 100000)) |
276 | cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); | |
5467fb02 DW |
277 | cpu_relax(); |
278 | } | |
195a253b | 279 | cafe_writel(cafe, doneint, NAND_IRQ); |
a020727b | 280 | cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", |
195a253b | 281 | command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
282 | } |
283 | ||
284 | ||
285 | cafe->ctl2 &= ~(1<<8); | |
286 | cafe->ctl2 &= ~(1<<30); | |
287 | ||
288 | switch (command) { | |
289 | ||
290 | case NAND_CMD_CACHEDPROG: | |
291 | case NAND_CMD_PAGEPROG: | |
292 | case NAND_CMD_ERASE1: | |
293 | case NAND_CMD_ERASE2: | |
294 | case NAND_CMD_SEQIN: | |
295 | case NAND_CMD_RNDIN: | |
296 | case NAND_CMD_STATUS: | |
297 | case NAND_CMD_DEPLETE1: | |
298 | case NAND_CMD_RNDOUT: | |
299 | case NAND_CMD_STATUS_ERROR: | |
300 | case NAND_CMD_STATUS_ERROR0: | |
301 | case NAND_CMD_STATUS_ERROR1: | |
302 | case NAND_CMD_STATUS_ERROR2: | |
303 | case NAND_CMD_STATUS_ERROR3: | |
195a253b | 304 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
305 | return; |
306 | } | |
307 | nand_wait_ready(mtd); | |
195a253b | 308 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
309 | } |
310 | ||
311 | static void cafe_select_chip(struct mtd_info *mtd, int chipnr) | |
312 | { | |
313 | //struct cafe_priv *cafe = mtd->priv; | |
8dd851de | 314 | // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); |
5467fb02 | 315 | } |
fbad5696 | 316 | |
5467fb02 DW |
317 | static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs) |
318 | { | |
319 | struct mtd_info *mtd = id; | |
320 | struct cafe_priv *cafe = mtd->priv; | |
195a253b DW |
321 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
322 | cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); | |
5467fb02 DW |
323 | if (!irqs) |
324 | return IRQ_NONE; | |
325 | ||
195a253b | 326 | cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
327 | return IRQ_HANDLED; |
328 | } | |
329 | ||
330 | static void cafe_nand_bug(struct mtd_info *mtd) | |
331 | { | |
332 | BUG(); | |
333 | } | |
334 | ||
335 | static int cafe_nand_write_oob(struct mtd_info *mtd, | |
336 | struct nand_chip *chip, int page) | |
337 | { | |
338 | int status = 0; | |
339 | ||
5467fb02 DW |
340 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); |
341 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
342 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
343 | status = chip->waitfunc(mtd, chip); | |
344 | ||
345 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
346 | } | |
347 | ||
348 | /* Don't use -- use nand_read_oob_std for now */ | |
349 | static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
350 | int page, int sndcmd) | |
351 | { | |
352 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
353 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
354 | return 1; | |
355 | } | |
356 | /** | |
357 | * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
358 | * @mtd: mtd info structure | |
359 | * @chip: nand chip info structure | |
360 | * @buf: buffer to store read data | |
361 | * | |
362 | * The hw generator calculates the error syndrome automatically. Therefor | |
363 | * we need a special oob layout and handling. | |
364 | */ | |
365 | static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
366 | uint8_t *buf) | |
367 | { | |
368 | struct cafe_priv *cafe = mtd->priv; | |
369 | ||
fbad5696 | 370 | cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", |
195a253b DW |
371 | cafe_readl(cafe, NAND_ECC_RESULT), |
372 | cafe_readl(cafe, NAND_ECC_SYN01)); | |
5467fb02 DW |
373 | |
374 | chip->read_buf(mtd, buf, mtd->writesize); | |
375 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
376 | ||
195a253b | 377 | if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { |
04459d7c DW |
378 | unsigned short syn[8]; |
379 | int i; | |
380 | ||
381 | for (i=0; i<8; i+=2) { | |
195a253b | 382 | uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); |
04459d7c DW |
383 | syn[i] = tmp & 0xfff; |
384 | syn[i+1] = (tmp >> 16) & 0xfff; | |
385 | } | |
386 | ||
63a14237 | 387 | if ((i = cafe_correct_ecc(buf, syn)) < 0) { |
be8444bd DW |
388 | dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", |
389 | cafe_readl(cafe, NAND_ADDR2) * 2048); | |
390 | for (i=0; i< 0x5c; i+=4) | |
391 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
04459d7c DW |
392 | mtd->ecc_stats.failed++; |
393 | } else { | |
394 | dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i); | |
395 | mtd->ecc_stats.corrected += i; | |
396 | } | |
397 | } | |
398 | ||
399 | ||
5467fb02 DW |
400 | return 0; |
401 | } | |
402 | ||
8dd851de DW |
403 | static struct nand_ecclayout cafe_oobinfo_2048 = { |
404 | .eccbytes = 14, | |
405 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
406 | .oobfree = {{14, 50}} | |
407 | }; | |
408 | ||
409 | /* Ick. The BBT code really ought to be able to work this bit out | |
fbad5696 DW |
410 | for itself from the above, at least for the 2KiB case */ |
411 | static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; | |
412 | static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; | |
413 | ||
414 | static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; | |
415 | static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; | |
416 | ||
8dd851de DW |
417 | |
418 | static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { | |
419 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
420 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
421 | .offs = 14, | |
422 | .len = 4, | |
423 | .veroffs = 18, | |
424 | .maxblocks = 4, | |
fbad5696 | 425 | .pattern = cafe_bbt_pattern_2048 |
8dd851de DW |
426 | }; |
427 | ||
428 | static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { | |
429 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
430 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
431 | .offs = 14, | |
432 | .len = 4, | |
433 | .veroffs = 18, | |
434 | .maxblocks = 4, | |
fbad5696 | 435 | .pattern = cafe_mirror_pattern_2048 |
8dd851de DW |
436 | }; |
437 | ||
438 | static struct nand_ecclayout cafe_oobinfo_512 = { | |
439 | .eccbytes = 14, | |
440 | .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, | |
441 | .oobfree = {{14, 2}} | |
442 | }; | |
443 | ||
fbad5696 DW |
444 | static struct nand_bbt_descr cafe_bbt_main_descr_512 = { |
445 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
446 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
447 | .offs = 14, | |
448 | .len = 1, | |
449 | .veroffs = 15, | |
450 | .maxblocks = 4, | |
451 | .pattern = cafe_bbt_pattern_512 | |
452 | }; | |
453 | ||
454 | static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { | |
455 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
456 | | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, | |
457 | .offs = 14, | |
458 | .len = 1, | |
459 | .veroffs = 15, | |
460 | .maxblocks = 4, | |
461 | .pattern = cafe_mirror_pattern_512 | |
462 | }; | |
463 | ||
464 | ||
5467fb02 DW |
465 | static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd, |
466 | struct nand_chip *chip, const uint8_t *buf) | |
467 | { | |
468 | struct cafe_priv *cafe = mtd->priv; | |
469 | ||
5467fb02 | 470 | chip->write_buf(mtd, buf, mtd->writesize); |
8dd851de | 471 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
472 | |
473 | /* Set up ECC autogeneration */ | |
474 | cafe->ctl2 |= (1<<27) | (1<<30); | |
475 | if (mtd->writesize == 2048) | |
476 | cafe->ctl2 |= (1<<29); | |
477 | } | |
478 | ||
479 | static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
480 | const uint8_t *buf, int page, int cached, int raw) | |
481 | { | |
482 | int status; | |
483 | ||
5467fb02 DW |
484 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); |
485 | ||
486 | if (unlikely(raw)) | |
487 | chip->ecc.write_page_raw(mtd, chip, buf); | |
488 | else | |
489 | chip->ecc.write_page(mtd, chip, buf); | |
490 | ||
491 | /* | |
492 | * Cached progamming disabled for now, Not sure if its worth the | |
493 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
494 | */ | |
495 | cached = 0; | |
496 | ||
497 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
498 | ||
499 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
500 | status = chip->waitfunc(mtd, chip); | |
501 | /* | |
502 | * See if operation failed and additional status checks are | |
503 | * available | |
504 | */ | |
505 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
506 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
507 | page); | |
508 | ||
509 | if (status & NAND_STATUS_FAIL) | |
510 | return -EIO; | |
511 | } else { | |
512 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
513 | status = chip->waitfunc(mtd, chip); | |
514 | } | |
515 | ||
516 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
517 | /* Send command to read back the data */ | |
518 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
519 | ||
520 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
521 | return -EIO; | |
522 | #endif | |
523 | return 0; | |
524 | } | |
525 | ||
8dd851de DW |
526 | static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) |
527 | { | |
528 | return 0; | |
529 | } | |
5467fb02 DW |
530 | |
531 | static int __devinit cafe_nand_probe(struct pci_dev *pdev, | |
532 | const struct pci_device_id *ent) | |
533 | { | |
534 | struct mtd_info *mtd; | |
535 | struct cafe_priv *cafe; | |
536 | uint32_t ctrl; | |
537 | int err = 0; | |
538 | ||
539 | err = pci_enable_device(pdev); | |
540 | if (err) | |
541 | return err; | |
542 | ||
543 | pci_set_master(pdev); | |
544 | ||
545 | mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL); | |
546 | if (!mtd) { | |
547 | dev_warn(&pdev->dev, "failed to alloc mtd_info\n"); | |
548 | return -ENOMEM; | |
549 | } | |
550 | cafe = (void *)(&mtd[1]); | |
551 | ||
552 | mtd->priv = cafe; | |
553 | mtd->owner = THIS_MODULE; | |
554 | ||
555 | cafe->pdev = pdev; | |
556 | cafe->mmio = pci_iomap(pdev, 0, 0); | |
557 | if (!cafe->mmio) { | |
558 | dev_warn(&pdev->dev, "failed to iomap\n"); | |
559 | err = -ENOMEM; | |
560 | goto out_free_mtd; | |
561 | } | |
562 | cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers), | |
563 | &cafe->dmaaddr, GFP_KERNEL); | |
564 | if (!cafe->dmabuf) { | |
565 | err = -ENOMEM; | |
566 | goto out_ior; | |
567 | } | |
568 | cafe->nand.buffers = (void *)cafe->dmabuf + 2112; | |
569 | ||
570 | cafe->nand.cmdfunc = cafe_nand_cmdfunc; | |
571 | cafe->nand.dev_ready = cafe_device_ready; | |
572 | cafe->nand.read_byte = cafe_read_byte; | |
573 | cafe->nand.read_buf = cafe_read_buf; | |
574 | cafe->nand.write_buf = cafe_write_buf; | |
575 | cafe->nand.select_chip = cafe_select_chip; | |
576 | ||
577 | cafe->nand.chip_delay = 0; | |
578 | ||
579 | /* Enable the following for a flash based bad block table */ | |
580 | cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS; | |
8dd851de DW |
581 | |
582 | if (skipbbt) { | |
583 | cafe->nand.options |= NAND_SKIP_BBTSCAN; | |
584 | cafe->nand.block_bad = cafe_nand_block_bad; | |
585 | } | |
5467fb02 | 586 | |
dcc41bc8 | 587 | /* Start off by resetting the NAND controller completely */ |
195a253b DW |
588 | cafe_writel(cafe, 1, NAND_RESET); |
589 | cafe_writel(cafe, 0, NAND_RESET); | |
dcc41bc8 | 590 | |
195a253b | 591 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
b478c775 | 592 | |
195a253b | 593 | /* Timings from Marvell's test code (not verified or calculated by us) */ |
b478c775 | 594 | if (!slowtiming) { |
195a253b DW |
595 | cafe_writel(cafe, 0x01010a0a, NAND_TIMING1); |
596 | cafe_writel(cafe, 0x24121212, NAND_TIMING2); | |
597 | cafe_writel(cafe, 0x11000000, NAND_TIMING3); | |
b478c775 | 598 | } else { |
195a253b DW |
599 | cafe_writel(cafe, 0xffffffff, NAND_TIMING1); |
600 | cafe_writel(cafe, 0xffffffff, NAND_TIMING2); | |
601 | cafe_writel(cafe, 0xffffffff, NAND_TIMING3); | |
b478c775 | 602 | } |
195a253b | 603 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
5467fb02 DW |
604 | err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd); |
605 | if (err) { | |
606 | dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); | |
607 | ||
608 | goto out_free_dma; | |
609 | } | |
610 | #if 1 | |
611 | /* Disable master reset, enable NAND clock */ | |
195a253b | 612 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); |
5467fb02 DW |
613 | ctrl &= 0xffffeff0; |
614 | ctrl |= 0x00007000; | |
195a253b DW |
615 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); |
616 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
617 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
5467fb02 | 618 | |
195a253b DW |
619 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); |
620 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
5467fb02 DW |
621 | |
622 | /* Set up DMA address */ | |
195a253b | 623 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); |
5467fb02 | 624 | if (sizeof(cafe->dmaaddr) > 4) |
fbad5696 | 625 | /* Shift in two parts to shut the compiler up */ |
195a253b | 626 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); |
5467fb02 | 627 | else |
195a253b | 628 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); |
fbad5696 | 629 | |
8dd851de | 630 | cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", |
195a253b | 631 | cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); |
5467fb02 DW |
632 | |
633 | /* Enable NAND IRQ in global IRQ mask register */ | |
195a253b | 634 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); |
8dd851de | 635 | cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", |
195a253b | 636 | cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK)); |
5467fb02 DW |
637 | #endif |
638 | #if 1 | |
639 | mtd->writesize=2048; | |
640 | mtd->oobsize = 0x40; | |
8dd851de | 641 | memset(cafe->dmabuf, 0x5a, 2112); |
5467fb02 DW |
642 | cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1); |
643 | cafe->nand.read_byte(mtd); | |
644 | cafe->nand.read_byte(mtd); | |
645 | cafe->nand.read_byte(mtd); | |
646 | cafe->nand.read_byte(mtd); | |
647 | cafe->nand.read_byte(mtd); | |
648 | #endif | |
649 | #if 0 | |
650 | cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0); | |
651 | // nand_wait_ready(mtd); | |
652 | cafe->nand.read_byte(mtd); | |
653 | cafe->nand.read_byte(mtd); | |
654 | cafe->nand.read_byte(mtd); | |
655 | cafe->nand.read_byte(mtd); | |
656 | #endif | |
657 | #if 0 | |
658 | writel(0x84600070, cafe->mmio); | |
659 | udelay(10); | |
195a253b | 660 | cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", cafe_readl(cafe, NAND_NONMEM)); |
5467fb02 DW |
661 | #endif |
662 | /* Scan to find existance of the device */ | |
663 | if (nand_scan_ident(mtd, 1)) { | |
664 | err = -ENXIO; | |
665 | goto out_irq; | |
666 | } | |
667 | ||
668 | cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ | |
669 | if (mtd->writesize == 2048) | |
670 | cafe->ctl2 |= 1<<29; /* 2KiB page size */ | |
671 | ||
672 | /* Set up ECC according to the type of chip we found */ | |
fbad5696 | 673 | if (mtd->writesize == 2048) { |
8dd851de DW |
674 | cafe->nand.ecc.layout = &cafe_oobinfo_2048; |
675 | cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; | |
676 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; | |
fbad5696 DW |
677 | } else if (mtd->writesize == 512) { |
678 | cafe->nand.ecc.layout = &cafe_oobinfo_512; | |
679 | cafe->nand.bbt_td = &cafe_bbt_main_descr_512; | |
680 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; | |
5467fb02 | 681 | } else { |
fbad5696 | 682 | printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n", |
5467fb02 | 683 | mtd->writesize); |
fbad5696 | 684 | goto out_irq; |
5467fb02 | 685 | } |
fbad5696 DW |
686 | cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; |
687 | cafe->nand.ecc.size = mtd->writesize; | |
688 | cafe->nand.ecc.bytes = 14; | |
689 | cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; | |
690 | cafe->nand.ecc.calculate = (void *)cafe_nand_bug; | |
691 | cafe->nand.ecc.correct = (void *)cafe_nand_bug; | |
692 | cafe->nand.write_page = cafe_nand_write_page; | |
693 | cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; | |
694 | cafe->nand.ecc.write_oob = cafe_nand_write_oob; | |
695 | cafe->nand.ecc.read_page = cafe_nand_read_page; | |
696 | cafe->nand.ecc.read_oob = cafe_nand_read_oob; | |
5467fb02 DW |
697 | |
698 | err = nand_scan_tail(mtd); | |
699 | if (err) | |
700 | goto out_irq; | |
701 | ||
5467fb02 DW |
702 | pci_set_drvdata(pdev, mtd); |
703 | add_mtd_device(mtd); | |
704 | goto out; | |
705 | ||
706 | out_irq: | |
707 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 708 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
709 | free_irq(pdev->irq, mtd); |
710 | out_free_dma: | |
711 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
712 | out_ior: | |
713 | pci_iounmap(pdev, cafe->mmio); | |
714 | out_free_mtd: | |
715 | kfree(mtd); | |
716 | out: | |
717 | return err; | |
718 | } | |
719 | ||
720 | static void __devexit cafe_nand_remove(struct pci_dev *pdev) | |
721 | { | |
722 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
723 | struct cafe_priv *cafe = mtd->priv; | |
724 | ||
725 | del_mtd_device(mtd); | |
726 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 727 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 DW |
728 | free_irq(pdev->irq, mtd); |
729 | nand_release(mtd); | |
730 | pci_iounmap(pdev, cafe->mmio); | |
731 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
732 | kfree(mtd); | |
733 | } | |
734 | ||
735 | static struct pci_device_id cafe_nand_tbl[] = { | |
736 | { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 } | |
737 | }; | |
738 | ||
739 | MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); | |
740 | ||
741 | static struct pci_driver cafe_nand_pci_driver = { | |
742 | .name = "CAFÉ NAND", | |
743 | .id_table = cafe_nand_tbl, | |
744 | .probe = cafe_nand_probe, | |
745 | .remove = __devexit_p(cafe_nand_remove), | |
746 | #ifdef CONFIG_PMx | |
747 | .suspend = cafe_nand_suspend, | |
748 | .resume = cafe_nand_resume, | |
749 | #endif | |
750 | }; | |
751 | ||
752 | static int cafe_nand_init(void) | |
753 | { | |
754 | return pci_register_driver(&cafe_nand_pci_driver); | |
755 | } | |
756 | ||
757 | static void cafe_nand_exit(void) | |
758 | { | |
759 | pci_unregister_driver(&cafe_nand_pci_driver); | |
760 | } | |
761 | module_init(cafe_nand_init); | |
762 | module_exit(cafe_nand_exit); | |
763 | ||
764 | MODULE_LICENSE("GPL"); | |
765 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); | |
766 | MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip"); | |
767 | ||
768 | /* Correct ECC for 2048 bytes of 0xff: | |
769 | 41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */ | |
8dd851de DW |
770 | |
771 | /* dwmw2's B-test board, in case of completely screwing it: | |
772 | Bad eraseblock 2394 at 0x12b40000 | |
773 | Bad eraseblock 2627 at 0x14860000 | |
774 | Bad eraseblock 3349 at 0x1a2a0000 | |
775 | */ |