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1 | /* linux/drivers/mtd/nand/bf5xx_nand.c |
2 | * | |
afc4bca6 | 3 | * Copyright 2006-2008 Analog Devices Inc. |
b37bde14 BW |
4 | * http://blackfin.uclinux.org/ |
5 | * Bryan Wu <bryan.wu@analog.com> | |
6 | * | |
8e87d782 | 7 | * Blackfin BF5xx on-chip NAND flash controller driver |
b37bde14 BW |
8 | * |
9 | * Derived from drivers/mtd/nand/s3c2410.c | |
10 | * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk> | |
11 | * | |
12 | * Derived from drivers/mtd/nand/cafe.c | |
13 | * Copyright © 2006 Red Hat, Inc. | |
14 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
15 | * | |
16 | * Changelog: | |
17 | * 12-Jun-2007 Bryan Wu: Initial version | |
18 | * 18-Jul-2007 Bryan Wu: | |
19 | * - ECC_HW and ECC_SW supported | |
20 | * - DMA supported in ECC_HW | |
21 | * - YAFFS tested as rootfs in both ECC_HW and ECC_SW | |
22 | * | |
23 | * TODO: | |
24 | * Enable JFFS2 over NAND as rootfs | |
25 | * | |
26 | * This program is free software; you can redistribute it and/or modify | |
27 | * it under the terms of the GNU General Public License as published by | |
28 | * the Free Software Foundation; either version 2 of the License, or | |
29 | * (at your option) any later version. | |
30 | * | |
31 | * This program is distributed in the hope that it will be useful, | |
32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
33 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
34 | * GNU General Public License for more details. | |
35 | * | |
36 | * You should have received a copy of the GNU General Public License | |
37 | * along with this program; if not, write to the Free Software | |
38 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
39 | */ | |
40 | ||
41 | #include <linux/module.h> | |
42 | #include <linux/types.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/kernel.h> | |
45 | #include <linux/string.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/platform_device.h> | |
48 | #include <linux/delay.h> | |
49 | #include <linux/dma-mapping.h> | |
50 | #include <linux/err.h> | |
51 | #include <linux/slab.h> | |
52 | #include <linux/io.h> | |
53 | #include <linux/bitops.h> | |
54 | ||
55 | #include <linux/mtd/mtd.h> | |
56 | #include <linux/mtd/nand.h> | |
57 | #include <linux/mtd/nand_ecc.h> | |
58 | #include <linux/mtd/partitions.h> | |
59 | ||
60 | #include <asm/blackfin.h> | |
61 | #include <asm/dma.h> | |
62 | #include <asm/cacheflush.h> | |
63 | #include <asm/nand.h> | |
64 | #include <asm/portmux.h> | |
65 | ||
66 | #define DRV_NAME "bf5xx-nand" | |
67 | #define DRV_VERSION "1.2" | |
68 | #define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>" | |
69 | #define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver" | |
70 | ||
71 | #ifdef CONFIG_MTD_NAND_BF5XX_HWECC | |
72 | static int hardware_ecc = 1; | |
73 | #else | |
74 | static int hardware_ecc; | |
75 | #endif | |
76 | ||
afc4bca6 | 77 | static const unsigned short bfin_nfc_pin_req[] = |
a25b7fee MH |
78 | {P_NAND_CE, |
79 | P_NAND_RB, | |
80 | P_NAND_D0, | |
81 | P_NAND_D1, | |
82 | P_NAND_D2, | |
83 | P_NAND_D3, | |
84 | P_NAND_D4, | |
85 | P_NAND_D5, | |
86 | P_NAND_D6, | |
87 | P_NAND_D7, | |
88 | P_NAND_WE, | |
89 | P_NAND_RE, | |
90 | P_NAND_CLE, | |
91 | P_NAND_ALE, | |
92 | 0}; | |
b37bde14 BW |
93 | |
94 | /* | |
95 | * Data structures for bf5xx nand flash controller driver | |
96 | */ | |
97 | ||
98 | /* bf5xx nand info */ | |
99 | struct bf5xx_nand_info { | |
100 | /* mtd info */ | |
101 | struct nand_hw_control controller; | |
102 | struct mtd_info mtd; | |
103 | struct nand_chip chip; | |
104 | ||
105 | /* platform info */ | |
106 | struct bf5xx_nand_platform *platform; | |
107 | ||
108 | /* device info */ | |
109 | struct device *device; | |
110 | ||
111 | /* DMA stuff */ | |
112 | struct completion dma_completion; | |
113 | }; | |
114 | ||
115 | /* | |
116 | * Conversion functions | |
117 | */ | |
118 | static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd) | |
119 | { | |
120 | return container_of(mtd, struct bf5xx_nand_info, mtd); | |
121 | } | |
122 | ||
123 | static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev) | |
124 | { | |
125 | return platform_get_drvdata(pdev); | |
126 | } | |
127 | ||
128 | static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev) | |
129 | { | |
130 | return pdev->dev.platform_data; | |
131 | } | |
132 | ||
133 | /* | |
134 | * struct nand_chip interface function pointers | |
135 | */ | |
136 | ||
137 | /* | |
138 | * bf5xx_nand_hwcontrol | |
139 | * | |
140 | * Issue command and address cycles to the chip | |
141 | */ | |
142 | static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd, | |
143 | unsigned int ctrl) | |
144 | { | |
145 | if (cmd == NAND_CMD_NONE) | |
146 | return; | |
147 | ||
148 | while (bfin_read_NFC_STAT() & WB_FULL) | |
149 | cpu_relax(); | |
150 | ||
151 | if (ctrl & NAND_CLE) | |
152 | bfin_write_NFC_CMD(cmd); | |
153 | else | |
154 | bfin_write_NFC_ADDR(cmd); | |
155 | SSYNC(); | |
156 | } | |
157 | ||
158 | /* | |
159 | * bf5xx_nand_devready() | |
160 | * | |
161 | * returns 0 if the nand is busy, 1 if it is ready | |
162 | */ | |
163 | static int bf5xx_nand_devready(struct mtd_info *mtd) | |
164 | { | |
165 | unsigned short val = bfin_read_NFC_IRQSTAT(); | |
166 | ||
167 | if ((val & NBUSYIRQ) == NBUSYIRQ) | |
168 | return 1; | |
169 | else | |
170 | return 0; | |
171 | } | |
172 | ||
173 | /* | |
174 | * ECC functions | |
175 | * These allow the bf5xx to use the controller's ECC | |
176 | * generator block to ECC the data as it passes through | |
177 | */ | |
178 | ||
179 | /* | |
180 | * ECC error correction function | |
181 | */ | |
182 | static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat, | |
183 | u_char *read_ecc, u_char *calc_ecc) | |
184 | { | |
185 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
186 | u32 syndrome[5]; | |
187 | u32 calced, stored; | |
188 | int i; | |
189 | unsigned short failing_bit, failing_byte; | |
190 | u_char data; | |
191 | ||
192 | calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16); | |
193 | stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16); | |
194 | ||
195 | syndrome[0] = (calced ^ stored); | |
196 | ||
197 | /* | |
198 | * syndrome 0: all zero | |
199 | * No error in data | |
200 | * No action | |
201 | */ | |
202 | if (!syndrome[0] || !calced || !stored) | |
203 | return 0; | |
204 | ||
205 | /* | |
206 | * sysdrome 0: only one bit is one | |
207 | * ECC data was incorrect | |
208 | * No action | |
209 | */ | |
210 | if (hweight32(syndrome[0]) == 1) { | |
211 | dev_err(info->device, "ECC data was incorrect!\n"); | |
212 | return 1; | |
213 | } | |
214 | ||
215 | syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF); | |
216 | syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF); | |
217 | syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF); | |
218 | syndrome[4] = syndrome[2] ^ syndrome[3]; | |
219 | ||
220 | for (i = 0; i < 5; i++) | |
221 | dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]); | |
222 | ||
223 | dev_info(info->device, | |
224 | "calced[0x%08x], stored[0x%08x]\n", | |
225 | calced, stored); | |
226 | ||
227 | /* | |
228 | * sysdrome 0: exactly 11 bits are one, each parity | |
229 | * and parity' pair is 1 & 0 or 0 & 1. | |
230 | * 1-bit correctable error | |
231 | * Correct the error | |
232 | */ | |
233 | if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) { | |
234 | dev_info(info->device, | |
235 | "1-bit correctable error, correct it.\n"); | |
236 | dev_info(info->device, | |
237 | "syndrome[1] 0x%08x\n", syndrome[1]); | |
238 | ||
239 | failing_bit = syndrome[1] & 0x7; | |
240 | failing_byte = syndrome[1] >> 0x3; | |
241 | data = *(dat + failing_byte); | |
242 | data = data ^ (0x1 << failing_bit); | |
243 | *(dat + failing_byte) = data; | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | /* | |
249 | * sysdrome 0: random data | |
250 | * More than 1-bit error, non-correctable error | |
251 | * Discard data, mark bad block | |
252 | */ | |
253 | dev_err(info->device, | |
254 | "More than 1-bit error, non-correctable error.\n"); | |
255 | dev_err(info->device, | |
256 | "Please discard data, mark bad block\n"); | |
257 | ||
258 | return 1; | |
259 | } | |
260 | ||
261 | static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat, | |
262 | u_char *read_ecc, u_char *calc_ecc) | |
263 | { | |
264 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
265 | struct bf5xx_nand_platform *plat = info->platform; | |
266 | unsigned short page_size = (plat->page_size ? 512 : 256); | |
267 | int ret; | |
268 | ||
269 | ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc); | |
270 | ||
271 | /* If page size is 512, correct second 256 bytes */ | |
272 | if (page_size == 512) { | |
273 | dat += 256; | |
274 | read_ecc += 8; | |
275 | calc_ecc += 8; | |
e274f025 | 276 | ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc); |
b37bde14 BW |
277 | } |
278 | ||
279 | return ret; | |
280 | } | |
281 | ||
282 | static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
283 | { | |
284 | return; | |
285 | } | |
286 | ||
287 | static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd, | |
288 | const u_char *dat, u_char *ecc_code) | |
289 | { | |
290 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
291 | struct bf5xx_nand_platform *plat = info->platform; | |
292 | u16 page_size = (plat->page_size ? 512 : 256); | |
293 | u16 ecc0, ecc1; | |
294 | u32 code[2]; | |
295 | u8 *p; | |
b37bde14 BW |
296 | |
297 | /* first 4 bytes ECC code for 256 page size */ | |
298 | ecc0 = bfin_read_NFC_ECC0(); | |
299 | ecc1 = bfin_read_NFC_ECC1(); | |
300 | ||
cf840392 | 301 | code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11); |
b37bde14 BW |
302 | |
303 | dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]); | |
304 | ||
5eb91034 BW |
305 | /* first 3 bytes in ecc_code for 256 page size */ |
306 | p = (u8 *) code; | |
307 | memcpy(ecc_code, p, 3); | |
308 | ||
b37bde14 BW |
309 | /* second 4 bytes ECC code for 512 page size */ |
310 | if (page_size == 512) { | |
311 | ecc0 = bfin_read_NFC_ECC2(); | |
312 | ecc1 = bfin_read_NFC_ECC3(); | |
cf840392 | 313 | code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11); |
5eb91034 BW |
314 | |
315 | /* second 3 bytes in ecc_code for second 256 | |
316 | * bytes of 512 page size | |
317 | */ | |
318 | p = (u8 *) (code + 1); | |
319 | memcpy((ecc_code + 3), p, 3); | |
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320 | dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]); |
321 | } | |
322 | ||
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323 | return 0; |
324 | } | |
325 | ||
326 | /* | |
327 | * PIO mode for buffer writing and reading | |
328 | */ | |
329 | static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
330 | { | |
331 | int i; | |
332 | unsigned short val; | |
333 | ||
334 | /* | |
335 | * Data reads are requested by first writing to NFC_DATA_RD | |
336 | * and then reading back from NFC_READ. | |
337 | */ | |
338 | for (i = 0; i < len; i++) { | |
339 | while (bfin_read_NFC_STAT() & WB_FULL) | |
340 | cpu_relax(); | |
341 | ||
342 | /* Contents do not matter */ | |
343 | bfin_write_NFC_DATA_RD(0x0000); | |
344 | SSYNC(); | |
345 | ||
346 | while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY) | |
347 | cpu_relax(); | |
348 | ||
349 | buf[i] = bfin_read_NFC_READ(); | |
350 | ||
351 | val = bfin_read_NFC_IRQSTAT(); | |
352 | val |= RD_RDY; | |
353 | bfin_write_NFC_IRQSTAT(val); | |
354 | SSYNC(); | |
355 | } | |
356 | } | |
357 | ||
358 | static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd) | |
359 | { | |
360 | uint8_t val; | |
361 | ||
362 | bf5xx_nand_read_buf(mtd, &val, 1); | |
363 | ||
364 | return val; | |
365 | } | |
366 | ||
367 | static void bf5xx_nand_write_buf(struct mtd_info *mtd, | |
368 | const uint8_t *buf, int len) | |
369 | { | |
370 | int i; | |
371 | ||
372 | for (i = 0; i < len; i++) { | |
373 | while (bfin_read_NFC_STAT() & WB_FULL) | |
374 | cpu_relax(); | |
375 | ||
376 | bfin_write_NFC_DATA_WR(buf[i]); | |
377 | SSYNC(); | |
378 | } | |
379 | } | |
380 | ||
381 | static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) | |
382 | { | |
383 | int i; | |
384 | u16 *p = (u16 *) buf; | |
385 | len >>= 1; | |
386 | ||
387 | /* | |
388 | * Data reads are requested by first writing to NFC_DATA_RD | |
389 | * and then reading back from NFC_READ. | |
390 | */ | |
391 | bfin_write_NFC_DATA_RD(0x5555); | |
392 | ||
393 | SSYNC(); | |
394 | ||
395 | for (i = 0; i < len; i++) | |
396 | p[i] = bfin_read_NFC_READ(); | |
397 | } | |
398 | ||
399 | static void bf5xx_nand_write_buf16(struct mtd_info *mtd, | |
400 | const uint8_t *buf, int len) | |
401 | { | |
402 | int i; | |
403 | u16 *p = (u16 *) buf; | |
404 | len >>= 1; | |
405 | ||
406 | for (i = 0; i < len; i++) | |
407 | bfin_write_NFC_DATA_WR(p[i]); | |
408 | ||
409 | SSYNC(); | |
410 | } | |
411 | ||
412 | /* | |
413 | * DMA functions for buffer writing and reading | |
414 | */ | |
415 | static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id) | |
416 | { | |
417 | struct bf5xx_nand_info *info = dev_id; | |
418 | ||
419 | clear_dma_irqstat(CH_NFC); | |
420 | disable_dma(CH_NFC); | |
421 | complete(&info->dma_completion); | |
422 | ||
423 | return IRQ_HANDLED; | |
424 | } | |
425 | ||
426 | static int bf5xx_nand_dma_rw(struct mtd_info *mtd, | |
427 | uint8_t *buf, int is_read) | |
428 | { | |
429 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
430 | struct bf5xx_nand_platform *plat = info->platform; | |
431 | unsigned short page_size = (plat->page_size ? 512 : 256); | |
432 | unsigned short val; | |
433 | ||
434 | dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n", | |
435 | mtd, buf, is_read); | |
436 | ||
437 | /* | |
438 | * Before starting a dma transfer, be sure to invalidate/flush | |
439 | * the cache over the address range of your DMA buffer to | |
440 | * prevent cache coherency problems. Otherwise very subtle bugs | |
441 | * can be introduced to your driver. | |
442 | */ | |
443 | if (is_read) | |
444 | invalidate_dcache_range((unsigned int)buf, | |
445 | (unsigned int)(buf + page_size)); | |
446 | else | |
447 | flush_dcache_range((unsigned int)buf, | |
448 | (unsigned int)(buf + page_size)); | |
449 | ||
450 | /* | |
451 | * This register must be written before each page is | |
452 | * transferred to generate the correct ECC register | |
453 | * values. | |
454 | */ | |
455 | bfin_write_NFC_RST(0x1); | |
456 | SSYNC(); | |
457 | ||
458 | disable_dma(CH_NFC); | |
459 | clear_dma_irqstat(CH_NFC); | |
460 | ||
461 | /* setup DMA register with Blackfin DMA API */ | |
462 | set_dma_config(CH_NFC, 0x0); | |
463 | set_dma_start_addr(CH_NFC, (unsigned long) buf); | |
464 | set_dma_x_count(CH_NFC, (page_size >> 2)); | |
465 | set_dma_x_modify(CH_NFC, 4); | |
466 | ||
467 | /* setup write or read operation */ | |
468 | val = DI_EN | WDSIZE_32; | |
469 | if (is_read) | |
470 | val |= WNR; | |
471 | set_dma_config(CH_NFC, val); | |
472 | enable_dma(CH_NFC); | |
473 | ||
474 | /* Start PAGE read/write operation */ | |
475 | if (is_read) | |
476 | bfin_write_NFC_PGCTL(0x1); | |
477 | else | |
478 | bfin_write_NFC_PGCTL(0x2); | |
479 | wait_for_completion(&info->dma_completion); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd, | |
485 | uint8_t *buf, int len) | |
486 | { | |
487 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
488 | struct bf5xx_nand_platform *plat = info->platform; | |
489 | unsigned short page_size = (plat->page_size ? 512 : 256); | |
490 | ||
491 | dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len); | |
492 | ||
493 | if (len == page_size) | |
494 | bf5xx_nand_dma_rw(mtd, buf, 1); | |
495 | else | |
496 | bf5xx_nand_read_buf(mtd, buf, len); | |
497 | } | |
498 | ||
499 | static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd, | |
500 | const uint8_t *buf, int len) | |
501 | { | |
502 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
503 | struct bf5xx_nand_platform *plat = info->platform; | |
504 | unsigned short page_size = (plat->page_size ? 512 : 256); | |
505 | ||
506 | dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len); | |
507 | ||
508 | if (len == page_size) | |
509 | bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0); | |
510 | else | |
511 | bf5xx_nand_write_buf(mtd, buf, len); | |
512 | } | |
513 | ||
514 | /* | |
515 | * System initialization functions | |
516 | */ | |
517 | ||
518 | static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info) | |
519 | { | |
520 | int ret; | |
521 | unsigned short val; | |
522 | ||
523 | /* Do not use dma */ | |
524 | if (!hardware_ecc) | |
525 | return 0; | |
526 | ||
527 | init_completion(&info->dma_completion); | |
528 | ||
a25b7fee | 529 | #ifdef CONFIG_BF54x |
b37bde14 BW |
530 | /* Setup DMAC1 channel mux for NFC which shared with SDH */ |
531 | val = bfin_read_DMAC1_PERIMUX(); | |
532 | val &= 0xFFFE; | |
533 | bfin_write_DMAC1_PERIMUX(val); | |
534 | SSYNC(); | |
a25b7fee | 535 | #endif |
b37bde14 BW |
536 | /* Request NFC DMA channel */ |
537 | ret = request_dma(CH_NFC, "BF5XX NFC driver"); | |
538 | if (ret < 0) { | |
539 | dev_err(info->device, " unable to get DMA channel\n"); | |
540 | return ret; | |
541 | } | |
542 | ||
543 | set_dma_callback(CH_NFC, (void *) bf5xx_nand_dma_irq, (void *) info); | |
544 | ||
545 | /* Turn off the DMA channel first */ | |
546 | disable_dma(CH_NFC); | |
547 | return 0; | |
548 | } | |
549 | ||
550 | /* | |
551 | * BF5XX NFC hardware initialization | |
552 | * - pin mux setup | |
553 | * - clear interrupt status | |
554 | */ | |
555 | static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info) | |
556 | { | |
557 | int err = 0; | |
558 | unsigned short val; | |
559 | struct bf5xx_nand_platform *plat = info->platform; | |
560 | ||
561 | /* setup NFC_CTL register */ | |
562 | dev_info(info->device, | |
563 | "page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n", | |
564 | (plat->page_size ? 512 : 256), | |
565 | (plat->data_width ? 16 : 8), | |
566 | plat->wr_dly, plat->rd_dly); | |
567 | ||
568 | val = (plat->page_size << NFC_PG_SIZE_OFFSET) | | |
569 | (plat->data_width << NFC_NWIDTH_OFFSET) | | |
570 | (plat->rd_dly << NFC_RDDLY_OFFSET) | | |
571 | (plat->rd_dly << NFC_WRDLY_OFFSET); | |
572 | dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val); | |
573 | ||
574 | bfin_write_NFC_CTL(val); | |
575 | SSYNC(); | |
576 | ||
577 | /* clear interrupt status */ | |
578 | bfin_write_NFC_IRQMASK(0x0); | |
579 | SSYNC(); | |
580 | val = bfin_read_NFC_IRQSTAT(); | |
581 | bfin_write_NFC_IRQSTAT(val); | |
582 | SSYNC(); | |
583 | ||
b37bde14 BW |
584 | /* DMA initialization */ |
585 | if (bf5xx_nand_dma_init(info)) | |
586 | err = -ENXIO; | |
587 | ||
588 | return err; | |
589 | } | |
590 | ||
591 | /* | |
592 | * Device management interface | |
593 | */ | |
594 | static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info) | |
595 | { | |
596 | struct mtd_info *mtd = &info->mtd; | |
597 | ||
598 | #ifdef CONFIG_MTD_PARTITIONS | |
599 | struct mtd_partition *parts = info->platform->partitions; | |
600 | int nr = info->platform->nr_partitions; | |
601 | ||
602 | return add_mtd_partitions(mtd, parts, nr); | |
603 | #else | |
604 | return add_mtd_device(mtd); | |
605 | #endif | |
606 | } | |
607 | ||
608 | static int bf5xx_nand_remove(struct platform_device *pdev) | |
609 | { | |
610 | struct bf5xx_nand_info *info = to_nand_info(pdev); | |
611 | struct mtd_info *mtd = NULL; | |
612 | ||
613 | platform_set_drvdata(pdev, NULL); | |
614 | ||
615 | /* first thing we need to do is release all our mtds | |
616 | * and their partitions, then go through freeing the | |
617 | * resources used | |
618 | */ | |
619 | mtd = &info->mtd; | |
620 | if (mtd) { | |
621 | nand_release(mtd); | |
622 | kfree(mtd); | |
623 | } | |
624 | ||
625 | peripheral_free_list(bfin_nfc_pin_req); | |
626 | ||
627 | /* free the common resources */ | |
628 | kfree(info); | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | /* | |
634 | * bf5xx_nand_probe | |
635 | * | |
636 | * called by device layer when it finds a device matching | |
637 | * one our driver can handled. This code checks to see if | |
638 | * it can allocate all necessary resources then calls the | |
639 | * nand layer to look for devices | |
640 | */ | |
641 | static int bf5xx_nand_probe(struct platform_device *pdev) | |
642 | { | |
643 | struct bf5xx_nand_platform *plat = to_nand_plat(pdev); | |
644 | struct bf5xx_nand_info *info = NULL; | |
645 | struct nand_chip *chip = NULL; | |
646 | struct mtd_info *mtd = NULL; | |
647 | int err = 0; | |
648 | ||
649 | dev_dbg(&pdev->dev, "(%p)\n", pdev); | |
650 | ||
afc4bca6 MH |
651 | if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) { |
652 | printk(KERN_ERR DRV_NAME | |
653 | ": Requesting Peripherals failed\n"); | |
654 | return -EFAULT; | |
655 | } | |
656 | ||
b37bde14 BW |
657 | if (!plat) { |
658 | dev_err(&pdev->dev, "no platform specific information\n"); | |
659 | goto exit_error; | |
660 | } | |
661 | ||
662 | info = kzalloc(sizeof(*info), GFP_KERNEL); | |
663 | if (info == NULL) { | |
664 | dev_err(&pdev->dev, "no memory for flash info\n"); | |
665 | err = -ENOMEM; | |
666 | goto exit_error; | |
667 | } | |
668 | ||
669 | platform_set_drvdata(pdev, info); | |
670 | ||
671 | spin_lock_init(&info->controller.lock); | |
672 | init_waitqueue_head(&info->controller.wq); | |
673 | ||
674 | info->device = &pdev->dev; | |
675 | info->platform = plat; | |
676 | ||
677 | /* initialise chip data struct */ | |
678 | chip = &info->chip; | |
679 | ||
680 | if (plat->data_width) | |
681 | chip->options |= NAND_BUSWIDTH_16; | |
682 | ||
683 | chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN; | |
684 | ||
685 | chip->read_buf = (plat->data_width) ? | |
686 | bf5xx_nand_read_buf16 : bf5xx_nand_read_buf; | |
687 | chip->write_buf = (plat->data_width) ? | |
688 | bf5xx_nand_write_buf16 : bf5xx_nand_write_buf; | |
689 | ||
690 | chip->read_byte = bf5xx_nand_read_byte; | |
691 | ||
692 | chip->cmd_ctrl = bf5xx_nand_hwcontrol; | |
693 | chip->dev_ready = bf5xx_nand_devready; | |
694 | ||
695 | chip->priv = &info->mtd; | |
696 | chip->controller = &info->controller; | |
697 | ||
698 | chip->IO_ADDR_R = (void __iomem *) NFC_READ; | |
699 | chip->IO_ADDR_W = (void __iomem *) NFC_DATA_WR; | |
700 | ||
701 | chip->chip_delay = 0; | |
702 | ||
703 | /* initialise mtd info data struct */ | |
704 | mtd = &info->mtd; | |
705 | mtd->priv = chip; | |
706 | mtd->owner = THIS_MODULE; | |
707 | ||
708 | /* initialise the hardware */ | |
709 | err = bf5xx_nand_hw_init(info); | |
710 | if (err != 0) | |
711 | goto exit_error; | |
712 | ||
713 | /* setup hardware ECC data struct */ | |
714 | if (hardware_ecc) { | |
715 | if (plat->page_size == NFC_PG_SIZE_256) { | |
716 | chip->ecc.bytes = 3; | |
717 | chip->ecc.size = 256; | |
718 | } else if (plat->page_size == NFC_PG_SIZE_512) { | |
719 | chip->ecc.bytes = 6; | |
720 | chip->ecc.size = 512; | |
721 | } | |
722 | ||
723 | chip->read_buf = bf5xx_nand_dma_read_buf; | |
724 | chip->write_buf = bf5xx_nand_dma_write_buf; | |
725 | chip->ecc.calculate = bf5xx_nand_calculate_ecc; | |
726 | chip->ecc.correct = bf5xx_nand_correct_data; | |
727 | chip->ecc.mode = NAND_ECC_HW; | |
728 | chip->ecc.hwctl = bf5xx_nand_enable_hwecc; | |
729 | } else { | |
730 | chip->ecc.mode = NAND_ECC_SOFT; | |
731 | } | |
732 | ||
733 | /* scan hardware nand chip and setup mtd info data struct */ | |
734 | if (nand_scan(mtd, 1)) { | |
735 | err = -ENXIO; | |
736 | goto exit_error; | |
737 | } | |
738 | ||
739 | /* add NAND partition */ | |
740 | bf5xx_nand_add_partition(info); | |
741 | ||
742 | dev_dbg(&pdev->dev, "initialised ok\n"); | |
743 | return 0; | |
744 | ||
745 | exit_error: | |
746 | bf5xx_nand_remove(pdev); | |
747 | ||
748 | if (err == 0) | |
749 | err = -EINVAL; | |
750 | return err; | |
751 | } | |
752 | ||
753 | /* PM Support */ | |
754 | #ifdef CONFIG_PM | |
755 | ||
756 | static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
757 | { | |
758 | struct bf5xx_nand_info *info = platform_get_drvdata(dev); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
763 | static int bf5xx_nand_resume(struct platform_device *dev) | |
764 | { | |
765 | struct bf5xx_nand_info *info = platform_get_drvdata(dev); | |
766 | ||
b37bde14 BW |
767 | return 0; |
768 | } | |
769 | ||
770 | #else | |
771 | #define bf5xx_nand_suspend NULL | |
772 | #define bf5xx_nand_resume NULL | |
773 | #endif | |
774 | ||
775 | /* driver device registration */ | |
776 | static struct platform_driver bf5xx_nand_driver = { | |
777 | .probe = bf5xx_nand_probe, | |
778 | .remove = bf5xx_nand_remove, | |
779 | .suspend = bf5xx_nand_suspend, | |
780 | .resume = bf5xx_nand_resume, | |
781 | .driver = { | |
782 | .name = DRV_NAME, | |
783 | .owner = THIS_MODULE, | |
784 | }, | |
785 | }; | |
786 | ||
787 | static int __init bf5xx_nand_init(void) | |
788 | { | |
789 | printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n", | |
790 | DRV_DESC, DRV_VERSION); | |
791 | ||
792 | return platform_driver_register(&bf5xx_nand_driver); | |
793 | } | |
794 | ||
795 | static void __exit bf5xx_nand_exit(void) | |
796 | { | |
797 | platform_driver_unregister(&bf5xx_nand_driver); | |
798 | } | |
799 | ||
800 | module_init(bf5xx_nand_init); | |
801 | module_exit(bf5xx_nand_exit); | |
802 | ||
803 | MODULE_LICENSE("GPL"); | |
804 | MODULE_AUTHOR(DRV_AUTHOR); | |
805 | MODULE_DESCRIPTION(DRV_DESC); | |
1ff18422 | 806 | MODULE_ALIAS("platform:" DRV_NAME); |