[net-next-2.6.git] / drivers / mtd / nand / au1550nd.c

/*
 *  drivers/mtd/nand/au1550nd.c
 *
 *  Copyright (C) 2004 Embedded Edge, LLC
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/version.h>
#include <asm/io.h>

#include <asm/mach-au1x00/au1xxx.h>

/*
 * MTD structure for NAND controller
 */
static struct mtd_info *au1550_mtd = NULL;
static void __iomem *p_nand;
static int nand_width = 1;	/* default x8 */
static void (*au1550_write_byte)(struct mtd_info *, u_char);

/*
 * Define partitions for flash device
 */
static const struct mtd_partition partition_info[] = {
	{
	 .name = "NAND FS 0",
	 .offset = 0,
	 .size = 8 * 1024 * 1024},
	{
	 .name = "NAND FS 1",
	 .offset = MTDPART_OFS_APPEND,
	 .size = MTDPART_SIZ_FULL}
};

/**
 * au_read_byte -  read one byte from the chip
 * @mtd:	MTD device structure
 *
 *  read function for 8bit buswith
 */
static u_char au_read_byte(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	u_char ret = readb(this->IO_ADDR_R);
	au_sync();
	return ret;
}

/**
 * au_write_byte -  write one byte to the chip
 * @mtd:	MTD device structure
 * @byte:	pointer to data byte to write
 *
 *  write function for 8it buswith
 */
static void au_write_byte(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	writeb(byte, this->IO_ADDR_W);
	au_sync();
}

/**
 * au_read_byte16 -  read one byte endianess aware from the chip
 * @mtd:	MTD device structure
 *
 *  read function for 16bit buswith with
 * endianess conversion
 */
static u_char au_read_byte16(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
	au_sync();
	return ret;
}

/**
 * au_write_byte16 -  write one byte endianess aware to the chip
 * @mtd:	MTD device structure
 * @byte:	pointer to data byte to write
 *
 *  write function for 16bit buswith with
 * endianess conversion
 */
static void au_write_byte16(struct mtd_info *mtd, u_char byte)
{
	struct nand_chip *this = mtd->priv;
	writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
	au_sync();
}

/**
 * au_read_word -  read one word from the chip
 * @mtd:	MTD device structure
 *
 *  read function for 16bit buswith without
 * endianess conversion
 */
static u16 au_read_word(struct mtd_info *mtd)
{
	struct nand_chip *this = mtd->priv;
	u16 ret = readw(this->IO_ADDR_R);
	au_sync();
	return ret;
}

/**
 * au_write_buf -  write buffer to chip
 * @mtd:	MTD device structure
 * @buf:	data buffer
 * @len:	number of bytes to write
 *
 *  write function for 8bit buswith
 */
static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;

	for (i = 0; i < len; i++) {
		writeb(buf[i], this->IO_ADDR_W);
		au_sync();
	}
}

/**
 * au_read_buf -  read chip data into buffer
 * @mtd:	MTD device structure
 * @buf:	buffer to store date
 * @len:	number of bytes to read
 *
 *  read function for 8bit buswith
 */
static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;

	for (i = 0; i < len; i++) {
		buf[i] = readb(this->IO_ADDR_R);
		au_sync();
	}
}

/**
 * au_verify_buf -  Verify chip data against buffer
 * @mtd:	MTD device structure
 * @buf:	buffer containing the data to compare
 * @len:	number of bytes to compare
 *
 *  verify function for 8bit buswith
 */
static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;

	for (i = 0; i < len; i++) {
		if (buf[i] != readb(this->IO_ADDR_R))
			return -EFAULT;
		au_sync();
	}

	return 0;
}

/**
 * au_write_buf16 -  write buffer to chip
 * @mtd:	MTD device structure
 * @buf:	data buffer
 * @len:	number of bytes to write
 *
 *  write function for 16bit buswith
 */
static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;
	u16 *p = (u16 *) buf;
	len >>= 1;

	for (i = 0; i < len; i++) {
		writew(p[i], this->IO_ADDR_W);
		au_sync();
	}

}

/**
 * au_read_buf16 -  read chip data into buffer
 * @mtd:	MTD device structure
 * @buf:	buffer to store date
 * @len:	number of bytes to read
 *
 *  read function for 16bit buswith
 */
static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;
	u16 *p = (u16 *) buf;
	len >>= 1;

	for (i = 0; i < len; i++) {
		p[i] = readw(this->IO_ADDR_R);
		au_sync();
	}
}

/**
 * au_verify_buf16 -  Verify chip data against buffer
 * @mtd:	MTD device structure
 * @buf:	buffer containing the data to compare
 * @len:	number of bytes to compare
 *
 *  verify function for 16bit buswith
 */
static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
{
	int i;
	struct nand_chip *this = mtd->priv;
	u16 *p = (u16 *) buf;
	len >>= 1;

	for (i = 0; i < len; i++) {
		if (p[i] != readw(this->IO_ADDR_R))
			return -EFAULT;
		au_sync();
	}
	return 0;
}

/* Select the chip by setting nCE to low */
#define NAND_CTL_SETNCE		1
/* Deselect the chip by setting nCE to high */
#define NAND_CTL_CLRNCE		2
/* Select the command latch by setting CLE to high */
#define NAND_CTL_SETCLE		3
/* Deselect the command latch by setting CLE to low */
#define NAND_CTL_CLRCLE		4
/* Select the address latch by setting ALE to high */
#define NAND_CTL_SETALE		5
/* Deselect the address latch by setting ALE to low */
#define NAND_CTL_CLRALE		6

static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
{
	register struct nand_chip *this = mtd->priv;

	switch (cmd) {

	case NAND_CTL_SETCLE:
		this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
		break;

	case NAND_CTL_CLRCLE:
		this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
		break;

	case NAND_CTL_SETALE:
		this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
		break;

	case NAND_CTL_CLRALE:
		this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
		/* FIXME: Nobody knows why this is necessary,
		 * but it works only that way */
		udelay(1);
		break;

	case NAND_CTL_SETNCE:
		/* assert (force assert) chip enable */
		au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
		break;

	case NAND_CTL_CLRNCE:
		/* deassert chip enable */
		au_writel(0, MEM_STNDCTL);
		break;
	}

	this->IO_ADDR_R = this->IO_ADDR_W;

	/* Drain the writebuffer */
	au_sync();
}

int au1550_device_ready(struct mtd_info *mtd)
{
	int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
	au_sync();
	return ret;
}

/**
 * au1550_select_chip - control -CE line
 *	Forbid driving -CE manually permitting the NAND controller to do this.
 *	Keeping -CE asserted during the whole sector reads interferes with the
 *	NOR flash and PCMCIA drivers as it causes contention on the static bus.
 *	We only have to hold -CE low for the NAND read commands since the flash
 *	chip needs it to be asserted during chip not ready time but the NAND
 *	controller keeps it released.
 *
 * @mtd:	MTD device structure
 * @chip:	chipnumber to select, -1 for deselect
 */
static void au1550_select_chip(struct mtd_info *mtd, int chip)
{
}

/**
 * au1550_command - Send command to NAND device
 * @mtd:	MTD device structure
 * @command:	the command to be sent
 * @column:	the column address for this command, -1 if none
 * @page_addr:	the page address for this command, -1 if none
 */
static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
{
	register struct nand_chip *this = mtd->priv;
	int ce_override = 0, i;
	ulong flags;

	/* Begin command latch cycle */
	au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
	/*
	 * Write out the command to the device.
	 */
	if (command == NAND_CMD_SEQIN) {
		int readcmd;

		if (column >= mtd->writesize) {
			/* OOB area */
			column -= mtd->writesize;
			readcmd = NAND_CMD_READOOB;
		} else if (column < 256) {
			/* First 256 bytes --> READ0 */
			readcmd = NAND_CMD_READ0;
		} else {
			column -= 256;
			readcmd = NAND_CMD_READ1;
		}
		au1550_write_byte(mtd, readcmd);
	}
	au1550_write_byte(mtd, command);

	/* Set ALE and clear CLE to start address cycle */
	au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);

	if (column != -1 || page_addr != -1) {
		au1550_hwcontrol(mtd, NAND_CTL_SETALE);

		/* Serially input address */
		if (column != -1) {
			/* Adjust columns for 16 bit buswidth */
			if (this->options & NAND_BUSWIDTH_16)
				column >>= 1;
			au1550_write_byte(mtd, column);
		}
		if (page_addr != -1) {
			au1550_write_byte(mtd, (u8)(page_addr & 0xff));

			if (command == NAND_CMD_READ0 ||
			    command == NAND_CMD_READ1 ||
			    command == NAND_CMD_READOOB) {
				/*
				 * NAND controller will release -CE after
				 * the last address byte is written, so we'll
				 * have to forcibly assert it. No interrupts
				 * are allowed while we do this as we don't
				 * want the NOR flash or PCMCIA drivers to
				 * steal our precious bytes of data...
				 */
				ce_override = 1;
				local_irq_save(flags);
				au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
			}

			au1550_write_byte(mtd, (u8)(page_addr >> 8));

			/* One more address cycle for devices > 32MiB */
			if (this->chipsize > (32 << 20))
				au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
		}
		/* Latch in address */
		au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
	}

	/*
	 * Program and erase have their own busy handlers.
	 * Status and sequential in need no delay.
	 */
	switch (command) {

	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
	case NAND_CMD_STATUS:
		return;

	case NAND_CMD_RESET:
		break;

	case NAND_CMD_READ0:
	case NAND_CMD_READ1:
	case NAND_CMD_READOOB:
		/* Check if we're really driving -CE low (just in case) */
		if (unlikely(!ce_override))
			break;

		/* Apply a short delay always to ensure that we do wait tWB. */
		ndelay(100);
		/* Wait for a chip to become ready... */
		for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
			udelay(1);

		/* Release -CE and re-enable interrupts. */
		au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
		local_irq_restore(flags);
		return;
	}
	/* Apply this short delay always to ensure that we do wait tWB. */
	ndelay(100);

	while(!this->dev_ready(mtd));
}


/*
 * Main initialization routine
 */
static int __init au1xxx_nand_init(void)
{
	struct nand_chip *this;
	u16 boot_swapboot = 0;	/* default value */
	int retval;
	u32 mem_staddr;
	u32 nand_phys;

	/* Allocate memory for MTD device structure and private data */
	au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
	if (!au1550_mtd) {
		printk("Unable to allocate NAND MTD dev structure.\n");
		return -ENOMEM;
	}

	/* Get pointer to private data */
	this = (struct nand_chip *)(&au1550_mtd[1]);

	/* Initialize structures */
	memset(au1550_mtd, 0, sizeof(struct mtd_info));
	memset(this, 0, sizeof(struct nand_chip));

	/* Link the private data with the MTD structure */
	au1550_mtd->priv = this;
	au1550_mtd->owner = THIS_MODULE;


	/* MEM_STNDCTL: disable ints, disable nand boot */
	au_writel(0, MEM_STNDCTL);

#ifdef CONFIG_MIPS_PB1550
	/* set gpio206 high */
	au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);

	boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr->status >> 6) & 0x1);
	switch (boot_swapboot) {
	case 0:
	case 2:
	case 8:
	case 0xC:
	case 0xD:
		/* x16 NAND Flash */
		nand_width = 0;
		break;
	case 1:
	case 9:
	case 3:
	case 0xE:
	case 0xF:
		/* x8 NAND Flash */
		nand_width = 1;
		break;
	default:
		printk("Pb1550 NAND: bad boot:swap\n");
		retval = -EINVAL;
		goto outmem;
	}
#endif

	/* Configure chip-select; normally done by boot code, e.g. YAMON */
#ifdef NAND_STCFG
	if (NAND_CS == 0) {
		au_writel(NAND_STCFG,  MEM_STCFG0);
		au_writel(NAND_STTIME, MEM_STTIME0);
		au_writel(NAND_STADDR, MEM_STADDR0);
	}
	if (NAND_CS == 1) {
		au_writel(NAND_STCFG,  MEM_STCFG1);
		au_writel(NAND_STTIME, MEM_STTIME1);
		au_writel(NAND_STADDR, MEM_STADDR1);
	}
	if (NAND_CS == 2) {
		au_writel(NAND_STCFG,  MEM_STCFG2);
		au_writel(NAND_STTIME, MEM_STTIME2);
		au_writel(NAND_STADDR, MEM_STADDR2);
	}
	if (NAND_CS == 3) {
		au_writel(NAND_STCFG,  MEM_STCFG3);
		au_writel(NAND_STTIME, MEM_STTIME3);
		au_writel(NAND_STADDR, MEM_STADDR3);
	}
#endif

	/* Locate NAND chip-select in order to determine NAND phys address */
	mem_staddr = 0x00000000;
	if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
		mem_staddr = au_readl(MEM_STADDR0);
	else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
		mem_staddr = au_readl(MEM_STADDR1);
	else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
		mem_staddr = au_readl(MEM_STADDR2);
	else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
		mem_staddr = au_readl(MEM_STADDR3);

	if (mem_staddr == 0x00000000) {
		printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
		kfree(au1550_mtd);
		return 1;
	}
	nand_phys = (mem_staddr << 4) & 0xFFFC0000;

	p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);

	/* make controller and MTD agree */
	if (NAND_CS == 0)
		nand_width = au_readl(MEM_STCFG0) & (1 << 22);
	if (NAND_CS == 1)
		nand_width = au_readl(MEM_STCFG1) & (1 << 22);
	if (NAND_CS == 2)
		nand_width = au_readl(MEM_STCFG2) & (1 << 22);
	if (NAND_CS == 3)
		nand_width = au_readl(MEM_STCFG3) & (1 << 22);

	/* Set address of hardware control function */
	this->dev_ready = au1550_device_ready;
	this->select_chip = au1550_select_chip;
	this->cmdfunc = au1550_command;

	/* 30 us command delay time */
	this->chip_delay = 30;
	this->ecc.mode = NAND_ECC_SOFT;

	this->options = NAND_NO_AUTOINCR;

	if (!nand_width)
		this->options |= NAND_BUSWIDTH_16;

	this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
	au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
	this->read_word = au_read_word;
	this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
	this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
	this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;

	/* Scan to find existence of the device */
	if (nand_scan(au1550_mtd, 1)) {
		retval = -ENXIO;
		goto outio;
	}

	/* Register the partitions */
	add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));

	return 0;

 outio:
	iounmap((void *)p_nand);

 outmem:
	kfree(au1550_mtd);
	return retval;
}

module_init(au1xxx_nand_init);

/*
 * Clean up routine
 */
static void __exit au1550_cleanup(void)
{
	/* Release resources, unregister device */
	nand_release(au1550_mtd);

	/* Free the MTD device structure */
	kfree(au1550_mtd);

	/* Unmap */
	iounmap((void *)p_nand);
}

module_exit(au1550_cleanup);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Embedded Edge, LLC");
MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/mtd/nand/au1550nd.c
	3	*
	4	* Copyright (C) 2004 Embedded Edge, LLC
	5	*
1da177e4 LT	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	#include <linux/slab.h>
	13	#include <linux/init.h>
	14	#include <linux/module.h>
35af68b5	15	#include <linux/interrupt.h>
1da177e4 LT	16	#include <linux/mtd/mtd.h>
	17	#include <linux/mtd/nand.h>
	18	#include <linux/mtd/partitions.h>
733482e4	19	#include <linux/version.h>
1da177e4 LT	20	#include <asm/io.h>
1da177e4 LT	21
ef6f0d1f	22	#include <asm/mach-au1x00/au1xxx.h>
1da177e4 LT	23
	24	/*
	25	* MTD structure for NAND controller
	26	*/
	27	static struct mtd_info *au1550_mtd = NULL;
	28	static void __iomem *p_nand;
e0c7d767	29	static int nand_width = 1; /* default x8 */
cad74f2c	30	static void (au1550_write_byte)(struct mtd_info , u_char);
1da177e4	31
1da177e4 LT	32	/*
	33	* Define partitions for flash device
	34	*/
3c6bee1d	35	static const struct mtd_partition partition_info[] = {
61b03bd7	36	{
e0c7d767 DW	37	.name = "NAND FS 0",
	38	.offset = 0,
	39	.size = 8 * 1024 * 1024},
61b03bd7	40	{
e0c7d767 DW	41	.name = "NAND FS 1",
	42	.offset = MTDPART_OFS_APPEND,
	43	.size = MTDPART_SIZ_FULL}
1da177e4	44	};
1da177e4 LT	45
	46	/**
	47	* au_read_byte - read one byte from the chip
	48	* @mtd: MTD device structure
	49	*
	50	* read function for 8bit buswith
	51	*/
	52	static u_char au_read_byte(struct mtd_info *mtd)
	53	{
	54	struct nand_chip *this = mtd->priv;
	55	u_char ret = readb(this->IO_ADDR_R);
	56	au_sync();
	57	return ret;
	58	}
	59
	60	/**
	61	* au_write_byte - write one byte to the chip
	62	* @mtd: MTD device structure
	63	* @byte: pointer to data byte to write
	64	*
	65	* write function for 8it buswith
	66	*/
	67	static void au_write_byte(struct mtd_info *mtd, u_char byte)
	68	{
	69	struct nand_chip *this = mtd->priv;
	70	writeb(byte, this->IO_ADDR_W);
	71	au_sync();
	72	}
	73
	74	/**
	75	* au_read_byte16 - read one byte endianess aware from the chip
	76	* @mtd: MTD device structure
	77	*
61b03bd7	78	* read function for 16bit buswith with
1da177e4 LT	79	* endianess conversion
	80	*/
	81	static u_char au_read_byte16(struct mtd_info *mtd)
	82	{
	83	struct nand_chip *this = mtd->priv;
	84	u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
	85	au_sync();
	86	return ret;
	87	}
	88
	89	/**
	90	* au_write_byte16 - write one byte endianess aware to the chip
	91	* @mtd: MTD device structure
	92	* @byte: pointer to data byte to write
	93	*
	94	* write function for 16bit buswith with
	95	* endianess conversion
	96	*/
	97	static void au_write_byte16(struct mtd_info *mtd, u_char byte)
	98	{
	99	struct nand_chip *this = mtd->priv;
	100	writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
	101	au_sync();
	102	}
	103
	104	/**
	105	* au_read_word - read one word from the chip
	106	* @mtd: MTD device structure
	107	*
61b03bd7	108	* read function for 16bit buswith without
1da177e4 LT	109	* endianess conversion
	110	*/
	111	static u16 au_read_word(struct mtd_info *mtd)
	112	{
	113	struct nand_chip *this = mtd->priv;
	114	u16 ret = readw(this->IO_ADDR_R);
	115	au_sync();
	116	return ret;
	117	}
	118
1da177e4 LT	119	/**
	120	* au_write_buf - write buffer to chip
	121	* @mtd: MTD device structure
	122	* @buf: data buffer
	123	* @len: number of bytes to write
	124	*
	125	* write function for 8bit buswith
	126	*/
	127	static void au_write_buf(struct mtd_info mtd, const u_char buf, int len)
	128	{
	129	int i;
	130	struct nand_chip *this = mtd->priv;
	131
e0c7d767	132	for (i = 0; i < len; i++) {
1da177e4 LT	133	writeb(buf[i], this->IO_ADDR_W);
	134	au_sync();
	135	}
	136	}
	137
	138	/**
61b03bd7	139	* au_read_buf - read chip data into buffer
1da177e4 LT	140	* @mtd: MTD device structure
	141	* @buf: buffer to store date
	142	* @len: number of bytes to read
	143	*
	144	* read function for 8bit buswith
	145	*/
	146	static void au_read_buf(struct mtd_info mtd, u_char buf, int len)
	147	{
	148	int i;
	149	struct nand_chip *this = mtd->priv;
	150
e0c7d767	151	for (i = 0; i < len; i++) {
1da177e4	152	buf[i] = readb(this->IO_ADDR_R);
61b03bd7	153	au_sync();
1da177e4 LT	154	}
	155	}
	156
	157	/**
61b03bd7	158	* au_verify_buf - Verify chip data against buffer
1da177e4 LT	159	* @mtd: MTD device structure
	160	* @buf: buffer containing the data to compare
	161	* @len: number of bytes to compare
	162	*
	163	* verify function for 8bit buswith
	164	*/
	165	static int au_verify_buf(struct mtd_info mtd, const u_char buf, int len)
	166	{
	167	int i;
	168	struct nand_chip *this = mtd->priv;
	169
e0c7d767	170	for (i = 0; i < len; i++) {
1da177e4 LT	171	if (buf[i] != readb(this->IO_ADDR_R))
	172	return -EFAULT;
	173	au_sync();
	174	}
	175
	176	return 0;
	177	}
	178
	179	/**
	180	* au_write_buf16 - write buffer to chip
	181	* @mtd: MTD device structure
	182	* @buf: data buffer
	183	* @len: number of bytes to write
	184	*
	185	* write function for 16bit buswith
	186	*/
	187	static void au_write_buf16(struct mtd_info mtd, const u_char buf, int len)
	188	{
	189	int i;
	190	struct nand_chip *this = mtd->priv;
	191	u16 p = (u16 ) buf;
	192	len >>= 1;
61b03bd7	193
e0c7d767	194	for (i = 0; i < len; i++) {
1da177e4 LT	195	writew(p[i], this->IO_ADDR_W);
	196	au_sync();
	197	}
61b03bd7	198
1da177e4 LT	199	}
	200
	201	/**
61b03bd7	202	* au_read_buf16 - read chip data into buffer
1da177e4 LT	203	* @mtd: MTD device structure
	204	* @buf: buffer to store date
	205	* @len: number of bytes to read
	206	*
	207	* read function for 16bit buswith
	208	*/
	209	static void au_read_buf16(struct mtd_info mtd, u_char buf, int len)
	210	{
	211	int i;
	212	struct nand_chip *this = mtd->priv;
	213	u16 p = (u16 ) buf;
	214	len >>= 1;
	215
e0c7d767	216	for (i = 0; i < len; i++) {
1da177e4 LT	217	p[i] = readw(this->IO_ADDR_R);
	218	au_sync();
	219	}
	220	}
	221
	222	/**
61b03bd7	223	* au_verify_buf16 - Verify chip data against buffer
1da177e4 LT	224	* @mtd: MTD device structure
	225	* @buf: buffer containing the data to compare
	226	* @len: number of bytes to compare
	227	*
	228	* verify function for 16bit buswith
	229	*/
	230	static int au_verify_buf16(struct mtd_info mtd, const u_char buf, int len)
	231	{
	232	int i;
	233	struct nand_chip *this = mtd->priv;
	234	u16 p = (u16 ) buf;
	235	len >>= 1;
	236
e0c7d767	237	for (i = 0; i < len; i++) {
1da177e4 LT	238	if (p[i] != readw(this->IO_ADDR_R))
	239	return -EFAULT;
	240	au_sync();
	241	}
	242	return 0;
	243	}
	244
7abd3ef9 TG	245	/* Select the chip by setting nCE to low */
	246	#define NAND_CTL_SETNCE 1
	247	/* Deselect the chip by setting nCE to high */
	248	#define NAND_CTL_CLRNCE 2
	249	/* Select the command latch by setting CLE to high */
	250	#define NAND_CTL_SETCLE 3
	251	/* Deselect the command latch by setting CLE to low */
	252	#define NAND_CTL_CLRCLE 4
	253	/* Select the address latch by setting ALE to high */
	254	#define NAND_CTL_SETALE 5
	255	/* Deselect the address latch by setting ALE to low */
	256	#define NAND_CTL_CLRALE 6
1da177e4 LT	257
	258	static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
	259	{
	260	register struct nand_chip *this = mtd->priv;
	261
e0c7d767 DW	262	switch (cmd) {
	263
	264	case NAND_CTL_SETCLE:
	265	this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
	266	break;
	267
	268	case NAND_CTL_CLRCLE:
	269	this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
	270	break;
1da177e4	271
e0c7d767 DW	272	case NAND_CTL_SETALE:
	273	this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
	274	break;
1da177e4	275
61b03bd7 TG	276	case NAND_CTL_CLRALE:
61b03bd7 TG	277	this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
e0c7d767	278	/* FIXME: Nobody knows why this is necessary,
1da177e4	279	* but it works only that way */
61b03bd7	280	udelay(1);
1da177e4 LT	281	break;
1da177e4 LT	282
61b03bd7	283	case NAND_CTL_SETNCE:
1da177e4	284	/* assert (force assert) chip enable */
e0c7d767	285	au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
1da177e4 LT	286	break;
1da177e4 LT	287
61b03bd7	288	case NAND_CTL_CLRNCE:
e0c7d767 DW	289	/* deassert chip enable */
e0c7d767 DW	290	au_writel(0, MEM_STNDCTL);
1da177e4 LT	291	break;
	292	}
	293
	294	this->IO_ADDR_R = this->IO_ADDR_W;
61b03bd7	295
1da177e4 LT	296	/* Drain the writebuffer */
	297	au_sync();
	298	}
	299
	300	int au1550_device_ready(struct mtd_info *mtd)
	301	{
	302	int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
	303	au_sync();
	304	return ret;
	305	}
	306
35af68b5 SS	307	/**
	308	* au1550_select_chip - control -CE line
	309	* Forbid driving -CE manually permitting the NAND controller to do this.
	310	* Keeping -CE asserted during the whole sector reads interferes with the
	311	* NOR flash and PCMCIA drivers as it causes contention on the static bus.
	312	* We only have to hold -CE low for the NAND read commands since the flash
	313	* chip needs it to be asserted during chip not ready time but the NAND
	314	* controller keeps it released.
	315	*
	316	* @mtd: MTD device structure
	317	* @chip: chipnumber to select, -1 for deselect
	318	*/
	319	static void au1550_select_chip(struct mtd_info *mtd, int chip)
	320	{
	321	}
	322
	323	/**
	324	* au1550_command - Send command to NAND device
	325	* @mtd: MTD device structure
	326	* @command: the command to be sent
	327	* @column: the column address for this command, -1 if none
	328	* @page_addr: the page address for this command, -1 if none
	329	*/
	330	static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
	331	{
	332	register struct nand_chip *this = mtd->priv;
	333	int ce_override = 0, i;
	334	ulong flags;
	335
	336	/* Begin command latch cycle */
7abd3ef9	337	au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
35af68b5 SS	338	/*
	339	* Write out the command to the device.
	340	*/
	341	if (command == NAND_CMD_SEQIN) {
	342	int readcmd;
	343
28318776	344	if (column >= mtd->writesize) {
35af68b5	345	/* OOB area */
28318776	346	column -= mtd->writesize;
35af68b5 SS	347	readcmd = NAND_CMD_READOOB;
	348	} else if (column < 256) {
	349	/* First 256 bytes --> READ0 */
	350	readcmd = NAND_CMD_READ0;
	351	} else {
	352	column -= 256;
	353	readcmd = NAND_CMD_READ1;
	354	}
cad74f2c	355	au1550_write_byte(mtd, readcmd);
35af68b5	356	}
cad74f2c	357	au1550_write_byte(mtd, command);
35af68b5 SS	358
35af68b5 SS	359	/* Set ALE and clear CLE to start address cycle */
7abd3ef9	360	au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
35af68b5 SS	361
35af68b5 SS	362	if (column != -1 \|\| page_addr != -1) {
7abd3ef9	363	au1550_hwcontrol(mtd, NAND_CTL_SETALE);
35af68b5 SS	364
	365	/* Serially input address */
	366	if (column != -1) {
	367	/* Adjust columns for 16 bit buswidth */
	368	if (this->options & NAND_BUSWIDTH_16)
	369	column >>= 1;
cad74f2c	370	au1550_write_byte(mtd, column);
35af68b5 SS	371	}
35af68b5 SS	372	if (page_addr != -1) {
cad74f2c	373	au1550_write_byte(mtd, (u8)(page_addr & 0xff));
35af68b5 SS	374
	375	if (command == NAND_CMD_READ0 \|\|
	376	command == NAND_CMD_READ1 \|\|
	377	command == NAND_CMD_READOOB) {
	378	/*
	379	* NAND controller will release -CE after
	380	* the last address byte is written, so we'll
	381	* have to forcibly assert it. No interrupts
	382	* are allowed while we do this as we don't
	383	* want the NOR flash or PCMCIA drivers to
	384	* steal our precious bytes of data...
	385	*/
	386	ce_override = 1;
	387	local_irq_save(flags);
7abd3ef9	388	au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
35af68b5 SS	389	}
35af68b5 SS	390
cad74f2c	391	au1550_write_byte(mtd, (u8)(page_addr >> 8));
35af68b5 SS	392
	393	/* One more address cycle for devices > 32MiB */
	394	if (this->chipsize > (32 << 20))
cad74f2c	395	au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
35af68b5 SS	396	}
35af68b5 SS	397	/* Latch in address */
7abd3ef9	398	au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
35af68b5 SS	399	}
	400
	401	/*
	402	* Program and erase have their own busy handlers.
	403	* Status and sequential in need no delay.
	404	*/
	405	switch (command) {
	406
	407	case NAND_CMD_PAGEPROG:
	408	case NAND_CMD_ERASE1:
	409	case NAND_CMD_ERASE2:
	410	case NAND_CMD_SEQIN:
	411	case NAND_CMD_STATUS:
	412	return;
	413
	414	case NAND_CMD_RESET:
	415	break;
	416
	417	case NAND_CMD_READ0:
	418	case NAND_CMD_READ1:
	419	case NAND_CMD_READOOB:
	420	/* Check if we're really driving -CE low (just in case) */
	421	if (unlikely(!ce_override))
	422	break;
	423
	424	/* Apply a short delay always to ensure that we do wait tWB. */
	425	ndelay(100);
	426	/* Wait for a chip to become ready... */
	427	for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
	428	udelay(1);
	429
	430	/* Release -CE and re-enable interrupts. */
7abd3ef9	431	au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
35af68b5 SS	432	local_irq_restore(flags);
	433	return;
	434	}
	435	/* Apply this short delay always to ensure that we do wait tWB. */
	436	ndelay(100);
	437
	438	while(!this->dev_ready(mtd));
	439	}
	440
	441
1da177e4 LT	442	/*
	443	* Main initialization routine
	444	*/
cead4dbc	445	static int __init au1xxx_nand_init(void)
1da177e4 LT	446	{
1da177e4 LT	447	struct nand_chip *this;
e0c7d767	448	u16 boot_swapboot = 0; /* default value */
1da177e4	449	int retval;
ef6f0d1f PP	450	u32 mem_staddr;
ef6f0d1f PP	451	u32 nand_phys;
1da177e4 LT	452
1da177e4 LT	453	/* Allocate memory for MTD device structure and private data */
e0c7d767	454	au1550_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
1da177e4	455	if (!au1550_mtd) {
e0c7d767	456	printk("Unable to allocate NAND MTD dev structure.\n");
1da177e4 LT	457	return -ENOMEM;
	458	}
	459
	460	/* Get pointer to private data */
e0c7d767	461	this = (struct nand_chip *)(&au1550_mtd[1]);
1da177e4 LT	462
1da177e4 LT	463	/* Initialize structures */
e0c7d767 DW	464	memset(au1550_mtd, 0, sizeof(struct mtd_info));
e0c7d767 DW	465	memset(this, 0, sizeof(struct nand_chip));
1da177e4 LT	466
	467	/* Link the private data with the MTD structure */
	468	au1550_mtd->priv = this;
552d9205	469	au1550_mtd->owner = THIS_MODULE;
1da177e4	470
61b03bd7	471
155285c4 SS	472	/* MEM_STNDCTL: disable ints, disable nand boot */
155285c4 SS	473	au_writel(0, MEM_STNDCTL);
1da177e4 LT	474
	475	#ifdef CONFIG_MIPS_PB1550
	476	/* set gpio206 high */
e0c7d767	477	au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR);
1da177e4	478
e0c7d767	479	boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) \| ((bcsr->status >> 6) & 0x1);
1da177e4	480	switch (boot_swapboot) {
e0c7d767 DW	481	case 0:
	482	case 2:
	483	case 8:
	484	case 0xC:
	485	case 0xD:
	486	/* x16 NAND Flash */
	487	nand_width = 0;
	488	break;
	489	case 1:
	490	case 9:
	491	case 3:
	492	case 0xE:
	493	case 0xF:
	494	/* x8 NAND Flash */
	495	nand_width = 1;
	496	break;
	497	default:
	498	printk("Pb1550 NAND: bad boot:swap\n");
	499	retval = -EINVAL;
	500	goto outmem;
1da177e4 LT	501	}
	502	#endif
	503
ef6f0d1f PP	504	/* Configure chip-select; normally done by boot code, e.g. YAMON */
	505	#ifdef NAND_STCFG
	506	if (NAND_CS == 0) {
	507	au_writel(NAND_STCFG, MEM_STCFG0);
	508	au_writel(NAND_STTIME, MEM_STTIME0);
	509	au_writel(NAND_STADDR, MEM_STADDR0);
	510	}
	511	if (NAND_CS == 1) {
	512	au_writel(NAND_STCFG, MEM_STCFG1);
	513	au_writel(NAND_STTIME, MEM_STTIME1);
	514	au_writel(NAND_STADDR, MEM_STADDR1);
	515	}
	516	if (NAND_CS == 2) {
	517	au_writel(NAND_STCFG, MEM_STCFG2);
	518	au_writel(NAND_STTIME, MEM_STTIME2);
	519	au_writel(NAND_STADDR, MEM_STADDR2);
	520	}
	521	if (NAND_CS == 3) {
	522	au_writel(NAND_STCFG, MEM_STCFG3);
	523	au_writel(NAND_STTIME, MEM_STTIME3);
	524	au_writel(NAND_STADDR, MEM_STADDR3);
	525	}
	526	#endif
61b03bd7	527
ef6f0d1f PP	528	/* Locate NAND chip-select in order to determine NAND phys address */
	529	mem_staddr = 0x00000000;
	530	if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
	531	mem_staddr = au_readl(MEM_STADDR0);
	532	else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
	533	mem_staddr = au_readl(MEM_STADDR1);
	534	else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
	535	mem_staddr = au_readl(MEM_STADDR2);
	536	else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
	537	mem_staddr = au_readl(MEM_STADDR3);
	538
	539	if (mem_staddr == 0x00000000) {
	540	printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
	541	kfree(au1550_mtd);
	542	return 1;
	543	}
	544	nand_phys = (mem_staddr << 4) & 0xFFFC0000;
1da177e4	545
ef6f0d1f PP	546	p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
	547
	548	/* make controller and MTD agree */
	549	if (NAND_CS == 0)
e0c7d767	550	nand_width = au_readl(MEM_STCFG0) & (1 << 22);
ef6f0d1f	551	if (NAND_CS == 1)
e0c7d767	552	nand_width = au_readl(MEM_STCFG1) & (1 << 22);
ef6f0d1f	553	if (NAND_CS == 2)
e0c7d767	554	nand_width = au_readl(MEM_STCFG2) & (1 << 22);
ef6f0d1f	555	if (NAND_CS == 3)
e0c7d767	556	nand_width = au_readl(MEM_STCFG3) & (1 << 22);
1da177e4 LT	557
1da177e4 LT	558	/* Set address of hardware control function */
1da177e4	559	this->dev_ready = au1550_device_ready;
35af68b5 SS	560	this->select_chip = au1550_select_chip;
	561	this->cmdfunc = au1550_command;
	562
1da177e4	563	/* 30 us command delay time */
61b03bd7	564	this->chip_delay = 30;
6dfc6d25	565	this->ecc.mode = NAND_ECC_SOFT;
1da177e4 LT	566
	567	this->options = NAND_NO_AUTOINCR;
	568
	569	if (!nand_width)
	570	this->options \|= NAND_BUSWIDTH_16;
	571
	572	this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
cad74f2c	573	au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
1da177e4 LT	574	this->read_word = au_read_word;
	575	this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
	576	this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
	577	this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
	578
	579	/* Scan to find existence of the device */
e0c7d767	580	if (nand_scan(au1550_mtd, 1)) {
1da177e4 LT	581	retval = -ENXIO;
	582	goto outio;
	583	}
	584
	585	/* Register the partitions */
87d10f3c	586	add_mtd_partitions(au1550_mtd, partition_info, ARRAY_SIZE(partition_info));
1da177e4 LT	587
	588	return 0;
	589
	590	outio:
e0c7d767	591	iounmap((void *)p_nand);
61b03bd7	592
1da177e4	593	outmem:
e0c7d767	594	kfree(au1550_mtd);
1da177e4 LT	595	return retval;
	596	}
	597
ef6f0d1f	598	module_init(au1xxx_nand_init);
1da177e4 LT	599
	600	/*
	601	* Clean up routine
	602	*/
e0c7d767	603	static void __exit au1550_cleanup(void)
1da177e4	604	{
1da177e4	605	/* Release resources, unregister device */
e0c7d767	606	nand_release(au1550_mtd);
1da177e4 LT	607
1da177e4 LT	608	/* Free the MTD device structure */
e0c7d767	609	kfree(au1550_mtd);
1da177e4 LT	610
1da177e4 LT	611	/* Unmap */
e0c7d767	612	iounmap((void *)p_nand);
1da177e4	613	}
e0c7d767	614
1da177e4	615	module_exit(au1550_cleanup);
1da177e4 LT	616
	617	MODULE_LICENSE("GPL");
	618	MODULE_AUTHOR("Embedded Edge, LLC");
	619	MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");