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Commit | Line | Data |
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2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/interrupt.h> | |
7d5230ea DB |
22 | #include <linux/mutex.h> |
23 | ||
2f9f7628 ML |
24 | #include <linux/mtd/mtd.h> |
25 | #include <linux/mtd/partitions.h> | |
7d5230ea | 26 | |
2f9f7628 ML |
27 | #include <linux/spi/spi.h> |
28 | #include <linux/spi/flash.h> | |
29 | ||
2f9f7628 | 30 | |
2f9f7628 ML |
31 | #define FLASH_PAGESIZE 256 |
32 | ||
33 | /* Flash opcodes. */ | |
fa0a8c71 DB |
34 | #define OPCODE_WREN 0x06 /* Write enable */ |
35 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
2230b76b | 36 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
37 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
38 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
02d087db DW |
39 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
40 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ | |
41 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ | |
2f9f7628 ML |
42 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
43 | ||
44 | /* Status Register bits. */ | |
45 | #define SR_WIP 1 /* Write in progress */ | |
46 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 47 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
48 | #define SR_BP0 4 /* Block protect 0 */ |
49 | #define SR_BP1 8 /* Block protect 1 */ | |
50 | #define SR_BP2 0x10 /* Block protect 2 */ | |
51 | #define SR_SRWD 0x80 /* SR write protect */ | |
52 | ||
53 | /* Define max times to check status register before we give up. */ | |
54 | #define MAX_READY_WAIT_COUNT 100000 | |
2230b76b | 55 | #define CMD_SIZE 4 |
2f9f7628 | 56 | |
2230b76b BW |
57 | #ifdef CONFIG_M25PXX_USE_FAST_READ |
58 | #define OPCODE_READ OPCODE_FAST_READ | |
59 | #define FAST_READ_DUMMY_BYTE 1 | |
60 | #else | |
61 | #define OPCODE_READ OPCODE_NORM_READ | |
62 | #define FAST_READ_DUMMY_BYTE 0 | |
63 | #endif | |
2f9f7628 ML |
64 | |
65 | #ifdef CONFIG_MTD_PARTITIONS | |
66 | #define mtd_has_partitions() (1) | |
67 | #else | |
68 | #define mtd_has_partitions() (0) | |
69 | #endif | |
70 | ||
71 | /****************************************************************************/ | |
72 | ||
73 | struct m25p { | |
74 | struct spi_device *spi; | |
7d5230ea | 75 | struct mutex lock; |
2f9f7628 | 76 | struct mtd_info mtd; |
fa0a8c71 DB |
77 | unsigned partitioned:1; |
78 | u8 erase_opcode; | |
2230b76b | 79 | u8 command[CMD_SIZE + FAST_READ_DUMMY_BYTE]; |
2f9f7628 ML |
80 | }; |
81 | ||
82 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
83 | { | |
84 | return container_of(mtd, struct m25p, mtd); | |
85 | } | |
86 | ||
87 | /****************************************************************************/ | |
88 | ||
89 | /* | |
90 | * Internal helper functions | |
91 | */ | |
92 | ||
93 | /* | |
94 | * Read the status register, returning its value in the location | |
95 | * Return the status register value. | |
96 | * Returns negative if error occurred. | |
97 | */ | |
98 | static int read_sr(struct m25p *flash) | |
99 | { | |
100 | ssize_t retval; | |
101 | u8 code = OPCODE_RDSR; | |
102 | u8 val; | |
103 | ||
104 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
105 | ||
106 | if (retval < 0) { | |
107 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
108 | (int) retval); | |
109 | return retval; | |
110 | } | |
111 | ||
112 | return val; | |
113 | } | |
114 | ||
115 | ||
116 | /* | |
117 | * Set write enable latch with Write Enable command. | |
118 | * Returns negative if error occurred. | |
119 | */ | |
120 | static inline int write_enable(struct m25p *flash) | |
121 | { | |
122 | u8 code = OPCODE_WREN; | |
123 | ||
124 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
125 | } | |
126 | ||
127 | ||
128 | /* | |
129 | * Service routine to read status register until ready, or timeout occurs. | |
130 | * Returns non-zero if error. | |
131 | */ | |
132 | static int wait_till_ready(struct m25p *flash) | |
133 | { | |
134 | int count; | |
135 | int sr; | |
136 | ||
137 | /* one chip guarantees max 5 msec wait here after page writes, | |
138 | * but potentially three seconds (!) after page erase. | |
139 | */ | |
140 | for (count = 0; count < MAX_READY_WAIT_COUNT; count++) { | |
141 | if ((sr = read_sr(flash)) < 0) | |
142 | break; | |
143 | else if (!(sr & SR_WIP)) | |
144 | return 0; | |
145 | ||
146 | /* REVISIT sometimes sleeping would be best */ | |
147 | } | |
148 | ||
149 | return 1; | |
150 | } | |
151 | ||
152 | ||
153 | /* | |
154 | * Erase one sector of flash memory at offset ``offset'' which is any | |
155 | * address within the sector which should be erased. | |
156 | * | |
157 | * Returns 0 if successful, non-zero otherwise. | |
158 | */ | |
159 | static int erase_sector(struct m25p *flash, u32 offset) | |
160 | { | |
02d087db | 161 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", |
cb53b3b9 | 162 | flash->spi->dev.bus_id, __func__, |
fa0a8c71 | 163 | flash->mtd.erasesize / 1024, offset); |
2f9f7628 ML |
164 | |
165 | /* Wait until finished previous write command. */ | |
166 | if (wait_till_ready(flash)) | |
167 | return 1; | |
168 | ||
169 | /* Send write enable, then erase commands. */ | |
170 | write_enable(flash); | |
171 | ||
172 | /* Set up command buffer. */ | |
fa0a8c71 | 173 | flash->command[0] = flash->erase_opcode; |
2f9f7628 ML |
174 | flash->command[1] = offset >> 16; |
175 | flash->command[2] = offset >> 8; | |
176 | flash->command[3] = offset; | |
177 | ||
2230b76b | 178 | spi_write(flash->spi, flash->command, CMD_SIZE); |
2f9f7628 ML |
179 | |
180 | return 0; | |
181 | } | |
182 | ||
183 | /****************************************************************************/ | |
184 | ||
185 | /* | |
186 | * MTD implementation | |
187 | */ | |
188 | ||
189 | /* | |
190 | * Erase an address range on the flash chip. The address range may extend | |
191 | * one or more erase sectors. Return an error is there is a problem erasing. | |
192 | */ | |
193 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
194 | { | |
195 | struct m25p *flash = mtd_to_m25p(mtd); | |
196 | u32 addr,len; | |
197 | ||
19676ff0 | 198 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %d\n", |
cb53b3b9 | 199 | flash->spi->dev.bus_id, __func__, "at", |
2f9f7628 ML |
200 | (u32)instr->addr, instr->len); |
201 | ||
202 | /* sanity checks */ | |
203 | if (instr->addr + instr->len > flash->mtd.size) | |
204 | return -EINVAL; | |
205 | if ((instr->addr % mtd->erasesize) != 0 | |
206 | || (instr->len % mtd->erasesize) != 0) { | |
207 | return -EINVAL; | |
208 | } | |
209 | ||
210 | addr = instr->addr; | |
211 | len = instr->len; | |
212 | ||
7d5230ea | 213 | mutex_lock(&flash->lock); |
2f9f7628 | 214 | |
fa0a8c71 DB |
215 | /* REVISIT in some cases we could speed up erasing large regions |
216 | * by using OPCODE_SE instead of OPCODE_BE_4K | |
217 | */ | |
218 | ||
2f9f7628 ML |
219 | /* now erase those sectors */ |
220 | while (len) { | |
221 | if (erase_sector(flash, addr)) { | |
222 | instr->state = MTD_ERASE_FAILED; | |
7d5230ea | 223 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
224 | return -EIO; |
225 | } | |
226 | ||
227 | addr += mtd->erasesize; | |
228 | len -= mtd->erasesize; | |
229 | } | |
230 | ||
7d5230ea | 231 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
232 | |
233 | instr->state = MTD_ERASE_DONE; | |
234 | mtd_erase_callback(instr); | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | /* | |
240 | * Read an address range from the flash chip. The address range | |
241 | * may be any size provided it is within the physical boundaries. | |
242 | */ | |
243 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
244 | size_t *retlen, u_char *buf) | |
245 | { | |
246 | struct m25p *flash = mtd_to_m25p(mtd); | |
247 | struct spi_transfer t[2]; | |
248 | struct spi_message m; | |
249 | ||
250 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
cb53b3b9 | 251 | flash->spi->dev.bus_id, __func__, "from", |
2f9f7628 ML |
252 | (u32)from, len); |
253 | ||
254 | /* sanity checks */ | |
255 | if (!len) | |
256 | return 0; | |
257 | ||
258 | if (from + len > flash->mtd.size) | |
259 | return -EINVAL; | |
260 | ||
8275c642 VW |
261 | spi_message_init(&m); |
262 | memset(t, 0, (sizeof t)); | |
263 | ||
2230b76b BW |
264 | /* NOTE: |
265 | * OPCODE_FAST_READ (if available) is faster. | |
266 | * Should add 1 byte DUMMY_BYTE. | |
267 | */ | |
8275c642 | 268 | t[0].tx_buf = flash->command; |
2230b76b | 269 | t[0].len = CMD_SIZE + FAST_READ_DUMMY_BYTE; |
8275c642 VW |
270 | spi_message_add_tail(&t[0], &m); |
271 | ||
272 | t[1].rx_buf = buf; | |
273 | t[1].len = len; | |
274 | spi_message_add_tail(&t[1], &m); | |
275 | ||
276 | /* Byte count starts at zero. */ | |
277 | if (retlen) | |
278 | *retlen = 0; | |
279 | ||
7d5230ea | 280 | mutex_lock(&flash->lock); |
2f9f7628 ML |
281 | |
282 | /* Wait till previous write/erase is done. */ | |
283 | if (wait_till_ready(flash)) { | |
284 | /* REVISIT status return?? */ | |
7d5230ea | 285 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
286 | return 1; |
287 | } | |
288 | ||
fa0a8c71 DB |
289 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
290 | * clocks; and at this writing, every chip this driver handles | |
291 | * supports that opcode. | |
292 | */ | |
2f9f7628 ML |
293 | |
294 | /* Set up the write data buffer. */ | |
295 | flash->command[0] = OPCODE_READ; | |
296 | flash->command[1] = from >> 16; | |
297 | flash->command[2] = from >> 8; | |
298 | flash->command[3] = from; | |
299 | ||
2f9f7628 ML |
300 | spi_sync(flash->spi, &m); |
301 | ||
2230b76b | 302 | *retlen = m.actual_length - CMD_SIZE - FAST_READ_DUMMY_BYTE; |
2f9f7628 | 303 | |
7d5230ea | 304 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
305 | |
306 | return 0; | |
307 | } | |
308 | ||
309 | /* | |
310 | * Write an address range to the flash chip. Data must be written in | |
311 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
312 | * it is within the physical boundaries. | |
313 | */ | |
314 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
315 | size_t *retlen, const u_char *buf) | |
316 | { | |
317 | struct m25p *flash = mtd_to_m25p(mtd); | |
318 | u32 page_offset, page_size; | |
319 | struct spi_transfer t[2]; | |
320 | struct spi_message m; | |
321 | ||
322 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
cb53b3b9 | 323 | flash->spi->dev.bus_id, __func__, "to", |
2f9f7628 ML |
324 | (u32)to, len); |
325 | ||
326 | if (retlen) | |
327 | *retlen = 0; | |
328 | ||
329 | /* sanity checks */ | |
330 | if (!len) | |
331 | return(0); | |
332 | ||
333 | if (to + len > flash->mtd.size) | |
334 | return -EINVAL; | |
335 | ||
8275c642 VW |
336 | spi_message_init(&m); |
337 | memset(t, 0, (sizeof t)); | |
338 | ||
339 | t[0].tx_buf = flash->command; | |
2230b76b | 340 | t[0].len = CMD_SIZE; |
8275c642 VW |
341 | spi_message_add_tail(&t[0], &m); |
342 | ||
343 | t[1].tx_buf = buf; | |
344 | spi_message_add_tail(&t[1], &m); | |
345 | ||
7d5230ea | 346 | mutex_lock(&flash->lock); |
2f9f7628 ML |
347 | |
348 | /* Wait until finished previous write command. */ | |
bc018863 CG |
349 | if (wait_till_ready(flash)) { |
350 | mutex_unlock(&flash->lock); | |
2f9f7628 | 351 | return 1; |
bc018863 | 352 | } |
2f9f7628 ML |
353 | |
354 | write_enable(flash); | |
355 | ||
2f9f7628 ML |
356 | /* Set up the opcode in the write buffer. */ |
357 | flash->command[0] = OPCODE_PP; | |
358 | flash->command[1] = to >> 16; | |
359 | flash->command[2] = to >> 8; | |
360 | flash->command[3] = to; | |
361 | ||
2f9f7628 ML |
362 | /* what page do we start with? */ |
363 | page_offset = to % FLASH_PAGESIZE; | |
364 | ||
365 | /* do all the bytes fit onto one page? */ | |
366 | if (page_offset + len <= FLASH_PAGESIZE) { | |
2f9f7628 ML |
367 | t[1].len = len; |
368 | ||
369 | spi_sync(flash->spi, &m); | |
370 | ||
2230b76b | 371 | *retlen = m.actual_length - CMD_SIZE; |
2f9f7628 ML |
372 | } else { |
373 | u32 i; | |
374 | ||
375 | /* the size of data remaining on the first page */ | |
376 | page_size = FLASH_PAGESIZE - page_offset; | |
377 | ||
2f9f7628 ML |
378 | t[1].len = page_size; |
379 | spi_sync(flash->spi, &m); | |
380 | ||
2230b76b | 381 | *retlen = m.actual_length - CMD_SIZE; |
2f9f7628 ML |
382 | |
383 | /* write everything in PAGESIZE chunks */ | |
384 | for (i = page_size; i < len; i += page_size) { | |
385 | page_size = len - i; | |
386 | if (page_size > FLASH_PAGESIZE) | |
387 | page_size = FLASH_PAGESIZE; | |
388 | ||
389 | /* write the next page to flash */ | |
390 | flash->command[1] = (to + i) >> 16; | |
391 | flash->command[2] = (to + i) >> 8; | |
392 | flash->command[3] = (to + i); | |
393 | ||
394 | t[1].tx_buf = buf + i; | |
395 | t[1].len = page_size; | |
396 | ||
397 | wait_till_ready(flash); | |
398 | ||
399 | write_enable(flash); | |
400 | ||
401 | spi_sync(flash->spi, &m); | |
402 | ||
7111763d | 403 | if (retlen) |
2230b76b | 404 | *retlen += m.actual_length - CMD_SIZE; |
7d5230ea DB |
405 | } |
406 | } | |
2f9f7628 | 407 | |
7d5230ea | 408 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
409 | |
410 | return 0; | |
411 | } | |
412 | ||
413 | ||
414 | /****************************************************************************/ | |
415 | ||
416 | /* | |
417 | * SPI device driver setup and teardown | |
418 | */ | |
419 | ||
420 | struct flash_info { | |
421 | char *name; | |
fa0a8c71 DB |
422 | |
423 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has | |
424 | * a high byte of zero plus three data bytes: the manufacturer id, | |
425 | * then a two byte device id. | |
426 | */ | |
427 | u32 jedec_id; | |
428 | ||
429 | /* The size listed here is what works with OPCODE_SE, which isn't | |
430 | * necessarily called a "sector" by the vendor. | |
431 | */ | |
2f9f7628 | 432 | unsigned sector_size; |
fa0a8c71 DB |
433 | u16 n_sectors; |
434 | ||
435 | u16 flags; | |
436 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
2f9f7628 ML |
437 | }; |
438 | ||
fa0a8c71 DB |
439 | |
440 | /* NOTE: double check command sets and memory organization when you add | |
441 | * more flash chips. This current list focusses on newer chips, which | |
442 | * have been converging on command sets which including JEDEC ID. | |
443 | */ | |
2f9f7628 | 444 | static struct flash_info __devinitdata m25p_data [] = { |
fa0a8c71 DB |
445 | |
446 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ | |
447 | { "at25fs010", 0x1f6601, 32 * 1024, 4, SECT_4K, }, | |
448 | { "at25fs040", 0x1f6604, 64 * 1024, 8, SECT_4K, }, | |
449 | ||
450 | { "at25df041a", 0x1f4401, 64 * 1024, 8, SECT_4K, }, | |
3887ed52 | 451 | { "at25df641", 0x1f4800, 64 * 1024, 128, SECT_4K, }, |
fa0a8c71 DB |
452 | |
453 | { "at26f004", 0x1f0400, 64 * 1024, 8, SECT_4K, }, | |
454 | { "at26df081a", 0x1f4501, 64 * 1024, 16, SECT_4K, }, | |
455 | { "at26df161a", 0x1f4601, 64 * 1024, 32, SECT_4K, }, | |
456 | { "at26df321", 0x1f4701, 64 * 1024, 64, SECT_4K, }, | |
457 | ||
458 | /* Spansion -- single (large) sector size only, at least | |
459 | * for the chips listed here (without boot sectors). | |
460 | */ | |
461 | { "s25sl004a", 0x010212, 64 * 1024, 8, }, | |
462 | { "s25sl008a", 0x010213, 64 * 1024, 16, }, | |
463 | { "s25sl016a", 0x010214, 64 * 1024, 32, }, | |
464 | { "s25sl032a", 0x010215, 64 * 1024, 64, }, | |
465 | { "s25sl064a", 0x010216, 64 * 1024, 128, }, | |
466 | ||
467 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
468 | { "sst25vf040b", 0xbf258d, 64 * 1024, 8, SECT_4K, }, | |
469 | { "sst25vf080b", 0xbf258e, 64 * 1024, 16, SECT_4K, }, | |
470 | { "sst25vf016b", 0xbf2541, 64 * 1024, 32, SECT_4K, }, | |
471 | { "sst25vf032b", 0xbf254a, 64 * 1024, 64, SECT_4K, }, | |
472 | ||
473 | /* ST Microelectronics -- newer production may have feature updates */ | |
474 | { "m25p05", 0x202010, 32 * 1024, 2, }, | |
475 | { "m25p10", 0x202011, 32 * 1024, 4, }, | |
476 | { "m25p20", 0x202012, 64 * 1024, 4, }, | |
477 | { "m25p40", 0x202013, 64 * 1024, 8, }, | |
478 | { "m25p80", 0, 64 * 1024, 16, }, | |
479 | { "m25p16", 0x202015, 64 * 1024, 32, }, | |
480 | { "m25p32", 0x202016, 64 * 1024, 64, }, | |
481 | { "m25p64", 0x202017, 64 * 1024, 128, }, | |
482 | { "m25p128", 0x202018, 256 * 1024, 64, }, | |
483 | ||
484 | { "m45pe80", 0x204014, 64 * 1024, 16, }, | |
485 | { "m45pe16", 0x204015, 64 * 1024, 32, }, | |
486 | ||
487 | { "m25pe80", 0x208014, 64 * 1024, 16, }, | |
488 | { "m25pe16", 0x208015, 64 * 1024, 32, SECT_4K, }, | |
489 | ||
02d087db | 490 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
fa0a8c71 DB |
491 | { "w25x10", 0xef3011, 64 * 1024, 2, SECT_4K, }, |
492 | { "w25x20", 0xef3012, 64 * 1024, 4, SECT_4K, }, | |
493 | { "w25x40", 0xef3013, 64 * 1024, 8, SECT_4K, }, | |
494 | { "w25x80", 0xef3014, 64 * 1024, 16, SECT_4K, }, | |
495 | { "w25x16", 0xef3015, 64 * 1024, 32, SECT_4K, }, | |
496 | { "w25x32", 0xef3016, 64 * 1024, 64, SECT_4K, }, | |
497 | { "w25x64", 0xef3017, 64 * 1024, 128, SECT_4K, }, | |
2f9f7628 ML |
498 | }; |
499 | ||
fa0a8c71 DB |
500 | static struct flash_info *__devinit jedec_probe(struct spi_device *spi) |
501 | { | |
502 | int tmp; | |
503 | u8 code = OPCODE_RDID; | |
504 | u8 id[3]; | |
505 | u32 jedec; | |
506 | struct flash_info *info; | |
507 | ||
508 | /* JEDEC also defines an optional "extended device information" | |
509 | * string for after vendor-specific data, after the three bytes | |
510 | * we use here. Supporting some chips might require using it. | |
511 | */ | |
512 | tmp = spi_write_then_read(spi, &code, 1, id, 3); | |
513 | if (tmp < 0) { | |
514 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
515 | spi->dev.bus_id, tmp); | |
516 | return NULL; | |
517 | } | |
518 | jedec = id[0]; | |
519 | jedec = jedec << 8; | |
520 | jedec |= id[1]; | |
521 | jedec = jedec << 8; | |
522 | jedec |= id[2]; | |
523 | ||
524 | for (tmp = 0, info = m25p_data; | |
525 | tmp < ARRAY_SIZE(m25p_data); | |
526 | tmp++, info++) { | |
527 | if (info->jedec_id == jedec) | |
528 | return info; | |
529 | } | |
530 | dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); | |
531 | return NULL; | |
532 | } | |
533 | ||
534 | ||
2f9f7628 ML |
535 | /* |
536 | * board specific setup should have ensured the SPI clock used here | |
537 | * matches what the READ command supports, at least until this driver | |
538 | * understands FAST_READ (for clocks over 25 MHz). | |
539 | */ | |
540 | static int __devinit m25p_probe(struct spi_device *spi) | |
541 | { | |
542 | struct flash_platform_data *data; | |
543 | struct m25p *flash; | |
544 | struct flash_info *info; | |
545 | unsigned i; | |
546 | ||
547 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
548 | * well as how this board partitions it. If we don't have |
549 | * a chip ID, try the JEDEC id commands; they'll work for most | |
550 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
551 | */ |
552 | data = spi->dev.platform_data; | |
fa0a8c71 DB |
553 | if (data && data->type) { |
554 | for (i = 0, info = m25p_data; | |
555 | i < ARRAY_SIZE(m25p_data); | |
556 | i++, info++) { | |
557 | if (strcmp(data->type, info->name) == 0) | |
558 | break; | |
559 | } | |
2f9f7628 | 560 | |
fa0a8c71 DB |
561 | /* unrecognized chip? */ |
562 | if (i == ARRAY_SIZE(m25p_data)) { | |
563 | DEBUG(MTD_DEBUG_LEVEL0, "%s: unrecognized id %s\n", | |
564 | spi->dev.bus_id, data->type); | |
565 | info = NULL; | |
566 | ||
567 | /* recognized; is that chip really what's there? */ | |
568 | } else if (info->jedec_id) { | |
569 | struct flash_info *chip = jedec_probe(spi); | |
570 | ||
571 | if (!chip || chip != info) { | |
572 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
573 | chip ? chip->name : "UNKNOWN", | |
574 | info->name); | |
575 | info = NULL; | |
576 | } | |
577 | } | |
578 | } else | |
579 | info = jedec_probe(spi); | |
580 | ||
581 | if (!info) | |
2f9f7628 | 582 | return -ENODEV; |
2f9f7628 | 583 | |
e94b1766 | 584 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
585 | if (!flash) |
586 | return -ENOMEM; | |
587 | ||
588 | flash->spi = spi; | |
7d5230ea | 589 | mutex_init(&flash->lock); |
2f9f7628 ML |
590 | dev_set_drvdata(&spi->dev, flash); |
591 | ||
fa0a8c71 | 592 | if (data && data->name) |
2f9f7628 ML |
593 | flash->mtd.name = data->name; |
594 | else | |
595 | flash->mtd.name = spi->dev.bus_id; | |
596 | ||
597 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 598 | flash->mtd.writesize = 1; |
2f9f7628 ML |
599 | flash->mtd.flags = MTD_CAP_NORFLASH; |
600 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
601 | flash->mtd.erase = m25p80_erase; |
602 | flash->mtd.read = m25p80_read; | |
603 | flash->mtd.write = m25p80_write; | |
604 | ||
fa0a8c71 DB |
605 | /* prefer "small sector" erase if possible */ |
606 | if (info->flags & SECT_4K) { | |
607 | flash->erase_opcode = OPCODE_BE_4K; | |
608 | flash->mtd.erasesize = 4096; | |
609 | } else { | |
610 | flash->erase_opcode = OPCODE_SE; | |
611 | flash->mtd.erasesize = info->sector_size; | |
612 | } | |
613 | ||
2f9f7628 ML |
614 | dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, |
615 | flash->mtd.size / 1024); | |
616 | ||
617 | DEBUG(MTD_DEBUG_LEVEL2, | |
02d087db DW |
618 | "mtd .name = %s, .size = 0x%.8x (%uMiB) " |
619 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
2f9f7628 ML |
620 | flash->mtd.name, |
621 | flash->mtd.size, flash->mtd.size / (1024*1024), | |
622 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, | |
623 | flash->mtd.numeraseregions); | |
624 | ||
625 | if (flash->mtd.numeraseregions) | |
626 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
627 | DEBUG(MTD_DEBUG_LEVEL2, | |
628 | "mtd.eraseregions[%d] = { .offset = 0x%.8x, " | |
02d087db | 629 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 ML |
630 | ".numblocks = %d }\n", |
631 | i, flash->mtd.eraseregions[i].offset, | |
632 | flash->mtd.eraseregions[i].erasesize, | |
633 | flash->mtd.eraseregions[i].erasesize / 1024, | |
634 | flash->mtd.eraseregions[i].numblocks); | |
635 | ||
636 | ||
637 | /* partitions should match sector boundaries; and it may be good to | |
638 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
639 | */ | |
640 | if (mtd_has_partitions()) { | |
641 | struct mtd_partition *parts = NULL; | |
642 | int nr_parts = 0; | |
643 | ||
644 | #ifdef CONFIG_MTD_CMDLINE_PARTS | |
645 | static const char *part_probes[] = { "cmdlinepart", NULL, }; | |
646 | ||
647 | nr_parts = parse_mtd_partitions(&flash->mtd, | |
648 | part_probes, &parts, 0); | |
649 | #endif | |
650 | ||
651 | if (nr_parts <= 0 && data && data->parts) { | |
652 | parts = data->parts; | |
653 | nr_parts = data->nr_parts; | |
654 | } | |
655 | ||
656 | if (nr_parts > 0) { | |
fa0a8c71 | 657 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 ML |
658 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
659 | "{.name = %s, .offset = 0x%.8x, " | |
02d087db | 660 | ".size = 0x%.8x (%uKiB) }\n", |
fa0a8c71 DB |
661 | i, parts[i].name, |
662 | parts[i].offset, | |
663 | parts[i].size, | |
664 | parts[i].size / 1024); | |
2f9f7628 ML |
665 | } |
666 | flash->partitioned = 1; | |
667 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
668 | } | |
669 | } else if (data->nr_parts) | |
670 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", | |
671 | data->nr_parts, data->name); | |
672 | ||
673 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
674 | } | |
675 | ||
676 | ||
677 | static int __devexit m25p_remove(struct spi_device *spi) | |
678 | { | |
679 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
680 | int status; | |
681 | ||
682 | /* Clean up MTD stuff. */ | |
683 | if (mtd_has_partitions() && flash->partitioned) | |
684 | status = del_mtd_partitions(&flash->mtd); | |
685 | else | |
686 | status = del_mtd_device(&flash->mtd); | |
687 | if (status == 0) | |
688 | kfree(flash); | |
689 | return 0; | |
690 | } | |
691 | ||
692 | ||
693 | static struct spi_driver m25p80_driver = { | |
694 | .driver = { | |
695 | .name = "m25p80", | |
696 | .bus = &spi_bus_type, | |
697 | .owner = THIS_MODULE, | |
698 | }, | |
699 | .probe = m25p_probe, | |
700 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
701 | |
702 | /* REVISIT: many of these chips have deep power-down modes, which | |
703 | * should clearly be entered on suspend() to minimize power use. | |
704 | * And also when they're otherwise idle... | |
705 | */ | |
2f9f7628 ML |
706 | }; |
707 | ||
708 | ||
709 | static int m25p80_init(void) | |
710 | { | |
711 | return spi_register_driver(&m25p80_driver); | |
712 | } | |
713 | ||
714 | ||
715 | static void m25p80_exit(void) | |
716 | { | |
717 | spi_unregister_driver(&m25p80_driver); | |
718 | } | |
719 | ||
720 | ||
721 | module_init(m25p80_init); | |
722 | module_exit(m25p80_exit); | |
723 | ||
724 | MODULE_LICENSE("GPL"); | |
725 | MODULE_AUTHOR("Mike Lavender"); | |
726 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |