[net-next-2.6.git] / drivers / mmc / pxamci.c

/*
 *  linux/drivers/mmc/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *	1 and 3 byte data transfers not supported
 *	max block length up to 1023
 */
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mmc/host.h>
#include <linux/mmc/protocol.h>

#include <asm/dma.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>

#include "pxamci.h"

#ifdef CONFIG_MMC_DEBUG
#define DBG(x...)	printk(KERN_DEBUG x)
#else
#define DBG(x...)	do { } while (0)
#endif

#define DRIVER_NAME	"pxa2xx-mci"

#define NR_SG	1

struct pxamci_host {
	struct mmc_host		*mmc;
	spinlock_t		lock;
	struct resource		*res;
	void __iomem		*base;
	int			irq;
	int			dma;
	unsigned int		clkrt;
	unsigned int		cmdat;
	unsigned int		imask;
	unsigned int		power_mode;
	struct pxamci_platform_data *pdata;

	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;

	dma_addr_t		sg_dma;
	struct pxa_dma_desc	*sg_cpu;
	unsigned int		dma_len;

	unsigned int		dma_dir;
};

static inline unsigned int ns_to_clocks(unsigned int ns)
{
	return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
}

static void pxamci_stop_clock(struct pxamci_host *host)
{
	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
		unsigned long timeout = 10000;
		unsigned int v;

		writel(STOP_CLOCK, host->base + MMC_STRPCL);

		do {
			v = readl(host->base + MMC_STAT);
			if (!(v & STAT_CLK_EN))
				break;
			udelay(1);
		} while (timeout--);

		if (v & STAT_CLK_EN)
			dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	}
}

static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask &= ~mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask |= mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned int timeout;
	u32 dcmd;
	int i;

	host->data = data;

	if (data->flags & MMC_DATA_STREAM)
		nob = 0xffff;

	writel(nob, host->base + MMC_NOB);
	writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);

	timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
	writel((timeout + 255) / 256, host->base + MMC_RDTO);

	if (data->flags & MMC_DATA_READ) {
		host->dma_dir = DMA_FROM_DEVICE;
		dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
		DRCMRTXMMC = 0;
		DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
	} else {
		host->dma_dir = DMA_TO_DEVICE;
		dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
		DRCMRRXMMC = 0;
		DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
	}

	dcmd |= DCMD_BURST32 | DCMD_WIDTH1;

	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
				   host->dma_dir);

	for (i = 0; i < host->dma_len; i++) {
		if (data->flags & MMC_DATA_READ) {
			host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
			host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
		} else {
			host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
			host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
		}
		host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
		host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
					sizeof(struct pxa_dma_desc);
	}
	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	wmb();

	DDADR(host->dma) = host->sg_dma;
	DCSR(host->dma) = DCSR_RUN;
}

static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
	WARN_ON(host->cmd != NULL);
	host->cmd = cmd;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdat |= CMDAT_BUSY;

	switch (cmd->flags & (MMC_RSP_MASK | MMC_RSP_CRC)) {
	case MMC_RSP_SHORT | MMC_RSP_CRC:
		cmdat |= CMDAT_RESP_SHORT;
		break;
	case MMC_RSP_SHORT:
		cmdat |= CMDAT_RESP_R3;
		break;
	case MMC_RSP_LONG | MMC_RSP_CRC:
		cmdat |= CMDAT_RESP_R2;
		break;
	default:
		break;
	}

	writel(cmd->opcode, host->base + MMC_CMD);
	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	writel(cmdat, host->base + MMC_CMDAT);
	writel(host->clkrt, host->base + MMC_CLKRT);

	writel(START_CLOCK, host->base + MMC_STRPCL);

	pxamci_enable_irq(host, END_CMD_RES);
}

static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
	DBG("PXAMCI: request done\n");
	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;
	mmc_request_done(host->mmc, mrq);
}

static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_command *cmd = host->cmd;
	int i;
	u32 v;

	if (!cmd)
		return 0;

	host->cmd = NULL;

	/*
	 * Did I mention this is Sick.  We always need to
	 * discard the upper 8 bits of the first 16-bit word.
	 */
	v = readl(host->base + MMC_RES) & 0xffff;
	for (i = 0; i < 4; i++) {
		u32 w1 = readl(host->base + MMC_RES) & 0xffff;
		u32 w2 = readl(host->base + MMC_RES) & 0xffff;
		cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
		v = w2;
	}

	if (stat & STAT_TIME_OUT_RESPONSE) {
		cmd->error = MMC_ERR_TIMEOUT;
	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
		/*
		 * workaround for erratum #42:
		 * Intel PXA27x Family Processor Specification Update Rev 001
		 */
		if (cmd->opcode == MMC_ALL_SEND_CID ||
		    cmd->opcode == MMC_SEND_CSD ||
		    cmd->opcode == MMC_SEND_CID) {
			/* a bogus CRC error can appear if the msb of
			   the 15 byte response is a one */
			if ((cmd->resp[0] & 0x80000000) == 0)
				cmd->error = MMC_ERR_BADCRC;
		} else {
			DBG("ignoring CRC from command %d - *risky*\n",cmd->opcode);
		}
#else
		cmd->error = MMC_ERR_BADCRC;
#endif
	}

	pxamci_disable_irq(host, END_CMD_RES);
	if (host->data && cmd->error == MMC_ERR_NONE) {
		pxamci_enable_irq(host, DATA_TRAN_DONE);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_data *data = host->data;

	if (!data)
		return 0;

	DCSR(host->dma) = 0;
	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
		     host->dma_dir);

	if (stat & STAT_READ_TIME_OUT)
		data->error = MMC_ERR_TIMEOUT;
	else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
		data->error = MMC_ERR_BADCRC;

	/*
	 * There appears to be a hardware design bug here.  There seems to
	 * be no way to find out how much data was transferred to the card.
	 * This means that if there was an error on any block, we mark all
	 * data blocks as being in error.
	 */
	if (data->error == MMC_ERR_NONE)
		data->bytes_xfered = data->blocks << data->blksz_bits;
	else
		data->bytes_xfered = 0;

	pxamci_disable_irq(host, DATA_TRAN_DONE);

	host->data = NULL;
	if (host->mrq->stop && data->error == MMC_ERR_NONE) {
		pxamci_stop_clock(host);
		pxamci_start_cmd(host, host->mrq->stop, 0);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
{
	struct pxamci_host *host = devid;
	unsigned int ireg;
	int handled = 0;

	ireg = readl(host->base + MMC_I_REG);

	DBG("PXAMCI: irq %08x\n", ireg);

	if (ireg) {
		unsigned stat = readl(host->base + MMC_STAT);

		DBG("PXAMCI: stat %08x\n", stat);

		if (ireg & END_CMD_RES)
			handled |= pxamci_cmd_done(host, stat);
		if (ireg & DATA_TRAN_DONE)
			handled |= pxamci_data_done(host, stat);
	}

	return IRQ_RETVAL(handled);
}

static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct pxamci_host *host = mmc_priv(mmc);
	unsigned int cmdat;

	WARN_ON(host->mrq != NULL);

	host->mrq = mrq;

	pxamci_stop_clock(host);

	cmdat = host->cmdat;
	host->cmdat &= ~CMDAT_INIT;

	if (mrq->data) {
		pxamci_setup_data(host, mrq->data);

		cmdat &= ~CMDAT_BUSY;
		cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
		if (mrq->data->flags & MMC_DATA_WRITE)
			cmdat |= CMDAT_WRITE;

		if (mrq->data->flags & MMC_DATA_STREAM)
			cmdat |= CMDAT_STREAM;
	}

	pxamci_start_cmd(host, mrq->cmd, cmdat);
}

static int pxamci_get_ro(struct mmc_host *mmc)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (host->pdata && host->pdata->get_ro)
		return host->pdata->get_ro(mmc->dev);
	/* Host doesn't support read only detection so assume writeable */
	return 0;
}

static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct pxamci_host *host = mmc_priv(mmc);

	DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
	    ios->clock, ios->power_mode, ios->vdd / 100,
	    ios->vdd % 100);

	if (ios->clock) {
		unsigned int clk = CLOCKRATE / ios->clock;
		if (CLOCKRATE / clk > ios->clock)
			clk <<= 1;
		host->clkrt = fls(clk) - 1;
		pxa_set_cken(CKEN12_MMC, 1);

		/*
		 * we write clkrt on the next command
		 */
	} else {
		pxamci_stop_clock(host);
		pxa_set_cken(CKEN12_MMC, 0);
	}

	if (host->power_mode != ios->power_mode) {
		host->power_mode = ios->power_mode;

		if (host->pdata && host->pdata->setpower)
			host->pdata->setpower(mmc->dev, ios->vdd);

		if (ios->power_mode == MMC_POWER_ON)
			host->cmdat |= CMDAT_INIT;
	}

	DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
	    host->clkrt, host->cmdat);
}

static struct mmc_host_ops pxamci_ops = {
	.request	= pxamci_request,
	.get_ro		= pxamci_get_ro,
	.set_ios	= pxamci_set_ios,
};

static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
{
	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
}

static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
{
	struct pxamci_host *host = mmc_priv(devid);

	mmc_detect_change(devid, host->pdata->detect_delay);
	return IRQ_HANDLED;
}

static int pxamci_probe(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct mmc_host *mmc;
	struct pxamci_host *host = NULL;
	struct resource *r;
	int ret, irq;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (!r || irq == NO_IRQ)
		return -ENXIO;

	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	if (!r)
		return -EBUSY;

	mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto out;
	}

	mmc->ops = &pxamci_ops;
	mmc->f_min = CLOCKRATE_MIN;
	mmc->f_max = CLOCKRATE_MAX;

	/*
	 * We can do SG-DMA, but we don't because we never know how much
	 * data we successfully wrote to the card.
	 */
	mmc->max_phys_segs = NR_SG;

	/*
	 * Our hardware DMA can handle a maximum of one page per SG entry.
	 */
	mmc->max_seg_size = PAGE_SIZE;

	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->dma = -1;
	host->pdata = pdev->dev.platform_data;
	mmc->ocr_avail = host->pdata ?
			 host->pdata->ocr_mask :
			 MMC_VDD_32_33|MMC_VDD_33_34;

	host->sg_cpu = dma_alloc_coherent(dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	if (!host->sg_cpu) {
		ret = -ENOMEM;
		goto out;
	}

	spin_lock_init(&host->lock);
	host->res = r;
	host->irq = irq;
	host->imask = MMC_I_MASK_ALL;

	host->base = ioremap(r->start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto out;
	}

	/*
	 * Ensure that the host controller is shut down, and setup
	 * with our defaults.
	 */
	pxamci_stop_clock(host);
	writel(0, host->base + MMC_SPI);
	writel(64, host->base + MMC_RESTO);
	writel(host->imask, host->base + MMC_I_MASK);

	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
				    pxamci_dma_irq, host);
	if (host->dma < 0) {
		ret = -EBUSY;
		goto out;
	}

	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	if (ret)
		goto out;

	dev_set_drvdata(dev, mmc);

	if (host->pdata && host->pdata->init)
		host->pdata->init(dev, pxamci_detect_irq, mmc);

	mmc_add_host(mmc);

	return 0;

 out:
	if (host) {
		if (host->dma >= 0)
			pxa_free_dma(host->dma);
		if (host->base)
			iounmap(host->base);
		if (host->sg_cpu)
			dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	}
	if (mmc)
		mmc_free_host(mmc);
	release_resource(r);
	return ret;
}

static int pxamci_remove(struct device *dev)
{
	struct mmc_host *mmc = dev_get_drvdata(dev);

	dev_set_drvdata(dev, NULL);

	if (mmc) {
		struct pxamci_host *host = mmc_priv(mmc);

		if (host->pdata && host->pdata->exit)
			host->pdata->exit(dev, mmc);

		mmc_remove_host(mmc);

		pxamci_stop_clock(host);
		writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
		       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
		       host->base + MMC_I_MASK);

		DRCMRRXMMC = 0;
		DRCMRTXMMC = 0;

		free_irq(host->irq, host);
		pxa_free_dma(host->dma);
		iounmap(host->base);
		dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);

		release_resource(host->res);

		mmc_free_host(mmc);
	}
	return 0;
}

#ifdef CONFIG_PM
static int pxamci_suspend(struct device *dev, pm_message_t state, u32 level)
{
	struct mmc_host *mmc = dev_get_drvdata(dev);
	int ret = 0;

	if (mmc && level == SUSPEND_DISABLE)
		ret = mmc_suspend_host(mmc, state);

	return ret;
}

static int pxamci_resume(struct device *dev, u32 level)
{
	struct mmc_host *mmc = dev_get_drvdata(dev);
	int ret = 0;

	if (mmc && level == RESUME_ENABLE)
		ret = mmc_resume_host(mmc);

	return ret;
}
#else
#define pxamci_suspend	NULL
#define pxamci_resume	NULL
#endif

static struct device_driver pxamci_driver = {
	.name		= DRIVER_NAME,
	.bus		= &platform_bus_type,
	.probe		= pxamci_probe,
	.remove		= pxamci_remove,
	.suspend	= pxamci_suspend,
	.resume		= pxamci_resume,
};

static int __init pxamci_init(void)
{
	return driver_register(&pxamci_driver);
}

static void __exit pxamci_exit(void)
{
	driver_unregister(&pxamci_driver);
}

module_init(pxamci_init);
module_exit(pxamci_exit);

MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/mmc/pxa.c - PXA MMCI driver
	3	*
	4	* Copyright (C) 2003 Russell King, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This hardware is really sick:
	11	* - No way to clear interrupts.
	12	* - Have to turn off the clock whenever we touch the device.
	13	* - Doesn't tell you how many data blocks were transferred.
	14	* Yuck!
	15	*
	16	* 1 and 3 byte data transfers not supported
	17	* max block length up to 1023
	18	*/
	19	#include <linux/config.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/ioport.h>
	23	#include <linux/device.h>
	24	#include <linux/delay.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/mmc/host.h>
	28	#include <linux/mmc/protocol.h>
	29
	30	#include <asm/dma.h>
	31	#include <asm/io.h>
	32	#include <asm/irq.h>
	33	#include <asm/scatterlist.h>
	34	#include <asm/sizes.h>
	35
	36	#include <asm/arch/pxa-regs.h>
	37	#include <asm/arch/mmc.h>
	38
	39	#include "pxamci.h"
	40
	41	#ifdef CONFIG_MMC_DEBUG
	42	#define DBG(x...) printk(KERN_DEBUG x)
	43	#else
	44	#define DBG(x...) do { } while (0)
	45	#endif
	46
	47	#define DRIVER_NAME "pxa2xx-mci"
	48
	49	#define NR_SG 1
	50
	51	struct pxamci_host {
	52	struct mmc_host *mmc;
	53	spinlock_t lock;
	54	struct resource *res;
	55	void __iomem *base;
	56	int irq;
	57	int dma;
	58	unsigned int clkrt;
	59	unsigned int cmdat;
	60	unsigned int imask;
	61	unsigned int power_mode;
	62	struct pxamci_platform_data *pdata;
	63
	64	struct mmc_request *mrq;
65	struct mmc_command *cmd;
66	struct mmc_data *data;
67
68	dma_addr_t sg_dma;
69	struct pxa_dma_desc *sg_cpu;
70	unsigned int dma_len;
71
72	unsigned int dma_dir;
73	};
74
75	static inline unsigned int ns_to_clocks(unsigned int ns)
76	{
77	return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
78	}
79
80	static void pxamci_stop_clock(struct pxamci_host *host)
81	{
82	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
83	unsigned long timeout = 10000;
84	unsigned int v;
85
86	writel(STOP_CLOCK, host->base + MMC_STRPCL);
87
88	do {
89	v = readl(host->base + MMC_STAT);
90	if (!(v & STAT_CLK_EN))
91	break;
92	udelay(1);
93	} while (timeout--);
94
95	if (v & STAT_CLK_EN)
96	dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
97	}
98	}
99
100	static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
101	{
102	unsigned long flags;
103
104	spin_lock_irqsave(&host->lock, flags);
105	host->imask &= ~mask;
106	writel(host->imask, host->base + MMC_I_MASK);
107	spin_unlock_irqrestore(&host->lock, flags);
108	}
109
110	static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
111	{
112	unsigned long flags;
113
114	spin_lock_irqsave(&host->lock, flags);
115	host->imask \|= mask;
116	writel(host->imask, host->base + MMC_I_MASK);
117	spin_unlock_irqrestore(&host->lock, flags);
118	}
119
120	static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)
121	{
122	unsigned int nob = data->blocks;
123	unsigned int timeout;
124	u32 dcmd;
125	int i;
126
127	host->data = data;
128
129	if (data->flags & MMC_DATA_STREAM)
130	nob = 0xffff;
131
132	writel(nob, host->base + MMC_NOB);
133	writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
134
135	timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
136	writel((timeout + 255) / 256, host->base + MMC_RDTO);
137
138	if (data->flags & MMC_DATA_READ) {
139	host->dma_dir = DMA_FROM_DEVICE;
140	dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;
141	DRCMRTXMMC = 0;
142	DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;
143	} else {
144	host->dma_dir = DMA_TO_DEVICE;
145	dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;
146	DRCMRRXMMC = 0;
147	DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;
148	}
149
150	dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;
151
152	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
153	host->dma_dir);
154
155	for (i = 0; i < host->dma_len; i++) {
156	if (data->flags & MMC_DATA_READ) {
157	host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
158	host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
159	} else {
160	host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
161	host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
162	}
163	host->sg_cpu[i].dcmd = dcmd \| sg_dma_len(&data->sg[i]);
164	host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
165	sizeof(struct pxa_dma_desc);
166	}
167	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
168	wmb();
169
170	DDADR(host->dma) = host->sg_dma;
171	DCSR(host->dma) = DCSR_RUN;
172	}
173
174	static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)
175	{
176	WARN_ON(host->cmd != NULL);
177	host->cmd = cmd;
178
179	if (cmd->flags & MMC_RSP_BUSY)
180	cmdat \|= CMDAT_BUSY;
181
182	switch (cmd->flags & (MMC_RSP_MASK \| MMC_RSP_CRC)) {
183	case MMC_RSP_SHORT \| MMC_RSP_CRC:
184	cmdat \|= CMDAT_RESP_SHORT;
185	break;
186	case MMC_RSP_SHORT:
187	cmdat \|= CMDAT_RESP_R3;
188	break;
189	case MMC_RSP_LONG \| MMC_RSP_CRC:
190	cmdat \|= CMDAT_RESP_R2;
191	break;
192	default:
193	break;
194	}
195
196	writel(cmd->opcode, host->base + MMC_CMD);
197	writel(cmd->arg >> 16, host->base + MMC_ARGH);
198	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
199	writel(cmdat, host->base + MMC_CMDAT);
200	writel(host->clkrt, host->base + MMC_CLKRT);
201
202	writel(START_CLOCK, host->base + MMC_STRPCL);
203
204	pxamci_enable_irq(host, END_CMD_RES);
205	}
206
207	static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)
208	{
209	DBG("PXAMCI: request done\n");
210	host->mrq = NULL;
211	host->cmd = NULL;
212	host->data = NULL;
213	mmc_request_done(host->mmc, mrq);
214	}
215
216	static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
217	{
218	struct mmc_command *cmd = host->cmd;
219	int i;
220	u32 v;
221
222	if (!cmd)
223	return 0;
224
225	host->cmd = NULL;
226
227	/*
228	* Did I mention this is Sick. We always need to
229	* discard the upper 8 bits of the first 16-bit word.
230	*/
231	v = readl(host->base + MMC_RES) & 0xffff;
232	for (i = 0; i < 4; i++) {
233	u32 w1 = readl(host->base + MMC_RES) & 0xffff;
234	u32 w2 = readl(host->base + MMC_RES) & 0xffff;
235	cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;
236	v = w2;
237	}
238
239	if (stat & STAT_TIME_OUT_RESPONSE) {
240	cmd->error = MMC_ERR_TIMEOUT;
241	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
242	#ifdef CONFIG_PXA27x
243	/*
244	* workaround for erratum #42:
245	* Intel PXA27x Family Processor Specification Update Rev 001
246	*/
247	if (cmd->opcode == MMC_ALL_SEND_CID \|\|
248	cmd->opcode == MMC_SEND_CSD \|\|
249	cmd->opcode == MMC_SEND_CID) {
250	/* a bogus CRC error can appear if the msb of
251	the 15 byte response is a one */
252	if ((cmd->resp[0] & 0x80000000) == 0)
253	cmd->error = MMC_ERR_BADCRC;
254	} else {
255	DBG("ignoring CRC from command %d - risky\n",cmd->opcode);
256	}
257	#else
258	cmd->error = MMC_ERR_BADCRC;
259	#endif
260	}
261
262	pxamci_disable_irq(host, END_CMD_RES);
263	if (host->data && cmd->error == MMC_ERR_NONE) {
264	pxamci_enable_irq(host, DATA_TRAN_DONE);
265	} else {
266	pxamci_finish_request(host, host->mrq);
267	}
268
269	return 1;
270	}
271
272	static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
273	{
274	struct mmc_data *data = host->data;
275
276	if (!data)
277	return 0;
278
279	DCSR(host->dma) = 0;
280	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
281	host->dma_dir);
282
283	if (stat & STAT_READ_TIME_OUT)
284	data->error = MMC_ERR_TIMEOUT;
285	else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))
286	data->error = MMC_ERR_BADCRC;
287
288	/*
289	* There appears to be a hardware design bug here. There seems to
290	* be no way to find out how much data was transferred to the card.
291	* This means that if there was an error on any block, we mark all
292	* data blocks as being in error.
293	*/
294	if (data->error == MMC_ERR_NONE)
295	data->bytes_xfered = data->blocks << data->blksz_bits;
296	else
297	data->bytes_xfered = 0;
298
299	pxamci_disable_irq(host, DATA_TRAN_DONE);
300
301	host->data = NULL;
302	if (host->mrq->stop && data->error == MMC_ERR_NONE) {
303	pxamci_stop_clock(host);
304	pxamci_start_cmd(host, host->mrq->stop, 0);
305	} else {
306	pxamci_finish_request(host, host->mrq);
307	}
308
309	return 1;
310	}
311
312	static irqreturn_t pxamci_irq(int irq, void devid, struct pt_regs regs)
313	{
314	struct pxamci_host *host = devid;
315	unsigned int ireg;
316	int handled = 0;
317
318	ireg = readl(host->base + MMC_I_REG);
319
320	DBG("PXAMCI: irq %08x\n", ireg);
321
322	if (ireg) {
323	unsigned stat = readl(host->base + MMC_STAT);
324
325	DBG("PXAMCI: stat %08x\n", stat);
326
327	if (ireg & END_CMD_RES)
328	handled \|= pxamci_cmd_done(host, stat);
329	if (ireg & DATA_TRAN_DONE)
330	handled \|= pxamci_data_done(host, stat);
331	}
332
333	return IRQ_RETVAL(handled);
334	}
335
336	static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)
337	{
338	struct pxamci_host *host = mmc_priv(mmc);
339	unsigned int cmdat;
340
341	WARN_ON(host->mrq != NULL);
342
343	host->mrq = mrq;
344
345	pxamci_stop_clock(host);
346
347	cmdat = host->cmdat;
348	host->cmdat &= ~CMDAT_INIT;
349
350	if (mrq->data) {
351	pxamci_setup_data(host, mrq->data);
352
353	cmdat &= ~CMDAT_BUSY;
354	cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;
355	if (mrq->data->flags & MMC_DATA_WRITE)
356	cmdat \|= CMDAT_WRITE;
357
358	if (mrq->data->flags & MMC_DATA_STREAM)
359	cmdat \|= CMDAT_STREAM;
360	}
361
362	pxamci_start_cmd(host, mrq->cmd, cmdat);
363	}
364
e619524f RP	365	static int pxamci_get_ro(struct mmc_host *mmc)
	366	{
	367	struct pxamci_host *host = mmc_priv(mmc);
	368
	369	if (host->pdata && host->pdata->get_ro)
	370	return host->pdata->get_ro(mmc->dev);
	371	/* Host doesn't support read only detection so assume writeable */
	372	return 0;
	373	}
	374
1da177e4 LT	375	static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	376	{
	377	struct pxamci_host *host = mmc_priv(mmc);
	378
	379	DBG("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
	380	ios->clock, ios->power_mode, ios->vdd / 100,
	381	ios->vdd % 100);
	382
	383	if (ios->clock) {
	384	unsigned int clk = CLOCKRATE / ios->clock;
	385	if (CLOCKRATE / clk > ios->clock)
	386	clk <<= 1;
	387	host->clkrt = fls(clk) - 1;
	388	pxa_set_cken(CKEN12_MMC, 1);
	389
	390	/*
	391	* we write clkrt on the next command
	392	*/
	393	} else {
	394	pxamci_stop_clock(host);
	395	pxa_set_cken(CKEN12_MMC, 0);
	396	}
	397
	398	if (host->power_mode != ios->power_mode) {
	399	host->power_mode = ios->power_mode;
	400
	401	if (host->pdata && host->pdata->setpower)
	402	host->pdata->setpower(mmc->dev, ios->vdd);
	403
	404	if (ios->power_mode == MMC_POWER_ON)
	405	host->cmdat \|= CMDAT_INIT;
	406	}
	407
	408	DBG("pxamci_set_ios: clkrt = %x cmdat = %x\n",
	409	host->clkrt, host->cmdat);
	410	}
	411
	412	static struct mmc_host_ops pxamci_ops = {
	413	.request = pxamci_request,
e619524f	414	.get_ro = pxamci_get_ro,
1da177e4 LT	415	.set_ios = pxamci_set_ios,
	416	};
	417
	418	static void pxamci_dma_irq(int dma, void devid, struct pt_regs regs)
	419	{
	420	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	421	DCSR(dma) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	422	}
	423
	424	static irqreturn_t pxamci_detect_irq(int irq, void devid, struct pt_regs regs)
	425	{
c26971cb RP	426	struct pxamci_host *host = mmc_priv(devid);
	427
	428	mmc_detect_change(devid, host->pdata->detect_delay);
1da177e4 LT	429	return IRQ_HANDLED;
	430	}
	431
	432	static int pxamci_probe(struct device *dev)
	433	{
	434	struct platform_device *pdev = to_platform_device(dev);
	435	struct mmc_host *mmc;
	436	struct pxamci_host *host = NULL;
	437	struct resource *r;
	438	int ret, irq;
	439
	440	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	441	irq = platform_get_irq(pdev, 0);
	442	if (!r \|\| irq == NO_IRQ)
	443	return -ENXIO;
	444
	445	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	446	if (!r)
	447	return -EBUSY;
	448
	449	mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
	450	if (!mmc) {
	451	ret = -ENOMEM;
	452	goto out;
	453	}
	454
	455	mmc->ops = &pxamci_ops;
	456	mmc->f_min = CLOCKRATE_MIN;
	457	mmc->f_max = CLOCKRATE_MAX;
	458
	459	/*
	460	* We can do SG-DMA, but we don't because we never know how much
	461	* data we successfully wrote to the card.
	462	*/
	463	mmc->max_phys_segs = NR_SG;
	464
	465	/*
	466	* Our hardware DMA can handle a maximum of one page per SG entry.
	467	*/
	468	mmc->max_seg_size = PAGE_SIZE;
	469
	470	host = mmc_priv(mmc);
	471	host->mmc = mmc;
	472	host->dma = -1;
	473	host->pdata = pdev->dev.platform_data;
	474	mmc->ocr_avail = host->pdata ?
	475	host->pdata->ocr_mask :
	476	MMC_VDD_32_33\|MMC_VDD_33_34;
	477
	478	host->sg_cpu = dma_alloc_coherent(dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	479	if (!host->sg_cpu) {
	480	ret = -ENOMEM;
	481	goto out;
	482	}
	483
	484	spin_lock_init(&host->lock);
	485	host->res = r;
	486	host->irq = irq;
	487	host->imask = MMC_I_MASK_ALL;
	488
	489	host->base = ioremap(r->start, SZ_4K);
	490	if (!host->base) {
	491	ret = -ENOMEM;
	492	goto out;
493	}
494
495	/*
496	* Ensure that the host controller is shut down, and setup
497	* with our defaults.
498	*/
499	pxamci_stop_clock(host);
500	writel(0, host->base + MMC_SPI);
501	writel(64, host->base + MMC_RESTO);
502	writel(host->imask, host->base + MMC_I_MASK);
503
504	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
505	pxamci_dma_irq, host);
506	if (host->dma < 0) {
507	ret = -EBUSY;
508	goto out;
509	}
510
511	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
512	if (ret)
513	goto out;
514
515	dev_set_drvdata(dev, mmc);
516
517	if (host->pdata && host->pdata->init)
518	host->pdata->init(dev, pxamci_detect_irq, mmc);
519
520	mmc_add_host(mmc);
521
522	return 0;
523
524	out:
525	if (host) {
526	if (host->dma >= 0)
527	pxa_free_dma(host->dma);
528	if (host->base)
529	iounmap(host->base);
530	if (host->sg_cpu)
531	dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
532	}
533	if (mmc)
534	mmc_free_host(mmc);
535	release_resource(r);
536	return ret;
537	}
538
539	static int pxamci_remove(struct device *dev)
540	{
541	struct mmc_host *mmc = dev_get_drvdata(dev);
542
543	dev_set_drvdata(dev, NULL);
544
545	if (mmc) {
546	struct pxamci_host *host = mmc_priv(mmc);
547
548	if (host->pdata && host->pdata->exit)
549	host->pdata->exit(dev, mmc);
550
551	mmc_remove_host(mmc);
552
553	pxamci_stop_clock(host);
554	writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|
555	END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,
556	host->base + MMC_I_MASK);
557
558	DRCMRRXMMC = 0;
559	DRCMRTXMMC = 0;
560
561	free_irq(host->irq, host);
562	pxa_free_dma(host->dma);
563	iounmap(host->base);
564	dma_free_coherent(dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
565
566	release_resource(host->res);
567
568	mmc_free_host(mmc);
569	}
570	return 0;
571	}
572
573	#ifdef CONFIG_PM
e5378ca8	574	static int pxamci_suspend(struct device *dev, pm_message_t state, u32 level)
1da177e4 LT	575	{
	576	struct mmc_host *mmc = dev_get_drvdata(dev);
	577	int ret = 0;
	578
	579	if (mmc && level == SUSPEND_DISABLE)
	580	ret = mmc_suspend_host(mmc, state);
	581
	582	return ret;
	583	}
	584
	585	static int pxamci_resume(struct device *dev, u32 level)
	586	{
	587	struct mmc_host *mmc = dev_get_drvdata(dev);
	588	int ret = 0;
	589
	590	if (mmc && level == RESUME_ENABLE)
	591	ret = mmc_resume_host(mmc);
	592
	593	return ret;
	594	}
	595	#else
	596	#define pxamci_suspend NULL
	597	#define pxamci_resume NULL
	598	#endif
	599
	600	static struct device_driver pxamci_driver = {
	601	.name = DRIVER_NAME,
	602	.bus = &platform_bus_type,
	603	.probe = pxamci_probe,
	604	.remove = pxamci_remove,
	605	.suspend = pxamci_suspend,
	606	.resume = pxamci_resume,
	607	};
	608
	609	static int __init pxamci_init(void)
	610	{
	611	return driver_register(&pxamci_driver);
	612	}
	613
	614	static void __exit pxamci_exit(void)
	615	{
	616	driver_unregister(&pxamci_driver);
	617	}
	618
	619	module_init(pxamci_init);
	620	module_exit(pxamci_exit);
	621
	622	MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
	623	MODULE_LICENSE("GPL");