[net-next-2.6.git] / drivers / mmc / host / sdhci.h

/*
 *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */
#ifndef __SDHCI_H
#define __SDHCI_H

#include <linux/scatterlist.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		0x01
#define  SDHCI_TRNS_BLK_CNT_EN	0x02
#define  SDHCI_TRNS_ACMD12	0x04
#define  SDHCI_TRNS_READ	0x10
#define  SDHCI_TRNS_MULTI	0x20

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	0x00000001
#define  SDHCI_DATA_INHIBIT	0x00000002
#define  SDHCI_DOING_WRITE	0x00000100
#define  SDHCI_DOING_READ	0x00000200
#define  SDHCI_SPACE_AVAILABLE	0x00000400
#define  SDHCI_DATA_AVAILABLE	0x00000800
#define  SDHCI_CARD_PRESENT	0x00010000
#define  SDHCI_WRITE_PROTECT	0x00080000

#define SDHCI_HOST_CONTROL 	0x28
#define  SDHCI_CTRL_LED		0x01
#define  SDHCI_CTRL_4BITBUS	0x02
#define  SDHCI_CTRL_HISPD	0x04
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_CLOCK_CARD_EN	0x0004
#define  SDHCI_CLOCK_INT_STABLE	0x0002
#define  SDHCI_CLOCK_INT_EN	0x0001

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	0x00000001
#define  SDHCI_INT_DATA_END	0x00000002
#define  SDHCI_INT_DMA_END	0x00000008
#define  SDHCI_INT_SPACE_AVAIL	0x00000010
#define  SDHCI_INT_DATA_AVAIL	0x00000020
#define  SDHCI_INT_CARD_INSERT	0x00000040
#define  SDHCI_INT_CARD_REMOVE	0x00000080
#define  SDHCI_INT_CARD_INT	0x00000100
#define  SDHCI_INT_ERROR	0x00008000
#define  SDHCI_INT_TIMEOUT	0x00010000
#define  SDHCI_INT_CRC		0x00020000
#define  SDHCI_INT_END_BIT	0x00040000
#define  SDHCI_INT_INDEX	0x00080000
#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
#define  SDHCI_INT_DATA_CRC	0x00200000
#define  SDHCI_INT_DATA_END_BIT	0x00400000
#define  SDHCI_INT_BUS_POWER	0x00800000
#define  SDHCI_INT_ACMD12ERR	0x01000000
#define  SDHCI_INT_ADMA_ERROR	0x02000000

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK	((unsigned int)-1)

#define SDHCI_ACMD12_ERR	0x3C

/* 3E-3F reserved */

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_ADMA2	0x00080000
#define  SDHCI_CAN_DO_ADMA1	0x00100000
#define  SDHCI_CAN_DO_HISPD	0x00200000
#define  SDHCI_CAN_DO_SDMA	0x00400000
#define  SDHCI_CAN_VDD_330	0x01000000
#define  SDHCI_CAN_VDD_300	0x02000000
#define  SDHCI_CAN_VDD_180	0x04000000
#define  SDHCI_CAN_64BIT	0x10000000

/* 44-47 reserved for more caps */

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1

struct sdhci_ops;

struct sdhci_host {
	/* Data set by hardware interface driver */
	const char		*hw_name;	/* Hardware bus name */

	unsigned int		quirks;		/* Deviations from spec. */

/* Controller doesn't honor resets unless we touch the clock register */
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
/* Controller has bad caps bits, but really supports DMA */
#define SDHCI_QUIRK_FORCE_DMA				(1<<1)
/* Controller doesn't like to be reset when there is no card inserted. */
#define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
/* Controller doesn't like clearing the power reg before a change */
#define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
/* Controller has flaky internal state so reset it on each ios change */
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
/* Controller has an unusable DMA engine */
#define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
/* Controller has an unusable ADMA engine */
#define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
/* Controller can only DMA from 32-bit aligned addresses */
#define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
/* Controller can only ADMA chunks that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
/* Controller needs to be reset after each request to stay stable */
#define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
/* Controller needs voltage and power writes to happen separately */
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
/* Controller provides an incorrect timeout value for transfers */
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)
/* Controller has an issue with buffer bits for small transfers */
#define SDHCI_QUIRK_BROKEN_SMALL_PIO			(1<<13)
/* Controller does not provide transfer-complete interrupt when not busy */
#define SDHCI_QUIRK_NO_BUSY_IRQ				(1<<14)
/* Controller has unreliable card detection */
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION		(1<<15)
/* Controller reports inverted write-protect state */
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT		(1<<16)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_CLOCK			(1<<17)
/* Controller does not like fast PIO transfers */
#define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
/* Controller losing signal/interrupt enable states after reset */
#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET		(1<<19)
/* Controller has to be forced to use block size of 2048 bytes */
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
/* Controller cannot do multi-block transfers */
#define SDHCI_QUIRK_NO_MULTIBLOCK			(1<<21)
/* Controller can only handle 1-bit data transfers */
#define SDHCI_QUIRK_FORCE_1_BIT_DATA			(1<<22)
/* Controller needs 10ms delay between applying power and clock */
#define SDHCI_QUIRK_DELAY_AFTER_POWER			(1<<23)
/* Controller uses SDCLK instead of TMCLK for data timeouts */
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK		(1<<24)
/* Controller reports wrong base clock capability */
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
/* Controller cannot support End Attribute in NOP ADMA descriptor */
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)

	int			irq;		/* Device IRQ */
	void __iomem *		ioaddr;		/* Mapped address */

	const struct sdhci_ops	*ops;		/* Low level hw interface */

	/* Internal data */
	struct mmc_host		*mmc;		/* MMC structure */
	u64			dma_mask;	/* custom DMA mask */

#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
	struct led_classdev	led;		/* LED control */
	char   led_name[32];
#endif

	spinlock_t		lock;		/* Mutex */

	int			flags;		/* Host attributes */
#define SDHCI_USE_SDMA		(1<<0)		/* Host is SDMA capable */
#define SDHCI_USE_ADMA		(1<<1)		/* Host is ADMA capable */
#define SDHCI_REQ_USE_DMA	(1<<2)		/* Use DMA for this req. */
#define SDHCI_DEVICE_DEAD	(1<<3)		/* Device unresponsive */

	unsigned int		version;	/* SDHCI spec. version */

	unsigned int		max_clk;	/* Max possible freq (MHz) */
	unsigned int		timeout_clk;	/* Timeout freq (KHz) */

	unsigned int		clock;		/* Current clock (MHz) */
	u8			pwr;		/* Current voltage */

	struct mmc_request	*mrq;		/* Current request */
	struct mmc_command	*cmd;		/* Current command */
	struct mmc_data		*data;		/* Current data request */
	unsigned int		data_early:1;	/* Data finished before cmd */

	struct sg_mapping_iter	sg_miter;	/* SG state for PIO */
	unsigned int		blocks;		/* remaining PIO blocks */

	int			sg_count;	/* Mapped sg entries */

	u8			*adma_desc;	/* ADMA descriptor table */
	u8			*align_buffer;	/* Bounce buffer */

	dma_addr_t		adma_addr;	/* Mapped ADMA descr. table */
	dma_addr_t		align_addr;	/* Mapped bounce buffer */

	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
	struct tasklet_struct	finish_tasklet;

	struct timer_list	timer;		/* Timer for timeouts */

	unsigned long		private[0] ____cacheline_aligned;
};


struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32		(*read_l)(struct sdhci_host *host, int reg);
	u16		(*read_w)(struct sdhci_host *host, int reg);
	u8		(*read_b)(struct sdhci_host *host, int reg);
	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif

	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);

	int		(*enable_dma)(struct sdhci_host *host);
	unsigned int	(*get_max_clock)(struct sdhci_host *host);
	unsigned int	(*get_min_clock)(struct sdhci_host *host);
	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
};

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	if (unlikely(host->ops->write_l))
		host->ops->write_l(host, val, reg);
	else
		writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	if (unlikely(host->ops->write_w))
		host->ops->write_w(host, val, reg);
	else
		writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	if (unlikely(host->ops->write_b))
		host->ops->write_b(host, val, reg);
	else
		writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_l))
		return host->ops->read_l(host, reg);
	else
		return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_w))
		return host->ops->read_w(host, reg);
	else
		return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_b))
		return host->ops->read_b(host, reg);
	else
		return readb(host->ioaddr + reg);
}

#else

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}

#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */

extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size);
extern void sdhci_free_host(struct sdhci_host *host);

static inline void *sdhci_priv(struct sdhci_host *host)
{
	return (void *)host->private;
}

extern int sdhci_add_host(struct sdhci_host *host);
extern void sdhci_remove_host(struct sdhci_host *host, int dead);

#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
extern int sdhci_resume_host(struct sdhci_host *host);
#endif

#endif /* __SDHCI_H */
Commit	Line	Data
d129bceb	1	/*
70f10482	2	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
d129bceb	3	*
b69c9058	4	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb PO	5	*
d129bceb PO	6	* This program is free software; you can redistribute it and/or modify
643f720c PO	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or (at
	9	* your option) any later version.
d129bceb	10	*/
c0bba0d2 AH	11	#ifndef __SDHCI_H
c0bba0d2 AH	12	#define __SDHCI_H
d129bceb	13
0c7ad106	14	#include <linux/scatterlist.h>
4e4141a5 AV	15	#include <linux/compiler.h>
	16	#include <linux/types.h>
	17	#include <linux/io.h>
0c7ad106	18
d129bceb PO	19	/*
	20	* Controller registers
	21	*/
	22
	23	#define SDHCI_DMA_ADDRESS 0x00
	24
	25	#define SDHCI_BLOCK_SIZE 0x04
bab76961	26	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
d129bceb PO	27
	28	#define SDHCI_BLOCK_COUNT 0x06
	29
	30	#define SDHCI_ARGUMENT 0x08
	31
	32	#define SDHCI_TRANSFER_MODE 0x0C
	33	#define SDHCI_TRNS_DMA 0x01
	34	#define SDHCI_TRNS_BLK_CNT_EN 0x02
	35	#define SDHCI_TRNS_ACMD12 0x04
	36	#define SDHCI_TRNS_READ 0x10
	37	#define SDHCI_TRNS_MULTI 0x20
	38
	39	#define SDHCI_COMMAND 0x0E
	40	#define SDHCI_CMD_RESP_MASK 0x03
	41	#define SDHCI_CMD_CRC 0x08
	42	#define SDHCI_CMD_INDEX 0x10
	43	#define SDHCI_CMD_DATA 0x20
	44
	45	#define SDHCI_CMD_RESP_NONE 0x00
	46	#define SDHCI_CMD_RESP_LONG 0x01
	47	#define SDHCI_CMD_RESP_SHORT 0x02
	48	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	49
	50	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	51
	52	#define SDHCI_RESPONSE 0x10
	53
	54	#define SDHCI_BUFFER 0x20
	55
	56	#define SDHCI_PRESENT_STATE 0x24
	57	#define SDHCI_CMD_INHIBIT 0x00000001
	58	#define SDHCI_DATA_INHIBIT 0x00000002
	59	#define SDHCI_DOING_WRITE 0x00000100
	60	#define SDHCI_DOING_READ 0x00000200
	61	#define SDHCI_SPACE_AVAILABLE 0x00000400
	62	#define SDHCI_DATA_AVAILABLE 0x00000800
	63	#define SDHCI_CARD_PRESENT 0x00010000
	64	#define SDHCI_WRITE_PROTECT 0x00080000
	65
	66	#define SDHCI_HOST_CONTROL 0x28
	67	#define SDHCI_CTRL_LED 0x01
	68	#define SDHCI_CTRL_4BITBUS 0x02
077df884	69	#define SDHCI_CTRL_HISPD 0x04
2134a922 PO	70	#define SDHCI_CTRL_DMA_MASK 0x18
	71	#define SDHCI_CTRL_SDMA 0x00
	72	#define SDHCI_CTRL_ADMA1 0x08
	73	#define SDHCI_CTRL_ADMA32 0x10
	74	#define SDHCI_CTRL_ADMA64 0x18
d129bceb PO	75
d129bceb PO	76	#define SDHCI_POWER_CONTROL 0x29
146ad66e PO	77	#define SDHCI_POWER_ON 0x01
	78	#define SDHCI_POWER_180 0x0A
	79	#define SDHCI_POWER_300 0x0C
	80	#define SDHCI_POWER_330 0x0E
d129bceb PO	81
	82	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	83
2df3b71b	84	#define SDHCI_WAKE_UP_CONTROL 0x2B
d129bceb PO	85
	86	#define SDHCI_CLOCK_CONTROL 0x2C
	87	#define SDHCI_DIVIDER_SHIFT 8
	88	#define SDHCI_CLOCK_CARD_EN 0x0004
	89	#define SDHCI_CLOCK_INT_STABLE 0x0002
	90	#define SDHCI_CLOCK_INT_EN 0x0001
	91
	92	#define SDHCI_TIMEOUT_CONTROL 0x2E
	93
	94	#define SDHCI_SOFTWARE_RESET 0x2F
	95	#define SDHCI_RESET_ALL 0x01
	96	#define SDHCI_RESET_CMD 0x02
	97	#define SDHCI_RESET_DATA 0x04
	98
	99	#define SDHCI_INT_STATUS 0x30
	100	#define SDHCI_INT_ENABLE 0x34
	101	#define SDHCI_SIGNAL_ENABLE 0x38
	102	#define SDHCI_INT_RESPONSE 0x00000001
	103	#define SDHCI_INT_DATA_END 0x00000002
	104	#define SDHCI_INT_DMA_END 0x00000008
a406f5a3 PO	105	#define SDHCI_INT_SPACE_AVAIL 0x00000010
a406f5a3 PO	106	#define SDHCI_INT_DATA_AVAIL 0x00000020
d129bceb PO	107	#define SDHCI_INT_CARD_INSERT 0x00000040
	108	#define SDHCI_INT_CARD_REMOVE 0x00000080
	109	#define SDHCI_INT_CARD_INT 0x00000100
964f9ce2	110	#define SDHCI_INT_ERROR 0x00008000
d129bceb PO	111	#define SDHCI_INT_TIMEOUT 0x00010000
	112	#define SDHCI_INT_CRC 0x00020000
	113	#define SDHCI_INT_END_BIT 0x00040000
	114	#define SDHCI_INT_INDEX 0x00080000
	115	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	116	#define SDHCI_INT_DATA_CRC 0x00200000
	117	#define SDHCI_INT_DATA_END_BIT 0x00400000
	118	#define SDHCI_INT_BUS_POWER 0x00800000
	119	#define SDHCI_INT_ACMD12ERR 0x01000000
2134a922	120	#define SDHCI_INT_ADMA_ERROR 0x02000000
d129bceb PO	121
	122	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	123	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	124
	125	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	126	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	127	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
a406f5a3	128	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
d129bceb	129	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
a751a7d6	130	SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR)
7260cf5e	131	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
d129bceb PO	132
	133	#define SDHCI_ACMD12_ERR 0x3C
	134
	135	/* 3E-3F reserved */
	136
	137	#define SDHCI_CAPABILITIES 0x40
1c8cde92 PO	138	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	139	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	140	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
d129bceb PO	141	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
d129bceb PO	142	#define SDHCI_CLOCK_BASE_SHIFT 8
1d676e02 PO	143	#define SDHCI_MAX_BLOCK_MASK 0x00030000
1d676e02 PO	144	#define SDHCI_MAX_BLOCK_SHIFT 16
2134a922 PO	145	#define SDHCI_CAN_DO_ADMA2 0x00080000
2134a922 PO	146	#define SDHCI_CAN_DO_ADMA1 0x00100000
077df884	147	#define SDHCI_CAN_DO_HISPD 0x00200000
a13abc7b	148	#define SDHCI_CAN_DO_SDMA 0x00400000
146ad66e PO	149	#define SDHCI_CAN_VDD_330 0x01000000
	150	#define SDHCI_CAN_VDD_300 0x02000000
	151	#define SDHCI_CAN_VDD_180 0x04000000
2134a922	152	#define SDHCI_CAN_64BIT 0x10000000
d129bceb PO	153
	154	/* 44-47 reserved for more caps */
	155
	156	#define SDHCI_MAX_CURRENT 0x48
	157
	158	/* 4C-4F reserved for more max current */
	159
2134a922 PO	160	#define SDHCI_SET_ACMD12_ERROR 0x50
	161	#define SDHCI_SET_INT_ERROR 0x52
	162
	163	#define SDHCI_ADMA_ERROR 0x54
	164
	165	/* 55-57 reserved */
	166
	167	#define SDHCI_ADMA_ADDRESS 0x58
	168
	169	/* 60-FB reserved */
d129bceb PO	170
	171	#define SDHCI_SLOT_INT_STATUS 0xFC
	172
	173	#define SDHCI_HOST_VERSION 0xFE
4a965505 PO	174	#define SDHCI_VENDOR_VER_MASK 0xFF00
	175	#define SDHCI_VENDOR_VER_SHIFT 8
	176	#define SDHCI_SPEC_VER_MASK 0x00FF
	177	#define SDHCI_SPEC_VER_SHIFT 0
2134a922 PO	178	#define SDHCI_SPEC_100 0
2134a922 PO	179	#define SDHCI_SPEC_200 1
d129bceb	180
b8c86fc5	181	struct sdhci_ops;
d129bceb PO	182
d129bceb PO	183	struct sdhci_host {
b8c86fc5 PO	184	/* Data set by hardware interface driver */
	185	const char hw_name; / Hardware bus name */
	186
	187	unsigned int quirks; /* Deviations from spec. */
	188
	189	/* Controller doesn't honor resets unless we touch the clock register */
	190	#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
	191	/* Controller has bad caps bits, but really supports DMA */
	192	#define SDHCI_QUIRK_FORCE_DMA (1<<1)
	193	/* Controller doesn't like to be reset when there is no card inserted. */
	194	#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
	195	/* Controller doesn't like clearing the power reg before a change */
	196	#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
	197	/* Controller has flaky internal state so reset it on each ios change */
	198	#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
	199	/* Controller has an unusable DMA engine */
	200	#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
2134a922 PO	201	/* Controller has an unusable ADMA engine */
2134a922 PO	202	#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
b8c86fc5	203	/* Controller can only DMA from 32-bit aligned addresses */
2134a922	204	#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
b8c86fc5	205	/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
2134a922 PO	206	#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
	207	/* Controller can only ADMA chunks that are a multiple of 32 bits */
	208	#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
b8c86fc5	209	/* Controller needs to be reset after each request to stay stable */
2134a922	210	#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
b8c86fc5	211	/* Controller needs voltage and power writes to happen separately */
2134a922	212	#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
ee53ab5d	213	/* Controller provides an incorrect timeout value for transfers */
2134a922	214	#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
4a3cba32 PO	215	/* Controller has an issue with buffer bits for small transfers */
4a3cba32 PO	216	#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
f945405c BD	217	/* Controller does not provide transfer-complete interrupt when not busy */
f945405c BD	218	#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
68d1fb7e AV	219	/* Controller has unreliable card detection */
68d1fb7e AV	220	#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
c5075a10 AV	221	/* Controller reports inverted write-protect state */
c5075a10 AV	222	#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
8114634c AV	223	/* Controller has nonstandard clock management */
8114634c AV	224	#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
3e3bf207 AV	225	/* Controller does not like fast PIO transfers */
3e3bf207 AV	226	#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
063a9dbb AV	227	/* Controller losing signal/interrupt enable states after reset */
063a9dbb AV	228	#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
0633f654 AV	229	/* Controller has to be forced to use block size of 2048 bytes */
0633f654 AV	230	#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
1388eefd BD	231	/* Controller cannot do multi-block transfers */
1388eefd BD	232	#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
5fe23c7f AV	233	/* Controller can only handle 1-bit data transfers */
5fe23c7f AV	234	#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
557b0697 HW	235	/* Controller needs 10ms delay between applying power and clock */
557b0697 HW	236	#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
81b39802 AV	237	/* Controller uses SDCLK instead of TMCLK for data timeouts */
81b39802 AV	238	#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
f27f47ef AV	239	/* Controller reports wrong base clock capability */
f27f47ef AV	240	#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
70764a90 TA	241	/* Controller cannot support End Attribute in NOP ADMA descriptor */
70764a90 TA	242	#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
b8c86fc5 PO	243
	244	int irq; /* Device IRQ */
	245	void __iomem * ioaddr; /* Mapped address */
	246
	247	const struct sdhci_ops ops; / Low level hw interface */
	248
	249	/* Internal data */
d129bceb	250	struct mmc_host mmc; / MMC structure */
7659150c	251	u64 dma_mask; /* custom DMA mask */
d129bceb	252
35ff8554	253	#if defined(CONFIG_LEDS_CLASS) \|\| defined(CONFIG_LEDS_CLASS_MODULE)
2f730fec	254	struct led_classdev led; /* LED control */
5dbace0c	255	char led_name[32];
2f730fec PO	256	#endif
2f730fec PO	257
d129bceb PO	258	spinlock_t lock; /* Mutex */
	259
	260	int flags; /* Host attributes */
a13abc7b	261	#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
2134a922 PO	262	#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
	263	#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
	264	#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
	265
	266	unsigned int version; /* SDHCI spec. version */
d129bceb PO	267
d129bceb PO	268	unsigned int max_clk; /* Max possible freq (MHz) */
1c8cde92	269	unsigned int timeout_clk; /* Timeout freq (KHz) */
d129bceb PO	270
d129bceb PO	271	unsigned int clock; /* Current clock (MHz) */
ae628903	272	u8 pwr; /* Current voltage */
d129bceb PO	273
	274	struct mmc_request mrq; / Current request */
	275	struct mmc_command cmd; / Current command */
	276	struct mmc_data data; / Current data request */
55654be9	277	unsigned int data_early:1; /* Data finished before cmd */
d129bceb	278
7659150c PO	279	struct sg_mapping_iter sg_miter; /* SG state for PIO */
7659150c PO	280	unsigned int blocks; /* remaining PIO blocks */
d129bceb	281
2134a922 PO	282	int sg_count; /* Mapped sg entries */
	283
	284	u8 adma_desc; / ADMA descriptor table */
	285	u8 align_buffer; / Bounce buffer */
	286
	287	dma_addr_t adma_addr; /* Mapped ADMA descr. table */
	288	dma_addr_t align_addr; /* Mapped bounce buffer */
	289
d129bceb PO	290	struct tasklet_struct card_tasklet; /* Tasklet structures */
	291	struct tasklet_struct finish_tasklet;
	292
	293	struct timer_list timer; /* Timer for timeouts */
d129bceb	294
b8c86fc5 PO	295	unsigned long private[0] ____cacheline_aligned;
b8c86fc5 PO	296	};
d129bceb	297
df673b22	298
b8c86fc5	299	struct sdhci_ops {
4e4141a5	300	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
dc297c92 MF	301	u32 (read_l)(struct sdhci_host host, int reg);
	302	u16 (read_w)(struct sdhci_host host, int reg);
	303	u8 (read_b)(struct sdhci_host host, int reg);
	304	void (write_l)(struct sdhci_host host, u32 val, int reg);
	305	void (write_w)(struct sdhci_host host, u16 val, int reg);
	306	void (write_b)(struct sdhci_host host, u8 val, int reg);
4e4141a5 AV	307	#endif
4e4141a5 AV	308
8114634c AV	309	void (set_clock)(struct sdhci_host host, unsigned int clock);
8114634c AV	310
b8c86fc5	311	int (enable_dma)(struct sdhci_host host);
4240ff0a	312	unsigned int (get_max_clock)(struct sdhci_host host);
a9e58f25	313	unsigned int (get_min_clock)(struct sdhci_host host);
4240ff0a	314	unsigned int (get_timeout_clock)(struct sdhci_host host);
d129bceb	315	};
b8c86fc5	316
4e4141a5 AV	317	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	318
	319	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	320	{
dc297c92 MF	321	if (unlikely(host->ops->write_l))
dc297c92 MF	322	host->ops->write_l(host, val, reg);
4e4141a5 AV	323	else
	324	writel(val, host->ioaddr + reg);
	325	}
	326
	327	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	328	{
dc297c92 MF	329	if (unlikely(host->ops->write_w))
dc297c92 MF	330	host->ops->write_w(host, val, reg);
4e4141a5 AV	331	else
	332	writew(val, host->ioaddr + reg);
	333	}
	334
	335	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	336	{
dc297c92 MF	337	if (unlikely(host->ops->write_b))
dc297c92 MF	338	host->ops->write_b(host, val, reg);
4e4141a5 AV	339	else
	340	writeb(val, host->ioaddr + reg);
	341	}
	342
	343	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	344	{
dc297c92 MF	345	if (unlikely(host->ops->read_l))
dc297c92 MF	346	return host->ops->read_l(host, reg);
4e4141a5 AV	347	else
	348	return readl(host->ioaddr + reg);
	349	}
	350
	351	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	352	{
dc297c92 MF	353	if (unlikely(host->ops->read_w))
dc297c92 MF	354	return host->ops->read_w(host, reg);
4e4141a5 AV	355	else
	356	return readw(host->ioaddr + reg);
	357	}
	358
	359	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	360	{
dc297c92 MF	361	if (unlikely(host->ops->read_b))
dc297c92 MF	362	return host->ops->read_b(host, reg);
4e4141a5 AV	363	else
	364	return readb(host->ioaddr + reg);
	365	}
	366
	367	#else
	368
	369	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	370	{
	371	writel(val, host->ioaddr + reg);
	372	}
	373
	374	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	375	{
	376	writew(val, host->ioaddr + reg);
	377	}
	378
	379	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	380	{
	381	writeb(val, host->ioaddr + reg);
	382	}
	383
	384	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	385	{
	386	return readl(host->ioaddr + reg);
	387	}
	388
	389	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	390	{
	391	return readw(host->ioaddr + reg);
	392	}
	393
	394	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	395	{
	396	return readb(host->ioaddr + reg);
	397	}
	398
	399	#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
b8c86fc5 PO	400
	401	extern struct sdhci_host sdhci_alloc_host(struct device dev,
	402	size_t priv_size);
	403	extern void sdhci_free_host(struct sdhci_host *host);
	404
	405	static inline void sdhci_priv(struct sdhci_host host)
	406	{
	407	return (void *)host->private;
	408	}
	409
	410	extern int sdhci_add_host(struct sdhci_host *host);
1e72859e	411	extern void sdhci_remove_host(struct sdhci_host *host, int dead);
b8c86fc5 PO	412
	413	#ifdef CONFIG_PM
	414	extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
	415	extern int sdhci_resume_host(struct sdhci_host *host);
	416	#endif
c0bba0d2 AH	417
c0bba0d2 AH	418	#endif /* __SDHCI_H */