[net-next-2.6.git] / drivers / mmc / host / sdhci.h

/*
 *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		0x01
#define  SDHCI_TRNS_BLK_CNT_EN	0x02
#define  SDHCI_TRNS_ACMD12	0x04
#define  SDHCI_TRNS_READ	0x10
#define  SDHCI_TRNS_MULTI	0x20

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	0x00000001
#define  SDHCI_DATA_INHIBIT	0x00000002
#define  SDHCI_DOING_WRITE	0x00000100
#define  SDHCI_DOING_READ	0x00000200
#define  SDHCI_SPACE_AVAILABLE	0x00000400
#define  SDHCI_DATA_AVAILABLE	0x00000800
#define  SDHCI_CARD_PRESENT	0x00010000
#define  SDHCI_WRITE_PROTECT	0x00080000

#define SDHCI_HOST_CONTROL 	0x28
#define  SDHCI_CTRL_LED		0x01
#define  SDHCI_CTRL_4BITBUS	0x02
#define  SDHCI_CTRL_HISPD	0x04
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_CLOCK_CARD_EN	0x0004
#define  SDHCI_CLOCK_INT_STABLE	0x0002
#define  SDHCI_CLOCK_INT_EN	0x0001

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	0x00000001
#define  SDHCI_INT_DATA_END	0x00000002
#define  SDHCI_INT_DMA_END	0x00000008
#define  SDHCI_INT_SPACE_AVAIL	0x00000010
#define  SDHCI_INT_DATA_AVAIL	0x00000020
#define  SDHCI_INT_CARD_INSERT	0x00000040
#define  SDHCI_INT_CARD_REMOVE	0x00000080
#define  SDHCI_INT_CARD_INT	0x00000100
#define  SDHCI_INT_ERROR	0x00008000
#define  SDHCI_INT_TIMEOUT	0x00010000
#define  SDHCI_INT_CRC		0x00020000
#define  SDHCI_INT_END_BIT	0x00040000
#define  SDHCI_INT_INDEX	0x00080000
#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
#define  SDHCI_INT_DATA_CRC	0x00200000
#define  SDHCI_INT_DATA_END_BIT	0x00400000
#define  SDHCI_INT_BUS_POWER	0x00800000
#define  SDHCI_INT_ACMD12ERR	0x01000000
#define  SDHCI_INT_ADMA_ERROR	0x02000000

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT)

#define SDHCI_ACMD12_ERR	0x3C

/* 3E-3F reserved */

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_ADMA2	0x00080000
#define  SDHCI_CAN_DO_ADMA1	0x00100000
#define  SDHCI_CAN_DO_HISPD	0x00200000
#define  SDHCI_CAN_DO_DMA	0x00400000
#define  SDHCI_CAN_VDD_330	0x01000000
#define  SDHCI_CAN_VDD_300	0x02000000
#define  SDHCI_CAN_VDD_180	0x04000000
#define  SDHCI_CAN_64BIT	0x10000000

/* 44-47 reserved for more caps */

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1

struct sdhci_ops;

struct sdhci_host {
	/* Data set by hardware interface driver */
	const char		*hw_name;	/* Hardware bus name */

	unsigned int		quirks;		/* Deviations from spec. */

/* Controller doesn't honor resets unless we touch the clock register */
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET			(1<<0)
/* Controller has bad caps bits, but really supports DMA */
#define SDHCI_QUIRK_FORCE_DMA				(1<<1)
/* Controller doesn't like to be reset when there is no card inserted. */
#define SDHCI_QUIRK_NO_CARD_NO_RESET			(1<<2)
/* Controller doesn't like clearing the power reg before a change */
#define SDHCI_QUIRK_SINGLE_POWER_WRITE			(1<<3)
/* Controller has flaky internal state so reset it on each ios change */
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS		(1<<4)
/* Controller has an unusable DMA engine */
#define SDHCI_QUIRK_BROKEN_DMA				(1<<5)
/* Controller has an unusable ADMA engine */
#define SDHCI_QUIRK_BROKEN_ADMA				(1<<6)
/* Controller can only DMA from 32-bit aligned addresses */
#define SDHCI_QUIRK_32BIT_DMA_ADDR			(1<<7)
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_DMA_SIZE			(1<<8)
/* Controller can only ADMA chunks that are a multiple of 32 bits */
#define SDHCI_QUIRK_32BIT_ADMA_SIZE			(1<<9)
/* Controller needs to be reset after each request to stay stable */
#define SDHCI_QUIRK_RESET_AFTER_REQUEST			(1<<10)
/* Controller needs voltage and power writes to happen separately */
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER		(1<<11)
/* Controller provides an incorrect timeout value for transfers */
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL			(1<<12)

	int			irq;		/* Device IRQ */
	void __iomem *		ioaddr;		/* Mapped address */

	const struct sdhci_ops	*ops;		/* Low level hw interface */

	/* Internal data */
	struct mmc_host		*mmc;		/* MMC structure */

#ifdef CONFIG_LEDS_CLASS
	struct led_classdev	led;		/* LED control */
#endif

	spinlock_t		lock;		/* Mutex */

	int			flags;		/* Host attributes */
#define SDHCI_USE_DMA		(1<<0)		/* Host is DMA capable */
#define SDHCI_USE_ADMA		(1<<1)		/* Host is ADMA capable */
#define SDHCI_REQ_USE_DMA	(1<<2)		/* Use DMA for this req. */
#define SDHCI_DEVICE_DEAD	(1<<3)		/* Device unresponsive */

	unsigned int		version;	/* SDHCI spec. version */

	unsigned int		max_clk;	/* Max possible freq (MHz) */
	unsigned int		timeout_clk;	/* Timeout freq (KHz) */

	unsigned int		clock;		/* Current clock (MHz) */
	unsigned short		power;		/* Current voltage */

	struct mmc_request	*mrq;		/* Current request */
	struct mmc_command	*cmd;		/* Current command */
	struct mmc_data		*data;		/* Current data request */
	unsigned int		data_early:1;	/* Data finished before cmd */

	struct scatterlist	*cur_sg;	/* We're working on this */
	int			num_sg;		/* Entries left */
	int			offset;		/* Offset into current sg */
	int			remain;		/* Bytes left in current */

	int			sg_count;	/* Mapped sg entries */

	u8			*adma_desc;	/* ADMA descriptor table */
	u8			*align_buffer;	/* Bounce buffer */

	dma_addr_t		adma_addr;	/* Mapped ADMA descr. table */
	dma_addr_t		align_addr;	/* Mapped bounce buffer */

	struct tasklet_struct	card_tasklet;	/* Tasklet structures */
	struct tasklet_struct	finish_tasklet;

	struct timer_list	timer;		/* Timer for timeouts */

	unsigned long		private[0] ____cacheline_aligned;
};


struct sdhci_ops {
	int		(*enable_dma)(struct sdhci_host *host);
};


extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size);
extern void sdhci_free_host(struct sdhci_host *host);

static inline void *sdhci_priv(struct sdhci_host *host)
{
	return (void *)host->private;
}

extern int sdhci_add_host(struct sdhci_host *host);
extern void sdhci_remove_host(struct sdhci_host *host, int dead);

#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
extern int sdhci_resume_host(struct sdhci_host *host);
#endif
Commit	Line	Data
d129bceb	1	/*
70f10482	2	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
d129bceb	3	*
b69c9058	4	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb PO	5	*
d129bceb PO	6	* This program is free software; you can redistribute it and/or modify
643f720c PO	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or (at
	9	* your option) any later version.
d129bceb PO	10	*/
d129bceb PO	11
d129bceb PO	12	/*
	13	* Controller registers
	14	*/
	15
	16	#define SDHCI_DMA_ADDRESS 0x00
	17
	18	#define SDHCI_BLOCK_SIZE 0x04
bab76961	19	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
d129bceb PO	20
	21	#define SDHCI_BLOCK_COUNT 0x06
	22
	23	#define SDHCI_ARGUMENT 0x08
	24
	25	#define SDHCI_TRANSFER_MODE 0x0C
	26	#define SDHCI_TRNS_DMA 0x01
	27	#define SDHCI_TRNS_BLK_CNT_EN 0x02
	28	#define SDHCI_TRNS_ACMD12 0x04
	29	#define SDHCI_TRNS_READ 0x10
	30	#define SDHCI_TRNS_MULTI 0x20
	31
	32	#define SDHCI_COMMAND 0x0E
	33	#define SDHCI_CMD_RESP_MASK 0x03
	34	#define SDHCI_CMD_CRC 0x08
	35	#define SDHCI_CMD_INDEX 0x10
	36	#define SDHCI_CMD_DATA 0x20
	37
	38	#define SDHCI_CMD_RESP_NONE 0x00
	39	#define SDHCI_CMD_RESP_LONG 0x01
	40	#define SDHCI_CMD_RESP_SHORT 0x02
	41	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	42
	43	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	44
	45	#define SDHCI_RESPONSE 0x10
	46
	47	#define SDHCI_BUFFER 0x20
	48
	49	#define SDHCI_PRESENT_STATE 0x24
	50	#define SDHCI_CMD_INHIBIT 0x00000001
	51	#define SDHCI_DATA_INHIBIT 0x00000002
	52	#define SDHCI_DOING_WRITE 0x00000100
	53	#define SDHCI_DOING_READ 0x00000200
	54	#define SDHCI_SPACE_AVAILABLE 0x00000400
	55	#define SDHCI_DATA_AVAILABLE 0x00000800
	56	#define SDHCI_CARD_PRESENT 0x00010000
	57	#define SDHCI_WRITE_PROTECT 0x00080000
	58
	59	#define SDHCI_HOST_CONTROL 0x28
	60	#define SDHCI_CTRL_LED 0x01
	61	#define SDHCI_CTRL_4BITBUS 0x02
077df884	62	#define SDHCI_CTRL_HISPD 0x04
2134a922 PO	63	#define SDHCI_CTRL_DMA_MASK 0x18
	64	#define SDHCI_CTRL_SDMA 0x00
	65	#define SDHCI_CTRL_ADMA1 0x08
	66	#define SDHCI_CTRL_ADMA32 0x10
	67	#define SDHCI_CTRL_ADMA64 0x18
d129bceb PO	68
d129bceb PO	69	#define SDHCI_POWER_CONTROL 0x29
146ad66e PO	70	#define SDHCI_POWER_ON 0x01
	71	#define SDHCI_POWER_180 0x0A
	72	#define SDHCI_POWER_300 0x0C
	73	#define SDHCI_POWER_330 0x0E
d129bceb PO	74
	75	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	76
2df3b71b	77	#define SDHCI_WAKE_UP_CONTROL 0x2B
d129bceb PO	78
	79	#define SDHCI_CLOCK_CONTROL 0x2C
	80	#define SDHCI_DIVIDER_SHIFT 8
	81	#define SDHCI_CLOCK_CARD_EN 0x0004
	82	#define SDHCI_CLOCK_INT_STABLE 0x0002
	83	#define SDHCI_CLOCK_INT_EN 0x0001
	84
	85	#define SDHCI_TIMEOUT_CONTROL 0x2E
	86
	87	#define SDHCI_SOFTWARE_RESET 0x2F
	88	#define SDHCI_RESET_ALL 0x01
	89	#define SDHCI_RESET_CMD 0x02
	90	#define SDHCI_RESET_DATA 0x04
	91
	92	#define SDHCI_INT_STATUS 0x30
	93	#define SDHCI_INT_ENABLE 0x34
	94	#define SDHCI_SIGNAL_ENABLE 0x38
	95	#define SDHCI_INT_RESPONSE 0x00000001
	96	#define SDHCI_INT_DATA_END 0x00000002
	97	#define SDHCI_INT_DMA_END 0x00000008
a406f5a3 PO	98	#define SDHCI_INT_SPACE_AVAIL 0x00000010
a406f5a3 PO	99	#define SDHCI_INT_DATA_AVAIL 0x00000020
d129bceb PO	100	#define SDHCI_INT_CARD_INSERT 0x00000040
	101	#define SDHCI_INT_CARD_REMOVE 0x00000080
	102	#define SDHCI_INT_CARD_INT 0x00000100
964f9ce2	103	#define SDHCI_INT_ERROR 0x00008000
d129bceb PO	104	#define SDHCI_INT_TIMEOUT 0x00010000
	105	#define SDHCI_INT_CRC 0x00020000
	106	#define SDHCI_INT_END_BIT 0x00040000
	107	#define SDHCI_INT_INDEX 0x00080000
	108	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	109	#define SDHCI_INT_DATA_CRC 0x00200000
	110	#define SDHCI_INT_DATA_END_BIT 0x00400000
	111	#define SDHCI_INT_BUS_POWER 0x00800000
	112	#define SDHCI_INT_ACMD12ERR 0x01000000
2134a922	113	#define SDHCI_INT_ADMA_ERROR 0x02000000
d129bceb PO	114
	115	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	116	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	117
	118	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	119	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	120	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
a406f5a3	121	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
d129bceb PO	122	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
	123	SDHCI_INT_DATA_END_BIT)
	124
	125	#define SDHCI_ACMD12_ERR 0x3C
	126
	127	/* 3E-3F reserved */
	128
	129	#define SDHCI_CAPABILITIES 0x40
1c8cde92 PO	130	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	131	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	132	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
d129bceb PO	133	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
d129bceb PO	134	#define SDHCI_CLOCK_BASE_SHIFT 8
1d676e02 PO	135	#define SDHCI_MAX_BLOCK_MASK 0x00030000
1d676e02 PO	136	#define SDHCI_MAX_BLOCK_SHIFT 16
2134a922 PO	137	#define SDHCI_CAN_DO_ADMA2 0x00080000
2134a922 PO	138	#define SDHCI_CAN_DO_ADMA1 0x00100000
077df884	139	#define SDHCI_CAN_DO_HISPD 0x00200000
146ad66e PO	140	#define SDHCI_CAN_DO_DMA 0x00400000
	141	#define SDHCI_CAN_VDD_330 0x01000000
	142	#define SDHCI_CAN_VDD_300 0x02000000
	143	#define SDHCI_CAN_VDD_180 0x04000000
2134a922	144	#define SDHCI_CAN_64BIT 0x10000000
d129bceb PO	145
	146	/* 44-47 reserved for more caps */
	147
	148	#define SDHCI_MAX_CURRENT 0x48
	149
	150	/* 4C-4F reserved for more max current */
	151
2134a922 PO	152	#define SDHCI_SET_ACMD12_ERROR 0x50
	153	#define SDHCI_SET_INT_ERROR 0x52
	154
	155	#define SDHCI_ADMA_ERROR 0x54
	156
	157	/* 55-57 reserved */
	158
	159	#define SDHCI_ADMA_ADDRESS 0x58
	160
	161	/* 60-FB reserved */
d129bceb PO	162
	163	#define SDHCI_SLOT_INT_STATUS 0xFC
	164
	165	#define SDHCI_HOST_VERSION 0xFE
4a965505 PO	166	#define SDHCI_VENDOR_VER_MASK 0xFF00
	167	#define SDHCI_VENDOR_VER_SHIFT 8
	168	#define SDHCI_SPEC_VER_MASK 0x00FF
	169	#define SDHCI_SPEC_VER_SHIFT 0
2134a922 PO	170	#define SDHCI_SPEC_100 0
2134a922 PO	171	#define SDHCI_SPEC_200 1
d129bceb	172
b8c86fc5	173	struct sdhci_ops;
d129bceb PO	174
d129bceb PO	175	struct sdhci_host {
b8c86fc5 PO	176	/* Data set by hardware interface driver */
	177	const char hw_name; / Hardware bus name */
	178
	179	unsigned int quirks; /* Deviations from spec. */
	180
	181	/* Controller doesn't honor resets unless we touch the clock register */
	182	#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
	183	/* Controller has bad caps bits, but really supports DMA */
	184	#define SDHCI_QUIRK_FORCE_DMA (1<<1)
	185	/* Controller doesn't like to be reset when there is no card inserted. */
	186	#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
	187	/* Controller doesn't like clearing the power reg before a change */
	188	#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
	189	/* Controller has flaky internal state so reset it on each ios change */
	190	#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
	191	/* Controller has an unusable DMA engine */
	192	#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
2134a922 PO	193	/* Controller has an unusable ADMA engine */
2134a922 PO	194	#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
b8c86fc5	195	/* Controller can only DMA from 32-bit aligned addresses */
2134a922	196	#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
b8c86fc5	197	/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
2134a922 PO	198	#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
	199	/* Controller can only ADMA chunks that are a multiple of 32 bits */
	200	#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
b8c86fc5	201	/* Controller needs to be reset after each request to stay stable */
2134a922	202	#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
b8c86fc5	203	/* Controller needs voltage and power writes to happen separately */
2134a922	204	#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
ee53ab5d	205	/* Controller provides an incorrect timeout value for transfers */
2134a922	206	#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
b8c86fc5 PO	207
	208	int irq; /* Device IRQ */
	209	void __iomem * ioaddr; /* Mapped address */
	210
	211	const struct sdhci_ops ops; / Low level hw interface */
	212
	213	/* Internal data */
d129bceb PO	214	struct mmc_host mmc; / MMC structure */
d129bceb PO	215
2f730fec PO	216	#ifdef CONFIG_LEDS_CLASS
	217	struct led_classdev led; /* LED control */
	218	#endif
	219
d129bceb PO	220	spinlock_t lock; /* Mutex */
	221
	222	int flags; /* Host attributes */
c9fddbc4	223	#define SDHCI_USE_DMA (1<<0) /* Host is DMA capable */
2134a922 PO	224	#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
	225	#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
	226	#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
	227
	228	unsigned int version; /* SDHCI spec. version */
d129bceb PO	229
d129bceb PO	230	unsigned int max_clk; /* Max possible freq (MHz) */
1c8cde92	231	unsigned int timeout_clk; /* Timeout freq (KHz) */
d129bceb PO	232
d129bceb PO	233	unsigned int clock; /* Current clock (MHz) */
146ad66e	234	unsigned short power; /* Current voltage */
d129bceb PO	235
	236	struct mmc_request mrq; / Current request */
	237	struct mmc_command cmd; / Current command */
	238	struct mmc_data data; / Current data request */
55654be9	239	unsigned int data_early:1; /* Data finished before cmd */
d129bceb PO	240
d129bceb PO	241	struct scatterlist cur_sg; / We're working on this */
d129bceb PO	242	int num_sg; /* Entries left */
	243	int offset; /* Offset into current sg */
	244	int remain; /* Bytes left in current */
	245
2134a922 PO	246	int sg_count; /* Mapped sg entries */
	247
	248	u8 adma_desc; / ADMA descriptor table */
	249	u8 align_buffer; / Bounce buffer */
	250
	251	dma_addr_t adma_addr; /* Mapped ADMA descr. table */
	252	dma_addr_t align_addr; /* Mapped bounce buffer */
	253
d129bceb PO	254	struct tasklet_struct card_tasklet; /* Tasklet structures */
	255	struct tasklet_struct finish_tasklet;
	256
	257	struct timer_list timer; /* Timer for timeouts */
d129bceb	258
b8c86fc5 PO	259	unsigned long private[0] ____cacheline_aligned;
b8c86fc5 PO	260	};
d129bceb	261
df673b22	262
b8c86fc5 PO	263	struct sdhci_ops {
b8c86fc5 PO	264	int (enable_dma)(struct sdhci_host host);
d129bceb	265	};
b8c86fc5 PO	266
	267
	268	extern struct sdhci_host sdhci_alloc_host(struct device dev,
	269	size_t priv_size);
	270	extern void sdhci_free_host(struct sdhci_host *host);
	271
	272	static inline void sdhci_priv(struct sdhci_host host)
	273	{
	274	return (void *)host->private;
	275	}
	276
	277	extern int sdhci_add_host(struct sdhci_host *host);
1e72859e	278	extern void sdhci_remove_host(struct sdhci_host *host, int dead);
b8c86fc5 PO	279
	280	#ifdef CONFIG_PM
	281	extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
	282	extern int sdhci_resume_host(struct sdhci_host *host);
	283	#endif