[net-next-2.6.git] / drivers / mmc / host / pxamci.c

/*
 *  linux/drivers/mmc/host/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *	1 and 3 byte data transfers not supported
 *	max block length up to 1023
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mmc/host.h>

#include <asm/dma.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>

#include "pxamci.h"

#define DRIVER_NAME	"pxa2xx-mci"

#define NR_SG	1

struct pxamci_host {
	struct mmc_host		*mmc;
	spinlock_t		lock;
	struct resource		*res;
	void __iomem		*base;
	int			irq;
	int			dma;
	unsigned int		clkrt;
	unsigned int		cmdat;
	unsigned int		imask;
	unsigned int		power_mode;
	struct pxamci_platform_data *pdata;

	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;

	dma_addr_t		sg_dma;
	struct pxa_dma_desc	*sg_cpu;
	unsigned int		dma_len;

	unsigned int		dma_dir;
};

static void pxamci_stop_clock(struct pxamci_host *host)
{
	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
		unsigned long timeout = 10000;
		unsigned int v;

		writel(STOP_CLOCK, host->base + MMC_STRPCL);

		do {
			v = readl(host->base + MMC_STAT);
			if (!(v & STAT_CLK_EN))
				break;
			udelay(1);
		} while (timeout--);

		if (v & STAT_CLK_EN)
			dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	}
}

static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask &= ~mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask |= mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned long long clks;
	unsigned int timeout;
	u32 dcmd;
	int i;

	host->data = data;

	if (data->flags & MMC_DATA_STREAM)
		nob = 0xffff;

	writel(nob, host->base + MMC_NOB);
	writel(data->blksz, host->base + MMC_BLKLEN);

	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	do_div(clks, 1000000000UL);
	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
	writel((timeout + 255) / 256, host->base + MMC_RDTO);

	if (data->flags & MMC_DATA_READ) {
		host->dma_dir = DMA_FROM_DEVICE;
		dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
		DRCMRTXMMC = 0;
		DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
	} else {
		host->dma_dir = DMA_TO_DEVICE;
		dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
		DRCMRRXMMC = 0;
		DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
	}

	dcmd |= DCMD_BURST32 | DCMD_WIDTH1;

	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
				   host->dma_dir);

	for (i = 0; i < host->dma_len; i++) {
		if (data->flags & MMC_DATA_READ) {
			host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
			host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
		} else {
			host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
			host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
		}
		host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
		host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
					sizeof(struct pxa_dma_desc);
	}
	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	wmb();

	DDADR(host->dma) = host->sg_dma;
	DCSR(host->dma) = DCSR_RUN;
}

static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
	WARN_ON(host->cmd != NULL);
	host->cmd = cmd;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdat |= CMDAT_BUSY;

#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
	switch (RSP_TYPE(mmc_resp_type(cmd))) {
	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
		cmdat |= CMDAT_RESP_SHORT;
		break;
	case RSP_TYPE(MMC_RSP_R3):
		cmdat |= CMDAT_RESP_R3;
		break;
	case RSP_TYPE(MMC_RSP_R2):
		cmdat |= CMDAT_RESP_R2;
		break;
	default:
		break;
	}

	writel(cmd->opcode, host->base + MMC_CMD);
	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	writel(cmdat, host->base + MMC_CMDAT);
	writel(host->clkrt, host->base + MMC_CLKRT);

	writel(START_CLOCK, host->base + MMC_STRPCL);

	pxamci_enable_irq(host, END_CMD_RES);
}

static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;
	mmc_request_done(host->mmc, mrq);
}

static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_command *cmd = host->cmd;
	int i;
	u32 v;

	if (!cmd)
		return 0;

	host->cmd = NULL;

	/*
	 * Did I mention this is Sick.  We always need to
	 * discard the upper 8 bits of the first 16-bit word.
	 */
	v = readl(host->base + MMC_RES) & 0xffff;
	for (i = 0; i < 4; i++) {
		u32 w1 = readl(host->base + MMC_RES) & 0xffff;
		u32 w2 = readl(host->base + MMC_RES) & 0xffff;
		cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
		v = w2;
	}

	if (stat & STAT_TIME_OUT_RESPONSE) {
		cmd->error = -ETIMEDOUT;
	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
		/*
		 * workaround for erratum #42:
		 * Intel PXA27x Family Processor Specification Update Rev 001
		 * A bogus CRC error can appear if the msb of a 136 bit
		 * response is a one.
		 */
		if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
			pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
		} else
#endif
		cmd->error = -EILSEQ;
	}

	pxamci_disable_irq(host, END_CMD_RES);
	if (host->data && !cmd->error) {
		pxamci_enable_irq(host, DATA_TRAN_DONE);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_data *data = host->data;

	if (!data)
		return 0;

	DCSR(host->dma) = 0;
	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
		     host->dma_dir);

	if (stat & STAT_READ_TIME_OUT)
		data->error = -ETIMEDOUT;
	else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
		data->error = -EILSEQ;

	/*
	 * There appears to be a hardware design bug here.  There seems to
	 * be no way to find out how much data was transferred to the card.
	 * This means that if there was an error on any block, we mark all
	 * data blocks as being in error.
	 */
	if (!data->error)
		data->bytes_xfered = data->blocks * data->blksz;
	else
		data->bytes_xfered = 0;

	pxamci_disable_irq(host, DATA_TRAN_DONE);

	host->data = NULL;
	if (host->mrq->stop) {
		pxamci_stop_clock(host);
		pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static irqreturn_t pxamci_irq(int irq, void *devid)
{
	struct pxamci_host *host = devid;
	unsigned int ireg;
	int handled = 0;

	ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);

	if (ireg) {
		unsigned stat = readl(host->base + MMC_STAT);

		pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);

		if (ireg & END_CMD_RES)
			handled |= pxamci_cmd_done(host, stat);
		if (ireg & DATA_TRAN_DONE)
			handled |= pxamci_data_done(host, stat);
	}

	return IRQ_RETVAL(handled);
}

static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct pxamci_host *host = mmc_priv(mmc);
	unsigned int cmdat;

	WARN_ON(host->mrq != NULL);

	host->mrq = mrq;

	pxamci_stop_clock(host);

	cmdat = host->cmdat;
	host->cmdat &= ~CMDAT_INIT;

	if (mrq->data) {
		pxamci_setup_data(host, mrq->data);

		cmdat &= ~CMDAT_BUSY;
		cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
		if (mrq->data->flags & MMC_DATA_WRITE)
			cmdat |= CMDAT_WRITE;

		if (mrq->data->flags & MMC_DATA_STREAM)
			cmdat |= CMDAT_STREAM;
	}

	pxamci_start_cmd(host, mrq->cmd, cmdat);
}

static int pxamci_get_ro(struct mmc_host *mmc)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (host->pdata && host->pdata->get_ro)
		return host->pdata->get_ro(mmc_dev(mmc));
	/* Host doesn't support read only detection so assume writeable */
	return 0;
}

static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (ios->clock) {
		unsigned int clk = CLOCKRATE / ios->clock;
		if (CLOCKRATE / clk > ios->clock)
			clk <<= 1;
		host->clkrt = fls(clk) - 1;
		pxa_set_cken(CKEN_MMC, 1);

		/*
		 * we write clkrt on the next command
		 */
	} else {
		pxamci_stop_clock(host);
		pxa_set_cken(CKEN_MMC, 0);
	}

	if (host->power_mode != ios->power_mode) {
		host->power_mode = ios->power_mode;

		if (host->pdata && host->pdata->setpower)
			host->pdata->setpower(mmc_dev(mmc), ios->vdd);

		if (ios->power_mode == MMC_POWER_ON)
			host->cmdat |= CMDAT_INIT;
	}

	if (ios->bus_width == MMC_BUS_WIDTH_4)
		host->cmdat |= CMDAT_SD_4DAT;
	else
		host->cmdat &= ~CMDAT_SD_4DAT;

	pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
		 host->clkrt, host->cmdat);
}

static const struct mmc_host_ops pxamci_ops = {
	.request	= pxamci_request,
	.get_ro		= pxamci_get_ro,
	.set_ios	= pxamci_set_ios,
};

static void pxamci_dma_irq(int dma, void *devid)
{
	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
}

static irqreturn_t pxamci_detect_irq(int irq, void *devid)
{
	struct pxamci_host *host = mmc_priv(devid);

	mmc_detect_change(devid, host->pdata->detect_delay);
	return IRQ_HANDLED;
}

static int pxamci_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct pxamci_host *host = NULL;
	struct resource *r;
	int ret, irq;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (!r || irq < 0)
		return -ENXIO;

	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	if (!r)
		return -EBUSY;

	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto out;
	}

	mmc->ops = &pxamci_ops;
	mmc->f_min = CLOCKRATE_MIN;
	mmc->f_max = CLOCKRATE_MAX;

	/*
	 * We can do SG-DMA, but we don't because we never know how much
	 * data we successfully wrote to the card.
	 */
	mmc->max_phys_segs = NR_SG;

	/*
	 * Our hardware DMA can handle a maximum of one page per SG entry.
	 */
	mmc->max_seg_size = PAGE_SIZE;

	/*
	 * Block length register is only 10 bits before PXA27x.
	 */
	mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;

	/*
	 * Block count register is 16 bits.
	 */
	mmc->max_blk_count = 65535;

	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->dma = -1;
	host->pdata = pdev->dev.platform_data;
	mmc->ocr_avail = host->pdata ?
			 host->pdata->ocr_mask :
			 MMC_VDD_32_33|MMC_VDD_33_34;
	mmc->caps = 0;
	if (!cpu_is_pxa21x() && !cpu_is_pxa25x())
		mmc->caps |= MMC_CAP_4_BIT_DATA;

	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	if (!host->sg_cpu) {
		ret = -ENOMEM;
		goto out;
	}

	spin_lock_init(&host->lock);
	host->res = r;
	host->irq = irq;
	host->imask = MMC_I_MASK_ALL;

	host->base = ioremap(r->start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto out;
	}

	/*
	 * Ensure that the host controller is shut down, and setup
	 * with our defaults.
	 */
	pxamci_stop_clock(host);
	writel(0, host->base + MMC_SPI);
	writel(64, host->base + MMC_RESTO);
	writel(host->imask, host->base + MMC_I_MASK);

	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
				    pxamci_dma_irq, host);
	if (host->dma < 0) {
		ret = -EBUSY;
		goto out;
	}

	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, mmc);

	if (host->pdata && host->pdata->init)
		host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);

	mmc_add_host(mmc);

	return 0;

 out:
	if (host) {
		if (host->dma >= 0)
			pxa_free_dma(host->dma);
		if (host->base)
			iounmap(host->base);
		if (host->sg_cpu)
			dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	}
	if (mmc)
		mmc_free_host(mmc);
	release_resource(r);
	return ret;
}

static int pxamci_remove(struct platform_device *pdev)
{
	struct mmc_host *mmc = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);

	if (mmc) {
		struct pxamci_host *host = mmc_priv(mmc);

		if (host->pdata && host->pdata->exit)
			host->pdata->exit(&pdev->dev, mmc);

		mmc_remove_host(mmc);

		pxamci_stop_clock(host);
		writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
		       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
		       host->base + MMC_I_MASK);

		DRCMRRXMMC = 0;
		DRCMRTXMMC = 0;

		free_irq(host->irq, host);
		pxa_free_dma(host->dma);
		iounmap(host->base);
		dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);

		release_resource(host->res);

		mmc_free_host(mmc);
	}
	return 0;
}

#ifdef CONFIG_PM
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_suspend_host(mmc, state);

	return ret;
}

static int pxamci_resume(struct platform_device *dev)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_resume_host(mmc);

	return ret;
}
#else
#define pxamci_suspend	NULL
#define pxamci_resume	NULL
#endif

static struct platform_driver pxamci_driver = {
	.probe		= pxamci_probe,
	.remove		= pxamci_remove,
	.suspend	= pxamci_suspend,
	.resume		= pxamci_resume,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

static int __init pxamci_init(void)
{
	return platform_driver_register(&pxamci_driver);
}

static void __exit pxamci_exit(void)
{
	platform_driver_unregister(&pxamci_driver);
}

module_init(pxamci_init);
module_exit(pxamci_exit);

MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
70f10482	2	* linux/drivers/mmc/host/pxa.c - PXA MMCI driver
1da177e4 LT	3	*
	4	* Copyright (C) 2003 Russell King, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This hardware is really sick:
	11	* - No way to clear interrupts.
	12	* - Have to turn off the clock whenever we touch the device.
	13	* - Doesn't tell you how many data blocks were transferred.
	14	* Yuck!
	15	*
	16	* 1 and 3 byte data transfers not supported
	17	* max block length up to 1023
	18	*/
1da177e4 LT	19	#include <linux/module.h>
	20	#include <linux/init.h>
	21	#include <linux/ioport.h>
d052d1be	22	#include <linux/platform_device.h>
1da177e4 LT	23	#include <linux/delay.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/dma-mapping.h>
	26	#include <linux/mmc/host.h>
1da177e4 LT	27
	28	#include <asm/dma.h>
	29	#include <asm/io.h>
1da177e4 LT	30	#include <asm/scatterlist.h>
	31	#include <asm/sizes.h>
	32
	33	#include <asm/arch/pxa-regs.h>
	34	#include <asm/arch/mmc.h>
	35
	36	#include "pxamci.h"
	37
1da177e4 LT	38	#define DRIVER_NAME "pxa2xx-mci"
	39
	40	#define NR_SG 1
	41
	42	struct pxamci_host {
	43	struct mmc_host *mmc;
	44	spinlock_t lock;
	45	struct resource *res;
	46	void __iomem *base;
	47	int irq;
	48	int dma;
	49	unsigned int clkrt;
	50	unsigned int cmdat;
	51	unsigned int imask;
	52	unsigned int power_mode;
	53	struct pxamci_platform_data *pdata;
	54
	55	struct mmc_request *mrq;
	56	struct mmc_command *cmd;
	57	struct mmc_data *data;
	58
	59	dma_addr_t sg_dma;
	60	struct pxa_dma_desc *sg_cpu;
	61	unsigned int dma_len;
	62
	63	unsigned int dma_dir;
	64	};
	65
1da177e4 LT	66	static void pxamci_stop_clock(struct pxamci_host *host)
	67	{
	68	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
	69	unsigned long timeout = 10000;
	70	unsigned int v;
	71
	72	writel(STOP_CLOCK, host->base + MMC_STRPCL);
	73
	74	do {
	75	v = readl(host->base + MMC_STAT);
	76	if (!(v & STAT_CLK_EN))
	77	break;
	78	udelay(1);
	79	} while (timeout--);
	80
	81	if (v & STAT_CLK_EN)
	82	dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	83	}
	84	}
	85
	86	static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
	87	{
	88	unsigned long flags;
	89
	90	spin_lock_irqsave(&host->lock, flags);
	91	host->imask &= ~mask;
	92	writel(host->imask, host->base + MMC_I_MASK);
	93	spin_unlock_irqrestore(&host->lock, flags);
	94	}
	95
	96	static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
	97	{
	98	unsigned long flags;
	99
	100	spin_lock_irqsave(&host->lock, flags);
	101	host->imask \|= mask;
	102	writel(host->imask, host->base + MMC_I_MASK);
	103	spin_unlock_irqrestore(&host->lock, flags);
	104	}
	105
	106	static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)
	107	{
	108	unsigned int nob = data->blocks;
3d63abe5	109	unsigned long long clks;
1da177e4 LT	110	unsigned int timeout;
	111	u32 dcmd;
	112	int i;
	113
	114	host->data = data;
	115
	116	if (data->flags & MMC_DATA_STREAM)
	117	nob = 0xffff;
	118
	119	writel(nob, host->base + MMC_NOB);
2c171bf1	120	writel(data->blksz, host->base + MMC_BLKLEN);
1da177e4	121
3d63abe5 RK	122	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	123	do_div(clks, 1000000000UL);
	124	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
1da177e4 LT	125	writel((timeout + 255) / 256, host->base + MMC_RDTO);
	126
	127	if (data->flags & MMC_DATA_READ) {
	128	host->dma_dir = DMA_FROM_DEVICE;
	129	dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;
	130	DRCMRTXMMC = 0;
	131	DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;
	132	} else {
	133	host->dma_dir = DMA_TO_DEVICE;
	134	dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;
	135	DRCMRRXMMC = 0;
	136	DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;
	137	}
	138
	139	dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;
	140
	141	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
	142	host->dma_dir);
	143
	144	for (i = 0; i < host->dma_len; i++) {
	145	if (data->flags & MMC_DATA_READ) {
	146	host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
	147	host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
	148	} else {
	149	host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
	150	host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
	151	}
	152	host->sg_cpu[i].dcmd = dcmd \| sg_dma_len(&data->sg[i]);
	153	host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
	154	sizeof(struct pxa_dma_desc);
	155	}
	156	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	157	wmb();
	158
	159	DDADR(host->dma) = host->sg_dma;
	160	DCSR(host->dma) = DCSR_RUN;
	161	}
	162
	163	static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)
	164	{
	165	WARN_ON(host->cmd != NULL);
	166	host->cmd = cmd;
	167
	168	if (cmd->flags & MMC_RSP_BUSY)
	169	cmdat \|= CMDAT_BUSY;
	170
e9225176 RK	171	#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY\|MMC_RSP_OPCODE))
e9225176 RK	172	switch (RSP_TYPE(mmc_resp_type(cmd))) {
6f949909	173	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
1da177e4 LT	174	cmdat \|= CMDAT_RESP_SHORT;
1da177e4 LT	175	break;
e9225176	176	case RSP_TYPE(MMC_RSP_R3):
1da177e4 LT	177	cmdat \|= CMDAT_RESP_R3;
1da177e4 LT	178	break;
e9225176	179	case RSP_TYPE(MMC_RSP_R2):
1da177e4 LT	180	cmdat \|= CMDAT_RESP_R2;
	181	break;
	182	default:
	183	break;
	184	}
	185
	186	writel(cmd->opcode, host->base + MMC_CMD);
	187	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	188	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	189	writel(cmdat, host->base + MMC_CMDAT);
	190	writel(host->clkrt, host->base + MMC_CLKRT);
	191
	192	writel(START_CLOCK, host->base + MMC_STRPCL);
	193
	194	pxamci_enable_irq(host, END_CMD_RES);
	195	}
	196
	197	static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)
	198	{
1da177e4 LT	199	host->mrq = NULL;
	200	host->cmd = NULL;
	201	host->data = NULL;
	202	mmc_request_done(host->mmc, mrq);
	203	}
	204
	205	static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
	206	{
	207	struct mmc_command *cmd = host->cmd;
	208	int i;
	209	u32 v;
	210
	211	if (!cmd)
	212	return 0;
	213
	214	host->cmd = NULL;
	215
	216	/*
	217	* Did I mention this is Sick. We always need to
	218	* discard the upper 8 bits of the first 16-bit word.
	219	*/
	220	v = readl(host->base + MMC_RES) & 0xffff;
	221	for (i = 0; i < 4; i++) {
	222	u32 w1 = readl(host->base + MMC_RES) & 0xffff;
	223	u32 w2 = readl(host->base + MMC_RES) & 0xffff;
	224	cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;
	225	v = w2;
	226	}
	227
	228	if (stat & STAT_TIME_OUT_RESPONSE) {
17b0429d	229	cmd->error = -ETIMEDOUT;
1da177e4 LT	230	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
	231	#ifdef CONFIG_PXA27x
	232	/*
	233	* workaround for erratum #42:
	234	* Intel PXA27x Family Processor Specification Update Rev 001
90e07d9f NP	235	* A bogus CRC error can appear if the msb of a 136 bit
90e07d9f NP	236	* response is a one.
1da177e4	237	*/
90e07d9f NP	238	if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
	239	pr_debug("ignoring CRC from command %d - risky\n", cmd->opcode);
	240	} else
1da177e4	241	#endif
17b0429d	242	cmd->error = -EILSEQ;
1da177e4 LT	243	}
	244
	245	pxamci_disable_irq(host, END_CMD_RES);
17b0429d	246	if (host->data && !cmd->error) {
1da177e4 LT	247	pxamci_enable_irq(host, DATA_TRAN_DONE);
	248	} else {
	249	pxamci_finish_request(host, host->mrq);
	250	}
	251
	252	return 1;
	253	}
	254
	255	static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
	256	{
	257	struct mmc_data *data = host->data;
	258
	259	if (!data)
	260	return 0;
	261
	262	DCSR(host->dma) = 0;
	263	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
	264	host->dma_dir);
	265
	266	if (stat & STAT_READ_TIME_OUT)
17b0429d	267	data->error = -ETIMEDOUT;
1da177e4	268	else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))
17b0429d	269	data->error = -EILSEQ;
1da177e4 LT	270
	271	/*
	272	* There appears to be a hardware design bug here. There seems to
	273	* be no way to find out how much data was transferred to the card.
	274	* This means that if there was an error on any block, we mark all
	275	* data blocks as being in error.
	276	*/
17b0429d	277	if (!data->error)
2c171bf1	278	data->bytes_xfered = data->blocks * data->blksz;
1da177e4 LT	279	else
	280	data->bytes_xfered = 0;
	281
	282	pxamci_disable_irq(host, DATA_TRAN_DONE);
	283
	284	host->data = NULL;
58741e8b	285	if (host->mrq->stop) {
1da177e4	286	pxamci_stop_clock(host);
df456f47	287	pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
1da177e4 LT	288	} else {
	289	pxamci_finish_request(host, host->mrq);
	290	}
	291
	292	return 1;
	293	}
	294
7d12e780	295	static irqreturn_t pxamci_irq(int irq, void *devid)
1da177e4 LT	296	{
	297	struct pxamci_host *host = devid;
	298	unsigned int ireg;
	299	int handled = 0;
	300
81ab570f	301	ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
1da177e4	302
1da177e4 LT	303	if (ireg) {
	304	unsigned stat = readl(host->base + MMC_STAT);
	305
d78e9079	306	pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
1da177e4 LT	307
	308	if (ireg & END_CMD_RES)
	309	handled \|= pxamci_cmd_done(host, stat);
	310	if (ireg & DATA_TRAN_DONE)
	311	handled \|= pxamci_data_done(host, stat);
	312	}
	313
	314	return IRQ_RETVAL(handled);
	315	}
	316
	317	static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)
	318	{
	319	struct pxamci_host *host = mmc_priv(mmc);
	320	unsigned int cmdat;
	321
	322	WARN_ON(host->mrq != NULL);
	323
	324	host->mrq = mrq;
	325
	326	pxamci_stop_clock(host);
	327
	328	cmdat = host->cmdat;
	329	host->cmdat &= ~CMDAT_INIT;
	330
	331	if (mrq->data) {
	332	pxamci_setup_data(host, mrq->data);
	333
	334	cmdat &= ~CMDAT_BUSY;
	335	cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;
	336	if (mrq->data->flags & MMC_DATA_WRITE)
	337	cmdat \|= CMDAT_WRITE;
	338
	339	if (mrq->data->flags & MMC_DATA_STREAM)
	340	cmdat \|= CMDAT_STREAM;
	341	}
	342
	343	pxamci_start_cmd(host, mrq->cmd, cmdat);
	344	}
	345
e619524f RP	346	static int pxamci_get_ro(struct mmc_host *mmc)
	347	{
	348	struct pxamci_host *host = mmc_priv(mmc);
	349
	350	if (host->pdata && host->pdata->get_ro)
9e86619b	351	return host->pdata->get_ro(mmc_dev(mmc));
e619524f RP	352	/* Host doesn't support read only detection so assume writeable */
	353	return 0;
	354	}
	355
1da177e4 LT	356	static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	357	{
	358	struct pxamci_host *host = mmc_priv(mmc);
	359
1da177e4 LT	360	if (ios->clock) {
	361	unsigned int clk = CLOCKRATE / ios->clock;
	362	if (CLOCKRATE / clk > ios->clock)
	363	clk <<= 1;
	364	host->clkrt = fls(clk) - 1;
7053acbd	365	pxa_set_cken(CKEN_MMC, 1);
1da177e4 LT	366
	367	/*
	368	* we write clkrt on the next command
	369	*/
	370	} else {
	371	pxamci_stop_clock(host);
7053acbd	372	pxa_set_cken(CKEN_MMC, 0);
1da177e4 LT	373	}
	374
	375	if (host->power_mode != ios->power_mode) {
	376	host->power_mode = ios->power_mode;
	377
	378	if (host->pdata && host->pdata->setpower)
9e86619b	379	host->pdata->setpower(mmc_dev(mmc), ios->vdd);
1da177e4 LT	380
	381	if (ios->power_mode == MMC_POWER_ON)
	382	host->cmdat \|= CMDAT_INIT;
	383	}
	384
df456f47 BW	385	if (ios->bus_width == MMC_BUS_WIDTH_4)
	386	host->cmdat \|= CMDAT_SD_4DAT;
	387	else
	388	host->cmdat &= ~CMDAT_SD_4DAT;
	389
d78e9079	390	pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
c6563178	391	host->clkrt, host->cmdat);
1da177e4 LT	392	}
1da177e4 LT	393
ab7aefd0	394	static const struct mmc_host_ops pxamci_ops = {
1da177e4	395	.request = pxamci_request,
e619524f	396	.get_ro = pxamci_get_ro,
1da177e4 LT	397	.set_ios = pxamci_set_ios,
	398	};
	399
7d12e780	400	static void pxamci_dma_irq(int dma, void *devid)
1da177e4 LT	401	{
	402	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	403	DCSR(dma) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	404	}
	405
7d12e780	406	static irqreturn_t pxamci_detect_irq(int irq, void *devid)
1da177e4	407	{
c26971cb RP	408	struct pxamci_host *host = mmc_priv(devid);
	409
	410	mmc_detect_change(devid, host->pdata->detect_delay);
1da177e4 LT	411	return IRQ_HANDLED;
	412	}
	413
3ae5eaec	414	static int pxamci_probe(struct platform_device *pdev)
1da177e4	415	{
1da177e4 LT	416	struct mmc_host *mmc;
	417	struct pxamci_host *host = NULL;
	418	struct resource *r;
	419	int ret, irq;
	420
	421	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	422	irq = platform_get_irq(pdev, 0);
48944738	423	if (!r \|\| irq < 0)
1da177e4 LT	424	return -ENXIO;
	425
	426	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	427	if (!r)
	428	return -EBUSY;
	429
3ae5eaec	430	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
1da177e4 LT	431	if (!mmc) {
	432	ret = -ENOMEM;
	433	goto out;
	434	}
	435
	436	mmc->ops = &pxamci_ops;
	437	mmc->f_min = CLOCKRATE_MIN;
	438	mmc->f_max = CLOCKRATE_MAX;
	439
	440	/*
	441	* We can do SG-DMA, but we don't because we never know how much
	442	* data we successfully wrote to the card.
	443	*/
	444	mmc->max_phys_segs = NR_SG;
	445
	446	/*
	447	* Our hardware DMA can handle a maximum of one page per SG entry.
	448	*/
	449	mmc->max_seg_size = PAGE_SIZE;
	450
fe4a3c7a	451	/*
fe2dc44e	452	* Block length register is only 10 bits before PXA27x.
fe4a3c7a	453	*/
fe2dc44e	454	mmc->max_blk_size = (cpu_is_pxa21x() \|\| cpu_is_pxa25x()) ? 1023 : 2048;
fe4a3c7a	455
55db890a PO	456	/*
	457	* Block count register is 16 bits.
	458	*/
	459	mmc->max_blk_count = 65535;
	460
1da177e4 LT	461	host = mmc_priv(mmc);
	462	host->mmc = mmc;
	463	host->dma = -1;
	464	host->pdata = pdev->dev.platform_data;
	465	mmc->ocr_avail = host->pdata ?
	466	host->pdata->ocr_mask :
	467	MMC_VDD_32_33\|MMC_VDD_33_34;
df456f47 BW	468	mmc->caps = 0;
	469	if (!cpu_is_pxa21x() && !cpu_is_pxa25x())
	470	mmc->caps \|= MMC_CAP_4_BIT_DATA;
1da177e4	471
3ae5eaec	472	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
1da177e4 LT	473	if (!host->sg_cpu) {
	474	ret = -ENOMEM;
	475	goto out;
	476	}
	477
	478	spin_lock_init(&host->lock);
	479	host->res = r;
	480	host->irq = irq;
	481	host->imask = MMC_I_MASK_ALL;
	482
	483	host->base = ioremap(r->start, SZ_4K);
	484	if (!host->base) {
	485	ret = -ENOMEM;
	486	goto out;
	487	}
	488
	489	/*
	490	* Ensure that the host controller is shut down, and setup
	491	* with our defaults.
	492	*/
	493	pxamci_stop_clock(host);
	494	writel(0, host->base + MMC_SPI);
	495	writel(64, host->base + MMC_RESTO);
	496	writel(host->imask, host->base + MMC_I_MASK);
	497
	498	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
	499	pxamci_dma_irq, host);
	500	if (host->dma < 0) {
	501	ret = -EBUSY;
	502	goto out;
	503	}
	504
	505	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	506	if (ret)
	507	goto out;
	508
3ae5eaec	509	platform_set_drvdata(pdev, mmc);
1da177e4 LT	510
1da177e4 LT	511	if (host->pdata && host->pdata->init)
3ae5eaec	512	host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
1da177e4 LT	513
	514	mmc_add_host(mmc);
	515
	516	return 0;
	517
	518	out:
	519	if (host) {
	520	if (host->dma >= 0)
	521	pxa_free_dma(host->dma);
	522	if (host->base)
	523	iounmap(host->base);
	524	if (host->sg_cpu)
3ae5eaec	525	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	526	}
	527	if (mmc)
	528	mmc_free_host(mmc);
	529	release_resource(r);
	530	return ret;
	531	}
	532
3ae5eaec	533	static int pxamci_remove(struct platform_device *pdev)
1da177e4	534	{
3ae5eaec	535	struct mmc_host *mmc = platform_get_drvdata(pdev);
1da177e4	536
3ae5eaec	537	platform_set_drvdata(pdev, NULL);
1da177e4 LT	538
	539	if (mmc) {
	540	struct pxamci_host *host = mmc_priv(mmc);
	541
	542	if (host->pdata && host->pdata->exit)
3ae5eaec	543	host->pdata->exit(&pdev->dev, mmc);
1da177e4 LT	544
	545	mmc_remove_host(mmc);
	546
	547	pxamci_stop_clock(host);
	548	writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|
	549	END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,
	550	host->base + MMC_I_MASK);
	551
	552	DRCMRRXMMC = 0;
	553	DRCMRTXMMC = 0;
	554
	555	free_irq(host->irq, host);
	556	pxa_free_dma(host->dma);
	557	iounmap(host->base);
3ae5eaec	558	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	559
	560	release_resource(host->res);
	561
	562	mmc_free_host(mmc);
	563	}
	564	return 0;
	565	}
	566
	567	#ifdef CONFIG_PM
3ae5eaec	568	static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
1da177e4	569	{
3ae5eaec	570	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	571	int ret = 0;
1da177e4 LT	572
9480e307	573	if (mmc)
1da177e4 LT	574	ret = mmc_suspend_host(mmc, state);
	575
	576	return ret;
	577	}
	578
3ae5eaec	579	static int pxamci_resume(struct platform_device *dev)
1da177e4	580	{
3ae5eaec	581	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	582	int ret = 0;
1da177e4 LT	583
9480e307	584	if (mmc)
1da177e4 LT	585	ret = mmc_resume_host(mmc);
	586
	587	return ret;
	588	}
	589	#else
	590	#define pxamci_suspend NULL
	591	#define pxamci_resume NULL
	592	#endif
	593
3ae5eaec	594	static struct platform_driver pxamci_driver = {
1da177e4 LT	595	.probe = pxamci_probe,
	596	.remove = pxamci_remove,
	597	.suspend = pxamci_suspend,
	598	.resume = pxamci_resume,
3ae5eaec RK	599	.driver = {
	600	.name = DRIVER_NAME,
	601	},
1da177e4 LT	602	};
	603
	604	static int __init pxamci_init(void)
	605	{
3ae5eaec	606	return platform_driver_register(&pxamci_driver);
1da177e4 LT	607	}
	608
	609	static void __exit pxamci_exit(void)
	610	{
3ae5eaec	611	platform_driver_unregister(&pxamci_driver);
1da177e4 LT	612	}
	613
	614	module_init(pxamci_init);
	615	module_exit(pxamci_exit);
	616
	617	MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
	618	MODULE_LICENSE("GPL");