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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
d900f712 DK |
20 | #include <linux/debugfs.h> |
21 | #include <linux/seq_file.h> | |
a45c6cb8 MC |
22 | #include <linux/interrupt.h> |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/workqueue.h> | |
27 | #include <linux/timer.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/mmc/host.h> | |
13189e78 | 30 | #include <linux/mmc/core.h> |
a45c6cb8 MC |
31 | #include <linux/io.h> |
32 | #include <linux/semaphore.h> | |
33 | #include <mach/dma.h> | |
34 | #include <mach/hardware.h> | |
35 | #include <mach/board.h> | |
36 | #include <mach/mmc.h> | |
37 | #include <mach/cpu.h> | |
38 | ||
39 | /* OMAP HSMMC Host Controller Registers */ | |
40 | #define OMAP_HSMMC_SYSCONFIG 0x0010 | |
11dd62a7 | 41 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
42 | #define OMAP_HSMMC_CON 0x002C |
43 | #define OMAP_HSMMC_BLK 0x0104 | |
44 | #define OMAP_HSMMC_ARG 0x0108 | |
45 | #define OMAP_HSMMC_CMD 0x010C | |
46 | #define OMAP_HSMMC_RSP10 0x0110 | |
47 | #define OMAP_HSMMC_RSP32 0x0114 | |
48 | #define OMAP_HSMMC_RSP54 0x0118 | |
49 | #define OMAP_HSMMC_RSP76 0x011C | |
50 | #define OMAP_HSMMC_DATA 0x0120 | |
51 | #define OMAP_HSMMC_HCTL 0x0128 | |
52 | #define OMAP_HSMMC_SYSCTL 0x012C | |
53 | #define OMAP_HSMMC_STAT 0x0130 | |
54 | #define OMAP_HSMMC_IE 0x0134 | |
55 | #define OMAP_HSMMC_ISE 0x0138 | |
56 | #define OMAP_HSMMC_CAPA 0x0140 | |
57 | ||
58 | #define VS18 (1 << 26) | |
59 | #define VS30 (1 << 25) | |
60 | #define SDVS18 (0x5 << 9) | |
61 | #define SDVS30 (0x6 << 9) | |
eb250826 | 62 | #define SDVS33 (0x7 << 9) |
1b331e69 | 63 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
64 | #define SDVSCLR 0xFFFFF1FF |
65 | #define SDVSDET 0x00000400 | |
66 | #define AUTOIDLE 0x1 | |
67 | #define SDBP (1 << 8) | |
68 | #define DTO 0xe | |
69 | #define ICE 0x1 | |
70 | #define ICS 0x2 | |
71 | #define CEN (1 << 2) | |
72 | #define CLKD_MASK 0x0000FFC0 | |
73 | #define CLKD_SHIFT 6 | |
74 | #define DTO_MASK 0x000F0000 | |
75 | #define DTO_SHIFT 16 | |
76 | #define INT_EN_MASK 0x307F0033 | |
ccdfe3a6 AG |
77 | #define BWR_ENABLE (1 << 4) |
78 | #define BRR_ENABLE (1 << 5) | |
a45c6cb8 MC |
79 | #define INIT_STREAM (1 << 1) |
80 | #define DP_SELECT (1 << 21) | |
81 | #define DDIR (1 << 4) | |
82 | #define DMA_EN 0x1 | |
83 | #define MSBS (1 << 5) | |
84 | #define BCE (1 << 1) | |
85 | #define FOUR_BIT (1 << 1) | |
73153010 | 86 | #define DW8 (1 << 5) |
a45c6cb8 MC |
87 | #define CC 0x1 |
88 | #define TC 0x02 | |
89 | #define OD 0x1 | |
90 | #define ERR (1 << 15) | |
91 | #define CMD_TIMEOUT (1 << 16) | |
92 | #define DATA_TIMEOUT (1 << 20) | |
93 | #define CMD_CRC (1 << 17) | |
94 | #define DATA_CRC (1 << 21) | |
95 | #define CARD_ERR (1 << 28) | |
96 | #define STAT_CLEAR 0xFFFFFFFF | |
97 | #define INIT_STREAM_CMD 0x00000000 | |
98 | #define DUAL_VOLT_OCR_BIT 7 | |
99 | #define SRC (1 << 25) | |
100 | #define SRD (1 << 26) | |
11dd62a7 DK |
101 | #define SOFTRESET (1 << 1) |
102 | #define RESETDONE (1 << 0) | |
a45c6cb8 MC |
103 | |
104 | /* | |
105 | * FIXME: Most likely all the data using these _DEVID defines should come | |
106 | * from the platform_data, or implemented in controller and slot specific | |
107 | * functions. | |
108 | */ | |
109 | #define OMAP_MMC1_DEVID 0 | |
110 | #define OMAP_MMC2_DEVID 1 | |
f3e2f1dd | 111 | #define OMAP_MMC3_DEVID 2 |
a45c6cb8 | 112 | |
a45c6cb8 MC |
113 | #define MMC_TIMEOUT_MS 20 |
114 | #define OMAP_MMC_MASTER_CLOCK 96000000 | |
115 | #define DRIVER_NAME "mmci-omap-hs" | |
116 | ||
dd498eff DK |
117 | /* Timeouts for entering power saving states on inactivity, msec */ |
118 | #define OMAP_MMC_DISABLED_TIMEOUT 100 | |
13189e78 JL |
119 | #define OMAP_MMC_SLEEP_TIMEOUT 1000 |
120 | #define OMAP_MMC_OFF_TIMEOUT 8000 | |
dd498eff | 121 | |
a45c6cb8 MC |
122 | /* |
123 | * One controller can have multiple slots, like on some omap boards using | |
124 | * omap.c controller driver. Luckily this is not currently done on any known | |
125 | * omap_hsmmc.c device. | |
126 | */ | |
127 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
128 | ||
129 | /* | |
130 | * MMC Host controller read/write API's | |
131 | */ | |
132 | #define OMAP_HSMMC_READ(base, reg) \ | |
133 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
134 | ||
135 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
136 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
137 | ||
70a3341a | 138 | struct omap_hsmmc_host { |
a45c6cb8 MC |
139 | struct device *dev; |
140 | struct mmc_host *mmc; | |
141 | struct mmc_request *mrq; | |
142 | struct mmc_command *cmd; | |
143 | struct mmc_data *data; | |
144 | struct clk *fclk; | |
145 | struct clk *iclk; | |
146 | struct clk *dbclk; | |
147 | struct semaphore sem; | |
148 | struct work_struct mmc_carddetect_work; | |
149 | void __iomem *base; | |
150 | resource_size_t mapbase; | |
4dffd7a2 AH |
151 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
152 | unsigned long flags; | |
a45c6cb8 MC |
153 | unsigned int id; |
154 | unsigned int dma_len; | |
0ccd76d4 | 155 | unsigned int dma_sg_idx; |
a45c6cb8 | 156 | unsigned char bus_mode; |
a3621465 | 157 | unsigned char power_mode; |
a45c6cb8 MC |
158 | u32 *buffer; |
159 | u32 bytesleft; | |
160 | int suspended; | |
161 | int irq; | |
a45c6cb8 | 162 | int use_dma, dma_ch; |
f3e2f1dd | 163 | int dma_line_tx, dma_line_rx; |
a45c6cb8 MC |
164 | int slot_id; |
165 | int dbclk_enabled; | |
4a694dc9 | 166 | int response_busy; |
11dd62a7 | 167 | int context_loss; |
dd498eff | 168 | int dpm_state; |
623821f7 | 169 | int vdd; |
b62f6228 AH |
170 | int protect_card; |
171 | int reqs_blocked; | |
11dd62a7 | 172 | |
a45c6cb8 MC |
173 | struct omap_mmc_platform_data *pdata; |
174 | }; | |
175 | ||
176 | /* | |
177 | * Stop clock to the card | |
178 | */ | |
70a3341a | 179 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
180 | { |
181 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
182 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
183 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
184 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); | |
185 | } | |
186 | ||
11dd62a7 DK |
187 | #ifdef CONFIG_PM |
188 | ||
189 | /* | |
190 | * Restore the MMC host context, if it was lost as result of a | |
191 | * power state change. | |
192 | */ | |
70a3341a | 193 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
194 | { |
195 | struct mmc_ios *ios = &host->mmc->ios; | |
196 | struct omap_mmc_platform_data *pdata = host->pdata; | |
197 | int context_loss = 0; | |
198 | u32 hctl, capa, con; | |
199 | u16 dsor = 0; | |
200 | unsigned long timeout; | |
201 | ||
202 | if (pdata->get_context_loss_count) { | |
203 | context_loss = pdata->get_context_loss_count(host->dev); | |
204 | if (context_loss < 0) | |
205 | return 1; | |
206 | } | |
207 | ||
208 | dev_dbg(mmc_dev(host->mmc), "context was %slost\n", | |
209 | context_loss == host->context_loss ? "not " : ""); | |
210 | if (host->context_loss == context_loss) | |
211 | return 1; | |
212 | ||
213 | /* Wait for hardware reset */ | |
214 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
215 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
216 | && time_before(jiffies, timeout)) | |
217 | ; | |
218 | ||
219 | /* Do software reset */ | |
220 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); | |
221 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
222 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
223 | && time_before(jiffies, timeout)) | |
224 | ; | |
225 | ||
226 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, | |
227 | OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); | |
228 | ||
229 | if (host->id == OMAP_MMC1_DEVID) { | |
230 | if (host->power_mode != MMC_POWER_OFF && | |
231 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
232 | hctl = SDVS18; | |
233 | else | |
234 | hctl = SDVS30; | |
235 | capa = VS30 | VS18; | |
236 | } else { | |
237 | hctl = SDVS18; | |
238 | capa = VS18; | |
239 | } | |
240 | ||
241 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
242 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
243 | ||
244 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
245 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
246 | ||
247 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
248 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
249 | ||
250 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
251 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
252 | && time_before(jiffies, timeout)) | |
253 | ; | |
254 | ||
255 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
256 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
257 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
258 | ||
259 | /* Do not initialize card-specific things if the power is off */ | |
260 | if (host->power_mode == MMC_POWER_OFF) | |
261 | goto out; | |
262 | ||
263 | con = OMAP_HSMMC_READ(host->base, CON); | |
264 | switch (ios->bus_width) { | |
265 | case MMC_BUS_WIDTH_8: | |
266 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
267 | break; | |
268 | case MMC_BUS_WIDTH_4: | |
269 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
270 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
271 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
272 | break; | |
273 | case MMC_BUS_WIDTH_1: | |
274 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
275 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
276 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
277 | break; | |
278 | } | |
279 | ||
280 | if (ios->clock) { | |
281 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
282 | if (dsor < 1) | |
283 | dsor = 1; | |
284 | ||
285 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
286 | dsor++; | |
287 | ||
288 | if (dsor > 250) | |
289 | dsor = 250; | |
290 | } | |
291 | ||
292 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
293 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
294 | OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); | |
295 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
296 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
297 | ||
298 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
299 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
300 | && time_before(jiffies, timeout)) | |
301 | ; | |
302 | ||
303 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
304 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
305 | ||
306 | con = OMAP_HSMMC_READ(host->base, CON); | |
307 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
308 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
309 | else | |
310 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
311 | out: | |
312 | host->context_loss = context_loss; | |
313 | ||
314 | dev_dbg(mmc_dev(host->mmc), "context is restored\n"); | |
315 | return 0; | |
316 | } | |
317 | ||
318 | /* | |
319 | * Save the MMC host context (store the number of power state changes so far). | |
320 | */ | |
70a3341a | 321 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
322 | { |
323 | struct omap_mmc_platform_data *pdata = host->pdata; | |
324 | int context_loss; | |
325 | ||
326 | if (pdata->get_context_loss_count) { | |
327 | context_loss = pdata->get_context_loss_count(host->dev); | |
328 | if (context_loss < 0) | |
329 | return; | |
330 | host->context_loss = context_loss; | |
331 | } | |
332 | } | |
333 | ||
334 | #else | |
335 | ||
70a3341a | 336 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
337 | { |
338 | return 0; | |
339 | } | |
340 | ||
70a3341a | 341 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
342 | { |
343 | } | |
344 | ||
345 | #endif | |
346 | ||
a45c6cb8 MC |
347 | /* |
348 | * Send init stream sequence to card | |
349 | * before sending IDLE command | |
350 | */ | |
70a3341a | 351 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
352 | { |
353 | int reg = 0; | |
354 | unsigned long timeout; | |
355 | ||
b62f6228 AH |
356 | if (host->protect_card) |
357 | return; | |
358 | ||
a45c6cb8 MC |
359 | disable_irq(host->irq); |
360 | OMAP_HSMMC_WRITE(host->base, CON, | |
361 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
362 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
363 | ||
364 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
365 | while ((reg != CC) && time_before(jiffies, timeout)) | |
366 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
367 | ||
368 | OMAP_HSMMC_WRITE(host->base, CON, | |
369 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
370 | |
371 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
372 | OMAP_HSMMC_READ(host->base, STAT); | |
373 | ||
a45c6cb8 MC |
374 | enable_irq(host->irq); |
375 | } | |
376 | ||
377 | static inline | |
70a3341a | 378 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
379 | { |
380 | int r = 1; | |
381 | ||
191d1f1d DK |
382 | if (mmc_slot(host).get_cover_state) |
383 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
384 | return r; |
385 | } | |
386 | ||
387 | static ssize_t | |
70a3341a | 388 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
389 | char *buf) |
390 | { | |
391 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 392 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 393 | |
70a3341a DK |
394 | return sprintf(buf, "%s\n", |
395 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
396 | } |
397 | ||
70a3341a | 398 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
399 | |
400 | static ssize_t | |
70a3341a | 401 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
402 | char *buf) |
403 | { | |
404 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 405 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 406 | |
191d1f1d | 407 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
408 | } |
409 | ||
70a3341a | 410 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
411 | |
412 | /* | |
413 | * Configure the response type and send the cmd. | |
414 | */ | |
415 | static void | |
70a3341a | 416 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
417 | struct mmc_data *data) |
418 | { | |
419 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
420 | ||
421 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", | |
422 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); | |
423 | host->cmd = cmd; | |
424 | ||
425 | /* | |
426 | * Clear status bits and enable interrupts | |
427 | */ | |
428 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
429 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
ccdfe3a6 AG |
430 | |
431 | if (host->use_dma) | |
432 | OMAP_HSMMC_WRITE(host->base, IE, | |
433 | INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE)); | |
434 | else | |
435 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 | 436 | |
4a694dc9 | 437 | host->response_busy = 0; |
a45c6cb8 MC |
438 | if (cmd->flags & MMC_RSP_PRESENT) { |
439 | if (cmd->flags & MMC_RSP_136) | |
440 | resptype = 1; | |
4a694dc9 AH |
441 | else if (cmd->flags & MMC_RSP_BUSY) { |
442 | resptype = 3; | |
443 | host->response_busy = 1; | |
444 | } else | |
a45c6cb8 MC |
445 | resptype = 2; |
446 | } | |
447 | ||
448 | /* | |
449 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
450 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
451 | * a val of 0x3, rest 0x0. | |
452 | */ | |
453 | if (cmd == host->mrq->stop) | |
454 | cmdtype = 0x3; | |
455 | ||
456 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
457 | ||
458 | if (data) { | |
459 | cmdreg |= DP_SELECT | MSBS | BCE; | |
460 | if (data->flags & MMC_DATA_READ) | |
461 | cmdreg |= DDIR; | |
462 | else | |
463 | cmdreg &= ~(DDIR); | |
464 | } | |
465 | ||
466 | if (host->use_dma) | |
467 | cmdreg |= DMA_EN; | |
468 | ||
4dffd7a2 AH |
469 | /* |
470 | * In an interrupt context (i.e. STOP command), the spinlock is unlocked | |
471 | * by the interrupt handler, otherwise (i.e. for a new request) it is | |
472 | * unlocked here. | |
473 | */ | |
474 | if (!in_interrupt()) | |
475 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
476 | ||
a45c6cb8 MC |
477 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
478 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
479 | } | |
480 | ||
0ccd76d4 | 481 | static int |
70a3341a | 482 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
483 | { |
484 | if (data->flags & MMC_DATA_WRITE) | |
485 | return DMA_TO_DEVICE; | |
486 | else | |
487 | return DMA_FROM_DEVICE; | |
488 | } | |
489 | ||
a45c6cb8 MC |
490 | /* |
491 | * Notify the transfer complete to MMC core | |
492 | */ | |
493 | static void | |
70a3341a | 494 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 495 | { |
4a694dc9 AH |
496 | if (!data) { |
497 | struct mmc_request *mrq = host->mrq; | |
498 | ||
23050103 AH |
499 | /* TC before CC from CMD6 - don't know why, but it happens */ |
500 | if (host->cmd && host->cmd->opcode == 6 && | |
501 | host->response_busy) { | |
502 | host->response_busy = 0; | |
503 | return; | |
504 | } | |
505 | ||
4a694dc9 | 506 | host->mrq = NULL; |
4a694dc9 AH |
507 | mmc_request_done(host->mmc, mrq); |
508 | return; | |
509 | } | |
510 | ||
a45c6cb8 MC |
511 | host->data = NULL; |
512 | ||
513 | if (host->use_dma && host->dma_ch != -1) | |
514 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
70a3341a | 515 | omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 MC |
516 | |
517 | if (!data->error) | |
518 | data->bytes_xfered += data->blocks * (data->blksz); | |
519 | else | |
520 | data->bytes_xfered = 0; | |
521 | ||
522 | if (!data->stop) { | |
523 | host->mrq = NULL; | |
524 | mmc_request_done(host->mmc, data->mrq); | |
525 | return; | |
526 | } | |
70a3341a | 527 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
528 | } |
529 | ||
530 | /* | |
531 | * Notify the core about command completion | |
532 | */ | |
533 | static void | |
70a3341a | 534 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
535 | { |
536 | host->cmd = NULL; | |
537 | ||
538 | if (cmd->flags & MMC_RSP_PRESENT) { | |
539 | if (cmd->flags & MMC_RSP_136) { | |
540 | /* response type 2 */ | |
541 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
542 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
543 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
544 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
545 | } else { | |
546 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
547 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
548 | } | |
549 | } | |
4a694dc9 | 550 | if ((host->data == NULL && !host->response_busy) || cmd->error) { |
a45c6cb8 MC |
551 | host->mrq = NULL; |
552 | mmc_request_done(host->mmc, cmd->mrq); | |
553 | } | |
554 | } | |
555 | ||
556 | /* | |
557 | * DMA clean up for command errors | |
558 | */ | |
70a3341a | 559 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 560 | { |
82788ff5 | 561 | host->data->error = errno; |
a45c6cb8 MC |
562 | |
563 | if (host->use_dma && host->dma_ch != -1) { | |
564 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, | |
70a3341a | 565 | omap_hsmmc_get_dma_dir(host, host->data)); |
a45c6cb8 MC |
566 | omap_free_dma(host->dma_ch); |
567 | host->dma_ch = -1; | |
568 | up(&host->sem); | |
569 | } | |
570 | host->data = NULL; | |
a45c6cb8 MC |
571 | } |
572 | ||
573 | /* | |
574 | * Readable error output | |
575 | */ | |
576 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 577 | static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
578 | { |
579 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 580 | static const char *omap_hsmmc_status_bits[] = { |
a45c6cb8 MC |
581 | "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", |
582 | "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", | |
583 | "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", | |
584 | "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" | |
585 | }; | |
586 | char res[256]; | |
587 | char *buf = res; | |
588 | int len, i; | |
589 | ||
590 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
591 | buf += len; | |
592 | ||
70a3341a | 593 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 594 | if (status & (1 << i)) { |
70a3341a | 595 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
596 | buf += len; |
597 | } | |
598 | ||
599 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); | |
600 | } | |
601 | #endif /* CONFIG_MMC_DEBUG */ | |
602 | ||
3ebf74b1 JP |
603 | /* |
604 | * MMC controller internal state machines reset | |
605 | * | |
606 | * Used to reset command or data internal state machines, using respectively | |
607 | * SRC or SRD bit of SYSCTL register | |
608 | * Can be called from interrupt context | |
609 | */ | |
70a3341a DK |
610 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
611 | unsigned long bit) | |
3ebf74b1 JP |
612 | { |
613 | unsigned long i = 0; | |
614 | unsigned long limit = (loops_per_jiffy * | |
615 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
616 | ||
617 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
618 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
619 | ||
620 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && | |
621 | (i++ < limit)) | |
622 | cpu_relax(); | |
623 | ||
624 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
625 | dev_err(mmc_dev(host->mmc), | |
626 | "Timeout waiting on controller reset in %s\n", | |
627 | __func__); | |
628 | } | |
a45c6cb8 MC |
629 | |
630 | /* | |
631 | * MMC controller IRQ handler | |
632 | */ | |
70a3341a | 633 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) |
a45c6cb8 | 634 | { |
70a3341a | 635 | struct omap_hsmmc_host *host = dev_id; |
a45c6cb8 MC |
636 | struct mmc_data *data; |
637 | int end_cmd = 0, end_trans = 0, status; | |
638 | ||
4dffd7a2 AH |
639 | spin_lock(&host->irq_lock); |
640 | ||
4a694dc9 | 641 | if (host->mrq == NULL) { |
a45c6cb8 MC |
642 | OMAP_HSMMC_WRITE(host->base, STAT, |
643 | OMAP_HSMMC_READ(host->base, STAT)); | |
00adadc1 KH |
644 | /* Flush posted write */ |
645 | OMAP_HSMMC_READ(host->base, STAT); | |
4dffd7a2 | 646 | spin_unlock(&host->irq_lock); |
a45c6cb8 MC |
647 | return IRQ_HANDLED; |
648 | } | |
649 | ||
650 | data = host->data; | |
651 | status = OMAP_HSMMC_READ(host->base, STAT); | |
652 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); | |
653 | ||
654 | if (status & ERR) { | |
655 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 656 | omap_hsmmc_report_irq(host, status); |
a45c6cb8 MC |
657 | #endif |
658 | if ((status & CMD_TIMEOUT) || | |
659 | (status & CMD_CRC)) { | |
660 | if (host->cmd) { | |
661 | if (status & CMD_TIMEOUT) { | |
70a3341a DK |
662 | omap_hsmmc_reset_controller_fsm(host, |
663 | SRC); | |
a45c6cb8 MC |
664 | host->cmd->error = -ETIMEDOUT; |
665 | } else { | |
666 | host->cmd->error = -EILSEQ; | |
667 | } | |
668 | end_cmd = 1; | |
669 | } | |
4a694dc9 AH |
670 | if (host->data || host->response_busy) { |
671 | if (host->data) | |
70a3341a DK |
672 | omap_hsmmc_dma_cleanup(host, |
673 | -ETIMEDOUT); | |
4a694dc9 | 674 | host->response_busy = 0; |
70a3341a | 675 | omap_hsmmc_reset_controller_fsm(host, SRD); |
c232f457 | 676 | } |
a45c6cb8 MC |
677 | } |
678 | if ((status & DATA_TIMEOUT) || | |
679 | (status & DATA_CRC)) { | |
4a694dc9 AH |
680 | if (host->data || host->response_busy) { |
681 | int err = (status & DATA_TIMEOUT) ? | |
682 | -ETIMEDOUT : -EILSEQ; | |
683 | ||
684 | if (host->data) | |
70a3341a | 685 | omap_hsmmc_dma_cleanup(host, err); |
a45c6cb8 | 686 | else |
4a694dc9 AH |
687 | host->mrq->cmd->error = err; |
688 | host->response_busy = 0; | |
70a3341a | 689 | omap_hsmmc_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
690 | end_trans = 1; |
691 | } | |
692 | } | |
693 | if (status & CARD_ERR) { | |
694 | dev_dbg(mmc_dev(host->mmc), | |
695 | "Ignoring card err CMD%d\n", host->cmd->opcode); | |
696 | if (host->cmd) | |
697 | end_cmd = 1; | |
698 | if (host->data) | |
699 | end_trans = 1; | |
700 | } | |
701 | } | |
702 | ||
703 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
00adadc1 KH |
704 | /* Flush posted write */ |
705 | OMAP_HSMMC_READ(host->base, STAT); | |
a45c6cb8 | 706 | |
a8fe29d8 | 707 | if (end_cmd || ((status & CC) && host->cmd)) |
70a3341a | 708 | omap_hsmmc_cmd_done(host, host->cmd); |
0a40e647 | 709 | if ((end_trans || (status & TC)) && host->mrq) |
70a3341a | 710 | omap_hsmmc_xfer_done(host, data); |
a45c6cb8 | 711 | |
4dffd7a2 AH |
712 | spin_unlock(&host->irq_lock); |
713 | ||
a45c6cb8 MC |
714 | return IRQ_HANDLED; |
715 | } | |
716 | ||
70a3341a | 717 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
718 | { |
719 | unsigned long i; | |
720 | ||
721 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
722 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
723 | for (i = 0; i < loops_per_jiffy; i++) { | |
724 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
725 | break; | |
726 | cpu_relax(); | |
727 | } | |
728 | } | |
729 | ||
a45c6cb8 | 730 | /* |
eb250826 DB |
731 | * Switch MMC interface voltage ... only relevant for MMC1. |
732 | * | |
733 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
734 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
735 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 736 | */ |
70a3341a | 737 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
738 | { |
739 | u32 reg_val = 0; | |
740 | int ret; | |
741 | ||
742 | /* Disable the clocks */ | |
743 | clk_disable(host->fclk); | |
744 | clk_disable(host->iclk); | |
745 | clk_disable(host->dbclk); | |
746 | ||
747 | /* Turn the power off */ | |
748 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
749 | if (ret != 0) | |
750 | goto err; | |
751 | ||
752 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
753 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); | |
754 | if (ret != 0) | |
755 | goto err; | |
756 | ||
757 | clk_enable(host->fclk); | |
758 | clk_enable(host->iclk); | |
759 | clk_enable(host->dbclk); | |
760 | ||
761 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
762 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
763 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 764 | |
a45c6cb8 MC |
765 | /* |
766 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
767 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 768 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 769 | * |
eb250826 DB |
770 | * Cope with a bit of slop in the range ... per data sheets: |
771 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
772 | * but recommended values are 1.71V to 1.89V | |
773 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
774 | * but recommended values are 2.7V to 3.3V | |
775 | * | |
776 | * Board setup code shouldn't permit anything very out-of-range. | |
777 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
778 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 779 | */ |
eb250826 | 780 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 781 | reg_val |= SDVS18; |
eb250826 DB |
782 | else |
783 | reg_val |= SDVS30; | |
a45c6cb8 MC |
784 | |
785 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 786 | set_sd_bus_power(host); |
a45c6cb8 MC |
787 | |
788 | return 0; | |
789 | err: | |
790 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
791 | return ret; | |
792 | } | |
793 | ||
b62f6228 AH |
794 | /* Protect the card while the cover is open */ |
795 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
796 | { | |
797 | if (!mmc_slot(host).get_cover_state) | |
798 | return; | |
799 | ||
800 | host->reqs_blocked = 0; | |
801 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
802 | if (host->protect_card) { | |
803 | printk(KERN_INFO "%s: cover is closed, " | |
804 | "card is now accessible\n", | |
805 | mmc_hostname(host->mmc)); | |
806 | host->protect_card = 0; | |
807 | } | |
808 | } else { | |
809 | if (!host->protect_card) { | |
810 | printk(KERN_INFO "%s: cover is open, " | |
811 | "card is now inaccessible\n", | |
812 | mmc_hostname(host->mmc)); | |
813 | host->protect_card = 1; | |
814 | } | |
815 | } | |
816 | } | |
817 | ||
a45c6cb8 MC |
818 | /* |
819 | * Work Item to notify the core about card insertion/removal | |
820 | */ | |
70a3341a | 821 | static void omap_hsmmc_detect(struct work_struct *work) |
a45c6cb8 | 822 | { |
70a3341a DK |
823 | struct omap_hsmmc_host *host = |
824 | container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); | |
249d0fa9 | 825 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
826 | int carddetect; |
827 | ||
828 | if (host->suspended) | |
829 | return; | |
830 | ||
831 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
249d0fa9 | 832 | |
191d1f1d | 833 | if (slot->card_detect) |
a6b2240d | 834 | carddetect = slot->card_detect(slot->card_detect_irq); |
b62f6228 AH |
835 | else { |
836 | omap_hsmmc_protect_card(host); | |
a6b2240d | 837 | carddetect = -ENOSYS; |
b62f6228 | 838 | } |
a45c6cb8 | 839 | |
a6b2240d | 840 | if (carddetect) { |
a45c6cb8 MC |
841 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
842 | } else { | |
5e2ea617 | 843 | mmc_host_enable(host->mmc); |
70a3341a | 844 | omap_hsmmc_reset_controller_fsm(host, SRD); |
5e2ea617 | 845 | mmc_host_lazy_disable(host->mmc); |
70a3341a | 846 | |
a45c6cb8 MC |
847 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
848 | } | |
849 | } | |
850 | ||
851 | /* | |
852 | * ISR for handling card insertion and removal | |
853 | */ | |
70a3341a | 854 | static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) |
a45c6cb8 | 855 | { |
70a3341a | 856 | struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; |
a45c6cb8 | 857 | |
a6b2240d AH |
858 | if (host->suspended) |
859 | return IRQ_HANDLED; | |
a45c6cb8 MC |
860 | schedule_work(&host->mmc_carddetect_work); |
861 | ||
862 | return IRQ_HANDLED; | |
863 | } | |
864 | ||
70a3341a | 865 | static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
866 | struct mmc_data *data) |
867 | { | |
868 | int sync_dev; | |
869 | ||
f3e2f1dd GI |
870 | if (data->flags & MMC_DATA_WRITE) |
871 | sync_dev = host->dma_line_tx; | |
872 | else | |
873 | sync_dev = host->dma_line_rx; | |
0ccd76d4 JY |
874 | return sync_dev; |
875 | } | |
876 | ||
70a3341a | 877 | static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
878 | struct mmc_data *data, |
879 | struct scatterlist *sgl) | |
880 | { | |
881 | int blksz, nblk, dma_ch; | |
882 | ||
883 | dma_ch = host->dma_ch; | |
884 | if (data->flags & MMC_DATA_WRITE) { | |
885 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
886 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
887 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
888 | sg_dma_address(sgl), 0, 0); | |
889 | } else { | |
890 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
191d1f1d | 891 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
0ccd76d4 JY |
892 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, |
893 | sg_dma_address(sgl), 0, 0); | |
894 | } | |
895 | ||
896 | blksz = host->data->blksz; | |
897 | nblk = sg_dma_len(sgl) / blksz; | |
898 | ||
899 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
900 | blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, | |
70a3341a | 901 | omap_hsmmc_get_dma_sync_dev(host, data), |
0ccd76d4 JY |
902 | !(data->flags & MMC_DATA_WRITE)); |
903 | ||
904 | omap_start_dma(dma_ch); | |
905 | } | |
906 | ||
a45c6cb8 MC |
907 | /* |
908 | * DMA call back function | |
909 | */ | |
70a3341a | 910 | static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) |
a45c6cb8 | 911 | { |
70a3341a | 912 | struct omap_hsmmc_host *host = data; |
a45c6cb8 MC |
913 | |
914 | if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) | |
915 | dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); | |
916 | ||
917 | if (host->dma_ch < 0) | |
918 | return; | |
919 | ||
0ccd76d4 JY |
920 | host->dma_sg_idx++; |
921 | if (host->dma_sg_idx < host->dma_len) { | |
922 | /* Fire up the next transfer. */ | |
70a3341a | 923 | omap_hsmmc_config_dma_params(host, host->data, |
0ccd76d4 JY |
924 | host->data->sg + host->dma_sg_idx); |
925 | return; | |
926 | } | |
927 | ||
a45c6cb8 MC |
928 | omap_free_dma(host->dma_ch); |
929 | host->dma_ch = -1; | |
930 | /* | |
931 | * DMA Callback: run in interrupt context. | |
85b84322 | 932 | * mutex_unlock will throw a kernel warning if used. |
a45c6cb8 MC |
933 | */ |
934 | up(&host->sem); | |
935 | } | |
936 | ||
a45c6cb8 MC |
937 | /* |
938 | * Routine to configure and start DMA for the MMC card | |
939 | */ | |
70a3341a DK |
940 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
941 | struct mmc_request *req) | |
a45c6cb8 | 942 | { |
0ccd76d4 | 943 | int dma_ch = 0, ret = 0, err = 1, i; |
a45c6cb8 MC |
944 | struct mmc_data *data = req->data; |
945 | ||
0ccd76d4 | 946 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 947 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
948 | struct scatterlist *sgl; |
949 | ||
950 | sgl = data->sg + i; | |
951 | if (sgl->length % data->blksz) | |
952 | return -EINVAL; | |
953 | } | |
954 | if ((data->blksz % 4) != 0) | |
955 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
956 | * Return error for blksz which is non multiple of four. | |
957 | */ | |
958 | return -EINVAL; | |
959 | ||
a45c6cb8 MC |
960 | /* |
961 | * If for some reason the DMA transfer is still active, | |
962 | * we wait for timeout period and free the dma | |
963 | */ | |
964 | if (host->dma_ch != -1) { | |
965 | set_current_state(TASK_UNINTERRUPTIBLE); | |
966 | schedule_timeout(100); | |
967 | if (down_trylock(&host->sem)) { | |
968 | omap_free_dma(host->dma_ch); | |
969 | host->dma_ch = -1; | |
970 | up(&host->sem); | |
971 | return err; | |
972 | } | |
973 | } else { | |
974 | if (down_trylock(&host->sem)) | |
975 | return err; | |
976 | } | |
977 | ||
70a3341a DK |
978 | ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), |
979 | "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); | |
a45c6cb8 | 980 | if (ret != 0) { |
0ccd76d4 | 981 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
982 | "%s: omap_request_dma() failed with %d\n", |
983 | mmc_hostname(host->mmc), ret); | |
984 | return ret; | |
985 | } | |
986 | ||
987 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
70a3341a | 988 | data->sg_len, omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 | 989 | host->dma_ch = dma_ch; |
0ccd76d4 | 990 | host->dma_sg_idx = 0; |
a45c6cb8 | 991 | |
70a3341a | 992 | omap_hsmmc_config_dma_params(host, data, data->sg); |
a45c6cb8 | 993 | |
a45c6cb8 MC |
994 | return 0; |
995 | } | |
996 | ||
70a3341a | 997 | static void set_data_timeout(struct omap_hsmmc_host *host, |
a45c6cb8 MC |
998 | struct mmc_request *req) |
999 | { | |
1000 | unsigned int timeout, cycle_ns; | |
1001 | uint32_t reg, clkd, dto = 0; | |
1002 | ||
1003 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1004 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1005 | if (clkd == 0) | |
1006 | clkd = 1; | |
1007 | ||
1008 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
1009 | timeout = req->data->timeout_ns / cycle_ns; | |
1010 | timeout += req->data->timeout_clks; | |
1011 | if (timeout) { | |
1012 | while ((timeout & 0x80000000) == 0) { | |
1013 | dto += 1; | |
1014 | timeout <<= 1; | |
1015 | } | |
1016 | dto = 31 - dto; | |
1017 | timeout <<= 1; | |
1018 | if (timeout && dto) | |
1019 | dto += 1; | |
1020 | if (dto >= 13) | |
1021 | dto -= 13; | |
1022 | else | |
1023 | dto = 0; | |
1024 | if (dto > 14) | |
1025 | dto = 14; | |
1026 | } | |
1027 | ||
1028 | reg &= ~DTO_MASK; | |
1029 | reg |= dto << DTO_SHIFT; | |
1030 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1031 | } | |
1032 | ||
1033 | /* | |
1034 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1035 | */ | |
1036 | static int | |
70a3341a | 1037 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1038 | { |
1039 | int ret; | |
1040 | host->data = req->data; | |
1041 | ||
1042 | if (req->data == NULL) { | |
a45c6cb8 MC |
1043 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1048 | | (req->data->blocks << 16)); | |
1049 | set_data_timeout(host, req); | |
1050 | ||
a45c6cb8 | 1051 | if (host->use_dma) { |
70a3341a | 1052 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 MC |
1053 | if (ret != 0) { |
1054 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
1055 | return ret; | |
1056 | } | |
1057 | } | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * Request function. for read/write operation | |
1063 | */ | |
70a3341a | 1064 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1065 | { |
70a3341a | 1066 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1067 | int err; |
a45c6cb8 | 1068 | |
4dffd7a2 AH |
1069 | /* |
1070 | * Prevent races with the interrupt handler because of unexpected | |
1071 | * interrupts, but not if we are already in interrupt context i.e. | |
1072 | * retries. | |
1073 | */ | |
b62f6228 | 1074 | if (!in_interrupt()) { |
4dffd7a2 | 1075 | spin_lock_irqsave(&host->irq_lock, host->flags); |
b62f6228 AH |
1076 | /* |
1077 | * Protect the card from I/O if there is a possibility | |
1078 | * it can be removed. | |
1079 | */ | |
1080 | if (host->protect_card) { | |
1081 | if (host->reqs_blocked < 3) { | |
1082 | /* | |
1083 | * Ensure the controller is left in a consistent | |
1084 | * state by resetting the command and data state | |
1085 | * machines. | |
1086 | */ | |
1087 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1088 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1089 | host->reqs_blocked += 1; | |
1090 | } | |
1091 | req->cmd->error = -EBADF; | |
1092 | if (req->data) | |
1093 | req->data->error = -EBADF; | |
1094 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
1095 | mmc_request_done(mmc, req); | |
1096 | return; | |
1097 | } else if (host->reqs_blocked) | |
1098 | host->reqs_blocked = 0; | |
1099 | } | |
a45c6cb8 MC |
1100 | WARN_ON(host->mrq != NULL); |
1101 | host->mrq = req; | |
70a3341a | 1102 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1103 | if (err) { |
1104 | req->cmd->error = err; | |
1105 | if (req->data) | |
1106 | req->data->error = err; | |
1107 | host->mrq = NULL; | |
4dffd7a2 AH |
1108 | if (!in_interrupt()) |
1109 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
a3f406f8 JL |
1110 | mmc_request_done(mmc, req); |
1111 | return; | |
1112 | } | |
1113 | ||
70a3341a | 1114 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1115 | } |
1116 | ||
a45c6cb8 | 1117 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1118 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1119 | { |
70a3341a | 1120 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 MC |
1121 | u16 dsor = 0; |
1122 | unsigned long regval; | |
1123 | unsigned long timeout; | |
73153010 | 1124 | u32 con; |
a3621465 | 1125 | int do_send_init_stream = 0; |
a45c6cb8 | 1126 | |
5e2ea617 AH |
1127 | mmc_host_enable(host->mmc); |
1128 | ||
a3621465 AH |
1129 | if (ios->power_mode != host->power_mode) { |
1130 | switch (ios->power_mode) { | |
1131 | case MMC_POWER_OFF: | |
1132 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1133 | 0, 0); | |
623821f7 | 1134 | host->vdd = 0; |
a3621465 AH |
1135 | break; |
1136 | case MMC_POWER_UP: | |
1137 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1138 | 1, ios->vdd); | |
623821f7 | 1139 | host->vdd = ios->vdd; |
a3621465 AH |
1140 | break; |
1141 | case MMC_POWER_ON: | |
1142 | do_send_init_stream = 1; | |
1143 | break; | |
1144 | } | |
1145 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1146 | } |
1147 | ||
dd498eff DK |
1148 | /* FIXME: set registers based only on changes to ios */ |
1149 | ||
73153010 | 1150 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1151 | switch (mmc->ios.bus_width) { |
73153010 JL |
1152 | case MMC_BUS_WIDTH_8: |
1153 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
1154 | break; | |
a45c6cb8 | 1155 | case MMC_BUS_WIDTH_4: |
73153010 | 1156 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1157 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1158 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
1159 | break; | |
1160 | case MMC_BUS_WIDTH_1: | |
73153010 | 1161 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1162 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1163 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
1164 | break; | |
1165 | } | |
1166 | ||
1167 | if (host->id == OMAP_MMC1_DEVID) { | |
eb250826 DB |
1168 | /* Only MMC1 can interface at 3V without some flavor |
1169 | * of external transceiver; but they all handle 1.8V. | |
1170 | */ | |
a45c6cb8 MC |
1171 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1172 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { | |
1173 | /* | |
1174 | * The mmc_select_voltage fn of the core does | |
1175 | * not seem to set the power_mode to | |
1176 | * MMC_POWER_UP upon recalculating the voltage. | |
1177 | * vdd 1.8v. | |
1178 | */ | |
70a3341a DK |
1179 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1180 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1181 | "Switch operation failed\n"); |
1182 | } | |
1183 | } | |
1184 | ||
1185 | if (ios->clock) { | |
1186 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
1187 | if (dsor < 1) | |
1188 | dsor = 1; | |
1189 | ||
1190 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
1191 | dsor++; | |
1192 | ||
1193 | if (dsor > 250) | |
1194 | dsor = 250; | |
1195 | } | |
70a3341a | 1196 | omap_hsmmc_stop_clock(host); |
a45c6cb8 MC |
1197 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); |
1198 | regval = regval & ~(CLKD_MASK); | |
1199 | regval = regval | (dsor << 6) | (DTO << 16); | |
1200 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); | |
1201 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1202 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
1203 | ||
1204 | /* Wait till the ICS bit is set */ | |
1205 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
11dd62a7 | 1206 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS |
a45c6cb8 MC |
1207 | && time_before(jiffies, timeout)) |
1208 | msleep(1); | |
1209 | ||
1210 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1211 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
1212 | ||
a3621465 | 1213 | if (do_send_init_stream) |
a45c6cb8 MC |
1214 | send_init_stream(host); |
1215 | ||
abb28e73 | 1216 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1217 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
abb28e73 DK |
1218 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); |
1219 | else | |
1220 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
5e2ea617 | 1221 | |
dd498eff DK |
1222 | if (host->power_mode == MMC_POWER_OFF) |
1223 | mmc_host_disable(host->mmc); | |
1224 | else | |
1225 | mmc_host_lazy_disable(host->mmc); | |
a45c6cb8 MC |
1226 | } |
1227 | ||
1228 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1229 | { | |
70a3341a | 1230 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1231 | |
191d1f1d | 1232 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1233 | return -ENOSYS; |
191d1f1d | 1234 | return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq); |
a45c6cb8 MC |
1235 | } |
1236 | ||
1237 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1238 | { | |
70a3341a | 1239 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1240 | |
191d1f1d | 1241 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1242 | return -ENOSYS; |
191d1f1d | 1243 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1244 | } |
1245 | ||
70a3341a | 1246 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1247 | { |
1248 | u32 hctl, capa, value; | |
1249 | ||
1250 | /* Only MMC1 supports 3.0V */ | |
1251 | if (host->id == OMAP_MMC1_DEVID) { | |
1252 | hctl = SDVS30; | |
1253 | capa = VS30 | VS18; | |
1254 | } else { | |
1255 | hctl = SDVS18; | |
1256 | capa = VS18; | |
1257 | } | |
1258 | ||
1259 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1260 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1261 | ||
1262 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1263 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1264 | ||
1265 | /* Set the controller to AUTO IDLE mode */ | |
1266 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); | |
1267 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); | |
1268 | ||
1269 | /* Set SD bus power bit */ | |
e13bb300 | 1270 | set_sd_bus_power(host); |
1b331e69 KK |
1271 | } |
1272 | ||
dd498eff DK |
1273 | /* |
1274 | * Dynamic power saving handling, FSM: | |
13189e78 JL |
1275 | * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF |
1276 | * ^___________| | | | |
1277 | * |______________________|______________________| | |
dd498eff DK |
1278 | * |
1279 | * ENABLED: mmc host is fully functional | |
1280 | * DISABLED: fclk is off | |
13189e78 JL |
1281 | * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep |
1282 | * REGSLEEP: fclk is off, voltage regulator is asleep | |
1283 | * OFF: fclk is off, voltage regulator is off | |
dd498eff DK |
1284 | * |
1285 | * Transition handlers return the timeout for the next state transition | |
1286 | * or negative error. | |
1287 | */ | |
1288 | ||
13189e78 | 1289 | enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; |
dd498eff DK |
1290 | |
1291 | /* Handler for [ENABLED -> DISABLED] transition */ | |
70a3341a | 1292 | static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) |
dd498eff | 1293 | { |
70a3341a | 1294 | omap_hsmmc_context_save(host); |
dd498eff DK |
1295 | clk_disable(host->fclk); |
1296 | host->dpm_state = DISABLED; | |
1297 | ||
1298 | dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); | |
1299 | ||
1300 | if (host->power_mode == MMC_POWER_OFF) | |
1301 | return 0; | |
1302 | ||
13189e78 | 1303 | return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT); |
dd498eff DK |
1304 | } |
1305 | ||
13189e78 | 1306 | /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ |
70a3341a | 1307 | static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) |
dd498eff | 1308 | { |
13189e78 | 1309 | int err, new_state; |
dd498eff DK |
1310 | |
1311 | if (!mmc_try_claim_host(host->mmc)) | |
1312 | return 0; | |
1313 | ||
1314 | clk_enable(host->fclk); | |
70a3341a | 1315 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1316 | if (mmc_card_can_sleep(host->mmc)) { |
1317 | err = mmc_card_sleep(host->mmc); | |
1318 | if (err < 0) { | |
1319 | clk_disable(host->fclk); | |
1320 | mmc_release_host(host->mmc); | |
1321 | return err; | |
1322 | } | |
1323 | new_state = CARDSLEEP; | |
70a3341a | 1324 | } else { |
13189e78 | 1325 | new_state = REGSLEEP; |
70a3341a | 1326 | } |
13189e78 JL |
1327 | if (mmc_slot(host).set_sleep) |
1328 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, | |
1329 | new_state == CARDSLEEP); | |
1330 | /* FIXME: turn off bus power and perhaps interrupts too */ | |
1331 | clk_disable(host->fclk); | |
1332 | host->dpm_state = new_state; | |
1333 | ||
1334 | mmc_release_host(host->mmc); | |
1335 | ||
1336 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", | |
1337 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff DK |
1338 | |
1339 | if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || | |
1340 | mmc_slot(host).card_detect || | |
1341 | (mmc_slot(host).get_cover_state && | |
13189e78 JL |
1342 | mmc_slot(host).get_cover_state(host->dev, host->slot_id))) |
1343 | return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT); | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ | |
70a3341a | 1349 | static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) |
13189e78 JL |
1350 | { |
1351 | if (!mmc_try_claim_host(host->mmc)) | |
1352 | return 0; | |
1353 | ||
1354 | if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || | |
1355 | mmc_slot(host).card_detect || | |
1356 | (mmc_slot(host).get_cover_state && | |
1357 | mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { | |
1358 | mmc_release_host(host->mmc); | |
1359 | return 0; | |
623821f7 | 1360 | } |
dd498eff | 1361 | |
13189e78 JL |
1362 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); |
1363 | host->vdd = 0; | |
1364 | host->power_mode = MMC_POWER_OFF; | |
dd498eff | 1365 | |
13189e78 JL |
1366 | dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", |
1367 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff | 1368 | |
13189e78 | 1369 | host->dpm_state = OFF; |
dd498eff DK |
1370 | |
1371 | mmc_release_host(host->mmc); | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | /* Handler for [DISABLED -> ENABLED] transition */ | |
70a3341a | 1377 | static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) |
dd498eff DK |
1378 | { |
1379 | int err; | |
1380 | ||
1381 | err = clk_enable(host->fclk); | |
1382 | if (err < 0) | |
1383 | return err; | |
1384 | ||
70a3341a | 1385 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1386 | host->dpm_state = ENABLED; |
1387 | ||
1388 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
13189e78 | 1393 | /* Handler for [SLEEP -> ENABLED] transition */ |
70a3341a | 1394 | static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) |
dd498eff | 1395 | { |
13189e78 JL |
1396 | if (!mmc_try_claim_host(host->mmc)) |
1397 | return 0; | |
dd498eff | 1398 | |
13189e78 | 1399 | clk_enable(host->fclk); |
70a3341a | 1400 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1401 | if (mmc_slot(host).set_sleep) |
1402 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, | |
1403 | host->vdd, host->dpm_state == CARDSLEEP); | |
1404 | if (mmc_card_can_sleep(host->mmc)) | |
1405 | mmc_card_awake(host->mmc); | |
1406 | ||
1407 | dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", | |
1408 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff DK |
1409 | |
1410 | host->dpm_state = ENABLED; | |
1411 | ||
13189e78 | 1412 | mmc_release_host(host->mmc); |
dd498eff DK |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
13189e78 | 1417 | /* Handler for [OFF -> ENABLED] transition */ |
70a3341a | 1418 | static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) |
623821f7 | 1419 | { |
623821f7 | 1420 | clk_enable(host->fclk); |
623821f7 | 1421 | |
70a3341a DK |
1422 | omap_hsmmc_context_restore(host); |
1423 | omap_hsmmc_conf_bus_power(host); | |
13189e78 | 1424 | mmc_power_restore_host(host->mmc); |
623821f7 AH |
1425 | |
1426 | host->dpm_state = ENABLED; | |
1427 | ||
13189e78 JL |
1428 | dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); |
1429 | ||
623821f7 AH |
1430 | return 0; |
1431 | } | |
1432 | ||
dd498eff DK |
1433 | /* |
1434 | * Bring MMC host to ENABLED from any other PM state. | |
1435 | */ | |
70a3341a | 1436 | static int omap_hsmmc_enable(struct mmc_host *mmc) |
dd498eff | 1437 | { |
70a3341a | 1438 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1439 | |
1440 | switch (host->dpm_state) { | |
1441 | case DISABLED: | |
70a3341a | 1442 | return omap_hsmmc_disabled_to_enabled(host); |
13189e78 | 1443 | case CARDSLEEP: |
623821f7 | 1444 | case REGSLEEP: |
70a3341a | 1445 | return omap_hsmmc_sleep_to_enabled(host); |
dd498eff | 1446 | case OFF: |
70a3341a | 1447 | return omap_hsmmc_off_to_enabled(host); |
dd498eff DK |
1448 | default: |
1449 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1450 | return -EINVAL; | |
1451 | } | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * Bring MMC host in PM state (one level deeper). | |
1456 | */ | |
70a3341a | 1457 | static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) |
dd498eff | 1458 | { |
70a3341a | 1459 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1460 | |
1461 | switch (host->dpm_state) { | |
1462 | case ENABLED: { | |
1463 | int delay; | |
1464 | ||
70a3341a | 1465 | delay = omap_hsmmc_enabled_to_disabled(host); |
dd498eff DK |
1466 | if (lazy || delay < 0) |
1467 | return delay; | |
1468 | return 0; | |
1469 | } | |
1470 | case DISABLED: | |
70a3341a | 1471 | return omap_hsmmc_disabled_to_sleep(host); |
13189e78 JL |
1472 | case CARDSLEEP: |
1473 | case REGSLEEP: | |
70a3341a | 1474 | return omap_hsmmc_sleep_to_off(host); |
dd498eff DK |
1475 | default: |
1476 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1477 | return -EINVAL; | |
1478 | } | |
1479 | } | |
1480 | ||
70a3341a | 1481 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1482 | { |
70a3341a | 1483 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1484 | int err; |
1485 | ||
1486 | err = clk_enable(host->fclk); | |
1487 | if (err) | |
1488 | return err; | |
1489 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); | |
70a3341a | 1490 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1491 | return 0; |
1492 | } | |
1493 | ||
70a3341a | 1494 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) |
dd498eff | 1495 | { |
70a3341a | 1496 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1497 | |
70a3341a | 1498 | omap_hsmmc_context_save(host); |
dd498eff DK |
1499 | clk_disable(host->fclk); |
1500 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); | |
1501 | return 0; | |
1502 | } | |
1503 | ||
70a3341a DK |
1504 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1505 | .enable = omap_hsmmc_enable_fclk, | |
1506 | .disable = omap_hsmmc_disable_fclk, | |
1507 | .request = omap_hsmmc_request, | |
1508 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1509 | .get_cd = omap_hsmmc_get_cd, |
1510 | .get_ro = omap_hsmmc_get_ro, | |
1511 | /* NYET -- enable_sdio_irq */ | |
1512 | }; | |
1513 | ||
70a3341a DK |
1514 | static const struct mmc_host_ops omap_hsmmc_ps_ops = { |
1515 | .enable = omap_hsmmc_enable, | |
1516 | .disable = omap_hsmmc_disable, | |
1517 | .request = omap_hsmmc_request, | |
1518 | .set_ios = omap_hsmmc_set_ios, | |
a45c6cb8 MC |
1519 | .get_cd = omap_hsmmc_get_cd, |
1520 | .get_ro = omap_hsmmc_get_ro, | |
1521 | /* NYET -- enable_sdio_irq */ | |
1522 | }; | |
1523 | ||
d900f712 DK |
1524 | #ifdef CONFIG_DEBUG_FS |
1525 | ||
70a3341a | 1526 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1527 | { |
1528 | struct mmc_host *mmc = s->private; | |
70a3341a | 1529 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
11dd62a7 DK |
1530 | int context_loss = 0; |
1531 | ||
70a3341a DK |
1532 | if (host->pdata->get_context_loss_count) |
1533 | context_loss = host->pdata->get_context_loss_count(host->dev); | |
d900f712 | 1534 | |
5e2ea617 AH |
1535 | seq_printf(s, "mmc%d:\n" |
1536 | " enabled:\t%d\n" | |
dd498eff | 1537 | " dpm_state:\t%d\n" |
5e2ea617 | 1538 | " nesting_cnt:\t%d\n" |
11dd62a7 | 1539 | " ctx_loss:\t%d:%d\n" |
5e2ea617 | 1540 | "\nregs:\n", |
dd498eff DK |
1541 | mmc->index, mmc->enabled ? 1 : 0, |
1542 | host->dpm_state, mmc->nesting_cnt, | |
11dd62a7 | 1543 | host->context_loss, context_loss); |
5e2ea617 | 1544 | |
13189e78 | 1545 | if (host->suspended || host->dpm_state == OFF) { |
dd498eff DK |
1546 | seq_printf(s, "host suspended, can't read registers\n"); |
1547 | return 0; | |
1548 | } | |
1549 | ||
5e2ea617 AH |
1550 | if (clk_enable(host->fclk) != 0) { |
1551 | seq_printf(s, "can't read the regs\n"); | |
dd498eff | 1552 | return 0; |
5e2ea617 | 1553 | } |
d900f712 DK |
1554 | |
1555 | seq_printf(s, "SYSCONFIG:\t0x%08x\n", | |
1556 | OMAP_HSMMC_READ(host->base, SYSCONFIG)); | |
1557 | seq_printf(s, "CON:\t\t0x%08x\n", | |
1558 | OMAP_HSMMC_READ(host->base, CON)); | |
1559 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1560 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1561 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1562 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1563 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1564 | OMAP_HSMMC_READ(host->base, IE)); | |
1565 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1566 | OMAP_HSMMC_READ(host->base, ISE)); | |
1567 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1568 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 AH |
1569 | |
1570 | clk_disable(host->fclk); | |
dd498eff | 1571 | |
d900f712 DK |
1572 | return 0; |
1573 | } | |
1574 | ||
70a3341a | 1575 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1576 | { |
70a3341a | 1577 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1578 | } |
1579 | ||
1580 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1581 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1582 | .read = seq_read, |
1583 | .llseek = seq_lseek, | |
1584 | .release = single_release, | |
1585 | }; | |
1586 | ||
70a3341a | 1587 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1588 | { |
1589 | if (mmc->debugfs_root) | |
1590 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1591 | mmc, &mmc_regs_fops); | |
1592 | } | |
1593 | ||
1594 | #else | |
1595 | ||
70a3341a | 1596 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1597 | { |
1598 | } | |
1599 | ||
1600 | #endif | |
1601 | ||
70a3341a | 1602 | static int __init omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1603 | { |
1604 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1605 | struct mmc_host *mmc; | |
70a3341a | 1606 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 MC |
1607 | struct resource *res; |
1608 | int ret = 0, irq; | |
a45c6cb8 MC |
1609 | |
1610 | if (pdata == NULL) { | |
1611 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1612 | return -ENXIO; | |
1613 | } | |
1614 | ||
1615 | if (pdata->nr_slots == 0) { | |
1616 | dev_err(&pdev->dev, "No Slots\n"); | |
1617 | return -ENXIO; | |
1618 | } | |
1619 | ||
1620 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1621 | irq = platform_get_irq(pdev, 0); | |
1622 | if (res == NULL || irq < 0) | |
1623 | return -ENXIO; | |
1624 | ||
1625 | res = request_mem_region(res->start, res->end - res->start + 1, | |
1626 | pdev->name); | |
1627 | if (res == NULL) | |
1628 | return -EBUSY; | |
1629 | ||
70a3341a | 1630 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1631 | if (!mmc) { |
1632 | ret = -ENOMEM; | |
1633 | goto err; | |
1634 | } | |
1635 | ||
1636 | host = mmc_priv(mmc); | |
1637 | host->mmc = mmc; | |
1638 | host->pdata = pdata; | |
1639 | host->dev = &pdev->dev; | |
1640 | host->use_dma = 1; | |
1641 | host->dev->dma_mask = &pdata->dma_mask; | |
1642 | host->dma_ch = -1; | |
1643 | host->irq = irq; | |
1644 | host->id = pdev->id; | |
1645 | host->slot_id = 0; | |
1646 | host->mapbase = res->start; | |
1647 | host->base = ioremap(host->mapbase, SZ_4K); | |
a3621465 | 1648 | host->power_mode = -1; |
a45c6cb8 MC |
1649 | |
1650 | platform_set_drvdata(pdev, host); | |
70a3341a | 1651 | INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); |
a45c6cb8 | 1652 | |
191d1f1d | 1653 | if (mmc_slot(host).power_saving) |
70a3341a | 1654 | mmc->ops = &omap_hsmmc_ps_ops; |
dd498eff | 1655 | else |
70a3341a | 1656 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 1657 | |
a45c6cb8 MC |
1658 | mmc->f_min = 400000; |
1659 | mmc->f_max = 52000000; | |
1660 | ||
1661 | sema_init(&host->sem, 1); | |
4dffd7a2 | 1662 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 1663 | |
6f7607cc | 1664 | host->iclk = clk_get(&pdev->dev, "ick"); |
a45c6cb8 MC |
1665 | if (IS_ERR(host->iclk)) { |
1666 | ret = PTR_ERR(host->iclk); | |
1667 | host->iclk = NULL; | |
1668 | goto err1; | |
1669 | } | |
6f7607cc | 1670 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1671 | if (IS_ERR(host->fclk)) { |
1672 | ret = PTR_ERR(host->fclk); | |
1673 | host->fclk = NULL; | |
1674 | clk_put(host->iclk); | |
1675 | goto err1; | |
1676 | } | |
1677 | ||
70a3341a | 1678 | omap_hsmmc_context_save(host); |
11dd62a7 | 1679 | |
5e2ea617 | 1680 | mmc->caps |= MMC_CAP_DISABLE; |
dd498eff DK |
1681 | mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); |
1682 | /* we start off in DISABLED state */ | |
1683 | host->dpm_state = DISABLED; | |
1684 | ||
5e2ea617 | 1685 | if (mmc_host_enable(host->mmc) != 0) { |
a45c6cb8 MC |
1686 | clk_put(host->iclk); |
1687 | clk_put(host->fclk); | |
1688 | goto err1; | |
1689 | } | |
1690 | ||
1691 | if (clk_enable(host->iclk) != 0) { | |
5e2ea617 | 1692 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1693 | clk_put(host->iclk); |
1694 | clk_put(host->fclk); | |
1695 | goto err1; | |
1696 | } | |
1697 | ||
1698 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | |
1699 | /* | |
1700 | * MMC can still work without debounce clock. | |
1701 | */ | |
1702 | if (IS_ERR(host->dbclk)) | |
1703 | dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); | |
1704 | else | |
1705 | if (clk_enable(host->dbclk) != 0) | |
1706 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" | |
1707 | " clk failed\n"); | |
1708 | else | |
1709 | host->dbclk_enabled = 1; | |
1710 | ||
0ccd76d4 JY |
1711 | /* Since we do only SG emulation, we can have as many segs |
1712 | * as we want. */ | |
1713 | mmc->max_phys_segs = 1024; | |
1714 | mmc->max_hw_segs = 1024; | |
1715 | ||
a45c6cb8 MC |
1716 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1717 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1718 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1719 | mmc->max_seg_size = mmc->max_req_size; | |
1720 | ||
13189e78 JL |
1721 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
1722 | MMC_CAP_WAIT_WHILE_BUSY; | |
a45c6cb8 | 1723 | |
191d1f1d | 1724 | if (mmc_slot(host).wires >= 8) |
73153010 | 1725 | mmc->caps |= MMC_CAP_8_BIT_DATA; |
191d1f1d | 1726 | else if (mmc_slot(host).wires >= 4) |
a45c6cb8 MC |
1727 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1728 | ||
191d1f1d | 1729 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
1730 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
1731 | ||
70a3341a | 1732 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 1733 | |
f3e2f1dd GI |
1734 | /* Select DMA lines */ |
1735 | switch (host->id) { | |
1736 | case OMAP_MMC1_DEVID: | |
1737 | host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; | |
1738 | host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; | |
1739 | break; | |
1740 | case OMAP_MMC2_DEVID: | |
1741 | host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; | |
1742 | host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; | |
1743 | break; | |
1744 | case OMAP_MMC3_DEVID: | |
1745 | host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; | |
1746 | host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; | |
1747 | break; | |
1748 | default: | |
1749 | dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); | |
1750 | goto err_irq; | |
1751 | } | |
a45c6cb8 MC |
1752 | |
1753 | /* Request IRQ for MMC operations */ | |
70a3341a | 1754 | ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, |
a45c6cb8 MC |
1755 | mmc_hostname(mmc), host); |
1756 | if (ret) { | |
1757 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
1758 | goto err_irq; | |
1759 | } | |
1760 | ||
b583f26d | 1761 | /* initialize power supplies, gpios, etc */ |
a45c6cb8 MC |
1762 | if (pdata->init != NULL) { |
1763 | if (pdata->init(&pdev->dev) != 0) { | |
70a3341a DK |
1764 | dev_dbg(mmc_dev(host->mmc), |
1765 | "Unable to configure MMC IRQs\n"); | |
a45c6cb8 MC |
1766 | goto err_irq_cd_init; |
1767 | } | |
1768 | } | |
b583f26d | 1769 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
1770 | |
1771 | /* Request IRQ for card detect */ | |
e1a55f5e | 1772 | if ((mmc_slot(host).card_detect_irq)) { |
a45c6cb8 | 1773 | ret = request_irq(mmc_slot(host).card_detect_irq, |
70a3341a | 1774 | omap_hsmmc_cd_handler, |
a45c6cb8 MC |
1775 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1776 | | IRQF_DISABLED, | |
1777 | mmc_hostname(mmc), host); | |
1778 | if (ret) { | |
1779 | dev_dbg(mmc_dev(host->mmc), | |
1780 | "Unable to grab MMC CD IRQ\n"); | |
1781 | goto err_irq_cd; | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
1786 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
1787 | ||
5e2ea617 AH |
1788 | mmc_host_lazy_disable(host->mmc); |
1789 | ||
b62f6228 AH |
1790 | omap_hsmmc_protect_card(host); |
1791 | ||
a45c6cb8 MC |
1792 | mmc_add_host(mmc); |
1793 | ||
191d1f1d | 1794 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
1795 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
1796 | if (ret < 0) | |
1797 | goto err_slot_name; | |
1798 | } | |
191d1f1d | 1799 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
1800 | ret = device_create_file(&mmc->class_dev, |
1801 | &dev_attr_cover_switch); | |
1802 | if (ret < 0) | |
1803 | goto err_cover_switch; | |
1804 | } | |
1805 | ||
70a3341a | 1806 | omap_hsmmc_debugfs(mmc); |
d900f712 | 1807 | |
a45c6cb8 MC |
1808 | return 0; |
1809 | ||
1810 | err_cover_switch: | |
1811 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); | |
1812 | err_slot_name: | |
1813 | mmc_remove_host(mmc); | |
1814 | err_irq_cd: | |
1815 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1816 | err_irq_cd_init: | |
1817 | free_irq(host->irq, host); | |
1818 | err_irq: | |
5e2ea617 | 1819 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1820 | clk_disable(host->iclk); |
1821 | clk_put(host->fclk); | |
1822 | clk_put(host->iclk); | |
1823 | if (host->dbclk_enabled) { | |
1824 | clk_disable(host->dbclk); | |
1825 | clk_put(host->dbclk); | |
1826 | } | |
1827 | ||
1828 | err1: | |
1829 | iounmap(host->base); | |
1830 | err: | |
1831 | dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); | |
1832 | release_mem_region(res->start, res->end - res->start + 1); | |
1833 | if (host) | |
1834 | mmc_free_host(mmc); | |
1835 | return ret; | |
1836 | } | |
1837 | ||
70a3341a | 1838 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 1839 | { |
70a3341a | 1840 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1841 | struct resource *res; |
1842 | ||
1843 | if (host) { | |
5e2ea617 | 1844 | mmc_host_enable(host->mmc); |
a45c6cb8 MC |
1845 | mmc_remove_host(host->mmc); |
1846 | if (host->pdata->cleanup) | |
1847 | host->pdata->cleanup(&pdev->dev); | |
1848 | free_irq(host->irq, host); | |
1849 | if (mmc_slot(host).card_detect_irq) | |
1850 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1851 | flush_scheduled_work(); | |
1852 | ||
5e2ea617 | 1853 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1854 | clk_disable(host->iclk); |
1855 | clk_put(host->fclk); | |
1856 | clk_put(host->iclk); | |
1857 | if (host->dbclk_enabled) { | |
1858 | clk_disable(host->dbclk); | |
1859 | clk_put(host->dbclk); | |
1860 | } | |
1861 | ||
1862 | mmc_free_host(host->mmc); | |
1863 | iounmap(host->base); | |
1864 | } | |
1865 | ||
1866 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1867 | if (res) | |
1868 | release_mem_region(res->start, res->end - res->start + 1); | |
1869 | platform_set_drvdata(pdev, NULL); | |
1870 | ||
1871 | return 0; | |
1872 | } | |
1873 | ||
1874 | #ifdef CONFIG_PM | |
70a3341a | 1875 | static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) |
a45c6cb8 MC |
1876 | { |
1877 | int ret = 0; | |
70a3341a | 1878 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1879 | |
1880 | if (host && host->suspended) | |
1881 | return 0; | |
1882 | ||
1883 | if (host) { | |
a6b2240d AH |
1884 | host->suspended = 1; |
1885 | if (host->pdata->suspend) { | |
1886 | ret = host->pdata->suspend(&pdev->dev, | |
1887 | host->slot_id); | |
1888 | if (ret) { | |
1889 | dev_dbg(mmc_dev(host->mmc), | |
1890 | "Unable to handle MMC board" | |
1891 | " level suspend\n"); | |
1892 | host->suspended = 0; | |
1893 | return ret; | |
1894 | } | |
1895 | } | |
1896 | cancel_work_sync(&host->mmc_carddetect_work); | |
5e2ea617 | 1897 | mmc_host_enable(host->mmc); |
a45c6cb8 MC |
1898 | ret = mmc_suspend_host(host->mmc, state); |
1899 | if (ret == 0) { | |
a45c6cb8 MC |
1900 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
1901 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
1902 | ||
a45c6cb8 | 1903 | |
0683af48 | 1904 | OMAP_HSMMC_WRITE(host->base, HCTL, |
191d1f1d | 1905 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); |
5e2ea617 | 1906 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1907 | clk_disable(host->iclk); |
1908 | clk_disable(host->dbclk); | |
a6b2240d AH |
1909 | } else { |
1910 | host->suspended = 0; | |
1911 | if (host->pdata->resume) { | |
1912 | ret = host->pdata->resume(&pdev->dev, | |
1913 | host->slot_id); | |
1914 | if (ret) | |
1915 | dev_dbg(mmc_dev(host->mmc), | |
1916 | "Unmask interrupt failed\n"); | |
1917 | } | |
5e2ea617 | 1918 | mmc_host_disable(host->mmc); |
a6b2240d | 1919 | } |
a45c6cb8 MC |
1920 | |
1921 | } | |
1922 | return ret; | |
1923 | } | |
1924 | ||
1925 | /* Routine to resume the MMC device */ | |
70a3341a | 1926 | static int omap_hsmmc_resume(struct platform_device *pdev) |
a45c6cb8 MC |
1927 | { |
1928 | int ret = 0; | |
70a3341a | 1929 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1930 | |
1931 | if (host && !host->suspended) | |
1932 | return 0; | |
1933 | ||
1934 | if (host) { | |
a45c6cb8 | 1935 | ret = clk_enable(host->iclk); |
11dd62a7 | 1936 | if (ret) |
a45c6cb8 | 1937 | goto clk_en_err; |
a45c6cb8 MC |
1938 | |
1939 | if (clk_enable(host->dbclk) != 0) | |
1940 | dev_dbg(mmc_dev(host->mmc), | |
1941 | "Enabling debounce clk failed\n"); | |
1942 | ||
11dd62a7 DK |
1943 | if (mmc_host_enable(host->mmc) != 0) { |
1944 | clk_disable(host->iclk); | |
1945 | goto clk_en_err; | |
1946 | } | |
1947 | ||
70a3341a | 1948 | omap_hsmmc_conf_bus_power(host); |
1b331e69 | 1949 | |
a45c6cb8 MC |
1950 | if (host->pdata->resume) { |
1951 | ret = host->pdata->resume(&pdev->dev, host->slot_id); | |
1952 | if (ret) | |
1953 | dev_dbg(mmc_dev(host->mmc), | |
1954 | "Unmask interrupt failed\n"); | |
1955 | } | |
1956 | ||
b62f6228 AH |
1957 | omap_hsmmc_protect_card(host); |
1958 | ||
a45c6cb8 MC |
1959 | /* Notify the core to resume the host */ |
1960 | ret = mmc_resume_host(host->mmc); | |
1961 | if (ret == 0) | |
1962 | host->suspended = 0; | |
70a3341a | 1963 | |
5e2ea617 | 1964 | mmc_host_lazy_disable(host->mmc); |
a45c6cb8 MC |
1965 | } |
1966 | ||
1967 | return ret; | |
1968 | ||
1969 | clk_en_err: | |
1970 | dev_dbg(mmc_dev(host->mmc), | |
1971 | "Failed to enable MMC clocks during resume\n"); | |
1972 | return ret; | |
1973 | } | |
1974 | ||
1975 | #else | |
70a3341a DK |
1976 | #define omap_hsmmc_suspend NULL |
1977 | #define omap_hsmmc_resume NULL | |
a45c6cb8 MC |
1978 | #endif |
1979 | ||
70a3341a DK |
1980 | static struct platform_driver omap_hsmmc_driver = { |
1981 | .remove = omap_hsmmc_remove, | |
1982 | .suspend = omap_hsmmc_suspend, | |
1983 | .resume = omap_hsmmc_resume, | |
a45c6cb8 MC |
1984 | .driver = { |
1985 | .name = DRIVER_NAME, | |
1986 | .owner = THIS_MODULE, | |
1987 | }, | |
1988 | }; | |
1989 | ||
70a3341a | 1990 | static int __init omap_hsmmc_init(void) |
a45c6cb8 MC |
1991 | { |
1992 | /* Register the MMC driver */ | |
70a3341a | 1993 | return platform_driver_register(&omap_hsmmc_driver); |
a45c6cb8 MC |
1994 | } |
1995 | ||
70a3341a | 1996 | static void __exit omap_hsmmc_cleanup(void) |
a45c6cb8 MC |
1997 | { |
1998 | /* Unregister MMC driver */ | |
70a3341a | 1999 | platform_driver_unregister(&omap_hsmmc_driver); |
a45c6cb8 MC |
2000 | } |
2001 | ||
70a3341a DK |
2002 | module_init(omap_hsmmc_init); |
2003 | module_exit(omap_hsmmc_cleanup); | |
a45c6cb8 MC |
2004 | |
2005 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); | |
2006 | MODULE_LICENSE("GPL"); | |
2007 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2008 | MODULE_AUTHOR("Texas Instruments Inc"); |