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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groec...
[net-next-2.6.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
121#define DRIVER_NAME "mmci-omap-hs"
122
dd498eff
DK		 123/* Timeouts for entering power saving states on inactivity, msec */
124#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 125#define OMAP_MMC_SLEEP_TIMEOUT 1000
126#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 127
a45c6cb8
MC		 128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
11dd62a7 187
a45c6cb8
MC		 188 struct omap_mmc_platform_data *pdata;
189};
190
db0fefc5
AH		 191static int omap_hsmmc_card_detect(struct device *dev, int slot)
192{
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205}
206
207static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
213}
214
215#ifdef CONFIG_PM
216
217static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218{
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
220
221 disable_irq(mmc->slots[0].card_detect_irq);
222 return 0;
223}
224
225static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226{
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
228
229 enable_irq(mmc->slots[0].card_detect_irq);
230 return 0;
231}
232
233#else
234
235#define omap_hsmmc_suspend_cdirq NULL
236#define omap_hsmmc_resume_cdirq NULL
237
238#endif
239
b702b106
AH		 240#ifdef CONFIG_REGULATOR
241
db0fefc5
AH		 242static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
243 int vdd)
244{
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
247 int ret;
248
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
251
252 if (power_on)
253 ret = mmc_regulator_set_ocr(host->vcc, vdd);
254 else
255 ret = mmc_regulator_set_ocr(host->vcc, 0);
256
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
259
260 return ret;
261}
262
263static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
264 int vdd)
265{
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
268 int ret = 0;
269
270 /*
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
273 */
274 if (!host->vcc)
275 return 0;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
294 ret = mmc_regulator_set_ocr(host->vcc, vdd);
295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
299 ret = mmc_regulator_set_ocr(host->vcc, 0);
300 }
301 } else {
6da20c89
AH		 302 if (host->vcc_aux)
303 ret = regulator_disable(host->vcc_aux);
db0fefc5
AH		 304 if (ret == 0)
305 ret = mmc_regulator_set_ocr(host->vcc, 0);
306 }
307
308 if (mmc_slot(host).after_set_reg)
309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
310
311 return ret;
312}
313
314static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
315 int vdd, int cardsleep)
316{
317 struct omap_hsmmc_host *host =
318 platform_get_drvdata(to_platform_device(dev));
319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
320
321 return regulator_set_mode(host->vcc, mode);
322}
323
324static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
325 int vdd, int cardsleep)
326{
327 struct omap_hsmmc_host *host =
328 platform_get_drvdata(to_platform_device(dev));
329 int err, mode;
330
331 /*
332 * If we don't see a Vcc regulator, assume it's a fixed
333 * voltage always-on regulator.
334 */
335 if (!host->vcc)
336 return 0;
337
338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
339
340 if (!host->vcc_aux)
341 return regulator_set_mode(host->vcc, mode);
342
343 if (cardsleep) {
344 /* VCC can be turned off if card is asleep */
345 if (sleep)
346 err = mmc_regulator_set_ocr(host->vcc, 0);
347 else
348 err = mmc_regulator_set_ocr(host->vcc, vdd);
349 } else
350 err = regulator_set_mode(host->vcc, mode);
351 if (err)
352 return err;
e0eb2424
AH		 353
354 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
355 return regulator_set_mode(host->vcc_aux, mode);
356
357 if (sleep)
358 return regulator_disable(host->vcc_aux);
359 else
360 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 361}
362
db0fefc5
AH		 363static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
364{
365 struct regulator *reg;
366 int ret = 0;
64be9782 367 int ocr_value = 0;
db0fefc5
AH		 368
369 switch (host->id) {
370 case OMAP_MMC1_DEVID:
371 /* On-chip level shifting via PBIAS0/PBIAS1 */
372 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
373 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
374 break;
375 case OMAP_MMC2_DEVID:
376 case OMAP_MMC3_DEVID:
377 /* Off-chip level shifting, or none */
378 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
379 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
380 break;
381 default:
382 pr_err("MMC%d configuration not supported!\n", host->id);
383 return -EINVAL;
384 }
385
386 reg = regulator_get(host->dev, "vmmc");
387 if (IS_ERR(reg)) {
388 dev_dbg(host->dev, "vmmc regulator missing\n");
389 /*
390 * HACK: until fixed.c regulator is usable,
391 * we don't require a main regulator
392 * for MMC2 or MMC3
393 */
394 if (host->id == OMAP_MMC1_DEVID) {
395 ret = PTR_ERR(reg);
396 goto err;
397 }
398 } else {
399 host->vcc = reg;
64be9782 400 ocr_value = mmc_regulator_get_ocrmask(reg);
401 if (!mmc_slot(host).ocr_mask) {
402 mmc_slot(host).ocr_mask = ocr_value;
403 } else {
404 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
405 pr_err("MMC%d ocrmask %x is not supported\n",
406 host->id, mmc_slot(host).ocr_mask);
407 mmc_slot(host).ocr_mask = 0;
408 return -EINVAL;
409 }
410 }
db0fefc5
AH		 411 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
412
413 /* Allow an aux regulator */
414 reg = regulator_get(host->dev, "vmmc_aux");
415 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
416
417 /*
418 * UGLY HACK: workaround regulator framework bugs.
419 * When the bootloader leaves a supply active, it's
420 * initialized with zero usecount ... and we can't
421 * disable it without first enabling it. Until the
422 * framework is fixed, we need a workaround like this
423 * (which is safe for MMC, but not in general).
424 */
425 if (regulator_is_enabled(host->vcc) > 0) {
426 regulator_enable(host->vcc);
427 regulator_disable(host->vcc);
428 }
429 if (host->vcc_aux) {
430 if (regulator_is_enabled(reg) > 0) {
431 regulator_enable(reg);
432 regulator_disable(reg);
433 }
434 }
435 }
436
437 return 0;
438
439err:
440 mmc_slot(host).set_power = NULL;
441 mmc_slot(host).set_sleep = NULL;
442 return ret;
443}
444
445static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
446{
447 regulator_put(host->vcc);
448 regulator_put(host->vcc_aux);
449 mmc_slot(host).set_power = NULL;
450 mmc_slot(host).set_sleep = NULL;
451}
452
b702b106
AH		 453static inline int omap_hsmmc_have_reg(void)
454{
455 return 1;
456}
457
458#else
459
460static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
461{
462 return -EINVAL;
463}
464
465static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
466{
467}
468
469static inline int omap_hsmmc_have_reg(void)
470{
471 return 0;
472}
473
474#endif
475
476static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
477{
478 int ret;
479
480 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
481 pdata->suspend = omap_hsmmc_suspend_cdirq;
482 pdata->resume = omap_hsmmc_resume_cdirq;
483 if (pdata->slots[0].cover)
484 pdata->slots[0].get_cover_state =
485 omap_hsmmc_get_cover_state;
486 else
487 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
488 pdata->slots[0].card_detect_irq =
489 gpio_to_irq(pdata->slots[0].switch_pin);
490 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
491 if (ret)
492 return ret;
493 ret = gpio_direction_input(pdata->slots[0].switch_pin);
494 if (ret)
495 goto err_free_sp;
496 } else
497 pdata->slots[0].switch_pin = -EINVAL;
498
499 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
500 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
501 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
502 if (ret)
503 goto err_free_cd;
504 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
505 if (ret)
506 goto err_free_wp;
507 } else
508 pdata->slots[0].gpio_wp = -EINVAL;
509
510 return 0;
511
512err_free_wp:
513 gpio_free(pdata->slots[0].gpio_wp);
514err_free_cd:
515 if (gpio_is_valid(pdata->slots[0].switch_pin))
516err_free_sp:
517 gpio_free(pdata->slots[0].switch_pin);
518 return ret;
519}
520
521static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
522{
523 if (gpio_is_valid(pdata->slots[0].gpio_wp))
524 gpio_free(pdata->slots[0].gpio_wp);
525 if (gpio_is_valid(pdata->slots[0].switch_pin))
526 gpio_free(pdata->slots[0].switch_pin);
527}
528
a45c6cb8
MC		 529/*
530 * Stop clock to the card
531 */
70a3341a 532static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 533{
534 OMAP_HSMMC_WRITE(host->base, SYSCTL,
535 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
536 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
537 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
538}
539
93caf8e6
AH		 540static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
541 struct mmc_command *cmd)
b417577d
AH		 542{
543 unsigned int irq_mask;
544
545 if (host->use_dma)
546 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
547 else
548 irq_mask = INT_EN_MASK;
549
93caf8e6
AH		 550 /* Disable timeout for erases */
551 if (cmd->opcode == MMC_ERASE)
552 irq_mask &= ~DTO_ENABLE;
553
b417577d
AH		 554 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
555 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
556 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
557}
558
559static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
560{
561 OMAP_HSMMC_WRITE(host->base, ISE, 0);
562 OMAP_HSMMC_WRITE(host->base, IE, 0);
563 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
564}
565
11dd62a7
DK		 566#ifdef CONFIG_PM
567
568/*
569 * Restore the MMC host context, if it was lost as result of a
570 * power state change.
571 */
70a3341a 572static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 573{
574 struct mmc_ios *ios = &host->mmc->ios;
575 struct omap_mmc_platform_data *pdata = host->pdata;
576 int context_loss = 0;
577 u32 hctl, capa, con;
578 u16 dsor = 0;
579 unsigned long timeout;
580
581 if (pdata->get_context_loss_count) {
582 context_loss = pdata->get_context_loss_count(host->dev);
583 if (context_loss < 0)
584 return 1;
585 }
586
587 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
588 context_loss == host->context_loss ? "not " : "");
589 if (host->context_loss == context_loss)
590 return 1;
591
592 /* Wait for hardware reset */
593 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
594 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
595 && time_before(jiffies, timeout))
596 ;
597
598 /* Do software reset */
599 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
600 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
601 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
602 && time_before(jiffies, timeout))
603 ;
604
605 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
606 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
607
608 if (host->id == OMAP_MMC1_DEVID) {
609 if (host->power_mode != MMC_POWER_OFF &&
610 (1 << ios->vdd) <= MMC_VDD_23_24)
611 hctl = SDVS18;
612 else
613 hctl = SDVS30;
614 capa = VS30 | VS18;
615 } else {
616 hctl = SDVS18;
617 capa = VS18;
618 }
619
620 OMAP_HSMMC_WRITE(host->base, HCTL,
621 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
622
623 OMAP_HSMMC_WRITE(host->base, CAPA,
624 OMAP_HSMMC_READ(host->base, CAPA) | capa);
625
626 OMAP_HSMMC_WRITE(host->base, HCTL,
627 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
628
629 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
630 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
631 && time_before(jiffies, timeout))
632 ;
633
b417577d 634 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 635
636 /* Do not initialize card-specific things if the power is off */
637 if (host->power_mode == MMC_POWER_OFF)
638 goto out;
639
640 con = OMAP_HSMMC_READ(host->base, CON);
641 switch (ios->bus_width) {
642 case MMC_BUS_WIDTH_8:
643 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
644 break;
645 case MMC_BUS_WIDTH_4:
646 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
647 OMAP_HSMMC_WRITE(host->base, HCTL,
648 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
649 break;
650 case MMC_BUS_WIDTH_1:
651 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
652 OMAP_HSMMC_WRITE(host->base, HCTL,
653 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
654 break;
655 }
656
657 if (ios->clock) {
658 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
659 if (dsor < 1)
660 dsor = 1;
661
662 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
663 dsor++;
664
665 if (dsor > 250)
666 dsor = 250;
667 }
668
669 OMAP_HSMMC_WRITE(host->base, SYSCTL,
670 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
671 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
672 OMAP_HSMMC_WRITE(host->base, SYSCTL,
673 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
674
675 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
676 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
677 && time_before(jiffies, timeout))
678 ;
679
680 OMAP_HSMMC_WRITE(host->base, SYSCTL,
681 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
682
683 con = OMAP_HSMMC_READ(host->base, CON);
684 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
685 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
686 else
687 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
688out:
689 host->context_loss = context_loss;
690
691 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
692 return 0;
693}
694
695/*
696 * Save the MMC host context (store the number of power state changes so far).
697 */
70a3341a 698static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 699{
700 struct omap_mmc_platform_data *pdata = host->pdata;
701 int context_loss;
702
703 if (pdata->get_context_loss_count) {
704 context_loss = pdata->get_context_loss_count(host->dev);
705 if (context_loss < 0)
706 return;
707 host->context_loss = context_loss;
708 }
709}
710
711#else
712
70a3341a 713static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 714{
715 return 0;
716}
717
70a3341a 718static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 719{
720}
721
722#endif
723
a45c6cb8
MC		 724/*
725 * Send init stream sequence to card
726 * before sending IDLE command
727 */
70a3341a 728static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 729{
730 int reg = 0;
731 unsigned long timeout;
732
b62f6228
AH		 733 if (host->protect_card)
734 return;
735
a45c6cb8 736 disable_irq(host->irq);
b417577d
AH		 737
738 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 739 OMAP_HSMMC_WRITE(host->base, CON,
740 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
741 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
742
743 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
744 while ((reg != CC) && time_before(jiffies, timeout))
745 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
746
747 OMAP_HSMMC_WRITE(host->base, CON,
748 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 749
750 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
751 OMAP_HSMMC_READ(host->base, STAT);
752
a45c6cb8
MC		 753 enable_irq(host->irq);
754}
755
756static inline
70a3341a 757int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 758{
759 int r = 1;
760
191d1f1d
DK		 761 if (mmc_slot(host).get_cover_state)
762 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 763 return r;
764}
765
766static ssize_t
70a3341a 767omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 768 char *buf)
769{
770 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 771 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 772
70a3341a
DK		 773 return sprintf(buf, "%s\n",
774 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 775}
776
70a3341a 777static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 778
779static ssize_t
70a3341a 780omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 781 char *buf)
782{
783 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 784 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 785
191d1f1d 786 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 787}
788
70a3341a 789static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 790
791/*
792 * Configure the response type and send the cmd.
793 */
794static void
70a3341a 795omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 796 struct mmc_data *data)
797{
798 int cmdreg = 0, resptype = 0, cmdtype = 0;
799
800 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
801 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
802 host->cmd = cmd;
803
93caf8e6 804 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 805
4a694dc9 806 host->response_busy = 0;
a45c6cb8
MC		 807 if (cmd->flags & MMC_RSP_PRESENT) {
808 if (cmd->flags & MMC_RSP_136)
809 resptype = 1;
4a694dc9
AH		 810 else if (cmd->flags & MMC_RSP_BUSY) {
811 resptype = 3;
812 host->response_busy = 1;
813 } else
a45c6cb8
MC		 814 resptype = 2;
815 }
816
817 /*
818 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
819 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
820 * a val of 0x3, rest 0x0.
821 */
822 if (cmd == host->mrq->stop)
823 cmdtype = 0x3;
824
825 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
826
827 if (data) {
828 cmdreg |= DP_SELECT | MSBS | BCE;
829 if (data->flags & MMC_DATA_READ)
830 cmdreg |= DDIR;
831 else
832 cmdreg &= ~(DDIR);
833 }
834
835 if (host->use_dma)
836 cmdreg |= DMA_EN;
837
b417577d 838 host->req_in_progress = 1;
4dffd7a2 839
a45c6cb8
MC		 840 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
841 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
842}
843
0ccd76d4 844static int
70a3341a 845omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 846{
847 if (data->flags & MMC_DATA_WRITE)
848 return DMA_TO_DEVICE;
849 else
850 return DMA_FROM_DEVICE;
851}
852
b417577d
AH		 853static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
854{
855 int dma_ch;
856
857 spin_lock(&host->irq_lock);
858 host->req_in_progress = 0;
859 dma_ch = host->dma_ch;
860 spin_unlock(&host->irq_lock);
861
862 omap_hsmmc_disable_irq(host);
863 /* Do not complete the request if DMA is still in progress */
864 if (mrq->data && host->use_dma && dma_ch != -1)
865 return;
866 host->mrq = NULL;
867 mmc_request_done(host->mmc, mrq);
868}
869
a45c6cb8
MC		 870/*
871 * Notify the transfer complete to MMC core
872 */
873static void
70a3341a 874omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 875{
4a694dc9
AH		 876 if (!data) {
877 struct mmc_request *mrq = host->mrq;
878
23050103
AH		 879 /* TC before CC from CMD6 - don't know why, but it happens */
880 if (host->cmd && host->cmd->opcode == 6 &&
881 host->response_busy) {
882 host->response_busy = 0;
883 return;
884 }
885
b417577d 886 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 887 return;
888 }
889
a45c6cb8
MC		 890 host->data = NULL;
891
a45c6cb8
MC		 892 if (!data->error)
893 data->bytes_xfered += data->blocks * (data->blksz);
894 else
895 data->bytes_xfered = 0;
896
897 if (!data->stop) {
b417577d 898 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 899 return;
900 }
70a3341a 901 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 902}
903
904/*
905 * Notify the core about command completion
906 */
907static void
70a3341a 908omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 909{
910 host->cmd = NULL;
911
912 if (cmd->flags & MMC_RSP_PRESENT) {
913 if (cmd->flags & MMC_RSP_136) {
914 /* response type 2 */
915 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
916 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
917 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
918 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
919 } else {
920 /* response types 1, 1b, 3, 4, 5, 6 */
921 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
922 }
923 }
b417577d
AH		 924 if ((host->data == NULL && !host->response_busy) || cmd->error)
925 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 926}
927
928/*
929 * DMA clean up for command errors
930 */
70a3341a 931static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 932{
b417577d
AH		 933 int dma_ch;
934
82788ff5 935 host->data->error = errno;
a45c6cb8 936
b417577d
AH		 937 spin_lock(&host->irq_lock);
938 dma_ch = host->dma_ch;
939 host->dma_ch = -1;
940 spin_unlock(&host->irq_lock);
941
942 if (host->use_dma && dma_ch != -1) {
a45c6cb8 943 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 944 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 945 omap_free_dma(dma_ch);
a45c6cb8
MC		 946 }
947 host->data = NULL;
a45c6cb8
MC		 948}
949
950/*
951 * Readable error output
952 */
953#ifdef CONFIG_MMC_DEBUG
70a3341a 954static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 955{
956 /* --- means reserved bit without definition at documentation */
70a3341a 957 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 958 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
959 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
960 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
961 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
962 };
963 char res[256];
964 char *buf = res;
965 int len, i;
966
967 len = sprintf(buf, "MMC IRQ 0x%x :", status);
968 buf += len;
969
70a3341a 970 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 971 if (status & (1 << i)) {
70a3341a 972 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 973 buf += len;
974 }
975
976 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
977}
978#endif /* CONFIG_MMC_DEBUG */
979
3ebf74b1
JP		 980/*
981 * MMC controller internal state machines reset
982 *
983 * Used to reset command or data internal state machines, using respectively
984 * SRC or SRD bit of SYSCTL register
985 * Can be called from interrupt context
986 */
70a3341a
DK		 987static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
988 unsigned long bit)
3ebf74b1
JP		 989{
990 unsigned long i = 0;
991 unsigned long limit = (loops_per_jiffy *
992 msecs_to_jiffies(MMC_TIMEOUT_MS));
993
994 OMAP_HSMMC_WRITE(host->base, SYSCTL,
995 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
996
07ad64b6
MC		 997 /*
998 * OMAP4 ES2 and greater has an updated reset logic.
999 * Monitor a 0->1 transition first
1000 */
1001 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1002 while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
1003 && (i++ < limit))
1004 cpu_relax();
1005 }
1006 i = 0;
1007
3ebf74b1
JP		 1008 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1009 (i++ < limit))
1010 cpu_relax();
1011
1012 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1013 dev_err(mmc_dev(host->mmc),
1014 "Timeout waiting on controller reset in %s\n",
1015 __func__);
1016}
a45c6cb8 1017
b417577d 1018static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1019{
a45c6cb8 1020 struct mmc_data *data;
b417577d
AH		 1021 int end_cmd = 0, end_trans = 0;
1022
1023 if (!host->req_in_progress) {
1024 do {
1025 OMAP_HSMMC_WRITE(host->base, STAT, status);
1026 /* Flush posted write */
1027 status = OMAP_HSMMC_READ(host->base, STAT);
1028 } while (status & INT_EN_MASK);
1029 return;
a45c6cb8
MC		 1030 }
1031
1032 data = host->data;
a45c6cb8
MC		 1033 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1034
1035 if (status & ERR) {
1036#ifdef CONFIG_MMC_DEBUG
70a3341a 1037 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1038#endif
1039 if ((status & CMD_TIMEOUT) ||
1040 (status & CMD_CRC)) {
1041 if (host->cmd) {
1042 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1043 omap_hsmmc_reset_controller_fsm(host,
1044 SRC);
a45c6cb8
MC		 1045 host->cmd->error = -ETIMEDOUT;
1046 } else {
1047 host->cmd->error = -EILSEQ;
1048 }
1049 end_cmd = 1;
1050 }
4a694dc9
AH		 1051 if (host->data || host->response_busy) {
1052 if (host->data)
70a3341a
DK		 1053 omap_hsmmc_dma_cleanup(host,
1054 -ETIMEDOUT);
4a694dc9 1055 host->response_busy = 0;
70a3341a 1056 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1057 }
a45c6cb8
MC		 1058 }
1059 if ((status & DATA_TIMEOUT) ||
1060 (status & DATA_CRC)) {
4a694dc9
AH		 1061 if (host->data || host->response_busy) {
1062 int err = (status & DATA_TIMEOUT) ?
1063 -ETIMEDOUT : -EILSEQ;
1064
1065 if (host->data)
70a3341a 1066 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1067 else
4a694dc9
AH		 1068 host->mrq->cmd->error = err;
1069 host->response_busy = 0;
70a3341a 1070 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1071 end_trans = 1;
1072 }
1073 }
1074 if (status & CARD_ERR) {
1075 dev_dbg(mmc_dev(host->mmc),
1076 "Ignoring card err CMD%d\n", host->cmd->opcode);
1077 if (host->cmd)
1078 end_cmd = 1;
1079 if (host->data)
1080 end_trans = 1;
1081 }
1082 }
1083
1084 OMAP_HSMMC_WRITE(host->base, STAT, status);
1085
a8fe29d8 1086 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1087 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1088 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1089 omap_hsmmc_xfer_done(host, data);
b417577d 1090}
a45c6cb8 1091
b417577d
AH		 1092/*
1093 * MMC controller IRQ handler
1094 */
1095static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1096{
1097 struct omap_hsmmc_host *host = dev_id;
1098 int status;
1099
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1101 do {
1102 omap_hsmmc_do_irq(host, status);
1103 /* Flush posted write */
1104 status = OMAP_HSMMC_READ(host->base, STAT);
1105 } while (status & INT_EN_MASK);
4dffd7a2 1106
a45c6cb8
MC		 1107 return IRQ_HANDLED;
1108}
1109
70a3341a 1110static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1111{
1112 unsigned long i;
1113
1114 OMAP_HSMMC_WRITE(host->base, HCTL,
1115 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1116 for (i = 0; i < loops_per_jiffy; i++) {
1117 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1118 break;
1119 cpu_relax();
1120 }
1121}
1122
a45c6cb8 1123/*
eb250826
DB		 1124 * Switch MMC interface voltage ... only relevant for MMC1.
1125 *
1126 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1127 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1128 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1129 */
70a3341a 1130static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1131{
1132 u32 reg_val = 0;
1133 int ret;
1134
1135 /* Disable the clocks */
1136 clk_disable(host->fclk);
1137 clk_disable(host->iclk);
2bec0893
AH		 1138 if (host->got_dbclk)
1139 clk_disable(host->dbclk);
a45c6cb8
MC		 1140
1141 /* Turn the power off */
1142 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1143
1144 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1145 if (!ret)
1146 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1147 vdd);
1148 clk_enable(host->iclk);
1149 clk_enable(host->fclk);
1150 if (host->got_dbclk)
1151 clk_enable(host->dbclk);
1152
a45c6cb8
MC		 1153 if (ret != 0)
1154 goto err;
1155
a45c6cb8
MC		 1156 OMAP_HSMMC_WRITE(host->base, HCTL,
1157 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1158 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1159
a45c6cb8
MC		 1160 /*
1161 * If a MMC dual voltage card is detected, the set_ios fn calls
1162 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1163 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1164 *
eb250826
DB		 1165 * Cope with a bit of slop in the range ... per data sheets:
1166 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1167 * but recommended values are 1.71V to 1.89V
1168 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1169 * but recommended values are 2.7V to 3.3V
1170 *
1171 * Board setup code shouldn't permit anything very out-of-range.
1172 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1173 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1174 */
eb250826 1175 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1176 reg_val |= SDVS18;
eb250826
DB		 1177 else
1178 reg_val |= SDVS30;
a45c6cb8
MC		 1179
1180 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1181 set_sd_bus_power(host);
a45c6cb8
MC		 1182
1183 return 0;
1184err:
1185 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1186 return ret;
1187}
1188
b62f6228
AH		 1189/* Protect the card while the cover is open */
1190static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1191{
1192 if (!mmc_slot(host).get_cover_state)
1193 return;
1194
1195 host->reqs_blocked = 0;
1196 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1197 if (host->protect_card) {
1198 printk(KERN_INFO "%s: cover is closed, "
1199 "card is now accessible\n",
1200 mmc_hostname(host->mmc));
1201 host->protect_card = 0;
1202 }
1203 } else {
1204 if (!host->protect_card) {
1205 printk(KERN_INFO "%s: cover is open, "
1206 "card is now inaccessible\n",
1207 mmc_hostname(host->mmc));
1208 host->protect_card = 1;
1209 }
1210 }
1211}
1212
a45c6cb8
MC		 1213/*
1214 * Work Item to notify the core about card insertion/removal
1215 */
70a3341a 1216static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1217{
70a3341a
DK		 1218 struct omap_hsmmc_host *host =
1219 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1220 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1221 int carddetect;
1222
1223 if (host->suspended)
1224 return;
1225
1226 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1227
191d1f1d 1228 if (slot->card_detect)
db0fefc5 1229 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1230 else {
1231 omap_hsmmc_protect_card(host);
a6b2240d 1232 carddetect = -ENOSYS;
b62f6228 1233 }
a45c6cb8 1234
cdeebadd 1235 if (carddetect)
a45c6cb8 1236 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1237 else
a45c6cb8 1238 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1239}
1240
1241/*
1242 * ISR for handling card insertion and removal
1243 */
70a3341a 1244static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1245{
70a3341a 1246 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1247
a6b2240d
AH		 1248 if (host->suspended)
1249 return IRQ_HANDLED;
a45c6cb8
MC		 1250 schedule_work(&host->mmc_carddetect_work);
1251
1252 return IRQ_HANDLED;
1253}
1254
70a3341a 1255static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1256 struct mmc_data *data)
1257{
1258 int sync_dev;
1259
f3e2f1dd
GI		 1260 if (data->flags & MMC_DATA_WRITE)
1261 sync_dev = host->dma_line_tx;
1262 else
1263 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1264 return sync_dev;
1265}
1266
70a3341a 1267static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1268 struct mmc_data *data,
1269 struct scatterlist *sgl)
1270{
1271 int blksz, nblk, dma_ch;
1272
1273 dma_ch = host->dma_ch;
1274 if (data->flags & MMC_DATA_WRITE) {
1275 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1276 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1277 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1278 sg_dma_address(sgl), 0, 0);
1279 } else {
1280 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1281 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1282 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1283 sg_dma_address(sgl), 0, 0);
1284 }
1285
1286 blksz = host->data->blksz;
1287 nblk = sg_dma_len(sgl) / blksz;
1288
1289 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1290 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1291 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1292 !(data->flags & MMC_DATA_WRITE));
1293
1294 omap_start_dma(dma_ch);
1295}
1296
a45c6cb8
MC		 1297/*
1298 * DMA call back function
1299 */
b417577d 1300static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1301{
b417577d
AH		 1302 struct omap_hsmmc_host *host = cb_data;
1303 struct mmc_data *data = host->mrq->data;
1304 int dma_ch, req_in_progress;
a45c6cb8 1305
f3584e5e
V		 1306 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1307 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1308 ch_status);
1309 return;
1310 }
a45c6cb8 1311
b417577d
AH		 1312 spin_lock(&host->irq_lock);
1313 if (host->dma_ch < 0) {
1314 spin_unlock(&host->irq_lock);
a45c6cb8 1315 return;
b417577d 1316 }
a45c6cb8 1317
0ccd76d4
JY		 1318 host->dma_sg_idx++;
1319 if (host->dma_sg_idx < host->dma_len) {
1320 /* Fire up the next transfer. */
b417577d
AH		 1321 omap_hsmmc_config_dma_params(host, data,
1322 data->sg + host->dma_sg_idx);
1323 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1324 return;
1325 }
1326
b417577d
AH		 1327 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1328 omap_hsmmc_get_dma_dir(host, data));
1329
1330 req_in_progress = host->req_in_progress;
1331 dma_ch = host->dma_ch;
a45c6cb8 1332 host->dma_ch = -1;
b417577d
AH		 1333 spin_unlock(&host->irq_lock);
1334
1335 omap_free_dma(dma_ch);
1336
1337 /* If DMA has finished after TC, complete the request */
1338 if (!req_in_progress) {
1339 struct mmc_request *mrq = host->mrq;
1340
1341 host->mrq = NULL;
1342 mmc_request_done(host->mmc, mrq);
1343 }
a45c6cb8
MC		 1344}
1345
a45c6cb8
MC		 1346/*
1347 * Routine to configure and start DMA for the MMC card
1348 */
70a3341a
DK		 1349static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1350 struct mmc_request *req)
a45c6cb8 1351{
b417577d 1352 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1353 struct mmc_data *data = req->data;
1354
0ccd76d4 1355 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1356 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1357 struct scatterlist *sgl;
1358
1359 sgl = data->sg + i;
1360 if (sgl->length % data->blksz)
1361 return -EINVAL;
1362 }
1363 if ((data->blksz % 4) != 0)
1364 /* REVISIT: The MMC buffer increments only when MSB is written.
1365 * Return error for blksz which is non multiple of four.
1366 */
1367 return -EINVAL;
1368
b417577d 1369 BUG_ON(host->dma_ch != -1);
a45c6cb8 1370
70a3341a
DK		 1371 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1372 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1373 if (ret != 0) {
0ccd76d4 1374 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1375 "%s: omap_request_dma() failed with %d\n",
1376 mmc_hostname(host->mmc), ret);
1377 return ret;
1378 }
1379
1380 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1381 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1382 host->dma_ch = dma_ch;
0ccd76d4 1383 host->dma_sg_idx = 0;
a45c6cb8 1384
70a3341a 1385 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1386
a45c6cb8
MC		 1387 return 0;
1388}
1389
70a3341a 1390static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1391 unsigned int timeout_ns,
1392 unsigned int timeout_clks)
a45c6cb8
MC		 1393{
1394 unsigned int timeout, cycle_ns;
1395 uint32_t reg, clkd, dto = 0;
1396
1397 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1398 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1399 if (clkd == 0)
1400 clkd = 1;
1401
1402 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1403 timeout = timeout_ns / cycle_ns;
1404 timeout += timeout_clks;
a45c6cb8
MC		 1405 if (timeout) {
1406 while ((timeout & 0x80000000) == 0) {
1407 dto += 1;
1408 timeout <<= 1;
1409 }
1410 dto = 31 - dto;
1411 timeout <<= 1;
1412 if (timeout && dto)
1413 dto += 1;
1414 if (dto >= 13)
1415 dto -= 13;
1416 else
1417 dto = 0;
1418 if (dto > 14)
1419 dto = 14;
1420 }
1421
1422 reg &= ~DTO_MASK;
1423 reg |= dto << DTO_SHIFT;
1424 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1425}
1426
1427/*
1428 * Configure block length for MMC/SD cards and initiate the transfer.
1429 */
1430static int
70a3341a 1431omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1432{
1433 int ret;
1434 host->data = req->data;
1435
1436 if (req->data == NULL) {
a45c6cb8 1437 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1438 /*
1439 * Set an arbitrary 100ms data timeout for commands with
1440 * busy signal.
1441 */
1442 if (req->cmd->flags & MMC_RSP_BUSY)
1443 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1444 return 0;
1445 }
1446
1447 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1448 | (req->data->blocks << 16));
e2bf08d6 1449 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1450
a45c6cb8 1451 if (host->use_dma) {
70a3341a 1452 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1453 if (ret != 0) {
1454 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1455 return ret;
1456 }
1457 }
1458 return 0;
1459}
1460
1461/*
1462 * Request function. for read/write operation
1463 */
70a3341a 1464static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1465{
70a3341a 1466 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1467 int err;
a45c6cb8 1468
b417577d
AH		 1469 BUG_ON(host->req_in_progress);
1470 BUG_ON(host->dma_ch != -1);
1471 if (host->protect_card) {
1472 if (host->reqs_blocked < 3) {
1473 /*
1474 * Ensure the controller is left in a consistent
1475 * state by resetting the command and data state
1476 * machines.
1477 */
1478 omap_hsmmc_reset_controller_fsm(host, SRD);
1479 omap_hsmmc_reset_controller_fsm(host, SRC);
1480 host->reqs_blocked += 1;
1481 }
1482 req->cmd->error = -EBADF;
1483 if (req->data)
1484 req->data->error = -EBADF;
1485 req->cmd->retries = 0;
1486 mmc_request_done(mmc, req);
1487 return;
1488 } else if (host->reqs_blocked)
1489 host->reqs_blocked = 0;
a45c6cb8
MC		 1490 WARN_ON(host->mrq != NULL);
1491 host->mrq = req;
70a3341a 1492 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1493 if (err) {
1494 req->cmd->error = err;
1495 if (req->data)
1496 req->data->error = err;
1497 host->mrq = NULL;
1498 mmc_request_done(mmc, req);
1499 return;
1500 }
1501
70a3341a 1502 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1503}
1504
a45c6cb8 1505/* Routine to configure clock values. Exposed API to core */
70a3341a 1506static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1507{
70a3341a 1508 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1509 u16 dsor = 0;
1510 unsigned long regval;
1511 unsigned long timeout;
73153010 1512 u32 con;
a3621465 1513 int do_send_init_stream = 0;
a45c6cb8 1514
5e2ea617
AH		 1515 mmc_host_enable(host->mmc);
1516
a3621465
AH		 1517 if (ios->power_mode != host->power_mode) {
1518 switch (ios->power_mode) {
1519 case MMC_POWER_OFF:
1520 mmc_slot(host).set_power(host->dev, host->slot_id,
1521 0, 0);
623821f7 1522 host->vdd = 0;
a3621465
AH		 1523 break;
1524 case MMC_POWER_UP:
1525 mmc_slot(host).set_power(host->dev, host->slot_id,
1526 1, ios->vdd);
623821f7 1527 host->vdd = ios->vdd;
a3621465
AH		 1528 break;
1529 case MMC_POWER_ON:
1530 do_send_init_stream = 1;
1531 break;
1532 }
1533 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1534 }
1535
dd498eff
DK		 1536 /* FIXME: set registers based only on changes to ios */
1537
73153010 1538 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1539 switch (mmc->ios.bus_width) {
73153010
JL		 1540 case MMC_BUS_WIDTH_8:
1541 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1542 break;
a45c6cb8 1543 case MMC_BUS_WIDTH_4:
73153010 1544 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1545 OMAP_HSMMC_WRITE(host->base, HCTL,
1546 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1547 break;
1548 case MMC_BUS_WIDTH_1:
73153010 1549 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1550 OMAP_HSMMC_WRITE(host->base, HCTL,
1551 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1552 break;
1553 }
1554
1555 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1556 /* Only MMC1 can interface at 3V without some flavor
1557 * of external transceiver; but they all handle 1.8V.
1558 */
a45c6cb8
MC		 1559 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1560 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1561 /*
1562 * The mmc_select_voltage fn of the core does
1563 * not seem to set the power_mode to
1564 * MMC_POWER_UP upon recalculating the voltage.
1565 * vdd 1.8v.
1566 */
70a3341a
DK		 1567 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1568 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1569 "Switch operation failed\n");
1570 }
1571 }
1572
1573 if (ios->clock) {
1574 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1575 if (dsor < 1)
1576 dsor = 1;
1577
1578 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1579 dsor++;
1580
1581 if (dsor > 250)
1582 dsor = 250;
1583 }
70a3341a 1584 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1585 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1586 regval = regval & ~(CLKD_MASK);
1587 regval = regval | (dsor << 6) | (DTO << 16);
1588 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1589 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1590 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1591
1592 /* Wait till the ICS bit is set */
1593 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1594 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1595 && time_before(jiffies, timeout))
1596 msleep(1);
1597
1598 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1599 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1600
a3621465 1601 if (do_send_init_stream)
a45c6cb8
MC		 1602 send_init_stream(host);
1603
abb28e73 1604 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1605 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1606 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1607 else
1608 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1609
dd498eff
DK		 1610 if (host->power_mode == MMC_POWER_OFF)
1611 mmc_host_disable(host->mmc);
1612 else
1613 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1614}
1615
1616static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1617{
70a3341a 1618 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1619
191d1f1d 1620 if (!mmc_slot(host).card_detect)
a45c6cb8 1621 return -ENOSYS;
db0fefc5 1622 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1623}
1624
1625static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1626{
70a3341a 1627 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1628
191d1f1d 1629 if (!mmc_slot(host).get_ro)
a45c6cb8 1630 return -ENOSYS;
191d1f1d 1631 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1632}
1633
4816858c
GI		 1634static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1635{
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1637
1638 if (mmc_slot(host).init_card)
1639 mmc_slot(host).init_card(card);
1640}
1641
70a3341a 1642static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1643{
1644 u32 hctl, capa, value;
1645
1646 /* Only MMC1 supports 3.0V */
1647 if (host->id == OMAP_MMC1_DEVID) {
1648 hctl = SDVS30;
1649 capa = VS30 | VS18;
1650 } else {
1651 hctl = SDVS18;
1652 capa = VS18;
1653 }
1654
1655 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1656 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1657
1658 value = OMAP_HSMMC_READ(host->base, CAPA);
1659 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1660
1661 /* Set the controller to AUTO IDLE mode */
1662 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1663 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1664
1665 /* Set SD bus power bit */
e13bb300 1666 set_sd_bus_power(host);
1b331e69
KK		 1667}
1668
dd498eff
DK		 1669/*
1670 * Dynamic power saving handling, FSM:
13189e78
JL		 1671 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1672 * ^___________| | |
1673 * |______________________|______________________|
dd498eff
DK		 1674 *
1675 * ENABLED: mmc host is fully functional
1676 * DISABLED: fclk is off
13189e78
JL		 1677 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1678 * REGSLEEP: fclk is off, voltage regulator is asleep
1679 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1680 *
1681 * Transition handlers return the timeout for the next state transition
1682 * or negative error.
1683 */
1684
13189e78 1685enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1686
1687/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1688static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1689{
70a3341a 1690 omap_hsmmc_context_save(host);
dd498eff
DK		 1691 clk_disable(host->fclk);
1692 host->dpm_state = DISABLED;
1693
1694 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1695
1696 if (host->power_mode == MMC_POWER_OFF)
1697 return 0;
1698
4380eea2 1699 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1700}
1701
13189e78 1702/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1703static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1704{
13189e78 1705 int err, new_state;
dd498eff
DK		 1706
1707 if (!mmc_try_claim_host(host->mmc))
1708 return 0;
1709
1710 clk_enable(host->fclk);
70a3341a 1711 omap_hsmmc_context_restore(host);
13189e78
JL		 1712 if (mmc_card_can_sleep(host->mmc)) {
1713 err = mmc_card_sleep(host->mmc);
1714 if (err < 0) {
1715 clk_disable(host->fclk);
1716 mmc_release_host(host->mmc);
1717 return err;
1718 }
1719 new_state = CARDSLEEP;
70a3341a 1720 } else {
13189e78 1721 new_state = REGSLEEP;
70a3341a 1722 }
13189e78
JL		 1723 if (mmc_slot(host).set_sleep)
1724 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1725 new_state == CARDSLEEP);
1726 /* FIXME: turn off bus power and perhaps interrupts too */
1727 clk_disable(host->fclk);
1728 host->dpm_state = new_state;
1729
1730 mmc_release_host(host->mmc);
1731
1732 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1733 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1734
1df58db8
AH		 1735 if (mmc_slot(host).no_off)
1736 return 0;
1737
dd498eff
DK		 1738 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1739 mmc_slot(host).card_detect ||
1740 (mmc_slot(host).get_cover_state &&
13189e78 1741 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1742 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1743
1744 return 0;
1745}
1746
1747/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1748static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1749{
1750 if (!mmc_try_claim_host(host->mmc))
1751 return 0;
1752
1df58db8
AH		 1753 if (mmc_slot(host).no_off)
1754 return 0;
1755
13189e78
JL		 1756 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1757 mmc_slot(host).card_detect ||
1758 (mmc_slot(host).get_cover_state &&
1759 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1760 mmc_release_host(host->mmc);
1761 return 0;
623821f7 1762 }
dd498eff 1763
13189e78
JL		 1764 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1765 host->vdd = 0;
1766 host->power_mode = MMC_POWER_OFF;
dd498eff 1767
13189e78
JL		 1768 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1769 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1770
13189e78 1771 host->dpm_state = OFF;
dd498eff
DK		 1772
1773 mmc_release_host(host->mmc);
1774
1775 return 0;
1776}
1777
1778/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1779static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1780{
1781 int err;
1782
1783 err = clk_enable(host->fclk);
1784 if (err < 0)
1785 return err;
1786
70a3341a 1787 omap_hsmmc_context_restore(host);
dd498eff
DK		 1788 host->dpm_state = ENABLED;
1789
1790 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1791
1792 return 0;
1793}
1794
13189e78 1795/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1796static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1797{
13189e78
JL		 1798 if (!mmc_try_claim_host(host->mmc))
1799 return 0;
dd498eff 1800
13189e78 1801 clk_enable(host->fclk);
70a3341a 1802 omap_hsmmc_context_restore(host);
13189e78
JL		 1803 if (mmc_slot(host).set_sleep)
1804 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1805 host->vdd, host->dpm_state == CARDSLEEP);
1806 if (mmc_card_can_sleep(host->mmc))
1807 mmc_card_awake(host->mmc);
1808
1809 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1810 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1811
1812 host->dpm_state = ENABLED;
1813
13189e78 1814 mmc_release_host(host->mmc);
dd498eff
DK		 1815
1816 return 0;
1817}
1818
13189e78 1819/* Handler for [OFF -> ENABLED] transition */
70a3341a 1820static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1821{
623821f7 1822 clk_enable(host->fclk);
623821f7 1823
70a3341a
DK		 1824 omap_hsmmc_context_restore(host);
1825 omap_hsmmc_conf_bus_power(host);
13189e78 1826 mmc_power_restore_host(host->mmc);
623821f7
AH		 1827
1828 host->dpm_state = ENABLED;
1829
13189e78
JL		 1830 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1831
623821f7
AH		 1832 return 0;
1833}
1834
dd498eff
DK		 1835/*
1836 * Bring MMC host to ENABLED from any other PM state.
1837 */
70a3341a 1838static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1839{
70a3341a 1840 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1841
1842 switch (host->dpm_state) {
1843 case DISABLED:
70a3341a 1844 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1845 case CARDSLEEP:
623821f7 1846 case REGSLEEP:
70a3341a 1847 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1848 case OFF:
70a3341a 1849 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1850 default:
1851 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1852 return -EINVAL;
1853 }
1854}
1855
1856/*
1857 * Bring MMC host in PM state (one level deeper).
1858 */
70a3341a 1859static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1860{
70a3341a 1861 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1862
1863 switch (host->dpm_state) {
1864 case ENABLED: {
1865 int delay;
1866
70a3341a 1867 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1868 if (lazy || delay < 0)
1869 return delay;
1870 return 0;
1871 }
1872 case DISABLED:
70a3341a 1873 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1874 case CARDSLEEP:
1875 case REGSLEEP:
70a3341a 1876 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1877 default:
1878 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1879 return -EINVAL;
1880 }
1881}
1882
70a3341a 1883static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1884{
70a3341a 1885 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1886 int err;
1887
1888 err = clk_enable(host->fclk);
1889 if (err)
1890 return err;
1891 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1892 omap_hsmmc_context_restore(host);
dd498eff
DK		 1893 return 0;
1894}
1895
70a3341a 1896static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1897{
70a3341a 1898 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1899
70a3341a 1900 omap_hsmmc_context_save(host);
dd498eff
DK		 1901 clk_disable(host->fclk);
1902 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1903 return 0;
1904}
1905
70a3341a
DK		 1906static const struct mmc_host_ops omap_hsmmc_ops = {
1907 .enable = omap_hsmmc_enable_fclk,
1908 .disable = omap_hsmmc_disable_fclk,
1909 .request = omap_hsmmc_request,
1910 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1911 .get_cd = omap_hsmmc_get_cd,
1912 .get_ro = omap_hsmmc_get_ro,
4816858c 1913 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1914 /* NYET -- enable_sdio_irq */
1915};
1916
70a3341a
DK		 1917static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1918 .enable = omap_hsmmc_enable,
1919 .disable = omap_hsmmc_disable,
1920 .request = omap_hsmmc_request,
1921 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1922 .get_cd = omap_hsmmc_get_cd,
1923 .get_ro = omap_hsmmc_get_ro,
4816858c 1924 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1925 /* NYET -- enable_sdio_irq */
1926};
1927
d900f712
DK		 1928#ifdef CONFIG_DEBUG_FS
1929
70a3341a 1930static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1931{
1932 struct mmc_host *mmc = s->private;
70a3341a 1933 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1934 int context_loss = 0;
1935
70a3341a
DK		 1936 if (host->pdata->get_context_loss_count)
1937 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1938
5e2ea617
AH		 1939 seq_printf(s, "mmc%d:\n"
1940 " enabled:\t%d\n"
dd498eff 1941 " dpm_state:\t%d\n"
5e2ea617 1942 " nesting_cnt:\t%d\n"
11dd62a7 1943 " ctx_loss:\t%d:%d\n"
5e2ea617 1944 "\nregs:\n",
dd498eff
DK		 1945 mmc->index, mmc->enabled ? 1 : 0,
1946 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1947 host->context_loss, context_loss);
5e2ea617 1948
13189e78 1949 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1950 seq_printf(s, "host suspended, can't read registers\n");
1951 return 0;
1952 }
1953
5e2ea617
AH		 1954 if (clk_enable(host->fclk) != 0) {
1955 seq_printf(s, "can't read the regs\n");
dd498eff 1956 return 0;
5e2ea617 1957 }
d900f712
DK		 1958
1959 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1960 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1961 seq_printf(s, "CON:\t\t0x%08x\n",
1962 OMAP_HSMMC_READ(host->base, CON));
1963 seq_printf(s, "HCTL:\t\t0x%08x\n",
1964 OMAP_HSMMC_READ(host->base, HCTL));
1965 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1966 OMAP_HSMMC_READ(host->base, SYSCTL));
1967 seq_printf(s, "IE:\t\t0x%08x\n",
1968 OMAP_HSMMC_READ(host->base, IE));
1969 seq_printf(s, "ISE:\t\t0x%08x\n",
1970 OMAP_HSMMC_READ(host->base, ISE));
1971 seq_printf(s, "CAPA:\t\t0x%08x\n",
1972 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1973
1974 clk_disable(host->fclk);
dd498eff 1975
d900f712
DK		 1976 return 0;
1977}
1978
70a3341a 1979static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1980{
70a3341a 1981 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1982}
1983
1984static const struct file_operations mmc_regs_fops = {
70a3341a 1985 .open = omap_hsmmc_regs_open,
d900f712
DK		 1986 .read = seq_read,
1987 .llseek = seq_lseek,
1988 .release = single_release,
1989};
1990
70a3341a 1991static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1992{
1993 if (mmc->debugfs_root)
1994 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1995 mmc, &mmc_regs_fops);
1996}
1997
1998#else
1999
70a3341a 2000static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 2001{
2002}
2003
2004#endif
2005
70a3341a 2006static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 2007{
2008 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2009 struct mmc_host *mmc;
70a3341a 2010 struct omap_hsmmc_host *host = NULL;
a45c6cb8 2011 struct resource *res;
db0fefc5 2012 int ret, irq;
a45c6cb8
MC		 2013
2014 if (pdata == NULL) {
2015 dev_err(&pdev->dev, "Platform Data is missing\n");
2016 return -ENXIO;
2017 }
2018
2019 if (pdata->nr_slots == 0) {
2020 dev_err(&pdev->dev, "No Slots\n");
2021 return -ENXIO;
2022 }
2023
2024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2025 irq = platform_get_irq(pdev, 0);
2026 if (res == NULL || irq < 0)
2027 return -ENXIO;
2028
91a0b089 2029 res->start += pdata->reg_offset;
2030 res->end += pdata->reg_offset;
a45c6cb8
MC		 2031 res = request_mem_region(res->start, res->end - res->start + 1,
2032 pdev->name);
2033 if (res == NULL)
2034 return -EBUSY;
2035
db0fefc5
AH		 2036 ret = omap_hsmmc_gpio_init(pdata);
2037 if (ret)
2038 goto err;
2039
70a3341a 2040 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2041 if (!mmc) {
2042 ret = -ENOMEM;
db0fefc5 2043 goto err_alloc;
a45c6cb8
MC		 2044 }
2045
2046 host = mmc_priv(mmc);
2047 host->mmc = mmc;
2048 host->pdata = pdata;
2049 host->dev = &pdev->dev;
2050 host->use_dma = 1;
2051 host->dev->dma_mask = &pdata->dma_mask;
2052 host->dma_ch = -1;
2053 host->irq = irq;
2054 host->id = pdev->id;
2055 host->slot_id = 0;
2056 host->mapbase = res->start;
2057 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2058 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2059
2060 platform_set_drvdata(pdev, host);
70a3341a 2061 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2062
191d1f1d 2063 if (mmc_slot(host).power_saving)
70a3341a 2064 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2065 else
70a3341a 2066 mmc->ops = &omap_hsmmc_ops;
dd498eff 2067
e0eb2424
AH		 2068 /*
2069 * If regulator_disable can only put vcc_aux to sleep then there is
2070 * no off state.
2071 */
2072 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2073 mmc_slot(host).no_off = 1;
2074
a45c6cb8
MC		 2075 mmc->f_min = 400000;
2076 mmc->f_max = 52000000;
2077
4dffd7a2 2078 spin_lock_init(&host->irq_lock);
a45c6cb8 2079
6f7607cc 2080 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2081 if (IS_ERR(host->iclk)) {
2082 ret = PTR_ERR(host->iclk);
2083 host->iclk = NULL;
2084 goto err1;
2085 }
6f7607cc 2086 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2087 if (IS_ERR(host->fclk)) {
2088 ret = PTR_ERR(host->fclk);
2089 host->fclk = NULL;
2090 clk_put(host->iclk);
2091 goto err1;
2092 }
2093
70a3341a 2094 omap_hsmmc_context_save(host);
11dd62a7 2095
5e2ea617 2096 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2097 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2098 /* we start off in DISABLED state */
2099 host->dpm_state = DISABLED;
2100
5e2ea617 2101 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 2102 clk_put(host->iclk);
2103 clk_put(host->fclk);
2104 goto err1;
2105 }
2106
2107 if (clk_enable(host->iclk) != 0) {
5e2ea617 2108 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2109 clk_put(host->iclk);
2110 clk_put(host->fclk);
2111 goto err1;
2112 }
2113
2bec0893
AH		 2114 if (cpu_is_omap2430()) {
2115 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2116 /*
2117 * MMC can still work without debounce clock.
2118 */
2119 if (IS_ERR(host->dbclk))
2120 dev_warn(mmc_dev(host->mmc),
2121 "Failed to get debounce clock\n");
a45c6cb8 2122 else
2bec0893
AH		 2123 host->got_dbclk = 1;
2124
2125 if (host->got_dbclk)
2126 if (clk_enable(host->dbclk) != 0)
2127 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2128 " clk failed\n");
2129 }
a45c6cb8 2130
0ccd76d4
JY		 2131 /* Since we do only SG emulation, we can have as many segs
2132 * as we want. */
2133 mmc->max_phys_segs = 1024;
2134 mmc->max_hw_segs = 1024;
2135
a45c6cb8
MC		 2136 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2137 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2138 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2139 mmc->max_seg_size = mmc->max_req_size;
2140
13189e78 2141 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2142 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2143
3a63833e
SG		 2144 mmc->caps |= mmc_slot(host).caps;
2145 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2146 mmc->caps |= MMC_CAP_4_BIT_DATA;
2147
191d1f1d 2148 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2149 mmc->caps |= MMC_CAP_NONREMOVABLE;
2150
70a3341a 2151 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2152
f3e2f1dd
GI		 2153 /* Select DMA lines */
2154 switch (host->id) {
2155 case OMAP_MMC1_DEVID:
2156 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2157 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2158 break;
2159 case OMAP_MMC2_DEVID:
2160 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2161 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2162 break;
2163 case OMAP_MMC3_DEVID:
2164 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2165 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2166 break;
82cf818d 2167 case OMAP_MMC4_DEVID:
2168 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2169 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2170 break;
2171 case OMAP_MMC5_DEVID:
2172 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2173 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2174 break;
f3e2f1dd
GI		 2175 default:
2176 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2177 goto err_irq;
2178 }
a45c6cb8
MC		 2179
2180 /* Request IRQ for MMC operations */
70a3341a 2181 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2182 mmc_hostname(mmc), host);
2183 if (ret) {
2184 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2185 goto err_irq;
2186 }
2187
2188 if (pdata->init != NULL) {
2189 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2190 dev_dbg(mmc_dev(host->mmc),
2191 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2192 goto err_irq_cd_init;
2193 }
2194 }
db0fefc5 2195
b702b106 2196 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2197 ret = omap_hsmmc_reg_get(host);
2198 if (ret)
2199 goto err_reg;
2200 host->use_reg = 1;
2201 }
2202
b583f26d 2203 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2204
2205 /* Request IRQ for card detect */
e1a55f5e 2206 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2207 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2208 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2209 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2210 | IRQF_DISABLED,
2211 mmc_hostname(mmc), host);
2212 if (ret) {
2213 dev_dbg(mmc_dev(host->mmc),
2214 "Unable to grab MMC CD IRQ\n");
2215 goto err_irq_cd;
2216 }
2217 }
2218
b417577d 2219 omap_hsmmc_disable_irq(host);
a45c6cb8 2220
5e2ea617
AH		 2221 mmc_host_lazy_disable(host->mmc);
2222
b62f6228
AH		 2223 omap_hsmmc_protect_card(host);
2224
a45c6cb8
MC		 2225 mmc_add_host(mmc);
2226
191d1f1d 2227 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2228 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2229 if (ret < 0)
2230 goto err_slot_name;
2231 }
191d1f1d 2232 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2233 ret = device_create_file(&mmc->class_dev,
2234 &dev_attr_cover_switch);
2235 if (ret < 0)
db0fefc5 2236 goto err_slot_name;
a45c6cb8
MC		 2237 }
2238
70a3341a 2239 omap_hsmmc_debugfs(mmc);
d900f712 2240
a45c6cb8
MC		 2241 return 0;
2242
a45c6cb8
MC		 2243err_slot_name:
2244 mmc_remove_host(mmc);
a45c6cb8 2245 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2246err_irq_cd:
2247 if (host->use_reg)
2248 omap_hsmmc_reg_put(host);
2249err_reg:
2250 if (host->pdata->cleanup)
2251 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2252err_irq_cd_init:
2253 free_irq(host->irq, host);
2254err_irq:
5e2ea617 2255 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2256 clk_disable(host->iclk);
2257 clk_put(host->fclk);
2258 clk_put(host->iclk);
2bec0893 2259 if (host->got_dbclk) {
a45c6cb8
MC		 2260 clk_disable(host->dbclk);
2261 clk_put(host->dbclk);
2262 }
a45c6cb8
MC		 2263err1:
2264 iounmap(host->base);
db0fefc5
AH		 2265 platform_set_drvdata(pdev, NULL);
2266 mmc_free_host(mmc);
2267err_alloc:
2268 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2269err:
a45c6cb8 2270 release_mem_region(res->start, res->end - res->start + 1);
a45c6cb8
MC		 2271 return ret;
2272}
2273
70a3341a 2274static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2275{
70a3341a 2276 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2277 struct resource *res;
2278
2279 if (host) {
5e2ea617 2280 mmc_host_enable(host->mmc);
a45c6cb8 2281 mmc_remove_host(host->mmc);
db0fefc5
AH		 2282 if (host->use_reg)
2283 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2284 if (host->pdata->cleanup)
2285 host->pdata->cleanup(&pdev->dev);
2286 free_irq(host->irq, host);
2287 if (mmc_slot(host).card_detect_irq)
2288 free_irq(mmc_slot(host).card_detect_irq, host);
2289 flush_scheduled_work();
2290
5e2ea617 2291 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2292 clk_disable(host->iclk);
2293 clk_put(host->fclk);
2294 clk_put(host->iclk);
2bec0893 2295 if (host->got_dbclk) {
a45c6cb8
MC		 2296 clk_disable(host->dbclk);
2297 clk_put(host->dbclk);
2298 }
2299
2300 mmc_free_host(host->mmc);
2301 iounmap(host->base);
db0fefc5 2302 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2303 }
2304
2305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2306 if (res)
2307 release_mem_region(res->start, res->end - res->start + 1);
2308 platform_set_drvdata(pdev, NULL);
2309
2310 return 0;
2311}
2312
2313#ifdef CONFIG_PM
a791daa1 2314static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2315{
2316 int ret = 0;
a791daa1 2317 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2318 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2319
2320 if (host && host->suspended)
2321 return 0;
2322
2323 if (host) {
a6b2240d
AH		 2324 host->suspended = 1;
2325 if (host->pdata->suspend) {
2326 ret = host->pdata->suspend(&pdev->dev,
2327 host->slot_id);
2328 if (ret) {
2329 dev_dbg(mmc_dev(host->mmc),
2330 "Unable to handle MMC board"
2331 " level suspend\n");
2332 host->suspended = 0;
2333 return ret;
2334 }
2335 }
2336 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2337 ret = mmc_suspend_host(host->mmc);
e7cb756f 2338 mmc_host_enable(host->mmc);
a45c6cb8 2339 if (ret == 0) {
b417577d 2340 omap_hsmmc_disable_irq(host);
0683af48 2341 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2342 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2343 mmc_host_disable(host->mmc);
a45c6cb8 2344 clk_disable(host->iclk);
2bec0893
AH		 2345 if (host->got_dbclk)
2346 clk_disable(host->dbclk);
a6b2240d
AH		 2347 } else {
2348 host->suspended = 0;
2349 if (host->pdata->resume) {
2350 ret = host->pdata->resume(&pdev->dev,
2351 host->slot_id);
2352 if (ret)
2353 dev_dbg(mmc_dev(host->mmc),
2354 "Unmask interrupt failed\n");
2355 }
5e2ea617 2356 mmc_host_disable(host->mmc);
a6b2240d 2357 }
a45c6cb8
MC		 2358
2359 }
2360 return ret;
2361}
2362
2363/* Routine to resume the MMC device */
a791daa1 2364static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2365{
2366 int ret = 0;
a791daa1 2367 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2368 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2369
2370 if (host && !host->suspended)
2371 return 0;
2372
2373 if (host) {
a45c6cb8 2374 ret = clk_enable(host->iclk);
11dd62a7 2375 if (ret)
a45c6cb8 2376 goto clk_en_err;
a45c6cb8 2377
11dd62a7
DK		 2378 if (mmc_host_enable(host->mmc) != 0) {
2379 clk_disable(host->iclk);
2380 goto clk_en_err;
2381 }
2382
2bec0893
AH		 2383 if (host->got_dbclk)
2384 clk_enable(host->dbclk);
2385
70a3341a 2386 omap_hsmmc_conf_bus_power(host);
1b331e69 2387
a45c6cb8
MC		 2388 if (host->pdata->resume) {
2389 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2390 if (ret)
2391 dev_dbg(mmc_dev(host->mmc),
2392 "Unmask interrupt failed\n");
2393 }
2394
b62f6228
AH		 2395 omap_hsmmc_protect_card(host);
2396
a45c6cb8
MC		 2397 /* Notify the core to resume the host */
2398 ret = mmc_resume_host(host->mmc);
2399 if (ret == 0)
2400 host->suspended = 0;
70a3341a 2401
5e2ea617 2402 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2403 }
2404
2405 return ret;
2406
2407clk_en_err:
2408 dev_dbg(mmc_dev(host->mmc),
2409 "Failed to enable MMC clocks during resume\n");
2410 return ret;
2411}
2412
2413#else
70a3341a
DK		 2414#define omap_hsmmc_suspend NULL
2415#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2416#endif
2417
a791daa1 2418static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2419 .suspend = omap_hsmmc_suspend,
2420 .resume = omap_hsmmc_resume,
a791daa1
KH		 2421};
2422
2423static struct platform_driver omap_hsmmc_driver = {
2424 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2425 .driver = {
2426 .name = DRIVER_NAME,
2427 .owner = THIS_MODULE,
a791daa1 2428 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2429 },
2430};
2431
70a3341a 2432static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2433{
2434 /* Register the MMC driver */
8753298a 2435 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2436}
2437
70a3341a 2438static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2439{
2440 /* Unregister MMC driver */
70a3341a 2441 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2442}
2443
70a3341a
DK		 2444module_init(omap_hsmmc_init);
2445module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2446
2447MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2448MODULE_LICENSE("GPL");
2449MODULE_ALIAS("platform:" DRIVER_NAME);
2450MODULE_AUTHOR("Texas Instruments Inc");
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