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mmc: Move regulator handling closer to core
[net-next-2.6.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
121#define DRIVER_NAME "mmci-omap-hs"
122
dd498eff
DK		 123/* Timeouts for entering power saving states on inactivity, msec */
124#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 125#define OMAP_MMC_SLEEP_TIMEOUT 1000
126#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 127
a45c6cb8
MC		 128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
11dd62a7 187
a45c6cb8
MC		 188 struct omap_mmc_platform_data *pdata;
189};
190
db0fefc5
AH		 191static int omap_hsmmc_card_detect(struct device *dev, int slot)
192{
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
194
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
197}
198
199static int omap_hsmmc_get_wp(struct device *dev, int slot)
200{
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205}
206
207static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208{
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
210
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
213}
214
215#ifdef CONFIG_PM
216
217static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
218{
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
220
221 disable_irq(mmc->slots[0].card_detect_irq);
222 return 0;
223}
224
225static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
226{
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
228
229 enable_irq(mmc->slots[0].card_detect_irq);
230 return 0;
231}
232
233#else
234
235#define omap_hsmmc_suspend_cdirq NULL
236#define omap_hsmmc_resume_cdirq NULL
237
238#endif
239
b702b106
AH		 240#ifdef CONFIG_REGULATOR
241
db0fefc5
AH		 242static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
243 int vdd)
244{
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
247 int ret;
248
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
251
252 if (power_on)
99fc5131 253 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 254 else
99fc5131 255 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 256
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
259
260 return ret;
261}
262
263static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
264 int vdd)
265{
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
268 int ret = 0;
269
270 /*
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
273 */
274 if (!host->vcc)
275 return 0;
276
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
279
280 /*
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 *
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
288 *
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
292 */
293 if (power_on) {
99fc5131 294 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
298 if (ret < 0)
99fc5131
LW		 299 ret = mmc_regulator_set_ocr(host->mmc,
300 host->vcc, 0);
db0fefc5
AH		 301 }
302 } else {
99fc5131 303 /* Shut down the rail */
6da20c89
AH		 304 if (host->vcc_aux)
305 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 306 if (!ret) {
307 /* Then proceed to shut down the local regulator */
308 ret = mmc_regulator_set_ocr(host->mmc,
309 host->vcc, 0);
310 }
db0fefc5
AH		 311 }
312
313 if (mmc_slot(host).after_set_reg)
314 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
315
316 return ret;
317}
318
319static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
320 int vdd, int cardsleep)
321{
322 struct omap_hsmmc_host *host =
323 platform_get_drvdata(to_platform_device(dev));
324 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
325
326 return regulator_set_mode(host->vcc, mode);
327}
328
329static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
330 int vdd, int cardsleep)
331{
332 struct omap_hsmmc_host *host =
333 platform_get_drvdata(to_platform_device(dev));
334 int err, mode;
335
336 /*
337 * If we don't see a Vcc regulator, assume it's a fixed
338 * voltage always-on regulator.
339 */
340 if (!host->vcc)
341 return 0;
342
343 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
344
345 if (!host->vcc_aux)
346 return regulator_set_mode(host->vcc, mode);
347
348 if (cardsleep) {
349 /* VCC can be turned off if card is asleep */
350 if (sleep)
99fc5131 351 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 352 else
99fc5131 353 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 354 } else
355 err = regulator_set_mode(host->vcc, mode);
356 if (err)
357 return err;
e0eb2424
AH		 358
359 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
360 return regulator_set_mode(host->vcc_aux, mode);
361
362 if (sleep)
363 return regulator_disable(host->vcc_aux);
364 else
365 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 366}
367
db0fefc5
AH		 368static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369{
370 struct regulator *reg;
371 int ret = 0;
372
373 switch (host->id) {
374 case OMAP_MMC1_DEVID:
375 /* On-chip level shifting via PBIAS0/PBIAS1 */
376 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
377 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
378 break;
379 case OMAP_MMC2_DEVID:
380 case OMAP_MMC3_DEVID:
381 /* Off-chip level shifting, or none */
382 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
383 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
384 break;
385 default:
386 pr_err("MMC%d configuration not supported!\n", host->id);
387 return -EINVAL;
388 }
389
390 reg = regulator_get(host->dev, "vmmc");
391 if (IS_ERR(reg)) {
392 dev_dbg(host->dev, "vmmc regulator missing\n");
393 /*
394 * HACK: until fixed.c regulator is usable,
395 * we don't require a main regulator
396 * for MMC2 or MMC3
397 */
398 if (host->id == OMAP_MMC1_DEVID) {
399 ret = PTR_ERR(reg);
400 goto err;
401 }
402 } else {
403 host->vcc = reg;
404 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
405
406 /* Allow an aux regulator */
407 reg = regulator_get(host->dev, "vmmc_aux");
408 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
409
410 /*
411 * UGLY HACK: workaround regulator framework bugs.
412 * When the bootloader leaves a supply active, it's
413 * initialized with zero usecount ... and we can't
414 * disable it without first enabling it. Until the
415 * framework is fixed, we need a workaround like this
416 * (which is safe for MMC, but not in general).
417 */
418 if (regulator_is_enabled(host->vcc) > 0) {
419 regulator_enable(host->vcc);
420 regulator_disable(host->vcc);
421 }
422 if (host->vcc_aux) {
423 if (regulator_is_enabled(reg) > 0) {
424 regulator_enable(reg);
425 regulator_disable(reg);
426 }
427 }
428 }
429
430 return 0;
431
432err:
433 mmc_slot(host).set_power = NULL;
434 mmc_slot(host).set_sleep = NULL;
435 return ret;
436}
437
438static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
439{
440 regulator_put(host->vcc);
441 regulator_put(host->vcc_aux);
442 mmc_slot(host).set_power = NULL;
443 mmc_slot(host).set_sleep = NULL;
444}
445
b702b106
AH		 446static inline int omap_hsmmc_have_reg(void)
447{
448 return 1;
449}
450
451#else
452
453static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
454{
455 return -EINVAL;
456}
457
458static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
459{
460}
461
462static inline int omap_hsmmc_have_reg(void)
463{
464 return 0;
465}
466
467#endif
468
469static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
470{
471 int ret;
472
473 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
474 pdata->suspend = omap_hsmmc_suspend_cdirq;
475 pdata->resume = omap_hsmmc_resume_cdirq;
476 if (pdata->slots[0].cover)
477 pdata->slots[0].get_cover_state =
478 omap_hsmmc_get_cover_state;
479 else
480 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
481 pdata->slots[0].card_detect_irq =
482 gpio_to_irq(pdata->slots[0].switch_pin);
483 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
484 if (ret)
485 return ret;
486 ret = gpio_direction_input(pdata->slots[0].switch_pin);
487 if (ret)
488 goto err_free_sp;
489 } else
490 pdata->slots[0].switch_pin = -EINVAL;
491
492 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
493 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
494 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
495 if (ret)
496 goto err_free_cd;
497 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
498 if (ret)
499 goto err_free_wp;
500 } else
501 pdata->slots[0].gpio_wp = -EINVAL;
502
503 return 0;
504
505err_free_wp:
506 gpio_free(pdata->slots[0].gpio_wp);
507err_free_cd:
508 if (gpio_is_valid(pdata->slots[0].switch_pin))
509err_free_sp:
510 gpio_free(pdata->slots[0].switch_pin);
511 return ret;
512}
513
514static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
515{
516 if (gpio_is_valid(pdata->slots[0].gpio_wp))
517 gpio_free(pdata->slots[0].gpio_wp);
518 if (gpio_is_valid(pdata->slots[0].switch_pin))
519 gpio_free(pdata->slots[0].switch_pin);
520}
521
a45c6cb8
MC		 522/*
523 * Stop clock to the card
524 */
70a3341a 525static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 526{
527 OMAP_HSMMC_WRITE(host->base, SYSCTL,
528 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
529 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
530 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
531}
532
93caf8e6
AH		 533static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
534 struct mmc_command *cmd)
b417577d
AH		 535{
536 unsigned int irq_mask;
537
538 if (host->use_dma)
539 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
540 else
541 irq_mask = INT_EN_MASK;
542
93caf8e6
AH		 543 /* Disable timeout for erases */
544 if (cmd->opcode == MMC_ERASE)
545 irq_mask &= ~DTO_ENABLE;
546
b417577d
AH		 547 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
548 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
549 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
550}
551
552static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
553{
554 OMAP_HSMMC_WRITE(host->base, ISE, 0);
555 OMAP_HSMMC_WRITE(host->base, IE, 0);
556 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
557}
558
11dd62a7
DK		 559#ifdef CONFIG_PM
560
561/*
562 * Restore the MMC host context, if it was lost as result of a
563 * power state change.
564 */
70a3341a 565static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 566{
567 struct mmc_ios *ios = &host->mmc->ios;
568 struct omap_mmc_platform_data *pdata = host->pdata;
569 int context_loss = 0;
570 u32 hctl, capa, con;
571 u16 dsor = 0;
572 unsigned long timeout;
573
574 if (pdata->get_context_loss_count) {
575 context_loss = pdata->get_context_loss_count(host->dev);
576 if (context_loss < 0)
577 return 1;
578 }
579
580 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
581 context_loss == host->context_loss ? "not " : "");
582 if (host->context_loss == context_loss)
583 return 1;
584
585 /* Wait for hardware reset */
586 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
587 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
588 && time_before(jiffies, timeout))
589 ;
590
591 /* Do software reset */
592 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
593 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
594 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
595 && time_before(jiffies, timeout))
596 ;
597
598 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
599 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
600
601 if (host->id == OMAP_MMC1_DEVID) {
602 if (host->power_mode != MMC_POWER_OFF &&
603 (1 << ios->vdd) <= MMC_VDD_23_24)
604 hctl = SDVS18;
605 else
606 hctl = SDVS30;
607 capa = VS30 | VS18;
608 } else {
609 hctl = SDVS18;
610 capa = VS18;
611 }
612
613 OMAP_HSMMC_WRITE(host->base, HCTL,
614 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
615
616 OMAP_HSMMC_WRITE(host->base, CAPA,
617 OMAP_HSMMC_READ(host->base, CAPA) | capa);
618
619 OMAP_HSMMC_WRITE(host->base, HCTL,
620 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
621
622 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
623 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
624 && time_before(jiffies, timeout))
625 ;
626
b417577d 627 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 628
629 /* Do not initialize card-specific things if the power is off */
630 if (host->power_mode == MMC_POWER_OFF)
631 goto out;
632
633 con = OMAP_HSMMC_READ(host->base, CON);
634 switch (ios->bus_width) {
635 case MMC_BUS_WIDTH_8:
636 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
637 break;
638 case MMC_BUS_WIDTH_4:
639 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
640 OMAP_HSMMC_WRITE(host->base, HCTL,
641 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
642 break;
643 case MMC_BUS_WIDTH_1:
644 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
645 OMAP_HSMMC_WRITE(host->base, HCTL,
646 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
647 break;
648 }
649
650 if (ios->clock) {
651 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
652 if (dsor < 1)
653 dsor = 1;
654
655 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
656 dsor++;
657
658 if (dsor > 250)
659 dsor = 250;
660 }
661
662 OMAP_HSMMC_WRITE(host->base, SYSCTL,
663 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
664 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
665 OMAP_HSMMC_WRITE(host->base, SYSCTL,
666 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
667
668 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
669 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
670 && time_before(jiffies, timeout))
671 ;
672
673 OMAP_HSMMC_WRITE(host->base, SYSCTL,
674 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
675
676 con = OMAP_HSMMC_READ(host->base, CON);
677 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
678 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
679 else
680 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
681out:
682 host->context_loss = context_loss;
683
684 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
685 return 0;
686}
687
688/*
689 * Save the MMC host context (store the number of power state changes so far).
690 */
70a3341a 691static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 692{
693 struct omap_mmc_platform_data *pdata = host->pdata;
694 int context_loss;
695
696 if (pdata->get_context_loss_count) {
697 context_loss = pdata->get_context_loss_count(host->dev);
698 if (context_loss < 0)
699 return;
700 host->context_loss = context_loss;
701 }
702}
703
704#else
705
70a3341a 706static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 707{
708 return 0;
709}
710
70a3341a 711static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 712{
713}
714
715#endif
716
a45c6cb8
MC		 717/*
718 * Send init stream sequence to card
719 * before sending IDLE command
720 */
70a3341a 721static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 722{
723 int reg = 0;
724 unsigned long timeout;
725
b62f6228
AH		 726 if (host->protect_card)
727 return;
728
a45c6cb8 729 disable_irq(host->irq);
b417577d
AH		 730
731 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 732 OMAP_HSMMC_WRITE(host->base, CON,
733 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
734 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
735
736 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
737 while ((reg != CC) && time_before(jiffies, timeout))
738 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
739
740 OMAP_HSMMC_WRITE(host->base, CON,
741 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 742
743 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
744 OMAP_HSMMC_READ(host->base, STAT);
745
a45c6cb8
MC		 746 enable_irq(host->irq);
747}
748
749static inline
70a3341a 750int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 751{
752 int r = 1;
753
191d1f1d
DK		 754 if (mmc_slot(host).get_cover_state)
755 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 756 return r;
757}
758
759static ssize_t
70a3341a 760omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 761 char *buf)
762{
763 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 764 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 765
70a3341a
DK		 766 return sprintf(buf, "%s\n",
767 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 768}
769
70a3341a 770static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 771
772static ssize_t
70a3341a 773omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 774 char *buf)
775{
776 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 777 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 778
191d1f1d 779 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 780}
781
70a3341a 782static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 783
784/*
785 * Configure the response type and send the cmd.
786 */
787static void
70a3341a 788omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 789 struct mmc_data *data)
790{
791 int cmdreg = 0, resptype = 0, cmdtype = 0;
792
793 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
794 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
795 host->cmd = cmd;
796
93caf8e6 797 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 798
4a694dc9 799 host->response_busy = 0;
a45c6cb8
MC		 800 if (cmd->flags & MMC_RSP_PRESENT) {
801 if (cmd->flags & MMC_RSP_136)
802 resptype = 1;
4a694dc9
AH		 803 else if (cmd->flags & MMC_RSP_BUSY) {
804 resptype = 3;
805 host->response_busy = 1;
806 } else
a45c6cb8
MC		 807 resptype = 2;
808 }
809
810 /*
811 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
812 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
813 * a val of 0x3, rest 0x0.
814 */
815 if (cmd == host->mrq->stop)
816 cmdtype = 0x3;
817
818 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
819
820 if (data) {
821 cmdreg |= DP_SELECT | MSBS | BCE;
822 if (data->flags & MMC_DATA_READ)
823 cmdreg |= DDIR;
824 else
825 cmdreg &= ~(DDIR);
826 }
827
828 if (host->use_dma)
829 cmdreg |= DMA_EN;
830
b417577d 831 host->req_in_progress = 1;
4dffd7a2 832
a45c6cb8
MC		 833 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
834 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
835}
836
0ccd76d4 837static int
70a3341a 838omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 839{
840 if (data->flags & MMC_DATA_WRITE)
841 return DMA_TO_DEVICE;
842 else
843 return DMA_FROM_DEVICE;
844}
845
b417577d
AH		 846static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
847{
848 int dma_ch;
849
850 spin_lock(&host->irq_lock);
851 host->req_in_progress = 0;
852 dma_ch = host->dma_ch;
853 spin_unlock(&host->irq_lock);
854
855 omap_hsmmc_disable_irq(host);
856 /* Do not complete the request if DMA is still in progress */
857 if (mrq->data && host->use_dma && dma_ch != -1)
858 return;
859 host->mrq = NULL;
860 mmc_request_done(host->mmc, mrq);
861}
862
a45c6cb8
MC		 863/*
864 * Notify the transfer complete to MMC core
865 */
866static void
70a3341a 867omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 868{
4a694dc9
AH		 869 if (!data) {
870 struct mmc_request *mrq = host->mrq;
871
23050103
AH		 872 /* TC before CC from CMD6 - don't know why, but it happens */
873 if (host->cmd && host->cmd->opcode == 6 &&
874 host->response_busy) {
875 host->response_busy = 0;
876 return;
877 }
878
b417577d 879 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 880 return;
881 }
882
a45c6cb8
MC		 883 host->data = NULL;
884
a45c6cb8
MC		 885 if (!data->error)
886 data->bytes_xfered += data->blocks * (data->blksz);
887 else
888 data->bytes_xfered = 0;
889
890 if (!data->stop) {
b417577d 891 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 892 return;
893 }
70a3341a 894 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 895}
896
897/*
898 * Notify the core about command completion
899 */
900static void
70a3341a 901omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 902{
903 host->cmd = NULL;
904
905 if (cmd->flags & MMC_RSP_PRESENT) {
906 if (cmd->flags & MMC_RSP_136) {
907 /* response type 2 */
908 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
909 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
910 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
911 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
912 } else {
913 /* response types 1, 1b, 3, 4, 5, 6 */
914 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
915 }
916 }
b417577d
AH		 917 if ((host->data == NULL && !host->response_busy) || cmd->error)
918 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 919}
920
921/*
922 * DMA clean up for command errors
923 */
70a3341a 924static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 925{
b417577d
AH		 926 int dma_ch;
927
82788ff5 928 host->data->error = errno;
a45c6cb8 929
b417577d
AH		 930 spin_lock(&host->irq_lock);
931 dma_ch = host->dma_ch;
932 host->dma_ch = -1;
933 spin_unlock(&host->irq_lock);
934
935 if (host->use_dma && dma_ch != -1) {
a45c6cb8 936 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 937 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 938 omap_free_dma(dma_ch);
a45c6cb8
MC		 939 }
940 host->data = NULL;
a45c6cb8
MC		 941}
942
943/*
944 * Readable error output
945 */
946#ifdef CONFIG_MMC_DEBUG
70a3341a 947static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 948{
949 /* --- means reserved bit without definition at documentation */
70a3341a 950 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 951 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
952 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
953 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
954 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
955 };
956 char res[256];
957 char *buf = res;
958 int len, i;
959
960 len = sprintf(buf, "MMC IRQ 0x%x :", status);
961 buf += len;
962
70a3341a 963 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 964 if (status & (1 << i)) {
70a3341a 965 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 966 buf += len;
967 }
968
969 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
970}
971#endif /* CONFIG_MMC_DEBUG */
972
3ebf74b1
JP		 973/*
974 * MMC controller internal state machines reset
975 *
976 * Used to reset command or data internal state machines, using respectively
977 * SRC or SRD bit of SYSCTL register
978 * Can be called from interrupt context
979 */
70a3341a
DK		 980static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
981 unsigned long bit)
3ebf74b1
JP		 982{
983 unsigned long i = 0;
984 unsigned long limit = (loops_per_jiffy *
985 msecs_to_jiffies(MMC_TIMEOUT_MS));
986
987 OMAP_HSMMC_WRITE(host->base, SYSCTL,
988 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
989
990 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
991 (i++ < limit))
992 cpu_relax();
993
994 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
995 dev_err(mmc_dev(host->mmc),
996 "Timeout waiting on controller reset in %s\n",
997 __func__);
998}
a45c6cb8 999
b417577d 1000static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1001{
a45c6cb8 1002 struct mmc_data *data;
b417577d
AH		 1003 int end_cmd = 0, end_trans = 0;
1004
1005 if (!host->req_in_progress) {
1006 do {
1007 OMAP_HSMMC_WRITE(host->base, STAT, status);
1008 /* Flush posted write */
1009 status = OMAP_HSMMC_READ(host->base, STAT);
1010 } while (status & INT_EN_MASK);
1011 return;
a45c6cb8
MC		 1012 }
1013
1014 data = host->data;
a45c6cb8
MC		 1015 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1016
1017 if (status & ERR) {
1018#ifdef CONFIG_MMC_DEBUG
70a3341a 1019 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1020#endif
1021 if ((status & CMD_TIMEOUT) ||
1022 (status & CMD_CRC)) {
1023 if (host->cmd) {
1024 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1025 omap_hsmmc_reset_controller_fsm(host,
1026 SRC);
a45c6cb8
MC		 1027 host->cmd->error = -ETIMEDOUT;
1028 } else {
1029 host->cmd->error = -EILSEQ;
1030 }
1031 end_cmd = 1;
1032 }
4a694dc9
AH		 1033 if (host->data || host->response_busy) {
1034 if (host->data)
70a3341a
DK		 1035 omap_hsmmc_dma_cleanup(host,
1036 -ETIMEDOUT);
4a694dc9 1037 host->response_busy = 0;
70a3341a 1038 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1039 }
a45c6cb8
MC		 1040 }
1041 if ((status & DATA_TIMEOUT) ||
1042 (status & DATA_CRC)) {
4a694dc9
AH		 1043 if (host->data || host->response_busy) {
1044 int err = (status & DATA_TIMEOUT) ?
1045 -ETIMEDOUT : -EILSEQ;
1046
1047 if (host->data)
70a3341a 1048 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1049 else
4a694dc9
AH		 1050 host->mrq->cmd->error = err;
1051 host->response_busy = 0;
70a3341a 1052 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1053 end_trans = 1;
1054 }
1055 }
1056 if (status & CARD_ERR) {
1057 dev_dbg(mmc_dev(host->mmc),
1058 "Ignoring card err CMD%d\n", host->cmd->opcode);
1059 if (host->cmd)
1060 end_cmd = 1;
1061 if (host->data)
1062 end_trans = 1;
1063 }
1064 }
1065
1066 OMAP_HSMMC_WRITE(host->base, STAT, status);
1067
a8fe29d8 1068 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1069 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1070 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1071 omap_hsmmc_xfer_done(host, data);
b417577d 1072}
a45c6cb8 1073
b417577d
AH		 1074/*
1075 * MMC controller IRQ handler
1076 */
1077static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1078{
1079 struct omap_hsmmc_host *host = dev_id;
1080 int status;
1081
1082 status = OMAP_HSMMC_READ(host->base, STAT);
1083 do {
1084 omap_hsmmc_do_irq(host, status);
1085 /* Flush posted write */
1086 status = OMAP_HSMMC_READ(host->base, STAT);
1087 } while (status & INT_EN_MASK);
4dffd7a2 1088
a45c6cb8
MC		 1089 return IRQ_HANDLED;
1090}
1091
70a3341a 1092static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1093{
1094 unsigned long i;
1095
1096 OMAP_HSMMC_WRITE(host->base, HCTL,
1097 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1098 for (i = 0; i < loops_per_jiffy; i++) {
1099 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1100 break;
1101 cpu_relax();
1102 }
1103}
1104
a45c6cb8 1105/*
eb250826
DB		 1106 * Switch MMC interface voltage ... only relevant for MMC1.
1107 *
1108 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1109 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1110 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1111 */
70a3341a 1112static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1113{
1114 u32 reg_val = 0;
1115 int ret;
1116
1117 /* Disable the clocks */
1118 clk_disable(host->fclk);
1119 clk_disable(host->iclk);
2bec0893
AH		 1120 if (host->got_dbclk)
1121 clk_disable(host->dbclk);
a45c6cb8
MC		 1122
1123 /* Turn the power off */
1124 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1125
1126 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1127 if (!ret)
1128 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1129 vdd);
1130 clk_enable(host->iclk);
1131 clk_enable(host->fclk);
1132 if (host->got_dbclk)
1133 clk_enable(host->dbclk);
1134
a45c6cb8
MC		 1135 if (ret != 0)
1136 goto err;
1137
a45c6cb8
MC		 1138 OMAP_HSMMC_WRITE(host->base, HCTL,
1139 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1140 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1141
a45c6cb8
MC		 1142 /*
1143 * If a MMC dual voltage card is detected, the set_ios fn calls
1144 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1145 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1146 *
eb250826
DB		 1147 * Cope with a bit of slop in the range ... per data sheets:
1148 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1149 * but recommended values are 1.71V to 1.89V
1150 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1151 * but recommended values are 2.7V to 3.3V
1152 *
1153 * Board setup code shouldn't permit anything very out-of-range.
1154 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1155 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1156 */
eb250826 1157 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1158 reg_val |= SDVS18;
eb250826
DB		 1159 else
1160 reg_val |= SDVS30;
a45c6cb8
MC		 1161
1162 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1163 set_sd_bus_power(host);
a45c6cb8
MC		 1164
1165 return 0;
1166err:
1167 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1168 return ret;
1169}
1170
b62f6228
AH		 1171/* Protect the card while the cover is open */
1172static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1173{
1174 if (!mmc_slot(host).get_cover_state)
1175 return;
1176
1177 host->reqs_blocked = 0;
1178 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1179 if (host->protect_card) {
1180 printk(KERN_INFO "%s: cover is closed, "
1181 "card is now accessible\n",
1182 mmc_hostname(host->mmc));
1183 host->protect_card = 0;
1184 }
1185 } else {
1186 if (!host->protect_card) {
1187 printk(KERN_INFO "%s: cover is open, "
1188 "card is now inaccessible\n",
1189 mmc_hostname(host->mmc));
1190 host->protect_card = 1;
1191 }
1192 }
1193}
1194
a45c6cb8
MC		 1195/*
1196 * Work Item to notify the core about card insertion/removal
1197 */
70a3341a 1198static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1199{
70a3341a
DK		 1200 struct omap_hsmmc_host *host =
1201 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1202 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1203 int carddetect;
1204
1205 if (host->suspended)
1206 return;
1207
1208 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1209
191d1f1d 1210 if (slot->card_detect)
db0fefc5 1211 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1212 else {
1213 omap_hsmmc_protect_card(host);
a6b2240d 1214 carddetect = -ENOSYS;
b62f6228 1215 }
a45c6cb8 1216
cdeebadd 1217 if (carddetect)
a45c6cb8 1218 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1219 else
a45c6cb8 1220 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1221}
1222
1223/*
1224 * ISR for handling card insertion and removal
1225 */
70a3341a 1226static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1227{
70a3341a 1228 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1229
a6b2240d
AH		 1230 if (host->suspended)
1231 return IRQ_HANDLED;
a45c6cb8
MC		 1232 schedule_work(&host->mmc_carddetect_work);
1233
1234 return IRQ_HANDLED;
1235}
1236
70a3341a 1237static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1238 struct mmc_data *data)
1239{
1240 int sync_dev;
1241
f3e2f1dd
GI		 1242 if (data->flags & MMC_DATA_WRITE)
1243 sync_dev = host->dma_line_tx;
1244 else
1245 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1246 return sync_dev;
1247}
1248
70a3341a 1249static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1250 struct mmc_data *data,
1251 struct scatterlist *sgl)
1252{
1253 int blksz, nblk, dma_ch;
1254
1255 dma_ch = host->dma_ch;
1256 if (data->flags & MMC_DATA_WRITE) {
1257 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1258 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1259 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1260 sg_dma_address(sgl), 0, 0);
1261 } else {
1262 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1263 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1264 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1265 sg_dma_address(sgl), 0, 0);
1266 }
1267
1268 blksz = host->data->blksz;
1269 nblk = sg_dma_len(sgl) / blksz;
1270
1271 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1272 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1273 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1274 !(data->flags & MMC_DATA_WRITE));
1275
1276 omap_start_dma(dma_ch);
1277}
1278
a45c6cb8
MC		 1279/*
1280 * DMA call back function
1281 */
b417577d 1282static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1283{
b417577d
AH		 1284 struct omap_hsmmc_host *host = cb_data;
1285 struct mmc_data *data = host->mrq->data;
1286 int dma_ch, req_in_progress;
a45c6cb8 1287
f3584e5e
V		 1288 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1289 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1290 ch_status);
1291 return;
1292 }
a45c6cb8 1293
b417577d
AH		 1294 spin_lock(&host->irq_lock);
1295 if (host->dma_ch < 0) {
1296 spin_unlock(&host->irq_lock);
a45c6cb8 1297 return;
b417577d 1298 }
a45c6cb8 1299
0ccd76d4
JY		 1300 host->dma_sg_idx++;
1301 if (host->dma_sg_idx < host->dma_len) {
1302 /* Fire up the next transfer. */
b417577d
AH		 1303 omap_hsmmc_config_dma_params(host, data,
1304 data->sg + host->dma_sg_idx);
1305 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1306 return;
1307 }
1308
b417577d
AH		 1309 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1310 omap_hsmmc_get_dma_dir(host, data));
1311
1312 req_in_progress = host->req_in_progress;
1313 dma_ch = host->dma_ch;
a45c6cb8 1314 host->dma_ch = -1;
b417577d
AH		 1315 spin_unlock(&host->irq_lock);
1316
1317 omap_free_dma(dma_ch);
1318
1319 /* If DMA has finished after TC, complete the request */
1320 if (!req_in_progress) {
1321 struct mmc_request *mrq = host->mrq;
1322
1323 host->mrq = NULL;
1324 mmc_request_done(host->mmc, mrq);
1325 }
a45c6cb8
MC		 1326}
1327
a45c6cb8
MC		 1328/*
1329 * Routine to configure and start DMA for the MMC card
1330 */
70a3341a
DK		 1331static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1332 struct mmc_request *req)
a45c6cb8 1333{
b417577d 1334 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1335 struct mmc_data *data = req->data;
1336
0ccd76d4 1337 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1338 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1339 struct scatterlist *sgl;
1340
1341 sgl = data->sg + i;
1342 if (sgl->length % data->blksz)
1343 return -EINVAL;
1344 }
1345 if ((data->blksz % 4) != 0)
1346 /* REVISIT: The MMC buffer increments only when MSB is written.
1347 * Return error for blksz which is non multiple of four.
1348 */
1349 return -EINVAL;
1350
b417577d 1351 BUG_ON(host->dma_ch != -1);
a45c6cb8 1352
70a3341a
DK		 1353 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1354 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1355 if (ret != 0) {
0ccd76d4 1356 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1357 "%s: omap_request_dma() failed with %d\n",
1358 mmc_hostname(host->mmc), ret);
1359 return ret;
1360 }
1361
1362 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1363 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1364 host->dma_ch = dma_ch;
0ccd76d4 1365 host->dma_sg_idx = 0;
a45c6cb8 1366
70a3341a 1367 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1368
a45c6cb8
MC		 1369 return 0;
1370}
1371
70a3341a 1372static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1373 unsigned int timeout_ns,
1374 unsigned int timeout_clks)
a45c6cb8
MC		 1375{
1376 unsigned int timeout, cycle_ns;
1377 uint32_t reg, clkd, dto = 0;
1378
1379 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1380 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1381 if (clkd == 0)
1382 clkd = 1;
1383
1384 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1385 timeout = timeout_ns / cycle_ns;
1386 timeout += timeout_clks;
a45c6cb8
MC		 1387 if (timeout) {
1388 while ((timeout & 0x80000000) == 0) {
1389 dto += 1;
1390 timeout <<= 1;
1391 }
1392 dto = 31 - dto;
1393 timeout <<= 1;
1394 if (timeout && dto)
1395 dto += 1;
1396 if (dto >= 13)
1397 dto -= 13;
1398 else
1399 dto = 0;
1400 if (dto > 14)
1401 dto = 14;
1402 }
1403
1404 reg &= ~DTO_MASK;
1405 reg |= dto << DTO_SHIFT;
1406 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1407}
1408
1409/*
1410 * Configure block length for MMC/SD cards and initiate the transfer.
1411 */
1412static int
70a3341a 1413omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1414{
1415 int ret;
1416 host->data = req->data;
1417
1418 if (req->data == NULL) {
a45c6cb8 1419 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1420 /*
1421 * Set an arbitrary 100ms data timeout for commands with
1422 * busy signal.
1423 */
1424 if (req->cmd->flags & MMC_RSP_BUSY)
1425 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1426 return 0;
1427 }
1428
1429 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1430 | (req->data->blocks << 16));
e2bf08d6 1431 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1432
a45c6cb8 1433 if (host->use_dma) {
70a3341a 1434 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1435 if (ret != 0) {
1436 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1437 return ret;
1438 }
1439 }
1440 return 0;
1441}
1442
1443/*
1444 * Request function. for read/write operation
1445 */
70a3341a 1446static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1447{
70a3341a 1448 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1449 int err;
a45c6cb8 1450
b417577d
AH		 1451 BUG_ON(host->req_in_progress);
1452 BUG_ON(host->dma_ch != -1);
1453 if (host->protect_card) {
1454 if (host->reqs_blocked < 3) {
1455 /*
1456 * Ensure the controller is left in a consistent
1457 * state by resetting the command and data state
1458 * machines.
1459 */
1460 omap_hsmmc_reset_controller_fsm(host, SRD);
1461 omap_hsmmc_reset_controller_fsm(host, SRC);
1462 host->reqs_blocked += 1;
1463 }
1464 req->cmd->error = -EBADF;
1465 if (req->data)
1466 req->data->error = -EBADF;
1467 req->cmd->retries = 0;
1468 mmc_request_done(mmc, req);
1469 return;
1470 } else if (host->reqs_blocked)
1471 host->reqs_blocked = 0;
a45c6cb8
MC		 1472 WARN_ON(host->mrq != NULL);
1473 host->mrq = req;
70a3341a 1474 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1475 if (err) {
1476 req->cmd->error = err;
1477 if (req->data)
1478 req->data->error = err;
1479 host->mrq = NULL;
1480 mmc_request_done(mmc, req);
1481 return;
1482 }
1483
70a3341a 1484 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1485}
1486
a45c6cb8 1487/* Routine to configure clock values. Exposed API to core */
70a3341a 1488static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1489{
70a3341a 1490 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1491 u16 dsor = 0;
1492 unsigned long regval;
1493 unsigned long timeout;
73153010 1494 u32 con;
a3621465 1495 int do_send_init_stream = 0;
a45c6cb8 1496
5e2ea617
AH		 1497 mmc_host_enable(host->mmc);
1498
a3621465
AH		 1499 if (ios->power_mode != host->power_mode) {
1500 switch (ios->power_mode) {
1501 case MMC_POWER_OFF:
1502 mmc_slot(host).set_power(host->dev, host->slot_id,
1503 0, 0);
623821f7 1504 host->vdd = 0;
a3621465
AH		 1505 break;
1506 case MMC_POWER_UP:
1507 mmc_slot(host).set_power(host->dev, host->slot_id,
1508 1, ios->vdd);
623821f7 1509 host->vdd = ios->vdd;
a3621465
AH		 1510 break;
1511 case MMC_POWER_ON:
1512 do_send_init_stream = 1;
1513 break;
1514 }
1515 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1516 }
1517
dd498eff
DK		 1518 /* FIXME: set registers based only on changes to ios */
1519
73153010 1520 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1521 switch (mmc->ios.bus_width) {
73153010
JL		 1522 case MMC_BUS_WIDTH_8:
1523 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1524 break;
a45c6cb8 1525 case MMC_BUS_WIDTH_4:
73153010 1526 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1527 OMAP_HSMMC_WRITE(host->base, HCTL,
1528 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1529 break;
1530 case MMC_BUS_WIDTH_1:
73153010 1531 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1532 OMAP_HSMMC_WRITE(host->base, HCTL,
1533 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1534 break;
1535 }
1536
1537 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1538 /* Only MMC1 can interface at 3V without some flavor
1539 * of external transceiver; but they all handle 1.8V.
1540 */
a45c6cb8
MC		 1541 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1542 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1543 /*
1544 * The mmc_select_voltage fn of the core does
1545 * not seem to set the power_mode to
1546 * MMC_POWER_UP upon recalculating the voltage.
1547 * vdd 1.8v.
1548 */
70a3341a
DK		 1549 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1550 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1551 "Switch operation failed\n");
1552 }
1553 }
1554
1555 if (ios->clock) {
1556 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1557 if (dsor < 1)
1558 dsor = 1;
1559
1560 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1561 dsor++;
1562
1563 if (dsor > 250)
1564 dsor = 250;
1565 }
70a3341a 1566 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1567 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1568 regval = regval & ~(CLKD_MASK);
1569 regval = regval | (dsor << 6) | (DTO << 16);
1570 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1571 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1572 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1573
1574 /* Wait till the ICS bit is set */
1575 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1576 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1577 && time_before(jiffies, timeout))
1578 msleep(1);
1579
1580 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1581 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1582
a3621465 1583 if (do_send_init_stream)
a45c6cb8
MC		 1584 send_init_stream(host);
1585
abb28e73 1586 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1587 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1588 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1589 else
1590 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1591
dd498eff
DK		 1592 if (host->power_mode == MMC_POWER_OFF)
1593 mmc_host_disable(host->mmc);
1594 else
1595 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1596}
1597
1598static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1599{
70a3341a 1600 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1601
191d1f1d 1602 if (!mmc_slot(host).card_detect)
a45c6cb8 1603 return -ENOSYS;
db0fefc5 1604 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1605}
1606
1607static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1608{
70a3341a 1609 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1610
191d1f1d 1611 if (!mmc_slot(host).get_ro)
a45c6cb8 1612 return -ENOSYS;
191d1f1d 1613 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1614}
1615
4816858c
GI		 1616static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1617{
1618 struct omap_hsmmc_host *host = mmc_priv(mmc);
1619
1620 if (mmc_slot(host).init_card)
1621 mmc_slot(host).init_card(card);
1622}
1623
70a3341a 1624static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1625{
1626 u32 hctl, capa, value;
1627
1628 /* Only MMC1 supports 3.0V */
1629 if (host->id == OMAP_MMC1_DEVID) {
1630 hctl = SDVS30;
1631 capa = VS30 | VS18;
1632 } else {
1633 hctl = SDVS18;
1634 capa = VS18;
1635 }
1636
1637 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1638 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1639
1640 value = OMAP_HSMMC_READ(host->base, CAPA);
1641 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1642
1643 /* Set the controller to AUTO IDLE mode */
1644 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1645 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1646
1647 /* Set SD bus power bit */
e13bb300 1648 set_sd_bus_power(host);
1b331e69
KK		 1649}
1650
dd498eff
DK		 1651/*
1652 * Dynamic power saving handling, FSM:
13189e78
JL		 1653 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1654 * ^___________| | |
1655 * |______________________|______________________|
dd498eff
DK		 1656 *
1657 * ENABLED: mmc host is fully functional
1658 * DISABLED: fclk is off
13189e78
JL		 1659 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1660 * REGSLEEP: fclk is off, voltage regulator is asleep
1661 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1662 *
1663 * Transition handlers return the timeout for the next state transition
1664 * or negative error.
1665 */
1666
13189e78 1667enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1668
1669/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1670static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1671{
70a3341a 1672 omap_hsmmc_context_save(host);
dd498eff
DK		 1673 clk_disable(host->fclk);
1674 host->dpm_state = DISABLED;
1675
1676 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1677
1678 if (host->power_mode == MMC_POWER_OFF)
1679 return 0;
1680
4380eea2 1681 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1682}
1683
13189e78 1684/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1685static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1686{
13189e78 1687 int err, new_state;
dd498eff
DK		 1688
1689 if (!mmc_try_claim_host(host->mmc))
1690 return 0;
1691
1692 clk_enable(host->fclk);
70a3341a 1693 omap_hsmmc_context_restore(host);
13189e78
JL		 1694 if (mmc_card_can_sleep(host->mmc)) {
1695 err = mmc_card_sleep(host->mmc);
1696 if (err < 0) {
1697 clk_disable(host->fclk);
1698 mmc_release_host(host->mmc);
1699 return err;
1700 }
1701 new_state = CARDSLEEP;
70a3341a 1702 } else {
13189e78 1703 new_state = REGSLEEP;
70a3341a 1704 }
13189e78
JL		 1705 if (mmc_slot(host).set_sleep)
1706 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1707 new_state == CARDSLEEP);
1708 /* FIXME: turn off bus power and perhaps interrupts too */
1709 clk_disable(host->fclk);
1710 host->dpm_state = new_state;
1711
1712 mmc_release_host(host->mmc);
1713
1714 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1715 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1716
1df58db8
AH		 1717 if (mmc_slot(host).no_off)
1718 return 0;
1719
dd498eff
DK		 1720 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1721 mmc_slot(host).card_detect ||
1722 (mmc_slot(host).get_cover_state &&
13189e78 1723 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1724 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1725
1726 return 0;
1727}
1728
1729/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1730static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1731{
1732 if (!mmc_try_claim_host(host->mmc))
1733 return 0;
1734
1df58db8
AH		 1735 if (mmc_slot(host).no_off)
1736 return 0;
1737
13189e78
JL		 1738 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1739 mmc_slot(host).card_detect ||
1740 (mmc_slot(host).get_cover_state &&
1741 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1742 mmc_release_host(host->mmc);
1743 return 0;
623821f7 1744 }
dd498eff 1745
13189e78
JL		 1746 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1747 host->vdd = 0;
1748 host->power_mode = MMC_POWER_OFF;
dd498eff 1749
13189e78
JL		 1750 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1751 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1752
13189e78 1753 host->dpm_state = OFF;
dd498eff
DK		 1754
1755 mmc_release_host(host->mmc);
1756
1757 return 0;
1758}
1759
1760/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1761static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1762{
1763 int err;
1764
1765 err = clk_enable(host->fclk);
1766 if (err < 0)
1767 return err;
1768
70a3341a 1769 omap_hsmmc_context_restore(host);
dd498eff
DK		 1770 host->dpm_state = ENABLED;
1771
1772 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1773
1774 return 0;
1775}
1776
13189e78 1777/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1778static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1779{
13189e78
JL		 1780 if (!mmc_try_claim_host(host->mmc))
1781 return 0;
dd498eff 1782
13189e78 1783 clk_enable(host->fclk);
70a3341a 1784 omap_hsmmc_context_restore(host);
13189e78
JL		 1785 if (mmc_slot(host).set_sleep)
1786 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1787 host->vdd, host->dpm_state == CARDSLEEP);
1788 if (mmc_card_can_sleep(host->mmc))
1789 mmc_card_awake(host->mmc);
1790
1791 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1792 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1793
1794 host->dpm_state = ENABLED;
1795
13189e78 1796 mmc_release_host(host->mmc);
dd498eff
DK		 1797
1798 return 0;
1799}
1800
13189e78 1801/* Handler for [OFF -> ENABLED] transition */
70a3341a 1802static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1803{
623821f7 1804 clk_enable(host->fclk);
623821f7 1805
70a3341a
DK		 1806 omap_hsmmc_context_restore(host);
1807 omap_hsmmc_conf_bus_power(host);
13189e78 1808 mmc_power_restore_host(host->mmc);
623821f7
AH		 1809
1810 host->dpm_state = ENABLED;
1811
13189e78
JL		 1812 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1813
623821f7
AH		 1814 return 0;
1815}
1816
dd498eff
DK		 1817/*
1818 * Bring MMC host to ENABLED from any other PM state.
1819 */
70a3341a 1820static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1821{
70a3341a 1822 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1823
1824 switch (host->dpm_state) {
1825 case DISABLED:
70a3341a 1826 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1827 case CARDSLEEP:
623821f7 1828 case REGSLEEP:
70a3341a 1829 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1830 case OFF:
70a3341a 1831 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1832 default:
1833 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1834 return -EINVAL;
1835 }
1836}
1837
1838/*
1839 * Bring MMC host in PM state (one level deeper).
1840 */
70a3341a 1841static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1842{
70a3341a 1843 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1844
1845 switch (host->dpm_state) {
1846 case ENABLED: {
1847 int delay;
1848
70a3341a 1849 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1850 if (lazy || delay < 0)
1851 return delay;
1852 return 0;
1853 }
1854 case DISABLED:
70a3341a 1855 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1856 case CARDSLEEP:
1857 case REGSLEEP:
70a3341a 1858 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1859 default:
1860 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1861 return -EINVAL;
1862 }
1863}
1864
70a3341a 1865static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1866{
70a3341a 1867 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1868 int err;
1869
1870 err = clk_enable(host->fclk);
1871 if (err)
1872 return err;
1873 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1874 omap_hsmmc_context_restore(host);
dd498eff
DK		 1875 return 0;
1876}
1877
70a3341a 1878static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1879{
70a3341a 1880 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1881
70a3341a 1882 omap_hsmmc_context_save(host);
dd498eff
DK		 1883 clk_disable(host->fclk);
1884 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1885 return 0;
1886}
1887
70a3341a
DK		 1888static const struct mmc_host_ops omap_hsmmc_ops = {
1889 .enable = omap_hsmmc_enable_fclk,
1890 .disable = omap_hsmmc_disable_fclk,
1891 .request = omap_hsmmc_request,
1892 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1893 .get_cd = omap_hsmmc_get_cd,
1894 .get_ro = omap_hsmmc_get_ro,
4816858c 1895 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1896 /* NYET -- enable_sdio_irq */
1897};
1898
70a3341a
DK		 1899static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1900 .enable = omap_hsmmc_enable,
1901 .disable = omap_hsmmc_disable,
1902 .request = omap_hsmmc_request,
1903 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1904 .get_cd = omap_hsmmc_get_cd,
1905 .get_ro = omap_hsmmc_get_ro,
4816858c 1906 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1907 /* NYET -- enable_sdio_irq */
1908};
1909
d900f712
DK		 1910#ifdef CONFIG_DEBUG_FS
1911
70a3341a 1912static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1913{
1914 struct mmc_host *mmc = s->private;
70a3341a 1915 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1916 int context_loss = 0;
1917
70a3341a
DK		 1918 if (host->pdata->get_context_loss_count)
1919 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1920
5e2ea617
AH		 1921 seq_printf(s, "mmc%d:\n"
1922 " enabled:\t%d\n"
dd498eff 1923 " dpm_state:\t%d\n"
5e2ea617 1924 " nesting_cnt:\t%d\n"
11dd62a7 1925 " ctx_loss:\t%d:%d\n"
5e2ea617 1926 "\nregs:\n",
dd498eff
DK		 1927 mmc->index, mmc->enabled ? 1 : 0,
1928 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1929 host->context_loss, context_loss);
5e2ea617 1930
13189e78 1931 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1932 seq_printf(s, "host suspended, can't read registers\n");
1933 return 0;
1934 }
1935
5e2ea617
AH		 1936 if (clk_enable(host->fclk) != 0) {
1937 seq_printf(s, "can't read the regs\n");
dd498eff 1938 return 0;
5e2ea617 1939 }
d900f712
DK		 1940
1941 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1942 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1943 seq_printf(s, "CON:\t\t0x%08x\n",
1944 OMAP_HSMMC_READ(host->base, CON));
1945 seq_printf(s, "HCTL:\t\t0x%08x\n",
1946 OMAP_HSMMC_READ(host->base, HCTL));
1947 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1948 OMAP_HSMMC_READ(host->base, SYSCTL));
1949 seq_printf(s, "IE:\t\t0x%08x\n",
1950 OMAP_HSMMC_READ(host->base, IE));
1951 seq_printf(s, "ISE:\t\t0x%08x\n",
1952 OMAP_HSMMC_READ(host->base, ISE));
1953 seq_printf(s, "CAPA:\t\t0x%08x\n",
1954 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1955
1956 clk_disable(host->fclk);
dd498eff 1957
d900f712
DK		 1958 return 0;
1959}
1960
70a3341a 1961static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1962{
70a3341a 1963 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1964}
1965
1966static const struct file_operations mmc_regs_fops = {
70a3341a 1967 .open = omap_hsmmc_regs_open,
d900f712
DK		 1968 .read = seq_read,
1969 .llseek = seq_lseek,
1970 .release = single_release,
1971};
1972
70a3341a 1973static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1974{
1975 if (mmc->debugfs_root)
1976 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1977 mmc, &mmc_regs_fops);
1978}
1979
1980#else
1981
70a3341a 1982static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1983{
1984}
1985
1986#endif
1987
70a3341a 1988static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1989{
1990 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1991 struct mmc_host *mmc;
70a3341a 1992 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1993 struct resource *res;
db0fefc5 1994 int ret, irq;
a45c6cb8
MC		 1995
1996 if (pdata == NULL) {
1997 dev_err(&pdev->dev, "Platform Data is missing\n");
1998 return -ENXIO;
1999 }
2000
2001 if (pdata->nr_slots == 0) {
2002 dev_err(&pdev->dev, "No Slots\n");
2003 return -ENXIO;
2004 }
2005
2006 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2007 irq = platform_get_irq(pdev, 0);
2008 if (res == NULL || irq < 0)
2009 return -ENXIO;
2010
2011 res = request_mem_region(res->start, res->end - res->start + 1,
2012 pdev->name);
2013 if (res == NULL)
2014 return -EBUSY;
2015
db0fefc5
AH		 2016 ret = omap_hsmmc_gpio_init(pdata);
2017 if (ret)
2018 goto err;
2019
70a3341a 2020 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2021 if (!mmc) {
2022 ret = -ENOMEM;
db0fefc5 2023 goto err_alloc;
a45c6cb8
MC		 2024 }
2025
2026 host = mmc_priv(mmc);
2027 host->mmc = mmc;
2028 host->pdata = pdata;
2029 host->dev = &pdev->dev;
2030 host->use_dma = 1;
2031 host->dev->dma_mask = &pdata->dma_mask;
2032 host->dma_ch = -1;
2033 host->irq = irq;
2034 host->id = pdev->id;
2035 host->slot_id = 0;
2036 host->mapbase = res->start;
2037 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2038 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2039
2040 platform_set_drvdata(pdev, host);
70a3341a 2041 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2042
191d1f1d 2043 if (mmc_slot(host).power_saving)
70a3341a 2044 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2045 else
70a3341a 2046 mmc->ops = &omap_hsmmc_ops;
dd498eff 2047
e0eb2424
AH		 2048 /*
2049 * If regulator_disable can only put vcc_aux to sleep then there is
2050 * no off state.
2051 */
2052 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2053 mmc_slot(host).no_off = 1;
2054
a45c6cb8
MC		 2055 mmc->f_min = 400000;
2056 mmc->f_max = 52000000;
2057
4dffd7a2 2058 spin_lock_init(&host->irq_lock);
a45c6cb8 2059
6f7607cc 2060 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2061 if (IS_ERR(host->iclk)) {
2062 ret = PTR_ERR(host->iclk);
2063 host->iclk = NULL;
2064 goto err1;
2065 }
6f7607cc 2066 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2067 if (IS_ERR(host->fclk)) {
2068 ret = PTR_ERR(host->fclk);
2069 host->fclk = NULL;
2070 clk_put(host->iclk);
2071 goto err1;
2072 }
2073
70a3341a 2074 omap_hsmmc_context_save(host);
11dd62a7 2075
5e2ea617 2076 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2077 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2078 /* we start off in DISABLED state */
2079 host->dpm_state = DISABLED;
2080
5e2ea617 2081 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 2082 clk_put(host->iclk);
2083 clk_put(host->fclk);
2084 goto err1;
2085 }
2086
2087 if (clk_enable(host->iclk) != 0) {
5e2ea617 2088 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2089 clk_put(host->iclk);
2090 clk_put(host->fclk);
2091 goto err1;
2092 }
2093
2bec0893
AH		 2094 if (cpu_is_omap2430()) {
2095 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2096 /*
2097 * MMC can still work without debounce clock.
2098 */
2099 if (IS_ERR(host->dbclk))
2100 dev_warn(mmc_dev(host->mmc),
2101 "Failed to get debounce clock\n");
a45c6cb8 2102 else
2bec0893
AH		 2103 host->got_dbclk = 1;
2104
2105 if (host->got_dbclk)
2106 if (clk_enable(host->dbclk) != 0)
2107 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2108 " clk failed\n");
2109 }
a45c6cb8 2110
0ccd76d4
JY		 2111 /* Since we do only SG emulation, we can have as many segs
2112 * as we want. */
a36274e0 2113 mmc->max_segs = 1024;
0ccd76d4 2114
a45c6cb8
MC		 2115 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2116 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2117 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2118 mmc->max_seg_size = mmc->max_req_size;
2119
13189e78 2120 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2121 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2122
27151dc9
KK		 2123 switch (mmc_slot(host).wires) {
2124 case 8:
73153010 2125 mmc->caps |= MMC_CAP_8_BIT_DATA;
27151dc9
KK		 2126 /* Fall through */
2127 case 4:
a45c6cb8 2128 mmc->caps |= MMC_CAP_4_BIT_DATA;
27151dc9
KK		 2129 break;
2130 case 1:
2131 /* Nothing to crib here */
2132 case 0:
2133 /* Assuming nothing was given by board, Core use's 1-Bit */
2134 break;
2135 default:
2136 /* Completely unexpected.. Core goes with 1-Bit Width */
2137 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!"
2138 "using 1 instead\n", mmc_slot(host).wires);
2139 }
a45c6cb8 2140
191d1f1d 2141 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2142 mmc->caps |= MMC_CAP_NONREMOVABLE;
2143
70a3341a 2144 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2145
f3e2f1dd
GI		 2146 /* Select DMA lines */
2147 switch (host->id) {
2148 case OMAP_MMC1_DEVID:
2149 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2150 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2151 break;
2152 case OMAP_MMC2_DEVID:
2153 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2154 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2155 break;
2156 case OMAP_MMC3_DEVID:
2157 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2158 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2159 break;
82cf818d 2160 case OMAP_MMC4_DEVID:
2161 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2162 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2163 break;
2164 case OMAP_MMC5_DEVID:
2165 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2166 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2167 break;
f3e2f1dd
GI		 2168 default:
2169 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2170 goto err_irq;
2171 }
a45c6cb8
MC		 2172
2173 /* Request IRQ for MMC operations */
70a3341a 2174 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2175 mmc_hostname(mmc), host);
2176 if (ret) {
2177 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2178 goto err_irq;
2179 }
2180
2181 if (pdata->init != NULL) {
2182 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2183 dev_dbg(mmc_dev(host->mmc),
2184 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2185 goto err_irq_cd_init;
2186 }
2187 }
db0fefc5 2188
b702b106 2189 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2190 ret = omap_hsmmc_reg_get(host);
2191 if (ret)
2192 goto err_reg;
2193 host->use_reg = 1;
2194 }
2195
b583f26d 2196 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2197
2198 /* Request IRQ for card detect */
e1a55f5e 2199 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2200 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2201 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2202 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2203 | IRQF_DISABLED,
2204 mmc_hostname(mmc), host);
2205 if (ret) {
2206 dev_dbg(mmc_dev(host->mmc),
2207 "Unable to grab MMC CD IRQ\n");
2208 goto err_irq_cd;
2209 }
2210 }
2211
b417577d 2212 omap_hsmmc_disable_irq(host);
a45c6cb8 2213
5e2ea617
AH		 2214 mmc_host_lazy_disable(host->mmc);
2215
b62f6228
AH		 2216 omap_hsmmc_protect_card(host);
2217
a45c6cb8
MC		 2218 mmc_add_host(mmc);
2219
191d1f1d 2220 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2221 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2222 if (ret < 0)
2223 goto err_slot_name;
2224 }
191d1f1d 2225 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2226 ret = device_create_file(&mmc->class_dev,
2227 &dev_attr_cover_switch);
2228 if (ret < 0)
db0fefc5 2229 goto err_slot_name;
a45c6cb8
MC		 2230 }
2231
70a3341a 2232 omap_hsmmc_debugfs(mmc);
d900f712 2233
a45c6cb8
MC		 2234 return 0;
2235
a45c6cb8
MC		 2236err_slot_name:
2237 mmc_remove_host(mmc);
a45c6cb8 2238 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2239err_irq_cd:
2240 if (host->use_reg)
2241 omap_hsmmc_reg_put(host);
2242err_reg:
2243 if (host->pdata->cleanup)
2244 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2245err_irq_cd_init:
2246 free_irq(host->irq, host);
2247err_irq:
5e2ea617 2248 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2249 clk_disable(host->iclk);
2250 clk_put(host->fclk);
2251 clk_put(host->iclk);
2bec0893 2252 if (host->got_dbclk) {
a45c6cb8
MC		 2253 clk_disable(host->dbclk);
2254 clk_put(host->dbclk);
2255 }
a45c6cb8
MC		 2256err1:
2257 iounmap(host->base);
db0fefc5
AH		 2258 platform_set_drvdata(pdev, NULL);
2259 mmc_free_host(mmc);
2260err_alloc:
2261 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2262err:
a45c6cb8 2263 release_mem_region(res->start, res->end - res->start + 1);
a45c6cb8
MC		 2264 return ret;
2265}
2266
70a3341a 2267static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2268{
70a3341a 2269 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2270 struct resource *res;
2271
2272 if (host) {
5e2ea617 2273 mmc_host_enable(host->mmc);
a45c6cb8 2274 mmc_remove_host(host->mmc);
db0fefc5
AH		 2275 if (host->use_reg)
2276 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2277 if (host->pdata->cleanup)
2278 host->pdata->cleanup(&pdev->dev);
2279 free_irq(host->irq, host);
2280 if (mmc_slot(host).card_detect_irq)
2281 free_irq(mmc_slot(host).card_detect_irq, host);
2282 flush_scheduled_work();
2283
5e2ea617 2284 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2285 clk_disable(host->iclk);
2286 clk_put(host->fclk);
2287 clk_put(host->iclk);
2bec0893 2288 if (host->got_dbclk) {
a45c6cb8
MC		 2289 clk_disable(host->dbclk);
2290 clk_put(host->dbclk);
2291 }
2292
2293 mmc_free_host(host->mmc);
2294 iounmap(host->base);
db0fefc5 2295 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2296 }
2297
2298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2299 if (res)
2300 release_mem_region(res->start, res->end - res->start + 1);
2301 platform_set_drvdata(pdev, NULL);
2302
2303 return 0;
2304}
2305
2306#ifdef CONFIG_PM
a791daa1 2307static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2308{
2309 int ret = 0;
a791daa1 2310 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2311 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2312
2313 if (host && host->suspended)
2314 return 0;
2315
2316 if (host) {
a6b2240d
AH		 2317 host->suspended = 1;
2318 if (host->pdata->suspend) {
2319 ret = host->pdata->suspend(&pdev->dev,
2320 host->slot_id);
2321 if (ret) {
2322 dev_dbg(mmc_dev(host->mmc),
2323 "Unable to handle MMC board"
2324 " level suspend\n");
2325 host->suspended = 0;
2326 return ret;
2327 }
2328 }
2329 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2330 ret = mmc_suspend_host(host->mmc);
e7cb756f 2331 mmc_host_enable(host->mmc);
a45c6cb8 2332 if (ret == 0) {
b417577d 2333 omap_hsmmc_disable_irq(host);
0683af48 2334 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2335 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2336 mmc_host_disable(host->mmc);
a45c6cb8 2337 clk_disable(host->iclk);
2bec0893
AH		 2338 if (host->got_dbclk)
2339 clk_disable(host->dbclk);
a6b2240d
AH		 2340 } else {
2341 host->suspended = 0;
2342 if (host->pdata->resume) {
2343 ret = host->pdata->resume(&pdev->dev,
2344 host->slot_id);
2345 if (ret)
2346 dev_dbg(mmc_dev(host->mmc),
2347 "Unmask interrupt failed\n");
2348 }
5e2ea617 2349 mmc_host_disable(host->mmc);
a6b2240d 2350 }
a45c6cb8
MC		 2351
2352 }
2353 return ret;
2354}
2355
2356/* Routine to resume the MMC device */
a791daa1 2357static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2358{
2359 int ret = 0;
a791daa1 2360 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2361 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2362
2363 if (host && !host->suspended)
2364 return 0;
2365
2366 if (host) {
a45c6cb8 2367 ret = clk_enable(host->iclk);
11dd62a7 2368 if (ret)
a45c6cb8 2369 goto clk_en_err;
a45c6cb8 2370
11dd62a7
DK		 2371 if (mmc_host_enable(host->mmc) != 0) {
2372 clk_disable(host->iclk);
2373 goto clk_en_err;
2374 }
2375
2bec0893
AH		 2376 if (host->got_dbclk)
2377 clk_enable(host->dbclk);
2378
70a3341a 2379 omap_hsmmc_conf_bus_power(host);
1b331e69 2380
a45c6cb8
MC		 2381 if (host->pdata->resume) {
2382 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2383 if (ret)
2384 dev_dbg(mmc_dev(host->mmc),
2385 "Unmask interrupt failed\n");
2386 }
2387
b62f6228
AH		 2388 omap_hsmmc_protect_card(host);
2389
a45c6cb8
MC		 2390 /* Notify the core to resume the host */
2391 ret = mmc_resume_host(host->mmc);
2392 if (ret == 0)
2393 host->suspended = 0;
70a3341a 2394
5e2ea617 2395 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2396 }
2397
2398 return ret;
2399
2400clk_en_err:
2401 dev_dbg(mmc_dev(host->mmc),
2402 "Failed to enable MMC clocks during resume\n");
2403 return ret;
2404}
2405
2406#else
70a3341a
DK		 2407#define omap_hsmmc_suspend NULL
2408#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2409#endif
2410
a791daa1 2411static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2412 .suspend = omap_hsmmc_suspend,
2413 .resume = omap_hsmmc_resume,
a791daa1
KH		 2414};
2415
2416static struct platform_driver omap_hsmmc_driver = {
2417 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2418 .driver = {
2419 .name = DRIVER_NAME,
2420 .owner = THIS_MODULE,
a791daa1 2421 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2422 },
2423};
2424
70a3341a 2425static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2426{
2427 /* Register the MMC driver */
8753298a 2428 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2429}
2430
70a3341a 2431static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2432{
2433 /* Unregister MMC driver */
70a3341a 2434 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2435}
2436
70a3341a
DK		 2437module_init(omap_hsmmc_init);
2438module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2439
2440MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2441MODULE_LICENSE("GPL");
2442MODULE_ALIAS("platform:" DRIVER_NAME);
2443MODULE_AUTHOR("Texas Instruments Inc");
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