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drivers/mmc/host/msm-sdcc: remove dead config options
[net-next-2.6.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
a45c6cb8
MC		 31#include <linux/io.h>
32#include <linux/semaphore.h>
db0fefc5
AH		 33#include <linux/gpio.h>
34#include <linux/regulator/consumer.h>
ce491cf8 35#include <plat/dma.h>
a45c6cb8 36#include <mach/hardware.h>
ce491cf8
TL		 37#include <plat/board.h>
38#include <plat/mmc.h>
39#include <plat/cpu.h>
a45c6cb8
MC		 40
41/* OMAP HSMMC Host Controller Registers */
42#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 43#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 44#define OMAP_HSMMC_CON 0x002C
45#define OMAP_HSMMC_BLK 0x0104
46#define OMAP_HSMMC_ARG 0x0108
47#define OMAP_HSMMC_CMD 0x010C
48#define OMAP_HSMMC_RSP10 0x0110
49#define OMAP_HSMMC_RSP32 0x0114
50#define OMAP_HSMMC_RSP54 0x0118
51#define OMAP_HSMMC_RSP76 0x011C
52#define OMAP_HSMMC_DATA 0x0120
53#define OMAP_HSMMC_HCTL 0x0128
54#define OMAP_HSMMC_SYSCTL 0x012C
55#define OMAP_HSMMC_STAT 0x0130
56#define OMAP_HSMMC_IE 0x0134
57#define OMAP_HSMMC_ISE 0x0138
58#define OMAP_HSMMC_CAPA 0x0140
59
60#define VS18 (1 << 26)
61#define VS30 (1 << 25)
62#define SDVS18 (0x5 << 9)
63#define SDVS30 (0x6 << 9)
eb250826 64#define SDVS33 (0x7 << 9)
1b331e69 65#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 66#define SDVSCLR 0xFFFFF1FF
67#define SDVSDET 0x00000400
68#define AUTOIDLE 0x1
69#define SDBP (1 << 8)
70#define DTO 0xe
71#define ICE 0x1
72#define ICS 0x2
73#define CEN (1 << 2)
74#define CLKD_MASK 0x0000FFC0
75#define CLKD_SHIFT 6
76#define DTO_MASK 0x000F0000
77#define DTO_SHIFT 16
78#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 79#define BWR_ENABLE (1 << 4)
80#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 81#define INIT_STREAM (1 << 1)
82#define DP_SELECT (1 << 21)
83#define DDIR (1 << 4)
84#define DMA_EN 0x1
85#define MSBS (1 << 5)
86#define BCE (1 << 1)
87#define FOUR_BIT (1 << 1)
73153010 88#define DW8 (1 << 5)
a45c6cb8
MC		 89#define CC 0x1
90#define TC 0x02
91#define OD 0x1
92#define ERR (1 << 15)
93#define CMD_TIMEOUT (1 << 16)
94#define DATA_TIMEOUT (1 << 20)
95#define CMD_CRC (1 << 17)
96#define DATA_CRC (1 << 21)
97#define CARD_ERR (1 << 28)
98#define STAT_CLEAR 0xFFFFFFFF
99#define INIT_STREAM_CMD 0x00000000
100#define DUAL_VOLT_OCR_BIT 7
101#define SRC (1 << 25)
102#define SRD (1 << 26)
11dd62a7
DK		 103#define SOFTRESET (1 << 1)
104#define RESETDONE (1 << 0)
a45c6cb8
MC		 105
106/*
107 * FIXME: Most likely all the data using these _DEVID defines should come
108 * from the platform_data, or implemented in controller and slot specific
109 * functions.
110 */
111#define OMAP_MMC1_DEVID 0
112#define OMAP_MMC2_DEVID 1
f3e2f1dd 113#define OMAP_MMC3_DEVID 2
82cf818d 114#define OMAP_MMC4_DEVID 3
115#define OMAP_MMC5_DEVID 4
a45c6cb8 116
a45c6cb8
MC		 117#define MMC_TIMEOUT_MS 20
118#define OMAP_MMC_MASTER_CLOCK 96000000
119#define DRIVER_NAME "mmci-omap-hs"
120
dd498eff
DK		 121/* Timeouts for entering power saving states on inactivity, msec */
122#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 123#define OMAP_MMC_SLEEP_TIMEOUT 1000
124#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 125
a45c6cb8
MC		 126/*
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
130 */
131#define mmc_slot(host) (host->pdata->slots[host->slot_id])
132
133/*
134 * MMC Host controller read/write API's
135 */
136#define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
138
139#define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
141
70a3341a 142struct omap_hsmmc_host {
a45c6cb8
MC		 143 struct device *dev;
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
148 struct clk *fclk;
149 struct clk *iclk;
150 struct clk *dbclk;
db0fefc5
AH		 151 /*
152 * vcc == configured supply
153 * vcc_aux == optional
154 * - MMC1, supply for DAT4..DAT7
155 * - MMC2/MMC2, external level shifter voltage supply, for
156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
157 */
158 struct regulator *vcc;
159 struct regulator *vcc_aux;
a45c6cb8
MC		 160 struct work_struct mmc_carddetect_work;
161 void __iomem *base;
162 resource_size_t mapbase;
4dffd7a2 163 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 164 unsigned int id;
165 unsigned int dma_len;
0ccd76d4 166 unsigned int dma_sg_idx;
a45c6cb8 167 unsigned char bus_mode;
a3621465 168 unsigned char power_mode;
a45c6cb8
MC		 169 u32 *buffer;
170 u32 bytesleft;
171 int suspended;
172 int irq;
a45c6cb8 173 int use_dma, dma_ch;
f3e2f1dd 174 int dma_line_tx, dma_line_rx;
a45c6cb8 175 int slot_id;
2bec0893 176 int got_dbclk;
4a694dc9 177 int response_busy;
11dd62a7 178 int context_loss;
dd498eff 179 int dpm_state;
623821f7 180 int vdd;
b62f6228
AH		 181 int protect_card;
182 int reqs_blocked;
db0fefc5 183 int use_reg;
b417577d 184 int req_in_progress;
11dd62a7 185
a45c6cb8
MC		 186 struct omap_mmc_platform_data *pdata;
187};
188
db0fefc5
AH		 189static int omap_hsmmc_card_detect(struct device *dev, int slot)
190{
191 struct omap_mmc_platform_data *mmc = dev->platform_data;
192
193 /* NOTE: assumes card detect signal is active-low */
194 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
195}
196
197static int omap_hsmmc_get_wp(struct device *dev, int slot)
198{
199 struct omap_mmc_platform_data *mmc = dev->platform_data;
200
201 /* NOTE: assumes write protect signal is active-high */
202 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
203}
204
205static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
206{
207 struct omap_mmc_platform_data *mmc = dev->platform_data;
208
209 /* NOTE: assumes card detect signal is active-low */
210 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
211}
212
213#ifdef CONFIG_PM
214
215static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
216{
217 struct omap_mmc_platform_data *mmc = dev->platform_data;
218
219 disable_irq(mmc->slots[0].card_detect_irq);
220 return 0;
221}
222
223static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
224{
225 struct omap_mmc_platform_data *mmc = dev->platform_data;
226
227 enable_irq(mmc->slots[0].card_detect_irq);
228 return 0;
229}
230
231#else
232
233#define omap_hsmmc_suspend_cdirq NULL
234#define omap_hsmmc_resume_cdirq NULL
235
236#endif
237
b702b106
AH		 238#ifdef CONFIG_REGULATOR
239
db0fefc5
AH		 240static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
241 int vdd)
242{
243 struct omap_hsmmc_host *host =
244 platform_get_drvdata(to_platform_device(dev));
245 int ret;
246
247 if (mmc_slot(host).before_set_reg)
248 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
249
250 if (power_on)
251 ret = mmc_regulator_set_ocr(host->vcc, vdd);
252 else
253 ret = mmc_regulator_set_ocr(host->vcc, 0);
254
255 if (mmc_slot(host).after_set_reg)
256 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
257
258 return ret;
259}
260
261static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
262 int vdd)
263{
264 struct omap_hsmmc_host *host =
265 platform_get_drvdata(to_platform_device(dev));
266 int ret = 0;
267
268 /*
269 * If we don't see a Vcc regulator, assume it's a fixed
270 * voltage always-on regulator.
271 */
272 if (!host->vcc)
273 return 0;
274
275 if (mmc_slot(host).before_set_reg)
276 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
277
278 /*
279 * Assume Vcc regulator is used only to power the card ... OMAP
280 * VDDS is used to power the pins, optionally with a transceiver to
281 * support cards using voltages other than VDDS (1.8V nominal). When a
282 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
283 *
284 * In some cases this regulator won't support enable/disable;
285 * e.g. it's a fixed rail for a WLAN chip.
286 *
287 * In other cases vcc_aux switches interface power. Example, for
288 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
289 * chips/cards need an interface voltage rail too.
290 */
291 if (power_on) {
292 ret = mmc_regulator_set_ocr(host->vcc, vdd);
293 /* Enable interface voltage rail, if needed */
294 if (ret == 0 && host->vcc_aux) {
295 ret = regulator_enable(host->vcc_aux);
296 if (ret < 0)
297 ret = mmc_regulator_set_ocr(host->vcc, 0);
298 }
299 } else {
6da20c89
AH		 300 if (host->vcc_aux)
301 ret = regulator_disable(host->vcc_aux);
db0fefc5
AH		 302 if (ret == 0)
303 ret = mmc_regulator_set_ocr(host->vcc, 0);
304 }
305
306 if (mmc_slot(host).after_set_reg)
307 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
308
309 return ret;
310}
311
312static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
313 int vdd, int cardsleep)
314{
315 struct omap_hsmmc_host *host =
316 platform_get_drvdata(to_platform_device(dev));
317 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
318
319 return regulator_set_mode(host->vcc, mode);
320}
321
322static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
323 int vdd, int cardsleep)
324{
325 struct omap_hsmmc_host *host =
326 platform_get_drvdata(to_platform_device(dev));
327 int err, mode;
328
329 /*
330 * If we don't see a Vcc regulator, assume it's a fixed
331 * voltage always-on regulator.
332 */
333 if (!host->vcc)
334 return 0;
335
336 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
337
338 if (!host->vcc_aux)
339 return regulator_set_mode(host->vcc, mode);
340
341 if (cardsleep) {
342 /* VCC can be turned off if card is asleep */
343 if (sleep)
344 err = mmc_regulator_set_ocr(host->vcc, 0);
345 else
346 err = mmc_regulator_set_ocr(host->vcc, vdd);
347 } else
348 err = regulator_set_mode(host->vcc, mode);
349 if (err)
350 return err;
e0eb2424
AH		 351
352 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
353 return regulator_set_mode(host->vcc_aux, mode);
354
355 if (sleep)
356 return regulator_disable(host->vcc_aux);
357 else
358 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 359}
360
db0fefc5
AH		 361static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
362{
363 struct regulator *reg;
364 int ret = 0;
365
366 switch (host->id) {
367 case OMAP_MMC1_DEVID:
368 /* On-chip level shifting via PBIAS0/PBIAS1 */
369 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
370 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
371 break;
372 case OMAP_MMC2_DEVID:
373 case OMAP_MMC3_DEVID:
374 /* Off-chip level shifting, or none */
375 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
376 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
377 break;
378 default:
379 pr_err("MMC%d configuration not supported!\n", host->id);
380 return -EINVAL;
381 }
382
383 reg = regulator_get(host->dev, "vmmc");
384 if (IS_ERR(reg)) {
385 dev_dbg(host->dev, "vmmc regulator missing\n");
386 /*
387 * HACK: until fixed.c regulator is usable,
388 * we don't require a main regulator
389 * for MMC2 or MMC3
390 */
391 if (host->id == OMAP_MMC1_DEVID) {
392 ret = PTR_ERR(reg);
393 goto err;
394 }
395 } else {
396 host->vcc = reg;
397 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
398
399 /* Allow an aux regulator */
400 reg = regulator_get(host->dev, "vmmc_aux");
401 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
402
403 /*
404 * UGLY HACK: workaround regulator framework bugs.
405 * When the bootloader leaves a supply active, it's
406 * initialized with zero usecount ... and we can't
407 * disable it without first enabling it. Until the
408 * framework is fixed, we need a workaround like this
409 * (which is safe for MMC, but not in general).
410 */
411 if (regulator_is_enabled(host->vcc) > 0) {
412 regulator_enable(host->vcc);
413 regulator_disable(host->vcc);
414 }
415 if (host->vcc_aux) {
416 if (regulator_is_enabled(reg) > 0) {
417 regulator_enable(reg);
418 regulator_disable(reg);
419 }
420 }
421 }
422
423 return 0;
424
425err:
426 mmc_slot(host).set_power = NULL;
427 mmc_slot(host).set_sleep = NULL;
428 return ret;
429}
430
431static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
432{
433 regulator_put(host->vcc);
434 regulator_put(host->vcc_aux);
435 mmc_slot(host).set_power = NULL;
436 mmc_slot(host).set_sleep = NULL;
437}
438
b702b106
AH		 439static inline int omap_hsmmc_have_reg(void)
440{
441 return 1;
442}
443
444#else
445
446static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
447{
448 return -EINVAL;
449}
450
451static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
452{
453}
454
455static inline int omap_hsmmc_have_reg(void)
456{
457 return 0;
458}
459
460#endif
461
462static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
463{
464 int ret;
465
466 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
467 pdata->suspend = omap_hsmmc_suspend_cdirq;
468 pdata->resume = omap_hsmmc_resume_cdirq;
469 if (pdata->slots[0].cover)
470 pdata->slots[0].get_cover_state =
471 omap_hsmmc_get_cover_state;
472 else
473 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
474 pdata->slots[0].card_detect_irq =
475 gpio_to_irq(pdata->slots[0].switch_pin);
476 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
477 if (ret)
478 return ret;
479 ret = gpio_direction_input(pdata->slots[0].switch_pin);
480 if (ret)
481 goto err_free_sp;
482 } else
483 pdata->slots[0].switch_pin = -EINVAL;
484
485 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
486 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
487 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
488 if (ret)
489 goto err_free_cd;
490 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
491 if (ret)
492 goto err_free_wp;
493 } else
494 pdata->slots[0].gpio_wp = -EINVAL;
495
496 return 0;
497
498err_free_wp:
499 gpio_free(pdata->slots[0].gpio_wp);
500err_free_cd:
501 if (gpio_is_valid(pdata->slots[0].switch_pin))
502err_free_sp:
503 gpio_free(pdata->slots[0].switch_pin);
504 return ret;
505}
506
507static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
508{
509 if (gpio_is_valid(pdata->slots[0].gpio_wp))
510 gpio_free(pdata->slots[0].gpio_wp);
511 if (gpio_is_valid(pdata->slots[0].switch_pin))
512 gpio_free(pdata->slots[0].switch_pin);
513}
514
a45c6cb8
MC		 515/*
516 * Stop clock to the card
517 */
70a3341a 518static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 519{
520 OMAP_HSMMC_WRITE(host->base, SYSCTL,
521 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
522 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
523 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
524}
525
b417577d
AH		 526static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host)
527{
528 unsigned int irq_mask;
529
530 if (host->use_dma)
531 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
532 else
533 irq_mask = INT_EN_MASK;
534
535 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
536 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
537 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
538}
539
540static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
541{
542 OMAP_HSMMC_WRITE(host->base, ISE, 0);
543 OMAP_HSMMC_WRITE(host->base, IE, 0);
544 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
545}
546
11dd62a7
DK		 547#ifdef CONFIG_PM
548
549/*
550 * Restore the MMC host context, if it was lost as result of a
551 * power state change.
552 */
70a3341a 553static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 554{
555 struct mmc_ios *ios = &host->mmc->ios;
556 struct omap_mmc_platform_data *pdata = host->pdata;
557 int context_loss = 0;
558 u32 hctl, capa, con;
559 u16 dsor = 0;
560 unsigned long timeout;
561
562 if (pdata->get_context_loss_count) {
563 context_loss = pdata->get_context_loss_count(host->dev);
564 if (context_loss < 0)
565 return 1;
566 }
567
568 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
569 context_loss == host->context_loss ? "not " : "");
570 if (host->context_loss == context_loss)
571 return 1;
572
573 /* Wait for hardware reset */
574 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
575 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
576 && time_before(jiffies, timeout))
577 ;
578
579 /* Do software reset */
580 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
583 && time_before(jiffies, timeout))
584 ;
585
586 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
587 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
588
589 if (host->id == OMAP_MMC1_DEVID) {
590 if (host->power_mode != MMC_POWER_OFF &&
591 (1 << ios->vdd) <= MMC_VDD_23_24)
592 hctl = SDVS18;
593 else
594 hctl = SDVS30;
595 capa = VS30 | VS18;
596 } else {
597 hctl = SDVS18;
598 capa = VS18;
599 }
600
601 OMAP_HSMMC_WRITE(host->base, HCTL,
602 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
603
604 OMAP_HSMMC_WRITE(host->base, CAPA,
605 OMAP_HSMMC_READ(host->base, CAPA) | capa);
606
607 OMAP_HSMMC_WRITE(host->base, HCTL,
608 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
609
610 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
611 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
612 && time_before(jiffies, timeout))
613 ;
614
b417577d 615 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 616
617 /* Do not initialize card-specific things if the power is off */
618 if (host->power_mode == MMC_POWER_OFF)
619 goto out;
620
621 con = OMAP_HSMMC_READ(host->base, CON);
622 switch (ios->bus_width) {
623 case MMC_BUS_WIDTH_8:
624 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
625 break;
626 case MMC_BUS_WIDTH_4:
627 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
628 OMAP_HSMMC_WRITE(host->base, HCTL,
629 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
630 break;
631 case MMC_BUS_WIDTH_1:
632 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
633 OMAP_HSMMC_WRITE(host->base, HCTL,
634 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
635 break;
636 }
637
638 if (ios->clock) {
639 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
640 if (dsor < 1)
641 dsor = 1;
642
643 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
644 dsor++;
645
646 if (dsor > 250)
647 dsor = 250;
648 }
649
650 OMAP_HSMMC_WRITE(host->base, SYSCTL,
651 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
652 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
653 OMAP_HSMMC_WRITE(host->base, SYSCTL,
654 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
655
656 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
657 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
658 && time_before(jiffies, timeout))
659 ;
660
661 OMAP_HSMMC_WRITE(host->base, SYSCTL,
662 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
663
664 con = OMAP_HSMMC_READ(host->base, CON);
665 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
666 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
667 else
668 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
669out:
670 host->context_loss = context_loss;
671
672 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
673 return 0;
674}
675
676/*
677 * Save the MMC host context (store the number of power state changes so far).
678 */
70a3341a 679static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 680{
681 struct omap_mmc_platform_data *pdata = host->pdata;
682 int context_loss;
683
684 if (pdata->get_context_loss_count) {
685 context_loss = pdata->get_context_loss_count(host->dev);
686 if (context_loss < 0)
687 return;
688 host->context_loss = context_loss;
689 }
690}
691
692#else
693
70a3341a 694static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 695{
696 return 0;
697}
698
70a3341a 699static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 700{
701}
702
703#endif
704
a45c6cb8
MC		 705/*
706 * Send init stream sequence to card
707 * before sending IDLE command
708 */
70a3341a 709static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 710{
711 int reg = 0;
712 unsigned long timeout;
713
b62f6228
AH		 714 if (host->protect_card)
715 return;
716
a45c6cb8 717 disable_irq(host->irq);
b417577d
AH		 718
719 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 720 OMAP_HSMMC_WRITE(host->base, CON,
721 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
722 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
723
724 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
725 while ((reg != CC) && time_before(jiffies, timeout))
726 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
727
728 OMAP_HSMMC_WRITE(host->base, CON,
729 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 730
731 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
732 OMAP_HSMMC_READ(host->base, STAT);
733
a45c6cb8
MC		 734 enable_irq(host->irq);
735}
736
737static inline
70a3341a 738int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 739{
740 int r = 1;
741
191d1f1d
DK		 742 if (mmc_slot(host).get_cover_state)
743 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 744 return r;
745}
746
747static ssize_t
70a3341a 748omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 749 char *buf)
750{
751 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 752 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 753
70a3341a
DK		 754 return sprintf(buf, "%s\n",
755 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 756}
757
70a3341a 758static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 759
760static ssize_t
70a3341a 761omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 762 char *buf)
763{
764 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 765 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 766
191d1f1d 767 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 768}
769
70a3341a 770static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 771
772/*
773 * Configure the response type and send the cmd.
774 */
775static void
70a3341a 776omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 777 struct mmc_data *data)
778{
779 int cmdreg = 0, resptype = 0, cmdtype = 0;
780
781 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
782 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
783 host->cmd = cmd;
784
b417577d 785 omap_hsmmc_enable_irq(host);
a45c6cb8 786
4a694dc9 787 host->response_busy = 0;
a45c6cb8
MC		 788 if (cmd->flags & MMC_RSP_PRESENT) {
789 if (cmd->flags & MMC_RSP_136)
790 resptype = 1;
4a694dc9
AH		 791 else if (cmd->flags & MMC_RSP_BUSY) {
792 resptype = 3;
793 host->response_busy = 1;
794 } else
a45c6cb8
MC		 795 resptype = 2;
796 }
797
798 /*
799 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
800 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
801 * a val of 0x3, rest 0x0.
802 */
803 if (cmd == host->mrq->stop)
804 cmdtype = 0x3;
805
806 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
807
808 if (data) {
809 cmdreg |= DP_SELECT | MSBS | BCE;
810 if (data->flags & MMC_DATA_READ)
811 cmdreg |= DDIR;
812 else
813 cmdreg &= ~(DDIR);
814 }
815
816 if (host->use_dma)
817 cmdreg |= DMA_EN;
818
b417577d 819 host->req_in_progress = 1;
4dffd7a2 820
a45c6cb8
MC		 821 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
822 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
823}
824
0ccd76d4 825static int
70a3341a 826omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 827{
828 if (data->flags & MMC_DATA_WRITE)
829 return DMA_TO_DEVICE;
830 else
831 return DMA_FROM_DEVICE;
832}
833
b417577d
AH		 834static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
835{
836 int dma_ch;
837
838 spin_lock(&host->irq_lock);
839 host->req_in_progress = 0;
840 dma_ch = host->dma_ch;
841 spin_unlock(&host->irq_lock);
842
843 omap_hsmmc_disable_irq(host);
844 /* Do not complete the request if DMA is still in progress */
845 if (mrq->data && host->use_dma && dma_ch != -1)
846 return;
847 host->mrq = NULL;
848 mmc_request_done(host->mmc, mrq);
849}
850
a45c6cb8
MC		 851/*
852 * Notify the transfer complete to MMC core
853 */
854static void
70a3341a 855omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 856{
4a694dc9
AH		 857 if (!data) {
858 struct mmc_request *mrq = host->mrq;
859
23050103
AH		 860 /* TC before CC from CMD6 - don't know why, but it happens */
861 if (host->cmd && host->cmd->opcode == 6 &&
862 host->response_busy) {
863 host->response_busy = 0;
864 return;
865 }
866
b417577d 867 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 868 return;
869 }
870
a45c6cb8
MC		 871 host->data = NULL;
872
a45c6cb8
MC		 873 if (!data->error)
874 data->bytes_xfered += data->blocks * (data->blksz);
875 else
876 data->bytes_xfered = 0;
877
878 if (!data->stop) {
b417577d 879 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 880 return;
881 }
70a3341a 882 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 883}
884
885/*
886 * Notify the core about command completion
887 */
888static void
70a3341a 889omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 890{
891 host->cmd = NULL;
892
893 if (cmd->flags & MMC_RSP_PRESENT) {
894 if (cmd->flags & MMC_RSP_136) {
895 /* response type 2 */
896 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
897 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
898 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
899 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
900 } else {
901 /* response types 1, 1b, 3, 4, 5, 6 */
902 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
903 }
904 }
b417577d
AH		 905 if ((host->data == NULL && !host->response_busy) || cmd->error)
906 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 907}
908
909/*
910 * DMA clean up for command errors
911 */
70a3341a 912static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 913{
b417577d
AH		 914 int dma_ch;
915
82788ff5 916 host->data->error = errno;
a45c6cb8 917
b417577d
AH		 918 spin_lock(&host->irq_lock);
919 dma_ch = host->dma_ch;
920 host->dma_ch = -1;
921 spin_unlock(&host->irq_lock);
922
923 if (host->use_dma && dma_ch != -1) {
a45c6cb8 924 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 925 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 926 omap_free_dma(dma_ch);
a45c6cb8
MC		 927 }
928 host->data = NULL;
a45c6cb8
MC		 929}
930
931/*
932 * Readable error output
933 */
934#ifdef CONFIG_MMC_DEBUG
70a3341a 935static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 936{
937 /* --- means reserved bit without definition at documentation */
70a3341a 938 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 939 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
940 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
941 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
942 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
943 };
944 char res[256];
945 char *buf = res;
946 int len, i;
947
948 len = sprintf(buf, "MMC IRQ 0x%x :", status);
949 buf += len;
950
70a3341a 951 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 952 if (status & (1 << i)) {
70a3341a 953 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 954 buf += len;
955 }
956
957 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
958}
959#endif /* CONFIG_MMC_DEBUG */
960
3ebf74b1
JP		 961/*
962 * MMC controller internal state machines reset
963 *
964 * Used to reset command or data internal state machines, using respectively
965 * SRC or SRD bit of SYSCTL register
966 * Can be called from interrupt context
967 */
70a3341a
DK		 968static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
969 unsigned long bit)
3ebf74b1
JP		 970{
971 unsigned long i = 0;
972 unsigned long limit = (loops_per_jiffy *
973 msecs_to_jiffies(MMC_TIMEOUT_MS));
974
975 OMAP_HSMMC_WRITE(host->base, SYSCTL,
976 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
977
978 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
979 (i++ < limit))
980 cpu_relax();
981
982 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
983 dev_err(mmc_dev(host->mmc),
984 "Timeout waiting on controller reset in %s\n",
985 __func__);
986}
a45c6cb8 987
b417577d 988static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 989{
a45c6cb8 990 struct mmc_data *data;
b417577d
AH		 991 int end_cmd = 0, end_trans = 0;
992
993 if (!host->req_in_progress) {
994 do {
995 OMAP_HSMMC_WRITE(host->base, STAT, status);
996 /* Flush posted write */
997 status = OMAP_HSMMC_READ(host->base, STAT);
998 } while (status & INT_EN_MASK);
999 return;
a45c6cb8
MC		 1000 }
1001
1002 data = host->data;
a45c6cb8
MC		 1003 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1004
1005 if (status & ERR) {
1006#ifdef CONFIG_MMC_DEBUG
70a3341a 1007 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1008#endif
1009 if ((status & CMD_TIMEOUT) ||
1010 (status & CMD_CRC)) {
1011 if (host->cmd) {
1012 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1013 omap_hsmmc_reset_controller_fsm(host,
1014 SRC);
a45c6cb8
MC		 1015 host->cmd->error = -ETIMEDOUT;
1016 } else {
1017 host->cmd->error = -EILSEQ;
1018 }
1019 end_cmd = 1;
1020 }
4a694dc9
AH		 1021 if (host->data || host->response_busy) {
1022 if (host->data)
70a3341a
DK		 1023 omap_hsmmc_dma_cleanup(host,
1024 -ETIMEDOUT);
4a694dc9 1025 host->response_busy = 0;
70a3341a 1026 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1027 }
a45c6cb8
MC		 1028 }
1029 if ((status & DATA_TIMEOUT) ||
1030 (status & DATA_CRC)) {
4a694dc9
AH		 1031 if (host->data || host->response_busy) {
1032 int err = (status & DATA_TIMEOUT) ?
1033 -ETIMEDOUT : -EILSEQ;
1034
1035 if (host->data)
70a3341a 1036 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1037 else
4a694dc9
AH		 1038 host->mrq->cmd->error = err;
1039 host->response_busy = 0;
70a3341a 1040 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1041 end_trans = 1;
1042 }
1043 }
1044 if (status & CARD_ERR) {
1045 dev_dbg(mmc_dev(host->mmc),
1046 "Ignoring card err CMD%d\n", host->cmd->opcode);
1047 if (host->cmd)
1048 end_cmd = 1;
1049 if (host->data)
1050 end_trans = 1;
1051 }
1052 }
1053
1054 OMAP_HSMMC_WRITE(host->base, STAT, status);
1055
a8fe29d8 1056 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1057 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1058 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1059 omap_hsmmc_xfer_done(host, data);
b417577d 1060}
a45c6cb8 1061
b417577d
AH		 1062/*
1063 * MMC controller IRQ handler
1064 */
1065static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1066{
1067 struct omap_hsmmc_host *host = dev_id;
1068 int status;
1069
1070 status = OMAP_HSMMC_READ(host->base, STAT);
1071 do {
1072 omap_hsmmc_do_irq(host, status);
1073 /* Flush posted write */
1074 status = OMAP_HSMMC_READ(host->base, STAT);
1075 } while (status & INT_EN_MASK);
4dffd7a2 1076
a45c6cb8
MC		 1077 return IRQ_HANDLED;
1078}
1079
70a3341a 1080static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1081{
1082 unsigned long i;
1083
1084 OMAP_HSMMC_WRITE(host->base, HCTL,
1085 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1086 for (i = 0; i < loops_per_jiffy; i++) {
1087 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1088 break;
1089 cpu_relax();
1090 }
1091}
1092
a45c6cb8 1093/*
eb250826
DB		 1094 * Switch MMC interface voltage ... only relevant for MMC1.
1095 *
1096 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1097 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1098 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1099 */
70a3341a 1100static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1101{
1102 u32 reg_val = 0;
1103 int ret;
1104
1105 /* Disable the clocks */
1106 clk_disable(host->fclk);
1107 clk_disable(host->iclk);
2bec0893
AH		 1108 if (host->got_dbclk)
1109 clk_disable(host->dbclk);
a45c6cb8
MC		 1110
1111 /* Turn the power off */
1112 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1113
1114 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1115 if (!ret)
1116 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1117 vdd);
1118 clk_enable(host->iclk);
1119 clk_enable(host->fclk);
1120 if (host->got_dbclk)
1121 clk_enable(host->dbclk);
1122
a45c6cb8
MC		 1123 if (ret != 0)
1124 goto err;
1125
a45c6cb8
MC		 1126 OMAP_HSMMC_WRITE(host->base, HCTL,
1127 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1128 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1129
a45c6cb8
MC		 1130 /*
1131 * If a MMC dual voltage card is detected, the set_ios fn calls
1132 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1133 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1134 *
eb250826
DB		 1135 * Cope with a bit of slop in the range ... per data sheets:
1136 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1137 * but recommended values are 1.71V to 1.89V
1138 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1139 * but recommended values are 2.7V to 3.3V
1140 *
1141 * Board setup code shouldn't permit anything very out-of-range.
1142 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1143 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1144 */
eb250826 1145 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1146 reg_val |= SDVS18;
eb250826
DB		 1147 else
1148 reg_val |= SDVS30;
a45c6cb8
MC		 1149
1150 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1151 set_sd_bus_power(host);
a45c6cb8
MC		 1152
1153 return 0;
1154err:
1155 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1156 return ret;
1157}
1158
b62f6228
AH		 1159/* Protect the card while the cover is open */
1160static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1161{
1162 if (!mmc_slot(host).get_cover_state)
1163 return;
1164
1165 host->reqs_blocked = 0;
1166 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1167 if (host->protect_card) {
1168 printk(KERN_INFO "%s: cover is closed, "
1169 "card is now accessible\n",
1170 mmc_hostname(host->mmc));
1171 host->protect_card = 0;
1172 }
1173 } else {
1174 if (!host->protect_card) {
1175 printk(KERN_INFO "%s: cover is open, "
1176 "card is now inaccessible\n",
1177 mmc_hostname(host->mmc));
1178 host->protect_card = 1;
1179 }
1180 }
1181}
1182
a45c6cb8
MC		 1183/*
1184 * Work Item to notify the core about card insertion/removal
1185 */
70a3341a 1186static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1187{
70a3341a
DK		 1188 struct omap_hsmmc_host *host =
1189 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1190 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1191 int carddetect;
1192
1193 if (host->suspended)
1194 return;
1195
1196 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1197
191d1f1d 1198 if (slot->card_detect)
db0fefc5 1199 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1200 else {
1201 omap_hsmmc_protect_card(host);
a6b2240d 1202 carddetect = -ENOSYS;
b62f6228 1203 }
a45c6cb8 1204
cdeebadd 1205 if (carddetect)
a45c6cb8 1206 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1207 else
a45c6cb8 1208 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1209}
1210
1211/*
1212 * ISR for handling card insertion and removal
1213 */
70a3341a 1214static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1215{
70a3341a 1216 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1217
a6b2240d
AH		 1218 if (host->suspended)
1219 return IRQ_HANDLED;
a45c6cb8
MC		 1220 schedule_work(&host->mmc_carddetect_work);
1221
1222 return IRQ_HANDLED;
1223}
1224
70a3341a 1225static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1226 struct mmc_data *data)
1227{
1228 int sync_dev;
1229
f3e2f1dd
GI		 1230 if (data->flags & MMC_DATA_WRITE)
1231 sync_dev = host->dma_line_tx;
1232 else
1233 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1234 return sync_dev;
1235}
1236
70a3341a 1237static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1238 struct mmc_data *data,
1239 struct scatterlist *sgl)
1240{
1241 int blksz, nblk, dma_ch;
1242
1243 dma_ch = host->dma_ch;
1244 if (data->flags & MMC_DATA_WRITE) {
1245 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1246 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1247 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1248 sg_dma_address(sgl), 0, 0);
1249 } else {
1250 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1251 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1252 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1253 sg_dma_address(sgl), 0, 0);
1254 }
1255
1256 blksz = host->data->blksz;
1257 nblk = sg_dma_len(sgl) / blksz;
1258
1259 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1260 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1261 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1262 !(data->flags & MMC_DATA_WRITE));
1263
1264 omap_start_dma(dma_ch);
1265}
1266
a45c6cb8
MC		 1267/*
1268 * DMA call back function
1269 */
b417577d 1270static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1271{
b417577d
AH		 1272 struct omap_hsmmc_host *host = cb_data;
1273 struct mmc_data *data = host->mrq->data;
1274 int dma_ch, req_in_progress;
a45c6cb8
MC		 1275
1276 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1277 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1278
b417577d
AH		 1279 spin_lock(&host->irq_lock);
1280 if (host->dma_ch < 0) {
1281 spin_unlock(&host->irq_lock);
a45c6cb8 1282 return;
b417577d 1283 }
a45c6cb8 1284
0ccd76d4
JY		 1285 host->dma_sg_idx++;
1286 if (host->dma_sg_idx < host->dma_len) {
1287 /* Fire up the next transfer. */
b417577d
AH		 1288 omap_hsmmc_config_dma_params(host, data,
1289 data->sg + host->dma_sg_idx);
1290 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1291 return;
1292 }
1293
b417577d
AH		 1294 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1295 omap_hsmmc_get_dma_dir(host, data));
1296
1297 req_in_progress = host->req_in_progress;
1298 dma_ch = host->dma_ch;
a45c6cb8 1299 host->dma_ch = -1;
b417577d
AH		 1300 spin_unlock(&host->irq_lock);
1301
1302 omap_free_dma(dma_ch);
1303
1304 /* If DMA has finished after TC, complete the request */
1305 if (!req_in_progress) {
1306 struct mmc_request *mrq = host->mrq;
1307
1308 host->mrq = NULL;
1309 mmc_request_done(host->mmc, mrq);
1310 }
a45c6cb8
MC		 1311}
1312
a45c6cb8
MC		 1313/*
1314 * Routine to configure and start DMA for the MMC card
1315 */
70a3341a
DK		 1316static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1317 struct mmc_request *req)
a45c6cb8 1318{
b417577d 1319 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1320 struct mmc_data *data = req->data;
1321
0ccd76d4 1322 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1323 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1324 struct scatterlist *sgl;
1325
1326 sgl = data->sg + i;
1327 if (sgl->length % data->blksz)
1328 return -EINVAL;
1329 }
1330 if ((data->blksz % 4) != 0)
1331 /* REVISIT: The MMC buffer increments only when MSB is written.
1332 * Return error for blksz which is non multiple of four.
1333 */
1334 return -EINVAL;
1335
b417577d 1336 BUG_ON(host->dma_ch != -1);
a45c6cb8 1337
70a3341a
DK		 1338 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1339 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1340 if (ret != 0) {
0ccd76d4 1341 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1342 "%s: omap_request_dma() failed with %d\n",
1343 mmc_hostname(host->mmc), ret);
1344 return ret;
1345 }
1346
1347 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1348 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1349 host->dma_ch = dma_ch;
0ccd76d4 1350 host->dma_sg_idx = 0;
a45c6cb8 1351
70a3341a 1352 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1353
a45c6cb8
MC		 1354 return 0;
1355}
1356
70a3341a 1357static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1358 unsigned int timeout_ns,
1359 unsigned int timeout_clks)
a45c6cb8
MC		 1360{
1361 unsigned int timeout, cycle_ns;
1362 uint32_t reg, clkd, dto = 0;
1363
1364 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1365 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1366 if (clkd == 0)
1367 clkd = 1;
1368
1369 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1370 timeout = timeout_ns / cycle_ns;
1371 timeout += timeout_clks;
a45c6cb8
MC		 1372 if (timeout) {
1373 while ((timeout & 0x80000000) == 0) {
1374 dto += 1;
1375 timeout <<= 1;
1376 }
1377 dto = 31 - dto;
1378 timeout <<= 1;
1379 if (timeout && dto)
1380 dto += 1;
1381 if (dto >= 13)
1382 dto -= 13;
1383 else
1384 dto = 0;
1385 if (dto > 14)
1386 dto = 14;
1387 }
1388
1389 reg &= ~DTO_MASK;
1390 reg |= dto << DTO_SHIFT;
1391 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1392}
1393
1394/*
1395 * Configure block length for MMC/SD cards and initiate the transfer.
1396 */
1397static int
70a3341a 1398omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1399{
1400 int ret;
1401 host->data = req->data;
1402
1403 if (req->data == NULL) {
a45c6cb8 1404 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1405 /*
1406 * Set an arbitrary 100ms data timeout for commands with
1407 * busy signal.
1408 */
1409 if (req->cmd->flags & MMC_RSP_BUSY)
1410 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1411 return 0;
1412 }
1413
1414 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1415 | (req->data->blocks << 16));
e2bf08d6 1416 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1417
a45c6cb8 1418 if (host->use_dma) {
70a3341a 1419 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1420 if (ret != 0) {
1421 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1422 return ret;
1423 }
1424 }
1425 return 0;
1426}
1427
1428/*
1429 * Request function. for read/write operation
1430 */
70a3341a 1431static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1432{
70a3341a 1433 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1434 int err;
a45c6cb8 1435
b417577d
AH		 1436 BUG_ON(host->req_in_progress);
1437 BUG_ON(host->dma_ch != -1);
1438 if (host->protect_card) {
1439 if (host->reqs_blocked < 3) {
1440 /*
1441 * Ensure the controller is left in a consistent
1442 * state by resetting the command and data state
1443 * machines.
1444 */
1445 omap_hsmmc_reset_controller_fsm(host, SRD);
1446 omap_hsmmc_reset_controller_fsm(host, SRC);
1447 host->reqs_blocked += 1;
1448 }
1449 req->cmd->error = -EBADF;
1450 if (req->data)
1451 req->data->error = -EBADF;
1452 req->cmd->retries = 0;
1453 mmc_request_done(mmc, req);
1454 return;
1455 } else if (host->reqs_blocked)
1456 host->reqs_blocked = 0;
a45c6cb8
MC		 1457 WARN_ON(host->mrq != NULL);
1458 host->mrq = req;
70a3341a 1459 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1460 if (err) {
1461 req->cmd->error = err;
1462 if (req->data)
1463 req->data->error = err;
1464 host->mrq = NULL;
1465 mmc_request_done(mmc, req);
1466 return;
1467 }
1468
70a3341a 1469 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1470}
1471
a45c6cb8 1472/* Routine to configure clock values. Exposed API to core */
70a3341a 1473static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1474{
70a3341a 1475 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1476 u16 dsor = 0;
1477 unsigned long regval;
1478 unsigned long timeout;
73153010 1479 u32 con;
a3621465 1480 int do_send_init_stream = 0;
a45c6cb8 1481
5e2ea617
AH		 1482 mmc_host_enable(host->mmc);
1483
a3621465
AH		 1484 if (ios->power_mode != host->power_mode) {
1485 switch (ios->power_mode) {
1486 case MMC_POWER_OFF:
1487 mmc_slot(host).set_power(host->dev, host->slot_id,
1488 0, 0);
623821f7 1489 host->vdd = 0;
a3621465
AH		 1490 break;
1491 case MMC_POWER_UP:
1492 mmc_slot(host).set_power(host->dev, host->slot_id,
1493 1, ios->vdd);
623821f7 1494 host->vdd = ios->vdd;
a3621465
AH		 1495 break;
1496 case MMC_POWER_ON:
1497 do_send_init_stream = 1;
1498 break;
1499 }
1500 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1501 }
1502
dd498eff
DK		 1503 /* FIXME: set registers based only on changes to ios */
1504
73153010 1505 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1506 switch (mmc->ios.bus_width) {
73153010
JL		 1507 case MMC_BUS_WIDTH_8:
1508 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1509 break;
a45c6cb8 1510 case MMC_BUS_WIDTH_4:
73153010 1511 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1512 OMAP_HSMMC_WRITE(host->base, HCTL,
1513 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1514 break;
1515 case MMC_BUS_WIDTH_1:
73153010 1516 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1517 OMAP_HSMMC_WRITE(host->base, HCTL,
1518 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1519 break;
1520 }
1521
1522 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1523 /* Only MMC1 can interface at 3V without some flavor
1524 * of external transceiver; but they all handle 1.8V.
1525 */
a45c6cb8
MC		 1526 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1527 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1528 /*
1529 * The mmc_select_voltage fn of the core does
1530 * not seem to set the power_mode to
1531 * MMC_POWER_UP upon recalculating the voltage.
1532 * vdd 1.8v.
1533 */
70a3341a
DK		 1534 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1535 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1536 "Switch operation failed\n");
1537 }
1538 }
1539
1540 if (ios->clock) {
1541 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1542 if (dsor < 1)
1543 dsor = 1;
1544
1545 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1546 dsor++;
1547
1548 if (dsor > 250)
1549 dsor = 250;
1550 }
70a3341a 1551 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1552 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1553 regval = regval & ~(CLKD_MASK);
1554 regval = regval | (dsor << 6) | (DTO << 16);
1555 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1556 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1557 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1558
1559 /* Wait till the ICS bit is set */
1560 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1561 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1562 && time_before(jiffies, timeout))
1563 msleep(1);
1564
1565 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1566 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1567
a3621465 1568 if (do_send_init_stream)
a45c6cb8
MC		 1569 send_init_stream(host);
1570
abb28e73 1571 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1572 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1573 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1574 else
1575 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1576
dd498eff
DK		 1577 if (host->power_mode == MMC_POWER_OFF)
1578 mmc_host_disable(host->mmc);
1579 else
1580 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1581}
1582
1583static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1584{
70a3341a 1585 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1586
191d1f1d 1587 if (!mmc_slot(host).card_detect)
a45c6cb8 1588 return -ENOSYS;
db0fefc5 1589 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1590}
1591
1592static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1593{
70a3341a 1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1595
191d1f1d 1596 if (!mmc_slot(host).get_ro)
a45c6cb8 1597 return -ENOSYS;
191d1f1d 1598 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1599}
1600
4816858c
GI		 1601static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1602{
1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
1604
1605 if (mmc_slot(host).init_card)
1606 mmc_slot(host).init_card(card);
1607}
1608
70a3341a 1609static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1610{
1611 u32 hctl, capa, value;
1612
1613 /* Only MMC1 supports 3.0V */
1614 if (host->id == OMAP_MMC1_DEVID) {
1615 hctl = SDVS30;
1616 capa = VS30 | VS18;
1617 } else {
1618 hctl = SDVS18;
1619 capa = VS18;
1620 }
1621
1622 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1623 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1624
1625 value = OMAP_HSMMC_READ(host->base, CAPA);
1626 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1627
1628 /* Set the controller to AUTO IDLE mode */
1629 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1630 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1631
1632 /* Set SD bus power bit */
e13bb300 1633 set_sd_bus_power(host);
1b331e69
KK		 1634}
1635
dd498eff
DK		 1636/*
1637 * Dynamic power saving handling, FSM:
13189e78
JL		 1638 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1639 * ^___________| | |
1640 * |______________________|______________________|
dd498eff
DK		 1641 *
1642 * ENABLED: mmc host is fully functional
1643 * DISABLED: fclk is off
13189e78
JL		 1644 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1645 * REGSLEEP: fclk is off, voltage regulator is asleep
1646 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1647 *
1648 * Transition handlers return the timeout for the next state transition
1649 * or negative error.
1650 */
1651
13189e78 1652enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1653
1654/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1655static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1656{
70a3341a 1657 omap_hsmmc_context_save(host);
dd498eff
DK		 1658 clk_disable(host->fclk);
1659 host->dpm_state = DISABLED;
1660
1661 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1662
1663 if (host->power_mode == MMC_POWER_OFF)
1664 return 0;
1665
4380eea2 1666 return OMAP_MMC_SLEEP_TIMEOUT;
dd498eff
DK		 1667}
1668
13189e78 1669/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1670static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1671{
13189e78 1672 int err, new_state;
dd498eff
DK		 1673
1674 if (!mmc_try_claim_host(host->mmc))
1675 return 0;
1676
1677 clk_enable(host->fclk);
70a3341a 1678 omap_hsmmc_context_restore(host);
13189e78
JL		 1679 if (mmc_card_can_sleep(host->mmc)) {
1680 err = mmc_card_sleep(host->mmc);
1681 if (err < 0) {
1682 clk_disable(host->fclk);
1683 mmc_release_host(host->mmc);
1684 return err;
1685 }
1686 new_state = CARDSLEEP;
70a3341a 1687 } else {
13189e78 1688 new_state = REGSLEEP;
70a3341a 1689 }
13189e78
JL		 1690 if (mmc_slot(host).set_sleep)
1691 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1692 new_state == CARDSLEEP);
1693 /* FIXME: turn off bus power and perhaps interrupts too */
1694 clk_disable(host->fclk);
1695 host->dpm_state = new_state;
1696
1697 mmc_release_host(host->mmc);
1698
1699 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1700 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1701
1df58db8
AH		 1702 if (mmc_slot(host).no_off)
1703 return 0;
1704
dd498eff
DK		 1705 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1706 mmc_slot(host).card_detect ||
1707 (mmc_slot(host).get_cover_state &&
13189e78 1708 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
4380eea2 1709 return OMAP_MMC_OFF_TIMEOUT;
13189e78
JL		 1710
1711 return 0;
1712}
1713
1714/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1715static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1716{
1717 if (!mmc_try_claim_host(host->mmc))
1718 return 0;
1719
1df58db8
AH		 1720 if (mmc_slot(host).no_off)
1721 return 0;
1722
13189e78
JL		 1723 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1724 mmc_slot(host).card_detect ||
1725 (mmc_slot(host).get_cover_state &&
1726 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1727 mmc_release_host(host->mmc);
1728 return 0;
623821f7 1729 }
dd498eff 1730
13189e78
JL		 1731 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1732 host->vdd = 0;
1733 host->power_mode = MMC_POWER_OFF;
dd498eff 1734
13189e78
JL		 1735 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1736 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1737
13189e78 1738 host->dpm_state = OFF;
dd498eff
DK		 1739
1740 mmc_release_host(host->mmc);
1741
1742 return 0;
1743}
1744
1745/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1746static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1747{
1748 int err;
1749
1750 err = clk_enable(host->fclk);
1751 if (err < 0)
1752 return err;
1753
70a3341a 1754 omap_hsmmc_context_restore(host);
dd498eff
DK		 1755 host->dpm_state = ENABLED;
1756
1757 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1758
1759 return 0;
1760}
1761
13189e78 1762/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1763static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1764{
13189e78
JL		 1765 if (!mmc_try_claim_host(host->mmc))
1766 return 0;
dd498eff 1767
13189e78 1768 clk_enable(host->fclk);
70a3341a 1769 omap_hsmmc_context_restore(host);
13189e78
JL		 1770 if (mmc_slot(host).set_sleep)
1771 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1772 host->vdd, host->dpm_state == CARDSLEEP);
1773 if (mmc_card_can_sleep(host->mmc))
1774 mmc_card_awake(host->mmc);
1775
1776 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1777 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1778
1779 host->dpm_state = ENABLED;
1780
13189e78 1781 mmc_release_host(host->mmc);
dd498eff
DK		 1782
1783 return 0;
1784}
1785
13189e78 1786/* Handler for [OFF -> ENABLED] transition */
70a3341a 1787static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1788{
623821f7 1789 clk_enable(host->fclk);
623821f7 1790
70a3341a
DK		 1791 omap_hsmmc_context_restore(host);
1792 omap_hsmmc_conf_bus_power(host);
13189e78 1793 mmc_power_restore_host(host->mmc);
623821f7
AH		 1794
1795 host->dpm_state = ENABLED;
1796
13189e78
JL		 1797 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1798
623821f7
AH		 1799 return 0;
1800}
1801
dd498eff
DK		 1802/*
1803 * Bring MMC host to ENABLED from any other PM state.
1804 */
70a3341a 1805static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1806{
70a3341a 1807 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1808
1809 switch (host->dpm_state) {
1810 case DISABLED:
70a3341a 1811 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1812 case CARDSLEEP:
623821f7 1813 case REGSLEEP:
70a3341a 1814 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1815 case OFF:
70a3341a 1816 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1817 default:
1818 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1819 return -EINVAL;
1820 }
1821}
1822
1823/*
1824 * Bring MMC host in PM state (one level deeper).
1825 */
70a3341a 1826static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1827{
70a3341a 1828 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1829
1830 switch (host->dpm_state) {
1831 case ENABLED: {
1832 int delay;
1833
70a3341a 1834 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1835 if (lazy || delay < 0)
1836 return delay;
1837 return 0;
1838 }
1839 case DISABLED:
70a3341a 1840 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1841 case CARDSLEEP:
1842 case REGSLEEP:
70a3341a 1843 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1844 default:
1845 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1846 return -EINVAL;
1847 }
1848}
1849
70a3341a 1850static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1851{
70a3341a 1852 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1853 int err;
1854
1855 err = clk_enable(host->fclk);
1856 if (err)
1857 return err;
1858 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1859 omap_hsmmc_context_restore(host);
dd498eff
DK		 1860 return 0;
1861}
1862
70a3341a 1863static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1864{
70a3341a 1865 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1866
70a3341a 1867 omap_hsmmc_context_save(host);
dd498eff
DK		 1868 clk_disable(host->fclk);
1869 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1870 return 0;
1871}
1872
70a3341a
DK		 1873static const struct mmc_host_ops omap_hsmmc_ops = {
1874 .enable = omap_hsmmc_enable_fclk,
1875 .disable = omap_hsmmc_disable_fclk,
1876 .request = omap_hsmmc_request,
1877 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1878 .get_cd = omap_hsmmc_get_cd,
1879 .get_ro = omap_hsmmc_get_ro,
4816858c 1880 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1881 /* NYET -- enable_sdio_irq */
1882};
1883
70a3341a
DK		 1884static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1885 .enable = omap_hsmmc_enable,
1886 .disable = omap_hsmmc_disable,
1887 .request = omap_hsmmc_request,
1888 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1889 .get_cd = omap_hsmmc_get_cd,
1890 .get_ro = omap_hsmmc_get_ro,
4816858c 1891 .init_card = omap_hsmmc_init_card,
a45c6cb8
MC		 1892 /* NYET -- enable_sdio_irq */
1893};
1894
d900f712
DK		 1895#ifdef CONFIG_DEBUG_FS
1896
70a3341a 1897static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1898{
1899 struct mmc_host *mmc = s->private;
70a3341a 1900 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1901 int context_loss = 0;
1902
70a3341a
DK		 1903 if (host->pdata->get_context_loss_count)
1904 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1905
5e2ea617
AH		 1906 seq_printf(s, "mmc%d:\n"
1907 " enabled:\t%d\n"
dd498eff 1908 " dpm_state:\t%d\n"
5e2ea617 1909 " nesting_cnt:\t%d\n"
11dd62a7 1910 " ctx_loss:\t%d:%d\n"
5e2ea617 1911 "\nregs:\n",
dd498eff
DK		 1912 mmc->index, mmc->enabled ? 1 : 0,
1913 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1914 host->context_loss, context_loss);
5e2ea617 1915
13189e78 1916 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1917 seq_printf(s, "host suspended, can't read registers\n");
1918 return 0;
1919 }
1920
5e2ea617
AH		 1921 if (clk_enable(host->fclk) != 0) {
1922 seq_printf(s, "can't read the regs\n");
dd498eff 1923 return 0;
5e2ea617 1924 }
d900f712
DK		 1925
1926 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1927 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1928 seq_printf(s, "CON:\t\t0x%08x\n",
1929 OMAP_HSMMC_READ(host->base, CON));
1930 seq_printf(s, "HCTL:\t\t0x%08x\n",
1931 OMAP_HSMMC_READ(host->base, HCTL));
1932 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1933 OMAP_HSMMC_READ(host->base, SYSCTL));
1934 seq_printf(s, "IE:\t\t0x%08x\n",
1935 OMAP_HSMMC_READ(host->base, IE));
1936 seq_printf(s, "ISE:\t\t0x%08x\n",
1937 OMAP_HSMMC_READ(host->base, ISE));
1938 seq_printf(s, "CAPA:\t\t0x%08x\n",
1939 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1940
1941 clk_disable(host->fclk);
dd498eff 1942
d900f712
DK		 1943 return 0;
1944}
1945
70a3341a 1946static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1947{
70a3341a 1948 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1949}
1950
1951static const struct file_operations mmc_regs_fops = {
70a3341a 1952 .open = omap_hsmmc_regs_open,
d900f712
DK		 1953 .read = seq_read,
1954 .llseek = seq_lseek,
1955 .release = single_release,
1956};
1957
70a3341a 1958static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1959{
1960 if (mmc->debugfs_root)
1961 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1962 mmc, &mmc_regs_fops);
1963}
1964
1965#else
1966
70a3341a 1967static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1968{
1969}
1970
1971#endif
1972
70a3341a 1973static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1974{
1975 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1976 struct mmc_host *mmc;
70a3341a 1977 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1978 struct resource *res;
db0fefc5 1979 int ret, irq;
a45c6cb8
MC		 1980
1981 if (pdata == NULL) {
1982 dev_err(&pdev->dev, "Platform Data is missing\n");
1983 return -ENXIO;
1984 }
1985
1986 if (pdata->nr_slots == 0) {
1987 dev_err(&pdev->dev, "No Slots\n");
1988 return -ENXIO;
1989 }
1990
1991 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1992 irq = platform_get_irq(pdev, 0);
1993 if (res == NULL || irq < 0)
1994 return -ENXIO;
1995
1996 res = request_mem_region(res->start, res->end - res->start + 1,
1997 pdev->name);
1998 if (res == NULL)
1999 return -EBUSY;
2000
db0fefc5
AH		 2001 ret = omap_hsmmc_gpio_init(pdata);
2002 if (ret)
2003 goto err;
2004
70a3341a 2005 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2006 if (!mmc) {
2007 ret = -ENOMEM;
db0fefc5 2008 goto err_alloc;
a45c6cb8
MC		 2009 }
2010
2011 host = mmc_priv(mmc);
2012 host->mmc = mmc;
2013 host->pdata = pdata;
2014 host->dev = &pdev->dev;
2015 host->use_dma = 1;
2016 host->dev->dma_mask = &pdata->dma_mask;
2017 host->dma_ch = -1;
2018 host->irq = irq;
2019 host->id = pdev->id;
2020 host->slot_id = 0;
2021 host->mapbase = res->start;
2022 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 2023 host->power_mode = MMC_POWER_OFF;
a45c6cb8
MC		 2024
2025 platform_set_drvdata(pdev, host);
70a3341a 2026 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 2027
191d1f1d 2028 if (mmc_slot(host).power_saving)
70a3341a 2029 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 2030 else
70a3341a 2031 mmc->ops = &omap_hsmmc_ops;
dd498eff 2032
e0eb2424
AH		 2033 /*
2034 * If regulator_disable can only put vcc_aux to sleep then there is
2035 * no off state.
2036 */
2037 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2038 mmc_slot(host).no_off = 1;
2039
a45c6cb8
MC		 2040 mmc->f_min = 400000;
2041 mmc->f_max = 52000000;
2042
4dffd7a2 2043 spin_lock_init(&host->irq_lock);
a45c6cb8 2044
6f7607cc 2045 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 2046 if (IS_ERR(host->iclk)) {
2047 ret = PTR_ERR(host->iclk);
2048 host->iclk = NULL;
2049 goto err1;
2050 }
6f7607cc 2051 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2052 if (IS_ERR(host->fclk)) {
2053 ret = PTR_ERR(host->fclk);
2054 host->fclk = NULL;
2055 clk_put(host->iclk);
2056 goto err1;
2057 }
2058
70a3341a 2059 omap_hsmmc_context_save(host);
11dd62a7 2060
5e2ea617 2061 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2062 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2063 /* we start off in DISABLED state */
2064 host->dpm_state = DISABLED;
2065
5e2ea617 2066 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 2067 clk_put(host->iclk);
2068 clk_put(host->fclk);
2069 goto err1;
2070 }
2071
2072 if (clk_enable(host->iclk) != 0) {
5e2ea617 2073 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2074 clk_put(host->iclk);
2075 clk_put(host->fclk);
2076 goto err1;
2077 }
2078
2bec0893
AH		 2079 if (cpu_is_omap2430()) {
2080 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2081 /*
2082 * MMC can still work without debounce clock.
2083 */
2084 if (IS_ERR(host->dbclk))
2085 dev_warn(mmc_dev(host->mmc),
2086 "Failed to get debounce clock\n");
a45c6cb8 2087 else
2bec0893
AH		 2088 host->got_dbclk = 1;
2089
2090 if (host->got_dbclk)
2091 if (clk_enable(host->dbclk) != 0)
2092 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2093 " clk failed\n");
2094 }
a45c6cb8 2095
0ccd76d4
JY		 2096 /* Since we do only SG emulation, we can have as many segs
2097 * as we want. */
2098 mmc->max_phys_segs = 1024;
2099 mmc->max_hw_segs = 1024;
2100
a45c6cb8
MC		 2101 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2102 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2103 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2104 mmc->max_seg_size = mmc->max_req_size;
2105
13189e78
JL		 2106 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2107 MMC_CAP_WAIT_WHILE_BUSY;
a45c6cb8 2108
27151dc9
KK		 2109 switch (mmc_slot(host).wires) {
2110 case 8:
73153010 2111 mmc->caps |= MMC_CAP_8_BIT_DATA;
27151dc9
KK		 2112 /* Fall through */
2113 case 4:
a45c6cb8 2114 mmc->caps |= MMC_CAP_4_BIT_DATA;
27151dc9
KK		 2115 break;
2116 case 1:
2117 /* Nothing to crib here */
2118 case 0:
2119 /* Assuming nothing was given by board, Core use's 1-Bit */
2120 break;
2121 default:
2122 /* Completely unexpected.. Core goes with 1-Bit Width */
2123 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!"
2124 "using 1 instead\n", mmc_slot(host).wires);
2125 }
a45c6cb8 2126
191d1f1d 2127 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2128 mmc->caps |= MMC_CAP_NONREMOVABLE;
2129
70a3341a 2130 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2131
f3e2f1dd
GI		 2132 /* Select DMA lines */
2133 switch (host->id) {
2134 case OMAP_MMC1_DEVID:
2135 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2136 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2137 break;
2138 case OMAP_MMC2_DEVID:
2139 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2140 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2141 break;
2142 case OMAP_MMC3_DEVID:
2143 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2144 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2145 break;
82cf818d 2146 case OMAP_MMC4_DEVID:
2147 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2148 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2149 break;
2150 case OMAP_MMC5_DEVID:
2151 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2152 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2153 break;
f3e2f1dd
GI		 2154 default:
2155 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2156 goto err_irq;
2157 }
a45c6cb8
MC		 2158
2159 /* Request IRQ for MMC operations */
70a3341a 2160 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2161 mmc_hostname(mmc), host);
2162 if (ret) {
2163 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2164 goto err_irq;
2165 }
2166
2167 if (pdata->init != NULL) {
2168 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2169 dev_dbg(mmc_dev(host->mmc),
2170 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2171 goto err_irq_cd_init;
2172 }
2173 }
db0fefc5 2174
b702b106 2175 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2176 ret = omap_hsmmc_reg_get(host);
2177 if (ret)
2178 goto err_reg;
2179 host->use_reg = 1;
2180 }
2181
b583f26d 2182 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2183
2184 /* Request IRQ for card detect */
e1a55f5e 2185 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2186 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2187 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2188 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2189 | IRQF_DISABLED,
2190 mmc_hostname(mmc), host);
2191 if (ret) {
2192 dev_dbg(mmc_dev(host->mmc),
2193 "Unable to grab MMC CD IRQ\n");
2194 goto err_irq_cd;
2195 }
2196 }
2197
b417577d 2198 omap_hsmmc_disable_irq(host);
a45c6cb8 2199
5e2ea617
AH		 2200 mmc_host_lazy_disable(host->mmc);
2201
b62f6228
AH		 2202 omap_hsmmc_protect_card(host);
2203
a45c6cb8
MC		 2204 mmc_add_host(mmc);
2205
191d1f1d 2206 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2207 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2208 if (ret < 0)
2209 goto err_slot_name;
2210 }
191d1f1d 2211 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2212 ret = device_create_file(&mmc->class_dev,
2213 &dev_attr_cover_switch);
2214 if (ret < 0)
db0fefc5 2215 goto err_slot_name;
a45c6cb8
MC		 2216 }
2217
70a3341a 2218 omap_hsmmc_debugfs(mmc);
d900f712 2219
a45c6cb8
MC		 2220 return 0;
2221
a45c6cb8
MC		 2222err_slot_name:
2223 mmc_remove_host(mmc);
a45c6cb8 2224 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2225err_irq_cd:
2226 if (host->use_reg)
2227 omap_hsmmc_reg_put(host);
2228err_reg:
2229 if (host->pdata->cleanup)
2230 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2231err_irq_cd_init:
2232 free_irq(host->irq, host);
2233err_irq:
5e2ea617 2234 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2235 clk_disable(host->iclk);
2236 clk_put(host->fclk);
2237 clk_put(host->iclk);
2bec0893 2238 if (host->got_dbclk) {
a45c6cb8
MC		 2239 clk_disable(host->dbclk);
2240 clk_put(host->dbclk);
2241 }
a45c6cb8
MC		 2242err1:
2243 iounmap(host->base);
db0fefc5
AH		 2244 platform_set_drvdata(pdev, NULL);
2245 mmc_free_host(mmc);
2246err_alloc:
2247 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2248err:
a45c6cb8 2249 release_mem_region(res->start, res->end - res->start + 1);
a45c6cb8
MC		 2250 return ret;
2251}
2252
70a3341a 2253static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2254{
70a3341a 2255 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2256 struct resource *res;
2257
2258 if (host) {
5e2ea617 2259 mmc_host_enable(host->mmc);
a45c6cb8 2260 mmc_remove_host(host->mmc);
db0fefc5
AH		 2261 if (host->use_reg)
2262 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2263 if (host->pdata->cleanup)
2264 host->pdata->cleanup(&pdev->dev);
2265 free_irq(host->irq, host);
2266 if (mmc_slot(host).card_detect_irq)
2267 free_irq(mmc_slot(host).card_detect_irq, host);
2268 flush_scheduled_work();
2269
5e2ea617 2270 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2271 clk_disable(host->iclk);
2272 clk_put(host->fclk);
2273 clk_put(host->iclk);
2bec0893 2274 if (host->got_dbclk) {
a45c6cb8
MC		 2275 clk_disable(host->dbclk);
2276 clk_put(host->dbclk);
2277 }
2278
2279 mmc_free_host(host->mmc);
2280 iounmap(host->base);
db0fefc5 2281 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2282 }
2283
2284 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2285 if (res)
2286 release_mem_region(res->start, res->end - res->start + 1);
2287 platform_set_drvdata(pdev, NULL);
2288
2289 return 0;
2290}
2291
2292#ifdef CONFIG_PM
a791daa1 2293static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2294{
2295 int ret = 0;
a791daa1 2296 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2297 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a791daa1 2298 pm_message_t state = PMSG_SUSPEND; /* unused by MMC core */
a45c6cb8
MC		 2299
2300 if (host && host->suspended)
2301 return 0;
2302
2303 if (host) {
a6b2240d
AH		 2304 host->suspended = 1;
2305 if (host->pdata->suspend) {
2306 ret = host->pdata->suspend(&pdev->dev,
2307 host->slot_id);
2308 if (ret) {
2309 dev_dbg(mmc_dev(host->mmc),
2310 "Unable to handle MMC board"
2311 " level suspend\n");
2312 host->suspended = 0;
2313 return ret;
2314 }
2315 }
2316 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 2317 mmc_host_enable(host->mmc);
1a13f8fa 2318 ret = mmc_suspend_host(host->mmc);
a45c6cb8 2319 if (ret == 0) {
b417577d 2320 omap_hsmmc_disable_irq(host);
0683af48 2321 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2322 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2323 mmc_host_disable(host->mmc);
a45c6cb8 2324 clk_disable(host->iclk);
2bec0893
AH		 2325 if (host->got_dbclk)
2326 clk_disable(host->dbclk);
a6b2240d
AH		 2327 } else {
2328 host->suspended = 0;
2329 if (host->pdata->resume) {
2330 ret = host->pdata->resume(&pdev->dev,
2331 host->slot_id);
2332 if (ret)
2333 dev_dbg(mmc_dev(host->mmc),
2334 "Unmask interrupt failed\n");
2335 }
5e2ea617 2336 mmc_host_disable(host->mmc);
a6b2240d 2337 }
a45c6cb8
MC		 2338
2339 }
2340 return ret;
2341}
2342
2343/* Routine to resume the MMC device */
a791daa1 2344static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2345{
2346 int ret = 0;
a791daa1 2347 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2348 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2349
2350 if (host && !host->suspended)
2351 return 0;
2352
2353 if (host) {
a45c6cb8 2354 ret = clk_enable(host->iclk);
11dd62a7 2355 if (ret)
a45c6cb8 2356 goto clk_en_err;
a45c6cb8 2357
11dd62a7
DK		 2358 if (mmc_host_enable(host->mmc) != 0) {
2359 clk_disable(host->iclk);
2360 goto clk_en_err;
2361 }
2362
2bec0893
AH		 2363 if (host->got_dbclk)
2364 clk_enable(host->dbclk);
2365
70a3341a 2366 omap_hsmmc_conf_bus_power(host);
1b331e69 2367
a45c6cb8
MC		 2368 if (host->pdata->resume) {
2369 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2370 if (ret)
2371 dev_dbg(mmc_dev(host->mmc),
2372 "Unmask interrupt failed\n");
2373 }
2374
b62f6228
AH		 2375 omap_hsmmc_protect_card(host);
2376
a45c6cb8
MC		 2377 /* Notify the core to resume the host */
2378 ret = mmc_resume_host(host->mmc);
2379 if (ret == 0)
2380 host->suspended = 0;
70a3341a 2381
5e2ea617 2382 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2383 }
2384
2385 return ret;
2386
2387clk_en_err:
2388 dev_dbg(mmc_dev(host->mmc),
2389 "Failed to enable MMC clocks during resume\n");
2390 return ret;
2391}
2392
2393#else
70a3341a
DK		 2394#define omap_hsmmc_suspend NULL
2395#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2396#endif
2397
a791daa1 2398static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2399 .suspend = omap_hsmmc_suspend,
2400 .resume = omap_hsmmc_resume,
a791daa1
KH		 2401};
2402
2403static struct platform_driver omap_hsmmc_driver = {
2404 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2405 .driver = {
2406 .name = DRIVER_NAME,
2407 .owner = THIS_MODULE,
a791daa1 2408 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2409 },
2410};
2411
70a3341a 2412static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2413{
2414 /* Register the MMC driver */
8753298a 2415 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2416}
2417
70a3341a 2418static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2419{
2420 /* Unregister MMC driver */
70a3341a 2421 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2422}
2423
70a3341a
DK		 2424module_init(omap_hsmmc_init);
2425module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2426
2427MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2428MODULE_LICENSE("GPL");
2429MODULE_ALIAS("platform:" DRIVER_NAME);
2430MODULE_AUTHOR("Texas Instruments Inc");
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